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--Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014 --Date : Sun Mar 01 22:41:07 2015 --Host : dodo-PC running 64-bit Service Pack 1 (build 7601) --Command : generate_target ARM.bd --Design : ARM --Purpose : IP block netlist ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity s00_couplers_imp_K5P28A is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 ); M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arready : in STD_LOGIC; M_AXI_arvalid : out STD_LOGIC; M_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 ); M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awready : in STD_LOGIC; M_AXI_awvalid : out STD_LOGIC; M_AXI_bready : out STD_LOGIC; M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bvalid : in STD_LOGIC; M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_rready : out STD_LOGIC; M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rvalid : in STD_LOGIC; M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_wready : in STD_LOGIC; M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_wvalid : out STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arready : out STD_LOGIC; S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arvalid : in STD_LOGIC; S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awready : out STD_LOGIC; S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awvalid : in STD_LOGIC; S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_bready : in STD_LOGIC; S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bvalid : out STD_LOGIC; S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_rlast : out STD_LOGIC; S_AXI_rready : in STD_LOGIC; S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rvalid : out STD_LOGIC; S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_wlast : in STD_LOGIC; S_AXI_wready : out STD_LOGIC; S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_wvalid : in STD_LOGIC ); end s00_couplers_imp_K5P28A; architecture STRUCTURE of s00_couplers_imp_K5P28A is component ARM_auto_pc_0 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end component ARM_auto_pc_0; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC; signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC; signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC; begin M_AXI_araddr(12 downto 0) <= auto_pc_to_s00_couplers_ARADDR(12 downto 0); M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0); M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID; M_AXI_awaddr(12 downto 0) <= auto_pc_to_s00_couplers_AWADDR(12 downto 0); M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0); M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID; M_AXI_bready <= auto_pc_to_s00_couplers_BREADY; M_AXI_rready <= auto_pc_to_s00_couplers_RREADY; M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0); M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0); M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID; S_ACLK_1 <= S_ACLK; S_ARESETN_1(0) <= S_ARESETN(0); S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY; S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY; S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0); S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0); S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID; S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0); S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0); S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST; S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0); S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID; S_AXI_wready <= s00_couplers_to_auto_pc_WREADY; auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready; auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready; auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid; auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid; auto_pc_to_s00_couplers_WREADY <= M_AXI_wready; s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0); s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0); s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0); s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0); s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid; s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0); s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0); s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0); s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0); s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid; s00_couplers_to_auto_pc_BREADY <= S_AXI_bready; s00_couplers_to_auto_pc_RREADY <= S_AXI_rready; s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0); s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast; s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid; auto_pc: component ARM_auto_pc_0 port map ( aclk => S_ACLK_1, aresetn => S_ARESETN_1(0), m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0), m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0), m_axi_arready => auto_pc_to_s00_couplers_ARREADY, m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID, m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0), m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0), m_axi_awready => auto_pc_to_s00_couplers_AWREADY, m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID, m_axi_bready => auto_pc_to_s00_couplers_BREADY, m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0), m_axi_bvalid => auto_pc_to_s00_couplers_BVALID, m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0), m_axi_rready => auto_pc_to_s00_couplers_RREADY, m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0), m_axi_rvalid => auto_pc_to_s00_couplers_RVALID, m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0), m_axi_wready => auto_pc_to_s00_couplers_WREADY, m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0), m_axi_wvalid => auto_pc_to_s00_couplers_WVALID, s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0), s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0), s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0), s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0), s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0), s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0), s_axi_arready => s00_couplers_to_auto_pc_ARREADY, s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0), s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID, s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0), s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0), s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0), s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0), s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0), s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0), s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0), s_axi_awready => s00_couplers_to_auto_pc_AWREADY, s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0), s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID, s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0), s_axi_bready => s00_couplers_to_auto_pc_BREADY, s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0), s_axi_bvalid => s00_couplers_to_auto_pc_BVALID, s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0), s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0), s_axi_rlast => s00_couplers_to_auto_pc_RLAST, s_axi_rready => s00_couplers_to_auto_pc_RREADY, s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0), s_axi_rvalid => s00_couplers_to_auto_pc_RVALID, s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0), s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0), s_axi_wlast => s00_couplers_to_auto_pc_WLAST, s_axi_wready => s00_couplers_to_auto_pc_WREADY, s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0), s_axi_wvalid => s00_couplers_to_auto_pc_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ARM_axi_mem_intercon_0 is port ( ACLK : in STD_LOGIC; ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M00_ACLK : in STD_LOGIC; M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M00_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 ); M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M00_AXI_arready : in STD_LOGIC; M00_AXI_arvalid : out STD_LOGIC; M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 ); M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M00_AXI_awready : in STD_LOGIC; M00_AXI_awvalid : out STD_LOGIC; M00_AXI_bready : out STD_LOGIC; M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_bvalid : in STD_LOGIC; M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_rready : out STD_LOGIC; M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_rvalid : in STD_LOGIC; M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_wready : in STD_LOGIC; M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_wvalid : out STD_LOGIC; S00_ACLK : in STD_LOGIC; S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arready : out STD_LOGIC; S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arvalid : in STD_LOGIC; S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awready : out STD_LOGIC; S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_awvalid : in STD_LOGIC; S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_bready : in STD_LOGIC; S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_bvalid : out STD_LOGIC; S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_rlast : out STD_LOGIC; S00_AXI_rready : in STD_LOGIC; S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_rvalid : out STD_LOGIC; S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_wlast : in STD_LOGIC; S00_AXI_wready : out STD_LOGIC; S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_wvalid : in STD_LOGIC ); end ARM_axi_mem_intercon_0; architecture STRUCTURE of ARM_axi_mem_intercon_0 is signal S00_ACLK_1 : STD_LOGIC; signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal axi_mem_intercon_ACLK_net : STD_LOGIC; signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 ); signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal axi_mem_intercon_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s00_couplers_AWREADY : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s00_couplers_AWVALID : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal axi_mem_intercon_to_s00_couplers_BREADY : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s00_couplers_BVALID : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal axi_mem_intercon_to_s00_couplers_WLAST : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_WREADY : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s00_couplers_WVALID : STD_LOGIC; signal s00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 ); signal s00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC; signal s00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC; signal s00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 ); signal s00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC; signal s00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC; signal s00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC; signal s00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC; signal s00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC; signal s00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC; signal s00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC; signal s00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC; begin M00_AXI_araddr(12 downto 0) <= s00_couplers_to_axi_mem_intercon_ARADDR(12 downto 0); M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0); M00_AXI_arvalid <= s00_couplers_to_axi_mem_intercon_ARVALID; M00_AXI_awaddr(12 downto 0) <= s00_couplers_to_axi_mem_intercon_AWADDR(12 downto 0); M00_AXI_awprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0); M00_AXI_awvalid <= s00_couplers_to_axi_mem_intercon_AWVALID; M00_AXI_bready <= s00_couplers_to_axi_mem_intercon_BREADY; M00_AXI_rready <= s00_couplers_to_axi_mem_intercon_RREADY; M00_AXI_wdata(31 downto 0) <= s00_couplers_to_axi_mem_intercon_WDATA(31 downto 0); M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0); M00_AXI_wvalid <= s00_couplers_to_axi_mem_intercon_WVALID; S00_ACLK_1 <= S00_ACLK; S00_ARESETN_1(0) <= S00_ARESETN(0); S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY; S00_AXI_awready <= axi_mem_intercon_to_s00_couplers_AWREADY; S00_AXI_bid(11 downto 0) <= axi_mem_intercon_to_s00_couplers_BID(11 downto 0); S00_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0); S00_AXI_bvalid <= axi_mem_intercon_to_s00_couplers_BVALID; S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0); S00_AXI_rid(11 downto 0) <= axi_mem_intercon_to_s00_couplers_RID(11 downto 0); S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST; S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0); S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID; S00_AXI_wready <= axi_mem_intercon_to_s00_couplers_WREADY; axi_mem_intercon_ACLK_net <= M00_ACLK; axi_mem_intercon_ARESETN_net(0) <= M00_ARESETN(0); axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); axi_mem_intercon_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0); axi_mem_intercon_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0); axi_mem_intercon_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0); axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0); axi_mem_intercon_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0); axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid; axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0); axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0); axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0); axi_mem_intercon_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0); axi_mem_intercon_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0); axi_mem_intercon_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0); axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0); axi_mem_intercon_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0); axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0); axi_mem_intercon_to_s00_couplers_AWVALID <= S00_AXI_awvalid; axi_mem_intercon_to_s00_couplers_BREADY <= S00_AXI_bready; axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready; axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0); axi_mem_intercon_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0); axi_mem_intercon_to_s00_couplers_WLAST <= S00_AXI_wlast; axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0); axi_mem_intercon_to_s00_couplers_WVALID <= S00_AXI_wvalid; s00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready; s00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready; s00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); s00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid; s00_couplers_to_axi_mem_intercon_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0); s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); s00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid; s00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready; s00_couplers: entity work.s00_couplers_imp_K5P28A port map ( M_ACLK => axi_mem_intercon_ACLK_net, M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0), M_AXI_araddr(12 downto 0) => s00_couplers_to_axi_mem_intercon_ARADDR(12 downto 0), M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0), M_AXI_arready => s00_couplers_to_axi_mem_intercon_ARREADY, M_AXI_arvalid => s00_couplers_to_axi_mem_intercon_ARVALID, M_AXI_awaddr(12 downto 0) => s00_couplers_to_axi_mem_intercon_AWADDR(12 downto 0), M_AXI_awprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0), M_AXI_awready => s00_couplers_to_axi_mem_intercon_AWREADY, M_AXI_awvalid => s00_couplers_to_axi_mem_intercon_AWVALID, M_AXI_bready => s00_couplers_to_axi_mem_intercon_BREADY, M_AXI_bresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_BRESP(1 downto 0), M_AXI_bvalid => s00_couplers_to_axi_mem_intercon_BVALID, M_AXI_rdata(31 downto 0) => s00_couplers_to_axi_mem_intercon_RDATA(31 downto 0), M_AXI_rready => s00_couplers_to_axi_mem_intercon_RREADY, M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0), M_AXI_rvalid => s00_couplers_to_axi_mem_intercon_RVALID, M_AXI_wdata(31 downto 0) => s00_couplers_to_axi_mem_intercon_WDATA(31 downto 0), M_AXI_wready => s00_couplers_to_axi_mem_intercon_WREADY, M_AXI_wstrb(3 downto 0) => s00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0), M_AXI_wvalid => s00_couplers_to_axi_mem_intercon_WVALID, S_ACLK => S00_ACLK_1, S_ARESETN(0) => S00_ARESETN_1(0), S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0), S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0), S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0), S_AXI_arid(11 downto 0) => axi_mem_intercon_to_s00_couplers_ARID(11 downto 0), S_AXI_arlen(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(3 downto 0), S_AXI_arlock(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARLOCK(1 downto 0), S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0), S_AXI_arqos(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARQOS(3 downto 0), S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY, S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0), S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID, S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0), S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0), S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0), S_AXI_awid(11 downto 0) => axi_mem_intercon_to_s00_couplers_AWID(11 downto 0), S_AXI_awlen(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWLEN(3 downto 0), S_AXI_awlock(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWLOCK(1 downto 0), S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0), S_AXI_awqos(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWQOS(3 downto 0), S_AXI_awready => axi_mem_intercon_to_s00_couplers_AWREADY, S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0), S_AXI_awvalid => axi_mem_intercon_to_s00_couplers_AWVALID, S_AXI_bid(11 downto 0) => axi_mem_intercon_to_s00_couplers_BID(11 downto 0), S_AXI_bready => axi_mem_intercon_to_s00_couplers_BREADY, S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0), S_AXI_bvalid => axi_mem_intercon_to_s00_couplers_BVALID, S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0), S_AXI_rid(11 downto 0) => axi_mem_intercon_to_s00_couplers_RID(11 downto 0), S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST, S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY, S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0), S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID, S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0), S_AXI_wid(11 downto 0) => axi_mem_intercon_to_s00_couplers_WID(11 downto 0), S_AXI_wlast => axi_mem_intercon_to_s00_couplers_WLAST, S_AXI_wready => axi_mem_intercon_to_s00_couplers_WREADY, S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0), S_AXI_wvalid => axi_mem_intercon_to_s00_couplers_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ARM is port ( BRAM_PORTA_addr : out STD_LOGIC_VECTOR ( 12 downto 0 ); BRAM_PORTA_clk : out STD_LOGIC; BRAM_PORTA_din : out STD_LOGIC_VECTOR ( 31 downto 0 ); BRAM_PORTA_dout : in STD_LOGIC_VECTOR ( 31 downto 0 ); BRAM_PORTA_en : out STD_LOGIC; BRAM_PORTA_rst : out STD_LOGIC; BRAM_PORTA_we : out STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC ); end ARM; architecture STRUCTURE of ARM is component ARM_arm_0 is port ( USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); end component ARM_arm_0; component ARM_armbus_0 is port ( s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; bram_rst_a : out STD_LOGIC; bram_clk_a : out STD_LOGIC; bram_en_a : out STD_LOGIC; bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 ); bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 ); bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 ); bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); end component ARM_armbus_0; component ARM_rst_arm_40M_0 is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end component ARM_rst_arm_40M_0; signal GND_1 : STD_LOGIC; signal VCC_1 : STD_LOGIC; signal arm_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 ); signal arm_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 ); signal arm_DDR_CAS_N : STD_LOGIC; signal arm_DDR_CKE : STD_LOGIC; signal arm_DDR_CK_N : STD_LOGIC; signal arm_DDR_CK_P : STD_LOGIC; signal arm_DDR_CS_N : STD_LOGIC; signal arm_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); signal arm_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal arm_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 ); signal arm_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 ); signal arm_DDR_ODT : STD_LOGIC; signal arm_DDR_RAS_N : STD_LOGIC; signal arm_DDR_RESET_N : STD_LOGIC; signal arm_DDR_WE_N : STD_LOGIC; signal arm_FCLK_CLK0 : STD_LOGIC; signal arm_FCLK_RESET0_N : STD_LOGIC; signal arm_FIXED_IO_DDR_VRN : STD_LOGIC; signal arm_FIXED_IO_DDR_VRP : STD_LOGIC; signal arm_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); signal arm_FIXED_IO_PS_CLK : STD_LOGIC; signal arm_FIXED_IO_PS_PORB : STD_LOGIC; signal arm_FIXED_IO_PS_SRSTB : STD_LOGIC; signal arm_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal arm_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal arm_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal arm_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal arm_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal arm_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal arm_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal arm_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal arm_M_AXI_GP0_ARREADY : STD_LOGIC; signal arm_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal arm_M_AXI_GP0_ARVALID : STD_LOGIC; signal arm_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal arm_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal arm_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal arm_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal arm_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal arm_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal arm_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal arm_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal arm_M_AXI_GP0_AWREADY : STD_LOGIC; signal arm_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal arm_M_AXI_GP0_AWVALID : STD_LOGIC; signal arm_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal arm_M_AXI_GP0_BREADY : STD_LOGIC; signal arm_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal arm_M_AXI_GP0_BVALID : STD_LOGIC; signal arm_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal arm_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal arm_M_AXI_GP0_RLAST : STD_LOGIC; signal arm_M_AXI_GP0_RREADY : STD_LOGIC; signal arm_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal arm_M_AXI_GP0_RVALID : STD_LOGIC; signal arm_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal arm_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal arm_M_AXI_GP0_WLAST : STD_LOGIC; signal arm_M_AXI_GP0_WREADY : STD_LOGIC; signal arm_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal arm_M_AXI_GP0_WVALID : STD_LOGIC; signal armbus_BRAM_PORTA_ADDR : STD_LOGIC_VECTOR ( 12 downto 0 ); signal armbus_BRAM_PORTA_CLK : STD_LOGIC; signal armbus_BRAM_PORTA_DIN : STD_LOGIC_VECTOR ( 31 downto 0 ); signal armbus_BRAM_PORTA_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 ); signal armbus_BRAM_PORTA_EN : STD_LOGIC; signal armbus_BRAM_PORTA_RST : STD_LOGIC; signal armbus_BRAM_PORTA_WE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 ); signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC; signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 ); signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC; signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC; signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC; signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC; signal rst_arm_40M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 ); signal rst_arm_40M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_arm_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; signal NLW_arm_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_rst_arm_40M_mb_reset_UNCONNECTED : STD_LOGIC; signal NLW_rst_arm_40M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_rst_arm_40M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); begin BRAM_PORTA_addr(12 downto 0) <= armbus_BRAM_PORTA_ADDR(12 downto 0); BRAM_PORTA_clk <= armbus_BRAM_PORTA_CLK; BRAM_PORTA_din(31 downto 0) <= armbus_BRAM_PORTA_DIN(31 downto 0); BRAM_PORTA_en <= armbus_BRAM_PORTA_EN; BRAM_PORTA_rst <= armbus_BRAM_PORTA_RST; BRAM_PORTA_we(3 downto 0) <= armbus_BRAM_PORTA_WE(3 downto 0); armbus_BRAM_PORTA_DOUT(31 downto 0) <= BRAM_PORTA_dout(31 downto 0); GND: unisim.vcomponents.GND port map ( G => GND_1 ); VCC: unisim.vcomponents.VCC port map ( P => VCC_1 ); arm: component ARM_arm_0 port map ( DDR_Addr(14 downto 0) => DDR_addr(14 downto 0), DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0), DDR_CAS_n => DDR_cas_n, DDR_CKE => DDR_cke, DDR_CS_n => DDR_cs_n, DDR_Clk => DDR_ck_p, DDR_Clk_n => DDR_ck_n, DDR_DM(3 downto 0) => DDR_dm(3 downto 0), DDR_DQ(31 downto 0) => DDR_dq(31 downto 0), DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_DRSTB => DDR_reset_n, DDR_ODT => DDR_odt, DDR_RAS_n => DDR_ras_n, DDR_VRN => FIXED_IO_ddr_vrn, DDR_VRP => FIXED_IO_ddr_vrp, DDR_WEB => DDR_we_n, FCLK_CLK0 => arm_FCLK_CLK0, FCLK_RESET0_N => arm_FCLK_RESET0_N, MIO(53 downto 0) => FIXED_IO_mio(53 downto 0), M_AXI_GP0_ACLK => arm_FCLK_CLK0, M_AXI_GP0_ARADDR(31 downto 0) => arm_M_AXI_GP0_ARADDR(31 downto 0), M_AXI_GP0_ARBURST(1 downto 0) => arm_M_AXI_GP0_ARBURST(1 downto 0), M_AXI_GP0_ARCACHE(3 downto 0) => arm_M_AXI_GP0_ARCACHE(3 downto 0), M_AXI_GP0_ARID(11 downto 0) => arm_M_AXI_GP0_ARID(11 downto 0), M_AXI_GP0_ARLEN(3 downto 0) => arm_M_AXI_GP0_ARLEN(3 downto 0), M_AXI_GP0_ARLOCK(1 downto 0) => arm_M_AXI_GP0_ARLOCK(1 downto 0), M_AXI_GP0_ARPROT(2 downto 0) => arm_M_AXI_GP0_ARPROT(2 downto 0), M_AXI_GP0_ARQOS(3 downto 0) => arm_M_AXI_GP0_ARQOS(3 downto 0), M_AXI_GP0_ARREADY => arm_M_AXI_GP0_ARREADY, M_AXI_GP0_ARSIZE(2 downto 0) => arm_M_AXI_GP0_ARSIZE(2 downto 0), M_AXI_GP0_ARVALID => arm_M_AXI_GP0_ARVALID, M_AXI_GP0_AWADDR(31 downto 0) => arm_M_AXI_GP0_AWADDR(31 downto 0), M_AXI_GP0_AWBURST(1 downto 0) => arm_M_AXI_GP0_AWBURST(1 downto 0), M_AXI_GP0_AWCACHE(3 downto 0) => arm_M_AXI_GP0_AWCACHE(3 downto 0), M_AXI_GP0_AWID(11 downto 0) => arm_M_AXI_GP0_AWID(11 downto 0), M_AXI_GP0_AWLEN(3 downto 0) => arm_M_AXI_GP0_AWLEN(3 downto 0), M_AXI_GP0_AWLOCK(1 downto 0) => arm_M_AXI_GP0_AWLOCK(1 downto 0), M_AXI_GP0_AWPROT(2 downto 0) => arm_M_AXI_GP0_AWPROT(2 downto 0), M_AXI_GP0_AWQOS(3 downto 0) => arm_M_AXI_GP0_AWQOS(3 downto 0), M_AXI_GP0_AWREADY => arm_M_AXI_GP0_AWREADY, M_AXI_GP0_AWSIZE(2 downto 0) => arm_M_AXI_GP0_AWSIZE(2 downto 0), M_AXI_GP0_AWVALID => arm_M_AXI_GP0_AWVALID, M_AXI_GP0_BID(11 downto 0) => arm_M_AXI_GP0_BID(11 downto 0), M_AXI_GP0_BREADY => arm_M_AXI_GP0_BREADY, M_AXI_GP0_BRESP(1 downto 0) => arm_M_AXI_GP0_BRESP(1 downto 0), M_AXI_GP0_BVALID => arm_M_AXI_GP0_BVALID, M_AXI_GP0_RDATA(31 downto 0) => arm_M_AXI_GP0_RDATA(31 downto 0), M_AXI_GP0_RID(11 downto 0) => arm_M_AXI_GP0_RID(11 downto 0), M_AXI_GP0_RLAST => arm_M_AXI_GP0_RLAST, M_AXI_GP0_RREADY => arm_M_AXI_GP0_RREADY, M_AXI_GP0_RRESP(1 downto 0) => arm_M_AXI_GP0_RRESP(1 downto 0), M_AXI_GP0_RVALID => arm_M_AXI_GP0_RVALID, M_AXI_GP0_WDATA(31 downto 0) => arm_M_AXI_GP0_WDATA(31 downto 0), M_AXI_GP0_WID(11 downto 0) => arm_M_AXI_GP0_WID(11 downto 0), M_AXI_GP0_WLAST => arm_M_AXI_GP0_WLAST, M_AXI_GP0_WREADY => arm_M_AXI_GP0_WREADY, M_AXI_GP0_WSTRB(3 downto 0) => arm_M_AXI_GP0_WSTRB(3 downto 0), M_AXI_GP0_WVALID => arm_M_AXI_GP0_WVALID, PS_CLK => FIXED_IO_ps_clk, PS_PORB => FIXED_IO_ps_porb, PS_SRSTB => FIXED_IO_ps_srstb, USB0_PORT_INDCTL(1 downto 0) => NLW_arm_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0), USB0_VBUS_PWRFAULT => GND_1, USB0_VBUS_PWRSELECT => NLW_arm_USB0_VBUS_PWRSELECT_UNCONNECTED ); armbus: component ARM_armbus_0 port map ( bram_addr_a(12 downto 0) => armbus_BRAM_PORTA_ADDR(12 downto 0), bram_clk_a => armbus_BRAM_PORTA_CLK, bram_en_a => armbus_BRAM_PORTA_EN, bram_rddata_a(31 downto 0) => armbus_BRAM_PORTA_DOUT(31 downto 0), bram_rst_a => armbus_BRAM_PORTA_RST, bram_we_a(3 downto 0) => armbus_BRAM_PORTA_WE(3 downto 0), bram_wrdata_a(31 downto 0) => armbus_BRAM_PORTA_DIN(31 downto 0), s_axi_aclk => arm_FCLK_CLK0, s_axi_araddr(12 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(12 downto 0), s_axi_aresetn => rst_arm_40M_peripheral_aresetn(0), s_axi_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0), s_axi_arready => axi_mem_intercon_M00_AXI_ARREADY, s_axi_arvalid => axi_mem_intercon_M00_AXI_ARVALID, s_axi_awaddr(12 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(12 downto 0), s_axi_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0), s_axi_awready => axi_mem_intercon_M00_AXI_AWREADY, s_axi_awvalid => axi_mem_intercon_M00_AXI_AWVALID, s_axi_bready => axi_mem_intercon_M00_AXI_BREADY, s_axi_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0), s_axi_bvalid => axi_mem_intercon_M00_AXI_BVALID, s_axi_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0), s_axi_rready => axi_mem_intercon_M00_AXI_RREADY, s_axi_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0), s_axi_rvalid => axi_mem_intercon_M00_AXI_RVALID, s_axi_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0), s_axi_wready => axi_mem_intercon_M00_AXI_WREADY, s_axi_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0), s_axi_wvalid => axi_mem_intercon_M00_AXI_WVALID ); axi_mem_intercon: entity work.ARM_axi_mem_intercon_0 port map ( ACLK => arm_FCLK_CLK0, ARESETN(0) => rst_arm_40M_interconnect_aresetn(0), M00_ACLK => arm_FCLK_CLK0, M00_ARESETN(0) => rst_arm_40M_peripheral_aresetn(0), M00_AXI_araddr(12 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(12 downto 0), M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0), M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY, M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID, M00_AXI_awaddr(12 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(12 downto 0), M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0), M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY, M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID, M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY, M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0), M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID, M00_AXI_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0), M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY, M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0), M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID, M00_AXI_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0), M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY, M00_AXI_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0), M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID, S00_ACLK => arm_FCLK_CLK0, S00_ARESETN(0) => rst_arm_40M_peripheral_aresetn(0), S00_AXI_araddr(31 downto 0) => arm_M_AXI_GP0_ARADDR(31 downto 0), S00_AXI_arburst(1 downto 0) => arm_M_AXI_GP0_ARBURST(1 downto 0), S00_AXI_arcache(3 downto 0) => arm_M_AXI_GP0_ARCACHE(3 downto 0), S00_AXI_arid(11 downto 0) => arm_M_AXI_GP0_ARID(11 downto 0), S00_AXI_arlen(3 downto 0) => arm_M_AXI_GP0_ARLEN(3 downto 0), S00_AXI_arlock(1 downto 0) => arm_M_AXI_GP0_ARLOCK(1 downto 0), S00_AXI_arprot(2 downto 0) => arm_M_AXI_GP0_ARPROT(2 downto 0), S00_AXI_arqos(3 downto 0) => arm_M_AXI_GP0_ARQOS(3 downto 0), S00_AXI_arready => arm_M_AXI_GP0_ARREADY, S00_AXI_arsize(2 downto 0) => arm_M_AXI_GP0_ARSIZE(2 downto 0), S00_AXI_arvalid => arm_M_AXI_GP0_ARVALID, S00_AXI_awaddr(31 downto 0) => arm_M_AXI_GP0_AWADDR(31 downto 0), S00_AXI_awburst(1 downto 0) => arm_M_AXI_GP0_AWBURST(1 downto 0), S00_AXI_awcache(3 downto 0) => arm_M_AXI_GP0_AWCACHE(3 downto 0), S00_AXI_awid(11 downto 0) => arm_M_AXI_GP0_AWID(11 downto 0), S00_AXI_awlen(3 downto 0) => arm_M_AXI_GP0_AWLEN(3 downto 0), S00_AXI_awlock(1 downto 0) => arm_M_AXI_GP0_AWLOCK(1 downto 0), S00_AXI_awprot(2 downto 0) => arm_M_AXI_GP0_AWPROT(2 downto 0), S00_AXI_awqos(3 downto 0) => arm_M_AXI_GP0_AWQOS(3 downto 0), S00_AXI_awready => arm_M_AXI_GP0_AWREADY, S00_AXI_awsize(2 downto 0) => arm_M_AXI_GP0_AWSIZE(2 downto 0), S00_AXI_awvalid => arm_M_AXI_GP0_AWVALID, S00_AXI_bid(11 downto 0) => arm_M_AXI_GP0_BID(11 downto 0), S00_AXI_bready => arm_M_AXI_GP0_BREADY, S00_AXI_bresp(1 downto 0) => arm_M_AXI_GP0_BRESP(1 downto 0), S00_AXI_bvalid => arm_M_AXI_GP0_BVALID, S00_AXI_rdata(31 downto 0) => arm_M_AXI_GP0_RDATA(31 downto 0), S00_AXI_rid(11 downto 0) => arm_M_AXI_GP0_RID(11 downto 0), S00_AXI_rlast => arm_M_AXI_GP0_RLAST, S00_AXI_rready => arm_M_AXI_GP0_RREADY, S00_AXI_rresp(1 downto 0) => arm_M_AXI_GP0_RRESP(1 downto 0), S00_AXI_rvalid => arm_M_AXI_GP0_RVALID, S00_AXI_wdata(31 downto 0) => arm_M_AXI_GP0_WDATA(31 downto 0), S00_AXI_wid(11 downto 0) => arm_M_AXI_GP0_WID(11 downto 0), S00_AXI_wlast => arm_M_AXI_GP0_WLAST, S00_AXI_wready => arm_M_AXI_GP0_WREADY, S00_AXI_wstrb(3 downto 0) => arm_M_AXI_GP0_WSTRB(3 downto 0), S00_AXI_wvalid => arm_M_AXI_GP0_WVALID ); rst_arm_40M: component ARM_rst_arm_40M_0 port map ( aux_reset_in => VCC_1, bus_struct_reset(0) => NLW_rst_arm_40M_bus_struct_reset_UNCONNECTED(0), dcm_locked => VCC_1, ext_reset_in => arm_FCLK_RESET0_N, interconnect_aresetn(0) => rst_arm_40M_interconnect_aresetn(0), mb_debug_sys_rst => GND_1, mb_reset => NLW_rst_arm_40M_mb_reset_UNCONNECTED, peripheral_aresetn(0) => rst_arm_40M_peripheral_aresetn(0), peripheral_reset(0) => NLW_rst_arm_40M_peripheral_reset_UNCONNECTED(0), slowest_sync_clk => arm_FCLK_CLK0 ); end STRUCTURE;
-------------------------------------------------------------------------------- -- FILE: Dlx -- DESC: Toplevel of DLX micro-processor -- -- Author: -- Create: 2015-05-24 -- Update: 2015-10-03 -- Status: TESTED -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.Types.all; use work.Consts.all; use work.Funcs.all; -------------------------------------------------------------------------------- -- ENTITY -------------------------------------------------------------------------------- entity Dlx is generic ( ADDR_SIZE : integer := C_SYS_ADDR_SIZE; DATA_SIZE : integer := C_SYS_DATA_SIZE; ISTR_SIZE : integer := C_SYS_ISTR_SIZE; DRCW_SIZE : integer := C_CTR_DRCW_SIZE ); port ( clk : in std_logic := '0'; rst : in std_logic := '0'; -- Active Low en_iram: out std_logic:='1'; pc_bus : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0'); ir_bus : in std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0'); en_dram : out std_logic:='1'; addr_bus : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0'); di_bus : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); do_bus : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); dr_cw : out std_logic_vector(DRCW_SIZE-1 downto 0):=(others=>'0') ); end Dlx; architecture dlx_arch of Dlx is -- Control Unit component ControlUnit is generic( ISTR_SIZE : integer := C_SYS_ISTR_SIZE; -- Instruction Register Size DATA_SIZE : integer := C_SYS_DATA_SIZE; -- Data Size OPCD_SIZE : integer := C_SYS_OPCD_SIZE; -- Op Code Size FUNC_SIZE : integer := C_SYS_FUNC_SIZE; -- Func Field Size for R-Type Ops CWRD_SIZE : integer := C_SYS_CWRD_SIZE; -- Control Word Size CALU_SIZE : integer := C_CTR_CALU_SIZE; -- ALU Op Code Word Size ADDR_SIZE : integer := C_SYS_ADDR_SIZE -- Address size ); port( clk : in std_logic; rst : in std_logic; ir : in std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0'); pc : in std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0'); reg_a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); ld_a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); sig_bal : in std_logic:='0'; sig_bpw : out std_logic:='0'; sig_jral: in std_logic:='0'; sig_ral : in std_logic; sig_mul : in std_logic; sig_div : in std_logic; sig_sqrt: in std_logic; cw : out std_logic_vector(CWRD_SIZE-1 downto 0); calu : out std_logic_vector(CALU_SIZE-1 downto 0) ); end component; -- Datapath (MISSING!You must include it in your final project!) component DataPath is generic ( ADDR_SIZE : integer := C_SYS_ADDR_SIZE; DATA_SIZE : integer := C_SYS_DATA_SIZE; ISTR_SIZE : integer := C_SYS_ISTR_SIZE; OPCD_SIZE : integer := C_SYS_OPCD_SIZE; IMME_SIZE : integer := C_SYS_IMME_SIZE; CWRD_SIZE : integer := C_SYS_CWRD_SIZE; -- Datapath Contrl Word CALU_SIZE : integer := C_CTR_CALU_SIZE; DRCW_SIZE : integer := C_CTR_DRCW_SIZE ); port ( clk : in std_logic; rst : in std_logic; istr_addr : out std_logic_vector(ADDR_SIZE-1 downto 0); istr_val : in std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0'); ir_out : out std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0'); pc_out : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0'); reg_a_out : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); ld_a_out : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); data_addr : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0'); data_i_val : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); data_o_val : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); cw : in std_logic_vector(CWRD_SIZE-1 downto 0):=(others=>'0'); dr_cw : out std_logic_vector(DRCW_SIZE-1 downto 0):=(others=>'0'); calu : in std_logic_vector(CALU_SIZE-1 downto 0):=(others=>'0'); sig_bal : out std_logic:='0'; sig_bpw : in std_logic:='0'; sig_jral : out std_logic:='0'; sig_ral : out std_logic:='0'; sig_mul : out std_logic:='0'; sig_div : out std_logic:='0'; sig_sqrt : out std_logic:='0' ); end component; -- CONSTANTS constant FUNC_SIZE : integer := C_SYS_FUNC_SIZE; constant OPCD_SIZE : integer := C_SYS_OPCD_SIZE; constant CWRD_SIZE : integer := C_SYS_CWRD_SIZE; constant CALU_SIZE : integer := C_CTR_CALU_SIZE; constant IMME_SIZE : integer := C_SYS_IMME_SIZE; -- SIGNALS signal ir : std_logic_vector(ISTR_SIZE-1 downto 0); signal pc : std_logic_vector(ADDR_SIZE-1 downto 0); signal cw : std_logic_vector(CWRD_SIZE-1 downto 0); signal calu : std_logic_vector(CALU_SIZE-1 downto 0); signal reg_a_val: std_logic_vector(DATA_SIZE-1 downto 0); signal ld_a_val : std_logic_vector(DATA_SIZE-1 downto 0); signal sig_bal : std_logic:='0'; signal sig_bpw : std_logic:='0'; signal sig_jral : std_logic:='0'; signal sig_ral : std_logic:='0'; signal sig_mul : std_logic:='0'; signal sig_div : std_logic:='0'; signal sig_sqrt : std_logic:='0'; begin CU0: ControlUnit generic map(ISTR_SIZE, DATA_SIZE, OPCD_SIZE, FUNC_SIZE, CWRD_SIZE, CALU_SIZE) port map(clk, rst, ir, pc, reg_a_val, ld_a_val, sig_bal, sig_bpw, sig_jral, sig_ral, sig_mul, sig_div, sig_sqrt, cw, calu); DP0: DataPath generic map(ADDR_SIZE, DATA_SIZE, ISTR_SIZE, OPCD_SIZE, IMME_SIZE, CWRD_SIZE, CALU_SIZE, DRCW_SIZE) port map(clk, rst, pc_bus, ir_bus, ir, pc, reg_a_val, ld_a_val, addr_bus, do_bus, di_bus, cw, dr_cw, calu, sig_bal, sig_bpw, sig_jral, sig_ral, sig_mul, sig_div, sig_sqrt); en_iram <= cw(CW_S1_LATCH); en_dram <= '1'; end dlx_arch;
------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact office@br-automation.com -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; USE ieee.math_real.log2; USE ieee.math_real.ceil; entity req_ack is generic( ack_delay_g : integer := 1; zero_delay_g : boolean := false ); port( clk : in std_logic; rst : in std_logic; enable : in std_logic; ack : out std_logic ); end req_ack; architecture rtl of req_ack is constant iMaxCnt : integer := ack_delay_g; constant iMaxCntLog2 : integer := integer(ceil(log2(real(iMaxCnt)))); signal cnt, cnt_next : std_logic_vector(iMaxCntLog2 downto 0); signal cnt_tc : std_logic; begin genDelay : if zero_delay_g = false generate theCnter : process(clk, rst) begin if rst = '1' then cnt <= (others => '0'); elsif clk = '1' and clk'event then cnt <= cnt_next; end if; end process; cnt_next <= cnt + 1 when enable = '1' and cnt_tc /= '1' else (others => '0'); cnt_tc <= '1' when cnt = iMaxCnt else '0'; ack <= cnt_tc; end generate; genNoDelay : if zero_delay_g = true generate ack <= enable; end generate; end rtl;
------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact office@br-automation.com -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; USE ieee.math_real.log2; USE ieee.math_real.ceil; entity req_ack is generic( ack_delay_g : integer := 1; zero_delay_g : boolean := false ); port( clk : in std_logic; rst : in std_logic; enable : in std_logic; ack : out std_logic ); end req_ack; architecture rtl of req_ack is constant iMaxCnt : integer := ack_delay_g; constant iMaxCntLog2 : integer := integer(ceil(log2(real(iMaxCnt)))); signal cnt, cnt_next : std_logic_vector(iMaxCntLog2 downto 0); signal cnt_tc : std_logic; begin genDelay : if zero_delay_g = false generate theCnter : process(clk, rst) begin if rst = '1' then cnt <= (others => '0'); elsif clk = '1' and clk'event then cnt <= cnt_next; end if; end process; cnt_next <= cnt + 1 when enable = '1' and cnt_tc /= '1' else (others => '0'); cnt_tc <= '1' when cnt = iMaxCnt else '0'; ack <= cnt_tc; end generate; genNoDelay : if zero_delay_g = true generate ack <= enable; end generate; end rtl;
------------------------------------------------------------------------------- --! @file syncTog-rtl-ea.vhd -- --! @brief Synchronizer with toggling signal -- --! @details This is a synchronizer that transfers an incoming signal to the --! target clock domain with toggling signal levels. ------------------------------------------------------------------------------- -- -- (c) B&R Industrial Automation GmbH, 2014 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact office@br-automation.com -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --! Common library library libcommon; --! Use common library global package use libcommon.global.all; entity syncTog is generic ( --! Stages gStages : natural := 2; --! Initialization level gInit : std_logic := cInactivated ); port ( --! Source reset iSrc_rst : in std_logic; --! Source clock iSrc_clk : in std_logic; --! Source data iSrc_data : in std_logic; --! Destination reset iDst_rst : in std_logic; --! Destination clock iDst_clk : in std_logic; --! Destination data oDst_data : out std_logic ); end syncTog; architecture rtl of syncTog is --! Source pulse signal srcPulse : std_logic; --! Transfer toggle signal metaToggle : std_logic; --! Transferred toggle signal toggle : std_logic; --! Destination pulse signal dstPulse : std_logic; begin -- Output map oDst_data <= dstPulse; --! This is the first edge detector generating a single pulse. FIRST_EDGE : entity libcommon.edgedetector port map ( iArst => iSrc_rst, iClk => iSrc_clk, iEnable => cActivated, iData => iSrc_data, oRising => srcPulse, oFalling => open, oAny => open ); --! This process generates a toggling signal, controled by the rising edge --! of the first edge detector. GEN_TOGGLE : process(iSrc_rst, iSrc_clk) begin if iSrc_rst = cActivated then metaToggle <= cInactivated; elsif rising_edge(iSrc_clk) then if srcPulse = cActivated then metaToggle <= not metaToggle; end if; end if; end process GEN_TOGGLE; --! This synchronizer transfers the metaToggle to the destination clock --! domain. SYNC : entity libcommon.synchronizer generic map ( gStages => gStages, gInit => gInit ) port map ( iArst => iDst_rst, iClk => iDst_clk, iAsync => metaToggle, oSync => toggle ); --! The second edge detector detects any edge of the synchronized toggle. SECOND_EDGE : entity libcommon.edgedetector port map ( iArst => iDst_rst, iClk => iDst_clk, iEnable => cActivated, iData => toggle, oRising => open, oFalling => open, oAny => dstPulse ); end rtl;
library verilog; use verilog.vl_types.all; entity drive_current_monitor is port( temp_vect : in vl_logic_vector(63 downto 0); resistor_vect : in vl_logic_vector(63 downto 0); current_vect : in vl_logic_vector(63 downto 0); serial_out : out vl_logic ); end drive_current_monitor;
library verilog; use verilog.vl_types.all; entity drive_current_monitor is port( temp_vect : in vl_logic_vector(63 downto 0); resistor_vect : in vl_logic_vector(63 downto 0); current_vect : in vl_logic_vector(63 downto 0); serial_out : out vl_logic ); end drive_current_monitor;
library verilog; use verilog.vl_types.all; entity drive_current_monitor is port( temp_vect : in vl_logic_vector(63 downto 0); resistor_vect : in vl_logic_vector(63 downto 0); current_vect : in vl_logic_vector(63 downto 0); serial_out : out vl_logic ); end drive_current_monitor;
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015 -- Date : Fri Oct 16 15:22:50 2015 -- Host : cascade.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.1 (Maipo) -- Command : write_vhdl -force -mode funcsim -- /afs/ece.cmu.edu/usr/cmbarker/Private/Atari7800/maria/maria.srcs/sources_1/ip/dll_img_ram/dll_img_ram_funcsim.vhdl -- Design : dll_img_ram -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity dll_img_ram_blk_mem_gen_prim_wrapper_init is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of dll_img_ram_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end dll_img_ram_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of dll_img_ram_blk_mem_gen_prim_wrapper_init is signal CASCADEINA : STD_LOGIC; signal CASCADEINB : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE"; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "LOWER", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 1, READ_WIDTH_B => 1, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "NONE", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1 ) port map ( ADDRARDADDR(15 downto 0) => addra(15 downto 0), ADDRBWRADDR(15) => '0', ADDRBWRADDR(14) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10) => '0', ADDRBWRADDR(9) => '0', ADDRBWRADDR(8) => '0', ADDRBWRADDR(7) => '0', ADDRBWRADDR(6) => '0', ADDRBWRADDR(5) => '0', ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => CASCADEINA, CASCADEOUTB => CASCADEINB, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3) => '0', DIADI(2) => '0', DIADI(1) => '0', DIADI(0) => dina(0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "UPPER", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 1, READ_WIDTH_B => 1, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "NONE", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1 ) port map ( ADDRARDADDR(15 downto 0) => addra(15 downto 0), ADDRBWRADDR(15) => '0', ADDRBWRADDR(14) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10) => '0', ADDRBWRADDR(9) => '0', ADDRBWRADDR(8) => '0', ADDRBWRADDR(7) => '0', ADDRBWRADDR(6) => '0', ADDRBWRADDR(5) => '0', ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CASCADEINA => CASCADEINA, CASCADEINB => CASCADEINB, CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3) => '0', DIADI(2) => '0', DIADI(1) => '0', DIADI(0) => dina(0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(3) => '0', DIPBDIP(2) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1), DOADO(0) => douta(0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7) => '0', WEBWE(6) => '0', WEBWE(5) => '0', WEBWE(4) => '0', WEBWE(3) => '0', WEBWE(2) => '0', WEBWE(1) => '0', WEBWE(0) => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized0\ is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init"; end \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized0\; architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized0\ is signal CASCADEINA : STD_LOGIC; signal CASCADEINB : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE"; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "LOWER", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 1, READ_WIDTH_B => 1, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "NONE", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1 ) port map ( ADDRARDADDR(15 downto 0) => addra(15 downto 0), ADDRBWRADDR(15) => '0', ADDRBWRADDR(14) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10) => '0', ADDRBWRADDR(9) => '0', ADDRBWRADDR(8) => '0', ADDRBWRADDR(7) => '0', ADDRBWRADDR(6) => '0', ADDRBWRADDR(5) => '0', ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => CASCADEINA, CASCADEOUTB => CASCADEINB, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3) => '0', DIADI(2) => '0', DIADI(1) => '0', DIADI(0) => dina(0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(3) => '0', DIPBDIP(2) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7) => '0', WEBWE(6) => '0', WEBWE(5) => '0', WEBWE(4) => '0', WEBWE(3) => '0', WEBWE(2) => '0', WEBWE(1) => '0', WEBWE(0) => '0' ); \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "UPPER", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 1, READ_WIDTH_B => 1, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "NONE", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1 ) port map ( ADDRARDADDR(15 downto 0) => addra(15 downto 0), ADDRBWRADDR(15) => '0', ADDRBWRADDR(14) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10) => '0', ADDRBWRADDR(9) => '0', ADDRBWRADDR(8) => '0', ADDRBWRADDR(7) => '0', ADDRBWRADDR(6) => '0', ADDRBWRADDR(5) => '0', ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CASCADEINA => CASCADEINA, CASCADEINB => CASCADEINB, CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3) => '0', DIADI(2) => '0', DIADI(1) => '0', DIADI(0) => dina(0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(3) => '0', DIPBDIP(2) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1), DOADO(0) => douta(0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7) => '0', WEBWE(6) => '0', WEBWE(5) => '0', WEBWE(4) => '0', WEBWE(3) => '0', WEBWE(2) => '0', WEBWE(1) => '0', WEBWE(0) => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized1\ is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init"; end \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized1\; architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized1\ is signal CASCADEINA : STD_LOGIC; signal CASCADEINB : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE"; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "LOWER", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 1, READ_WIDTH_B => 1, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "NONE", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1 ) port map ( ADDRARDADDR(15 downto 0) => addra(15 downto 0), ADDRBWRADDR(15) => '0', ADDRBWRADDR(14) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10) => '0', ADDRBWRADDR(9) => '0', ADDRBWRADDR(8) => '0', ADDRBWRADDR(7) => '0', ADDRBWRADDR(6) => '0', ADDRBWRADDR(5) => '0', ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => CASCADEINA, CASCADEOUTB => CASCADEINB, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3) => '0', DIADI(2) => '0', DIADI(1) => '0', DIADI(0) => dina(0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(3) => '0', DIPBDIP(2) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(31 downto 0) => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "UPPER", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 1, READ_WIDTH_B => 1, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "NONE", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1 ) port map ( ADDRARDADDR(15 downto 0) => addra(15 downto 0), ADDRBWRADDR(15) => '0', ADDRBWRADDR(14) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10) => '0', ADDRBWRADDR(9) => '0', ADDRBWRADDR(8) => '0', ADDRBWRADDR(7) => '0', ADDRBWRADDR(6) => '0', ADDRBWRADDR(5) => '0', ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CASCADEINA => CASCADEINA, CASCADEINB => CASCADEINB, CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3) => '0', DIADI(2) => '0', DIADI(1) => '0', DIADI(0) => dina(0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(3) => '0', DIPBDIP(2) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1), DOADO(0) => douta(0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7) => '0', WEBWE(6) => '0', WEBWE(5) => '0', WEBWE(4) => '0', WEBWE(3) => '0', WEBWE(2) => '0', WEBWE(1) => '0', WEBWE(0) => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized2\ is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init"; end \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized2\; architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized2\ is signal CASCADEINA : STD_LOGIC; signal CASCADEINB : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "LOWER", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 1, READ_WIDTH_B => 1, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "NONE", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1 ) port map ( ADDRARDADDR(15 downto 0) => addra(15 downto 0), ADDRBWRADDR(15) => '0', ADDRBWRADDR(14) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10) => '0', ADDRBWRADDR(9) => '0', ADDRBWRADDR(8) => '0', ADDRBWRADDR(7) => '0', ADDRBWRADDR(6) => '0', ADDRBWRADDR(5) => '0', ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => CASCADEINA, CASCADEOUTB => CASCADEINB, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3) => '0', DIADI(2) => '0', DIADI(1) => '0', DIADI(0) => dina(0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(3) => '0', DIPBDIP(2) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7) => '0', WEBWE(6) => '0', WEBWE(5) => '0', WEBWE(4) => '0', WEBWE(3) => '0', WEBWE(2) => '0', WEBWE(1) => '0', WEBWE(0) => '0' ); \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "UPPER", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 1, READ_WIDTH_B => 1, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "NONE", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1 ) port map ( ADDRARDADDR(15 downto 0) => addra(15 downto 0), ADDRBWRADDR(15) => '0', ADDRBWRADDR(14) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10) => '0', ADDRBWRADDR(9) => '0', ADDRBWRADDR(8) => '0', ADDRBWRADDR(7) => '0', ADDRBWRADDR(6) => '0', ADDRBWRADDR(5) => '0', ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CASCADEINA => CASCADEINA, CASCADEINB => CASCADEINB, CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3) => '0', DIADI(2) => '0', DIADI(1) => '0', DIADI(0) => dina(0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(3) => '0', DIPBDIP(2) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1), DOADO(0) => douta(0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7) => '0', WEBWE(6) => '0', WEBWE(5) => '0', WEBWE(4) => '0', WEBWE(3) => '0', WEBWE(2) => '0', WEBWE(1) => '0', WEBWE(0) => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized3\ is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init"; end \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized3\; architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized3\ is signal CASCADEINA : STD_LOGIC; signal CASCADEINB : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE"; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "LOWER", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 1, READ_WIDTH_B => 1, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "NONE", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1 ) port map ( ADDRARDADDR(15 downto 0) => addra(15 downto 0), ADDRBWRADDR(15) => '0', ADDRBWRADDR(14) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10) => '0', ADDRBWRADDR(9) => '0', ADDRBWRADDR(8) => '0', ADDRBWRADDR(7) => '0', ADDRBWRADDR(6) => '0', ADDRBWRADDR(5) => '0', ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => CASCADEINA, CASCADEOUTB => CASCADEINB, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3) => '0', DIADI(2) => '0', DIADI(1) => '0', DIADI(0) => dina(0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(3) => '0', DIPBDIP(2) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => 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INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "UPPER", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 1, READ_WIDTH_B => 1, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "NONE", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1 ) port map ( ADDRARDADDR(15 downto 0) => addra(15 downto 0), ADDRBWRADDR(15) => '0', ADDRBWRADDR(14) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10) => '0', ADDRBWRADDR(9) => '0', ADDRBWRADDR(8) => '0', ADDRBWRADDR(7) => '0', ADDRBWRADDR(6) => '0', ADDRBWRADDR(5) => '0', ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CASCADEINA => CASCADEINA, CASCADEINB => CASCADEINB, CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3) => '0', DIADI(2) => '0', DIADI(1) => '0', DIADI(0) => dina(0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(3) => '0', DIPBDIP(2) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1), DOADO(0) => douta(0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7) => '0', WEBWE(6) => '0', WEBWE(5) => '0', WEBWE(4) => '0', WEBWE(3) => '0', WEBWE(2) => '0', WEBWE(1) => '0', WEBWE(0) => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized4\ is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init"; end \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized4\; architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized4\ is signal CASCADEINA : STD_LOGIC; signal CASCADEINB : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute box_type : string; attribute box_type of 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "LOWER", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 1, READ_WIDTH_B => 1, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "NONE", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1 ) port map ( ADDRARDADDR(15 downto 0) => addra(15 downto 0), ADDRBWRADDR(15) => '0', ADDRBWRADDR(14) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10) => '0', ADDRBWRADDR(9) => '0', ADDRBWRADDR(8) => '0', ADDRBWRADDR(7) => '0', ADDRBWRADDR(6) => '0', ADDRBWRADDR(5) => '0', ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => CASCADEINA, CASCADEOUTB => CASCADEINB, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3) => '0', DIADI(2) => '0', DIADI(1) => '0', DIADI(0) => dina(0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(3) => '0', DIPBDIP(2) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7) => '0', WEBWE(6) => '0', WEBWE(5) => '0', WEBWE(4) => '0', WEBWE(3) => '0', WEBWE(2) => '0', WEBWE(1) => '0', WEBWE(0) => '0' ); \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => 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WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1 ) port map ( ADDRARDADDR(15 downto 0) => addra(15 downto 0), ADDRBWRADDR(15) => '0', ADDRBWRADDR(14) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10) => '0', ADDRBWRADDR(9) => '0', ADDRBWRADDR(8) => '0', ADDRBWRADDR(7) => '0', ADDRBWRADDR(6) => '0', ADDRBWRADDR(5) => '0', ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CASCADEINA => CASCADEINA, CASCADEINB => CASCADEINB, CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3) => '0', DIADI(2) => '0', DIADI(1) => '0', DIADI(0) => dina(0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(3) => '0', DIPBDIP(2) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1), DOADO(0) => douta(0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7) => '0', WEBWE(6) => '0', WEBWE(5) => '0', WEBWE(4) => '0', WEBWE(3) => '0', WEBWE(2) => '0', WEBWE(1) => '0', WEBWE(0) => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized5\ is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init"; end \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized5\; architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized5\ is signal CASCADEINA : STD_LOGIC; signal CASCADEINB : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "UPPER", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 1, READ_WIDTH_B => 1, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "NONE", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1 ) port map ( ADDRARDADDR(15 downto 0) => addra(15 downto 0), ADDRBWRADDR(15) => '0', ADDRBWRADDR(14) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10) => '0', ADDRBWRADDR(9) => '0', ADDRBWRADDR(8) => '0', ADDRBWRADDR(7) => '0', ADDRBWRADDR(6) => '0', ADDRBWRADDR(5) => '0', ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CASCADEINA => CASCADEINA, CASCADEINB => CASCADEINB, CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3) => '0', DIADI(2) => '0', DIADI(1) => '0', DIADI(0) => dina(0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(3) => '0', DIPBDIP(2) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1), DOADO(0) => douta(0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => 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out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init"; end \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized6\; architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized6\ is signal CASCADEINA : STD_LOGIC; signal CASCADEINB : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE"; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, 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INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "UPPER", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 1, READ_WIDTH_B => 1, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "NONE", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "NO_CHANGE", WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1 ) port map ( ADDRARDADDR(15 downto 0) => addra(15 downto 0), ADDRBWRADDR(15) => '0', ADDRBWRADDR(14) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10) => '0', ADDRBWRADDR(9) => '0', ADDRBWRADDR(8) => '0', ADDRBWRADDR(7) => '0', ADDRBWRADDR(6) => '0', ADDRBWRADDR(5) => '0', ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CASCADEINA => CASCADEINA, CASCADEINB => CASCADEINB, CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\, DIADI(31) => '0', DIADI(30) => '0', DIADI(29) => '0', DIADI(28) => '0', DIADI(27) => '0', DIADI(26) => '0', DIADI(25) => '0', DIADI(24) => '0', DIADI(23) => '0', DIADI(22) => '0', DIADI(21) => '0', DIADI(20) => '0', DIADI(19) => '0', DIADI(18) => '0', DIADI(17) => '0', DIADI(16) => '0', DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11) => '0', DIADI(10) => '0', DIADI(9) => '0', DIADI(8) => '0', DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3) => '0', DIADI(2) => '0', DIADI(1) => '0', DIADI(0) => dina(0), DIBDI(31) => '0', DIBDI(30) => '0', DIBDI(29) => '0', DIBDI(28) => '0', DIBDI(27) => '0', DIBDI(26) => '0', DIBDI(25) => '0', DIBDI(24) => '0', DIBDI(23) => '0', DIBDI(22) => '0', DIBDI(21) => '0', DIBDI(20) => '0', DIBDI(19) => '0', DIBDI(18) => '0', DIBDI(17) => '0', DIBDI(16) => '0', DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11) => '0', DIBDI(10) => '0', DIBDI(9) => '0', DIBDI(8) => '0', DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3) => '0', DIBDI(2) => '0', DIBDI(1) => '0', DIBDI(0) => '0', DIPADIP(3) => '0', DIPADIP(2) => '0', DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(3) => '0', DIPBDIP(2) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1), DOADO(0) => douta(0), DOBDO(31 downto 0) => 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'0', WEBWE(1) => '0', WEBWE(0) => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity dll_img_ram_blk_mem_gen_prim_width is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of dll_img_ram_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end dll_img_ram_blk_mem_gen_prim_width; architecture STRUCTURE of dll_img_ram_blk_mem_gen_prim_width is begin \prim_init.ram\: entity work.dll_img_ram_blk_mem_gen_prim_wrapper_init port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(0), douta(0) => douta(0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \dll_img_ram_blk_mem_gen_prim_width__parameterized0\ is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; end \dll_img_ram_blk_mem_gen_prim_width__parameterized0\; architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_width__parameterized0\ is begin \prim_init.ram\: entity work.\dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized0\ port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(0), douta(0) => douta(0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \dll_img_ram_blk_mem_gen_prim_width__parameterized1\ is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width"; end \dll_img_ram_blk_mem_gen_prim_width__parameterized1\; architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_width__parameterized1\ is begin \prim_init.ram\: entity work.\dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized1\ port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(0), douta(0) => douta(0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \dll_img_ram_blk_mem_gen_prim_width__parameterized2\ is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width"; end \dll_img_ram_blk_mem_gen_prim_width__parameterized2\; architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_width__parameterized2\ is begin \prim_init.ram\: entity work.\dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized2\ port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(0), douta(0) => douta(0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \dll_img_ram_blk_mem_gen_prim_width__parameterized3\ is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width"; end \dll_img_ram_blk_mem_gen_prim_width__parameterized3\; architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_width__parameterized3\ is begin \prim_init.ram\: entity work.\dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized3\ port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(0), douta(0) => douta(0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \dll_img_ram_blk_mem_gen_prim_width__parameterized4\ is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width"; end \dll_img_ram_blk_mem_gen_prim_width__parameterized4\; architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_width__parameterized4\ is begin \prim_init.ram\: entity work.\dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized4\ port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(0), douta(0) => douta(0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \dll_img_ram_blk_mem_gen_prim_width__parameterized5\ is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width"; end \dll_img_ram_blk_mem_gen_prim_width__parameterized5\; architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_width__parameterized5\ is begin \prim_init.ram\: entity work.\dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized5\ port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(0), douta(0) => douta(0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \dll_img_ram_blk_mem_gen_prim_width__parameterized6\ is port ( douta : out STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 0 to 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width"; end \dll_img_ram_blk_mem_gen_prim_width__parameterized6\; architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_width__parameterized6\ is begin \prim_init.ram\: entity work.\dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized6\ port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(0), douta(0) => douta(0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity dll_img_ram_blk_mem_gen_generic_cstr is port ( douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of dll_img_ram_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end dll_img_ram_blk_mem_gen_generic_cstr; architecture STRUCTURE of dll_img_ram_blk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.dll_img_ram_blk_mem_gen_prim_width port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(0), douta(0) => douta(0), ena => ena, wea(0) => wea(0) ); \ramloop[1].ram.r\: entity work.\dll_img_ram_blk_mem_gen_prim_width__parameterized0\ port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(1), douta(0) => douta(1), ena => ena, wea(0) => wea(0) ); \ramloop[2].ram.r\: entity work.\dll_img_ram_blk_mem_gen_prim_width__parameterized1\ port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(2), douta(0) => douta(2), ena => ena, wea(0) => wea(0) ); \ramloop[3].ram.r\: entity work.\dll_img_ram_blk_mem_gen_prim_width__parameterized2\ port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(3), douta(0) => douta(3), ena => ena, wea(0) => wea(0) ); \ramloop[4].ram.r\: entity work.\dll_img_ram_blk_mem_gen_prim_width__parameterized3\ port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(4), douta(0) => douta(4), ena => ena, wea(0) => wea(0) ); \ramloop[5].ram.r\: entity work.\dll_img_ram_blk_mem_gen_prim_width__parameterized4\ port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(5), douta(0) => douta(5), ena => ena, wea(0) => wea(0) ); \ramloop[6].ram.r\: entity work.\dll_img_ram_blk_mem_gen_prim_width__parameterized5\ port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(6), douta(0) => douta(6), ena => ena, wea(0) => wea(0) ); \ramloop[7].ram.r\: entity work.\dll_img_ram_blk_mem_gen_prim_width__parameterized6\ port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(0) => dina(7), douta(0) => douta(7), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity dll_img_ram_blk_mem_gen_top is port ( douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of dll_img_ram_blk_mem_gen_top : entity is "blk_mem_gen_top"; end dll_img_ram_blk_mem_gen_top; architecture STRUCTURE of dll_img_ram_blk_mem_gen_top is begin \valid.cstr\: entity work.dll_img_ram_blk_mem_gen_generic_cstr port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(7 downto 0) => dina(7 downto 0), douta(7 downto 0) => douta(7 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity dll_img_ram_blk_mem_gen_v8_2_synth is port ( douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of dll_img_ram_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth"; end dll_img_ram_blk_mem_gen_v8_2_synth; architecture STRUCTURE of dll_img_ram_blk_mem_gen_v8_2_synth is begin \gnativebmg.native_blk_mem_gen\: entity work.dll_img_ram_blk_mem_gen_top port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(7 downto 0) => dina(7 downto 0), douta(7 downto 0) => douta(7 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity dll_img_ram_blk_mem_gen_v8_2 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 15 downto 0 ); sleep : in STD_LOGIC; deepsleep : in STD_LOGIC; shutdown : in STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of dll_img_ram_blk_mem_gen_v8_2 : entity is 16; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of dll_img_ram_blk_mem_gen_v8_2 : entity is 16; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of dll_img_ram_blk_mem_gen_v8_2 : entity is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of dll_img_ram_blk_mem_gen_v8_2 : entity is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of dll_img_ram_blk_mem_gen_v8_2 : entity is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of dll_img_ram_blk_mem_gen_v8_2 : entity is "0"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of dll_img_ram_blk_mem_gen_v8_2 : entity is "16"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of dll_img_ram_blk_mem_gen_v8_2 : entity is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of dll_img_ram_blk_mem_gen_v8_2 : entity is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of dll_img_ram_blk_mem_gen_v8_2 : entity is 1; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of dll_img_ram_blk_mem_gen_v8_2 : entity is 1; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of dll_img_ram_blk_mem_gen_v8_2 : entity is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of dll_img_ram_blk_mem_gen_v8_2 : entity is "Estimated Power for IP : 16.114201 mW"; attribute C_FAMILY : string; attribute C_FAMILY of dll_img_ram_blk_mem_gen_v8_2 : entity is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of dll_img_ram_blk_mem_gen_v8_2 : entity is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of dll_img_ram_blk_mem_gen_v8_2 : entity is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of dll_img_ram_blk_mem_gen_v8_2 : entity is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of dll_img_ram_blk_mem_gen_v8_2 : entity is "dll_img_ram.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of dll_img_ram_blk_mem_gen_v8_2 : entity is "no_coe_file_loaded"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of dll_img_ram_blk_mem_gen_v8_2 : entity is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 65536; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 65536; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 8; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 8; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of dll_img_ram_blk_mem_gen_v8_2 : entity is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of dll_img_ram_blk_mem_gen_v8_2 : entity is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of dll_img_ram_blk_mem_gen_v8_2 : entity is "NONE"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of dll_img_ram_blk_mem_gen_v8_2 : entity is 1; attribute C_USE_ECC : integer; attribute C_USE_ECC of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of dll_img_ram_blk_mem_gen_v8_2 : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of dll_img_ram_blk_mem_gen_v8_2 : entity is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of dll_img_ram_blk_mem_gen_v8_2 : entity is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 65536; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 65536; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of dll_img_ram_blk_mem_gen_v8_2 : entity is "NO_CHANGE"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of dll_img_ram_blk_mem_gen_v8_2 : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 8; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 8; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of dll_img_ram_blk_mem_gen_v8_2 : entity is "zynq"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of dll_img_ram_blk_mem_gen_v8_2 : entity is "blk_mem_gen_v8_2"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of dll_img_ram_blk_mem_gen_v8_2 : entity is "yes"; end dll_img_ram_blk_mem_gen_v8_2; architecture STRUCTURE of dll_img_ram_blk_mem_gen_v8_2 is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; doutb(7) <= \<const0>\; doutb(6) <= \<const0>\; doutb(5) <= \<const0>\; doutb(4) <= \<const0>\; doutb(3) <= \<const0>\; doutb(2) <= \<const0>\; doutb(1) <= \<const0>\; doutb(0) <= \<const0>\; rdaddrecc(15) <= \<const0>\; rdaddrecc(14) <= \<const0>\; rdaddrecc(13) <= \<const0>\; rdaddrecc(12) <= \<const0>\; rdaddrecc(11) <= \<const0>\; rdaddrecc(10) <= \<const0>\; rdaddrecc(9) <= \<const0>\; rdaddrecc(8) <= \<const0>\; rdaddrecc(7) <= \<const0>\; rdaddrecc(6) <= \<const0>\; rdaddrecc(5) <= \<const0>\; rdaddrecc(4) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(15) <= \<const0>\; s_axi_rdaddrecc(14) <= \<const0>\; s_axi_rdaddrecc(13) <= \<const0>\; s_axi_rdaddrecc(12) <= \<const0>\; s_axi_rdaddrecc(11) <= \<const0>\; s_axi_rdaddrecc(10) <= \<const0>\; s_axi_rdaddrecc(9) <= \<const0>\; s_axi_rdaddrecc(8) <= \<const0>\; s_axi_rdaddrecc(7) <= \<const0>\; s_axi_rdaddrecc(6) <= \<const0>\; s_axi_rdaddrecc(5) <= \<const0>\; s_axi_rdaddrecc(4) <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.dll_img_ram_blk_mem_gen_v8_2_synth port map ( addra(15 downto 0) => addra(15 downto 0), clka => clka, dina(7 downto 0) => dina(7 downto 0), douta(7 downto 0) => douta(7 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity dll_img_ram is port ( clka : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of dll_img_ram : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of dll_img_ram : entity is "dll_img_ram,blk_mem_gen_v8_2,{}"; attribute core_generation_info : string; attribute core_generation_info of dll_img_ram : entity is "dll_img_ram,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=0,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=dll_img_ram.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=65536,C_READ_DEPTH_A=65536,C_ADDRA_WIDTH=16,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=65536,C_READ_DEPTH_B=65536,C_ADDRB_WIDTH=16,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=NONE,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=1,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=1,C_COUNT_36K_BRAM=16,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 16.114201 mW}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of dll_img_ram : entity is "yes"; attribute x_core_info : string; attribute x_core_info of dll_img_ram : entity is "blk_mem_gen_v8_2,Vivado 2015.2"; end dll_img_ram; architecture STRUCTURE of dll_img_ram is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 16; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 16; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 0; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "0"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "16"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 1; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 1; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of U0 : label is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of U0 : label is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 16.114201 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "dll_img_ram.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 0; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 65536; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 65536; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 8; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 8; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "NONE"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 1; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 65536; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 65536; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "NO_CHANGE"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 8; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 8; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "zynq"; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of U0 : label is std.standard.true; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.dll_img_ram_blk_mem_gen_v8_2 port map ( addra(15 downto 0) => addra(15 downto 0), addrb(15) => '0', addrb(14) => '0', addrb(13) => '0', addrb(12) => '0', addrb(11) => '0', addrb(10) => '0', addrb(9) => '0', addrb(8) => '0', addrb(7) => '0', addrb(6) => '0', addrb(5) => '0', addrb(4) => '0', addrb(3) => '0', addrb(2) => '0', addrb(1) => '0', addrb(0) => '0', clka => clka, clkb => '0', dbiterr => NLW_U0_dbiterr_UNCONNECTED, deepsleep => '0', dina(7 downto 0) => dina(7 downto 0), dinb(7) => '0', dinb(6) => '0', dinb(5) => '0', dinb(4) => '0', dinb(3) => '0', dinb(2) => '0', dinb(1) => '0', dinb(0) => '0', douta(7 downto 0) => douta(7 downto 0), doutb(7 downto 0) => NLW_U0_doutb_UNCONNECTED(7 downto 0), eccpipece => '0', ena => ena, enb => '0', injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(15 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(15 downto 0), regcea => '0', regceb => '0', rsta => '0', rstb => '0', s_aclk => '0', s_aresetn => '0', s_axi_araddr(31) => '0', s_axi_araddr(30) => '0', s_axi_araddr(29) => '0', s_axi_araddr(28) => '0', s_axi_araddr(27) => '0', s_axi_araddr(26) => '0', s_axi_araddr(25) => '0', s_axi_araddr(24) => '0', s_axi_araddr(23) => '0', s_axi_araddr(22) => '0', s_axi_araddr(21) => '0', s_axi_araddr(20) => '0', s_axi_araddr(19) => '0', s_axi_araddr(18) => '0', s_axi_araddr(17) => '0', s_axi_araddr(16) => '0', s_axi_araddr(15) => '0', s_axi_araddr(14) => '0', s_axi_araddr(13) => '0', s_axi_araddr(12) => '0', s_axi_araddr(11) => '0', s_axi_araddr(10) => '0', s_axi_araddr(9) => '0', s_axi_araddr(8) => '0', s_axi_araddr(7) => '0', s_axi_araddr(6) => '0', s_axi_araddr(5) => '0', s_axi_araddr(4) => '0', s_axi_araddr(3) => '0', s_axi_araddr(2) => '0', s_axi_araddr(1) => '0', s_axi_araddr(0) => '0', s_axi_arburst(1) => '0', s_axi_arburst(0) => '0', s_axi_arid(3) => '0', s_axi_arid(2) => '0', s_axi_arid(1) => '0', s_axi_arid(0) => '0', s_axi_arlen(7) => '0', s_axi_arlen(6) => '0', s_axi_arlen(5) => '0', s_axi_arlen(4) => '0', s_axi_arlen(3) => '0', s_axi_arlen(2) => '0', s_axi_arlen(1) => '0', s_axi_arlen(0) => '0', s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2) => '0', s_axi_arsize(1) => '0', s_axi_arsize(0) => '0', s_axi_arvalid => '0', s_axi_awaddr(31) => '0', s_axi_awaddr(30) => '0', s_axi_awaddr(29) => '0', s_axi_awaddr(28) => '0', s_axi_awaddr(27) => '0', s_axi_awaddr(26) => '0', s_axi_awaddr(25) => '0', s_axi_awaddr(24) => '0', s_axi_awaddr(23) => '0', s_axi_awaddr(22) => '0', s_axi_awaddr(21) => '0', s_axi_awaddr(20) => '0', s_axi_awaddr(19) => '0', s_axi_awaddr(18) => '0', s_axi_awaddr(17) => '0', s_axi_awaddr(16) => '0', s_axi_awaddr(15) => '0', s_axi_awaddr(14) => '0', s_axi_awaddr(13) => '0', s_axi_awaddr(12) => '0', s_axi_awaddr(11) => '0', s_axi_awaddr(10) => '0', s_axi_awaddr(9) => '0', s_axi_awaddr(8) => '0', s_axi_awaddr(7) => '0', s_axi_awaddr(6) => '0', s_axi_awaddr(5) => '0', s_axi_awaddr(4) => '0', s_axi_awaddr(3) => '0', s_axi_awaddr(2) => '0', s_axi_awaddr(1) => '0', s_axi_awaddr(0) => '0', s_axi_awburst(1) => '0', s_axi_awburst(0) => '0', s_axi_awid(3) => '0', s_axi_awid(2) => '0', s_axi_awid(1) => '0', s_axi_awid(0) => '0', s_axi_awlen(7) => '0', s_axi_awlen(6) => '0', s_axi_awlen(5) => '0', s_axi_awlen(4) => '0', s_axi_awlen(3) => '0', s_axi_awlen(2) => '0', s_axi_awlen(1) => '0', s_axi_awlen(0) => '0', s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2) => '0', s_axi_awsize(1) => '0', s_axi_awsize(0) => '0', s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(15 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(15 downto 0), s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(7) => '0', s_axi_wdata(6) => '0', s_axi_wdata(5) => '0', s_axi_wdata(4) => '0', s_axi_wdata(3) => '0', s_axi_wdata(2) => '0', s_axi_wdata(1) => '0', s_axi_wdata(0) => '0', s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, shutdown => '0', sleep => '0', wea(0) => wea(0), web(0) => '0' ); end STRUCTURE;
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY reg_tb IS END reg_tb; ARCHITECTURE behavior OF reg_tb IS constant REG_WIDTH: integer := 16; -- Component Declaration for the Unit Under Test (UUT) COMPONENT reg GENERIC(WIDTH : integer := REG_WIDTH); PORT( I_clk : IN std_logic; I_reset : IN std_logic; I_dataIn : IN std_logic_vector(WIDTH-1 downto 0); O_dataOut : OUT std_logic_vector(WIDTH-1 downto 0) ); END COMPONENT; --Inputs signal I_clk : std_logic := '0'; signal I_reset : std_logic := '0'; signal I_dataIn : std_logic_vector(REG_WIDTH-1 downto 0) := (others => '0'); --Outputs signal O_dataOut : std_logic_vector(REG_WIDTH-1 downto 0); -- Clock period definitions constant I_clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: reg PORT MAP ( I_clk => I_clk, I_reset => I_reset, I_dataIn => I_dataIn, O_dataOut => O_dataOut ); -- Clock process definitions I_clk_process :process begin I_clk <= '0'; wait for I_clk_period/2; I_clk <= '1'; wait for I_clk_period/2; end process; -- Stimulus process stim_proc: process begin I_reset <= '1'; wait for I_clk_period; I_reset <= '0'; I_dataIn <= X"0010"; wait for I_clk_period; assert O_dataOut = X"0010" report "Wrong output." severity error; wait; end process; END;
library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity dk17_jed is port( clock: in std_logic; input: in std_logic_vector(1 downto 0); output: out std_logic_vector(2 downto 0) ); end dk17_jed; architecture behaviour of dk17_jed is constant s10000000: std_logic_vector(2 downto 0) := "010"; constant s01000000: std_logic_vector(2 downto 0) := "000"; constant s00100000: std_logic_vector(2 downto 0) := "100"; constant s00010000: std_logic_vector(2 downto 0) := "110"; constant s00001000: std_logic_vector(2 downto 0) := "101"; constant s00000100: std_logic_vector(2 downto 0) := "001"; constant s00000010: std_logic_vector(2 downto 0) := "111"; constant s00000001: std_logic_vector(2 downto 0) := "011"; signal current_state, next_state: std_logic_vector(2 downto 0); begin process(clock) begin if rising_edge(clock) then current_state <= next_state; end if; end process; process(input, current_state) begin next_state <= "---"; output <= "---"; case current_state is when s10000000 => if std_match(input, "00") then next_state <= s10000000; output <= "001"; elsif std_match(input, "01") then next_state <= s00010000; output <= "010"; elsif std_match(input, "10") then next_state <= s01000000; output <= "001"; elsif std_match(input, "11") then next_state <= s00001000; output <= "010"; end if; when s01000000 => if std_match(input, "00") then next_state <= s00100000; output <= "000"; elsif std_match(input, "01") then next_state <= s00010000; output <= "000"; elsif std_match(input, "10") then next_state <= s00100000; output <= "010"; elsif std_match(input, "11") then next_state <= s00000100; output <= "000"; end if; when s00100000 => if std_match(input, "00") then next_state <= s10000000; output <= "001"; elsif std_match(input, "01") then next_state <= s10000000; output <= "101"; elsif std_match(input, "10") then next_state <= s01000000; output <= "001"; elsif std_match(input, "11") then next_state <= s01000000; output <= "101"; end if; when s00010000 => if std_match(input, "00") then next_state <= s00010000; output <= "100"; elsif std_match(input, "01") then next_state <= s00001000; output <= "101"; elsif std_match(input, "10") then next_state <= s00010000; output <= "010"; elsif std_match(input, "11") then next_state <= s00001000; output <= "101"; end if; when s00001000 => if std_match(input, "00") then next_state <= s00100000; output <= "000"; elsif std_match(input, "01") then next_state <= s00010000; output <= "100"; elsif std_match(input, "10") then next_state <= s00100000; output <= "010"; elsif std_match(input, "11") then next_state <= s00100000; output <= "100"; end if; when s00000100 => if std_match(input, "00") then next_state <= s00000010; output <= "000"; elsif std_match(input, "01") then next_state <= s00000001; output <= "000"; elsif std_match(input, "10") then next_state <= s00100000; output <= "010"; elsif std_match(input, "11") then next_state <= s00100000; output <= "100"; end if; when s00000010 => if std_match(input, "00") then next_state <= s00010000; output <= "010"; elsif std_match(input, "01") then next_state <= s10000000; output <= "101"; elsif std_match(input, "10") then next_state <= s00001000; output <= "010"; elsif std_match(input, "11") then next_state <= s01000000; output <= "101"; end if; when s00000001 => if std_match(input, "00") then next_state <= s00010000; output <= "100"; elsif std_match(input, "01") then next_state <= s00001000; output <= "100"; elsif std_match(input, "10") then next_state <= s00100000; output <= "010"; elsif std_match(input, "11") then next_state <= s00100000; output <= "100"; end if; when others => next_state <= "---"; output <= "---"; end case; end process; end behaviour;
---------------------------------------------------------------------------------- -- Engineer: Mike Field <hamster@snap.net.nz> -- -- Module Name: udp_test_source - Behavioral -- -- Description: Generate a few UDP packets for testing. -- ------------------------------------------------------------------------------------ -- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver ------------------------------------------------------------------------------------ -- The MIT License (MIT) -- -- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz> -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. ------------------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity udp_test_source is Port ( clk : in STD_LOGIC; -- interface for data to be sent over UDP udp_tx_busy : in std_logic := '0'; udp_tx_valid : out std_logic := '0'; udp_tx_data : out std_logic_vector(7 downto 0) := (others => '0'); udp_tx_src_port : out std_logic_vector(15 downto 0) := (others => '0'); udp_tx_dst_mac : out std_logic_vector(47 downto 0) := (others => '0'); udp_tx_dst_ip : out std_logic_vector(31 downto 0) := (others => '0'); udp_tx_dst_port : out std_logic_vector(15 downto 0) := (others => '0')); end udp_test_source; architecture Behavioral of udp_test_source is type t_state is (waiting, armed, sending); signal state : t_state := waiting; signal countdown : unsigned(27 downto 0) := to_unsigned(1000,28); signal data_count : unsigned(7 downto 0) := to_unsigned(0,8); begin process(clk) begin if rising_edge(clk) then udp_tx_valid <= '0'; udp_tx_data <= (others => '0'); udp_tx_src_port <= (others => '0'); udp_tx_dst_mac <= (others => '0'); udp_tx_dst_ip <= (others => '0'); udp_tx_dst_port <= (others => '0'); case state is when waiting => udp_tx_valid <= '0'; if countdown = 0 then countdown <= to_unsigned(124_999_999,28); -- 1 packet per second -- countdown <= to_unsigned(499,24); state <= armed; else countdown <= countdown-1; end if; when armed => udp_tx_valid <= '0'; if udp_tx_busy = '0' then data_count <= (others => '0'); state <= sending; end if; when sending => -- Broadcast data from port 4660 to port 9029 on 10.0.0.255 udp_tx_valid <= '1'; udp_tx_src_port <= std_logic_vector(to_unsigned(4660,16)); udp_tx_dst_mac <= x"FF_FF_FF_FF_FF_FF"; udp_tx_dst_ip <= x"FF_00_00_0A"; udp_tx_dst_port <= std_logic_vector(to_unsigned(9029,16)); udp_tx_data <= std_logic_vector(data_count); data_count <= data_count + 1; if data_count = 2 then state <= waiting; end if; when others => state <= waiting; end case; end if; end process; end Behavioral;
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin -- federico.madotto (at) gmail.com -- coline.doebelin (at) gmail.com -- https://github.com/fmadotto/DS_bitcoin_miner -- sha256_pl_old.vhd is part of DS_bitcoin_miner. -- DS_bitcoin_miner is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- DS_bitcoin_miner is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. library ieee; use ieee.std_logic_1164.all; -- std_logic use ieee.numeric_std.all; -- to_integer() use work.axi_pkg.all; entity sha256_pl_old is port ( aclk : in std_logic; -- clock aresetn : in std_logic; -- asynchronous active low reset done : out std_logic; -- done signal -------------------------------- -- AXI lite slave port s0_axi -- -------------------------------- -- Inputs (master to slave) -- ------------------------------ -- Read address channel s0_axi_araddr: in std_logic_vector(29 downto 0); s0_axi_arprot: in std_logic_vector(2 downto 0); s0_axi_arvalid: in std_logic; -- Read data channel s0_axi_rready: in std_logic; -- Write address channel s0_axi_awaddr: in std_logic_vector(29 downto 0); s0_axi_awprot: in std_logic_vector(2 downto 0); s0_axi_awvalid: in std_logic; -- Write data channel s0_axi_wdata: in std_logic_vector(31 downto 0); s0_axi_wstrb: in std_logic_vector(3 downto 0); s0_axi_wvalid: in std_logic; -- Write response channel s0_axi_bready: in std_logic; ------------------------------- -- Outputs (slave to master) -- ------------------------------- -- Read address channel s0_axi_arready: out std_logic; -- Read data channel s0_axi_rdata: out std_logic_vector(31 downto 0); s0_axi_rresp: out std_logic_vector(1 downto 0); s0_axi_rvalid: out std_logic; -- Write address channel s0_axi_awready: out std_logic; -- Write data channel s0_axi_wready: out std_logic; -- Write response channel s0_axi_bresp: out std_logic_vector(1 downto 0); s0_axi_bvalid: out std_logic ); end entity sha256_pl_old; architecture rtl of sha256_pl_old is -- Or reduction of std_ulogic_vector function or_reduce(v: std_ulogic_vector) return std_ulogic is variable tmp: std_ulogic_vector(v'length - 1 downto 0) := v; begin if tmp'length = 0 then return '0'; elsif tmp'length = 1 then return tmp(0); else return or_reduce(tmp(tmp'length - 1 downto tmp'length / 2)) or or_reduce(tmp(tmp'length / 2 - 1 downto 0)); end if; end function or_reduce; -- signals -- Record versions of AXI signals signal s0_axi_m2s : axilite_gp_m2s; signal s0_axi_s2m : axilite_gp_s2m; -- STATUS register signal status : std_ulogic_vector(31 downto 0); -- M_j_memory signal M_j_memory_wcs_n_in, M_j_memory_we_n_in : std_ulogic; signal M_j_memory_w_addr_in : std_ulogic_vector(3 downto 0); signal M_j_memory_data_in : std_ulogic_vector(31 downto 0); signal M_j_memory_data_out : std_ulogic_vector(31 downto 0); -- start_FF signal start_FF_start_in : std_ulogic; signal start_FF_start_out : std_ulogic; -- control_unit signal cu_exp_sel1_delayed_out : std_ulogic; signal cu_com_sel1_delayed_out : std_ulogic; signal cu_M_j_memory_rcs_n_out : std_ulogic; signal cu_M_j_memory_r_addr_out : std_ulogic_vector(3 downto 0); signal cu_reg_H_minus_1_en_out : std_ulogic; signal cu_reg_H_minus_1_sel_out : std_ulogic; signal cu_K_j_init_out : std_ulogic; -- K_j_constants signal K_j_constants_out : std_ulogic_vector(31 downto 0); -- data_path signal dp_H_i_A_out, dp_H_i_B_out, dp_H_i_C_out, dp_H_i_D_out, dp_H_i_E_out, dp_H_i_F_out, dp_H_i_G_out, dp_H_i_H_out : std_ulogic_vector(31 downto 0); -- reg_H_minus_1 signal reg_H_iminus1_A_out, reg_H_iminus1_B_out, reg_H_iminus1_C_out, reg_H_iminus1_D_out, reg_H_iminus1_E_out, reg_H_iminus1_F_out, reg_H_iminus1_G_out, reg_H_iminus1_H_out : std_ulogic_vector(31 downto 0); begin pl_M_j_memory1 : entity work.M_j_memory generic map ( row_size => 32, address_size => 4 ) port map ( clk => aclk, rcs_n => cu_M_j_memory_rcs_n_out, wcs_n => M_j_memory_wcs_n_in, we_n => M_j_memory_we_n_in, r_addr => cu_M_j_memory_r_addr_out, w_addr => M_j_memory_w_addr_in, data_in => M_j_memory_data_in, data_out => M_j_memory_data_out ); pl_start_FF1 : entity work.start_FF port map ( clk => aclk, d => start_FF_start_in, start => start_FF_start_out ); pl_control_unit1 : entity work.control_unit port map ( clk => aclk, rstn => aresetn, start => start_FF_start_out, done => done, -- data path ports exp_sel1_delayed => cu_exp_sel1_delayed_out, com_sel1_delayed => cu_com_sel1_delayed_out, -- M_j_memory ports M_j_memory_rcs_n => cu_M_j_memory_rcs_n_out, M_j_memory_r_addr => cu_M_j_memory_r_addr_out, -- reg_H_minus_1 ports reg_H_minus_1_en => cu_reg_H_minus_1_en_out, reg_H_minus_1_sel => cu_reg_H_minus_1_sel_out, -- K_j_constants ports K_j_init => cu_K_j_init_out ); pl_K_j_constants1 : entity work.K_j_constants port map ( clk => aclk, rstn => aresetn, K_j_init => cu_K_j_init_out, K_j => K_j_constants_out ); pl_reg_H_minus_11 : entity work.reg_H_minus_1 port map ( clk => aclk, rstn => aresetn, reg_H_minus_1_en => cu_reg_H_minus_1_en_out, reg_H_minus_1_sel => cu_reg_H_minus_1_sel_out, H_i_A => dp_H_i_A_out, H_i_B => dp_H_i_B_out, H_i_C => dp_H_i_C_out, H_i_D => dp_H_i_D_out, H_i_E => dp_H_i_E_out, H_i_F => dp_H_i_F_out, H_i_G => dp_H_i_G_out, H_i_H => dp_H_i_H_out, H_iminus1_A => reg_H_iminus1_A_out, H_iminus1_B => reg_H_iminus1_B_out, H_iminus1_C => reg_H_iminus1_C_out, H_iminus1_D => reg_H_iminus1_D_out, H_iminus1_E => reg_H_iminus1_E_out, H_iminus1_F => reg_H_iminus1_F_out, H_iminus1_G => reg_H_iminus1_G_out, H_iminus1_H => reg_H_iminus1_H_out ); pl_data_path1 : entity work.data_path port map ( -- common ports clk => aclk, rstn => aresetn, -- expander input ports exp_sel1 => cu_exp_sel1_delayed_out, M_i_j => M_j_memory_data_out, -- compressor input ports com_sel1 => cu_com_sel1_delayed_out, K_j => K_j_constants_out, H_iminus1_A => reg_H_iminus1_A_out, H_iminus1_B => reg_H_iminus1_B_out, H_iminus1_C => reg_H_iminus1_C_out, H_iminus1_D => reg_H_iminus1_D_out, H_iminus1_E => reg_H_iminus1_E_out, H_iminus1_F => reg_H_iminus1_F_out, H_iminus1_G => reg_H_iminus1_G_out, H_iminus1_H => reg_H_iminus1_H_out, -- output ports H_i_A => dp_H_i_A_out, H_i_B => dp_H_i_B_out, H_i_C => dp_H_i_C_out, H_i_D => dp_H_i_D_out, H_i_E => dp_H_i_E_out, H_i_F => dp_H_i_F_out, H_i_G => dp_H_i_G_out, H_i_H => dp_H_i_H_out ); -- S0_AXI read-write requests s0_axi_pr: process(aclk, aresetn) -- idle: waiting for AXI master requests: when receiving write address and data valid (higher priority than read), perform the write, assert write address -- ready, write data ready and bvalid, go to w1, else, when receiving address read valid, perform the read, assert read address ready, read data valid -- and go to r1 -- w1: deassert write address ready and write data ready, wait for write response ready: when receiving it, deassert write response valid, go to idle -- r1: deassert read address ready, wait for read response ready: when receiving it, deassert read data valid, go to idle type state_type is (idle, w1, r1); variable state: state_type; begin if aresetn = '0' then s0_axi_s2m <= (rdata => (others => '0'), rresp => axi_resp_okay, bresp => axi_resp_okay, others => '0'); M_j_memory_wcs_n_in <= '1'; M_j_memory_we_n_in <= '1'; start_FF_start_in <= '0'; state := idle; elsif aclk'event and aclk = '1' then -- s0_axi write and read case state is when idle => if s0_axi_m2s.awvalid = '1' and s0_axi_m2s.wvalid = '1' then -- Write address and data if or_reduce(s0_axi_m2s.awaddr(31 downto 7)) /= '0' then -- If unmapped address s0_axi_s2m.bresp <= axi_resp_decerr; elsif s0_axi_m2s.awaddr(7 downto 0) = x"00" or s0_axi_m2s.awaddr(7 downto 0) > x"44" then -- If read-only status register or H_(i-1) s0_axi_s2m.bresp <= axi_resp_slverr; else s0_axi_s2m.bresp <= axi_resp_okay; if s0_axi_m2s.awaddr(7 downto 0) >= x"04" and s0_axi_m2s.awaddr(7 downto 0) < x"44" then -- If M_j memory for i in 0 to 3 loop if s0_axi_m2s.wstrb(i) = '1' then M_j_memory_data_in(8 * i + 7 downto 8 * i) <= s0_axi_m2s.wdata(8 * i + 7 downto 8 * i); end if; end loop; -- every row in the memory can contain 32 bits, while the input address refers to byte: -- it is first divided by 4 (i.e. 2-bit right shift), then 1 is subtracted (the first address is the status register) -- then it is converted back to a ulogic_vector M_j_memory_w_addr_in <= std_ulogic_vector(to_unsigned((to_integer(unsigned("00" & s0_axi_m2s.awaddr(7 downto 2))) - 1), 4)); M_j_memory_wcs_n_in <= '0'; M_j_memory_we_n_in <= '0'; elsif s0_axi_m2s.awaddr(7 downto 0) = x"44" then -- start command start_FF_start_in <= '1'; end if; end if; s0_axi_s2m.awready <= '1'; s0_axi_s2m.wready <= '1'; s0_axi_s2m.bvalid <= '1'; state := w1; elsif s0_axi_m2s.arvalid = '1' then if or_reduce(s0_axi_m2s.araddr(31 downto 7)) /= '0' then -- If unmapped address s0_axi_s2m.rdata <= (others => '0'); s0_axi_s2m.rresp <= axi_resp_decerr; elsif s0_axi_m2s.araddr(7 downto 0) > x"00" and s0_axi_m2s.araddr(7 downto 0) <= x"44" then -- If write-only Mj or start s0_axi_s2m.rresp <= axi_resp_slverr; else s0_axi_s2m.rresp <= axi_resp_okay; case s0_axi_m2s.araddr(7 downto 0) is when x"00" => -- status register s0_axi_s2m.rdata <= status; -- H(i-1) when x"48" => s0_axi_s2m.rdata <= reg_H_iminus1_A_out; when x"4c" => s0_axi_s2m.rdata <= reg_H_iminus1_B_out; when x"50" => s0_axi_s2m.rdata <= reg_H_iminus1_C_out; when x"54" => s0_axi_s2m.rdata <= reg_H_iminus1_D_out; when x"58" => s0_axi_s2m.rdata <= reg_H_iminus1_E_out; when x"5c" => s0_axi_s2m.rdata <= reg_H_iminus1_F_out; when x"60" => s0_axi_s2m.rdata <= reg_H_iminus1_G_out; when x"64" => s0_axi_s2m.rdata <= reg_H_iminus1_H_out; when others => s0_axi_s2m.rdata <= x"00000000"; end case; end if; s0_axi_s2m.arready <= '1'; s0_axi_s2m.rvalid <= '1'; state := r1; end if; when w1 => s0_axi_s2m.awready <= '0'; s0_axi_s2m.wready <= '0'; M_j_memory_wcs_n_in <= '1'; M_j_memory_we_n_in <= '1'; start_FF_start_in <= '0'; if s0_axi_m2s.bready = '1' then s0_axi_s2m.bvalid <= '0'; state := idle; end if; when r1 => s0_axi_s2m.arready <= '0'; if s0_axi_m2s.rready = '1' then s0_axi_s2m.rvalid <= '0'; state := idle; end if; end case; end if; end process s0_axi_pr; -- Record types to flat signals s0_axi_m2s.araddr <= std_ulogic_vector("00" & s0_axi_araddr); s0_axi_m2s.arprot <= std_ulogic_vector(s0_axi_arprot); s0_axi_m2s.arvalid <= s0_axi_arvalid; s0_axi_m2s.rready <= s0_axi_rready; s0_axi_m2s.awaddr <= std_ulogic_vector("00" & s0_axi_awaddr); s0_axi_m2s.awprot <= std_ulogic_vector(s0_axi_awprot); s0_axi_m2s.awvalid <= s0_axi_awvalid; s0_axi_m2s.wdata <= std_ulogic_vector(s0_axi_wdata); s0_axi_m2s.wstrb <= std_ulogic_vector(s0_axi_wstrb); s0_axi_m2s.wvalid <= s0_axi_wvalid; s0_axi_m2s.bready <= s0_axi_bready; s0_axi_arready <= s0_axi_s2m.arready; s0_axi_rdata <= std_logic_vector(s0_axi_s2m.rdata); s0_axi_rresp <= std_logic_vector(s0_axi_s2m.rresp); s0_axi_rvalid <= s0_axi_s2m.rvalid; s0_axi_awready <= s0_axi_s2m.awready; s0_axi_wready <= s0_axi_s2m.wready; s0_axi_bvalid <= s0_axi_s2m.bvalid; s0_axi_bresp <= std_logic_vector(s0_axi_s2m.bresp); status <= x"aabbccdd"; end architecture rtl;
-- The original source comes from: -- http://ghdl.free.fr/ghdl/A-full-adder.html entity adder is -- i0, i1 and the carry-in ci are inputs of the adder. -- s is the sum output, co is the carry-out. port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); end adder; architecture rtl of adder is begin -- This full-adder architecture contains two concurrent assignment. -- Compute the sum. s <= i0 xor i1 xor ci; co <= (i0 and i1) or (i0 and ci) or (i1 and ci); end rtl;
------------------------------------------------------------------------------- -- Title : HPI MEMORY -- Project : LEON3MINI ------------------------------------------------------------------------------- -- $Id: $ ------------------------------------------------------------------------------- -- Author : Thomas Ameseder -- Company : Gleichmann Electronics -- Created : 2005-08-19 -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: -- -- This module is for testing the AHB2HPI(2) core. It is a memory that -- can be connected to the HPI interface. Also features HPI timing -- checks. ------------------------------------------------------------------------------- -- Copyright (c) 2005 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; entity hpi_ram is generic (abits : integer := 9; dbits : integer := 16); port ( clk : in std_ulogic; address : in std_logic_vector(1 downto 0); datain : in std_logic_vector(dbits-1 downto 0); dataout : out std_logic_vector(dbits-1 downto 0); writen : in std_ulogic; readn : in std_ulogic; csn : in std_ulogic ); end; architecture behavioral of hpi_ram is constant Tcyc : time := 40000 ps; -- cycle time type mem is array(0 to (2**abits -1)) of std_logic_vector((dbits -1) downto 0); signal memarr : mem; signal data_reg, -- "00" mailbox_reg, -- "01" address_reg, -- "10" status_reg -- "11" : std_logic_vector(dbits-1 downto 0); begin write : process(clk) begin if rising_edge(clk) then if csn = '0' then if writen = '0' then case address(1 downto 0) is when "00" => memarr(conv_integer(address_reg(abits-1 downto 1))) <= datain; when "01" => mailbox_reg <= datain; when "10" => address_reg <= datain; when "11" => status_reg <= datain; when others => null; end case; end if; end if; end if; end process; read : process(address, address_reg, csn, mailbox_reg, memarr, readn, status_reg) constant Tacc : time := Tcyc; -- data access time begin if (readn = '0' and csn = '0') then case address(1 downto 0) is when "00" => dataout <= memarr(conv_integer(address_reg(abits-1 downto 1))) after Tacc; when "01" => dataout <= mailbox_reg after Tacc; when "10" => dataout <= address_reg after Tacc; when "11" => dataout <= status_reg after Tacc; when others => null; end case; else -- the rest of the time, invalid data shall be driven -- (note: makes an 'X' when being resolved on a high-impedance bus) dataout <= (others => 'Z'); end if; end process; -- pragma translate_off --------------------------------------------------------------------------------------- -- HPI TIMING CHECKS --------------------------------------------------------------------------------------- cycle_timing_check : process(datain, readn, writen) constant Tcycmin : time := 6 * Tcyc; -- minimum write/read cycle time constant Tpulsemin : time := 2 * Tcyc; -- minimum write/read pulse time constant Twdatasu : time := 6 ns; -- write data setup time constant Twdatahold : time := 2 ns; -- write data hold time variable wrlastev, rdlastev : time := 0 ps; variable wrlowlastev, rdlowlastev : time := 0 ps; variable wdatalastev : time := 0 ps; -- write data last event variable wrhighlastev : time := 0 ps; begin -- write data hold check if datain'event then assert (now = 0 ps) or (now - wrhighlastev >= Twdatahold) report "Write data hold violation!" severity error; wdatalastev := now; end if; -- exclusive read or write check assert writen = '1' or readn = '1' report "Both read and write are signals are low!" severity error; -- write cycle time and write pulse width checks if writen'event then if writen = '0' then assert (now = 0 ps) or (now - wrlowlastev >= Tcycmin) report "Write cycle time violation!" severity error; wrlowlastev := now; wrlastev := now; elsif writen = '1' then assert (now = 0 ps) or (now - wrlastev >= Tpulsemin) report "Write pulse width violation!" severity error; assert (now = 0 ps) or (now - wdatalastev >= Twdatasu) report "Write data setup violation!" severity error; wrhighlastev := now; wrlastev := now; end if; end if; -- read cycle time and read pulse width checks if readn'event then if readn = '0' then assert (now = 0 ps) or (now - rdlowlastev >= Tcycmin) report "Read cycle time violation!" severity error; rdlowlastev := now; rdlastev := now; elsif readn = '1' then assert (now = 0 ps) or (now - rdlastev >= Tpulsemin) report "Read pulse width violation!" severity error; rdlastev := now; end if; end if; end process cycle_timing_check; -- pragma translate_on end architecture;
------------------------------------------------------------------------------- -- Title : HPI MEMORY -- Project : LEON3MINI ------------------------------------------------------------------------------- -- $Id: $ ------------------------------------------------------------------------------- -- Author : Thomas Ameseder -- Company : Gleichmann Electronics -- Created : 2005-08-19 -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: -- -- This module is for testing the AHB2HPI(2) core. It is a memory that -- can be connected to the HPI interface. Also features HPI timing -- checks. ------------------------------------------------------------------------------- -- Copyright (c) 2005 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; entity hpi_ram is generic (abits : integer := 9; dbits : integer := 16); port ( clk : in std_ulogic; address : in std_logic_vector(1 downto 0); datain : in std_logic_vector(dbits-1 downto 0); dataout : out std_logic_vector(dbits-1 downto 0); writen : in std_ulogic; readn : in std_ulogic; csn : in std_ulogic ); end; architecture behavioral of hpi_ram is constant Tcyc : time := 40000 ps; -- cycle time type mem is array(0 to (2**abits -1)) of std_logic_vector((dbits -1) downto 0); signal memarr : mem; signal data_reg, -- "00" mailbox_reg, -- "01" address_reg, -- "10" status_reg -- "11" : std_logic_vector(dbits-1 downto 0); begin write : process(clk) begin if rising_edge(clk) then if csn = '0' then if writen = '0' then case address(1 downto 0) is when "00" => memarr(conv_integer(address_reg(abits-1 downto 1))) <= datain; when "01" => mailbox_reg <= datain; when "10" => address_reg <= datain; when "11" => status_reg <= datain; when others => null; end case; end if; end if; end if; end process; read : process(address, address_reg, csn, mailbox_reg, memarr, readn, status_reg) constant Tacc : time := Tcyc; -- data access time begin if (readn = '0' and csn = '0') then case address(1 downto 0) is when "00" => dataout <= memarr(conv_integer(address_reg(abits-1 downto 1))) after Tacc; when "01" => dataout <= mailbox_reg after Tacc; when "10" => dataout <= address_reg after Tacc; when "11" => dataout <= status_reg after Tacc; when others => null; end case; else -- the rest of the time, invalid data shall be driven -- (note: makes an 'X' when being resolved on a high-impedance bus) dataout <= (others => 'Z'); end if; end process; -- pragma translate_off --------------------------------------------------------------------------------------- -- HPI TIMING CHECKS --------------------------------------------------------------------------------------- cycle_timing_check : process(datain, readn, writen) constant Tcycmin : time := 6 * Tcyc; -- minimum write/read cycle time constant Tpulsemin : time := 2 * Tcyc; -- minimum write/read pulse time constant Twdatasu : time := 6 ns; -- write data setup time constant Twdatahold : time := 2 ns; -- write data hold time variable wrlastev, rdlastev : time := 0 ps; variable wrlowlastev, rdlowlastev : time := 0 ps; variable wdatalastev : time := 0 ps; -- write data last event variable wrhighlastev : time := 0 ps; begin -- write data hold check if datain'event then assert (now = 0 ps) or (now - wrhighlastev >= Twdatahold) report "Write data hold violation!" severity error; wdatalastev := now; end if; -- exclusive read or write check assert writen = '1' or readn = '1' report "Both read and write are signals are low!" severity error; -- write cycle time and write pulse width checks if writen'event then if writen = '0' then assert (now = 0 ps) or (now - wrlowlastev >= Tcycmin) report "Write cycle time violation!" severity error; wrlowlastev := now; wrlastev := now; elsif writen = '1' then assert (now = 0 ps) or (now - wrlastev >= Tpulsemin) report "Write pulse width violation!" severity error; assert (now = 0 ps) or (now - wdatalastev >= Twdatasu) report "Write data setup violation!" severity error; wrhighlastev := now; wrlastev := now; end if; end if; -- read cycle time and read pulse width checks if readn'event then if readn = '0' then assert (now = 0 ps) or (now - rdlowlastev >= Tcycmin) report "Read cycle time violation!" severity error; rdlowlastev := now; rdlastev := now; elsif readn = '1' then assert (now = 0 ps) or (now - rdlastev >= Tpulsemin) report "Read pulse width violation!" severity error; rdlastev := now; end if; end if; end process cycle_timing_check; -- pragma translate_on end architecture;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:12:06 10/06/2010 -- Design Name: -- Module Name: Cont0a3 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Cont0a3 is port ( Enable : in STD_LOGIC; Rst : in STD_LOGIC; Clk : in STD_LOGIC; Cuenta : out STD_LOGIC_VECTOR (1 downto 0)); end Cont0a3; architecture Behavioral of Cont0a3 is signal Cont : STD_LOGIC_VECTOR (1 downto 0); begin --Contador de 0 a 3 para seleccionar Display y sigito de Tiempo process (Rst, Clk, Enable,Cont) begin if Rst = '1' then Cont <= (others => '0'); elsif (rising_edge(Clk) and Enable = '1') then Cont <= Cont + 1; end if; Cuenta <= Cont; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:12:06 10/06/2010 -- Design Name: -- Module Name: Cont0a3 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Cont0a3 is port ( Enable : in STD_LOGIC; Rst : in STD_LOGIC; Clk : in STD_LOGIC; Cuenta : out STD_LOGIC_VECTOR (1 downto 0)); end Cont0a3; architecture Behavioral of Cont0a3 is signal Cont : STD_LOGIC_VECTOR (1 downto 0); begin --Contador de 0 a 3 para seleccionar Display y sigito de Tiempo process (Rst, Clk, Enable,Cont) begin if Rst = '1' then Cont <= (others => '0'); elsif (rising_edge(Clk) and Enable = '1') then Cont <= Cont + 1; end if; Cuenta <= Cont; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:12:06 10/06/2010 -- Design Name: -- Module Name: Cont0a3 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Cont0a3 is port ( Enable : in STD_LOGIC; Rst : in STD_LOGIC; Clk : in STD_LOGIC; Cuenta : out STD_LOGIC_VECTOR (1 downto 0)); end Cont0a3; architecture Behavioral of Cont0a3 is signal Cont : STD_LOGIC_VECTOR (1 downto 0); begin --Contador de 0 a 3 para seleccionar Display y sigito de Tiempo process (Rst, Clk, Enable,Cont) begin if Rst = '1' then Cont <= (others => '0'); elsif (rising_edge(Clk) and Enable = '1') then Cont <= Cont + 1; end if; Cuenta <= Cont; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:12:06 10/06/2010 -- Design Name: -- Module Name: Cont0a3 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Cont0a3 is port ( Enable : in STD_LOGIC; Rst : in STD_LOGIC; Clk : in STD_LOGIC; Cuenta : out STD_LOGIC_VECTOR (1 downto 0)); end Cont0a3; architecture Behavioral of Cont0a3 is signal Cont : STD_LOGIC_VECTOR (1 downto 0); begin --Contador de 0 a 3 para seleccionar Display y sigito de Tiempo process (Rst, Clk, Enable,Cont) begin if Rst = '1' then Cont <= (others => '0'); elsif (rising_edge(Clk) and Enable = '1') then Cont <= Cont + 1; end if; Cuenta <= Cont; end process; end Behavioral;
entity access7 is end entity; architecture test of access7 is type int_ptr is access integer; type int_ptr_ptr is access int_ptr; type int_ptr_array is array (integer range <>) of int_ptr; type int_ptr_array_ptr is access int_ptr_array; procedure alloc_ptr(x : out int_ptr_ptr) is begin x := new int_ptr; end procedure; procedure alloc_ptr_array(x : out int_ptr_array_ptr) is begin x := new int_ptr_array(1 to 3); end procedure; begin process is variable pp : int_ptr_ptr; variable pa : int_ptr_array_ptr; begin alloc_ptr(pp); assert pp.all = null; pp.all := new integer'(4); assert pp.all.all = 4; alloc_ptr_array(pa); assert pa.all = (null, null, null); pa(1) := new integer'(6); assert pa(1).all = 6; wait; end process; end architecture;
entity access7 is end entity; architecture test of access7 is type int_ptr is access integer; type int_ptr_ptr is access int_ptr; type int_ptr_array is array (integer range <>) of int_ptr; type int_ptr_array_ptr is access int_ptr_array; procedure alloc_ptr(x : out int_ptr_ptr) is begin x := new int_ptr; end procedure; procedure alloc_ptr_array(x : out int_ptr_array_ptr) is begin x := new int_ptr_array(1 to 3); end procedure; begin process is variable pp : int_ptr_ptr; variable pa : int_ptr_array_ptr; begin alloc_ptr(pp); assert pp.all = null; pp.all := new integer'(4); assert pp.all.all = 4; alloc_ptr_array(pa); assert pa.all = (null, null, null); pa(1) := new integer'(6); assert pa(1).all = 6; wait; end process; end architecture;
entity access7 is end entity; architecture test of access7 is type int_ptr is access integer; type int_ptr_ptr is access int_ptr; type int_ptr_array is array (integer range <>) of int_ptr; type int_ptr_array_ptr is access int_ptr_array; procedure alloc_ptr(x : out int_ptr_ptr) is begin x := new int_ptr; end procedure; procedure alloc_ptr_array(x : out int_ptr_array_ptr) is begin x := new int_ptr_array(1 to 3); end procedure; begin process is variable pp : int_ptr_ptr; variable pa : int_ptr_array_ptr; begin alloc_ptr(pp); assert pp.all = null; pp.all := new integer'(4); assert pp.all.all = 4; alloc_ptr_array(pa); assert pa.all = (null, null, null); pa(1) := new integer'(6); assert pa(1).all = 6; wait; end process; end architecture;
entity access7 is end entity; architecture test of access7 is type int_ptr is access integer; type int_ptr_ptr is access int_ptr; type int_ptr_array is array (integer range <>) of int_ptr; type int_ptr_array_ptr is access int_ptr_array; procedure alloc_ptr(x : out int_ptr_ptr) is begin x := new int_ptr; end procedure; procedure alloc_ptr_array(x : out int_ptr_array_ptr) is begin x := new int_ptr_array(1 to 3); end procedure; begin process is variable pp : int_ptr_ptr; variable pa : int_ptr_array_ptr; begin alloc_ptr(pp); assert pp.all = null; pp.all := new integer'(4); assert pp.all.all = 4; alloc_ptr_array(pa); assert pa.all = (null, null, null); pa(1) := new integer'(6); assert pa(1).all = 6; wait; end process; end architecture;
-- ----------------------------------------------------------------------- -- -- Company: INVEA-TECH a.s. -- -- Project: IPFIX design -- -- ----------------------------------------------------------------------- -- -- (c) Copyright 2011 INVEA-TECH a.s. -- All rights reserved. -- -- Please review the terms of the license agreement before using this -- file. If you are not an authorized user, please destroy this -- source code file and notify INVEA-TECH a.s. immediately that you -- inadvertently received an unauthorized copy. -- -- ----------------------------------------------------------------------- -- -- combov2_user_const.vhd: User constants for NetCOPE on ComboV2 -- Copyright (C) 2008 CESNET -- Author(s): Viktor Pus <pus@liberouter.org> -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in -- the documentation and/or other materials provided with the -- distribution. -- 3. Neither the name of the Company nor the names of its contributors -- may be used to endorse or promote products derived from this -- software without specific prior written permission. -- -- This software is provided ``as is'', and any express or implied -- warranties, including, but not limited to, the implied warranties of -- merchantability and fitness for a particular purpose are disclaimed. -- In no event shall the company or contributors be liable for any -- direct, indirect, incidental, special, exemplary, or consequential -- damages (including, but not limited to, procurement of substitute -- goods or services; loss of use, data, or profits; or business -- interruption) however caused and on any theory of liability, whether -- in contract, strict liability, or tort (including negligence or -- otherwise) arising in any way out of the use of this software, even -- if advised of the possibility of such damage. -- -- $Id$ -- library IEEE; use IEEE.std_logic_1164.all; package combov2_user_const is -- ------------------------------------------------------------------------- -- constant PCIE_EP_IFC_125 : boolean := true;-- true=125 MHz endpoint, false=250 MHz -- now this is obsolete -- ------------------------------------------------------------------------- -- Clock frequencies setting -- ------------------------------------------------------------------------- constant CLK_MULT : integer := 9; -- Fvco = 62.5 MHz x CLK_MULT constant CLK_ICS_DIV : integer := 3; -- CLK_ICS freq. = Fvco / CLK_ICS_DIV constant CLK_USER0_DIV : integer := 5; -- CLK_USER0 freq. = Fvco / CLK_USER0_DIV constant CLK_USER1_DIV : integer := 5; -- CLK_USER1 freq. = Fvco / CLK_USER1_DIV constant CLK_USER2_DIV : integer := 5; -- CLK_USER2 freq. = Fvco / CLK_USER2_DIV constant CLK_USER3_DIV : integer := 5; -- CLK_USER3 freq. = Fvco / CLK_USER3_DIV constant CLK_USER4_DIV : integer := 5; -- CLK_USER4 freq. = Fvco / CLK_USER4_DIV -- ------------------------------------------------------------------------- -- Design identification --------------------------------------------------- constant ID_PROJECT : std_logic_vector( 15 downto 0):= X"F101"; constant ID_SW_MAJOR : std_logic_vector( 7 downto 0):= X"03"; constant ID_SW_MINOR : std_logic_vector( 7 downto 0):= X"0C"; constant ID_HW_MAJOR : std_logic_vector( 15 downto 0):= X"0007"; constant ID_HW_MINOR : std_logic_vector( 15 downto 0):= X"0000"; -- F l e x i b l e _ F l o w M o n\0 constant ID_PROJECT_TEXT : std_logic_vector(255 downto 0) := X"466C657869626C655F466C6F774D6F6E00000000000000000000000000000000"; constant ID_TX_CHANNELS : std_logic_vector( 7 downto 0):= X"00"; constant ID_RX_CHANNELS : std_logic_vector( 7 downto 0):= X"08"; -- ------------------------------------------------------------------------- -- Network Module setting (constant INBANDFCS) is done in NetCOPE's network module -- ------------------------------------------------------------------------- -- DMA Module setting -- straight zero copy DMA - Non-generic version -- constant DMA_TYPE : String := "SZE"; -- straight zero copy DMA - Generic version constant DMA_TYPE : String := "GEN"; -- packet DMA through linux kernel stack -- constant DMA_TYPE : String := "PAC"; -- ------------------------------------------------------------------------- -- Timestamp unit setting -- Set to false if you don't need timestamps -- Synchronize your choice with ../top/combov2/Makefile (USE_TIMESTAMP) constant TIMESTAMP_UNIT : boolean := true; -- constant TIMESTAMP_UNIT : boolean := false; -- ------------------------------------------------------------------------- -- Support for JUMBO packets -- (un)comment all three lines together -- Synchronize your choice with ../top/combov2/Makefile (JUMBO) constant JUMBO : boolean := true; constant MAX_MTU_RX : std_logic_vector(31 downto 0) := X"00003FE0"; constant MAX_MTU_TX : std_logic_vector(31 downto 0) := X"00003FE0"; -- constant JUMBO : boolean := false; -- constant MAX_MTU_RX : std_logic_vector(31 downto 0) := X"00000FE0"; -- constant MAX_MTU_TX : std_logic_vector(31 downto 0) := X"00000FE0"; end combov2_user_const; package body combov2_user_const is end combov2_user_const;
---------------------------------------------------------------------- -- myPllOsc50m (myPllOsc50m4.vhd) ---------------------------------------------------------------------- -- (C) 2016 by Anton Mause -- -- Instantiate G4 1 MHz OnChip RC Oscillator and use PLL to get 50 MHz -- -- !!Watch Out!! Think twice where the OnChip Oscillator can be used. -- The datasheet allows it to be up to 6% off, beside having 1% typ. -- In real world you face silicon, power and temperature variations. -- -- See below for PLL lock (wide/default/narrow), can be used to -- verify quality of power supply and pcb layout. -- ---------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library smartfusion2; use smartfusion2.all; ---------------------------------------------------------------------- entity myPllOsc50m is port ( o_clk : OUT std_logic; o_rst_n : OUT std_logic ); end myPllOsc50m; ---------------------------------------------------------------------- architecture DEF_ARCH of myPllOsc50m is component RCOSC_1MHZ port( CLKOUT : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; component CCC generic (INIT:std_logic_vector(209 downto 0) := "00" & x"0000000000000000000000000000000000000000000000000000"; VCOFREQUENCY:real := 0.0); port( Y0 : out std_logic; Y1 : out std_logic; Y2 : out std_logic; Y3 : out std_logic; PRDATA : out std_logic_vector(7 downto 0); LOCK : out std_logic; BUSY : out std_logic; CLK0 : in std_logic := 'U'; CLK1 : in std_logic := 'U'; CLK2 : in std_logic := 'U'; CLK3 : in std_logic := 'U'; NGMUX0_SEL : in std_logic := 'U'; NGMUX1_SEL : in std_logic := 'U'; NGMUX2_SEL : in std_logic := 'U'; NGMUX3_SEL : in std_logic := 'U'; NGMUX0_HOLD_N : in std_logic := 'U'; NGMUX1_HOLD_N : in std_logic := 'U'; NGMUX2_HOLD_N : in std_logic := 'U'; NGMUX3_HOLD_N : in std_logic := 'U'; NGMUX0_ARST_N : in std_logic := 'U'; NGMUX1_ARST_N : in std_logic := 'U'; NGMUX2_ARST_N : in std_logic := 'U'; NGMUX3_ARST_N : in std_logic := 'U'; PLL_BYPASS_N : in std_logic := 'U'; PLL_ARST_N : in std_logic := 'U'; PLL_POWERDOWN_N : in std_logic := 'U'; GPD0_ARST_N : in std_logic := 'U'; GPD1_ARST_N : in std_logic := 'U'; GPD2_ARST_N : in std_logic := 'U'; GPD3_ARST_N : in std_logic := 'U'; PRESET_N : in std_logic := 'U'; PCLK : in std_logic := 'U'; PSEL : in std_logic := 'U'; PENABLE : in std_logic := 'U'; PWRITE : in std_logic := 'U'; PADDR : in std_logic_vector(7 downto 2) := (others => 'U'); PWDATA : in std_logic_vector(7 downto 0) := (others => 'U'); CLK0_PAD : in std_logic := 'U'; CLK1_PAD : in std_logic := 'U'; CLK2_PAD : in std_logic := 'U'; CLK3_PAD : in std_logic := 'U'; GL0 : out std_logic; GL1 : out std_logic; GL2 : out std_logic; GL3 : out std_logic; RCOSC_25_50MHZ : in std_logic := 'U'; RCOSC_1MHZ : in std_logic := 'U'; XTLOSC : in std_logic := 'U' ); end component; component CLKINT port( A : in std_logic := 'U'; Y : out std_logic ); end component; signal N_RCOSC_1MHZ : std_logic; signal N_RCOSC_1MHZ_CCC : std_logic; signal gnd_net, vcc_net, GL0_net : std_logic; signal nc7, nc6, nc2, nc5, nc4, nc3, nc1, nc0 : std_logic; begin I_RCOSC_1MHZ : RCOSC_1MHZ port map(CLKOUT => N_RCOSC_1MHZ_CCC); vcc_inst : VCC port map(Y => vcc_net); gnd_inst : GND port map(Y => gnd_net); GL0_INST : CLKINT port map(A => GL0_net, Y => o_clk); CCC_INST : CCC -- wide=64000ppm default=8000ppm narrow=500ppm -- generic map(INIT => "00" & x"000007F8800004503C000318C6318C1F18C61E80404040403100",-- wide -- generic map(INIT => "00" & x"000007F88000045164000318C6318C1F18C61E80404040403100",-- default generic map(INIT => "00" & x"000007F88000045004000318C6318C1F18C61E80404040403100",-- narrow VCOFREQUENCY => 800.000) port map(Y0 => OPEN, Y1 => OPEN, Y2 => OPEN, Y3 => OPEN, PRDATA(7) => nc7, PRDATA(6) => nc6, PRDATA(5) => nc5, PRDATA(4) => nc4, PRDATA(3) => nc3, PRDATA(2) => nc2, PRDATA(1) => nc1, PRDATA(0) => nc0, LOCK => o_rst_n, BUSY => OPEN, CLK0 => vcc_net, CLK1 => vcc_net, CLK2 => vcc_net, CLK3 => vcc_net, NGMUX0_SEL => gnd_net, NGMUX1_SEL => gnd_net, NGMUX2_SEL => gnd_net, NGMUX3_SEL => gnd_net, NGMUX0_HOLD_N => vcc_net, NGMUX1_HOLD_N => vcc_net, NGMUX2_HOLD_N => vcc_net, NGMUX3_HOLD_N => vcc_net, NGMUX0_ARST_N => vcc_net, NGMUX1_ARST_N => vcc_net, NGMUX2_ARST_N => vcc_net, NGMUX3_ARST_N => vcc_net, PLL_BYPASS_N => vcc_net, PLL_ARST_N => vcc_net, PLL_POWERDOWN_N => vcc_net, GPD0_ARST_N => vcc_net, GPD1_ARST_N => vcc_net, GPD2_ARST_N => vcc_net, GPD3_ARST_N => vcc_net, PRESET_N => gnd_net, PCLK => vcc_net, PSEL => vcc_net, PENABLE => vcc_net, PWRITE => vcc_net, PADDR(7) => vcc_net, PADDR(6) => vcc_net, PADDR(5) => vcc_net, PADDR(4) => vcc_net, PADDR(3) => vcc_net, PADDR(2) => vcc_net, PWDATA(7) => vcc_net, PWDATA(6) => vcc_net, PWDATA(5) => vcc_net, PWDATA(4) => vcc_net, PWDATA(3) => vcc_net, PWDATA(2) => vcc_net, PWDATA(1) => vcc_net, PWDATA(0) => vcc_net, CLK0_PAD => gnd_net, CLK1_PAD => gnd_net, CLK2_PAD => gnd_net, CLK3_PAD => gnd_net, GL0 => GL0_net, GL1 => OPEN, GL2 => OPEN, GL3 => OPEN, RCOSC_25_50MHZ => gnd_net, RCOSC_1MHZ => N_RCOSC_1MHZ_CCC, XTLOSC => gnd_net); end DEF_ARCH; -------------------------------------------------------------------------------- -- HowTo : This piece of source code was creted using Libero SoC 11.7 : -- Create new vhdl project, block flow, SmartFusion2 M2S010S-TQ144, no template, no files. -- Create new SmartDesign, open catalog, drag Chip Oscillators and drop to canvas. -- Configure ChipOsc to enable OnChip 25/50MHz RC Oscillator to drive fabric logic -- Promote signal to toplevel, generate component, open hdl and extract relevant components ----------------------------------------------------------------------
------------------------------------------------------------------------------- -- Title : Shift In Register (74HC(T)165 and similar types) -- Project : Loa ------------------------------------------------------------------------------- -- Author : Fabian Greif <fabian@kleinvieh> -- Company : Roboterclub Aachen e.V. -- Platform : Spartan 3 ------------------------------------------------------------------------------- -- Description: -- -- Maximum frequency 74HC165 : xx MHz -- 74HCT165 : xx MHz -- -- -- ## Pins -- -- !CE (Pin 15) should be tied to low. -- -- ## Waveform -- -- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 -- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ -- clke __| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| | -- ___ ___ ___ ___ ___ ___ ___ ___ -- sck ______| |___| |___| |___| |___| |___| |___| |___| |_________ -- _______ _______ _______ _______ _______ _______ _______ _______ -- dout __X_______X_______X_______X_______X_______X_______X_______X_______X_________ -- bit 0 1 2 3 4 5 6 7 8 9 -- ___ -- load ______________________________________________________________________| |__ -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package shiftin_pkg is type shiftin_out_type is record sck : std_logic; -- or CP (Pin 2) load_n : std_logic; -- or !PL (Pin 1) end record; type shiftout_in_type is record din : std_logic; -- or Q7 (Pin 9) end record shiftout_in_type; component shiftin is port ( register_out_p : out shiftin_out_type; register_in_p : in shiftout_in_type; re_p : in std_logic; busy_p : out std_logic; value_p : out std_logic_vector(7 downto 0); clk : in std_logic); end component shiftin; end package shiftin_pkg; ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.shiftin_pkg.all; entity shiftin is port ( register_out_p : out shiftin_out_type; register_in_p : in shiftout_in_type; re_p : in std_logic; -- Start transaction busy_p : out std_logic; -- Transaction in progress value_p : out std_logic_vector(7 downto 0); clk : in std_logic); end entity shiftin; architecture behavioral of shiftin is signal clk_enable : std_logic := '1'; -- clock enable for the SCK speed type shiftin_state_type is ( STATE_IDLE, STATE_LOAD, STATE_LOAD_WAIT, STATE_WRITE, STATE_WRITE_NEXT); type shiftin_type is record state : shiftin_state_type; value_buffer : std_logic_vector(7 downto 0); value : std_logic_vector(7 downto 0); bitcount : integer range 0 to 9; -- Number of bits loaded o : shiftin_out_type; end record shiftin_type; signal r, rin : shiftin_type := ( state => STATE_IDLE, value_buffer => (others => '0'), value => (others => '0'), bitcount => 0, o => ( sck => '0', load_n => '1')); begin seq_proc : process (clk) is begin if rising_edge(clk) then r <= rin; end if; end process seq_proc; comb_proc : process (clk_enable, r, r.bitcount, r.o, r.state, r.value, r.value_buffer(6 downto 0), r.value_buffer(7), value_p) is variable v : shiftin_type; begin v := r; case r.state is when STATE_IDLE => if re_p = '1' then v.state := STATE_LOAD; end if; when STATE_LOAD => if clk_enable = '1' then v.o.load_n := '0'; v.state := STATE_LOAD_WAIT; end if; when STATE_LOAD_WAIT => if clk_enable = '1' then v.o.load_n := '1'; v.state := STATE_WRITE_NEXT; end if; when STATE_WRITE => if clk_enable = '1' then v.o.sck := '1'; v.state := STATE_WRITE_NEXT; end if; when STATE_WRITE_NEXT => if clk_enable = '1' then v.o.sck := '0'; v.state := STATE_WRITE; end if; ---- Clock low and switch to the next bit --when STATE_WRITE_NEXT => -- if clk_enable = '1' then -- v.o.sck := '0'; -- -- MSB first -- v.o.dout := r.value_buffer(7); -- v.value_buffer := r.value_buffer(6 downto 0) & '0'; -- v.bitcount := r.bitcount + 1; -- if r.bitcount = 8 then -- v.state := STATE_LOAD; -- else -- v.state := STATE_WRITE; -- end if; -- end if; end case; -- register outputs register_out_p <= r.o; rin <= v; end process comb_proc; -- TODO clk_enable generation -- to adapt to higher clk frequencies end architecture behavioral;
------------------------------------------------------------------------------- -- Title : Shift In Register (74HC(T)165 and similar types) -- Project : Loa ------------------------------------------------------------------------------- -- Author : Fabian Greif <fabian@kleinvieh> -- Company : Roboterclub Aachen e.V. -- Platform : Spartan 3 ------------------------------------------------------------------------------- -- Description: -- -- Maximum frequency 74HC165 : xx MHz -- 74HCT165 : xx MHz -- -- -- ## Pins -- -- !CE (Pin 15) should be tied to low. -- -- ## Waveform -- -- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 -- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ -- clke __| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| | -- ___ ___ ___ ___ ___ ___ ___ ___ -- sck ______| |___| |___| |___| |___| |___| |___| |___| |_________ -- _______ _______ _______ _______ _______ _______ _______ _______ -- dout __X_______X_______X_______X_______X_______X_______X_______X_______X_________ -- bit 0 1 2 3 4 5 6 7 8 9 -- ___ -- load ______________________________________________________________________| |__ -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package shiftin_pkg is type shiftin_out_type is record sck : std_logic; -- or CP (Pin 2) load_n : std_logic; -- or !PL (Pin 1) end record; type shiftout_in_type is record din : std_logic; -- or Q7 (Pin 9) end record shiftout_in_type; component shiftin is port ( register_out_p : out shiftin_out_type; register_in_p : in shiftout_in_type; re_p : in std_logic; busy_p : out std_logic; value_p : out std_logic_vector(7 downto 0); clk : in std_logic); end component shiftin; end package shiftin_pkg; ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.shiftin_pkg.all; entity shiftin is port ( register_out_p : out shiftin_out_type; register_in_p : in shiftout_in_type; re_p : in std_logic; -- Start transaction busy_p : out std_logic; -- Transaction in progress value_p : out std_logic_vector(7 downto 0); clk : in std_logic); end entity shiftin; architecture behavioral of shiftin is signal clk_enable : std_logic := '1'; -- clock enable for the SCK speed type shiftin_state_type is ( STATE_IDLE, STATE_LOAD, STATE_LOAD_WAIT, STATE_WRITE, STATE_WRITE_NEXT); type shiftin_type is record state : shiftin_state_type; value_buffer : std_logic_vector(7 downto 0); value : std_logic_vector(7 downto 0); bitcount : integer range 0 to 9; -- Number of bits loaded o : shiftin_out_type; end record shiftin_type; signal r, rin : shiftin_type := ( state => STATE_IDLE, value_buffer => (others => '0'), value => (others => '0'), bitcount => 0, o => ( sck => '0', load_n => '1')); begin seq_proc : process (clk) is begin if rising_edge(clk) then r <= rin; end if; end process seq_proc; comb_proc : process (clk_enable, r, r.bitcount, r.o, r.state, r.value, r.value_buffer(6 downto 0), r.value_buffer(7), value_p) is variable v : shiftin_type; begin v := r; case r.state is when STATE_IDLE => if re_p = '1' then v.state := STATE_LOAD; end if; when STATE_LOAD => if clk_enable = '1' then v.o.load_n := '0'; v.state := STATE_LOAD_WAIT; end if; when STATE_LOAD_WAIT => if clk_enable = '1' then v.o.load_n := '1'; v.state := STATE_WRITE_NEXT; end if; when STATE_WRITE => if clk_enable = '1' then v.o.sck := '1'; v.state := STATE_WRITE_NEXT; end if; when STATE_WRITE_NEXT => if clk_enable = '1' then v.o.sck := '0'; v.state := STATE_WRITE; end if; ---- Clock low and switch to the next bit --when STATE_WRITE_NEXT => -- if clk_enable = '1' then -- v.o.sck := '0'; -- -- MSB first -- v.o.dout := r.value_buffer(7); -- v.value_buffer := r.value_buffer(6 downto 0) & '0'; -- v.bitcount := r.bitcount + 1; -- if r.bitcount = 8 then -- v.state := STATE_LOAD; -- else -- v.state := STATE_WRITE; -- end if; -- end if; end case; -- register outputs register_out_p <= r.o; rin <= v; end process comb_proc; -- TODO clk_enable generation -- to adapt to higher clk frequencies end architecture behavioral;
library verilog; use verilog.vl_types.all; entity finalproject_mm_interconnect_1 is port( clocks_c1_clk : in vl_logic; clock_crossing_io_m0_reset_reset_bridge_in_reset_reset: in vl_logic; clock_crossing_io_m0_address: in vl_logic_vector(21 downto 0); clock_crossing_io_m0_waitrequest: out vl_logic; clock_crossing_io_m0_burstcount: in vl_logic_vector(0 downto 0); clock_crossing_io_m0_byteenable: in vl_logic_vector(3 downto 0); clock_crossing_io_m0_read: in vl_logic; clock_crossing_io_m0_readdata: out vl_logic_vector(31 downto 0); clock_crossing_io_m0_readdatavalid: out vl_logic; clock_crossing_io_m0_write: in vl_logic; clock_crossing_io_m0_writedata: in vl_logic_vector(31 downto 0); clock_crossing_io_m0_debugaccess: in vl_logic; CY7C67200_IF_0_hpi_address: out vl_logic_vector(1 downto 0); CY7C67200_IF_0_hpi_write: out vl_logic; CY7C67200_IF_0_hpi_read: out vl_logic; CY7C67200_IF_0_hpi_readdata: in vl_logic_vector(31 downto 0); CY7C67200_IF_0_hpi_writedata: out vl_logic_vector(31 downto 0); CY7C67200_IF_0_hpi_chipselect: out vl_logic ); end finalproject_mm_interconnect_1;
library IEEE; use IEEE.STD_LOGIC_1164.all; package bfconfig is -- Sizes are log2 of full sizes constant INST_MEM_SIZE : integer := 14; constant JUMPF_CACHE_SIZE : integer := 3; constant STACK_SIZE : integer := 8; constant REG_SIZE : integer := 9; subtype pctype is std_logic_vector(INST_MEM_SIZE-1 downto 0); subtype pointertype is std_logic_vector(REG_SIZE-1 downto 0); end bfconfig; package body bfconfig is end bfconfig;
package func is function add(x, y : integer; z : in integer) return integer; impure function naughty return integer; function "+"(x, y : integer) return integer; end package; package body func is function "+"(x, y : integer) return integer is begin return 42; end function "+"; end package body;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1845.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s01b00x00p08n01i01845ent IS type small_int is range 0 to 7; END c07s01b00x00p08n01i01845ent; ARCHITECTURE c07s01b00x00p08n01i01845arch OF c07s01b00x00p08n01i01845ent IS signal s_int : small_int := ch0701_p00801_36_arch; BEGIN TESTING : PROCESS BEGIN wait for 5 ns; assert FALSE report "***FAILED TEST: c07s01b00x00p08n01i01845 - Architecture body names are not permitted as primaries in an initialization expression." severity ERROR; wait; END PROCESS TESTING; END c07s01b00x00p08n01i01845arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1845.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s01b00x00p08n01i01845ent IS type small_int is range 0 to 7; END c07s01b00x00p08n01i01845ent; ARCHITECTURE c07s01b00x00p08n01i01845arch OF c07s01b00x00p08n01i01845ent IS signal s_int : small_int := ch0701_p00801_36_arch; BEGIN TESTING : PROCESS BEGIN wait for 5 ns; assert FALSE report "***FAILED TEST: c07s01b00x00p08n01i01845 - Architecture body names are not permitted as primaries in an initialization expression." severity ERROR; wait; END PROCESS TESTING; END c07s01b00x00p08n01i01845arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1845.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s01b00x00p08n01i01845ent IS type small_int is range 0 to 7; END c07s01b00x00p08n01i01845ent; ARCHITECTURE c07s01b00x00p08n01i01845arch OF c07s01b00x00p08n01i01845ent IS signal s_int : small_int := ch0701_p00801_36_arch; BEGIN TESTING : PROCESS BEGIN wait for 5 ns; assert FALSE report "***FAILED TEST: c07s01b00x00p08n01i01845 - Architecture body names are not permitted as primaries in an initialization expression." severity ERROR; wait; END PROCESS TESTING; END c07s01b00x00p08n01i01845arch;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 3.9 -- \ \ Application : MIG -- / / Filename : sim_tb_top.vhd -- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $ -- \ \ / \ Date Created : Jul 03 2009 -- \___\/\___\ -- -- Device : Spartan-6 -- Design Name : DDR/DDR2/DDR3/LPDDR -- Purpose : This is the simulation testbench which is used to verify the -- design. The basic clocks and resets to the interface are -- generated here. This also connects the memory interface to the -- memory model. --***************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity sim_tb_top is end entity sim_tb_top; architecture arch of sim_tb_top is -- ========================================================================== -- -- Parameters -- -- ========================================================================== -- constant DEBUG_EN : integer :=0; constant C3_HW_TESTING : string := "FALSE"; function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is begin if (C3_HW_TESTING = "FALSE") then return val1; else return val2; end if; end function; constant C3_MEMCLK_PERIOD : integer := 3000; constant C3_RST_ACT_LOW : integer := 0; constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED"; constant C3_CLK_PERIOD_NS : real := 3000.0 / 1000.0; constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0; constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns; constant C3_NUM_DQ_PINS : integer := 16; constant C3_MEM_ADDR_WIDTH : integer := 14; constant C3_MEM_BANKADDR_WIDTH : integer := 3; constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; constant C3_P0_MASK_SIZE : integer := 8; constant C3_P0_DATA_PORT_SIZE : integer := 64; constant C3_P1_MASK_SIZE : integer := 4; constant C3_P1_DATA_PORT_SIZE : integer := 32; constant C3_CALIB_SOFT_IP : string := "TRUE"; constant C3_SIMULATION : string := "TRUE"; -- ========================================================================== -- -- Component Declarations -- ========================================================================== -- component example_top is generic ( C3_P0_MASK_SIZE : integer; C3_P0_DATA_PORT_SIZE : integer; C3_P1_MASK_SIZE : integer; C3_P1_DATA_PORT_SIZE : integer; C3_MEMCLK_PERIOD : integer; C3_RST_ACT_LOW : integer; C3_INPUT_CLK_TYPE : string; DEBUG_EN : integer; C3_CALIB_SOFT_IP : string; C3_SIMULATION : string; C3_HW_TESTING : string; C3_MEM_ADDR_ORDER : string; C3_NUM_DQ_PINS : integer; C3_MEM_ADDR_WIDTH : integer; C3_MEM_BANKADDR_WIDTH : integer ); port ( calib_done : out std_logic; error : out std_logic; mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0); mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0); mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_rzq : inout std_logic; c3_sys_clk : in std_logic; c3_sys_rst_i : in std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_dram_udm : out std_logic; mcb3_dram_reset_n : out std_logic ); end component; component ddr3_model_c3 is port ( ck : in std_logic; ck_n : in std_logic; cke : in std_logic; cs_n : in std_logic; ras_n : in std_logic; cas_n : in std_logic; we_n : in std_logic; dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0); ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0); addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0); dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0); dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0); dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0); tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0); odt : in std_logic; rst_n : in std_logic ); end component; -- ========================================================================== -- -- Signal Declarations -- -- ========================================================================== -- -- Clocks signal c3_sys_clk : std_logic := '0'; signal c3_sys_clk_p : std_logic; signal c3_sys_clk_n : std_logic; -- System Reset signal c3_sys_rst : std_logic := '0'; signal c3_sys_rst_i : std_logic; -- Design-Top Port Map signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0); signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0); signal mcb3_dram_ck : std_logic; signal mcb3_dram_ck_n : std_logic; signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0); signal mcb3_dram_dqs : std_logic; signal mcb3_dram_dqs_n : std_logic; signal mcb3_dram_dm : std_logic; signal mcb3_dram_ras_n : std_logic; signal mcb3_dram_cas_n : std_logic; signal mcb3_dram_we_n : std_logic; signal mcb3_dram_cke : std_logic; signal mcb3_dram_odt : std_logic; signal mcb3_dram_reset_n : std_logic; signal calib_done : std_logic; signal error : std_logic; signal mcb3_dram_udqs : std_logic; signal mcb3_dram_udqs_n : std_logic; signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0); signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0); signal mcb3_dram_udm :std_logic; -- for X16 parts signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0); signal mcb3_command : std_logic_vector(2 downto 0); signal mcb3_enable1 : std_logic; signal mcb3_enable2 : std_logic; signal rzq3 : std_logic; function vector (asi:std_logic) return std_logic_vector is variable v : std_logic_vector(0 downto 0) ; begin v(0) := asi; return(v); end function vector; begin -- ========================================================================== -- -- Clocks Generation -- -- ========================================================================== -- process begin c3_sys_clk <= not c3_sys_clk; wait for (C3_TCYC_SYS_DIV2); end process; c3_sys_clk_p <= c3_sys_clk; c3_sys_clk_n <= not c3_sys_clk; -- ========================================================================== -- -- Reset Generation -- -- ========================================================================== -- process begin c3_sys_rst <= '0'; wait for 200 ns; c3_sys_rst <= '1'; wait; end process; c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst); rzq_pulldown3 : PULLDOWN port map(O => rzq3); -- ========================================================================== -- -- DESIGN TOP INSTANTIATION -- -- ========================================================================== -- design_top : example_top generic map ( C3_P0_MASK_SIZE => C3_P0_MASK_SIZE, C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE, C3_P1_MASK_SIZE => C3_P1_MASK_SIZE, C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE, C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD, C3_RST_ACT_LOW => C3_RST_ACT_LOW, C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE, DEBUG_EN => DEBUG_EN, C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER, C3_NUM_DQ_PINS => C3_NUM_DQ_PINS, C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH, C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH, C3_HW_TESTING => C3_HW_TESTING, C3_SIMULATION => C3_SIMULATION, C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP ) port map ( calib_done => calib_done, error => error, c3_sys_clk => c3_sys_clk, c3_sys_rst_i => c3_sys_rst_i, mcb3_dram_dq => mcb3_dram_dq, mcb3_dram_a => mcb3_dram_a, mcb3_dram_ba => mcb3_dram_ba, mcb3_dram_ras_n => mcb3_dram_ras_n, mcb3_dram_cas_n => mcb3_dram_cas_n, mcb3_dram_we_n => mcb3_dram_we_n, mcb3_dram_odt => mcb3_dram_odt, mcb3_dram_cke => mcb3_dram_cke, mcb3_dram_ck => mcb3_dram_ck, mcb3_dram_ck_n => mcb3_dram_ck_n, mcb3_dram_dqs_n => mcb3_dram_dqs_n, mcb3_dram_reset_n => mcb3_dram_reset_n, mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts mcb3_dram_dm => mcb3_dram_dm, mcb3_rzq => rzq3, mcb3_dram_dqs => mcb3_dram_dqs ); -- ========================================================================== -- -- Memory model instances -- -- ========================================================================== -- mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n); process(mcb3_dram_ck) begin if (rising_edge(mcb3_dram_ck)) then if (c3_sys_rst = '0') then mcb3_enable1 <= '0'; mcb3_enable2 <= '0'; elsif (mcb3_command = "100") then mcb3_enable2 <= '0'; elsif (mcb3_command = "101") then mcb3_enable2 <= '1'; else mcb3_enable2 <= mcb3_enable2; end if; mcb3_enable1 <= mcb3_enable2; end if; end process; ----------------------------------------------------------------------------- --read ----------------------------------------------------------------------------- mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs) when (mcb3_enable2 = '0' and mcb3_enable1 = '0') else "ZZ"; mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n) when (mcb3_enable2 = '0' and mcb3_enable1 = '0') else "ZZ"; ----------------------------------------------------------------------------- --write ----------------------------------------------------------------------------- mcb3_dram_dqs <= mcb3_dram_dqs_vector(0) when ( mcb3_enable1 = '1') else 'Z'; mcb3_dram_udqs <= mcb3_dram_dqs_vector(1) when (mcb3_enable1 = '1') else 'Z'; mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0) when (mcb3_enable1 = '1') else 'Z'; mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1) when (mcb3_enable1 = '1') else 'Z'; mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm); u_mem_c3 : ddr3_model_c3 port map ( ck => mcb3_dram_ck, ck_n => mcb3_dram_ck_n, cke => mcb3_dram_cke, cs_n => '0', ras_n => mcb3_dram_ras_n, cas_n => mcb3_dram_cas_n, we_n => mcb3_dram_we_n, dm_tdqs => mcb3_dram_dm_vector, ba => mcb3_dram_ba, addr => mcb3_dram_a, dq => mcb3_dram_dq, dqs => mcb3_dram_dqs_vector, dqs_n => mcb3_dram_dqs_n_vector, tdqs_n => open, odt => mcb3_dram_odt, rst_n => mcb3_dram_reset_n ); ----------------------------------------------------------------------------- -- Reporting the test case status ----------------------------------------------------------------------------- Logging: process begin wait for 200 us; if (calib_done = '1') then if (error = '0') then report ("****TEST PASSED****"); else report ("****TEST FAILED: DATA ERROR****"); end if; else report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****"); end if; end process; end architecture;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 3.9 -- \ \ Application : MIG -- / / Filename : sim_tb_top.vhd -- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $ -- \ \ / \ Date Created : Jul 03 2009 -- \___\/\___\ -- -- Device : Spartan-6 -- Design Name : DDR/DDR2/DDR3/LPDDR -- Purpose : This is the simulation testbench which is used to verify the -- design. The basic clocks and resets to the interface are -- generated here. This also connects the memory interface to the -- memory model. --***************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity sim_tb_top is end entity sim_tb_top; architecture arch of sim_tb_top is -- ========================================================================== -- -- Parameters -- -- ========================================================================== -- constant DEBUG_EN : integer :=0; constant C3_HW_TESTING : string := "FALSE"; function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is begin if (C3_HW_TESTING = "FALSE") then return val1; else return val2; end if; end function; constant C3_MEMCLK_PERIOD : integer := 3000; constant C3_RST_ACT_LOW : integer := 0; constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED"; constant C3_CLK_PERIOD_NS : real := 3000.0 / 1000.0; constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0; constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns; constant C3_NUM_DQ_PINS : integer := 16; constant C3_MEM_ADDR_WIDTH : integer := 14; constant C3_MEM_BANKADDR_WIDTH : integer := 3; constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; constant C3_P0_MASK_SIZE : integer := 8; constant C3_P0_DATA_PORT_SIZE : integer := 64; constant C3_P1_MASK_SIZE : integer := 4; constant C3_P1_DATA_PORT_SIZE : integer := 32; constant C3_CALIB_SOFT_IP : string := "TRUE"; constant C3_SIMULATION : string := "TRUE"; -- ========================================================================== -- -- Component Declarations -- ========================================================================== -- component example_top is generic ( C3_P0_MASK_SIZE : integer; C3_P0_DATA_PORT_SIZE : integer; C3_P1_MASK_SIZE : integer; C3_P1_DATA_PORT_SIZE : integer; C3_MEMCLK_PERIOD : integer; C3_RST_ACT_LOW : integer; C3_INPUT_CLK_TYPE : string; DEBUG_EN : integer; C3_CALIB_SOFT_IP : string; C3_SIMULATION : string; C3_HW_TESTING : string; C3_MEM_ADDR_ORDER : string; C3_NUM_DQ_PINS : integer; C3_MEM_ADDR_WIDTH : integer; C3_MEM_BANKADDR_WIDTH : integer ); port ( calib_done : out std_logic; error : out std_logic; mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0); mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0); mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_rzq : inout std_logic; c3_sys_clk : in std_logic; c3_sys_rst_i : in std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_dram_udm : out std_logic; mcb3_dram_reset_n : out std_logic ); end component; component ddr3_model_c3 is port ( ck : in std_logic; ck_n : in std_logic; cke : in std_logic; cs_n : in std_logic; ras_n : in std_logic; cas_n : in std_logic; we_n : in std_logic; dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0); ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0); addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0); dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0); dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0); dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0); tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0); odt : in std_logic; rst_n : in std_logic ); end component; -- ========================================================================== -- -- Signal Declarations -- -- ========================================================================== -- -- Clocks signal c3_sys_clk : std_logic := '0'; signal c3_sys_clk_p : std_logic; signal c3_sys_clk_n : std_logic; -- System Reset signal c3_sys_rst : std_logic := '0'; signal c3_sys_rst_i : std_logic; -- Design-Top Port Map signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0); signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0); signal mcb3_dram_ck : std_logic; signal mcb3_dram_ck_n : std_logic; signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0); signal mcb3_dram_dqs : std_logic; signal mcb3_dram_dqs_n : std_logic; signal mcb3_dram_dm : std_logic; signal mcb3_dram_ras_n : std_logic; signal mcb3_dram_cas_n : std_logic; signal mcb3_dram_we_n : std_logic; signal mcb3_dram_cke : std_logic; signal mcb3_dram_odt : std_logic; signal mcb3_dram_reset_n : std_logic; signal calib_done : std_logic; signal error : std_logic; signal mcb3_dram_udqs : std_logic; signal mcb3_dram_udqs_n : std_logic; signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0); signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0); signal mcb3_dram_udm :std_logic; -- for X16 parts signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0); signal mcb3_command : std_logic_vector(2 downto 0); signal mcb3_enable1 : std_logic; signal mcb3_enable2 : std_logic; signal rzq3 : std_logic; function vector (asi:std_logic) return std_logic_vector is variable v : std_logic_vector(0 downto 0) ; begin v(0) := asi; return(v); end function vector; begin -- ========================================================================== -- -- Clocks Generation -- -- ========================================================================== -- process begin c3_sys_clk <= not c3_sys_clk; wait for (C3_TCYC_SYS_DIV2); end process; c3_sys_clk_p <= c3_sys_clk; c3_sys_clk_n <= not c3_sys_clk; -- ========================================================================== -- -- Reset Generation -- -- ========================================================================== -- process begin c3_sys_rst <= '0'; wait for 200 ns; c3_sys_rst <= '1'; wait; end process; c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst); rzq_pulldown3 : PULLDOWN port map(O => rzq3); -- ========================================================================== -- -- DESIGN TOP INSTANTIATION -- -- ========================================================================== -- design_top : example_top generic map ( C3_P0_MASK_SIZE => C3_P0_MASK_SIZE, C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE, C3_P1_MASK_SIZE => C3_P1_MASK_SIZE, C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE, C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD, C3_RST_ACT_LOW => C3_RST_ACT_LOW, C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE, DEBUG_EN => DEBUG_EN, C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER, C3_NUM_DQ_PINS => C3_NUM_DQ_PINS, C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH, C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH, C3_HW_TESTING => C3_HW_TESTING, C3_SIMULATION => C3_SIMULATION, C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP ) port map ( calib_done => calib_done, error => error, c3_sys_clk => c3_sys_clk, c3_sys_rst_i => c3_sys_rst_i, mcb3_dram_dq => mcb3_dram_dq, mcb3_dram_a => mcb3_dram_a, mcb3_dram_ba => mcb3_dram_ba, mcb3_dram_ras_n => mcb3_dram_ras_n, mcb3_dram_cas_n => mcb3_dram_cas_n, mcb3_dram_we_n => mcb3_dram_we_n, mcb3_dram_odt => mcb3_dram_odt, mcb3_dram_cke => mcb3_dram_cke, mcb3_dram_ck => mcb3_dram_ck, mcb3_dram_ck_n => mcb3_dram_ck_n, mcb3_dram_dqs_n => mcb3_dram_dqs_n, mcb3_dram_reset_n => mcb3_dram_reset_n, mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts mcb3_dram_dm => mcb3_dram_dm, mcb3_rzq => rzq3, mcb3_dram_dqs => mcb3_dram_dqs ); -- ========================================================================== -- -- Memory model instances -- -- ========================================================================== -- mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n); process(mcb3_dram_ck) begin if (rising_edge(mcb3_dram_ck)) then if (c3_sys_rst = '0') then mcb3_enable1 <= '0'; mcb3_enable2 <= '0'; elsif (mcb3_command = "100") then mcb3_enable2 <= '0'; elsif (mcb3_command = "101") then mcb3_enable2 <= '1'; else mcb3_enable2 <= mcb3_enable2; end if; mcb3_enable1 <= mcb3_enable2; end if; end process; ----------------------------------------------------------------------------- --read ----------------------------------------------------------------------------- mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs) when (mcb3_enable2 = '0' and mcb3_enable1 = '0') else "ZZ"; mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n) when (mcb3_enable2 = '0' and mcb3_enable1 = '0') else "ZZ"; ----------------------------------------------------------------------------- --write ----------------------------------------------------------------------------- mcb3_dram_dqs <= mcb3_dram_dqs_vector(0) when ( mcb3_enable1 = '1') else 'Z'; mcb3_dram_udqs <= mcb3_dram_dqs_vector(1) when (mcb3_enable1 = '1') else 'Z'; mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0) when (mcb3_enable1 = '1') else 'Z'; mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1) when (mcb3_enable1 = '1') else 'Z'; mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm); u_mem_c3 : ddr3_model_c3 port map ( ck => mcb3_dram_ck, ck_n => mcb3_dram_ck_n, cke => mcb3_dram_cke, cs_n => '0', ras_n => mcb3_dram_ras_n, cas_n => mcb3_dram_cas_n, we_n => mcb3_dram_we_n, dm_tdqs => mcb3_dram_dm_vector, ba => mcb3_dram_ba, addr => mcb3_dram_a, dq => mcb3_dram_dq, dqs => mcb3_dram_dqs_vector, dqs_n => mcb3_dram_dqs_n_vector, tdqs_n => open, odt => mcb3_dram_odt, rst_n => mcb3_dram_reset_n ); ----------------------------------------------------------------------------- -- Reporting the test case status ----------------------------------------------------------------------------- Logging: process begin wait for 200 us; if (calib_done = '1') then if (error = '0') then report ("****TEST PASSED****"); else report ("****TEST FAILED: DATA ERROR****"); end if; else report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****"); end if; end process; end architecture;
architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); -- Violations below U_INST1 : INST1 port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : configuration CONFIG port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : entity FIFO port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : entity FIFO(rtl) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : component FIFO port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end architecture ARCH;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3174.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c14s01b00x00p22n01i03174ent IS END c14s01b00x00p22n01i03174ent; ARCHITECTURE c14s01b00x00p22n01i03174arch OF c14s01b00x00p22n01i03174ent IS signal gate : BOOLEAN; signal s : CHARACTER := NUL; BEGIN TESTING: PROCESS BEGIN gate <= s < CHARACTER'HIGH after 2 ns; wait for 5 ns; assert NOT( gate = TRUE ) report "***PASSED TEST: c14s01b00x00p22n01i03174" severity NOTE; assert ( gate = TRUE ) report "***FAILED TEST: c14s01b00x00p22n01i03174 - Predefined attribute HIGH test for character type failed." severity ERROR; wait; END PROCESS TESTING; END c14s01b00x00p22n01i03174arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3174.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c14s01b00x00p22n01i03174ent IS END c14s01b00x00p22n01i03174ent; ARCHITECTURE c14s01b00x00p22n01i03174arch OF c14s01b00x00p22n01i03174ent IS signal gate : BOOLEAN; signal s : CHARACTER := NUL; BEGIN TESTING: PROCESS BEGIN gate <= s < CHARACTER'HIGH after 2 ns; wait for 5 ns; assert NOT( gate = TRUE ) report "***PASSED TEST: c14s01b00x00p22n01i03174" severity NOTE; assert ( gate = TRUE ) report "***FAILED TEST: c14s01b00x00p22n01i03174 - Predefined attribute HIGH test for character type failed." severity ERROR; wait; END PROCESS TESTING; END c14s01b00x00p22n01i03174arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3174.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c14s01b00x00p22n01i03174ent IS END c14s01b00x00p22n01i03174ent; ARCHITECTURE c14s01b00x00p22n01i03174arch OF c14s01b00x00p22n01i03174ent IS signal gate : BOOLEAN; signal s : CHARACTER := NUL; BEGIN TESTING: PROCESS BEGIN gate <= s < CHARACTER'HIGH after 2 ns; wait for 5 ns; assert NOT( gate = TRUE ) report "***PASSED TEST: c14s01b00x00p22n01i03174" severity NOTE; assert ( gate = TRUE ) report "***FAILED TEST: c14s01b00x00p22n01i03174 - Predefined attribute HIGH test for character type failed." severity ERROR; wait; END PROCESS TESTING; END c14s01b00x00p22n01i03174arch;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mcu is port ( clk : in std_logic; rst : in std_logic; instr : out std_logic_vector(31 downto 0)); end mcu; architecture Behavioral of mcu is component memory_no_clk is generic ( N : integer); port ( clk : in std_logic; write_en: in std_logic; addr_1 : in std_logic_vector (31 downto 0); addr_2 : in std_logic_vector (31 downto 0); data_w2 : in std_logic_vector (31 downto 0); data_r1 : out std_logic_vector (31 downto 0); data_r2 : out std_logic_vector (31 downto 0)); end component memory_no_clk; component regfile_no_clk is port ( clk : in std_logic; write_en: in std_logic; addr_r1 : in std_logic_vector (3 downto 0); addr_r2 : in std_logic_vector (3 downto 0); addr_w1 : in std_logic_vector (3 downto 0); data_w1 : in std_logic_vector (31 downto 0); pc_next : in std_logic_vector (31 downto 0); data_r1 : out std_logic_vector (31 downto 0); data_r2 : out std_logic_vector (31 downto 0); data_pc : out std_logic_vector (31 downto 0)); end component regfile_no_clk; component alu is port ( input_1 : in std_logic_vector (31 downto 0); input_2 : in std_logic_vector (31 downto 0); funct : in std_logic_vector (4 downto 0); flags_current : in std_logic_vector(3 downto 0); output : out std_logic_vector (31 downto 0); flags_next : out std_logic_vector (3 downto 0); flags_update : out std_logic_vector (1 downto 0)); end component alu; signal instruction_fetched : std_logic_vector (31 downto 0) := (others=>'0'); signal pc_current, pc_next, pc_shifted, pc_plus4 : std_logic_vector (31 downto 0) := (others=>'0'); signal cond_branch : std_logic; signal reg_read_addr_1, reg_read_addr_2, reg_write_addr : std_logic_vector (3 downto 0) := (others=>'0'); signal reg_read_data_1, reg_read_data_2, reg_write_data, reg_write_data_pre : std_logic_vector (31 downto 0) := (others=>'0'); signal reg_write_enable : std_logic := '1'; signal mem_output : std_logic_vector (31 downto 0) := (others=>'0'); signal mem_write_data : std_logic_vector (31 downto 0) := (others=>'0'); signal mem_write_enable : std_logic := '1'; signal flags_current, flags_next : std_logic_vector (3 downto 0) := (others=>'0'); signal flags_update : std_logic_vector (1 downto 0) := (others=>'0'); signal alu_function : std_logic_vector (4 downto 0) := (others=>'0'); signal alu_input_1, alu_input_2, alu_output, alu_output_shifted : std_logic_vector (31 downto 0) := (others=>'0'); signal instr_ok, instr_0, instr_1, instr_2, instr_3, instr_4, instr_5, instr_6, instr_7, instr_8, instr_9 : std_logic; signal instr_10, instr_11, instr_12, instr_13, instr_14, instr_15, instr_16, instr_17, instr_18, instr_19 : std_logic; signal stack_finished : std_logic := '0'; signal stack_started : std_logic := '0'; signal listofreg : std_logic_vector (8 downto 0) := (others=>'0'); signal increasedpointer : std_logic_vector (3 downto 0); begin --USELESS instr <= instruction_fetched; --END pc_shifted <= "00" & pc_current(31 downto 2); alu_output_shifted <= "00" & alu_output(31 downto 2); memory_block : memory_no_clk generic map ( N => 29 ) port map ( clk => clk , write_en=> mem_write_enable , addr_1 => pc_shifted , addr_2 => alu_output_shifted , data_w2 => mem_write_data , data_r1 => instruction_fetched , data_r2 => mem_output ); register_block : regfile_no_clk port map ( clk => clk , write_en=> reg_write_enable , addr_r1 => reg_read_addr_1 , addr_r2 => reg_read_addr_2 , addr_w1 => reg_write_addr , data_w1 => reg_write_data , pc_next => pc_next , data_r1 => reg_read_data_1 , data_r2 => reg_read_data_2 , data_pc => pc_current ); alu_block : alu port map ( input_1 => alu_input_1 , input_2 => alu_input_2 , funct => alu_function , flags_current => flags_current , output => alu_output , flags_next => flags_next , flags_update => flags_update ); --PC updating block pc_plus4 <= std_logic_vector( unsigned(pc_current) + 4 ); pc_next <= "00000000000000000000000000000000" when rst = '1' else --reset "00000000000000000000000000001000" when instr_17 = '1' else --SWI int pc_current when instr_14 = '1' and stack_finished = '0' else reg_read_data_2 when instr_5 = '1' and instruction_fetched(9 downto 8) = "11" else alu_output when (instr_16 = '1' and cond_branch = '1') or instr_18 = '1' else pc_plus4; cond_branch <= '1' when (instruction_fetched(11 downto 8) = "0000" and flags_current(2) = '1') or (instruction_fetched(11 downto 8) = "0001" and flags_current(2) = '0') or (instruction_fetched(11 downto 8) = "0010" and flags_current(1) = '1') or (instruction_fetched(11 downto 8) = "0011" and flags_current(1) = '0') or (instruction_fetched(11 downto 8) = "0100" and flags_current(3) = '1') or (instruction_fetched(11 downto 8) = "0101" and flags_current(3) = '0') or (instruction_fetched(11 downto 8) = "0110" and flags_current(0) = '1') or (instruction_fetched(11 downto 8) = "0111" and flags_current(0) = '0') or (instruction_fetched(11 downto 8) = "1000" and flags_current(1) = '1' and flags_current(2) = '0') or (instruction_fetched(11 downto 8) = "1001" and (flags_current(1) = '0' or flags_current(2) = '1')) or (instruction_fetched(11 downto 8) = "1010" and flags_current(3) = flags_current(0)) or (instruction_fetched(11 downto 8) = "1011" and flags_current(3) /= flags_current(0)) or (instruction_fetched(11 downto 8) = "1100" and flags_current(2) = '0' and flags_current(3) = flags_current(0)) or (instruction_fetched(11 downto 8) = "1101" and flags_current(2) = '1' and flags_current(3) /= flags_current(0)) else '0'; --Flags updating block --flag_current(3) == N , flag_current(2) == Z , flag_current(1) == C , flag_current(0) == V process(clk) begin if rising_edge(clk) then case flags_update is --Update mode for flags 0:none 1:NZ 2:NZC 3:NZCV when "01" => flags_current <= flags_next(3 downto 2) & flags_current(1 downto 0); when "10" => flags_current <= flags_next(3 downto 1) & flags_current(0); when "11" => flags_current <= flags_next; when others => flags_current <= flags_current; end case; end if; end process; --Multiple push/pop process(clk) begin if rising_edge(clk) then if instr_14 = '1' then if stack_started = '0' then listofreg <= instruction_fetched(8 downto 0); stack_started <= '1'; else if listofreg(8) = '1' then listofreg(8) <= '0'; if listofreg(7) = '0' and listofreg(6) = '0' and listofreg(5) = '0' and listofreg(4) = '0' and listofreg(3) = '0' and listofreg(2) = '0' and listofreg(1) = '0' and listofreg(0) = '0' then stack_finished <= '1'; end if; elsif listofreg(7) = '1' then listofreg(7) <= '0'; if listofreg(6) = '0' and listofreg(5) = '0' and listofreg(4) = '0' and listofreg(3) = '0' and listofreg(2) = '0' and listofreg(1) = '0' and listofreg(0) = '0' then stack_finished <= '1'; end if; elsif listofreg(6) = '1' then listofreg(6) <= '0'; if listofreg(5) = '0' and listofreg(4) = '0' and listofreg(3) = '0' and listofreg(2) = '0' and listofreg(1) = '0' and listofreg(0) = '0' then stack_finished <= '1'; end if; elsif listofreg(5) = '1' then listofreg(5) <= '0'; if listofreg(4) = '0' and listofreg(3) = '0' and listofreg(2) = '0' and listofreg(1) = '0' and listofreg(0) = '0' then stack_finished <= '1'; end if; elsif listofreg(4) = '1' then listofreg(4) <= '0'; if listofreg(3) = '0' and listofreg(2) = '0' and listofreg(1) = '0' and listofreg(0) = '0' then stack_finished <= '1'; end if; elsif listofreg(3) = '1' then listofreg(3) <= '0'; if listofreg(2) = '0' and listofreg(1) = '0' and listofreg(0) = '0' then stack_finished <= '1'; end if; elsif listofreg(2) = '1' then listofreg(2) <= '0'; if listofreg(1) = '0' and listofreg(0) = '0' then stack_finished <= '1'; end if; elsif listofreg(1) = '1' then listofreg(1) <= '0'; if listofreg(0) = '0' then stack_finished <= '1'; end if; else listofreg(0) <= '0'; stack_finished <= '1'; end if; end if; else stack_started <= '0'; stack_finished <= '0'; end if; end if; end process; increasedpointer <= "1111" when listofreg(8) = '1' and instruction_fetched(11) = '0' else "1110" when listofreg(8) = '1' and instruction_fetched(11) = '1' else "0111" when listofreg(7) = '1' else "0110" when listofreg(6) = '1' else "0101" when listofreg(5) = '1' else "0100" when listofreg(4) = '1' else "0011" when listofreg(3) = '1' else "0010" when listofreg(2) = '1' else "0001" when listofreg(1) = '1' else "0000"; --Register address decoding reg_read_addr_1 <= '0' & instruction_fetched(5 downto 3) when instr_1 = '1' or instr_2 = '1' or instr_7 = '1' else '0' & instruction_fetched(10 downto 8) when instr_3 = '1' else '0' & instruction_fetched(2 downto 0) when instr_4 = '1' or instr_9 = '1' or instr_10 = '1' else instruction_fetched(7) & instruction_fetched(2 downto 0) when instr_5 = '1' else --high reg "1101" when instr_11 = '1' or (instr_12 = '1' and instruction_fetched(11) ='1') or instr_13 = '1' or instr_14 = '1' else --SP "1111" when instr_16 = '1' or instr_18 = '1' else --PC (others=>'0'); reg_read_addr_2 <= '0' & instruction_fetched(8 downto 6) when (instr_2 ='1' and instruction_fetched(10) ='0') or instr_7 = '1' else '0' & instruction_fetched(5 downto 3) when instr_4 ='1' or instr_9 = '1' or instr_10 = '1' else instruction_fetched(6 downto 3) when instr_5 = '1' else --high reg increasedpointer when instr_14 = '1' and instruction_fetched(11) = '0' else (others=>'0'); --ALU input alu_input_1 <= pc_plus4 when instr_6 = '1' or (instr_12 = '1' and instruction_fetched(11) ='0') else "000000000000000000000000000" & instruction_fetched(10 downto 6) when (instr_9 = '1' and instruction_fetched(12) ='1') else "0000000000000000000000000" & instruction_fetched(10 downto 6) & "00" when (instr_9 = '1' and instruction_fetched(12) ='0') else "00000000000000000000000000" & instruction_fetched(10 downto 6) & "0" when instr_10 = '1' else reg_read_data_1; alu_input_2 <= "000000000000000000000000000" & instruction_fetched(10 downto 6) when instr_1 = '1' else "00000000000000000000000000000" & instruction_fetched(8 downto 6) when (instr_2 = '1' and instruction_fetched(10) ='1') else X"000000" & instruction_fetched(7 downto 0) when instr_3 = '1' else "0000000000000000000000" & instruction_fetched(7 downto 0) & "00" when instr_6 = '1' or instr_11 = '1' or instr_12 = '1' else (31 downto 9 => instruction_fetched(7)) & instruction_fetched(6 downto 0) & "00" when instr_13 = '1' else "00000000000000000000000" & instruction_fetched(7 downto 0) & '0' when instr_16 = '1' else (31 downto 12 => instruction_fetched(10)) & instruction_fetched(10 downto 0) & '0' when instr_18 = '1' else (31 downto 3 => '0') & "100" when instr_14 = '1' else --SP +- 4 reg_read_data_2; --FIX OP CODE --0000 AND,0001 EOR,0010 LSL,0011 LSR,0100 ASR,0101 ADC,0110 SBC,0111 ROR, --1000 TST,1001 NEG,1010 CMP,1011 CMN,1100 ORR,1101 MUL,1110 BIC,1111 MVN alu_function <= "0" & instruction_fetched(9 downto 6) when instr_4 = '1' else "00010" when (instr_1 = '1' and instruction_fetched(12 downto 11) = "00") else --LSL "00011" when (instr_1 = '1' and instruction_fetched(12 downto 11) = "01") else --LSR "00100" when (instr_1 = '1' and instruction_fetched(12 downto 11) = "10") else --ASR "10000" when (instr_3 = '1' and instruction_fetched(12 downto 11) = "00") or (instr_5 = '1' and instruction_fetched(12 downto 11) = "10") else --MOV "01010" when (instr_3 = '1' and instruction_fetched(12 downto 11) = "01") or (instr_5 = '1' and instruction_fetched(12 downto 11) = "01") else --CMP "10001" when (instr_2 = '1' and instruction_fetched(9) = '0') or (instr_3 = '1' and instruction_fetched(12 downto 11) = "10") or (instr_13 = '1' and instruction_fetched(7) ='0') or (instr_5 = '1' and instruction_fetched(12 downto 11) = "00") or instr_6 = '1' or instr_7 = '1' or instr_9 = '1' or instr_10 = '1' or instr_11 = '1' or instr_12 = '1' or instr_16 = '1' or instr_18 = '1' or (instr_14 = '1' and instruction_fetched(11) = '1') else --ADD "10010" when (instr_2 = '1' and instruction_fetched(9) = '1') or (instr_3 = '1' and instruction_fetched(12 downto 11) = "11") or (instr_13 = '1' and instruction_fetched(7) ='1') or (instr_14 = '1' and instruction_fetched(11) = '0') else --SUB (others=>'1'); --Memory write port mem_write_enable <= '1' when (instr_9 = '1' and instruction_fetched(11) = '0') or (instr_10 = '1' and instruction_fetched(11) = '0') or (instr_11 = '1' and instruction_fetched(11) = '0') or (instr_14 = '1' and instruction_fetched(11) = '0' and stack_started = '1') else '0'; mem_write_data <= X"000000" & reg_read_data_1(7 downto 0) when (instr_9 = '1' and instruction_fetched(12) = '1') else X"0000" & reg_read_data_1(15 downto 0) when instr_10 = '1' else reg_read_data_2 when instr_14 = '1' and instruction_fetched(11) = '0' else reg_read_data_1; --Register write port reg_write_enable <= '0' when (instr_9 = '1' and instruction_fetched(11) = '0') or (instr_5 = '1' and instruction_fetched(9 downto 8) = "11") or (instr_10 = '1' and instruction_fetched(11) = '0') or (instr_11 = '1' and instruction_fetched(11) = '0') or instr_16 = '1' or instr_18 = '1' or instr_0 = '1' or (instr_14 = '1' and instruction_fetched(11) = '0' and stack_started = '0') else '1'; reg_write_addr <= '0' & instruction_fetched(2 downto 0) when instr_1 = '1' or instr_2 = '1' or instr_4 = '1' or instr_7 = '1' or instr_9 = '1' or instr_10 = '1' else '0' & instruction_fetched(10 downto 8) when instr_3 = '1' or instr_6 = '1' or instr_11 = '1' or instr_12 = '1' else instruction_fetched(7) & instruction_fetched(2 downto 0) when instr_5 = '1' else "1101" when instr_13 = '1' or (instr_14 = '1' and instruction_fetched(11) = '0' and stack_started = '1') else "1110" when instr_17 = '1' else (others=>'0'); reg_write_data_pre <= mem_output when instr_6 = '1' or instr_7 = '1' or instr_9 = '1' or instr_10 = '1' or instr_11 = '1' else pc_plus4 when instr_17 = '1' else alu_output; reg_write_data <= X"000000" & reg_write_data_pre(7 downto 0) when (instr_7 = '1' and instruction_fetched(10) = '1') or (instr_9 = '1' and instruction_fetched(12) = '1') else X"0000" & reg_write_data_pre(15 downto 0) when instr_10 = '1' else reg_write_data_pre; --Instruction basic decoding into 19 groups, depending on the format of instructions instr_ok <= '1' when instruction_fetched(31 downto 16) = (31 downto 16 => '0') else '0'; instr_0 <= '1' when instruction_fetched(31 downto 0) = (31 downto 0 => '0') else '0'; --nop instr_1 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 13) = "000" and instruction_fetched(12 downto 11) /= "11" else '0'; instr_2 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 13) = "000" and instruction_fetched(12 downto 11) = "11" else '0'; instr_3 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 13) = "001" else '0'; instr_4 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 10) = "010000" else '0'; instr_5 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 10) = "010001" else '0'; instr_6 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 11) = "01001" else '0'; instr_7 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "0101" and instruction_fetched(9) = '0' else '0'; --only implemented LDR, STR not working instr_8 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "0101" and instruction_fetched(9) = '1' else '0'; --not implemented instr_9 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 13) = "011" else '0'; instr_10 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "1000" else '0'; instr_11 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "1001" else '0'; instr_12 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "1010" else '0'; instr_13 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 8 ) = "10110000" else '0'; --only implemented +offset, ignoring sign instr_14 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "1011" and instruction_fetched(10 downto 9) = "10" else '0'; --multiple push implemented, multiple pop not instr_15 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "1100" else '0'; --TODO instr_16 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "1101" and instruction_fetched(11 downto 8) /= "1111" else '0'; instr_17 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 8 ) = "11011111" else '0'; --CPSR->SPSR not implemented, only thumb mode enable instr_18 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 11) = "11100" else '0'; instr_19 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "1111" else '0'; --TODO end Behavioral;
architecture test of test2 is constant foo, foo2 : bar := baz; begin end;
architecture rtl of fifo is begin my_signal <= '1' when input = "00" else my_signal2 or my_sig3 when input = "01" else my_sig4 and my_sig5 when input = "10" else '0'; my_signal <= '1' when input = "0000" else my_signal2 or my_sig3 when input = "0100" and input = "1100" else my_sig4 when input = "0010" else '0'; my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else '0' when input(3 downto 0) = "0010" else 'Z'; my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else '0' when input(3 downto 0) = "0010" else 'Z'; my_signal <= '1' when a = "0000" and func1(345) or b = "1000" and func2(567) and c = "00" else sig1 when a = "1000" and func2(560) and b = "0010" else '0'; my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; -- Testing no code after assignment my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; my_signal <= (others => '0') when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; end architecture rtl;
----------------------------------------------------------------------------- -- File: leaves.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: A set of multipliers generated from the Arithmetic Module -- Generator at Norwegian University of Science and Technology. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; package blocks is component FLIPFLOP port ( DIN, CLK: in std_logic; DOUT: out std_logic ); end component; component DBLCADDER_32_32 port(OPA: in std_logic_vector(0 to 31); OPB: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; SUM: out std_logic_vector(0 to 31); COUT: out std_logic); end component; component FULL_ADDER port ( DATA_A, DATA_B, DATA_C: in std_logic; SAVE, CARRY: out std_logic ); end component; component HALF_ADDER port ( DATA_A, DATA_B: in std_logic; SAVE, CARRY: out std_logic ); end component; component R_GATE port ( INA, INB, INC: in std_logic; PPBIT: out std_logic ); end component; component DECODER port ( INA, INB, INC: in std_logic; TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic ); end component; component PP_LOW port ( ONEPOS, ONENEG, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end component; component PP_MIDDLE port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB, INC, IND: in std_logic; PPBIT: out std_logic ); end component; component PP_HIGH port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end component; component BLOCK0 port ( A,B,PHI: in std_logic; POUT,GOUT: out std_logic ); end component; component INVBLOCK port ( GIN,PHI:in std_logic; GOUT:out std_logic ); end component; component BLOCK1 port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end component; component BLOCK1A port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end component; component BLOCK2 port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end component; component BLOCK2A port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end component; component PRESTAGE_32 port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 31); GOUT: out std_logic_vector(0 to 32) ); end component; component XXOR1 port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end component; component XXOR2 port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end component; component DBLCTREE_32 port ( PIN:in std_logic_vector(0 to 31); GIN:in std_logic_vector(0 to 32); PHI:in std_logic; GOUT:out std_logic_vector(0 to 32); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_32 port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 32); SUM: out std_logic_vector(0 to 31); COUT: out std_logic ); end component; component DBLC_0_32 port ( PIN: in std_logic_vector(0 to 31); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 30); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_1_32 port ( PIN: in std_logic_vector(0 to 30); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 28); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_2_32 port ( PIN: in std_logic_vector(0 to 28); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 24); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_3_32 port ( PIN: in std_logic_vector(0 to 24); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 16); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_4_32 port ( PIN: in std_logic_vector(0 to 16); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 32) ); end component; component PRESTAGE_64 port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 63); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLCTREE_64 port ( PIN:in std_logic_vector(0 to 63); GIN:in std_logic_vector(0 to 64); PHI:in std_logic; GOUT:out std_logic_vector(0 to 64); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_64 port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 64); SUM: out std_logic_vector(0 to 63); COUT: out std_logic ); end component; component DBLC_0_64 port ( PIN: in std_logic_vector(0 to 63); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 62); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_1_64 port ( PIN: in std_logic_vector(0 to 62); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 60); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_2_64 port ( PIN: in std_logic_vector(0 to 60); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 56); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_3_64 port ( PIN: in std_logic_vector(0 to 56); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 48); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_4_64 port ( PIN: in std_logic_vector(0 to 48); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 32); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_5_64 port ( PIN: in std_logic_vector(0 to 32); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_0_128 port ( PIN: in std_logic_vector(0 to 127); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 126); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_1_128 port ( PIN: in std_logic_vector(0 to 126); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 124); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_2_128 port ( PIN: in std_logic_vector(0 to 124); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 120); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_3_128 port ( PIN: in std_logic_vector(0 to 120); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 112); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_4_128 port ( PIN: in std_logic_vector(0 to 112); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 96); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_5_128 port ( PIN: in std_logic_vector(0 to 96); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 64); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_6_128 port ( PIN: in std_logic_vector(0 to 64); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 128) ); end component; component PRESTAGE_128 port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 127); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLCTREE_128 port ( PIN:in std_logic_vector(0 to 127); GIN:in std_logic_vector(0 to 128); PHI:in std_logic; GOUT:out std_logic_vector(0 to 128); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_128 port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 128); SUM: out std_logic_vector(0 to 127); COUT: out std_logic ); end component; component BOOTHCODER_18_18 port ( OPA: in std_logic_vector(0 to 17); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 188) ); end component; component WALLACE_18_18 port ( SUMMAND: in std_logic_vector(0 to 188); CARRY: out std_logic_vector(0 to 33); SUM: out std_logic_vector(0 to 34) ); end component; component DBLCADDER_64_64 port ( OPA:in std_logic_vector(0 to 63); OPB:in std_logic_vector(0 to 63); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 63); COUT:out std_logic ); end component; component BOOTHCODER_34_10 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 9); SUMMAND: out std_logic_vector(0 to 184) ); end component; component WALLACE_34_10 port ( SUMMAND: in std_logic_vector(0 to 184); CARRY: out std_logic_vector(0 to 41); SUM: out std_logic_vector(0 to 42) ); end component; component BOOTHCODER_34_18 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 332) ); end component; component WALLACE_34_18 port ( SUMMAND: in std_logic_vector(0 to 332); CARRY: out std_logic_vector(0 to 49); SUM: out std_logic_vector(0 to 50) ); end component; component BOOTHCODER_34_34 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 33); SUMMAND: out std_logic_vector(0 to 628) ); end component; component WALLACE_34_34 port ( SUMMAND: in std_logic_vector(0 to 628); CARRY: out std_logic_vector(0 to 65); SUM: out std_logic_vector(0 to 66) ); end component; component DBLCADDER_128_128 port ( OPA:in std_logic_vector(0 to 127); OPB:in std_logic_vector(0 to 127); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 127); COUT:out std_logic ); end component; component MULTIPLIER_18_18 generic (mulpipe : integer := 0); port(MULTIPLICAND: in std_logic_vector(0 to 17); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_ulogic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_10 port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 9); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_18 port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_34 generic (mulpipe : integer := 0); port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 33); PHI: in std_logic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 127)); end component; end; ------------------------------------------------------------ -- START: Entities used within the Modified Booth Recoding ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity FLIPFLOP is port ( DIN: in std_logic; CLK: in std_logic; DOUT: out std_logic ); end FLIPFLOP; architecture FLIPFLOP of FLIPFLOP is begin process(CLK) begin if(CLK='1')and(CLK'event)then DOUT <= DIN; end if; end process; end FLIPFLOP; library ieee; use ieee.std_logic_1164.all; entity PP_LOW is port ( ONEPOS, ONENEG, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end PP_LOW; architecture PP_LOW of PP_LOW is begin PPBIT <= (ONEPOS and INA) or (ONENEG and INB) or TWONEG; end PP_LOW; library ieee; use ieee.std_logic_1164.all; entity PP_MIDDLE is port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB, INC, IND: in std_logic; PPBIT: out std_logic ); end PP_MIDDLE; architecture PP_MIDDLE of PP_MIDDLE is begin PPBIT <= not((not(INA and TWOPOS)) and (not(INB and TWONEG)) and (not(INC and ONEPOS)) and (not(IND and ONENEG))); end PP_MIDDLE; library ieee; use ieee.std_logic_1164.all; entity PP_HIGH is port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end PP_HIGH; architecture PP_HIGH of PP_HIGH is begin PPBIT <= not ((INA and ONEPOS) or (INB and ONENEG) or (INA and TWOPOS) or (INB and TWONEG)); end PP_HIGH; library ieee; use ieee.std_logic_1164.all; entity R_GATE is port ( INA, INB, INC: in std_logic; PPBIT: out std_logic ); end R_GATE; architecture R_GATE of R_GATE is begin PPBIT <= (not(INA and INB)) and INC; end R_GATE; library ieee; use ieee.std_logic_1164.all; entity DECODER is port ( INA, INB, INC: in std_logic; TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic ); end DECODER; architecture DECODER of DECODER is begin TWOPOS <= not(not(INA and INB and (not INC))); TWONEG <= not(not((not INA) and (not INB) and INC)); ONEPOS <= ((not INA) and INB and (not INC)) or ((not INC) and (not INB) and INA); ONENEG <= (INA and (not INB) and INC) or (INC and INB and (not INA)); end DECODER; library ieee; use ieee.std_logic_1164.all; entity FULL_ADDER is port ( DATA_A, DATA_B, DATA_C: in std_logic; SAVE, CARRY: out std_logic ); end FULL_ADDER; architecture FULL_ADDER of FULL_ADDER is signal TMP: std_logic; begin TMP <= DATA_A xor DATA_B; SAVE <= TMP xor DATA_C; CARRY <= not((not (TMP and DATA_C)) and (not (DATA_A and DATA_B))); end FULL_ADDER; library ieee; use ieee.std_logic_1164.all; entity HALF_ADDER is port ( DATA_A, DATA_B: in std_logic; SAVE, CARRY: out std_logic ); end HALF_ADDER; architecture HALF_ADDER of HALF_ADDER is begin SAVE <= DATA_A xor DATA_B; CARRY <= DATA_A and DATA_B; end HALF_ADDER; library ieee; use ieee.std_logic_1164.all; entity INVBLOCK is port ( GIN,PHI:in std_logic; GOUT:out std_logic ); end INVBLOCK; architecture INVBLOCK_regular of INVBLOCK is begin GOUT <= not GIN; end INVBLOCK_regular; library ieee; use ieee.std_logic_1164.all; entity XXOR1 is port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end XXOR1; architecture XXOR_regular of XXOR1 is begin SUM <= (not (A xor B)) xor GIN; end XXOR_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK0 is port ( A,B,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK0; architecture BLOCK0_regular of BLOCK0 is begin POUT <= not(A or B); GOUT <= not(A and B); end BLOCK0_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK1 is port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK1; architecture BLOCK1_regular of BLOCK1 is begin POUT <= not(PIN1 or PIN2); GOUT <= not(GIN2 and (PIN2 or GIN1)); end BLOCK1_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK2 is port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK2; architecture BLOCK2_regular of BLOCK2 is begin POUT <= not(PIN1 and PIN2); GOUT <= not(GIN2 or (PIN2 and GIN1)); end BLOCK2_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK1A is port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end BLOCK1A; architecture BLOCK1A_regular of BLOCK1A is begin GOUT <= not(GIN2 and (PIN2 or GIN1)); end BLOCK1A_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK2A is port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end BLOCK2A; architecture BLOCK2A_regular of BLOCK2A is begin GOUT <= not(GIN2 or (PIN2 and GIN1)); end BLOCK2A_regular; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_64 is port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 63); GOUT: out std_logic_vector(0 to 64) ); end PRESTAGE_64; architecture PRESTAGE of PRESTAGE_64 is begin -- PRESTAGE U1:for I in 0 to 63 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: Level 0 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_64 is port ( PIN: in std_logic_vector(0 to 63); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 62); GOUT: out std_logic_vector(0 to 64) ); end DBLC_0_64; architecture DBLC_0 of DBLC_0_64 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 64 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_64 is port ( PIN: in std_logic_vector(0 to 62); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 60); GOUT: out std_logic_vector(0 to 64) ); end DBLC_1_64; architecture DBLC_1 of DBLC_1_64 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 64 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_64 is port ( PIN: in std_logic_vector(0 to 60); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 56); GOUT: out std_logic_vector(0 to 64) ); end DBLC_2_64; architecture DBLC_2 of DBLC_2_64 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 64 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_64 is port ( PIN: in std_logic_vector(0 to 56); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 48); GOUT: out std_logic_vector(0 to 64) ); end DBLC_3_64; architecture DBLC_3 of DBLC_3_64 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 64 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_64 is port ( PIN: in std_logic_vector(0 to 48); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 32); GOUT: out std_logic_vector(0 to 64) ); end DBLC_4_64; architecture DBLC_4 of DBLC_4_64 is begin -- Architecture DBLC_4 U1: for I in 0 to 15 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 64 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; -- The DBLC-tree: Level 5 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_5_64 is port ( PIN: in std_logic_vector(0 to 32); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 64) ); end DBLC_5_64; architecture DBLC_5 of DBLC_5_64 is begin -- Architecture DBLC_5 U1: for I in 0 to 31 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 32 to 63 generate U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 64 to 64 generate U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I)); end generate U3; end DBLC_5; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_64 is port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 64); SUM: out std_logic_vector(0 to 63); COUT: out std_logic ); end XORSTAGE_64; architecture XORSTAGE of XORSTAGE_64 is begin -- XORSTAGE U2:for I in 0 to 63 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U1: BLOCK1A port map(PBIT,CARRY(0),CARRY(64),PHI,COUT); end XORSTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_64 is port ( PIN:in std_logic_vector(0 to 63); GIN:in std_logic_vector(0 to 64); PHI:in std_logic; GOUT:out std_logic_vector(0 to 64); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_64; architecture DBLCTREE of DBLCTREE_64 is signal INTPROP_0: std_logic_vector(0 to 62); signal INTGEN_0: std_logic_vector(0 to 64); signal INTPROP_1: std_logic_vector(0 to 60); signal INTGEN_1: std_logic_vector(0 to 64); signal INTPROP_2: std_logic_vector(0 to 56); signal INTGEN_2: std_logic_vector(0 to 64); signal INTPROP_3: std_logic_vector(0 to 48); signal INTGEN_3: std_logic_vector(0 to 64); signal INTPROP_4: std_logic_vector(0 to 32); signal INTGEN_4: std_logic_vector(0 to 64); begin -- Architecture DBLCTREE U_0: DBLC_0_64 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_64 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_64 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_64 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_64 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4); U_5: DBLC_5_64 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_64_64 is port ( OPA:in std_logic_vector(0 to 63); OPB:in std_logic_vector(0 to 63); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 63); COUT:out std_logic ); end DBLCADDER_64_64; architecture DBLCADDER of DBLCADDER_64_64 is signal INTPROP: std_logic_vector(0 to 63); signal INTGEN: std_logic_vector(0 to 64); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 64); begin -- Architecture DBLCADDER U1: PRESTAGE_64 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_64 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_64 port map(OPA(0 to 63),OPB(0 to 63),PBIT(0),PHI,CARRY(0 to 64),SUM,COUT); end DBLCADDER; ------------------------------------------------------------ -- END: Architectures used with the DBLC adder ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity XXOR2 is port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end XXOR2; architecture XXOR_true of XXOR2 is begin SUM <= (A xor B) xor GIN; end XXOR_true; -- -- Modgen adder created Fri Aug 16 14:47:23 2002 -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_32 is port ( PIN: in std_logic_vector(0 to 31); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 30); GOUT: out std_logic_vector(0 to 32) ); end DBLC_0_32; architecture DBLC_0 of DBLC_0_32 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 32 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_32 is port ( PIN: in std_logic_vector(0 to 30); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 28); GOUT: out std_logic_vector(0 to 32) ); end DBLC_1_32; architecture DBLC_1 of DBLC_1_32 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 32 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_32 is port ( PIN: in std_logic_vector(0 to 28); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 24); GOUT: out std_logic_vector(0 to 32) ); end DBLC_2_32; architecture DBLC_2 of DBLC_2_32 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 32 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_32 is port ( PIN: in std_logic_vector(0 to 24); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 16); GOUT: out std_logic_vector(0 to 32) ); end DBLC_3_32; architecture DBLC_3 of DBLC_3_32 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 32 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_32 is port ( PIN: in std_logic_vector(0 to 16); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 32) ); end DBLC_4_32; architecture DBLC_4 of DBLC_4_32 is begin -- Architecture DBLC_4 GOUT(0 to 15) <= GIN(0 to 15); U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 32 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_32 is port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 32); SUM: out std_logic_vector(0 to 31); COUT: out std_logic ); end XORSTAGE_32; architecture XORSTAGE of XORSTAGE_32 is begin -- XORSTAGE U2:for I in 0 to 15 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U3:for I in 16 to 31 generate U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U3; U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(32),PHI,COUT); end XORSTAGE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_32 is port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 31); GOUT: out std_logic_vector(0 to 32) ); end PRESTAGE_32; architecture PRESTAGE of PRESTAGE_32 is begin -- PRESTAGE U1:for I in 0 to 31 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_32 is port ( PIN:in std_logic_vector(0 to 31); GIN:in std_logic_vector(0 to 32); PHI:in std_logic; GOUT:out std_logic_vector(0 to 32); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_32; architecture DBLCTREE of DBLCTREE_32 is signal INTPROP_0: std_logic_vector(0 to 30); signal INTGEN_0: std_logic_vector(0 to 32); signal INTPROP_1: std_logic_vector(0 to 28); signal INTGEN_1: std_logic_vector(0 to 32); signal INTPROP_2: std_logic_vector(0 to 24); signal INTGEN_2: std_logic_vector(0 to 32); signal INTPROP_3: std_logic_vector(0 to 16); signal INTGEN_3: std_logic_vector(0 to 32); begin -- Architecture DBLCTREE U_0: DBLC_0_32 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_32 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_32 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_32 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_32 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_32_32 is port ( OPA:in std_logic_vector(0 to 31); OPB:in std_logic_vector(0 to 31); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 31); COUT:out std_logic ); end DBLCADDER_32_32; architecture DBLCADDER of DBLCADDER_32_32 is signal INTPROP: std_logic_vector(0 to 31); signal INTGEN: std_logic_vector(0 to 32); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 32); begin -- Architecture DBLCADDER U1: PRESTAGE_32 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_32 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_32 port map(OPA(0 to 31),OPB(0 to 31),PBIT(0),PHI,CARRY(0 to 32),SUM,COUT); end DBLCADDER; ------------------------------------------------------------ -- END: Architectures used with the DBLC adder ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_128 is port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 127); GOUT: out std_logic_vector(0 to 128) ); end PRESTAGE_128; architecture PRESTAGE of PRESTAGE_128 is begin -- PRESTAGE U1:for I in 0 to 127 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: Level 0 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_128 is port ( PIN: in std_logic_vector(0 to 127); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 126); GOUT: out std_logic_vector(0 to 128) ); end DBLC_0_128; architecture DBLC_0 of DBLC_0_128 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 128 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_128 is port ( PIN: in std_logic_vector(0 to 126); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 124); GOUT: out std_logic_vector(0 to 128) ); end DBLC_1_128; architecture DBLC_1 of DBLC_1_128 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 128 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_128 is port ( PIN: in std_logic_vector(0 to 124); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 120); GOUT: out std_logic_vector(0 to 128) ); end DBLC_2_128; architecture DBLC_2 of DBLC_2_128 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 128 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_128 is port ( PIN: in std_logic_vector(0 to 120); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 112); GOUT: out std_logic_vector(0 to 128) ); end DBLC_3_128; architecture DBLC_3 of DBLC_3_128 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 128 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_128 is port ( PIN: in std_logic_vector(0 to 112); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 96); GOUT: out std_logic_vector(0 to 128) ); end DBLC_4_128; architecture DBLC_4 of DBLC_4_128 is begin -- Architecture DBLC_4 U1: for I in 0 to 15 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 128 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; -- The DBLC-tree: Level 5 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_5_128 is port ( PIN: in std_logic_vector(0 to 96); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 64); GOUT: out std_logic_vector(0 to 128) ); end DBLC_5_128; architecture DBLC_5 of DBLC_5_128 is begin -- Architecture DBLC_5 U1: for I in 0 to 31 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 32 to 63 generate U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 64 to 128 generate U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I)); end generate U3; end DBLC_5; -- The DBLC-tree: Level 6 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_6_128 is port ( PIN: in std_logic_vector(0 to 64); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 128) ); end DBLC_6_128; architecture DBLC_6 of DBLC_6_128 is begin -- Architecture DBLC_6 GOUT(0 to 63) <= GIN(0 to 63); U2: for I in 64 to 127 generate U21: BLOCK1A port map(PIN(I-64),GIN(I-64),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 128 to 128 generate U31: BLOCK1 port map(PIN(I-128),PIN(I-64),GIN(I-64),GIN(I),PHI,POUT(I-128),GOUT(I)); end generate U3; end DBLC_6; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_128 is port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 128); SUM: out std_logic_vector(0 to 127); COUT: out std_logic ); end XORSTAGE_128; architecture XORSTAGE of XORSTAGE_128 is begin -- XORSTAGE U2:for I in 0 to 63 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U3:for I in 64 to 127 generate U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U3; U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(128),PHI,COUT); end XORSTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_128 is port ( PIN:in std_logic_vector(0 to 127); GIN:in std_logic_vector(0 to 128); PHI:in std_logic; GOUT:out std_logic_vector(0 to 128); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_128; architecture DBLCTREE of DBLCTREE_128 is signal INTPROP_0: std_logic_vector(0 to 126); signal INTGEN_0: std_logic_vector(0 to 128); signal INTPROP_1: std_logic_vector(0 to 124); signal INTGEN_1: std_logic_vector(0 to 128); signal INTPROP_2: std_logic_vector(0 to 120); signal INTGEN_2: std_logic_vector(0 to 128); signal INTPROP_3: std_logic_vector(0 to 112); signal INTGEN_3: std_logic_vector(0 to 128); signal INTPROP_4: std_logic_vector(0 to 96); signal INTGEN_4: std_logic_vector(0 to 128); signal INTPROP_5: std_logic_vector(0 to 64); signal INTGEN_5: std_logic_vector(0 to 128); begin -- Architecture DBLCTREE U_0: DBLC_0_128 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_128 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_128 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_128 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_128 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4); U_5: DBLC_5_128 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>INTPROP_5,GOUT=>INTGEN_5); U_6: DBLC_6_128 port map(PIN=>INTPROP_5,GIN=>INTGEN_5,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_128_128 is port ( OPA:in std_logic_vector(0 to 127); OPB:in std_logic_vector(0 to 127); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 127); COUT:out std_logic ); end DBLCADDER_128_128; architecture DBLCADDER of DBLCADDER_128_128 is signal INTPROP: std_logic_vector(0 to 127); signal INTGEN: std_logic_vector(0 to 128); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 128); begin -- Architecture DBLCADDER U1: PRESTAGE_128 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_128 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_128 port map(OPA(0 to 127),OPB(0 to 127),PBIT(0),PHI,CARRY(0 to 128),SUM,COUT); end DBLCADDER; -- -- Modified Booth algorithm architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_18_18 is port ( OPA: in std_logic_vector(0 to 17); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 188) ); end BOOTHCODER_18_18; ------------------------------------------------------------ -- END: Entities used within the Modified Booth Recoding ------------------------------------------------------------ architecture BOOTHCODER of BOOTHCODER_18_18 is -- Components used in the architecture -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 17); signal INT_MULTIPLIER: std_logic_vector(0 to 35); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); PPH_0:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); SUMMAND(100) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_17:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_18:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_19:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_20:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_21:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_22:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_23:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_24:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_25:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_26:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_27:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_28:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_29:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_30:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_31:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_32:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(101) ); PPM_33:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(109) ); SUMMAND(110) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(118) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_34:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_35:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_36:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_37:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_38:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_39:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_40:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_41:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_42:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_43:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_44:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_45:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_46:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_47:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(102) ); PPM_48:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(111) ); PPM_49:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(119) ); PPM_50:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(126) ); SUMMAND(127) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(134) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_51:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_52:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_53:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_54:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_55:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_56:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_57:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_58:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_59:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_60:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_61:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_62:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(103) ); PPM_63:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(112) ); PPM_64:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(120) ); PPM_65:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(128) ); PPM_66:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(135) ); PPM_67:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(141) ); SUMMAND(142) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(148) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_68:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_69:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_70:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_71:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_72:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_73:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_74:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_75:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_76:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_77:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(104) ); PPM_78:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(113) ); PPM_79:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(121) ); PPM_80:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(129) ); PPM_81:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(136) ); PPM_82:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(143) ); PPM_83:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(149) ); PPM_84:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(154) ); SUMMAND(155) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_85:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_86:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_87:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_88:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_89:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_90:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_91:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_92:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(105) ); PPM_93:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(114) ); PPM_94:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(122) ); PPM_95:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(130) ); PPM_96:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(137) ); PPM_97:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(144) ); PPM_98:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(150) ); PPM_99:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(156) ); PPM_100:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(161) ); PPM_101:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(165) ); SUMMAND(166) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(170) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_102:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_103:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_104:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_105:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_106:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_107:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(106) ); PPM_108:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(115) ); PPM_109:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(123) ); PPM_110:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(131) ); PPM_111:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(138) ); PPM_112:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(145) ); PPM_113:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(151) ); PPM_114:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(157) ); PPM_115:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(162) ); PPM_116:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(167) ); PPM_117:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(171) ); PPM_118:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(174) ); SUMMAND(175) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(178) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_119:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_120:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_121:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_122:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(107) ); PPM_123:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(116) ); PPM_124:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(124) ); PPM_125:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(132) ); PPM_126:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(139) ); PPM_127:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(146) ); PPM_128:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(152) ); PPM_129:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(158) ); PPM_130:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(163) ); PPM_131:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(168) ); PPM_132:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(172) ); PPM_133:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(176) ); PPM_134:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(179) ); PPM_135:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(181) ); SUMMAND(182) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(184) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_136:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_137:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(108) ); PPM_138:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(117) ); PPM_139:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(125) ); PPM_140:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(133) ); PPM_141:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(140) ); PPM_142:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(147) ); PPM_143:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(153) ); PPM_144:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(159) ); PPM_145:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(164) ); PPM_146:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(169) ); PPM_147:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(173) ); PPM_148:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(177) ); PPM_149:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(180) ); PPM_150:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(183) ); PPM_151:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(185) ); PPM_152:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(186) ); SUMMAND(187) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(188) ); -- Begin partial product 9 end BOOTHCODER; ------------------------------------------------------------ -- END: Architectures used with the Modified Booth recoding ------------------------------------------------------------ -- -- Wallace tree architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_18_18 is port ( SUMMAND: in std_logic_vector(0 to 188); CARRY: out std_logic_vector(0 to 33); SUM: out std_logic_vector(0 to 34) ); end WALLACE_18_18; ------------------------------------------------------------ -- END: Entities within the Wallace-tree ------------------------------------------------------------ architecture WALLACE of WALLACE_18_18 is -- Components used in the netlist -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 114); signal INT_SUM: std_logic_vector(0 to 158); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin NO stage INT_SUM(76) <= SUMMAND(108); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(77), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_CARRY(49), DATA_C => INT_CARRY(50), SAVE => INT_SUM(78), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(51); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(77), DATA_B => INT_SUM(78), DATA_C => INT_SUM(79), SAVE => INT_SUM(80), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin NO stage INT_SUM(81) <= INT_CARRY(52); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(82) <= INT_CARRY(53); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_SUM(82), SAVE => INT_SUM(83), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin NO stage INT_SUM(84) <= INT_CARRY(54); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_64:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(83), DATA_B => INT_SUM(84), DATA_C => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End FA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_65:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(109), DATA_B => SUMMAND(110), DATA_C => SUMMAND(111), SAVE => INT_SUM(85), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(112), DATA_B => SUMMAND(113), DATA_C => SUMMAND(114), SAVE => INT_SUM(86), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117), SAVE => INT_SUM(87), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58), SAVE => INT_SUM(88), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(59), DATA_C => INT_CARRY(60), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_CARRY(61), SAVE => INT_SUM(91), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(91), DATA_B => INT_CARRY(62), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End HA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_72:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), DATA_C => SUMMAND(120), SAVE => INT_SUM(92), CARRY => INT_CARRY(70) ); ---- End FA stage ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(121), DATA_B => SUMMAND(122), DATA_C => SUMMAND(123), SAVE => INT_SUM(93), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(94) <= SUMMAND(124); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(95) <= SUMMAND(125); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_SUM(94), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin NO stage INT_SUM(97) <= INT_SUM(95); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(63), SAVE => INT_SUM(98), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(64), DATA_B => INT_CARRY(65), DATA_C => INT_CARRY(66), SAVE => INT_SUM(99), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(67), SAVE => INT_SUM(100), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin NO stage INT_SUM(101) <= INT_CARRY(68); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(69), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_79:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(102), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(103), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => INT_CARRY(70), SAVE => INT_SUM(104), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin NO stage INT_SUM(105) <= INT_CARRY(71); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_82:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_SUM(104), SAVE => INT_SUM(106), CARRY => INT_CARRY(79) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(105), DATA_B => INT_CARRY(72), SAVE => INT_SUM(107), CARRY => INT_CARRY(80) ); ---- End HA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(73), SAVE => INT_SUM(108), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin NO stage INT_SUM(109) <= INT_CARRY(74); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(75), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(134), DATA_B => SUMMAND(135), DATA_C => SUMMAND(136), SAVE => INT_SUM(110), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(137), DATA_B => SUMMAND(138), DATA_C => SUMMAND(139), SAVE => INT_SUM(111), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(112) <= SUMMAND(140); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_SUM(112), SAVE => INT_SUM(113), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), DATA_C => INT_CARRY(78), SAVE => INT_SUM(114), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_CARRY(79), SAVE => INT_SUM(115), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin NO stage INT_SUM(116) <= INT_CARRY(80); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(81), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_91:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143), SAVE => INT_SUM(117), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin FA stage FA_92:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146), SAVE => INT_SUM(118), CARRY => INT_CARRY(88) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= SUMMAND(147); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_SUM(119), SAVE => INT_SUM(120), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83), SAVE => INT_SUM(121), CARRY => INT_CARRY(90) ); ---- End HA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(84), SAVE => INT_SUM(122), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= INT_CARRY(85); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(86), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), DATA_C => SUMMAND(150), SAVE => INT_SUM(124), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(151), DATA_B => SUMMAND(152), DATA_C => SUMMAND(153), SAVE => INT_SUM(125), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(87), SAVE => INT_SUM(126), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin NO stage INT_SUM(127) <= INT_CARRY(88); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_99:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(89), SAVE => INT_SUM(128), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin NO stage INT_SUM(129) <= INT_CARRY(90); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(91), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_101:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(154), DATA_B => SUMMAND(155), DATA_C => SUMMAND(156), SAVE => INT_SUM(130), CARRY => INT_CARRY(96) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(157), DATA_B => SUMMAND(158), DATA_C => SUMMAND(159), SAVE => INT_SUM(131), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), DATA_C => INT_CARRY(92), SAVE => INT_SUM(132), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin NO stage INT_SUM(133) <= INT_CARRY(93); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(94), SAVE => INT_SUM(134), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(134), DATA_B => INT_CARRY(95), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End HA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_105:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(160), DATA_B => SUMMAND(161), DATA_C => SUMMAND(162), SAVE => INT_SUM(135), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(163), DATA_B => SUMMAND(164), SAVE => INT_SUM(136), CARRY => INT_CARRY(101) ); ---- End HA stage ---- Begin FA stage FA_106:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_CARRY(96), SAVE => INT_SUM(137), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin NO stage INT_SUM(138) <= INT_CARRY(97); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_CARRY(98), SAVE => INT_SUM(139), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(139), DATA_B => INT_CARRY(99), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_108:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(140), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), SAVE => INT_SUM(141), CARRY => INT_CARRY(105) ); ---- End HA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(100), SAVE => INT_SUM(142), CARRY => INT_CARRY(106) ); ---- End FA stage ---- Begin NO stage INT_SUM(143) <= INT_CARRY(101); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(102), SAVE => INT_SUM(144), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(144), DATA_B => INT_CARRY(103), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End HA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_111:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172), SAVE => INT_SUM(145), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(173), DATA_B => INT_CARRY(104), DATA_C => INT_CARRY(105), SAVE => INT_SUM(146), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin FA stage FA_113:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(106), SAVE => INT_SUM(147), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(147), DATA_B => INT_CARRY(107), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_114:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(148), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin NO stage INT_SUM(149) <= SUMMAND(177); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(108), SAVE => INT_SUM(150), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin NO stage INT_SUM(151) <= INT_CARRY(109); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(110), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_117:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(178), DATA_B => SUMMAND(179), DATA_C => SUMMAND(180), SAVE => INT_SUM(152), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin NO stage INT_SUM(153) <= INT_SUM(152); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(154) <= INT_CARRY(111); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_CARRY(112), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_119:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(181), DATA_B => SUMMAND(182), DATA_C => SUMMAND(183), SAVE => INT_SUM(155), CARRY => INT_CARRY(114) ); ---- End FA stage ---- Begin NO stage INT_SUM(156) <= INT_CARRY(113); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(155), DATA_B => INT_SUM(156), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End HA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin NO stage INT_SUM(157) <= SUMMAND(184); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(158) <= SUMMAND(185); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_120:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(114), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin HA stage HA_26:HALF_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End HA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin NO stage SUM(34) <= SUMMAND(188); -- At Level 5 ---- End NO stage -- End WT-branch 35 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_18_18 is generic (mulpipe : integer := 0); port ( MULTIPLICAND: in std_logic_vector(0 to 17); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_ulogic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_18_18; architecture MULTIPLIER of MULTIPLIER_18_18 is signal PPBIT:std_logic_vector(0 to 188); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_CARRYR: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal INT_SUMR: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_18_18 port map ( OPA(0 to 17) => MULTIPLICAND(0 to 17), OPB(0 to 17) => MULTIPLIER(0 to 17), SUMMAND(0 to 188) => PPBIT(0 to 188) ); W:WALLACE_18_18 port map ( SUMMAND(0 to 188) => PPBIT(0 to 188), CARRY(0 to 33) => INT_CARRY(1 to 34), SUM(0 to 34) => INT_SUM(0 to 34) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(35) <= LOGIC_ZERO; INT_CARRY(36) <= LOGIC_ZERO; INT_CARRY(37) <= LOGIC_ZERO; INT_CARRY(38) <= LOGIC_ZERO; INT_CARRY(39) <= LOGIC_ZERO; INT_CARRY(40) <= LOGIC_ZERO; INT_CARRY(41) <= LOGIC_ZERO; INT_CARRY(42) <= LOGIC_ZERO; INT_CARRY(43) <= LOGIC_ZERO; INT_CARRY(44) <= LOGIC_ZERO; INT_CARRY(45) <= LOGIC_ZERO; INT_CARRY(46) <= LOGIC_ZERO; INT_CARRY(47) <= LOGIC_ZERO; INT_CARRY(48) <= LOGIC_ZERO; INT_CARRY(49) <= LOGIC_ZERO; INT_CARRY(50) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(35) <= LOGIC_ZERO; INT_SUM(36) <= LOGIC_ZERO; INT_SUM(37) <= LOGIC_ZERO; INT_SUM(38) <= LOGIC_ZERO; INT_SUM(39) <= LOGIC_ZERO; INT_SUM(40) <= LOGIC_ZERO; INT_SUM(41) <= LOGIC_ZERO; INT_SUM(42) <= LOGIC_ZERO; INT_SUM(43) <= LOGIC_ZERO; INT_SUM(44) <= LOGIC_ZERO; INT_SUM(45) <= LOGIC_ZERO; INT_SUM(46) <= LOGIC_ZERO; INT_SUM(47) <= LOGIC_ZERO; INT_SUM(48) <= LOGIC_ZERO; INT_SUM(49) <= LOGIC_ZERO; INT_SUM(50) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; INT_SUMR(35 to 63) <= INT_SUM(35 to 63); INT_CARRYR(35 to 63) <= INT_CARRY(35 to 63); INT_CARRYR(0) <= INT_CARRY(0); reg : if MULPIPE /= 0 generate process (PHI) begin if rising_edge(PHI ) then if (holdn = '1') then INT_SUMR(0 to 34) <= INT_SUM(0 to 34); INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34); end if; end if; end process; end generate; noreg : if MULPIPE = 0 generate INT_SUMR(0 to 34) <= INT_SUM(0 to 34); INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34); end generate; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUMR(0 to 63), OPB(0 to 63) => INT_CARRYR(0 to 63), CIN => LOGIC_ZERO, PHI => PHI , SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_10 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 9); SUMMAND: out std_logic_vector(0 to 184) ); end BOOTHCODER_34_10; architecture BOOTHCODER of BOOTHCODER_34_10 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 19); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(40) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(45) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(50) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(55) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(60) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(65) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(70) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(75) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(85) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(95) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(100) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(105) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(110) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(115) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(120) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(125) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(130) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(135) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(140) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(145) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(150) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(155) ); SUMMAND(156) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(41) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(46) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(51) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(56) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(61) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(66) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(71) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(76) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(86) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(96) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(101) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(106) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(111) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(116) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(121) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(126) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(131) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(136) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(141) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(146) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(151) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(157) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(161) ); SUMMAND(162) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(166) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(42) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(47) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(52) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(57) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(62) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(67) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(72) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(77) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(87) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(97) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(102) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(107) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(112) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(117) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(122) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(127) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(132) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(137) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(142) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(147) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(152) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(158) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(163) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(167) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(170) ); SUMMAND(171) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(174) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(43) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(48) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(53) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(58) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(63) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(68) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(73) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(78) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(88) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(98) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(103) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(108) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(113) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(118) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(123) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(128) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(133) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(138) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(143) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(148) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(153) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(159) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(164) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(168) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(172) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(175) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(177) ); SUMMAND(178) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(180) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(44) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(49) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(54) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(59) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(64) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(69) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(74) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(79) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(89) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(99) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(104) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(109) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(114) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(119) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(124) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(129) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(134) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(139) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(144) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(149) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(154) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(165) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(169) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(173) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(176) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(179) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(181) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(182) ); SUMMAND(183) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(184) ); -- Begin partial product 5 end BOOTHCODER; ------------------------------------------------------------ -- END: Architectures used with the Modified Booth recoding ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the Wallace-tree ------------------------------------------------------------ -- -- Wallace tree architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_10 is port ( SUMMAND: in std_logic_vector(0 to 184); CARRY: out std_logic_vector(0 to 41); SUM: out std_logic_vector(0 to 42) ); end WALLACE_34_10; architecture WALLACE of WALLACE_34_10 is signal INT_CARRY: std_logic_vector(0 to 95); signal INT_SUM: std_logic_vector(0 to 133); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End HA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_CARRY(9), SAVE => INT_SUM(18), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin NO stage INT_SUM(19) <= INT_CARRY(10); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(18), DATA_B => INT_SUM(19), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_16:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(40), DATA_B => SUMMAND(41), DATA_C => SUMMAND(42), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End FA stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(43), DATA_B => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End HA stage ---- Begin FA stage FA_17:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(20), DATA_B => INT_SUM(21), DATA_C => INT_CARRY(12), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin NO stage INT_SUM(23) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(22), DATA_B => INT_SUM(23), DATA_C => INT_CARRY(14), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End FA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_19:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(24), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End HA stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(24), DATA_B => INT_SUM(25), DATA_C => INT_CARRY(15), SAVE => INT_SUM(26), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin NO stage INT_SUM(27) <= INT_CARRY(16); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_21:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(26), DATA_B => INT_SUM(27), DATA_C => INT_CARRY(17), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End FA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(50), DATA_B => SUMMAND(51), DATA_C => SUMMAND(52), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(53), DATA_B => SUMMAND(54), SAVE => INT_SUM(29), CARRY => INT_CARRY(22) ); ---- End HA stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(28), DATA_B => INT_SUM(29), DATA_C => INT_CARRY(18), SAVE => INT_SUM(30), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin NO stage INT_SUM(31) <= INT_CARRY(19); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(30), DATA_B => INT_SUM(31), DATA_C => INT_CARRY(20), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_25:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(55), DATA_B => SUMMAND(56), DATA_C => SUMMAND(57), SAVE => INT_SUM(32), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(58), DATA_B => SUMMAND(59), SAVE => INT_SUM(33), CARRY => INT_CARRY(25) ); ---- End HA stage ---- Begin FA stage FA_26:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(32), DATA_B => INT_SUM(33), DATA_C => INT_CARRY(21), SAVE => INT_SUM(34), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(35) <= INT_CARRY(22); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_CARRY(23), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_28:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(60), DATA_B => SUMMAND(61), DATA_C => SUMMAND(62), SAVE => INT_SUM(36), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), SAVE => INT_SUM(37), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(36), DATA_B => INT_SUM(37), DATA_C => INT_CARRY(24), SAVE => INT_SUM(38), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(39) <= INT_CARRY(25); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(38), DATA_B => INT_SUM(39), DATA_C => INT_CARRY(26), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(65), DATA_B => SUMMAND(66), DATA_C => SUMMAND(67), SAVE => INT_SUM(40), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(68), DATA_B => SUMMAND(69), SAVE => INT_SUM(41), CARRY => INT_CARRY(31) ); ---- End HA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(40), DATA_B => INT_SUM(41), DATA_C => INT_CARRY(27), SAVE => INT_SUM(42), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin NO stage INT_SUM(43) <= INT_CARRY(28); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(42), DATA_B => INT_SUM(43), DATA_C => INT_CARRY(29), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_34:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(70), DATA_B => SUMMAND(71), DATA_C => SUMMAND(72), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(73), DATA_B => SUMMAND(74), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(30), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(31); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(32), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End FA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End HA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_CARRY(33), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End FA stage ---- Begin NO stage INT_SUM(51) <= INT_CARRY(34); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(50), DATA_B => INT_SUM(51), DATA_C => INT_CARRY(35), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End FA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_40:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(52), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), SAVE => INT_SUM(53), CARRY => INT_CARRY(40) ); ---- End HA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(52), DATA_B => INT_SUM(53), DATA_C => INT_CARRY(36), SAVE => INT_SUM(54), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(55) <= INT_CARRY(37); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(54), DATA_B => INT_SUM(55), DATA_C => INT_CARRY(38), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End FA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(85), DATA_B => SUMMAND(86), DATA_C => SUMMAND(87), SAVE => INT_SUM(56), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(88), DATA_B => SUMMAND(89), SAVE => INT_SUM(57), CARRY => INT_CARRY(43) ); ---- End HA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(56), DATA_B => INT_SUM(57), DATA_C => INT_CARRY(39), SAVE => INT_SUM(58), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(59) <= INT_CARRY(40); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(58), DATA_B => INT_SUM(59), DATA_C => INT_CARRY(41), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_46:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(60), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), SAVE => INT_SUM(61), CARRY => INT_CARRY(46) ); ---- End HA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(60), DATA_B => INT_SUM(61), DATA_C => INT_CARRY(42), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin NO stage INT_SUM(63) <= INT_CARRY(43); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(44), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_49:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(95), DATA_B => SUMMAND(96), DATA_C => SUMMAND(97), SAVE => INT_SUM(64), CARRY => INT_CARRY(48) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(98), DATA_B => SUMMAND(99), SAVE => INT_SUM(65), CARRY => INT_CARRY(49) ); ---- End HA stage ---- Begin FA stage FA_50:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_CARRY(45), SAVE => INT_SUM(66), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin NO stage INT_SUM(67) <= INT_CARRY(46); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(66), DATA_B => INT_SUM(67), DATA_C => INT_CARRY(47), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(100), DATA_B => SUMMAND(101), DATA_C => SUMMAND(102), SAVE => INT_SUM(68), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(103), DATA_B => SUMMAND(104), SAVE => INT_SUM(69), CARRY => INT_CARRY(52) ); ---- End HA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(68), DATA_B => INT_SUM(69), DATA_C => INT_CARRY(48), SAVE => INT_SUM(70), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin NO stage INT_SUM(71) <= INT_CARRY(49); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(70), DATA_B => INT_SUM(71), DATA_C => INT_CARRY(50), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_55:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(72), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), SAVE => INT_SUM(73), CARRY => INT_CARRY(55) ); ---- End HA stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(72), DATA_B => INT_SUM(73), DATA_C => INT_CARRY(51), SAVE => INT_SUM(74), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin NO stage INT_SUM(75) <= INT_CARRY(52); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_57:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(74), DATA_B => INT_SUM(75), DATA_C => INT_CARRY(53), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112), SAVE => INT_SUM(76), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), SAVE => INT_SUM(77), CARRY => INT_CARRY(58) ); ---- End HA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(54), SAVE => INT_SUM(78), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(55); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(56), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End FA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_61:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117), SAVE => INT_SUM(80), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), SAVE => INT_SUM(81), CARRY => INT_CARRY(61) ); ---- End HA stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_CARRY(57), SAVE => INT_SUM(82), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin NO stage INT_SUM(83) <= INT_CARRY(58); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(59), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End FA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_64:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(84), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), SAVE => INT_SUM(85), CARRY => INT_CARRY(64) ); ---- End HA stage ---- Begin FA stage FA_65:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(60), SAVE => INT_SUM(86), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin NO stage INT_SUM(87) <= INT_CARRY(61); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(62), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End FA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_67:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(125), DATA_B => SUMMAND(126), DATA_C => SUMMAND(127), SAVE => INT_SUM(88), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(128), DATA_B => SUMMAND(129), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End HA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(88), DATA_B => INT_SUM(89), DATA_C => INT_CARRY(63), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(91) <= INT_CARRY(64); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(90), DATA_B => INT_SUM(91), DATA_C => INT_CARRY(65), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End FA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_70:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(130), DATA_B => SUMMAND(131), DATA_C => SUMMAND(132), SAVE => INT_SUM(92), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(133), DATA_B => SUMMAND(134), SAVE => INT_SUM(93), CARRY => INT_CARRY(70) ); ---- End HA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66), SAVE => INT_SUM(94), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(67); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), SAVE => INT_SUM(97), CARRY => INT_CARRY(73) ); ---- End HA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(69), SAVE => INT_SUM(98), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin NO stage INT_SUM(99) <= INT_CARRY(70); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(71), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_76:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(140), DATA_B => SUMMAND(141), DATA_C => SUMMAND(142), SAVE => INT_SUM(100), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), SAVE => INT_SUM(101), CARRY => INT_CARRY(76) ); ---- End HA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(72), SAVE => INT_SUM(102), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin NO stage INT_SUM(103) <= INT_CARRY(73); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(74), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End FA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_79:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(145), DATA_B => SUMMAND(146), DATA_C => SUMMAND(147), SAVE => INT_SUM(104), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), SAVE => INT_SUM(105), CARRY => INT_CARRY(79) ); ---- End HA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(104), DATA_B => INT_SUM(105), DATA_C => INT_CARRY(75), SAVE => INT_SUM(106), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin NO stage INT_SUM(107) <= INT_CARRY(76); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(77), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_82:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152), SAVE => INT_SUM(108), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), SAVE => INT_SUM(109), CARRY => INT_CARRY(82) ); ---- End HA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(78), SAVE => INT_SUM(110), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(111) <= INT_CARRY(79); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(80), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End FA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(155), DATA_B => SUMMAND(156), DATA_C => SUMMAND(157), SAVE => INT_SUM(112), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(158), DATA_B => SUMMAND(159), DATA_C => SUMMAND(160), SAVE => INT_SUM(113), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_CARRY(81), SAVE => INT_SUM(114), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin NO stage INT_SUM(115) <= INT_CARRY(82); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(114), DATA_B => INT_SUM(115), DATA_C => INT_CARRY(83), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_89:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(161), DATA_B => SUMMAND(162), DATA_C => SUMMAND(163), SAVE => INT_SUM(116), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(164), DATA_B => SUMMAND(165), SAVE => INT_SUM(117), CARRY => INT_CARRY(88) ); ---- End HA stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(84), SAVE => INT_SUM(118), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= INT_CARRY(85); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_91:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(86), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End FA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(166), DATA_B => SUMMAND(167), DATA_C => SUMMAND(168), SAVE => INT_SUM(120), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin NO stage INT_SUM(121) <= SUMMAND(169); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(87), SAVE => INT_SUM(122), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= INT_CARRY(88); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(89), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_95:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172), SAVE => INT_SUM(124), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin NO stage INT_SUM(125) <= SUMMAND(173); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(90), SAVE => INT_SUM(126), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(126), DATA_B => INT_CARRY(91), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End HA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_97:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(127), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin NO stage INT_SUM(128) <= INT_SUM(127); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(129) <= INT_CARRY(92); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(93), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_99:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(130), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin NO stage INT_SUM(131) <= INT_CARRY(94); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End HA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin NO stage INT_SUM(132) <= SUMMAND(180); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(133) <= SUMMAND(181); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(95), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin HA stage HA_35:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End HA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin NO stage SUM(42) <= SUMMAND(184); -- At Level 3 ---- End NO stage -- End WT-branch 43 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_10 is port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 9); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_34_10; ------------------------------------------------------------ -- End: Multiplier Entitiy architecture MULTIPLIER of MULTIPLIER_34_10 is signal PPBIT:std_logic_vector(0 to 184); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_10 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 9) => MULTIPLIER(0 to 9), SUMMAND(0 to 184) => PPBIT(0 to 184) ); W:WALLACE_34_10 port map ( SUMMAND(0 to 184) => PPBIT(0 to 184), CARRY(0 to 41) => INT_CARRY(1 to 42), SUM(0 to 42) => INT_SUM(0 to 42) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(43) <= LOGIC_ZERO; INT_CARRY(44) <= LOGIC_ZERO; INT_CARRY(45) <= LOGIC_ZERO; INT_CARRY(46) <= LOGIC_ZERO; INT_CARRY(47) <= LOGIC_ZERO; INT_CARRY(48) <= LOGIC_ZERO; INT_CARRY(49) <= LOGIC_ZERO; INT_CARRY(50) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(43) <= LOGIC_ZERO; INT_SUM(44) <= LOGIC_ZERO; INT_SUM(45) <= LOGIC_ZERO; INT_SUM(46) <= LOGIC_ZERO; INT_SUM(47) <= LOGIC_ZERO; INT_SUM(48) <= LOGIC_ZERO; INT_SUM(49) <= LOGIC_ZERO; INT_SUM(50) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUM(0 to 63), OPB(0 to 63) => INT_CARRY(0 to 63), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_9 is port(X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(8 downto 0); P: out std_logic_vector(41 downto 0)); end MUL_33_9; library ieee; use ieee.std_logic_1164.all; architecture A of MUL_33_9 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 9); signal Q: std_logic_vector(0 to 63); signal CLK: std_logic; begin U1: MULTIPLIER_34_10 port map(A,B,CLK,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(8); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); end A; ------------------------------------------------------------ -- START: Entities within the Wallace-tree ------------------------------------------------------------ -- -- Modified Booth algorithm architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_18 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 332) ); end BOOTHCODER_34_18; architecture BOOTHCODER of BOOTHCODER_34_18 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 35); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(108) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(117) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(126) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(135) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(144) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(153) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(162) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(171) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(180) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(189) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(198) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(207) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(216) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(225) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(234) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(243) ); SUMMAND(244) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(100) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(109) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(118) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(127) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(136) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(145) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(154) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(163) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(172) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(181) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(190) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(199) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(208) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(217) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(226) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(235) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(245) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(253) ); SUMMAND(254) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(262) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(101) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(110) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(119) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(128) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(137) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(146) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(155) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(164) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(173) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(182) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(191) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(200) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(209) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(218) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(227) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(236) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(246) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(255) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(263) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(270) ); SUMMAND(271) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(278) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(102) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(111) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(120) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(129) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(138) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(147) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(156) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(165) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(174) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(183) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(192) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(201) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(210) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(219) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(228) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(237) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(247) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(256) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(264) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(272) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(279) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(285) ); SUMMAND(286) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(292) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(103) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(112) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(121) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(130) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(139) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(148) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(157) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(166) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(175) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(184) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(193) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(202) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(211) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(220) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(229) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(238) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(248) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(257) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(265) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(273) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(280) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(287) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(293) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(298) ); SUMMAND(299) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(304) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_165:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_166:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_167:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_168:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_169:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_170:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_171:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_172:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(104) ); PPM_173:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(113) ); PPM_174:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(122) ); PPM_175:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(131) ); PPM_176:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(140) ); PPM_177:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(149) ); PPM_178:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(158) ); PPM_179:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(167) ); PPM_180:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(176) ); PPM_181:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(185) ); PPM_182:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(194) ); PPM_183:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(203) ); PPM_184:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(212) ); PPM_185:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(221) ); PPM_186:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(230) ); PPM_187:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(239) ); PPM_188:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(249) ); PPM_189:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(258) ); PPM_190:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(266) ); PPM_191:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(274) ); PPM_192:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(281) ); PPM_193:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(288) ); PPM_194:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(294) ); PPM_195:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(300) ); PPM_196:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(305) ); PPM_197:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(309) ); SUMMAND(310) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(314) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_198:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_199:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_200:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_201:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_202:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_203:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(105) ); PPM_204:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(114) ); PPM_205:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(123) ); PPM_206:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(132) ); PPM_207:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(141) ); PPM_208:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(150) ); PPM_209:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(159) ); PPM_210:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(168) ); PPM_211:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(177) ); PPM_212:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(186) ); PPM_213:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(195) ); PPM_214:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(204) ); PPM_215:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(213) ); PPM_216:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(222) ); PPM_217:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(231) ); PPM_218:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(240) ); PPM_219:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(250) ); PPM_220:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(259) ); PPM_221:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(267) ); PPM_222:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(275) ); PPM_223:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(282) ); PPM_224:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(289) ); PPM_225:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(295) ); PPM_226:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(301) ); PPM_227:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(306) ); PPM_228:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(311) ); PPM_229:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(315) ); PPM_230:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(318) ); SUMMAND(319) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(322) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_231:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_232:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_233:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_234:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(106) ); PPM_235:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(115) ); PPM_236:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(124) ); PPM_237:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(133) ); PPM_238:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(142) ); PPM_239:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(151) ); PPM_240:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(160) ); PPM_241:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(169) ); PPM_242:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(178) ); PPM_243:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(187) ); PPM_244:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(196) ); PPM_245:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(205) ); PPM_246:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(214) ); PPM_247:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(223) ); PPM_248:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(232) ); PPM_249:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(241) ); PPM_250:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(251) ); PPM_251:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(260) ); PPM_252:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(268) ); PPM_253:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(276) ); PPM_254:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(283) ); PPM_255:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(290) ); PPM_256:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(296) ); PPM_257:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(302) ); PPM_258:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(307) ); PPM_259:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(312) ); PPM_260:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(316) ); PPM_261:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(320) ); PPM_262:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(323) ); PPM_263:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(325) ); SUMMAND(326) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(328) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_264:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_265:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(107) ); PPM_266:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(116) ); PPM_267:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(125) ); PPM_268:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(134) ); PPM_269:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(143) ); PPM_270:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(152) ); PPM_271:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(161) ); PPM_272:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(170) ); PPM_273:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(179) ); PPM_274:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(188) ); PPM_275:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(197) ); PPM_276:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(206) ); PPM_277:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(215) ); PPM_278:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(224) ); PPM_279:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(233) ); PPM_280:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(242) ); PPM_281:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(252) ); PPM_282:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(261) ); PPM_283:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(269) ); PPM_284:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(277) ); PPM_285:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(284) ); PPM_286:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(291) ); PPM_287:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(297) ); PPM_288:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(303) ); PPM_289:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(308) ); PPM_290:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(313) ); PPM_291:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(317) ); PPM_292:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(321) ); PPM_293:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(324) ); PPM_294:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(327) ); PPM_295:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(329) ); PPM_296:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(330) ); SUMMAND(331) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(332) ); -- Begin partial product 9 end BOOTHCODER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_18 is port ( SUMMAND: in std_logic_vector(0 to 332); CARRY: out std_logic_vector(0 to 49); SUM: out std_logic_vector(0 to 50) ); end WALLACE_34_18; architecture WALLACE of WALLACE_34_18 is -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 226); signal INT_SUM: std_logic_vector(0 to 286); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(76), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(49), DATA_B => INT_CARRY(50), DATA_C => INT_CARRY(51), SAVE => INT_SUM(77), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(52), SAVE => INT_SUM(78), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(53); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(54), SAVE => INT_SUM(80), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(80), DATA_B => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End HA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_64:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), DATA_C => SUMMAND(110), SAVE => INT_SUM(81), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin FA stage FA_65:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(111), DATA_B => SUMMAND(112), DATA_C => SUMMAND(113), SAVE => INT_SUM(82), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(114), DATA_B => SUMMAND(115), DATA_C => SUMMAND(116), SAVE => INT_SUM(83), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(81), DATA_B => INT_SUM(82), DATA_C => INT_SUM(83), SAVE => INT_SUM(84), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58), SAVE => INT_SUM(85), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(59), SAVE => INT_SUM(86), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(87) <= INT_CARRY(60); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(61), SAVE => INT_SUM(88), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(62), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End HA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_71:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(117), DATA_B => SUMMAND(118), DATA_C => SUMMAND(119), SAVE => INT_SUM(89), CARRY => INT_CARRY(70) ); ---- End FA stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(90), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125), SAVE => INT_SUM(91), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91), SAVE => INT_SUM(92), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(63), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65), SAVE => INT_SUM(93), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66), SAVE => INT_SUM(94), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(67); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68), SAVE => INT_SUM(96), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(96), DATA_B => INT_CARRY(69), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End HA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_78:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(97), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin FA stage FA_79:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(98), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134), SAVE => INT_SUM(99), CARRY => INT_CARRY(79) ); ---- End FA stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(97), DATA_B => INT_SUM(98), DATA_C => INT_SUM(99), SAVE => INT_SUM(100), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin FA stage FA_82:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(70), DATA_B => INT_CARRY(71), DATA_C => INT_CARRY(72), SAVE => INT_SUM(101), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(73), SAVE => INT_SUM(102), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin NO stage INT_SUM(103) <= INT_CARRY(74); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(75), SAVE => INT_SUM(104), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(104), DATA_B => INT_CARRY(76), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End HA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(105), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140), SAVE => INT_SUM(106), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143), SAVE => INT_SUM(107), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_SUM(107), SAVE => INT_SUM(108), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(77), DATA_B => INT_CARRY(78), DATA_C => INT_CARRY(79), SAVE => INT_SUM(109), CARRY => INT_CARRY(88) ); ---- End FA stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(80), SAVE => INT_SUM(110), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(111) <= INT_CARRY(81); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_91:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(82), SAVE => INT_SUM(112), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(112), DATA_B => INT_CARRY(83), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End HA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146), SAVE => INT_SUM(113), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(147), DATA_B => SUMMAND(148), DATA_C => SUMMAND(149), SAVE => INT_SUM(114), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152), SAVE => INT_SUM(115), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_SUM(115), SAVE => INT_SUM(116), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86), SAVE => INT_SUM(117), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(87), SAVE => INT_SUM(118), CARRY => INT_CARRY(96) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= INT_CARRY(88); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(89), SAVE => INT_SUM(120), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(120), DATA_B => INT_CARRY(90), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End HA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_99:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), DATA_C => SUMMAND(155), SAVE => INT_SUM(121), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158), SAVE => INT_SUM(122), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin FA stage FA_101:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161), SAVE => INT_SUM(123), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(121), DATA_B => INT_SUM(122), DATA_C => INT_SUM(123), SAVE => INT_SUM(124), CARRY => INT_CARRY(101) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(91), DATA_B => INT_CARRY(92), DATA_C => INT_CARRY(93), SAVE => INT_SUM(125), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(94), SAVE => INT_SUM(126), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin NO stage INT_SUM(127) <= INT_CARRY(95); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_105:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(96), SAVE => INT_SUM(128), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(128), DATA_B => INT_CARRY(97), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End HA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_106:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164), SAVE => INT_SUM(129), CARRY => INT_CARRY(105) ); ---- End FA stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(130), CARRY => INT_CARRY(106) ); ---- End FA stage ---- Begin FA stage FA_108:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170), SAVE => INT_SUM(131), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_SUM(131), SAVE => INT_SUM(132), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(98), DATA_B => INT_CARRY(99), DATA_C => INT_CARRY(100), SAVE => INT_SUM(133), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin FA stage FA_111:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(101), SAVE => INT_SUM(134), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin NO stage INT_SUM(135) <= INT_CARRY(102); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(134), DATA_B => INT_SUM(135), DATA_C => INT_CARRY(103), SAVE => INT_SUM(136), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(136), DATA_B => INT_CARRY(104), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End HA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_113:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173), SAVE => INT_SUM(137), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin FA stage FA_114:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(138), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(139), CARRY => INT_CARRY(114) ); ---- End FA stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_SUM(139), SAVE => INT_SUM(140), CARRY => INT_CARRY(115) ); ---- End FA stage ---- Begin FA stage FA_117:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(105), DATA_B => INT_CARRY(106), DATA_C => INT_CARRY(107), SAVE => INT_SUM(141), CARRY => INT_CARRY(116) ); ---- End FA stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(108), SAVE => INT_SUM(142), CARRY => INT_CARRY(117) ); ---- End FA stage ---- Begin NO stage INT_SUM(143) <= INT_CARRY(109); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_119:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(110), SAVE => INT_SUM(144), CARRY => INT_CARRY(118) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(144), DATA_B => INT_CARRY(111), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_120:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), DATA_C => SUMMAND(182), SAVE => INT_SUM(145), CARRY => INT_CARRY(119) ); ---- End FA stage ---- Begin FA stage FA_121:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(183), DATA_B => SUMMAND(184), DATA_C => SUMMAND(185), SAVE => INT_SUM(146), CARRY => INT_CARRY(120) ); ---- End FA stage ---- Begin FA stage FA_122:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), DATA_C => SUMMAND(188), SAVE => INT_SUM(147), CARRY => INT_CARRY(121) ); ---- End FA stage ---- Begin FA stage FA_123:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_SUM(147), SAVE => INT_SUM(148), CARRY => INT_CARRY(122) ); ---- End FA stage ---- Begin FA stage FA_124:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(112), DATA_B => INT_CARRY(113), DATA_C => INT_CARRY(114), SAVE => INT_SUM(149), CARRY => INT_CARRY(123) ); ---- End FA stage ---- Begin FA stage FA_125:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(115), SAVE => INT_SUM(150), CARRY => INT_CARRY(124) ); ---- End FA stage ---- Begin NO stage INT_SUM(151) <= INT_CARRY(116); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_126:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(117), SAVE => INT_SUM(152), CARRY => INT_CARRY(125) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(152), DATA_B => INT_CARRY(118), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End HA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_127:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(189), DATA_B => SUMMAND(190), DATA_C => SUMMAND(191), SAVE => INT_SUM(153), CARRY => INT_CARRY(126) ); ---- End FA stage ---- Begin FA stage FA_128:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(192), DATA_B => SUMMAND(193), DATA_C => SUMMAND(194), SAVE => INT_SUM(154), CARRY => INT_CARRY(127) ); ---- End FA stage ---- Begin FA stage FA_129:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197), SAVE => INT_SUM(155), CARRY => INT_CARRY(128) ); ---- End FA stage ---- Begin FA stage FA_130:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_SUM(155), SAVE => INT_SUM(156), CARRY => INT_CARRY(129) ); ---- End FA stage ---- Begin FA stage FA_131:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(119), DATA_B => INT_CARRY(120), DATA_C => INT_CARRY(121), SAVE => INT_SUM(157), CARRY => INT_CARRY(130) ); ---- End FA stage ---- Begin FA stage FA_132:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(156), DATA_B => INT_SUM(157), DATA_C => INT_CARRY(122), SAVE => INT_SUM(158), CARRY => INT_CARRY(131) ); ---- End FA stage ---- Begin NO stage INT_SUM(159) <= INT_CARRY(123); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_133:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(158), DATA_B => INT_SUM(159), DATA_C => INT_CARRY(124), SAVE => INT_SUM(160), CARRY => INT_CARRY(132) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(160), DATA_B => INT_CARRY(125), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_134:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200), SAVE => INT_SUM(161), CARRY => INT_CARRY(133) ); ---- End FA stage ---- Begin FA stage FA_135:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203), SAVE => INT_SUM(162), CARRY => INT_CARRY(134) ); ---- End FA stage ---- Begin FA stage FA_136:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206), SAVE => INT_SUM(163), CARRY => INT_CARRY(135) ); ---- End FA stage ---- Begin FA stage FA_137:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(161), DATA_B => INT_SUM(162), DATA_C => INT_SUM(163), SAVE => INT_SUM(164), CARRY => INT_CARRY(136) ); ---- End FA stage ---- Begin FA stage FA_138:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(126), DATA_B => INT_CARRY(127), DATA_C => INT_CARRY(128), SAVE => INT_SUM(165), CARRY => INT_CARRY(137) ); ---- End FA stage ---- Begin FA stage FA_139:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(164), DATA_B => INT_SUM(165), DATA_C => INT_CARRY(129), SAVE => INT_SUM(166), CARRY => INT_CARRY(138) ); ---- End FA stage ---- Begin NO stage INT_SUM(167) <= INT_CARRY(130); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_140:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(131), SAVE => INT_SUM(168), CARRY => INT_CARRY(139) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(168), DATA_B => INT_CARRY(132), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End HA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_141:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209), SAVE => INT_SUM(169), CARRY => INT_CARRY(140) ); ---- End FA stage ---- Begin FA stage FA_142:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212), SAVE => INT_SUM(170), CARRY => INT_CARRY(141) ); ---- End FA stage ---- Begin FA stage FA_143:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215), SAVE => INT_SUM(171), CARRY => INT_CARRY(142) ); ---- End FA stage ---- Begin FA stage FA_144:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(169), DATA_B => INT_SUM(170), DATA_C => INT_SUM(171), SAVE => INT_SUM(172), CARRY => INT_CARRY(143) ); ---- End FA stage ---- Begin FA stage FA_145:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135), SAVE => INT_SUM(173), CARRY => INT_CARRY(144) ); ---- End FA stage ---- Begin FA stage FA_146:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(172), DATA_B => INT_SUM(173), DATA_C => INT_CARRY(136), SAVE => INT_SUM(174), CARRY => INT_CARRY(145) ); ---- End FA stage ---- Begin NO stage INT_SUM(175) <= INT_CARRY(137); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_147:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(174), DATA_B => INT_SUM(175), DATA_C => INT_CARRY(138), SAVE => INT_SUM(176), CARRY => INT_CARRY(146) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(176), DATA_B => INT_CARRY(139), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End HA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_148:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218), SAVE => INT_SUM(177), CARRY => INT_CARRY(147) ); ---- End FA stage ---- Begin FA stage FA_149:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221), SAVE => INT_SUM(178), CARRY => INT_CARRY(148) ); ---- End FA stage ---- Begin FA stage FA_150:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), DATA_C => SUMMAND(224), SAVE => INT_SUM(179), CARRY => INT_CARRY(149) ); ---- End FA stage ---- Begin FA stage FA_151:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(177), DATA_B => INT_SUM(178), DATA_C => INT_SUM(179), SAVE => INT_SUM(180), CARRY => INT_CARRY(150) ); ---- End FA stage ---- Begin FA stage FA_152:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(140), DATA_B => INT_CARRY(141), DATA_C => INT_CARRY(142), SAVE => INT_SUM(181), CARRY => INT_CARRY(151) ); ---- End FA stage ---- Begin FA stage FA_153:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), DATA_C => INT_CARRY(143), SAVE => INT_SUM(182), CARRY => INT_CARRY(152) ); ---- End FA stage ---- Begin NO stage INT_SUM(183) <= INT_CARRY(144); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_154:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_CARRY(145), SAVE => INT_SUM(184), CARRY => INT_CARRY(153) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(184), DATA_B => INT_CARRY(146), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End HA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_155:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(225), DATA_B => SUMMAND(226), DATA_C => SUMMAND(227), SAVE => INT_SUM(185), CARRY => INT_CARRY(154) ); ---- End FA stage ---- Begin FA stage FA_156:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(228), DATA_B => SUMMAND(229), DATA_C => SUMMAND(230), SAVE => INT_SUM(186), CARRY => INT_CARRY(155) ); ---- End FA stage ---- Begin FA stage FA_157:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(231), DATA_B => SUMMAND(232), DATA_C => SUMMAND(233), SAVE => INT_SUM(187), CARRY => INT_CARRY(156) ); ---- End FA stage ---- Begin FA stage FA_158:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_SUM(187), SAVE => INT_SUM(188), CARRY => INT_CARRY(157) ); ---- End FA stage ---- Begin FA stage FA_159:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(147), DATA_B => INT_CARRY(148), DATA_C => INT_CARRY(149), SAVE => INT_SUM(189), CARRY => INT_CARRY(158) ); ---- End FA stage ---- Begin FA stage FA_160:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(188), DATA_B => INT_SUM(189), DATA_C => INT_CARRY(150), SAVE => INT_SUM(190), CARRY => INT_CARRY(159) ); ---- End FA stage ---- Begin NO stage INT_SUM(191) <= INT_CARRY(151); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_161:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(190), DATA_B => INT_SUM(191), DATA_C => INT_CARRY(152), SAVE => INT_SUM(192), CARRY => INT_CARRY(160) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(192), DATA_B => INT_CARRY(153), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End HA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_162:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(234), DATA_B => SUMMAND(235), DATA_C => SUMMAND(236), SAVE => INT_SUM(193), CARRY => INT_CARRY(161) ); ---- End FA stage ---- Begin FA stage FA_163:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(237), DATA_B => SUMMAND(238), DATA_C => SUMMAND(239), SAVE => INT_SUM(194), CARRY => INT_CARRY(162) ); ---- End FA stage ---- Begin FA stage FA_164:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242), SAVE => INT_SUM(195), CARRY => INT_CARRY(163) ); ---- End FA stage ---- Begin FA stage FA_165:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(193), DATA_B => INT_SUM(194), DATA_C => INT_SUM(195), SAVE => INT_SUM(196), CARRY => INT_CARRY(164) ); ---- End FA stage ---- Begin FA stage FA_166:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(154), DATA_B => INT_CARRY(155), DATA_C => INT_CARRY(156), SAVE => INT_SUM(197), CARRY => INT_CARRY(165) ); ---- End FA stage ---- Begin FA stage FA_167:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(196), DATA_B => INT_SUM(197), DATA_C => INT_CARRY(157), SAVE => INT_SUM(198), CARRY => INT_CARRY(166) ); ---- End FA stage ---- Begin NO stage INT_SUM(199) <= INT_CARRY(158); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_168:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(198), DATA_B => INT_SUM(199), DATA_C => INT_CARRY(159), SAVE => INT_SUM(200), CARRY => INT_CARRY(167) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(200), DATA_B => INT_CARRY(160), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End HA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_169:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245), SAVE => INT_SUM(201), CARRY => INT_CARRY(168) ); ---- End FA stage ---- Begin FA stage FA_170:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248), SAVE => INT_SUM(202), CARRY => INT_CARRY(169) ); ---- End FA stage ---- Begin FA stage FA_171:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251), SAVE => INT_SUM(203), CARRY => INT_CARRY(170) ); ---- End FA stage ---- Begin NO stage INT_SUM(204) <= SUMMAND(252); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_172:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(201), DATA_B => INT_SUM(202), DATA_C => INT_SUM(203), SAVE => INT_SUM(205), CARRY => INT_CARRY(171) ); ---- End FA stage ---- Begin FA stage FA_173:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(204), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162), SAVE => INT_SUM(206), CARRY => INT_CARRY(172) ); ---- End FA stage ---- Begin NO stage INT_SUM(207) <= INT_CARRY(163); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_174:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207), SAVE => INT_SUM(208), CARRY => INT_CARRY(173) ); ---- End FA stage ---- Begin NO stage INT_SUM(209) <= INT_CARRY(164); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(210) <= INT_CARRY(165); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_175:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_SUM(210), SAVE => INT_SUM(211), CARRY => INT_CARRY(174) ); ---- End FA stage ---- Begin NO stage INT_SUM(212) <= INT_CARRY(166); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_176:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(211), DATA_B => INT_SUM(212), DATA_C => INT_CARRY(167), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_177:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(253), DATA_B => SUMMAND(254), DATA_C => SUMMAND(255), SAVE => INT_SUM(213), CARRY => INT_CARRY(175) ); ---- End FA stage ---- Begin FA stage FA_178:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(256), DATA_B => SUMMAND(257), DATA_C => SUMMAND(258), SAVE => INT_SUM(214), CARRY => INT_CARRY(176) ); ---- End FA stage ---- Begin FA stage FA_179:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(259), DATA_B => SUMMAND(260), DATA_C => SUMMAND(261), SAVE => INT_SUM(215), CARRY => INT_CARRY(177) ); ---- End FA stage ---- Begin FA stage FA_180:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(168), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170), SAVE => INT_SUM(216), CARRY => INT_CARRY(178) ); ---- End FA stage ---- Begin FA stage FA_181:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(213), DATA_B => INT_SUM(214), DATA_C => INT_SUM(215), SAVE => INT_SUM(217), CARRY => INT_CARRY(179) ); ---- End FA stage ---- Begin FA stage FA_182:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(216), DATA_B => INT_CARRY(171), DATA_C => INT_CARRY(172), SAVE => INT_SUM(218), CARRY => INT_CARRY(180) ); ---- End FA stage ---- Begin FA stage FA_183:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_CARRY(173), SAVE => INT_SUM(219), CARRY => INT_CARRY(181) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(219), DATA_B => INT_CARRY(174), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End HA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_184:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(262), DATA_B => SUMMAND(263), DATA_C => SUMMAND(264), SAVE => INT_SUM(220), CARRY => INT_CARRY(182) ); ---- End FA stage ---- Begin FA stage FA_185:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(265), DATA_B => SUMMAND(266), DATA_C => SUMMAND(267), SAVE => INT_SUM(221), CARRY => INT_CARRY(183) ); ---- End FA stage ---- Begin NO stage INT_SUM(222) <= SUMMAND(268); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(223) <= SUMMAND(269); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_186:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_SUM(222), SAVE => INT_SUM(224), CARRY => INT_CARRY(184) ); ---- End FA stage ---- Begin NO stage INT_SUM(225) <= INT_SUM(223); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_187:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(224), DATA_B => INT_SUM(225), DATA_C => INT_CARRY(175), SAVE => INT_SUM(226), CARRY => INT_CARRY(185) ); ---- End FA stage ---- Begin FA stage FA_188:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(176), DATA_B => INT_CARRY(177), DATA_C => INT_CARRY(178), SAVE => INT_SUM(227), CARRY => INT_CARRY(186) ); ---- End FA stage ---- Begin FA stage FA_189:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_CARRY(179), SAVE => INT_SUM(228), CARRY => INT_CARRY(187) ); ---- End FA stage ---- Begin NO stage INT_SUM(229) <= INT_CARRY(180); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_190:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(228), DATA_B => INT_SUM(229), DATA_C => INT_CARRY(181), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_191:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(270), DATA_B => SUMMAND(271), DATA_C => SUMMAND(272), SAVE => INT_SUM(230), CARRY => INT_CARRY(188) ); ---- End FA stage ---- Begin FA stage FA_192:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(273), DATA_B => SUMMAND(274), DATA_C => SUMMAND(275), SAVE => INT_SUM(231), CARRY => INT_CARRY(189) ); ---- End FA stage ---- Begin FA stage FA_193:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(276), DATA_B => SUMMAND(277), DATA_C => INT_CARRY(182), SAVE => INT_SUM(232), CARRY => INT_CARRY(190) ); ---- End FA stage ---- Begin NO stage INT_SUM(233) <= INT_CARRY(183); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_194:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(230), DATA_B => INT_SUM(231), DATA_C => INT_SUM(232), SAVE => INT_SUM(234), CARRY => INT_CARRY(191) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(233), DATA_B => INT_CARRY(184), SAVE => INT_SUM(235), CARRY => INT_CARRY(192) ); ---- End HA stage ---- Begin FA stage FA_195:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(234), DATA_B => INT_SUM(235), DATA_C => INT_CARRY(185), SAVE => INT_SUM(236), CARRY => INT_CARRY(193) ); ---- End FA stage ---- Begin NO stage INT_SUM(237) <= INT_CARRY(186); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_196:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_CARRY(187), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End FA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_197:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280), SAVE => INT_SUM(238), CARRY => INT_CARRY(194) ); ---- End FA stage ---- Begin FA stage FA_198:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283), SAVE => INT_SUM(239), CARRY => INT_CARRY(195) ); ---- End FA stage ---- Begin NO stage INT_SUM(240) <= SUMMAND(284); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_199:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(238), DATA_B => INT_SUM(239), DATA_C => INT_SUM(240), SAVE => INT_SUM(241), CARRY => INT_CARRY(196) ); ---- End FA stage ---- Begin FA stage FA_200:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190), SAVE => INT_SUM(242), CARRY => INT_CARRY(197) ); ---- End FA stage ---- Begin FA stage FA_201:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(241), DATA_B => INT_SUM(242), DATA_C => INT_CARRY(191), SAVE => INT_SUM(243), CARRY => INT_CARRY(198) ); ---- End FA stage ---- Begin NO stage INT_SUM(244) <= INT_CARRY(192); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_202:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(243), DATA_B => INT_SUM(244), DATA_C => INT_CARRY(193), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_203:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(285), DATA_B => SUMMAND(286), DATA_C => SUMMAND(287), SAVE => INT_SUM(245), CARRY => INT_CARRY(199) ); ---- End FA stage ---- Begin FA stage FA_204:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290), SAVE => INT_SUM(246), CARRY => INT_CARRY(200) ); ---- End FA stage ---- Begin NO stage INT_SUM(247) <= SUMMAND(291); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_205:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(245), DATA_B => INT_SUM(246), DATA_C => INT_SUM(247), SAVE => INT_SUM(248), CARRY => INT_CARRY(201) ); ---- End FA stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(194), DATA_B => INT_CARRY(195), SAVE => INT_SUM(249), CARRY => INT_CARRY(202) ); ---- End HA stage ---- Begin FA stage FA_206:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(248), DATA_B => INT_SUM(249), DATA_C => INT_CARRY(196), SAVE => INT_SUM(250), CARRY => INT_CARRY(203) ); ---- End FA stage ---- Begin NO stage INT_SUM(251) <= INT_CARRY(197); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_207:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(250), DATA_B => INT_SUM(251), DATA_C => INT_CARRY(198), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End FA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin FA stage FA_208:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(292), DATA_B => SUMMAND(293), DATA_C => SUMMAND(294), SAVE => INT_SUM(252), CARRY => INT_CARRY(204) ); ---- End FA stage ---- Begin FA stage FA_209:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(295), DATA_B => SUMMAND(296), DATA_C => SUMMAND(297), SAVE => INT_SUM(253), CARRY => INT_CARRY(205) ); ---- End FA stage ---- Begin FA stage FA_210:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(252), DATA_B => INT_SUM(253), DATA_C => INT_CARRY(199), SAVE => INT_SUM(254), CARRY => INT_CARRY(206) ); ---- End FA stage ---- Begin NO stage INT_SUM(255) <= INT_CARRY(200); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_211:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_CARRY(201), SAVE => INT_SUM(256), CARRY => INT_CARRY(207) ); ---- End FA stage ---- Begin NO stage INT_SUM(257) <= INT_CARRY(202); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_212:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(256), DATA_B => INT_SUM(257), DATA_C => INT_CARRY(203), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin FA stage FA_213:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(298), DATA_B => SUMMAND(299), DATA_C => SUMMAND(300), SAVE => INT_SUM(258), CARRY => INT_CARRY(208) ); ---- End FA stage ---- Begin FA stage FA_214:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(301), DATA_B => SUMMAND(302), DATA_C => SUMMAND(303), SAVE => INT_SUM(259), CARRY => INT_CARRY(209) ); ---- End FA stage ---- Begin FA stage FA_215:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(258), DATA_B => INT_SUM(259), DATA_C => INT_CARRY(204), SAVE => INT_SUM(260), CARRY => INT_CARRY(210) ); ---- End FA stage ---- Begin NO stage INT_SUM(261) <= INT_CARRY(205); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_216:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(206), SAVE => INT_SUM(262), CARRY => INT_CARRY(211) ); ---- End FA stage ---- Begin HA stage HA_35:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(262), DATA_B => INT_CARRY(207), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End HA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin FA stage FA_217:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(304), DATA_B => SUMMAND(305), DATA_C => SUMMAND(306), SAVE => INT_SUM(263), CARRY => INT_CARRY(212) ); ---- End FA stage ---- Begin HA stage HA_36:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(307), DATA_B => SUMMAND(308), SAVE => INT_SUM(264), CARRY => INT_CARRY(213) ); ---- End HA stage ---- Begin FA stage FA_218:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(263), DATA_B => INT_SUM(264), DATA_C => INT_CARRY(208), SAVE => INT_SUM(265), CARRY => INT_CARRY(214) ); ---- End FA stage ---- Begin NO stage INT_SUM(266) <= INT_CARRY(209); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_219:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(210), SAVE => INT_SUM(267), CARRY => INT_CARRY(215) ); ---- End FA stage ---- Begin HA stage HA_37:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(267), DATA_B => INT_CARRY(211), SAVE => SUM(42), CARRY => CARRY(42) ); ---- End HA stage -- End WT-branch 43 -- Begin WT-branch 44 ---- Begin FA stage FA_220:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311), SAVE => INT_SUM(268), CARRY => INT_CARRY(216) ); ---- End FA stage ---- Begin HA stage HA_38:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), SAVE => INT_SUM(269), CARRY => INT_CARRY(217) ); ---- End HA stage ---- Begin FA stage FA_221:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(268), DATA_B => INT_SUM(269), DATA_C => INT_CARRY(212), SAVE => INT_SUM(270), CARRY => INT_CARRY(218) ); ---- End FA stage ---- Begin NO stage INT_SUM(271) <= INT_CARRY(213); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_222:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(270), DATA_B => INT_SUM(271), DATA_C => INT_CARRY(214), SAVE => INT_SUM(272), CARRY => INT_CARRY(219) ); ---- End FA stage ---- Begin HA stage HA_39:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(272), DATA_B => INT_CARRY(215), SAVE => SUM(43), CARRY => CARRY(43) ); ---- End HA stage -- End WT-branch 44 -- Begin WT-branch 45 ---- Begin FA stage FA_223:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(314), DATA_B => SUMMAND(315), DATA_C => SUMMAND(316), SAVE => INT_SUM(273), CARRY => INT_CARRY(220) ); ---- End FA stage ---- Begin FA stage FA_224:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(317), DATA_B => INT_CARRY(216), DATA_C => INT_CARRY(217), SAVE => INT_SUM(274), CARRY => INT_CARRY(221) ); ---- End FA stage ---- Begin FA stage FA_225:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(273), DATA_B => INT_SUM(274), DATA_C => INT_CARRY(218), SAVE => INT_SUM(275), CARRY => INT_CARRY(222) ); ---- End FA stage ---- Begin HA stage HA_40:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(275), DATA_B => INT_CARRY(219), SAVE => SUM(44), CARRY => CARRY(44) ); ---- End HA stage -- End WT-branch 45 -- Begin WT-branch 46 ---- Begin FA stage FA_226:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320), SAVE => INT_SUM(276), CARRY => INT_CARRY(223) ); ---- End FA stage ---- Begin NO stage INT_SUM(277) <= SUMMAND(321); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_227:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(276), DATA_B => INT_SUM(277), DATA_C => INT_CARRY(220), SAVE => INT_SUM(278), CARRY => INT_CARRY(224) ); ---- End FA stage ---- Begin NO stage INT_SUM(279) <= INT_CARRY(221); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_228:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(278), DATA_B => INT_SUM(279), DATA_C => INT_CARRY(222), SAVE => SUM(45), CARRY => CARRY(45) ); ---- End FA stage -- End WT-branch 46 -- Begin WT-branch 47 ---- Begin FA stage FA_229:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(322), DATA_B => SUMMAND(323), DATA_C => SUMMAND(324), SAVE => INT_SUM(280), CARRY => INT_CARRY(225) ); ---- End FA stage ---- Begin NO stage INT_SUM(281) <= INT_SUM(280); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(282) <= INT_CARRY(223); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_230:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(281), DATA_B => INT_SUM(282), DATA_C => INT_CARRY(224), SAVE => SUM(46), CARRY => CARRY(46) ); ---- End FA stage -- End WT-branch 47 -- Begin WT-branch 48 ---- Begin FA stage FA_231:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(325), DATA_B => SUMMAND(326), DATA_C => SUMMAND(327), SAVE => INT_SUM(283), CARRY => INT_CARRY(226) ); ---- End FA stage ---- Begin NO stage INT_SUM(284) <= INT_CARRY(225); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_41:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(283), DATA_B => INT_SUM(284), SAVE => SUM(47), CARRY => CARRY(47) ); ---- End HA stage -- End WT-branch 48 -- Begin WT-branch 49 ---- Begin NO stage INT_SUM(285) <= SUMMAND(328); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(286) <= SUMMAND(329); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_232:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(285), DATA_B => INT_SUM(286), DATA_C => INT_CARRY(226), SAVE => SUM(48), CARRY => CARRY(48) ); ---- End FA stage -- End WT-branch 49 -- Begin WT-branch 50 ---- Begin HA stage HA_42:HALF_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(330), DATA_B => SUMMAND(331), SAVE => SUM(49), CARRY => CARRY(49) ); ---- End HA stage -- End WT-branch 50 -- Begin WT-branch 51 ---- Begin NO stage SUM(50) <= SUMMAND(332); -- At Level 5 ---- End NO stage -- End WT-branch 51 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_18 is port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_34_18; ------------------------------------------------------------ -- End: Multiplier Entitiy architecture MULTIPLIER of MULTIPLIER_34_18 is signal PPBIT:std_logic_vector(0 to 332); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_18 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 17) => MULTIPLIER(0 to 17), SUMMAND(0 to 332) => PPBIT(0 to 332) ); W:WALLACE_34_18 port map ( SUMMAND(0 to 332) => PPBIT(0 to 332), CARRY(0 to 49) => INT_CARRY(1 to 50), SUM(0 to 50) => INT_SUM(0 to 50) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUM(0 to 63), OPB(0 to 63) => INT_CARRY(0 to 63), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ -- -- Modgen multiplier created Fri Aug 16 16:29:15 2002 -- ------------------------------------------------------------ -- START: Multiplier Entitiy ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -- START: Top entity ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_17 is port(X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(16 downto 0); P: out std_logic_vector(49 downto 0)); end MUL_33_17; library ieee; use ieee.std_logic_1164.all; architecture A of MUL_33_17 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 17); signal Q: std_logic_vector(0 to 63); signal CLK: std_logic; begin U1: MULTIPLIER_34_18 port map(A,B,CLK,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(16); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); P(42) <= Q(42); P(43) <= Q(43); P(44) <= Q(44); P(45) <= Q(45); P(46) <= Q(46); P(47) <= Q(47); P(48) <= Q(48); P(49) <= Q(49); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_34 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 33); SUMMAND: out std_logic_vector(0 to 628) ); end BOOTHCODER_34_34; architecture BOOTHCODER of BOOTHCODER_34_34 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 67); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(110) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(120) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(132) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(143) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(156) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(168) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(182) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(195) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(210) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(224) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(240) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(255) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(272) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(288) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(306) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(323) ); SUMMAND(324) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(100) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(111) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(121) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(133) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(144) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(157) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(169) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(183) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(196) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(211) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(225) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(241) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(256) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(273) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(289) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(307) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(325) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(341) ); SUMMAND(342) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(358) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(101) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(112) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(122) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(134) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(145) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(158) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(170) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(184) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(197) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(212) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(226) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(242) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(257) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(274) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(290) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(308) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(326) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(343) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(359) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(374) ); SUMMAND(375) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(390) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(102) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(113) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(123) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(135) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(146) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(159) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(171) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(185) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(198) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(213) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(227) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(243) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(258) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(275) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(291) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(309) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(327) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(344) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(360) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(376) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(391) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(405) ); SUMMAND(406) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(420) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(103) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(114) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(124) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(136) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(147) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(172) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(186) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(199) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(214) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(228) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(244) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(259) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(276) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(292) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(310) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(328) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(345) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(361) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(377) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(392) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(407) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(421) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(434) ); SUMMAND(435) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(448) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_165:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_166:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_167:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_168:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_169:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_170:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_171:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_172:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(104) ); PPM_173:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(115) ); PPM_174:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(125) ); PPM_175:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(137) ); PPM_176:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(148) ); PPM_177:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(161) ); PPM_178:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(173) ); PPM_179:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(187) ); PPM_180:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(200) ); PPM_181:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(215) ); PPM_182:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(229) ); PPM_183:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(245) ); PPM_184:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(260) ); PPM_185:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(277) ); PPM_186:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(293) ); PPM_187:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(311) ); PPM_188:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(329) ); PPM_189:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(346) ); PPM_190:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(362) ); PPM_191:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(378) ); PPM_192:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(393) ); PPM_193:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(408) ); PPM_194:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(422) ); PPM_195:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(436) ); PPM_196:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(449) ); PPM_197:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(461) ); SUMMAND(462) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(474) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_198:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_199:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_200:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_201:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_202:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_203:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(105) ); PPM_204:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(116) ); PPM_205:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(126) ); PPM_206:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(138) ); PPM_207:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(149) ); PPM_208:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(162) ); PPM_209:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(174) ); PPM_210:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(188) ); PPM_211:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(201) ); PPM_212:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(216) ); PPM_213:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(230) ); PPM_214:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(246) ); PPM_215:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(261) ); PPM_216:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(278) ); PPM_217:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(294) ); PPM_218:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(312) ); PPM_219:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(330) ); PPM_220:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(347) ); PPM_221:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(363) ); PPM_222:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(379) ); PPM_223:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(394) ); PPM_224:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(409) ); PPM_225:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(423) ); PPM_226:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(437) ); PPM_227:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(450) ); PPM_228:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(463) ); PPM_229:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(475) ); PPM_230:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(486) ); SUMMAND(487) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(498) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_231:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_232:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_233:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_234:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(106) ); PPM_235:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(117) ); PPM_236:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(127) ); PPM_237:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(139) ); PPM_238:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(150) ); PPM_239:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(163) ); PPM_240:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(175) ); PPM_241:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(189) ); PPM_242:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(202) ); PPM_243:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(217) ); PPM_244:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(231) ); PPM_245:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(247) ); PPM_246:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(262) ); PPM_247:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(279) ); PPM_248:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(295) ); PPM_249:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(313) ); PPM_250:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(331) ); PPM_251:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(348) ); PPM_252:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(364) ); PPM_253:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(380) ); PPM_254:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(395) ); PPM_255:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(410) ); PPM_256:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(424) ); PPM_257:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(438) ); PPM_258:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(451) ); PPM_259:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(464) ); PPM_260:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(476) ); PPM_261:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(488) ); PPM_262:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(499) ); PPM_263:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(509) ); SUMMAND(510) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(520) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_264:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_265:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(107) ); PPM_266:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(118) ); PPM_267:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(128) ); PPM_268:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(140) ); PPM_269:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(151) ); PPM_270:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(164) ); PPM_271:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(176) ); PPM_272:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(190) ); PPM_273:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(203) ); PPM_274:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(218) ); PPM_275:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(232) ); PPM_276:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(248) ); PPM_277:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(263) ); PPM_278:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(280) ); PPM_279:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(296) ); PPM_280:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(314) ); PPM_281:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(332) ); PPM_282:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(349) ); PPM_283:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(365) ); PPM_284:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(381) ); PPM_285:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(396) ); PPM_286:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(411) ); PPM_287:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(425) ); PPM_288:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(439) ); PPM_289:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(452) ); PPM_290:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(465) ); PPM_291:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(477) ); PPM_292:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(489) ); PPM_293:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(500) ); PPM_294:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(511) ); PPM_295:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(521) ); PPM_296:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(530) ); SUMMAND(531) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(540) ); -- Begin partial product 9 -- Begin decoder block 10 DEC_9:DECODER -- Decoder of multiplier operand port map ( INA => OPB(17),INB => OPB(18),INC => OPB(19), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39) ); -- End decoder block 10 -- Begin partial product 10 PPL_9:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(108) ); RGATE_9:R_GATE port map ( INA => OPB(17),INB => OPB(18),INC => OPB(19), PPBIT => SUMMAND(109) ); PPM_297:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(119) ); PPM_298:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(129) ); PPM_299:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(141) ); PPM_300:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(152) ); PPM_301:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(165) ); PPM_302:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(177) ); PPM_303:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(191) ); PPM_304:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(204) ); PPM_305:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(219) ); PPM_306:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(233) ); PPM_307:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(249) ); PPM_308:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(264) ); PPM_309:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(281) ); PPM_310:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(297) ); PPM_311:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(315) ); PPM_312:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(333) ); PPM_313:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(350) ); PPM_314:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(366) ); PPM_315:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(382) ); PPM_316:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(397) ); PPM_317:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(412) ); PPM_318:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(426) ); PPM_319:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(440) ); PPM_320:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(453) ); PPM_321:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(466) ); PPM_322:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(478) ); PPM_323:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(490) ); PPM_324:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(501) ); PPM_325:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(512) ); PPM_326:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(522) ); PPM_327:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(532) ); PPM_328:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(541) ); PPM_329:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(549) ); SUMMAND(550) <= LOGIC_ONE; PPH_9:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(558) ); -- Begin partial product 10 -- Begin decoder block 11 DEC_10:DECODER -- Decoder of multiplier operand port map ( INA => OPB(19),INB => OPB(20),INC => OPB(21), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43) ); -- End decoder block 11 -- Begin partial product 11 PPL_10:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(130) ); RGATE_10:R_GATE port map ( INA => OPB(19),INB => OPB(20),INC => OPB(21), PPBIT => SUMMAND(131) ); PPM_330:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(142) ); PPM_331:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(153) ); PPM_332:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(166) ); PPM_333:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(178) ); PPM_334:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(192) ); PPM_335:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(205) ); PPM_336:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(220) ); PPM_337:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(234) ); PPM_338:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(250) ); PPM_339:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(265) ); PPM_340:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(282) ); PPM_341:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(298) ); PPM_342:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(316) ); PPM_343:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(334) ); PPM_344:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(351) ); PPM_345:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(367) ); PPM_346:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(383) ); PPM_347:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(398) ); PPM_348:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(413) ); PPM_349:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(427) ); PPM_350:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(441) ); PPM_351:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(454) ); PPM_352:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(467) ); PPM_353:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(479) ); PPM_354:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(491) ); PPM_355:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(502) ); PPM_356:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(513) ); PPM_357:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(523) ); PPM_358:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(533) ); PPM_359:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(542) ); PPM_360:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(551) ); PPM_361:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(559) ); PPM_362:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(566) ); SUMMAND(567) <= LOGIC_ONE; PPH_10:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(574) ); -- Begin partial product 11 -- Begin decoder block 12 DEC_11:DECODER -- Decoder of multiplier operand port map ( INA => OPB(21),INB => OPB(22),INC => OPB(23), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47) ); -- End decoder block 12 -- Begin partial product 12 PPL_11:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(154) ); RGATE_11:R_GATE port map ( INA => OPB(21),INB => OPB(22),INC => OPB(23), PPBIT => SUMMAND(155) ); PPM_363:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(167) ); PPM_364:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(179) ); PPM_365:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(193) ); PPM_366:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(206) ); PPM_367:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(221) ); PPM_368:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(235) ); PPM_369:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(251) ); PPM_370:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(266) ); PPM_371:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(283) ); PPM_372:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(299) ); PPM_373:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(317) ); PPM_374:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(335) ); PPM_375:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(352) ); PPM_376:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(368) ); PPM_377:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(384) ); PPM_378:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(399) ); PPM_379:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(414) ); PPM_380:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(428) ); PPM_381:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(442) ); PPM_382:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(455) ); PPM_383:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(468) ); PPM_384:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(480) ); PPM_385:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(492) ); PPM_386:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(503) ); PPM_387:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(514) ); PPM_388:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(524) ); PPM_389:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(534) ); PPM_390:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(543) ); PPM_391:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(552) ); PPM_392:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(560) ); PPM_393:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(568) ); PPM_394:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(575) ); PPM_395:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(581) ); SUMMAND(582) <= LOGIC_ONE; PPH_11:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(588) ); -- Begin partial product 12 -- Begin decoder block 13 DEC_12:DECODER -- Decoder of multiplier operand port map ( INA => OPB(23),INB => OPB(24),INC => OPB(25), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51) ); -- End decoder block 13 -- Begin partial product 13 PPL_12:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(180) ); RGATE_12:R_GATE port map ( INA => OPB(23),INB => OPB(24),INC => OPB(25), PPBIT => SUMMAND(181) ); PPM_396:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(194) ); PPM_397:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(207) ); PPM_398:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(222) ); PPM_399:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(236) ); PPM_400:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(252) ); PPM_401:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(267) ); PPM_402:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(284) ); PPM_403:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(300) ); PPM_404:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(318) ); PPM_405:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(336) ); PPM_406:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(353) ); PPM_407:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(369) ); PPM_408:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(385) ); PPM_409:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(400) ); PPM_410:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(415) ); PPM_411:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(429) ); PPM_412:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(443) ); PPM_413:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(456) ); PPM_414:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(469) ); PPM_415:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(481) ); PPM_416:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(493) ); PPM_417:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(504) ); PPM_418:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(515) ); PPM_419:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(525) ); PPM_420:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(535) ); PPM_421:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(544) ); PPM_422:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(553) ); PPM_423:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(561) ); PPM_424:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(569) ); PPM_425:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(576) ); PPM_426:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(583) ); PPM_427:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(589) ); PPM_428:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(594) ); SUMMAND(595) <= LOGIC_ONE; PPH_12:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(600) ); -- Begin partial product 13 -- Begin decoder block 14 DEC_13:DECODER -- Decoder of multiplier operand port map ( INA => OPB(25),INB => OPB(26),INC => OPB(27), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55) ); -- End decoder block 14 -- Begin partial product 14 PPL_13:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(208) ); RGATE_13:R_GATE port map ( INA => OPB(25),INB => OPB(26),INC => OPB(27), PPBIT => SUMMAND(209) ); PPM_429:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(223) ); PPM_430:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(237) ); PPM_431:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(253) ); PPM_432:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(268) ); PPM_433:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(285) ); PPM_434:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(301) ); PPM_435:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(319) ); PPM_436:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(337) ); PPM_437:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(354) ); PPM_438:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(370) ); PPM_439:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(386) ); PPM_440:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(401) ); PPM_441:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(416) ); PPM_442:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(430) ); PPM_443:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(444) ); PPM_444:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(457) ); PPM_445:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(470) ); PPM_446:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(482) ); PPM_447:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(494) ); PPM_448:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(505) ); PPM_449:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(516) ); PPM_450:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(526) ); PPM_451:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(536) ); PPM_452:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(545) ); PPM_453:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(554) ); PPM_454:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(562) ); PPM_455:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(570) ); PPM_456:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(577) ); PPM_457:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(584) ); PPM_458:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(590) ); PPM_459:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(596) ); PPM_460:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(601) ); PPM_461:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(605) ); SUMMAND(606) <= LOGIC_ONE; PPH_13:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(610) ); -- Begin partial product 14 -- Begin decoder block 15 DEC_14:DECODER -- Decoder of multiplier operand port map ( INA => OPB(27),INB => OPB(28),INC => OPB(29), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59) ); -- End decoder block 15 -- Begin partial product 15 PPL_14:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(238) ); RGATE_14:R_GATE port map ( INA => OPB(27),INB => OPB(28),INC => OPB(29), PPBIT => SUMMAND(239) ); PPM_462:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(254) ); PPM_463:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(269) ); PPM_464:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(286) ); PPM_465:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(302) ); PPM_466:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(320) ); PPM_467:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(338) ); PPM_468:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(355) ); PPM_469:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(371) ); PPM_470:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(387) ); PPM_471:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(402) ); PPM_472:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(417) ); PPM_473:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(431) ); PPM_474:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(445) ); PPM_475:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(458) ); PPM_476:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(471) ); PPM_477:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(483) ); PPM_478:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(495) ); PPM_479:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(506) ); PPM_480:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(517) ); PPM_481:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(527) ); PPM_482:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(537) ); PPM_483:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(546) ); PPM_484:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(555) ); PPM_485:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(563) ); PPM_486:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(571) ); PPM_487:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(578) ); PPM_488:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(585) ); PPM_489:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(591) ); PPM_490:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(597) ); PPM_491:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(602) ); PPM_492:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(607) ); PPM_493:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(611) ); PPM_494:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(614) ); SUMMAND(615) <= LOGIC_ONE; PPH_14:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(618) ); -- Begin partial product 15 -- Begin decoder block 16 DEC_15:DECODER -- Decoder of multiplier operand port map ( INA => OPB(29),INB => OPB(30),INC => OPB(31), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63) ); -- End decoder block 16 -- Begin partial product 16 PPL_15:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(270) ); RGATE_15:R_GATE port map ( INA => OPB(29),INB => OPB(30),INC => OPB(31), PPBIT => SUMMAND(271) ); PPM_495:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(287) ); PPM_496:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(303) ); PPM_497:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(321) ); PPM_498:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(339) ); PPM_499:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(356) ); PPM_500:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(372) ); PPM_501:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(388) ); PPM_502:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(403) ); PPM_503:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(418) ); PPM_504:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(432) ); PPM_505:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(446) ); PPM_506:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(459) ); PPM_507:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(472) ); PPM_508:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(484) ); PPM_509:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(496) ); PPM_510:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(507) ); PPM_511:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(518) ); PPM_512:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(528) ); PPM_513:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(538) ); PPM_514:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(547) ); PPM_515:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(556) ); PPM_516:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(564) ); PPM_517:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(572) ); PPM_518:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(579) ); PPM_519:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(586) ); PPM_520:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(592) ); PPM_521:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(598) ); PPM_522:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(603) ); PPM_523:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(608) ); PPM_524:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(612) ); PPM_525:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(616) ); PPM_526:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(619) ); PPM_527:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(621) ); SUMMAND(622) <= LOGIC_ONE; PPH_15:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(624) ); -- Begin partial product 16 -- Begin decoder block 17 DEC_16:DECODER -- Decoder of multiplier operand port map ( INA => OPB(31),INB => OPB(32),INC => OPB(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67) ); -- End decoder block 17 -- Begin partial product 17 PPL_16:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(304) ); RGATE_16:R_GATE port map ( INA => OPB(31),INB => OPB(32),INC => OPB(33), PPBIT => SUMMAND(305) ); PPM_528:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(322) ); PPM_529:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(340) ); PPM_530:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(357) ); PPM_531:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(373) ); PPM_532:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(389) ); PPM_533:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(404) ); PPM_534:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(419) ); PPM_535:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(433) ); PPM_536:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(447) ); PPM_537:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(460) ); PPM_538:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(473) ); PPM_539:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(485) ); PPM_540:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(497) ); PPM_541:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(508) ); PPM_542:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(519) ); PPM_543:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(529) ); PPM_544:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(539) ); PPM_545:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(548) ); PPM_546:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(557) ); PPM_547:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(565) ); PPM_548:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(573) ); PPM_549:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(580) ); PPM_550:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(587) ); PPM_551:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(593) ); PPM_552:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(599) ); PPM_553:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(604) ); PPM_554:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(609) ); PPM_555:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(613) ); PPM_556:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(617) ); PPM_557:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(620) ); PPM_558:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(623) ); PPM_559:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(625) ); PPM_560:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(626) ); SUMMAND(627) <= LOGIC_ONE; PPH_16:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(628) ); -- Begin partial product 17 end BOOTHCODER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_34 is port ( SUMMAND: in std_logic_vector(0 to 628); CARRY: out std_logic_vector(0 to 65); SUM: out std_logic_vector(0 to 66) ); end WALLACE_34_34; architecture WALLACE of WALLACE_34_34 is -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 486); signal INT_SUM: std_logic_vector(0 to 620); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin NO stage INT_SUM(76) <= SUMMAND(108); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(77) <= SUMMAND(109); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(78), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(49), SAVE => INT_SUM(79), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin NO stage INT_SUM(80) <= INT_CARRY(50); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(81) <= INT_CARRY(51); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_SUM(80), SAVE => INT_SUM(82), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(81), DATA_B => INT_CARRY(52), DATA_C => INT_CARRY(53), SAVE => INT_SUM(83), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin FA stage FA_64:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(54), SAVE => INT_SUM(84), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(84), DATA_B => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End HA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_65:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112), SAVE => INT_SUM(85), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), DATA_C => SUMMAND(115), SAVE => INT_SUM(86), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(116), DATA_B => SUMMAND(117), DATA_C => SUMMAND(118), SAVE => INT_SUM(87), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin NO stage INT_SUM(88) <= SUMMAND(119); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(56), DATA_C => INT_CARRY(57), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(91) <= INT_CARRY(58); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91), SAVE => INT_SUM(92), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(59), DATA_B => INT_CARRY(60), SAVE => INT_SUM(93), CARRY => INT_CARRY(70) ); ---- End HA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(61), SAVE => INT_SUM(94), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(62); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(63), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End FA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125), SAVE => INT_SUM(97), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(98), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(99), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_SUM(98), SAVE => INT_SUM(100), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(99), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65), SAVE => INT_SUM(101), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin NO stage INT_SUM(102) <= INT_CARRY(66); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_79:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_SUM(102), SAVE => INT_SUM(103), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(67), DATA_B => INT_CARRY(68), SAVE => INT_SUM(104), CARRY => INT_CARRY(79) ); ---- End HA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(103), DATA_B => INT_SUM(104), DATA_C => INT_CARRY(69), SAVE => INT_SUM(105), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin NO stage INT_SUM(106) <= INT_CARRY(70); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_CARRY(71), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_82:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134), SAVE => INT_SUM(107), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(108), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140), SAVE => INT_SUM(109), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(110) <= SUMMAND(141); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(111) <= SUMMAND(142); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_85:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(107), DATA_B => INT_SUM(108), DATA_C => INT_SUM(109), SAVE => INT_SUM(112), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(72), SAVE => INT_SUM(113), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(73), DATA_B => INT_CARRY(74), DATA_C => INT_CARRY(75), SAVE => INT_SUM(114), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_SUM(114), SAVE => INT_SUM(115), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), SAVE => INT_SUM(116), CARRY => INT_CARRY(88) ); ---- End HA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(78), SAVE => INT_SUM(117), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(118) <= INT_CARRY(79); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_CARRY(80), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_91:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), DATA_C => SUMMAND(145), SAVE => INT_SUM(119), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(146), DATA_B => SUMMAND(147), DATA_C => SUMMAND(148), SAVE => INT_SUM(120), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(149), DATA_B => SUMMAND(150), DATA_C => SUMMAND(151), SAVE => INT_SUM(121), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(152), DATA_B => SUMMAND(153), DATA_C => SUMMAND(154), SAVE => INT_SUM(122), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= SUMMAND(155); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(119), DATA_B => INT_SUM(120), DATA_C => INT_SUM(121), SAVE => INT_SUM(124), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(81), SAVE => INT_SUM(125), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83), SAVE => INT_SUM(126), CARRY => INT_CARRY(96) ); ---- End HA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_SUM(126), SAVE => INT_SUM(127), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86), SAVE => INT_SUM(128), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin FA stage FA_99:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(127), DATA_B => INT_SUM(128), DATA_C => INT_CARRY(87), SAVE => INT_SUM(129), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin NO stage INT_SUM(130) <= INT_CARRY(88); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_CARRY(89), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_101:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158), SAVE => INT_SUM(131), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161), SAVE => INT_SUM(132), CARRY => INT_CARRY(101) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164), SAVE => INT_SUM(133), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(134), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin FA stage FA_105:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(131), DATA_B => INT_SUM(132), DATA_C => INT_SUM(133), SAVE => INT_SUM(135), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin FA stage FA_106:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(134), DATA_B => INT_CARRY(90), DATA_C => INT_CARRY(91), SAVE => INT_SUM(136), CARRY => INT_CARRY(105) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(92), DATA_B => INT_CARRY(93), SAVE => INT_SUM(137), CARRY => INT_CARRY(106) ); ---- End HA stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_SUM(137), SAVE => INT_SUM(138), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin FA stage FA_108:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(94), DATA_B => INT_CARRY(95), DATA_C => INT_CARRY(96), SAVE => INT_SUM(139), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(138), DATA_B => INT_SUM(139), DATA_C => INT_CARRY(97), SAVE => INT_SUM(140), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin NO stage INT_SUM(141) <= INT_CARRY(98); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(99), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_111:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170), SAVE => INT_SUM(142), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173), SAVE => INT_SUM(143), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin FA stage FA_113:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(144), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin FA stage FA_114:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(145), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), SAVE => INT_SUM(146), CARRY => INT_CARRY(114) ); ---- End HA stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_SUM(144), SAVE => INT_SUM(147), CARRY => INT_CARRY(115) ); ---- End FA stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(100), SAVE => INT_SUM(148), CARRY => INT_CARRY(116) ); ---- End FA stage ---- Begin FA stage FA_117:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(101), DATA_B => INT_CARRY(102), DATA_C => INT_CARRY(103), SAVE => INT_SUM(149), CARRY => INT_CARRY(117) ); ---- End FA stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(147), DATA_B => INT_SUM(148), DATA_C => INT_SUM(149), SAVE => INT_SUM(150), CARRY => INT_CARRY(118) ); ---- End FA stage ---- Begin FA stage FA_119:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(104), DATA_B => INT_CARRY(105), DATA_C => INT_CARRY(106), SAVE => INT_SUM(151), CARRY => INT_CARRY(119) ); ---- End FA stage ---- Begin FA stage FA_120:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(107), SAVE => INT_SUM(152), CARRY => INT_CARRY(120) ); ---- End FA stage ---- Begin NO stage INT_SUM(153) <= INT_CARRY(108); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_121:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(152), DATA_B => INT_SUM(153), DATA_C => INT_CARRY(109), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_122:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), DATA_C => SUMMAND(184), SAVE => INT_SUM(154), CARRY => INT_CARRY(121) ); ---- End FA stage ---- Begin FA stage FA_123:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(185), DATA_B => SUMMAND(186), DATA_C => SUMMAND(187), SAVE => INT_SUM(155), CARRY => INT_CARRY(122) ); ---- End FA stage ---- Begin FA stage FA_124:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(188), DATA_B => SUMMAND(189), DATA_C => SUMMAND(190), SAVE => INT_SUM(156), CARRY => INT_CARRY(123) ); ---- End FA stage ---- Begin FA stage FA_125:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(191), DATA_B => SUMMAND(192), DATA_C => SUMMAND(193), SAVE => INT_SUM(157), CARRY => INT_CARRY(124) ); ---- End FA stage ---- Begin NO stage INT_SUM(158) <= SUMMAND(194); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_126:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(154), DATA_B => INT_SUM(155), DATA_C => INT_SUM(156), SAVE => INT_SUM(159), CARRY => INT_CARRY(125) ); ---- End FA stage ---- Begin FA stage FA_127:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(110), SAVE => INT_SUM(160), CARRY => INT_CARRY(126) ); ---- End FA stage ---- Begin FA stage FA_128:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(111), DATA_B => INT_CARRY(112), DATA_C => INT_CARRY(113), SAVE => INT_SUM(161), CARRY => INT_CARRY(127) ); ---- End FA stage ---- Begin NO stage INT_SUM(162) <= INT_CARRY(114); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_129:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(159), DATA_B => INT_SUM(160), DATA_C => INT_SUM(161), SAVE => INT_SUM(163), CARRY => INT_CARRY(128) ); ---- End FA stage ---- Begin FA stage FA_130:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(162), DATA_B => INT_CARRY(115), DATA_C => INT_CARRY(116), SAVE => INT_SUM(164), CARRY => INT_CARRY(129) ); ---- End FA stage ---- Begin NO stage INT_SUM(165) <= INT_CARRY(117); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_131:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(163), DATA_B => INT_SUM(164), DATA_C => INT_SUM(165), SAVE => INT_SUM(166), CARRY => INT_CARRY(130) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(118), DATA_B => INT_CARRY(119), SAVE => INT_SUM(167), CARRY => INT_CARRY(131) ); ---- End HA stage ---- Begin FA stage FA_132:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(120), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End FA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_133:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197), SAVE => INT_SUM(168), CARRY => INT_CARRY(132) ); ---- End FA stage ---- Begin FA stage FA_134:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200), SAVE => INT_SUM(169), CARRY => INT_CARRY(133) ); ---- End FA stage ---- Begin FA stage FA_135:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203), SAVE => INT_SUM(170), CARRY => INT_CARRY(134) ); ---- End FA stage ---- Begin FA stage FA_136:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206), SAVE => INT_SUM(171), CARRY => INT_CARRY(135) ); ---- End FA stage ---- Begin FA stage FA_137:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209), SAVE => INT_SUM(172), CARRY => INT_CARRY(136) ); ---- End FA stage ---- Begin FA stage FA_138:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(168), DATA_B => INT_SUM(169), DATA_C => INT_SUM(170), SAVE => INT_SUM(173), CARRY => INT_CARRY(137) ); ---- End FA stage ---- Begin FA stage FA_139:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(171), DATA_B => INT_SUM(172), DATA_C => INT_CARRY(121), SAVE => INT_SUM(174), CARRY => INT_CARRY(138) ); ---- End FA stage ---- Begin FA stage FA_140:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(122), DATA_B => INT_CARRY(123), DATA_C => INT_CARRY(124), SAVE => INT_SUM(175), CARRY => INT_CARRY(139) ); ---- End FA stage ---- Begin FA stage FA_141:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(173), DATA_B => INT_SUM(174), DATA_C => INT_SUM(175), SAVE => INT_SUM(176), CARRY => INT_CARRY(140) ); ---- End FA stage ---- Begin FA stage FA_142:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(125), DATA_B => INT_CARRY(126), DATA_C => INT_CARRY(127), SAVE => INT_SUM(177), CARRY => INT_CARRY(141) ); ---- End FA stage ---- Begin FA stage FA_143:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(176), DATA_B => INT_SUM(177), DATA_C => INT_CARRY(128), SAVE => INT_SUM(178), CARRY => INT_CARRY(142) ); ---- End FA stage ---- Begin NO stage INT_SUM(179) <= INT_CARRY(129); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_144:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(178), DATA_B => INT_SUM(179), DATA_C => INT_CARRY(130), SAVE => INT_SUM(180), CARRY => INT_CARRY(143) ); ---- End FA stage ---- Begin NO stage INT_SUM(181) <= INT_CARRY(131); -- At Level 5 ---- End NO stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_145:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212), SAVE => INT_SUM(182), CARRY => INT_CARRY(144) ); ---- End FA stage ---- Begin FA stage FA_146:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215), SAVE => INT_SUM(183), CARRY => INT_CARRY(145) ); ---- End FA stage ---- Begin FA stage FA_147:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218), SAVE => INT_SUM(184), CARRY => INT_CARRY(146) ); ---- End FA stage ---- Begin FA stage FA_148:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221), SAVE => INT_SUM(185), CARRY => INT_CARRY(147) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), SAVE => INT_SUM(186), CARRY => INT_CARRY(148) ); ---- End HA stage ---- Begin FA stage FA_149:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_SUM(184), SAVE => INT_SUM(187), CARRY => INT_CARRY(149) ); ---- End FA stage ---- Begin FA stage FA_150:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_CARRY(132), SAVE => INT_SUM(188), CARRY => INT_CARRY(150) ); ---- End FA stage ---- Begin FA stage FA_151:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135), SAVE => INT_SUM(189), CARRY => INT_CARRY(151) ); ---- End FA stage ---- Begin NO stage INT_SUM(190) <= INT_CARRY(136); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_152:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(187), DATA_B => INT_SUM(188), DATA_C => INT_SUM(189), SAVE => INT_SUM(191), CARRY => INT_CARRY(152) ); ---- End FA stage ---- Begin FA stage FA_153:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(190), DATA_B => INT_CARRY(137), DATA_C => INT_CARRY(138), SAVE => INT_SUM(192), CARRY => INT_CARRY(153) ); ---- End FA stage ---- Begin NO stage INT_SUM(193) <= INT_CARRY(139); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_154:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(191), DATA_B => INT_SUM(192), DATA_C => INT_SUM(193), SAVE => INT_SUM(194), CARRY => INT_CARRY(154) ); ---- End FA stage ---- Begin NO stage INT_SUM(195) <= INT_CARRY(140); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(196) <= INT_CARRY(141); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_155:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(194), DATA_B => INT_SUM(195), DATA_C => INT_SUM(196), SAVE => INT_SUM(197), CARRY => INT_CARRY(155) ); ---- End FA stage ---- Begin NO stage INT_SUM(198) <= INT_CARRY(142); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_156:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(197), DATA_B => INT_SUM(198), DATA_C => INT_CARRY(143), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End FA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_157:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(224), DATA_B => SUMMAND(225), DATA_C => SUMMAND(226), SAVE => INT_SUM(199), CARRY => INT_CARRY(156) ); ---- End FA stage ---- Begin FA stage FA_158:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(227), DATA_B => SUMMAND(228), DATA_C => SUMMAND(229), SAVE => INT_SUM(200), CARRY => INT_CARRY(157) ); ---- End FA stage ---- Begin FA stage FA_159:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(230), DATA_B => SUMMAND(231), DATA_C => SUMMAND(232), SAVE => INT_SUM(201), CARRY => INT_CARRY(158) ); ---- End FA stage ---- Begin FA stage FA_160:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(233), DATA_B => SUMMAND(234), DATA_C => SUMMAND(235), SAVE => INT_SUM(202), CARRY => INT_CARRY(159) ); ---- End FA stage ---- Begin FA stage FA_161:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(236), DATA_B => SUMMAND(237), DATA_C => SUMMAND(238), SAVE => INT_SUM(203), CARRY => INT_CARRY(160) ); ---- End FA stage ---- Begin NO stage INT_SUM(204) <= SUMMAND(239); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_162:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(199), DATA_B => INT_SUM(200), DATA_C => INT_SUM(201), SAVE => INT_SUM(205), CARRY => INT_CARRY(161) ); ---- End FA stage ---- Begin FA stage FA_163:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(202), DATA_B => INT_SUM(203), DATA_C => INT_SUM(204), SAVE => INT_SUM(206), CARRY => INT_CARRY(162) ); ---- End FA stage ---- Begin FA stage FA_164:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(144), DATA_B => INT_CARRY(145), DATA_C => INT_CARRY(146), SAVE => INT_SUM(207), CARRY => INT_CARRY(163) ); ---- End FA stage ---- Begin NO stage INT_SUM(208) <= INT_CARRY(147); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(209) <= INT_CARRY(148); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_165:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207), SAVE => INT_SUM(210), CARRY => INT_CARRY(164) ); ---- End FA stage ---- Begin FA stage FA_166:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_CARRY(149), SAVE => INT_SUM(211), CARRY => INT_CARRY(165) ); ---- End FA stage ---- Begin NO stage INT_SUM(212) <= INT_CARRY(150); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(213) <= INT_CARRY(151); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_167:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(210), DATA_B => INT_SUM(211), DATA_C => INT_SUM(212), SAVE => INT_SUM(214), CARRY => INT_CARRY(166) ); ---- End FA stage ---- Begin FA stage FA_168:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(213), DATA_B => INT_CARRY(152), DATA_C => INT_CARRY(153), SAVE => INT_SUM(215), CARRY => INT_CARRY(167) ); ---- End FA stage ---- Begin FA stage FA_169:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(214), DATA_B => INT_SUM(215), DATA_C => INT_CARRY(154), SAVE => INT_SUM(216), CARRY => INT_CARRY(168) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(216), DATA_B => INT_CARRY(155), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_170:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242), SAVE => INT_SUM(217), CARRY => INT_CARRY(169) ); ---- End FA stage ---- Begin FA stage FA_171:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245), SAVE => INT_SUM(218), CARRY => INT_CARRY(170) ); ---- End FA stage ---- Begin FA stage FA_172:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248), SAVE => INT_SUM(219), CARRY => INT_CARRY(171) ); ---- End FA stage ---- Begin FA stage FA_173:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251), SAVE => INT_SUM(220), CARRY => INT_CARRY(172) ); ---- End FA stage ---- Begin FA stage FA_174:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(252), DATA_B => SUMMAND(253), DATA_C => SUMMAND(254), SAVE => INT_SUM(221), CARRY => INT_CARRY(173) ); ---- End FA stage ---- Begin FA stage FA_175:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_SUM(219), SAVE => INT_SUM(222), CARRY => INT_CARRY(174) ); ---- End FA stage ---- Begin FA stage FA_176:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_CARRY(156), SAVE => INT_SUM(223), CARRY => INT_CARRY(175) ); ---- End FA stage ---- Begin FA stage FA_177:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(157), DATA_B => INT_CARRY(158), DATA_C => INT_CARRY(159), SAVE => INT_SUM(224), CARRY => INT_CARRY(176) ); ---- End FA stage ---- Begin NO stage INT_SUM(225) <= INT_CARRY(160); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_178:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(222), DATA_B => INT_SUM(223), DATA_C => INT_SUM(224), SAVE => INT_SUM(226), CARRY => INT_CARRY(177) ); ---- End FA stage ---- Begin FA stage FA_179:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(225), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162), SAVE => INT_SUM(227), CARRY => INT_CARRY(178) ); ---- End FA stage ---- Begin NO stage INT_SUM(228) <= INT_CARRY(163); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_180:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_SUM(228), SAVE => INT_SUM(229), CARRY => INT_CARRY(179) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(164), DATA_B => INT_CARRY(165), SAVE => INT_SUM(230), CARRY => INT_CARRY(180) ); ---- End HA stage ---- Begin FA stage FA_181:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(229), DATA_B => INT_SUM(230), DATA_C => INT_CARRY(166), SAVE => INT_SUM(231), CARRY => INT_CARRY(181) ); ---- End FA stage ---- Begin NO stage INT_SUM(232) <= INT_CARRY(167); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_182:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(231), DATA_B => INT_SUM(232), DATA_C => INT_CARRY(168), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_183:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(255), DATA_B => SUMMAND(256), DATA_C => SUMMAND(257), SAVE => INT_SUM(233), CARRY => INT_CARRY(182) ); ---- End FA stage ---- Begin FA stage FA_184:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(258), DATA_B => SUMMAND(259), DATA_C => SUMMAND(260), SAVE => INT_SUM(234), CARRY => INT_CARRY(183) ); ---- End FA stage ---- Begin FA stage FA_185:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(261), DATA_B => SUMMAND(262), DATA_C => SUMMAND(263), SAVE => INT_SUM(235), CARRY => INT_CARRY(184) ); ---- End FA stage ---- Begin FA stage FA_186:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(264), DATA_B => SUMMAND(265), DATA_C => SUMMAND(266), SAVE => INT_SUM(236), CARRY => INT_CARRY(185) ); ---- End FA stage ---- Begin FA stage FA_187:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(267), DATA_B => SUMMAND(268), DATA_C => SUMMAND(269), SAVE => INT_SUM(237), CARRY => INT_CARRY(186) ); ---- End FA stage ---- Begin NO stage INT_SUM(238) <= SUMMAND(270); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(239) <= SUMMAND(271); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_188:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(233), DATA_B => INT_SUM(234), DATA_C => INT_SUM(235), SAVE => INT_SUM(240), CARRY => INT_CARRY(187) ); ---- End FA stage ---- Begin FA stage FA_189:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_SUM(238), SAVE => INT_SUM(241), CARRY => INT_CARRY(188) ); ---- End FA stage ---- Begin FA stage FA_190:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(239), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170), SAVE => INT_SUM(242), CARRY => INT_CARRY(189) ); ---- End FA stage ---- Begin FA stage FA_191:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(171), DATA_B => INT_CARRY(172), DATA_C => INT_CARRY(173), SAVE => INT_SUM(243), CARRY => INT_CARRY(190) ); ---- End FA stage ---- Begin FA stage FA_192:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(240), DATA_B => INT_SUM(241), DATA_C => INT_SUM(242), SAVE => INT_SUM(244), CARRY => INT_CARRY(191) ); ---- End FA stage ---- Begin FA stage FA_193:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(243), DATA_B => INT_CARRY(174), DATA_C => INT_CARRY(175), SAVE => INT_SUM(245), CARRY => INT_CARRY(192) ); ---- End FA stage ---- Begin NO stage INT_SUM(246) <= INT_CARRY(176); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_194:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(244), DATA_B => INT_SUM(245), DATA_C => INT_SUM(246), SAVE => INT_SUM(247), CARRY => INT_CARRY(193) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(177), DATA_B => INT_CARRY(178), SAVE => INT_SUM(248), CARRY => INT_CARRY(194) ); ---- End HA stage ---- Begin FA stage FA_195:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(247), DATA_B => INT_SUM(248), DATA_C => INT_CARRY(179), SAVE => INT_SUM(249), CARRY => INT_CARRY(195) ); ---- End FA stage ---- Begin NO stage INT_SUM(250) <= INT_CARRY(180); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_196:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(249), DATA_B => INT_SUM(250), DATA_C => INT_CARRY(181), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_197:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(272), DATA_B => SUMMAND(273), DATA_C => SUMMAND(274), SAVE => INT_SUM(251), CARRY => INT_CARRY(196) ); ---- End FA stage ---- Begin FA stage FA_198:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(275), DATA_B => SUMMAND(276), DATA_C => SUMMAND(277), SAVE => INT_SUM(252), CARRY => INT_CARRY(197) ); ---- End FA stage ---- Begin FA stage FA_199:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280), SAVE => INT_SUM(253), CARRY => INT_CARRY(198) ); ---- End FA stage ---- Begin FA stage FA_200:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283), SAVE => INT_SUM(254), CARRY => INT_CARRY(199) ); ---- End FA stage ---- Begin FA stage FA_201:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(284), DATA_B => SUMMAND(285), DATA_C => SUMMAND(286), SAVE => INT_SUM(255), CARRY => INT_CARRY(200) ); ---- End FA stage ---- Begin NO stage INT_SUM(256) <= SUMMAND(287); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_202:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(251), DATA_B => INT_SUM(252), DATA_C => INT_SUM(253), SAVE => INT_SUM(257), CARRY => INT_CARRY(201) ); ---- End FA stage ---- Begin FA stage FA_203:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_SUM(256), SAVE => INT_SUM(258), CARRY => INT_CARRY(202) ); ---- End FA stage ---- Begin FA stage FA_204:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(182), DATA_B => INT_CARRY(183), DATA_C => INT_CARRY(184), SAVE => INT_SUM(259), CARRY => INT_CARRY(203) ); ---- End FA stage ---- Begin NO stage INT_SUM(260) <= INT_CARRY(185); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(261) <= INT_CARRY(186); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_205:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(257), DATA_B => INT_SUM(258), DATA_C => INT_SUM(259), SAVE => INT_SUM(262), CARRY => INT_CARRY(204) ); ---- End FA stage ---- Begin FA stage FA_206:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(187), SAVE => INT_SUM(263), CARRY => INT_CARRY(205) ); ---- End FA stage ---- Begin FA stage FA_207:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190), SAVE => INT_SUM(264), CARRY => INT_CARRY(206) ); ---- End FA stage ---- Begin FA stage FA_208:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(262), DATA_B => INT_SUM(263), DATA_C => INT_SUM(264), SAVE => INT_SUM(265), CARRY => INT_CARRY(207) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(191), DATA_B => INT_CARRY(192), SAVE => INT_SUM(266), CARRY => INT_CARRY(208) ); ---- End HA stage ---- Begin FA stage FA_209:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(193), SAVE => INT_SUM(267), CARRY => INT_CARRY(209) ); ---- End FA stage ---- Begin NO stage INT_SUM(268) <= INT_CARRY(194); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_210:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(267), DATA_B => INT_SUM(268), DATA_C => INT_CARRY(195), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End FA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_211:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290), SAVE => INT_SUM(269), CARRY => INT_CARRY(210) ); ---- End FA stage ---- Begin FA stage FA_212:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(291), DATA_B => SUMMAND(292), DATA_C => SUMMAND(293), SAVE => INT_SUM(270), CARRY => INT_CARRY(211) ); ---- End FA stage ---- Begin FA stage FA_213:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(294), DATA_B => SUMMAND(295), DATA_C => SUMMAND(296), SAVE => INT_SUM(271), CARRY => INT_CARRY(212) ); ---- End FA stage ---- Begin FA stage FA_214:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(297), DATA_B => SUMMAND(298), DATA_C => SUMMAND(299), SAVE => INT_SUM(272), CARRY => INT_CARRY(213) ); ---- End FA stage ---- Begin FA stage FA_215:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(300), DATA_B => SUMMAND(301), DATA_C => SUMMAND(302), SAVE => INT_SUM(273), CARRY => INT_CARRY(214) ); ---- End FA stage ---- Begin FA stage FA_216:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(303), DATA_B => SUMMAND(304), DATA_C => SUMMAND(305), SAVE => INT_SUM(274), CARRY => INT_CARRY(215) ); ---- End FA stage ---- Begin FA stage FA_217:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(269), DATA_B => INT_SUM(270), DATA_C => INT_SUM(271), SAVE => INT_SUM(275), CARRY => INT_CARRY(216) ); ---- End FA stage ---- Begin FA stage FA_218:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(272), DATA_B => INT_SUM(273), DATA_C => INT_SUM(274), SAVE => INT_SUM(276), CARRY => INT_CARRY(217) ); ---- End FA stage ---- Begin FA stage FA_219:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(196), DATA_B => INT_CARRY(197), DATA_C => INT_CARRY(198), SAVE => INT_SUM(277), CARRY => INT_CARRY(218) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(199), DATA_B => INT_CARRY(200), SAVE => INT_SUM(278), CARRY => INT_CARRY(219) ); ---- End HA stage ---- Begin FA stage FA_220:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(275), DATA_B => INT_SUM(276), DATA_C => INT_SUM(277), SAVE => INT_SUM(279), CARRY => INT_CARRY(220) ); ---- End FA stage ---- Begin FA stage FA_221:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(278), DATA_B => INT_CARRY(201), DATA_C => INT_CARRY(202), SAVE => INT_SUM(280), CARRY => INT_CARRY(221) ); ---- End FA stage ---- Begin NO stage INT_SUM(281) <= INT_CARRY(203); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_222:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(279), DATA_B => INT_SUM(280), DATA_C => INT_SUM(281), SAVE => INT_SUM(282), CARRY => INT_CARRY(222) ); ---- End FA stage ---- Begin FA stage FA_223:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(204), DATA_B => INT_CARRY(205), DATA_C => INT_CARRY(206), SAVE => INT_SUM(283), CARRY => INT_CARRY(223) ); ---- End FA stage ---- Begin FA stage FA_224:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(282), DATA_B => INT_SUM(283), DATA_C => INT_CARRY(207), SAVE => INT_SUM(284), CARRY => INT_CARRY(224) ); ---- End FA stage ---- Begin NO stage INT_SUM(285) <= INT_CARRY(208); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_225:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(284), DATA_B => INT_SUM(285), DATA_C => INT_CARRY(209), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_226:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(306), DATA_B => SUMMAND(307), DATA_C => SUMMAND(308), SAVE => INT_SUM(286), CARRY => INT_CARRY(225) ); ---- End FA stage ---- Begin FA stage FA_227:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311), SAVE => INT_SUM(287), CARRY => INT_CARRY(226) ); ---- End FA stage ---- Begin FA stage FA_228:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), DATA_C => SUMMAND(314), SAVE => INT_SUM(288), CARRY => INT_CARRY(227) ); ---- End FA stage ---- Begin FA stage FA_229:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(315), DATA_B => SUMMAND(316), DATA_C => SUMMAND(317), SAVE => INT_SUM(289), CARRY => INT_CARRY(228) ); ---- End FA stage ---- Begin FA stage FA_230:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320), SAVE => INT_SUM(290), CARRY => INT_CARRY(229) ); ---- End FA stage ---- Begin NO stage INT_SUM(291) <= SUMMAND(321); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(292) <= SUMMAND(322); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_231:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(286), DATA_B => INT_SUM(287), DATA_C => INT_SUM(288), SAVE => INT_SUM(293), CARRY => INT_CARRY(230) ); ---- End FA stage ---- Begin FA stage FA_232:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(289), DATA_B => INT_SUM(290), DATA_C => INT_SUM(291), SAVE => INT_SUM(294), CARRY => INT_CARRY(231) ); ---- End FA stage ---- Begin FA stage FA_233:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(292), DATA_B => INT_CARRY(210), DATA_C => INT_CARRY(211), SAVE => INT_SUM(295), CARRY => INT_CARRY(232) ); ---- End FA stage ---- Begin FA stage FA_234:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(212), DATA_B => INT_CARRY(213), DATA_C => INT_CARRY(214), SAVE => INT_SUM(296), CARRY => INT_CARRY(233) ); ---- End FA stage ---- Begin NO stage INT_SUM(297) <= INT_CARRY(215); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_235:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(293), DATA_B => INT_SUM(294), DATA_C => INT_SUM(295), SAVE => INT_SUM(298), CARRY => INT_CARRY(234) ); ---- End FA stage ---- Begin FA stage FA_236:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(296), DATA_B => INT_SUM(297), DATA_C => INT_CARRY(216), SAVE => INT_SUM(299), CARRY => INT_CARRY(235) ); ---- End FA stage ---- Begin FA stage FA_237:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(217), DATA_B => INT_CARRY(218), DATA_C => INT_CARRY(219), SAVE => INT_SUM(300), CARRY => INT_CARRY(236) ); ---- End FA stage ---- Begin FA stage FA_238:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(298), DATA_B => INT_SUM(299), DATA_C => INT_SUM(300), SAVE => INT_SUM(301), CARRY => INT_CARRY(237) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(220), DATA_B => INT_CARRY(221), SAVE => INT_SUM(302), CARRY => INT_CARRY(238) ); ---- End HA stage ---- Begin FA stage FA_239:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(301), DATA_B => INT_SUM(302), DATA_C => INT_CARRY(222), SAVE => INT_SUM(303), CARRY => INT_CARRY(239) ); ---- End FA stage ---- Begin NO stage INT_SUM(304) <= INT_CARRY(223); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_240:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(303), DATA_B => INT_SUM(304), DATA_C => INT_CARRY(224), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End FA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_241:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(323), DATA_B => SUMMAND(324), DATA_C => SUMMAND(325), SAVE => INT_SUM(305), CARRY => INT_CARRY(240) ); ---- End FA stage ---- Begin FA stage FA_242:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(326), DATA_B => SUMMAND(327), DATA_C => SUMMAND(328), SAVE => INT_SUM(306), CARRY => INT_CARRY(241) ); ---- End FA stage ---- Begin FA stage FA_243:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(329), DATA_B => SUMMAND(330), DATA_C => SUMMAND(331), SAVE => INT_SUM(307), CARRY => INT_CARRY(242) ); ---- End FA stage ---- Begin FA stage FA_244:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(332), DATA_B => SUMMAND(333), DATA_C => SUMMAND(334), SAVE => INT_SUM(308), CARRY => INT_CARRY(243) ); ---- End FA stage ---- Begin FA stage FA_245:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(335), DATA_B => SUMMAND(336), DATA_C => SUMMAND(337), SAVE => INT_SUM(309), CARRY => INT_CARRY(244) ); ---- End FA stage ---- Begin FA stage FA_246:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(338), DATA_B => SUMMAND(339), DATA_C => SUMMAND(340), SAVE => INT_SUM(310), CARRY => INT_CARRY(245) ); ---- End FA stage ---- Begin FA stage FA_247:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(305), DATA_B => INT_SUM(306), DATA_C => INT_SUM(307), SAVE => INT_SUM(311), CARRY => INT_CARRY(246) ); ---- End FA stage ---- Begin FA stage FA_248:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(308), DATA_B => INT_SUM(309), DATA_C => INT_SUM(310), SAVE => INT_SUM(312), CARRY => INT_CARRY(247) ); ---- End FA stage ---- Begin FA stage FA_249:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(225), DATA_B => INT_CARRY(226), DATA_C => INT_CARRY(227), SAVE => INT_SUM(313), CARRY => INT_CARRY(248) ); ---- End FA stage ---- Begin NO stage INT_SUM(314) <= INT_CARRY(228); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(315) <= INT_CARRY(229); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_250:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(311), DATA_B => INT_SUM(312), DATA_C => INT_SUM(313), SAVE => INT_SUM(316), CARRY => INT_CARRY(249) ); ---- End FA stage ---- Begin FA stage FA_251:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(314), DATA_B => INT_SUM(315), DATA_C => INT_CARRY(230), SAVE => INT_SUM(317), CARRY => INT_CARRY(250) ); ---- End FA stage ---- Begin FA stage FA_252:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(231), DATA_B => INT_CARRY(232), DATA_C => INT_CARRY(233), SAVE => INT_SUM(318), CARRY => INT_CARRY(251) ); ---- End FA stage ---- Begin FA stage FA_253:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(316), DATA_B => INT_SUM(317), DATA_C => INT_SUM(318), SAVE => INT_SUM(319), CARRY => INT_CARRY(252) ); ---- End FA stage ---- Begin FA stage FA_254:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(234), DATA_B => INT_CARRY(235), DATA_C => INT_CARRY(236), SAVE => INT_SUM(320), CARRY => INT_CARRY(253) ); ---- End FA stage ---- Begin FA stage FA_255:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(319), DATA_B => INT_SUM(320), DATA_C => INT_CARRY(237), SAVE => INT_SUM(321), CARRY => INT_CARRY(254) ); ---- End FA stage ---- Begin NO stage INT_SUM(322) <= INT_CARRY(238); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_256:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(321), DATA_B => INT_SUM(322), DATA_C => INT_CARRY(239), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_257:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(341), DATA_B => SUMMAND(342), DATA_C => SUMMAND(343), SAVE => INT_SUM(323), CARRY => INT_CARRY(255) ); ---- End FA stage ---- Begin FA stage FA_258:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(344), DATA_B => SUMMAND(345), DATA_C => SUMMAND(346), SAVE => INT_SUM(324), CARRY => INT_CARRY(256) ); ---- End FA stage ---- Begin FA stage FA_259:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(347), DATA_B => SUMMAND(348), DATA_C => SUMMAND(349), SAVE => INT_SUM(325), CARRY => INT_CARRY(257) ); ---- End FA stage ---- Begin FA stage FA_260:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(350), DATA_B => SUMMAND(351), DATA_C => SUMMAND(352), SAVE => INT_SUM(326), CARRY => INT_CARRY(258) ); ---- End FA stage ---- Begin FA stage FA_261:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(353), DATA_B => SUMMAND(354), DATA_C => SUMMAND(355), SAVE => INT_SUM(327), CARRY => INT_CARRY(259) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(356), DATA_B => SUMMAND(357), SAVE => INT_SUM(328), CARRY => INT_CARRY(260) ); ---- End HA stage ---- Begin FA stage FA_262:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(323), DATA_B => INT_SUM(324), DATA_C => INT_SUM(325), SAVE => INT_SUM(329), CARRY => INT_CARRY(261) ); ---- End FA stage ---- Begin FA stage FA_263:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(326), DATA_B => INT_SUM(327), DATA_C => INT_SUM(328), SAVE => INT_SUM(330), CARRY => INT_CARRY(262) ); ---- End FA stage ---- Begin FA stage FA_264:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(240), DATA_B => INT_CARRY(241), DATA_C => INT_CARRY(242), SAVE => INT_SUM(331), CARRY => INT_CARRY(263) ); ---- End FA stage ---- Begin FA stage FA_265:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(243), DATA_B => INT_CARRY(244), DATA_C => INT_CARRY(245), SAVE => INT_SUM(332), CARRY => INT_CARRY(264) ); ---- End FA stage ---- Begin FA stage FA_266:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(329), DATA_B => INT_SUM(330), DATA_C => INT_SUM(331), SAVE => INT_SUM(333), CARRY => INT_CARRY(265) ); ---- End FA stage ---- Begin FA stage FA_267:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(332), DATA_B => INT_CARRY(246), DATA_C => INT_CARRY(247), SAVE => INT_SUM(334), CARRY => INT_CARRY(266) ); ---- End FA stage ---- Begin NO stage INT_SUM(335) <= INT_CARRY(248); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_268:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(333), DATA_B => INT_SUM(334), DATA_C => INT_SUM(335), SAVE => INT_SUM(336), CARRY => INT_CARRY(267) ); ---- End FA stage ---- Begin FA stage FA_269:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(249), DATA_B => INT_CARRY(250), DATA_C => INT_CARRY(251), SAVE => INT_SUM(337), CARRY => INT_CARRY(268) ); ---- End FA stage ---- Begin FA stage FA_270:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(336), DATA_B => INT_SUM(337), DATA_C => INT_CARRY(252), SAVE => INT_SUM(338), CARRY => INT_CARRY(269) ); ---- End FA stage ---- Begin NO stage INT_SUM(339) <= INT_CARRY(253); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_271:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(338), DATA_B => INT_SUM(339), DATA_C => INT_CARRY(254), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End FA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_272:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(358), DATA_B => SUMMAND(359), DATA_C => SUMMAND(360), SAVE => INT_SUM(340), CARRY => INT_CARRY(270) ); ---- End FA stage ---- Begin FA stage FA_273:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(361), DATA_B => SUMMAND(362), DATA_C => SUMMAND(363), SAVE => INT_SUM(341), CARRY => INT_CARRY(271) ); ---- End FA stage ---- Begin FA stage FA_274:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(364), DATA_B => SUMMAND(365), DATA_C => SUMMAND(366), SAVE => INT_SUM(342), CARRY => INT_CARRY(272) ); ---- End FA stage ---- Begin FA stage FA_275:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(367), DATA_B => SUMMAND(368), DATA_C => SUMMAND(369), SAVE => INT_SUM(343), CARRY => INT_CARRY(273) ); ---- End FA stage ---- Begin FA stage FA_276:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(370), DATA_B => SUMMAND(371), DATA_C => SUMMAND(372), SAVE => INT_SUM(344), CARRY => INT_CARRY(274) ); ---- End FA stage ---- Begin NO stage INT_SUM(345) <= SUMMAND(373); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_277:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(340), DATA_B => INT_SUM(341), DATA_C => INT_SUM(342), SAVE => INT_SUM(346), CARRY => INT_CARRY(275) ); ---- End FA stage ---- Begin FA stage FA_278:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(343), DATA_B => INT_SUM(344), DATA_C => INT_SUM(345), SAVE => INT_SUM(347), CARRY => INT_CARRY(276) ); ---- End FA stage ---- Begin FA stage FA_279:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(255), DATA_B => INT_CARRY(256), DATA_C => INT_CARRY(257), SAVE => INT_SUM(348), CARRY => INT_CARRY(277) ); ---- End FA stage ---- Begin FA stage FA_280:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(258), DATA_B => INT_CARRY(259), DATA_C => INT_CARRY(260), SAVE => INT_SUM(349), CARRY => INT_CARRY(278) ); ---- End FA stage ---- Begin FA stage FA_281:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(346), DATA_B => INT_SUM(347), DATA_C => INT_SUM(348), SAVE => INT_SUM(350), CARRY => INT_CARRY(279) ); ---- End FA stage ---- Begin FA stage FA_282:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(349), DATA_B => INT_CARRY(261), DATA_C => INT_CARRY(262), SAVE => INT_SUM(351), CARRY => INT_CARRY(280) ); ---- End FA stage ---- Begin NO stage INT_SUM(352) <= INT_CARRY(263); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(353) <= INT_CARRY(264); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_283:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(350), DATA_B => INT_SUM(351), DATA_C => INT_SUM(352), SAVE => INT_SUM(354), CARRY => INT_CARRY(281) ); ---- End FA stage ---- Begin FA stage FA_284:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(353), DATA_B => INT_CARRY(265), DATA_C => INT_CARRY(266), SAVE => INT_SUM(355), CARRY => INT_CARRY(282) ); ---- End FA stage ---- Begin FA stage FA_285:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(354), DATA_B => INT_SUM(355), DATA_C => INT_CARRY(267), SAVE => INT_SUM(356), CARRY => INT_CARRY(283) ); ---- End FA stage ---- Begin NO stage INT_SUM(357) <= INT_CARRY(268); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_286:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(356), DATA_B => INT_SUM(357), DATA_C => INT_CARRY(269), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_287:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(374), DATA_B => SUMMAND(375), DATA_C => SUMMAND(376), SAVE => INT_SUM(358), CARRY => INT_CARRY(284) ); ---- End FA stage ---- Begin FA stage FA_288:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(377), DATA_B => SUMMAND(378), DATA_C => SUMMAND(379), SAVE => INT_SUM(359), CARRY => INT_CARRY(285) ); ---- End FA stage ---- Begin FA stage FA_289:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(380), DATA_B => SUMMAND(381), DATA_C => SUMMAND(382), SAVE => INT_SUM(360), CARRY => INT_CARRY(286) ); ---- End FA stage ---- Begin FA stage FA_290:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(383), DATA_B => SUMMAND(384), DATA_C => SUMMAND(385), SAVE => INT_SUM(361), CARRY => INT_CARRY(287) ); ---- End FA stage ---- Begin FA stage FA_291:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(386), DATA_B => SUMMAND(387), DATA_C => SUMMAND(388), SAVE => INT_SUM(362), CARRY => INT_CARRY(288) ); ---- End FA stage ---- Begin NO stage INT_SUM(363) <= SUMMAND(389); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_292:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(358), DATA_B => INT_SUM(359), DATA_C => INT_SUM(360), SAVE => INT_SUM(364), CARRY => INT_CARRY(289) ); ---- End FA stage ---- Begin FA stage FA_293:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(361), DATA_B => INT_SUM(362), DATA_C => INT_SUM(363), SAVE => INT_SUM(365), CARRY => INT_CARRY(290) ); ---- End FA stage ---- Begin FA stage FA_294:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(270), DATA_B => INT_CARRY(271), DATA_C => INT_CARRY(272), SAVE => INT_SUM(366), CARRY => INT_CARRY(291) ); ---- End FA stage ---- Begin NO stage INT_SUM(367) <= INT_CARRY(273); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(368) <= INT_CARRY(274); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_295:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(364), DATA_B => INT_SUM(365), DATA_C => INT_SUM(366), SAVE => INT_SUM(369), CARRY => INT_CARRY(292) ); ---- End FA stage ---- Begin FA stage FA_296:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(367), DATA_B => INT_SUM(368), DATA_C => INT_CARRY(275), SAVE => INT_SUM(370), CARRY => INT_CARRY(293) ); ---- End FA stage ---- Begin FA stage FA_297:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(276), DATA_B => INT_CARRY(277), DATA_C => INT_CARRY(278), SAVE => INT_SUM(371), CARRY => INT_CARRY(294) ); ---- End FA stage ---- Begin FA stage FA_298:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(369), DATA_B => INT_SUM(370), DATA_C => INT_SUM(371), SAVE => INT_SUM(372), CARRY => INT_CARRY(295) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(279), DATA_B => INT_CARRY(280), SAVE => INT_SUM(373), CARRY => INT_CARRY(296) ); ---- End HA stage ---- Begin FA stage FA_299:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(372), DATA_B => INT_SUM(373), DATA_C => INT_CARRY(281), SAVE => INT_SUM(374), CARRY => INT_CARRY(297) ); ---- End FA stage ---- Begin NO stage INT_SUM(375) <= INT_CARRY(282); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_300:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(374), DATA_B => INT_SUM(375), DATA_C => INT_CARRY(283), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End FA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_301:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(390), DATA_B => SUMMAND(391), DATA_C => SUMMAND(392), SAVE => INT_SUM(376), CARRY => INT_CARRY(298) ); ---- End FA stage ---- Begin FA stage FA_302:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(393), DATA_B => SUMMAND(394), DATA_C => SUMMAND(395), SAVE => INT_SUM(377), CARRY => INT_CARRY(299) ); ---- End FA stage ---- Begin FA stage FA_303:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(396), DATA_B => SUMMAND(397), DATA_C => SUMMAND(398), SAVE => INT_SUM(378), CARRY => INT_CARRY(300) ); ---- End FA stage ---- Begin FA stage FA_304:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(399), DATA_B => SUMMAND(400), DATA_C => SUMMAND(401), SAVE => INT_SUM(379), CARRY => INT_CARRY(301) ); ---- End FA stage ---- Begin FA stage FA_305:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(402), DATA_B => SUMMAND(403), DATA_C => SUMMAND(404), SAVE => INT_SUM(380), CARRY => INT_CARRY(302) ); ---- End FA stage ---- Begin FA stage FA_306:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(376), DATA_B => INT_SUM(377), DATA_C => INT_SUM(378), SAVE => INT_SUM(381), CARRY => INT_CARRY(303) ); ---- End FA stage ---- Begin FA stage FA_307:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(379), DATA_B => INT_SUM(380), DATA_C => INT_CARRY(284), SAVE => INT_SUM(382), CARRY => INT_CARRY(304) ); ---- End FA stage ---- Begin FA stage FA_308:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(285), DATA_B => INT_CARRY(286), DATA_C => INT_CARRY(287), SAVE => INT_SUM(383), CARRY => INT_CARRY(305) ); ---- End FA stage ---- Begin NO stage INT_SUM(384) <= INT_CARRY(288); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_309:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(381), DATA_B => INT_SUM(382), DATA_C => INT_SUM(383), SAVE => INT_SUM(385), CARRY => INT_CARRY(306) ); ---- End FA stage ---- Begin FA stage FA_310:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(384), DATA_B => INT_CARRY(289), DATA_C => INT_CARRY(290), SAVE => INT_SUM(386), CARRY => INT_CARRY(307) ); ---- End FA stage ---- Begin NO stage INT_SUM(387) <= INT_CARRY(291); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_311:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(385), DATA_B => INT_SUM(386), DATA_C => INT_SUM(387), SAVE => INT_SUM(388), CARRY => INT_CARRY(308) ); ---- End FA stage ---- Begin FA stage FA_312:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(292), DATA_B => INT_CARRY(293), DATA_C => INT_CARRY(294), SAVE => INT_SUM(389), CARRY => INT_CARRY(309) ); ---- End FA stage ---- Begin FA stage FA_313:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(388), DATA_B => INT_SUM(389), DATA_C => INT_CARRY(295), SAVE => INT_SUM(390), CARRY => INT_CARRY(310) ); ---- End FA stage ---- Begin NO stage INT_SUM(391) <= INT_CARRY(296); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_314:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(390), DATA_B => INT_SUM(391), DATA_C => INT_CARRY(297), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_315:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(405), DATA_B => SUMMAND(406), DATA_C => SUMMAND(407), SAVE => INT_SUM(392), CARRY => INT_CARRY(311) ); ---- End FA stage ---- Begin FA stage FA_316:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(408), DATA_B => SUMMAND(409), DATA_C => SUMMAND(410), SAVE => INT_SUM(393), CARRY => INT_CARRY(312) ); ---- End FA stage ---- Begin FA stage FA_317:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(411), DATA_B => SUMMAND(412), DATA_C => SUMMAND(413), SAVE => INT_SUM(394), CARRY => INT_CARRY(313) ); ---- End FA stage ---- Begin FA stage FA_318:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(414), DATA_B => SUMMAND(415), DATA_C => SUMMAND(416), SAVE => INT_SUM(395), CARRY => INT_CARRY(314) ); ---- End FA stage ---- Begin FA stage FA_319:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(417), DATA_B => SUMMAND(418), DATA_C => SUMMAND(419), SAVE => INT_SUM(396), CARRY => INT_CARRY(315) ); ---- End FA stage ---- Begin FA stage FA_320:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(392), DATA_B => INT_SUM(393), DATA_C => INT_SUM(394), SAVE => INT_SUM(397), CARRY => INT_CARRY(316) ); ---- End FA stage ---- Begin FA stage FA_321:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(395), DATA_B => INT_SUM(396), DATA_C => INT_CARRY(298), SAVE => INT_SUM(398), CARRY => INT_CARRY(317) ); ---- End FA stage ---- Begin FA stage FA_322:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(299), DATA_B => INT_CARRY(300), DATA_C => INT_CARRY(301), SAVE => INT_SUM(399), CARRY => INT_CARRY(318) ); ---- End FA stage ---- Begin NO stage INT_SUM(400) <= INT_CARRY(302); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_323:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(397), DATA_B => INT_SUM(398), DATA_C => INT_SUM(399), SAVE => INT_SUM(401), CARRY => INT_CARRY(319) ); ---- End FA stage ---- Begin FA stage FA_324:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(400), DATA_B => INT_CARRY(303), DATA_C => INT_CARRY(304), SAVE => INT_SUM(402), CARRY => INT_CARRY(320) ); ---- End FA stage ---- Begin NO stage INT_SUM(403) <= INT_CARRY(305); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_325:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(401), DATA_B => INT_SUM(402), DATA_C => INT_SUM(403), SAVE => INT_SUM(404), CARRY => INT_CARRY(321) ); ---- End FA stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(306), DATA_B => INT_CARRY(307), SAVE => INT_SUM(405), CARRY => INT_CARRY(322) ); ---- End HA stage ---- Begin FA stage FA_326:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(404), DATA_B => INT_SUM(405), DATA_C => INT_CARRY(308), SAVE => INT_SUM(406), CARRY => INT_CARRY(323) ); ---- End FA stage ---- Begin NO stage INT_SUM(407) <= INT_CARRY(309); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_327:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(406), DATA_B => INT_SUM(407), DATA_C => INT_CARRY(310), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End FA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin FA stage FA_328:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(420), DATA_B => SUMMAND(421), DATA_C => SUMMAND(422), SAVE => INT_SUM(408), CARRY => INT_CARRY(324) ); ---- End FA stage ---- Begin FA stage FA_329:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(423), DATA_B => SUMMAND(424), DATA_C => SUMMAND(425), SAVE => INT_SUM(409), CARRY => INT_CARRY(325) ); ---- End FA stage ---- Begin FA stage FA_330:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(426), DATA_B => SUMMAND(427), DATA_C => SUMMAND(428), SAVE => INT_SUM(410), CARRY => INT_CARRY(326) ); ---- End FA stage ---- Begin FA stage FA_331:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(429), DATA_B => SUMMAND(430), DATA_C => SUMMAND(431), SAVE => INT_SUM(411), CARRY => INT_CARRY(327) ); ---- End FA stage ---- Begin HA stage HA_35:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(432), DATA_B => SUMMAND(433), SAVE => INT_SUM(412), CARRY => INT_CARRY(328) ); ---- End HA stage ---- Begin FA stage FA_332:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(408), DATA_B => INT_SUM(409), DATA_C => INT_SUM(410), SAVE => INT_SUM(413), CARRY => INT_CARRY(329) ); ---- End FA stage ---- Begin FA stage FA_333:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(411), DATA_B => INT_SUM(412), DATA_C => INT_CARRY(311), SAVE => INT_SUM(414), CARRY => INT_CARRY(330) ); ---- End FA stage ---- Begin FA stage FA_334:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(312), DATA_B => INT_CARRY(313), DATA_C => INT_CARRY(314), SAVE => INT_SUM(415), CARRY => INT_CARRY(331) ); ---- End FA stage ---- Begin NO stage INT_SUM(416) <= INT_CARRY(315); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_335:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(413), DATA_B => INT_SUM(414), DATA_C => INT_SUM(415), SAVE => INT_SUM(417), CARRY => INT_CARRY(332) ); ---- End FA stage ---- Begin FA stage FA_336:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(416), DATA_B => INT_CARRY(316), DATA_C => INT_CARRY(317), SAVE => INT_SUM(418), CARRY => INT_CARRY(333) ); ---- End FA stage ---- Begin NO stage INT_SUM(419) <= INT_CARRY(318); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_337:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(417), DATA_B => INT_SUM(418), DATA_C => INT_SUM(419), SAVE => INT_SUM(420), CARRY => INT_CARRY(334) ); ---- End FA stage ---- Begin HA stage HA_36:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(319), DATA_B => INT_CARRY(320), SAVE => INT_SUM(421), CARRY => INT_CARRY(335) ); ---- End HA stage ---- Begin FA stage FA_338:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(420), DATA_B => INT_SUM(421), DATA_C => INT_CARRY(321), SAVE => INT_SUM(422), CARRY => INT_CARRY(336) ); ---- End FA stage ---- Begin NO stage INT_SUM(423) <= INT_CARRY(322); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_339:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(422), DATA_B => INT_SUM(423), DATA_C => INT_CARRY(323), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin FA stage FA_340:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(434), DATA_B => SUMMAND(435), DATA_C => SUMMAND(436), SAVE => INT_SUM(424), CARRY => INT_CARRY(337) ); ---- End FA stage ---- Begin FA stage FA_341:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(437), DATA_B => SUMMAND(438), DATA_C => SUMMAND(439), SAVE => INT_SUM(425), CARRY => INT_CARRY(338) ); ---- End FA stage ---- Begin FA stage FA_342:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(440), DATA_B => SUMMAND(441), DATA_C => SUMMAND(442), SAVE => INT_SUM(426), CARRY => INT_CARRY(339) ); ---- End FA stage ---- Begin FA stage FA_343:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(443), DATA_B => SUMMAND(444), DATA_C => SUMMAND(445), SAVE => INT_SUM(427), CARRY => INT_CARRY(340) ); ---- End FA stage ---- Begin HA stage HA_37:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(446), DATA_B => SUMMAND(447), SAVE => INT_SUM(428), CARRY => INT_CARRY(341) ); ---- End HA stage ---- Begin FA stage FA_344:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(424), DATA_B => INT_SUM(425), DATA_C => INT_SUM(426), SAVE => INT_SUM(429), CARRY => INT_CARRY(342) ); ---- End FA stage ---- Begin FA stage FA_345:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(427), DATA_B => INT_SUM(428), DATA_C => INT_CARRY(324), SAVE => INT_SUM(430), CARRY => INT_CARRY(343) ); ---- End FA stage ---- Begin FA stage FA_346:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(325), DATA_B => INT_CARRY(326), DATA_C => INT_CARRY(327), SAVE => INT_SUM(431), CARRY => INT_CARRY(344) ); ---- End FA stage ---- Begin NO stage INT_SUM(432) <= INT_CARRY(328); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_347:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(429), DATA_B => INT_SUM(430), DATA_C => INT_SUM(431), SAVE => INT_SUM(433), CARRY => INT_CARRY(345) ); ---- End FA stage ---- Begin FA stage FA_348:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(432), DATA_B => INT_CARRY(329), DATA_C => INT_CARRY(330), SAVE => INT_SUM(434), CARRY => INT_CARRY(346) ); ---- End FA stage ---- Begin NO stage INT_SUM(435) <= INT_CARRY(331); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_349:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(433), DATA_B => INT_SUM(434), DATA_C => INT_SUM(435), SAVE => INT_SUM(436), CARRY => INT_CARRY(347) ); ---- End FA stage ---- Begin HA stage HA_38:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(332), DATA_B => INT_CARRY(333), SAVE => INT_SUM(437), CARRY => INT_CARRY(348) ); ---- End HA stage ---- Begin FA stage FA_350:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(436), DATA_B => INT_SUM(437), DATA_C => INT_CARRY(334), SAVE => INT_SUM(438), CARRY => INT_CARRY(349) ); ---- End FA stage ---- Begin NO stage INT_SUM(439) <= INT_CARRY(335); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_351:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(438), DATA_B => INT_SUM(439), DATA_C => INT_CARRY(336), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End FA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin FA stage FA_352:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(448), DATA_B => SUMMAND(449), DATA_C => SUMMAND(450), SAVE => INT_SUM(440), CARRY => INT_CARRY(350) ); ---- End FA stage ---- Begin FA stage FA_353:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(451), DATA_B => SUMMAND(452), DATA_C => SUMMAND(453), SAVE => INT_SUM(441), CARRY => INT_CARRY(351) ); ---- End FA stage ---- Begin FA stage FA_354:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(454), DATA_B => SUMMAND(455), DATA_C => SUMMAND(456), SAVE => INT_SUM(442), CARRY => INT_CARRY(352) ); ---- End FA stage ---- Begin FA stage FA_355:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(457), DATA_B => SUMMAND(458), DATA_C => SUMMAND(459), SAVE => INT_SUM(443), CARRY => INT_CARRY(353) ); ---- End FA stage ---- Begin NO stage INT_SUM(444) <= SUMMAND(460); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_356:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(440), DATA_B => INT_SUM(441), DATA_C => INT_SUM(442), SAVE => INT_SUM(445), CARRY => INT_CARRY(354) ); ---- End FA stage ---- Begin FA stage FA_357:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(443), DATA_B => INT_SUM(444), DATA_C => INT_CARRY(337), SAVE => INT_SUM(446), CARRY => INT_CARRY(355) ); ---- End FA stage ---- Begin FA stage FA_358:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(338), DATA_B => INT_CARRY(339), DATA_C => INT_CARRY(340), SAVE => INT_SUM(447), CARRY => INT_CARRY(356) ); ---- End FA stage ---- Begin NO stage INT_SUM(448) <= INT_CARRY(341); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_359:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(445), DATA_B => INT_SUM(446), DATA_C => INT_SUM(447), SAVE => INT_SUM(449), CARRY => INT_CARRY(357) ); ---- End FA stage ---- Begin FA stage FA_360:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(448), DATA_B => INT_CARRY(342), DATA_C => INT_CARRY(343), SAVE => INT_SUM(450), CARRY => INT_CARRY(358) ); ---- End FA stage ---- Begin NO stage INT_SUM(451) <= INT_CARRY(344); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_361:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(449), DATA_B => INT_SUM(450), DATA_C => INT_SUM(451), SAVE => INT_SUM(452), CARRY => INT_CARRY(359) ); ---- End FA stage ---- Begin HA stage HA_39:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(345), DATA_B => INT_CARRY(346), SAVE => INT_SUM(453), CARRY => INT_CARRY(360) ); ---- End HA stage ---- Begin FA stage FA_362:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(452), DATA_B => INT_SUM(453), DATA_C => INT_CARRY(347), SAVE => INT_SUM(454), CARRY => INT_CARRY(361) ); ---- End FA stage ---- Begin NO stage INT_SUM(455) <= INT_CARRY(348); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_363:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(454), DATA_B => INT_SUM(455), DATA_C => INT_CARRY(349), SAVE => SUM(42), CARRY => CARRY(42) ); ---- End FA stage -- End WT-branch 43 -- Begin WT-branch 44 ---- Begin FA stage FA_364:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(461), DATA_B => SUMMAND(462), DATA_C => SUMMAND(463), SAVE => INT_SUM(456), CARRY => INT_CARRY(362) ); ---- End FA stage ---- Begin FA stage FA_365:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(464), DATA_B => SUMMAND(465), DATA_C => SUMMAND(466), SAVE => INT_SUM(457), CARRY => INT_CARRY(363) ); ---- End FA stage ---- Begin FA stage FA_366:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(467), DATA_B => SUMMAND(468), DATA_C => SUMMAND(469), SAVE => INT_SUM(458), CARRY => INT_CARRY(364) ); ---- End FA stage ---- Begin FA stage FA_367:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(470), DATA_B => SUMMAND(471), DATA_C => SUMMAND(472), SAVE => INT_SUM(459), CARRY => INT_CARRY(365) ); ---- End FA stage ---- Begin FA stage FA_368:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(473), DATA_B => INT_CARRY(350), DATA_C => INT_CARRY(351), SAVE => INT_SUM(460), CARRY => INT_CARRY(366) ); ---- End FA stage ---- Begin NO stage INT_SUM(461) <= INT_CARRY(352); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(462) <= INT_CARRY(353); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_369:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(456), DATA_B => INT_SUM(457), DATA_C => INT_SUM(458), SAVE => INT_SUM(463), CARRY => INT_CARRY(367) ); ---- End FA stage ---- Begin FA stage FA_370:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(459), DATA_B => INT_SUM(460), DATA_C => INT_SUM(461), SAVE => INT_SUM(464), CARRY => INT_CARRY(368) ); ---- End FA stage ---- Begin FA stage FA_371:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(462), DATA_B => INT_CARRY(354), DATA_C => INT_CARRY(355), SAVE => INT_SUM(465), CARRY => INT_CARRY(369) ); ---- End FA stage ---- Begin NO stage INT_SUM(466) <= INT_CARRY(356); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_372:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(463), DATA_B => INT_SUM(464), DATA_C => INT_SUM(465), SAVE => INT_SUM(467), CARRY => INT_CARRY(370) ); ---- End FA stage ---- Begin FA stage FA_373:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(466), DATA_B => INT_CARRY(357), DATA_C => INT_CARRY(358), SAVE => INT_SUM(468), CARRY => INT_CARRY(371) ); ---- End FA stage ---- Begin FA stage FA_374:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(467), DATA_B => INT_SUM(468), DATA_C => INT_CARRY(359), SAVE => INT_SUM(469), CARRY => INT_CARRY(372) ); ---- End FA stage ---- Begin NO stage INT_SUM(470) <= INT_CARRY(360); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_375:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(469), DATA_B => INT_SUM(470), DATA_C => INT_CARRY(361), SAVE => SUM(43), CARRY => CARRY(43) ); ---- End FA stage -- End WT-branch 44 -- Begin WT-branch 45 ---- Begin FA stage FA_376:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(474), DATA_B => SUMMAND(475), DATA_C => SUMMAND(476), SAVE => INT_SUM(471), CARRY => INT_CARRY(373) ); ---- End FA stage ---- Begin FA stage FA_377:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(477), DATA_B => SUMMAND(478), DATA_C => SUMMAND(479), SAVE => INT_SUM(472), CARRY => INT_CARRY(374) ); ---- End FA stage ---- Begin FA stage FA_378:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(480), DATA_B => SUMMAND(481), DATA_C => SUMMAND(482), SAVE => INT_SUM(473), CARRY => INT_CARRY(375) ); ---- End FA stage ---- Begin FA stage FA_379:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(483), DATA_B => SUMMAND(484), DATA_C => SUMMAND(485), SAVE => INT_SUM(474), CARRY => INT_CARRY(376) ); ---- End FA stage ---- Begin FA stage FA_380:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(471), DATA_B => INT_SUM(472), DATA_C => INT_SUM(473), SAVE => INT_SUM(475), CARRY => INT_CARRY(377) ); ---- End FA stage ---- Begin FA stage FA_381:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(474), DATA_B => INT_CARRY(362), DATA_C => INT_CARRY(363), SAVE => INT_SUM(476), CARRY => INT_CARRY(378) ); ---- End FA stage ---- Begin FA stage FA_382:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(364), DATA_B => INT_CARRY(365), DATA_C => INT_CARRY(366), SAVE => INT_SUM(477), CARRY => INT_CARRY(379) ); ---- End FA stage ---- Begin FA stage FA_383:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(475), DATA_B => INT_SUM(476), DATA_C => INT_SUM(477), SAVE => INT_SUM(478), CARRY => INT_CARRY(380) ); ---- End FA stage ---- Begin FA stage FA_384:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(367), DATA_B => INT_CARRY(368), DATA_C => INT_CARRY(369), SAVE => INT_SUM(479), CARRY => INT_CARRY(381) ); ---- End FA stage ---- Begin FA stage FA_385:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(478), DATA_B => INT_SUM(479), DATA_C => INT_CARRY(370), SAVE => INT_SUM(480), CARRY => INT_CARRY(382) ); ---- End FA stage ---- Begin NO stage INT_SUM(481) <= INT_CARRY(371); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_386:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(480), DATA_B => INT_SUM(481), DATA_C => INT_CARRY(372), SAVE => SUM(44), CARRY => CARRY(44) ); ---- End FA stage -- End WT-branch 45 -- Begin WT-branch 46 ---- Begin FA stage FA_387:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(486), DATA_B => SUMMAND(487), DATA_C => SUMMAND(488), SAVE => INT_SUM(482), CARRY => INT_CARRY(383) ); ---- End FA stage ---- Begin FA stage FA_388:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(489), DATA_B => SUMMAND(490), DATA_C => SUMMAND(491), SAVE => INT_SUM(483), CARRY => INT_CARRY(384) ); ---- End FA stage ---- Begin FA stage FA_389:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(492), DATA_B => SUMMAND(493), DATA_C => SUMMAND(494), SAVE => INT_SUM(484), CARRY => INT_CARRY(385) ); ---- End FA stage ---- Begin FA stage FA_390:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(495), DATA_B => SUMMAND(496), DATA_C => SUMMAND(497), SAVE => INT_SUM(485), CARRY => INT_CARRY(386) ); ---- End FA stage ---- Begin FA stage FA_391:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(482), DATA_B => INT_SUM(483), DATA_C => INT_SUM(484), SAVE => INT_SUM(486), CARRY => INT_CARRY(387) ); ---- End FA stage ---- Begin FA stage FA_392:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(485), DATA_B => INT_CARRY(373), DATA_C => INT_CARRY(374), SAVE => INT_SUM(487), CARRY => INT_CARRY(388) ); ---- End FA stage ---- Begin HA stage HA_40:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(375), DATA_B => INT_CARRY(376), SAVE => INT_SUM(488), CARRY => INT_CARRY(389) ); ---- End HA stage ---- Begin FA stage FA_393:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(486), DATA_B => INT_SUM(487), DATA_C => INT_SUM(488), SAVE => INT_SUM(489), CARRY => INT_CARRY(390) ); ---- End FA stage ---- Begin FA stage FA_394:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(377), DATA_B => INT_CARRY(378), DATA_C => INT_CARRY(379), SAVE => INT_SUM(490), CARRY => INT_CARRY(391) ); ---- End FA stage ---- Begin FA stage FA_395:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(489), DATA_B => INT_SUM(490), DATA_C => INT_CARRY(380), SAVE => INT_SUM(491), CARRY => INT_CARRY(392) ); ---- End FA stage ---- Begin NO stage INT_SUM(492) <= INT_CARRY(381); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_396:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(491), DATA_B => INT_SUM(492), DATA_C => INT_CARRY(382), SAVE => SUM(45), CARRY => CARRY(45) ); ---- End FA stage -- End WT-branch 46 -- Begin WT-branch 47 ---- Begin FA stage FA_397:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(498), DATA_B => SUMMAND(499), DATA_C => SUMMAND(500), SAVE => INT_SUM(493), CARRY => INT_CARRY(393) ); ---- End FA stage ---- Begin FA stage FA_398:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(501), DATA_B => SUMMAND(502), DATA_C => SUMMAND(503), SAVE => INT_SUM(494), CARRY => INT_CARRY(394) ); ---- End FA stage ---- Begin FA stage FA_399:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(504), DATA_B => SUMMAND(505), DATA_C => SUMMAND(506), SAVE => INT_SUM(495), CARRY => INT_CARRY(395) ); ---- End FA stage ---- Begin NO stage INT_SUM(496) <= SUMMAND(507); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(497) <= SUMMAND(508); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_400:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(493), DATA_B => INT_SUM(494), DATA_C => INT_SUM(495), SAVE => INT_SUM(498), CARRY => INT_CARRY(396) ); ---- End FA stage ---- Begin FA stage FA_401:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(496), DATA_B => INT_SUM(497), DATA_C => INT_CARRY(383), SAVE => INT_SUM(499), CARRY => INT_CARRY(397) ); ---- End FA stage ---- Begin FA stage FA_402:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(384), DATA_B => INT_CARRY(385), DATA_C => INT_CARRY(386), SAVE => INT_SUM(500), CARRY => INT_CARRY(398) ); ---- End FA stage ---- Begin FA stage FA_403:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(498), DATA_B => INT_SUM(499), DATA_C => INT_SUM(500), SAVE => INT_SUM(501), CARRY => INT_CARRY(399) ); ---- End FA stage ---- Begin FA stage FA_404:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(387), DATA_B => INT_CARRY(388), DATA_C => INT_CARRY(389), SAVE => INT_SUM(502), CARRY => INT_CARRY(400) ); ---- End FA stage ---- Begin FA stage FA_405:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(501), DATA_B => INT_SUM(502), DATA_C => INT_CARRY(390), SAVE => INT_SUM(503), CARRY => INT_CARRY(401) ); ---- End FA stage ---- Begin NO stage INT_SUM(504) <= INT_CARRY(391); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_406:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(503), DATA_B => INT_SUM(504), DATA_C => INT_CARRY(392), SAVE => SUM(46), CARRY => CARRY(46) ); ---- End FA stage -- End WT-branch 47 -- Begin WT-branch 48 ---- Begin FA stage FA_407:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(509), DATA_B => SUMMAND(510), DATA_C => SUMMAND(511), SAVE => INT_SUM(505), CARRY => INT_CARRY(402) ); ---- End FA stage ---- Begin FA stage FA_408:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(512), DATA_B => SUMMAND(513), DATA_C => SUMMAND(514), SAVE => INT_SUM(506), CARRY => INT_CARRY(403) ); ---- End FA stage ---- Begin FA stage FA_409:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(515), DATA_B => SUMMAND(516), DATA_C => SUMMAND(517), SAVE => INT_SUM(507), CARRY => INT_CARRY(404) ); ---- End FA stage ---- Begin HA stage HA_41:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(518), DATA_B => SUMMAND(519), SAVE => INT_SUM(508), CARRY => INT_CARRY(405) ); ---- End HA stage ---- Begin FA stage FA_410:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(505), DATA_B => INT_SUM(506), DATA_C => INT_SUM(507), SAVE => INT_SUM(509), CARRY => INT_CARRY(406) ); ---- End FA stage ---- Begin FA stage FA_411:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(508), DATA_B => INT_CARRY(393), DATA_C => INT_CARRY(394), SAVE => INT_SUM(510), CARRY => INT_CARRY(407) ); ---- End FA stage ---- Begin NO stage INT_SUM(511) <= INT_CARRY(395); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_412:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(509), DATA_B => INT_SUM(510), DATA_C => INT_SUM(511), SAVE => INT_SUM(512), CARRY => INT_CARRY(408) ); ---- End FA stage ---- Begin FA stage FA_413:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(396), DATA_B => INT_CARRY(397), DATA_C => INT_CARRY(398), SAVE => INT_SUM(513), CARRY => INT_CARRY(409) ); ---- End FA stage ---- Begin FA stage FA_414:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(512), DATA_B => INT_SUM(513), DATA_C => INT_CARRY(399), SAVE => INT_SUM(514), CARRY => INT_CARRY(410) ); ---- End FA stage ---- Begin NO stage INT_SUM(515) <= INT_CARRY(400); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_415:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(514), DATA_B => INT_SUM(515), DATA_C => INT_CARRY(401), SAVE => SUM(47), CARRY => CARRY(47) ); ---- End FA stage -- End WT-branch 48 -- Begin WT-branch 49 ---- Begin FA stage FA_416:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(520), DATA_B => SUMMAND(521), DATA_C => SUMMAND(522), SAVE => INT_SUM(516), CARRY => INT_CARRY(411) ); ---- End FA stage ---- Begin FA stage FA_417:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(523), DATA_B => SUMMAND(524), DATA_C => SUMMAND(525), SAVE => INT_SUM(517), CARRY => INT_CARRY(412) ); ---- End FA stage ---- Begin FA stage FA_418:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(526), DATA_B => SUMMAND(527), DATA_C => SUMMAND(528), SAVE => INT_SUM(518), CARRY => INT_CARRY(413) ); ---- End FA stage ---- Begin NO stage INT_SUM(519) <= SUMMAND(529); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_419:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(516), DATA_B => INT_SUM(517), DATA_C => INT_SUM(518), SAVE => INT_SUM(520), CARRY => INT_CARRY(414) ); ---- End FA stage ---- Begin FA stage FA_420:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(519), DATA_B => INT_CARRY(402), DATA_C => INT_CARRY(403), SAVE => INT_SUM(521), CARRY => INT_CARRY(415) ); ---- End FA stage ---- Begin NO stage INT_SUM(522) <= INT_CARRY(404); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(523) <= INT_CARRY(405); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_421:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(520), DATA_B => INT_SUM(521), DATA_C => INT_SUM(522), SAVE => INT_SUM(524), CARRY => INT_CARRY(416) ); ---- End FA stage ---- Begin FA stage FA_422:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(523), DATA_B => INT_CARRY(406), DATA_C => INT_CARRY(407), SAVE => INT_SUM(525), CARRY => INT_CARRY(417) ); ---- End FA stage ---- Begin FA stage FA_423:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(524), DATA_B => INT_SUM(525), DATA_C => INT_CARRY(408), SAVE => INT_SUM(526), CARRY => INT_CARRY(418) ); ---- End FA stage ---- Begin NO stage INT_SUM(527) <= INT_CARRY(409); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_424:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(526), DATA_B => INT_SUM(527), DATA_C => INT_CARRY(410), SAVE => SUM(48), CARRY => CARRY(48) ); ---- End FA stage -- End WT-branch 49 -- Begin WT-branch 50 ---- Begin FA stage FA_425:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(530), DATA_B => SUMMAND(531), DATA_C => SUMMAND(532), SAVE => INT_SUM(528), CARRY => INT_CARRY(419) ); ---- End FA stage ---- Begin FA stage FA_426:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(533), DATA_B => SUMMAND(534), DATA_C => SUMMAND(535), SAVE => INT_SUM(529), CARRY => INT_CARRY(420) ); ---- End FA stage ---- Begin FA stage FA_427:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(536), DATA_B => SUMMAND(537), DATA_C => SUMMAND(538), SAVE => INT_SUM(530), CARRY => INT_CARRY(421) ); ---- End FA stage ---- Begin NO stage INT_SUM(531) <= SUMMAND(539); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_428:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(528), DATA_B => INT_SUM(529), DATA_C => INT_SUM(530), SAVE => INT_SUM(532), CARRY => INT_CARRY(422) ); ---- End FA stage ---- Begin FA stage FA_429:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(531), DATA_B => INT_CARRY(411), DATA_C => INT_CARRY(412), SAVE => INT_SUM(533), CARRY => INT_CARRY(423) ); ---- End FA stage ---- Begin NO stage INT_SUM(534) <= INT_CARRY(413); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_430:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(532), DATA_B => INT_SUM(533), DATA_C => INT_SUM(534), SAVE => INT_SUM(535), CARRY => INT_CARRY(424) ); ---- End FA stage ---- Begin HA stage HA_42:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(414), DATA_B => INT_CARRY(415), SAVE => INT_SUM(536), CARRY => INT_CARRY(425) ); ---- End HA stage ---- Begin FA stage FA_431:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(535), DATA_B => INT_SUM(536), DATA_C => INT_CARRY(416), SAVE => INT_SUM(537), CARRY => INT_CARRY(426) ); ---- End FA stage ---- Begin NO stage INT_SUM(538) <= INT_CARRY(417); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_432:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(537), DATA_B => INT_SUM(538), DATA_C => INT_CARRY(418), SAVE => SUM(49), CARRY => CARRY(49) ); ---- End FA stage -- End WT-branch 50 -- Begin WT-branch 51 ---- Begin FA stage FA_433:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(540), DATA_B => SUMMAND(541), DATA_C => SUMMAND(542), SAVE => INT_SUM(539), CARRY => INT_CARRY(427) ); ---- End FA stage ---- Begin FA stage FA_434:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(543), DATA_B => SUMMAND(544), DATA_C => SUMMAND(545), SAVE => INT_SUM(540), CARRY => INT_CARRY(428) ); ---- End FA stage ---- Begin FA stage FA_435:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(546), DATA_B => SUMMAND(547), DATA_C => SUMMAND(548), SAVE => INT_SUM(541), CARRY => INT_CARRY(429) ); ---- End FA stage ---- Begin FA stage FA_436:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(539), DATA_B => INT_SUM(540), DATA_C => INT_SUM(541), SAVE => INT_SUM(542), CARRY => INT_CARRY(430) ); ---- End FA stage ---- Begin FA stage FA_437:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(419), DATA_B => INT_CARRY(420), DATA_C => INT_CARRY(421), SAVE => INT_SUM(543), CARRY => INT_CARRY(431) ); ---- End FA stage ---- Begin FA stage FA_438:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(542), DATA_B => INT_SUM(543), DATA_C => INT_CARRY(422), SAVE => INT_SUM(544), CARRY => INT_CARRY(432) ); ---- End FA stage ---- Begin NO stage INT_SUM(545) <= INT_CARRY(423); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_439:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(544), DATA_B => INT_SUM(545), DATA_C => INT_CARRY(424), SAVE => INT_SUM(546), CARRY => INT_CARRY(433) ); ---- End FA stage ---- Begin NO stage INT_SUM(547) <= INT_CARRY(425); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_440:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(546), DATA_B => INT_SUM(547), DATA_C => INT_CARRY(426), SAVE => SUM(50), CARRY => CARRY(50) ); ---- End FA stage -- End WT-branch 51 -- Begin WT-branch 52 ---- Begin FA stage FA_441:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(549), DATA_B => SUMMAND(550), DATA_C => SUMMAND(551), SAVE => INT_SUM(548), CARRY => INT_CARRY(434) ); ---- End FA stage ---- Begin FA stage FA_442:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(552), DATA_B => SUMMAND(553), DATA_C => SUMMAND(554), SAVE => INT_SUM(549), CARRY => INT_CARRY(435) ); ---- End FA stage ---- Begin FA stage FA_443:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(555), DATA_B => SUMMAND(556), DATA_C => SUMMAND(557), SAVE => INT_SUM(550), CARRY => INT_CARRY(436) ); ---- End FA stage ---- Begin FA stage FA_444:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(548), DATA_B => INT_SUM(549), DATA_C => INT_SUM(550), SAVE => INT_SUM(551), CARRY => INT_CARRY(437) ); ---- End FA stage ---- Begin FA stage FA_445:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(427), DATA_B => INT_CARRY(428), DATA_C => INT_CARRY(429), SAVE => INT_SUM(552), CARRY => INT_CARRY(438) ); ---- End FA stage ---- Begin FA stage FA_446:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(551), DATA_B => INT_SUM(552), DATA_C => INT_CARRY(430), SAVE => INT_SUM(553), CARRY => INT_CARRY(439) ); ---- End FA stage ---- Begin NO stage INT_SUM(554) <= INT_CARRY(431); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_447:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(553), DATA_B => INT_SUM(554), DATA_C => INT_CARRY(432), SAVE => INT_SUM(555), CARRY => INT_CARRY(440) ); ---- End FA stage ---- Begin HA stage HA_43:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(555), DATA_B => INT_CARRY(433), SAVE => SUM(51), CARRY => CARRY(51) ); ---- End HA stage -- End WT-branch 52 -- Begin WT-branch 53 ---- Begin FA stage FA_448:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(558), DATA_B => SUMMAND(559), DATA_C => SUMMAND(560), SAVE => INT_SUM(556), CARRY => INT_CARRY(441) ); ---- End FA stage ---- Begin FA stage FA_449:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(561), DATA_B => SUMMAND(562), DATA_C => SUMMAND(563), SAVE => INT_SUM(557), CARRY => INT_CARRY(442) ); ---- End FA stage ---- Begin FA stage FA_450:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(564), DATA_B => SUMMAND(565), DATA_C => INT_CARRY(434), SAVE => INT_SUM(558), CARRY => INT_CARRY(443) ); ---- End FA stage ---- Begin HA stage HA_44:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(435), DATA_B => INT_CARRY(436), SAVE => INT_SUM(559), CARRY => INT_CARRY(444) ); ---- End HA stage ---- Begin FA stage FA_451:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(556), DATA_B => INT_SUM(557), DATA_C => INT_SUM(558), SAVE => INT_SUM(560), CARRY => INT_CARRY(445) ); ---- End FA stage ---- Begin FA stage FA_452:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(559), DATA_B => INT_CARRY(437), DATA_C => INT_CARRY(438), SAVE => INT_SUM(561), CARRY => INT_CARRY(446) ); ---- End FA stage ---- Begin FA stage FA_453:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(560), DATA_B => INT_SUM(561), DATA_C => INT_CARRY(439), SAVE => INT_SUM(562), CARRY => INT_CARRY(447) ); ---- End FA stage ---- Begin HA stage HA_45:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(562), DATA_B => INT_CARRY(440), SAVE => SUM(52), CARRY => CARRY(52) ); ---- End HA stage -- End WT-branch 53 -- Begin WT-branch 54 ---- Begin FA stage FA_454:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(566), DATA_B => SUMMAND(567), DATA_C => SUMMAND(568), SAVE => INT_SUM(563), CARRY => INT_CARRY(448) ); ---- End FA stage ---- Begin FA stage FA_455:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(569), DATA_B => SUMMAND(570), DATA_C => SUMMAND(571), SAVE => INT_SUM(564), CARRY => INT_CARRY(449) ); ---- End FA stage ---- Begin NO stage INT_SUM(565) <= SUMMAND(572); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(566) <= SUMMAND(573); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_456:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(563), DATA_B => INT_SUM(564), DATA_C => INT_SUM(565), SAVE => INT_SUM(567), CARRY => INT_CARRY(450) ); ---- End FA stage ---- Begin NO stage INT_SUM(568) <= INT_SUM(566); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_457:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(567), DATA_B => INT_SUM(568), DATA_C => INT_CARRY(441), SAVE => INT_SUM(569), CARRY => INT_CARRY(451) ); ---- End FA stage ---- Begin FA stage FA_458:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(442), DATA_B => INT_CARRY(443), DATA_C => INT_CARRY(444), SAVE => INT_SUM(570), CARRY => INT_CARRY(452) ); ---- End FA stage ---- Begin FA stage FA_459:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(569), DATA_B => INT_SUM(570), DATA_C => INT_CARRY(445), SAVE => INT_SUM(571), CARRY => INT_CARRY(453) ); ---- End FA stage ---- Begin NO stage INT_SUM(572) <= INT_CARRY(446); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_460:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(571), DATA_B => INT_SUM(572), DATA_C => INT_CARRY(447), SAVE => SUM(53), CARRY => CARRY(53) ); ---- End FA stage -- End WT-branch 54 -- Begin WT-branch 55 ---- Begin FA stage FA_461:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(574), DATA_B => SUMMAND(575), DATA_C => SUMMAND(576), SAVE => INT_SUM(573), CARRY => INT_CARRY(454) ); ---- End FA stage ---- Begin FA stage FA_462:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(577), DATA_B => SUMMAND(578), DATA_C => SUMMAND(579), SAVE => INT_SUM(574), CARRY => INT_CARRY(455) ); ---- End FA stage ---- Begin FA stage FA_463:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(580), DATA_B => INT_CARRY(448), DATA_C => INT_CARRY(449), SAVE => INT_SUM(575), CARRY => INT_CARRY(456) ); ---- End FA stage ---- Begin FA stage FA_464:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(573), DATA_B => INT_SUM(574), DATA_C => INT_SUM(575), SAVE => INT_SUM(576), CARRY => INT_CARRY(457) ); ---- End FA stage ---- Begin NO stage INT_SUM(577) <= INT_CARRY(450); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_465:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(576), DATA_B => INT_SUM(577), DATA_C => INT_CARRY(451), SAVE => INT_SUM(578), CARRY => INT_CARRY(458) ); ---- End FA stage ---- Begin NO stage INT_SUM(579) <= INT_CARRY(452); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_466:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(578), DATA_B => INT_SUM(579), DATA_C => INT_CARRY(453), SAVE => SUM(54), CARRY => CARRY(54) ); ---- End FA stage -- End WT-branch 55 -- Begin WT-branch 56 ---- Begin FA stage FA_467:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(581), DATA_B => SUMMAND(582), DATA_C => SUMMAND(583), SAVE => INT_SUM(580), CARRY => INT_CARRY(459) ); ---- End FA stage ---- Begin FA stage FA_468:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(584), DATA_B => SUMMAND(585), DATA_C => SUMMAND(586), SAVE => INT_SUM(581), CARRY => INT_CARRY(460) ); ---- End FA stage ---- Begin NO stage INT_SUM(582) <= SUMMAND(587); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_469:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(580), DATA_B => INT_SUM(581), DATA_C => INT_SUM(582), SAVE => INT_SUM(583), CARRY => INT_CARRY(461) ); ---- End FA stage ---- Begin FA stage FA_470:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(454), DATA_B => INT_CARRY(455), DATA_C => INT_CARRY(456), SAVE => INT_SUM(584), CARRY => INT_CARRY(462) ); ---- End FA stage ---- Begin FA stage FA_471:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(583), DATA_B => INT_SUM(584), DATA_C => INT_CARRY(457), SAVE => INT_SUM(585), CARRY => INT_CARRY(463) ); ---- End FA stage ---- Begin HA stage HA_46:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(585), DATA_B => INT_CARRY(458), SAVE => SUM(55), CARRY => CARRY(55) ); ---- End HA stage -- End WT-branch 56 -- Begin WT-branch 57 ---- Begin FA stage FA_472:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(588), DATA_B => SUMMAND(589), DATA_C => SUMMAND(590), SAVE => INT_SUM(586), CARRY => INT_CARRY(464) ); ---- End FA stage ---- Begin FA stage FA_473:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(591), DATA_B => SUMMAND(592), DATA_C => SUMMAND(593), SAVE => INT_SUM(587), CARRY => INT_CARRY(465) ); ---- End FA stage ---- Begin FA stage FA_474:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(586), DATA_B => INT_SUM(587), DATA_C => INT_CARRY(459), SAVE => INT_SUM(588), CARRY => INT_CARRY(466) ); ---- End FA stage ---- Begin NO stage INT_SUM(589) <= INT_CARRY(460); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_475:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(588), DATA_B => INT_SUM(589), DATA_C => INT_CARRY(461), SAVE => INT_SUM(590), CARRY => INT_CARRY(467) ); ---- End FA stage ---- Begin NO stage INT_SUM(591) <= INT_CARRY(462); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_476:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(590), DATA_B => INT_SUM(591), DATA_C => INT_CARRY(463), SAVE => SUM(56), CARRY => CARRY(56) ); ---- End FA stage -- End WT-branch 57 -- Begin WT-branch 58 ---- Begin FA stage FA_477:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(594), DATA_B => SUMMAND(595), DATA_C => SUMMAND(596), SAVE => INT_SUM(592), CARRY => INT_CARRY(468) ); ---- End FA stage ---- Begin FA stage FA_478:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(597), DATA_B => SUMMAND(598), DATA_C => SUMMAND(599), SAVE => INT_SUM(593), CARRY => INT_CARRY(469) ); ---- End FA stage ---- Begin FA stage FA_479:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(592), DATA_B => INT_SUM(593), DATA_C => INT_CARRY(464), SAVE => INT_SUM(594), CARRY => INT_CARRY(470) ); ---- End FA stage ---- Begin NO stage INT_SUM(595) <= INT_CARRY(465); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_480:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(594), DATA_B => INT_SUM(595), DATA_C => INT_CARRY(466), SAVE => INT_SUM(596), CARRY => INT_CARRY(471) ); ---- End FA stage ---- Begin HA stage HA_47:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(596), DATA_B => INT_CARRY(467), SAVE => SUM(57), CARRY => CARRY(57) ); ---- End HA stage -- End WT-branch 58 -- Begin WT-branch 59 ---- Begin FA stage FA_481:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(600), DATA_B => SUMMAND(601), DATA_C => SUMMAND(602), SAVE => INT_SUM(597), CARRY => INT_CARRY(472) ); ---- End FA stage ---- Begin HA stage HA_48:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(603), DATA_B => SUMMAND(604), SAVE => INT_SUM(598), CARRY => INT_CARRY(473) ); ---- End HA stage ---- Begin FA stage FA_482:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(597), DATA_B => INT_SUM(598), DATA_C => INT_CARRY(468), SAVE => INT_SUM(599), CARRY => INT_CARRY(474) ); ---- End FA stage ---- Begin NO stage INT_SUM(600) <= INT_CARRY(469); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_483:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(599), DATA_B => INT_SUM(600), DATA_C => INT_CARRY(470), SAVE => INT_SUM(601), CARRY => INT_CARRY(475) ); ---- End FA stage ---- Begin HA stage HA_49:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(601), DATA_B => INT_CARRY(471), SAVE => SUM(58), CARRY => CARRY(58) ); ---- End HA stage -- End WT-branch 59 -- Begin WT-branch 60 ---- Begin FA stage FA_484:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(605), DATA_B => SUMMAND(606), DATA_C => SUMMAND(607), SAVE => INT_SUM(602), CARRY => INT_CARRY(476) ); ---- End FA stage ---- Begin HA stage HA_50:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(608), DATA_B => SUMMAND(609), SAVE => INT_SUM(603), CARRY => INT_CARRY(477) ); ---- End HA stage ---- Begin FA stage FA_485:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(602), DATA_B => INT_SUM(603), DATA_C => INT_CARRY(472), SAVE => INT_SUM(604), CARRY => INT_CARRY(478) ); ---- End FA stage ---- Begin NO stage INT_SUM(605) <= INT_CARRY(473); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_486:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(604), DATA_B => INT_SUM(605), DATA_C => INT_CARRY(474), SAVE => INT_SUM(606), CARRY => INT_CARRY(479) ); ---- End FA stage ---- Begin HA stage HA_51:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(606), DATA_B => INT_CARRY(475), SAVE => SUM(59), CARRY => CARRY(59) ); ---- End HA stage -- End WT-branch 60 -- Begin WT-branch 61 ---- Begin FA stage FA_487:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(610), DATA_B => SUMMAND(611), DATA_C => SUMMAND(612), SAVE => INT_SUM(607), CARRY => INT_CARRY(480) ); ---- End FA stage ---- Begin FA stage FA_488:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(613), DATA_B => INT_CARRY(476), DATA_C => INT_CARRY(477), SAVE => INT_SUM(608), CARRY => INT_CARRY(481) ); ---- End FA stage ---- Begin FA stage FA_489:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(607), DATA_B => INT_SUM(608), DATA_C => INT_CARRY(478), SAVE => INT_SUM(609), CARRY => INT_CARRY(482) ); ---- End FA stage ---- Begin HA stage HA_52:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(609), DATA_B => INT_CARRY(479), SAVE => SUM(60), CARRY => CARRY(60) ); ---- End HA stage -- End WT-branch 61 -- Begin WT-branch 62 ---- Begin FA stage FA_490:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(614), DATA_B => SUMMAND(615), DATA_C => SUMMAND(616), SAVE => INT_SUM(610), CARRY => INT_CARRY(483) ); ---- End FA stage ---- Begin NO stage INT_SUM(611) <= SUMMAND(617); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_491:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(610), DATA_B => INT_SUM(611), DATA_C => INT_CARRY(480), SAVE => INT_SUM(612), CARRY => INT_CARRY(484) ); ---- End FA stage ---- Begin NO stage INT_SUM(613) <= INT_CARRY(481); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_492:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(612), DATA_B => INT_SUM(613), DATA_C => INT_CARRY(482), SAVE => SUM(61), CARRY => CARRY(61) ); ---- End FA stage -- End WT-branch 62 -- Begin WT-branch 63 ---- Begin FA stage FA_493:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(618), DATA_B => SUMMAND(619), DATA_C => SUMMAND(620), SAVE => INT_SUM(614), CARRY => INT_CARRY(485) ); ---- End FA stage ---- Begin NO stage INT_SUM(615) <= INT_SUM(614); -- At Level 5 ---- End NO stage ---- Begin NO stage INT_SUM(616) <= INT_CARRY(483); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_494:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(615), DATA_B => INT_SUM(616), DATA_C => INT_CARRY(484), SAVE => SUM(62), CARRY => CARRY(62) ); ---- End FA stage -- End WT-branch 63 -- Begin WT-branch 64 ---- Begin FA stage FA_495:FULL_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(621), DATA_B => SUMMAND(622), DATA_C => SUMMAND(623), SAVE => INT_SUM(617), CARRY => INT_CARRY(486) ); ---- End FA stage ---- Begin NO stage INT_SUM(618) <= INT_CARRY(485); -- At Level 5 ---- End NO stage ---- Begin HA stage HA_53:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(617), DATA_B => INT_SUM(618), SAVE => SUM(63), CARRY => CARRY(63) ); ---- End HA stage -- End WT-branch 64 -- Begin WT-branch 65 ---- Begin NO stage INT_SUM(619) <= SUMMAND(624); -- At Level 5 ---- End NO stage ---- Begin NO stage INT_SUM(620) <= SUMMAND(625); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_496:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(619), DATA_B => INT_SUM(620), DATA_C => INT_CARRY(486), SAVE => SUM(64), CARRY => CARRY(64) ); ---- End FA stage -- End WT-branch 65 -- Begin WT-branch 66 ---- Begin HA stage HA_54:HALF_ADDER -- At Level 6 port map ( DATA_A => SUMMAND(626), DATA_B => SUMMAND(627), SAVE => SUM(65), CARRY => CARRY(65) ); ---- End HA stage -- End WT-branch 66 -- Begin WT-branch 67 ---- Begin NO stage SUM(66) <= SUMMAND(628); -- At Level 6 ---- End NO stage -- End WT-branch 67 end WALLACE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_34 is generic (mulpipe : integer := 0); port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 33); PHI: in std_logic; holdn: in std_logic; RESULT: out std_logic_vector(0 to 127) ); end MULTIPLIER_34_34; architecture MULTIPLIER of MULTIPLIER_34_34 is signal PPBIT:std_logic_vector(0 to 628); signal INT_CARRY: std_logic_vector(0 to 128); signal INT_SUM: std_logic_vector(0 to 127); signal LOGIC_ZERO: std_logic; signal INT_CARRYR: std_logic_vector(0 to 128); signal INT_SUMR: std_logic_vector(0 to 127); begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_34 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 33) => MULTIPLIER(0 to 33), SUMMAND(0 to 628) => PPBIT(0 to 628) ); W:WALLACE_34_34 port map ( SUMMAND(0 to 628) => PPBIT(0 to 628), CARRY(0 to 65) => INT_CARRY(1 to 66), SUM(0 to 66) => INT_SUM(0 to 66) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(67) <= LOGIC_ZERO; INT_CARRY(68) <= LOGIC_ZERO; INT_CARRY(69) <= LOGIC_ZERO; INT_CARRY(70) <= LOGIC_ZERO; INT_CARRY(71) <= LOGIC_ZERO; INT_CARRY(72) <= LOGIC_ZERO; INT_CARRY(73) <= LOGIC_ZERO; INT_CARRY(74) <= LOGIC_ZERO; INT_CARRY(75) <= LOGIC_ZERO; INT_CARRY(76) <= LOGIC_ZERO; INT_CARRY(77) <= LOGIC_ZERO; INT_CARRY(78) <= LOGIC_ZERO; INT_CARRY(79) <= LOGIC_ZERO; INT_CARRY(80) <= LOGIC_ZERO; INT_CARRY(81) <= LOGIC_ZERO; INT_CARRY(82) <= LOGIC_ZERO; INT_CARRY(83) <= LOGIC_ZERO; INT_CARRY(84) <= LOGIC_ZERO; INT_CARRY(85) <= LOGIC_ZERO; INT_CARRY(86) <= LOGIC_ZERO; INT_CARRY(87) <= LOGIC_ZERO; INT_CARRY(88) <= LOGIC_ZERO; INT_CARRY(89) <= LOGIC_ZERO; INT_CARRY(90) <= LOGIC_ZERO; INT_CARRY(91) <= LOGIC_ZERO; INT_CARRY(92) <= LOGIC_ZERO; INT_CARRY(93) <= LOGIC_ZERO; INT_CARRY(94) <= LOGIC_ZERO; INT_CARRY(95) <= LOGIC_ZERO; INT_CARRY(96) <= LOGIC_ZERO; INT_CARRY(97) <= LOGIC_ZERO; INT_CARRY(98) <= LOGIC_ZERO; INT_CARRY(99) <= LOGIC_ZERO; INT_CARRY(100) <= LOGIC_ZERO; INT_CARRY(101) <= LOGIC_ZERO; INT_CARRY(102) <= LOGIC_ZERO; INT_CARRY(103) <= LOGIC_ZERO; INT_CARRY(104) <= LOGIC_ZERO; INT_CARRY(105) <= LOGIC_ZERO; INT_CARRY(106) <= LOGIC_ZERO; INT_CARRY(107) <= LOGIC_ZERO; INT_CARRY(108) <= LOGIC_ZERO; INT_CARRY(109) <= LOGIC_ZERO; INT_CARRY(110) <= LOGIC_ZERO; INT_CARRY(111) <= LOGIC_ZERO; INT_CARRY(112) <= LOGIC_ZERO; INT_CARRY(113) <= LOGIC_ZERO; INT_CARRY(114) <= LOGIC_ZERO; INT_CARRY(115) <= LOGIC_ZERO; INT_CARRY(116) <= LOGIC_ZERO; INT_CARRY(117) <= LOGIC_ZERO; INT_CARRY(118) <= LOGIC_ZERO; INT_CARRY(119) <= LOGIC_ZERO; INT_CARRY(120) <= LOGIC_ZERO; INT_CARRY(121) <= LOGIC_ZERO; INT_CARRY(122) <= LOGIC_ZERO; INT_CARRY(123) <= LOGIC_ZERO; INT_CARRY(124) <= LOGIC_ZERO; INT_CARRY(125) <= LOGIC_ZERO; INT_CARRY(126) <= LOGIC_ZERO; INT_CARRY(127) <= LOGIC_ZERO; INT_SUM(67) <= LOGIC_ZERO; INT_SUM(68) <= LOGIC_ZERO; INT_SUM(69) <= LOGIC_ZERO; INT_SUM(70) <= LOGIC_ZERO; INT_SUM(71) <= LOGIC_ZERO; INT_SUM(72) <= LOGIC_ZERO; INT_SUM(73) <= LOGIC_ZERO; INT_SUM(74) <= LOGIC_ZERO; INT_SUM(75) <= LOGIC_ZERO; INT_SUM(76) <= LOGIC_ZERO; INT_SUM(77) <= LOGIC_ZERO; INT_SUM(78) <= LOGIC_ZERO; INT_SUM(79) <= LOGIC_ZERO; INT_SUM(80) <= LOGIC_ZERO; INT_SUM(81) <= LOGIC_ZERO; INT_SUM(82) <= LOGIC_ZERO; INT_SUM(83) <= LOGIC_ZERO; INT_SUM(84) <= LOGIC_ZERO; INT_SUM(85) <= LOGIC_ZERO; INT_SUM(86) <= LOGIC_ZERO; INT_SUM(87) <= LOGIC_ZERO; INT_SUM(88) <= LOGIC_ZERO; INT_SUM(89) <= LOGIC_ZERO; INT_SUM(90) <= LOGIC_ZERO; INT_SUM(91) <= LOGIC_ZERO; INT_SUM(92) <= LOGIC_ZERO; INT_SUM(93) <= LOGIC_ZERO; INT_SUM(94) <= LOGIC_ZERO; INT_SUM(95) <= LOGIC_ZERO; INT_SUM(96) <= LOGIC_ZERO; INT_SUM(97) <= LOGIC_ZERO; INT_SUM(98) <= LOGIC_ZERO; INT_SUM(99) <= LOGIC_ZERO; INT_SUM(100) <= LOGIC_ZERO; INT_SUM(101) <= LOGIC_ZERO; INT_SUM(102) <= LOGIC_ZERO; INT_SUM(103) <= LOGIC_ZERO; INT_SUM(104) <= LOGIC_ZERO; INT_SUM(105) <= LOGIC_ZERO; INT_SUM(106) <= LOGIC_ZERO; INT_SUM(107) <= LOGIC_ZERO; INT_SUM(108) <= LOGIC_ZERO; INT_SUM(109) <= LOGIC_ZERO; INT_SUM(110) <= LOGIC_ZERO; INT_SUM(111) <= LOGIC_ZERO; INT_SUM(112) <= LOGIC_ZERO; INT_SUM(113) <= LOGIC_ZERO; INT_SUM(114) <= LOGIC_ZERO; INT_SUM(115) <= LOGIC_ZERO; INT_SUM(116) <= LOGIC_ZERO; INT_SUM(117) <= LOGIC_ZERO; INT_SUM(118) <= LOGIC_ZERO; INT_SUM(119) <= LOGIC_ZERO; INT_SUM(120) <= LOGIC_ZERO; INT_SUM(121) <= LOGIC_ZERO; INT_SUM(122) <= LOGIC_ZERO; INT_SUM(123) <= LOGIC_ZERO; INT_SUM(124) <= LOGIC_ZERO; INT_SUM(125) <= LOGIC_ZERO; INT_SUM(126) <= LOGIC_ZERO; INT_SUM(127) <= LOGIC_ZERO; INT_SUMR(67 to 127) <= INT_SUM(67 to 127); INT_CARRYR(67 to 127) <= INT_CARRY(67 to 127); INT_CARRYR(0) <= INT_CARRY(0); reg : if MULPIPE /= 0 generate process (PHI) begin if rising_edge(PHI ) then if (holdn = '1') then INT_SUMR(0 to 66) <= INT_SUM(0 to 66); INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66); end if; end if; end process; end generate; noreg : if MULPIPE = 0 generate INT_SUMR(0 to 66) <= INT_SUM(0 to 66); INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66); end generate; D:DBLCADDER_128_128 port map ( OPA(0 to 127) => INT_SUMR(0 to 127), OPB(0 to 127) => INT_CARRYR(0 to 127), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 127) => RESULT(0 to 127) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ -- -- Modgen multiplier created Fri Aug 16 16:35:11 2002 -- ------------------------------------------------------------ -- START: Multiplier Entitiy ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -- START: Top entity ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_33 is generic (mulpipe : integer := 0); port(clk : in std_ulogic; holdn: in std_ulogic; X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(32 downto 0); P: out std_logic_vector(65 downto 0)); end MUL_33_33; architecture A of MUL_33_33 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 33); signal Q: std_logic_vector(0 to 127); begin U1: MULTIPLIER_34_34 generic map (mulpipe) port map(A,B,CLK, holdn ,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(17); B(18) <= Y(18); B(19) <= Y(19); B(20) <= Y(20); B(21) <= Y(21); B(22) <= Y(22); B(23) <= Y(23); B(24) <= Y(24); B(25) <= Y(25); B(26) <= Y(26); B(27) <= Y(27); B(28) <= Y(28); B(29) <= Y(29); B(30) <= Y(30); B(31) <= Y(31); B(32) <= Y(32); B(33) <= Y(32); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); P(42) <= Q(42); P(43) <= Q(43); P(44) <= Q(44); P(45) <= Q(45); P(46) <= Q(46); P(47) <= Q(47); P(48) <= Q(48); P(49) <= Q(49); P(50) <= Q(50); P(51) <= Q(51); P(52) <= Q(52); P(53) <= Q(53); P(54) <= Q(54); P(55) <= Q(55); P(56) <= Q(56); P(57) <= Q(57); P(58) <= Q(58); P(59) <= Q(59); P(60) <= Q(60); P(61) <= Q(61); P(62) <= Q(62); P(63) <= Q(63); P(64) <= Q(64); P(65) <= Q(65); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity ADD32 is port(X: in std_logic_vector(31 downto 0); Y: in std_logic_vector(31 downto 0); CI: in std_logic; S: out std_logic_vector(31 downto 0); CO: out std_logic); end ADD32; architecture A of ADD32 is signal A,B,Q: std_logic_vector(0 to 31); signal CLK: std_logic; begin U1: DBLCADDER_32_32 port map(A,B,CI,CLK,Q,CO); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); B(0) <= Y(0); A(1) <= X(1); B(1) <= Y(1); A(2) <= X(2); B(2) <= Y(2); A(3) <= X(3); B(3) <= Y(3); A(4) <= X(4); B(4) <= Y(4); A(5) <= X(5); B(5) <= Y(5); A(6) <= X(6); B(6) <= Y(6); A(7) <= X(7); B(7) <= Y(7); A(8) <= X(8); B(8) <= Y(8); A(9) <= X(9); B(9) <= Y(9); A(10) <= X(10); B(10) <= Y(10); A(11) <= X(11); B(11) <= Y(11); A(12) <= X(12); B(12) <= Y(12); A(13) <= X(13); B(13) <= Y(13); A(14) <= X(14); B(14) <= Y(14); A(15) <= X(15); B(15) <= Y(15); A(16) <= X(16); B(16) <= Y(16); A(17) <= X(17); B(17) <= Y(17); A(18) <= X(18); B(18) <= Y(18); A(19) <= X(19); B(19) <= Y(19); A(20) <= X(20); B(20) <= Y(20); A(21) <= X(21); B(21) <= Y(21); A(22) <= X(22); B(22) <= Y(22); A(23) <= X(23); B(23) <= Y(23); A(24) <= X(24); B(24) <= Y(24); A(25) <= X(25); B(25) <= Y(25); A(26) <= X(26); B(26) <= Y(26); A(27) <= X(27); B(27) <= Y(27); A(28) <= X(28); B(28) <= Y(28); A(29) <= X(29); B(29) <= Y(29); A(30) <= X(30); B(30) <= Y(30); A(31) <= X(31); B(31) <= Y(31); S(0) <= Q(0); S(1) <= Q(1); S(2) <= Q(2); S(3) <= Q(3); S(4) <= Q(4); S(5) <= Q(5); S(6) <= Q(6); S(7) <= Q(7); S(8) <= Q(8); S(9) <= Q(9); S(10) <= Q(10); S(11) <= Q(11); S(12) <= Q(12); S(13) <= Q(13); S(14) <= Q(14); S(15) <= Q(15); S(16) <= Q(16); S(17) <= Q(17); S(18) <= Q(18); S(19) <= Q(19); S(20) <= Q(20); S(21) <= Q(21); S(22) <= Q(22); S(23) <= Q(23); S(24) <= Q(24); S(25) <= Q(25); S(26) <= Q(26); S(27) <= Q(27); S(28) <= Q(28); S(29) <= Q(29); S(30) <= Q(30); S(31) <= Q(31); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_17_17 is generic (mulpipe : integer := 0); port(clk : in std_ulogic; holdn: in std_ulogic; X: in std_logic_vector(16 downto 0); Y: in std_logic_vector(16 downto 0); P: out std_logic_vector(33 downto 0)); end MUL_17_17; architecture A of MUL_17_17 is signal A: std_logic_vector(0 to 17); signal B: std_logic_vector(0 to 17); signal Q: std_logic_vector(0 to 63); begin U1: MULTIPLIER_18_18 generic map (mulpipe) port map(A,B,CLK, holdn, Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(16); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(16); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); end A;
----------------------------------------------------------------------------- -- File: leaves.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: A set of multipliers generated from the Arithmetic Module -- Generator at Norwegian University of Science and Technology. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; package blocks is component FLIPFLOP port ( DIN, CLK: in std_logic; DOUT: out std_logic ); end component; component DBLCADDER_32_32 port(OPA: in std_logic_vector(0 to 31); OPB: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; SUM: out std_logic_vector(0 to 31); COUT: out std_logic); end component; component FULL_ADDER port ( DATA_A, DATA_B, DATA_C: in std_logic; SAVE, CARRY: out std_logic ); end component; component HALF_ADDER port ( DATA_A, DATA_B: in std_logic; SAVE, CARRY: out std_logic ); end component; component R_GATE port ( INA, INB, INC: in std_logic; PPBIT: out std_logic ); end component; component DECODER port ( INA, INB, INC: in std_logic; TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic ); end component; component PP_LOW port ( ONEPOS, ONENEG, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end component; component PP_MIDDLE port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB, INC, IND: in std_logic; PPBIT: out std_logic ); end component; component PP_HIGH port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end component; component BLOCK0 port ( A,B,PHI: in std_logic; POUT,GOUT: out std_logic ); end component; component INVBLOCK port ( GIN,PHI:in std_logic; GOUT:out std_logic ); end component; component BLOCK1 port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end component; component BLOCK1A port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end component; component BLOCK2 port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end component; component BLOCK2A port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end component; component PRESTAGE_32 port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 31); GOUT: out std_logic_vector(0 to 32) ); end component; component XXOR1 port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end component; component XXOR2 port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end component; component DBLCTREE_32 port ( PIN:in std_logic_vector(0 to 31); GIN:in std_logic_vector(0 to 32); PHI:in std_logic; GOUT:out std_logic_vector(0 to 32); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_32 port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 32); SUM: out std_logic_vector(0 to 31); COUT: out std_logic ); end component; component DBLC_0_32 port ( PIN: in std_logic_vector(0 to 31); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 30); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_1_32 port ( PIN: in std_logic_vector(0 to 30); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 28); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_2_32 port ( PIN: in std_logic_vector(0 to 28); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 24); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_3_32 port ( PIN: in std_logic_vector(0 to 24); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 16); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_4_32 port ( PIN: in std_logic_vector(0 to 16); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 32) ); end component; component PRESTAGE_64 port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 63); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLCTREE_64 port ( PIN:in std_logic_vector(0 to 63); GIN:in std_logic_vector(0 to 64); PHI:in std_logic; GOUT:out std_logic_vector(0 to 64); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_64 port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 64); SUM: out std_logic_vector(0 to 63); COUT: out std_logic ); end component; component DBLC_0_64 port ( PIN: in std_logic_vector(0 to 63); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 62); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_1_64 port ( PIN: in std_logic_vector(0 to 62); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 60); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_2_64 port ( PIN: in std_logic_vector(0 to 60); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 56); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_3_64 port ( PIN: in std_logic_vector(0 to 56); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 48); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_4_64 port ( PIN: in std_logic_vector(0 to 48); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 32); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_5_64 port ( PIN: in std_logic_vector(0 to 32); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_0_128 port ( PIN: in std_logic_vector(0 to 127); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 126); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_1_128 port ( PIN: in std_logic_vector(0 to 126); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 124); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_2_128 port ( PIN: in std_logic_vector(0 to 124); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 120); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_3_128 port ( PIN: in std_logic_vector(0 to 120); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 112); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_4_128 port ( PIN: in std_logic_vector(0 to 112); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 96); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_5_128 port ( PIN: in std_logic_vector(0 to 96); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 64); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_6_128 port ( PIN: in std_logic_vector(0 to 64); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 128) ); end component; component PRESTAGE_128 port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 127); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLCTREE_128 port ( PIN:in std_logic_vector(0 to 127); GIN:in std_logic_vector(0 to 128); PHI:in std_logic; GOUT:out std_logic_vector(0 to 128); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_128 port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 128); SUM: out std_logic_vector(0 to 127); COUT: out std_logic ); end component; component BOOTHCODER_18_18 port ( OPA: in std_logic_vector(0 to 17); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 188) ); end component; component WALLACE_18_18 port ( SUMMAND: in std_logic_vector(0 to 188); CARRY: out std_logic_vector(0 to 33); SUM: out std_logic_vector(0 to 34) ); end component; component DBLCADDER_64_64 port ( OPA:in std_logic_vector(0 to 63); OPB:in std_logic_vector(0 to 63); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 63); COUT:out std_logic ); end component; component BOOTHCODER_34_10 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 9); SUMMAND: out std_logic_vector(0 to 184) ); end component; component WALLACE_34_10 port ( SUMMAND: in std_logic_vector(0 to 184); CARRY: out std_logic_vector(0 to 41); SUM: out std_logic_vector(0 to 42) ); end component; component BOOTHCODER_34_18 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 332) ); end component; component WALLACE_34_18 port ( SUMMAND: in std_logic_vector(0 to 332); CARRY: out std_logic_vector(0 to 49); SUM: out std_logic_vector(0 to 50) ); end component; component BOOTHCODER_34_34 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 33); SUMMAND: out std_logic_vector(0 to 628) ); end component; component WALLACE_34_34 port ( SUMMAND: in std_logic_vector(0 to 628); CARRY: out std_logic_vector(0 to 65); SUM: out std_logic_vector(0 to 66) ); end component; component DBLCADDER_128_128 port ( OPA:in std_logic_vector(0 to 127); OPB:in std_logic_vector(0 to 127); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 127); COUT:out std_logic ); end component; component MULTIPLIER_18_18 generic (mulpipe : integer := 0); port(MULTIPLICAND: in std_logic_vector(0 to 17); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_ulogic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_10 port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 9); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_18 port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_34 generic (mulpipe : integer := 0); port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 33); PHI: in std_logic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 127)); end component; end; ------------------------------------------------------------ -- START: Entities used within the Modified Booth Recoding ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity FLIPFLOP is port ( DIN: in std_logic; CLK: in std_logic; DOUT: out std_logic ); end FLIPFLOP; architecture FLIPFLOP of FLIPFLOP is begin process(CLK) begin if(CLK='1')and(CLK'event)then DOUT <= DIN; end if; end process; end FLIPFLOP; library ieee; use ieee.std_logic_1164.all; entity PP_LOW is port ( ONEPOS, ONENEG, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end PP_LOW; architecture PP_LOW of PP_LOW is begin PPBIT <= (ONEPOS and INA) or (ONENEG and INB) or TWONEG; end PP_LOW; library ieee; use ieee.std_logic_1164.all; entity PP_MIDDLE is port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB, INC, IND: in std_logic; PPBIT: out std_logic ); end PP_MIDDLE; architecture PP_MIDDLE of PP_MIDDLE is begin PPBIT <= not((not(INA and TWOPOS)) and (not(INB and TWONEG)) and (not(INC and ONEPOS)) and (not(IND and ONENEG))); end PP_MIDDLE; library ieee; use ieee.std_logic_1164.all; entity PP_HIGH is port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end PP_HIGH; architecture PP_HIGH of PP_HIGH is begin PPBIT <= not ((INA and ONEPOS) or (INB and ONENEG) or (INA and TWOPOS) or (INB and TWONEG)); end PP_HIGH; library ieee; use ieee.std_logic_1164.all; entity R_GATE is port ( INA, INB, INC: in std_logic; PPBIT: out std_logic ); end R_GATE; architecture R_GATE of R_GATE is begin PPBIT <= (not(INA and INB)) and INC; end R_GATE; library ieee; use ieee.std_logic_1164.all; entity DECODER is port ( INA, INB, INC: in std_logic; TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic ); end DECODER; architecture DECODER of DECODER is begin TWOPOS <= not(not(INA and INB and (not INC))); TWONEG <= not(not((not INA) and (not INB) and INC)); ONEPOS <= ((not INA) and INB and (not INC)) or ((not INC) and (not INB) and INA); ONENEG <= (INA and (not INB) and INC) or (INC and INB and (not INA)); end DECODER; library ieee; use ieee.std_logic_1164.all; entity FULL_ADDER is port ( DATA_A, DATA_B, DATA_C: in std_logic; SAVE, CARRY: out std_logic ); end FULL_ADDER; architecture FULL_ADDER of FULL_ADDER is signal TMP: std_logic; begin TMP <= DATA_A xor DATA_B; SAVE <= TMP xor DATA_C; CARRY <= not((not (TMP and DATA_C)) and (not (DATA_A and DATA_B))); end FULL_ADDER; library ieee; use ieee.std_logic_1164.all; entity HALF_ADDER is port ( DATA_A, DATA_B: in std_logic; SAVE, CARRY: out std_logic ); end HALF_ADDER; architecture HALF_ADDER of HALF_ADDER is begin SAVE <= DATA_A xor DATA_B; CARRY <= DATA_A and DATA_B; end HALF_ADDER; library ieee; use ieee.std_logic_1164.all; entity INVBLOCK is port ( GIN,PHI:in std_logic; GOUT:out std_logic ); end INVBLOCK; architecture INVBLOCK_regular of INVBLOCK is begin GOUT <= not GIN; end INVBLOCK_regular; library ieee; use ieee.std_logic_1164.all; entity XXOR1 is port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end XXOR1; architecture XXOR_regular of XXOR1 is begin SUM <= (not (A xor B)) xor GIN; end XXOR_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK0 is port ( A,B,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK0; architecture BLOCK0_regular of BLOCK0 is begin POUT <= not(A or B); GOUT <= not(A and B); end BLOCK0_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK1 is port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK1; architecture BLOCK1_regular of BLOCK1 is begin POUT <= not(PIN1 or PIN2); GOUT <= not(GIN2 and (PIN2 or GIN1)); end BLOCK1_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK2 is port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK2; architecture BLOCK2_regular of BLOCK2 is begin POUT <= not(PIN1 and PIN2); GOUT <= not(GIN2 or (PIN2 and GIN1)); end BLOCK2_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK1A is port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end BLOCK1A; architecture BLOCK1A_regular of BLOCK1A is begin GOUT <= not(GIN2 and (PIN2 or GIN1)); end BLOCK1A_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK2A is port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end BLOCK2A; architecture BLOCK2A_regular of BLOCK2A is begin GOUT <= not(GIN2 or (PIN2 and GIN1)); end BLOCK2A_regular; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_64 is port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 63); GOUT: out std_logic_vector(0 to 64) ); end PRESTAGE_64; architecture PRESTAGE of PRESTAGE_64 is begin -- PRESTAGE U1:for I in 0 to 63 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: Level 0 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_64 is port ( PIN: in std_logic_vector(0 to 63); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 62); GOUT: out std_logic_vector(0 to 64) ); end DBLC_0_64; architecture DBLC_0 of DBLC_0_64 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 64 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_64 is port ( PIN: in std_logic_vector(0 to 62); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 60); GOUT: out std_logic_vector(0 to 64) ); end DBLC_1_64; architecture DBLC_1 of DBLC_1_64 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 64 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_64 is port ( PIN: in std_logic_vector(0 to 60); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 56); GOUT: out std_logic_vector(0 to 64) ); end DBLC_2_64; architecture DBLC_2 of DBLC_2_64 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 64 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_64 is port ( PIN: in std_logic_vector(0 to 56); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 48); GOUT: out std_logic_vector(0 to 64) ); end DBLC_3_64; architecture DBLC_3 of DBLC_3_64 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 64 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_64 is port ( PIN: in std_logic_vector(0 to 48); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 32); GOUT: out std_logic_vector(0 to 64) ); end DBLC_4_64; architecture DBLC_4 of DBLC_4_64 is begin -- Architecture DBLC_4 U1: for I in 0 to 15 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 64 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; -- The DBLC-tree: Level 5 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_5_64 is port ( PIN: in std_logic_vector(0 to 32); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 64) ); end DBLC_5_64; architecture DBLC_5 of DBLC_5_64 is begin -- Architecture DBLC_5 U1: for I in 0 to 31 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 32 to 63 generate U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 64 to 64 generate U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I)); end generate U3; end DBLC_5; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_64 is port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 64); SUM: out std_logic_vector(0 to 63); COUT: out std_logic ); end XORSTAGE_64; architecture XORSTAGE of XORSTAGE_64 is begin -- XORSTAGE U2:for I in 0 to 63 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U1: BLOCK1A port map(PBIT,CARRY(0),CARRY(64),PHI,COUT); end XORSTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_64 is port ( PIN:in std_logic_vector(0 to 63); GIN:in std_logic_vector(0 to 64); PHI:in std_logic; GOUT:out std_logic_vector(0 to 64); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_64; architecture DBLCTREE of DBLCTREE_64 is signal INTPROP_0: std_logic_vector(0 to 62); signal INTGEN_0: std_logic_vector(0 to 64); signal INTPROP_1: std_logic_vector(0 to 60); signal INTGEN_1: std_logic_vector(0 to 64); signal INTPROP_2: std_logic_vector(0 to 56); signal INTGEN_2: std_logic_vector(0 to 64); signal INTPROP_3: std_logic_vector(0 to 48); signal INTGEN_3: std_logic_vector(0 to 64); signal INTPROP_4: std_logic_vector(0 to 32); signal INTGEN_4: std_logic_vector(0 to 64); begin -- Architecture DBLCTREE U_0: DBLC_0_64 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_64 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_64 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_64 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_64 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4); U_5: DBLC_5_64 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_64_64 is port ( OPA:in std_logic_vector(0 to 63); OPB:in std_logic_vector(0 to 63); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 63); COUT:out std_logic ); end DBLCADDER_64_64; architecture DBLCADDER of DBLCADDER_64_64 is signal INTPROP: std_logic_vector(0 to 63); signal INTGEN: std_logic_vector(0 to 64); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 64); begin -- Architecture DBLCADDER U1: PRESTAGE_64 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_64 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_64 port map(OPA(0 to 63),OPB(0 to 63),PBIT(0),PHI,CARRY(0 to 64),SUM,COUT); end DBLCADDER; ------------------------------------------------------------ -- END: Architectures used with the DBLC adder ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity XXOR2 is port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end XXOR2; architecture XXOR_true of XXOR2 is begin SUM <= (A xor B) xor GIN; end XXOR_true; -- -- Modgen adder created Fri Aug 16 14:47:23 2002 -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_32 is port ( PIN: in std_logic_vector(0 to 31); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 30); GOUT: out std_logic_vector(0 to 32) ); end DBLC_0_32; architecture DBLC_0 of DBLC_0_32 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 32 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_32 is port ( PIN: in std_logic_vector(0 to 30); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 28); GOUT: out std_logic_vector(0 to 32) ); end DBLC_1_32; architecture DBLC_1 of DBLC_1_32 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 32 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_32 is port ( PIN: in std_logic_vector(0 to 28); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 24); GOUT: out std_logic_vector(0 to 32) ); end DBLC_2_32; architecture DBLC_2 of DBLC_2_32 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 32 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_32 is port ( PIN: in std_logic_vector(0 to 24); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 16); GOUT: out std_logic_vector(0 to 32) ); end DBLC_3_32; architecture DBLC_3 of DBLC_3_32 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 32 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_32 is port ( PIN: in std_logic_vector(0 to 16); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 32) ); end DBLC_4_32; architecture DBLC_4 of DBLC_4_32 is begin -- Architecture DBLC_4 GOUT(0 to 15) <= GIN(0 to 15); U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 32 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_32 is port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 32); SUM: out std_logic_vector(0 to 31); COUT: out std_logic ); end XORSTAGE_32; architecture XORSTAGE of XORSTAGE_32 is begin -- XORSTAGE U2:for I in 0 to 15 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U3:for I in 16 to 31 generate U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U3; U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(32),PHI,COUT); end XORSTAGE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_32 is port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 31); GOUT: out std_logic_vector(0 to 32) ); end PRESTAGE_32; architecture PRESTAGE of PRESTAGE_32 is begin -- PRESTAGE U1:for I in 0 to 31 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_32 is port ( PIN:in std_logic_vector(0 to 31); GIN:in std_logic_vector(0 to 32); PHI:in std_logic; GOUT:out std_logic_vector(0 to 32); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_32; architecture DBLCTREE of DBLCTREE_32 is signal INTPROP_0: std_logic_vector(0 to 30); signal INTGEN_0: std_logic_vector(0 to 32); signal INTPROP_1: std_logic_vector(0 to 28); signal INTGEN_1: std_logic_vector(0 to 32); signal INTPROP_2: std_logic_vector(0 to 24); signal INTGEN_2: std_logic_vector(0 to 32); signal INTPROP_3: std_logic_vector(0 to 16); signal INTGEN_3: std_logic_vector(0 to 32); begin -- Architecture DBLCTREE U_0: DBLC_0_32 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_32 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_32 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_32 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_32 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_32_32 is port ( OPA:in std_logic_vector(0 to 31); OPB:in std_logic_vector(0 to 31); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 31); COUT:out std_logic ); end DBLCADDER_32_32; architecture DBLCADDER of DBLCADDER_32_32 is signal INTPROP: std_logic_vector(0 to 31); signal INTGEN: std_logic_vector(0 to 32); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 32); begin -- Architecture DBLCADDER U1: PRESTAGE_32 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_32 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_32 port map(OPA(0 to 31),OPB(0 to 31),PBIT(0),PHI,CARRY(0 to 32),SUM,COUT); end DBLCADDER; ------------------------------------------------------------ -- END: Architectures used with the DBLC adder ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_128 is port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 127); GOUT: out std_logic_vector(0 to 128) ); end PRESTAGE_128; architecture PRESTAGE of PRESTAGE_128 is begin -- PRESTAGE U1:for I in 0 to 127 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: Level 0 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_128 is port ( PIN: in std_logic_vector(0 to 127); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 126); GOUT: out std_logic_vector(0 to 128) ); end DBLC_0_128; architecture DBLC_0 of DBLC_0_128 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 128 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_128 is port ( PIN: in std_logic_vector(0 to 126); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 124); GOUT: out std_logic_vector(0 to 128) ); end DBLC_1_128; architecture DBLC_1 of DBLC_1_128 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 128 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_128 is port ( PIN: in std_logic_vector(0 to 124); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 120); GOUT: out std_logic_vector(0 to 128) ); end DBLC_2_128; architecture DBLC_2 of DBLC_2_128 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 128 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_128 is port ( PIN: in std_logic_vector(0 to 120); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 112); GOUT: out std_logic_vector(0 to 128) ); end DBLC_3_128; architecture DBLC_3 of DBLC_3_128 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 128 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_128 is port ( PIN: in std_logic_vector(0 to 112); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 96); GOUT: out std_logic_vector(0 to 128) ); end DBLC_4_128; architecture DBLC_4 of DBLC_4_128 is begin -- Architecture DBLC_4 U1: for I in 0 to 15 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 128 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; -- The DBLC-tree: Level 5 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_5_128 is port ( PIN: in std_logic_vector(0 to 96); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 64); GOUT: out std_logic_vector(0 to 128) ); end DBLC_5_128; architecture DBLC_5 of DBLC_5_128 is begin -- Architecture DBLC_5 U1: for I in 0 to 31 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 32 to 63 generate U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 64 to 128 generate U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I)); end generate U3; end DBLC_5; -- The DBLC-tree: Level 6 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_6_128 is port ( PIN: in std_logic_vector(0 to 64); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 128) ); end DBLC_6_128; architecture DBLC_6 of DBLC_6_128 is begin -- Architecture DBLC_6 GOUT(0 to 63) <= GIN(0 to 63); U2: for I in 64 to 127 generate U21: BLOCK1A port map(PIN(I-64),GIN(I-64),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 128 to 128 generate U31: BLOCK1 port map(PIN(I-128),PIN(I-64),GIN(I-64),GIN(I),PHI,POUT(I-128),GOUT(I)); end generate U3; end DBLC_6; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_128 is port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 128); SUM: out std_logic_vector(0 to 127); COUT: out std_logic ); end XORSTAGE_128; architecture XORSTAGE of XORSTAGE_128 is begin -- XORSTAGE U2:for I in 0 to 63 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U3:for I in 64 to 127 generate U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U3; U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(128),PHI,COUT); end XORSTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_128 is port ( PIN:in std_logic_vector(0 to 127); GIN:in std_logic_vector(0 to 128); PHI:in std_logic; GOUT:out std_logic_vector(0 to 128); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_128; architecture DBLCTREE of DBLCTREE_128 is signal INTPROP_0: std_logic_vector(0 to 126); signal INTGEN_0: std_logic_vector(0 to 128); signal INTPROP_1: std_logic_vector(0 to 124); signal INTGEN_1: std_logic_vector(0 to 128); signal INTPROP_2: std_logic_vector(0 to 120); signal INTGEN_2: std_logic_vector(0 to 128); signal INTPROP_3: std_logic_vector(0 to 112); signal INTGEN_3: std_logic_vector(0 to 128); signal INTPROP_4: std_logic_vector(0 to 96); signal INTGEN_4: std_logic_vector(0 to 128); signal INTPROP_5: std_logic_vector(0 to 64); signal INTGEN_5: std_logic_vector(0 to 128); begin -- Architecture DBLCTREE U_0: DBLC_0_128 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_128 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_128 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_128 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_128 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4); U_5: DBLC_5_128 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>INTPROP_5,GOUT=>INTGEN_5); U_6: DBLC_6_128 port map(PIN=>INTPROP_5,GIN=>INTGEN_5,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_128_128 is port ( OPA:in std_logic_vector(0 to 127); OPB:in std_logic_vector(0 to 127); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 127); COUT:out std_logic ); end DBLCADDER_128_128; architecture DBLCADDER of DBLCADDER_128_128 is signal INTPROP: std_logic_vector(0 to 127); signal INTGEN: std_logic_vector(0 to 128); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 128); begin -- Architecture DBLCADDER U1: PRESTAGE_128 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_128 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_128 port map(OPA(0 to 127),OPB(0 to 127),PBIT(0),PHI,CARRY(0 to 128),SUM,COUT); end DBLCADDER; -- -- Modified Booth algorithm architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_18_18 is port ( OPA: in std_logic_vector(0 to 17); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 188) ); end BOOTHCODER_18_18; ------------------------------------------------------------ -- END: Entities used within the Modified Booth Recoding ------------------------------------------------------------ architecture BOOTHCODER of BOOTHCODER_18_18 is -- Components used in the architecture -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 17); signal INT_MULTIPLIER: std_logic_vector(0 to 35); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); PPH_0:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); SUMMAND(100) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_17:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_18:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_19:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_20:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_21:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_22:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_23:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_24:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_25:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_26:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_27:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_28:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_29:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_30:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_31:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_32:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(101) ); PPM_33:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(109) ); SUMMAND(110) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(118) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_34:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_35:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_36:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_37:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_38:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_39:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_40:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_41:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_42:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_43:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_44:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_45:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_46:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_47:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(102) ); PPM_48:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(111) ); PPM_49:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(119) ); PPM_50:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(126) ); SUMMAND(127) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(134) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_51:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_52:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_53:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_54:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_55:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_56:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_57:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_58:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_59:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_60:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_61:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_62:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(103) ); PPM_63:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(112) ); PPM_64:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(120) ); PPM_65:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(128) ); PPM_66:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(135) ); PPM_67:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(141) ); SUMMAND(142) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(148) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_68:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_69:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_70:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_71:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_72:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_73:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_74:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_75:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_76:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_77:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(104) ); PPM_78:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(113) ); PPM_79:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(121) ); PPM_80:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(129) ); PPM_81:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(136) ); PPM_82:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(143) ); PPM_83:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(149) ); PPM_84:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(154) ); SUMMAND(155) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_85:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_86:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_87:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_88:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_89:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_90:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_91:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_92:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(105) ); PPM_93:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(114) ); PPM_94:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(122) ); PPM_95:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(130) ); PPM_96:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(137) ); PPM_97:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(144) ); PPM_98:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(150) ); PPM_99:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(156) ); PPM_100:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(161) ); PPM_101:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(165) ); SUMMAND(166) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(170) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_102:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_103:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_104:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_105:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_106:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_107:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(106) ); PPM_108:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(115) ); PPM_109:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(123) ); PPM_110:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(131) ); PPM_111:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(138) ); PPM_112:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(145) ); PPM_113:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(151) ); PPM_114:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(157) ); PPM_115:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(162) ); PPM_116:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(167) ); PPM_117:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(171) ); PPM_118:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(174) ); SUMMAND(175) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(178) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_119:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_120:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_121:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_122:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(107) ); PPM_123:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(116) ); PPM_124:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(124) ); PPM_125:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(132) ); PPM_126:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(139) ); PPM_127:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(146) ); PPM_128:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(152) ); PPM_129:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(158) ); PPM_130:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(163) ); PPM_131:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(168) ); PPM_132:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(172) ); PPM_133:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(176) ); PPM_134:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(179) ); PPM_135:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(181) ); SUMMAND(182) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(184) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_136:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_137:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(108) ); PPM_138:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(117) ); PPM_139:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(125) ); PPM_140:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(133) ); PPM_141:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(140) ); PPM_142:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(147) ); PPM_143:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(153) ); PPM_144:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(159) ); PPM_145:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(164) ); PPM_146:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(169) ); PPM_147:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(173) ); PPM_148:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(177) ); PPM_149:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(180) ); PPM_150:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(183) ); PPM_151:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(185) ); PPM_152:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(186) ); SUMMAND(187) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(188) ); -- Begin partial product 9 end BOOTHCODER; ------------------------------------------------------------ -- END: Architectures used with the Modified Booth recoding ------------------------------------------------------------ -- -- Wallace tree architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_18_18 is port ( SUMMAND: in std_logic_vector(0 to 188); CARRY: out std_logic_vector(0 to 33); SUM: out std_logic_vector(0 to 34) ); end WALLACE_18_18; ------------------------------------------------------------ -- END: Entities within the Wallace-tree ------------------------------------------------------------ architecture WALLACE of WALLACE_18_18 is -- Components used in the netlist -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 114); signal INT_SUM: std_logic_vector(0 to 158); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin NO stage INT_SUM(76) <= SUMMAND(108); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(77), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_CARRY(49), DATA_C => INT_CARRY(50), SAVE => INT_SUM(78), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(51); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(77), DATA_B => INT_SUM(78), DATA_C => INT_SUM(79), SAVE => INT_SUM(80), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin NO stage INT_SUM(81) <= INT_CARRY(52); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(82) <= INT_CARRY(53); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_SUM(82), SAVE => INT_SUM(83), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin NO stage INT_SUM(84) <= INT_CARRY(54); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_64:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(83), DATA_B => INT_SUM(84), DATA_C => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End FA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_65:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(109), DATA_B => SUMMAND(110), DATA_C => SUMMAND(111), SAVE => INT_SUM(85), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(112), DATA_B => SUMMAND(113), DATA_C => SUMMAND(114), SAVE => INT_SUM(86), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117), SAVE => INT_SUM(87), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58), SAVE => INT_SUM(88), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(59), DATA_C => INT_CARRY(60), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_CARRY(61), SAVE => INT_SUM(91), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(91), DATA_B => INT_CARRY(62), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End HA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_72:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), DATA_C => SUMMAND(120), SAVE => INT_SUM(92), CARRY => INT_CARRY(70) ); ---- End FA stage ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(121), DATA_B => SUMMAND(122), DATA_C => SUMMAND(123), SAVE => INT_SUM(93), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(94) <= SUMMAND(124); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(95) <= SUMMAND(125); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_SUM(94), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin NO stage INT_SUM(97) <= INT_SUM(95); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(63), SAVE => INT_SUM(98), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(64), DATA_B => INT_CARRY(65), DATA_C => INT_CARRY(66), SAVE => INT_SUM(99), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(67), SAVE => INT_SUM(100), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin NO stage INT_SUM(101) <= INT_CARRY(68); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(69), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_79:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(102), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(103), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => INT_CARRY(70), SAVE => INT_SUM(104), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin NO stage INT_SUM(105) <= INT_CARRY(71); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_82:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_SUM(104), SAVE => INT_SUM(106), CARRY => INT_CARRY(79) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(105), DATA_B => INT_CARRY(72), SAVE => INT_SUM(107), CARRY => INT_CARRY(80) ); ---- End HA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(73), SAVE => INT_SUM(108), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin NO stage INT_SUM(109) <= INT_CARRY(74); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(75), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(134), DATA_B => SUMMAND(135), DATA_C => SUMMAND(136), SAVE => INT_SUM(110), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(137), DATA_B => SUMMAND(138), DATA_C => SUMMAND(139), SAVE => INT_SUM(111), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(112) <= SUMMAND(140); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_SUM(112), SAVE => INT_SUM(113), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), DATA_C => INT_CARRY(78), SAVE => INT_SUM(114), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_CARRY(79), SAVE => INT_SUM(115), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin NO stage INT_SUM(116) <= INT_CARRY(80); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(81), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_91:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143), SAVE => INT_SUM(117), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin FA stage FA_92:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146), SAVE => INT_SUM(118), CARRY => INT_CARRY(88) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= SUMMAND(147); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_SUM(119), SAVE => INT_SUM(120), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83), SAVE => INT_SUM(121), CARRY => INT_CARRY(90) ); ---- End HA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(84), SAVE => INT_SUM(122), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= INT_CARRY(85); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(86), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), DATA_C => SUMMAND(150), SAVE => INT_SUM(124), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(151), DATA_B => SUMMAND(152), DATA_C => SUMMAND(153), SAVE => INT_SUM(125), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(87), SAVE => INT_SUM(126), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin NO stage INT_SUM(127) <= INT_CARRY(88); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_99:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(89), SAVE => INT_SUM(128), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin NO stage INT_SUM(129) <= INT_CARRY(90); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(91), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_101:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(154), DATA_B => SUMMAND(155), DATA_C => SUMMAND(156), SAVE => INT_SUM(130), CARRY => INT_CARRY(96) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(157), DATA_B => SUMMAND(158), DATA_C => SUMMAND(159), SAVE => INT_SUM(131), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), DATA_C => INT_CARRY(92), SAVE => INT_SUM(132), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin NO stage INT_SUM(133) <= INT_CARRY(93); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(94), SAVE => INT_SUM(134), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(134), DATA_B => INT_CARRY(95), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End HA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_105:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(160), DATA_B => SUMMAND(161), DATA_C => SUMMAND(162), SAVE => INT_SUM(135), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(163), DATA_B => SUMMAND(164), SAVE => INT_SUM(136), CARRY => INT_CARRY(101) ); ---- End HA stage ---- Begin FA stage FA_106:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_CARRY(96), SAVE => INT_SUM(137), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin NO stage INT_SUM(138) <= INT_CARRY(97); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_CARRY(98), SAVE => INT_SUM(139), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(139), DATA_B => INT_CARRY(99), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_108:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(140), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), SAVE => INT_SUM(141), CARRY => INT_CARRY(105) ); ---- End HA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(100), SAVE => INT_SUM(142), CARRY => INT_CARRY(106) ); ---- End FA stage ---- Begin NO stage INT_SUM(143) <= INT_CARRY(101); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(102), SAVE => INT_SUM(144), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(144), DATA_B => INT_CARRY(103), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End HA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_111:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172), SAVE => INT_SUM(145), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(173), DATA_B => INT_CARRY(104), DATA_C => INT_CARRY(105), SAVE => INT_SUM(146), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin FA stage FA_113:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(106), SAVE => INT_SUM(147), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(147), DATA_B => INT_CARRY(107), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_114:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(148), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin NO stage INT_SUM(149) <= SUMMAND(177); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(108), SAVE => INT_SUM(150), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin NO stage INT_SUM(151) <= INT_CARRY(109); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(110), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_117:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(178), DATA_B => SUMMAND(179), DATA_C => SUMMAND(180), SAVE => INT_SUM(152), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin NO stage INT_SUM(153) <= INT_SUM(152); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(154) <= INT_CARRY(111); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_CARRY(112), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_119:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(181), DATA_B => SUMMAND(182), DATA_C => SUMMAND(183), SAVE => INT_SUM(155), CARRY => INT_CARRY(114) ); ---- End FA stage ---- Begin NO stage INT_SUM(156) <= INT_CARRY(113); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(155), DATA_B => INT_SUM(156), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End HA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin NO stage INT_SUM(157) <= SUMMAND(184); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(158) <= SUMMAND(185); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_120:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(114), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin HA stage HA_26:HALF_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End HA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin NO stage SUM(34) <= SUMMAND(188); -- At Level 5 ---- End NO stage -- End WT-branch 35 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_18_18 is generic (mulpipe : integer := 0); port ( MULTIPLICAND: in std_logic_vector(0 to 17); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_ulogic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_18_18; architecture MULTIPLIER of MULTIPLIER_18_18 is signal PPBIT:std_logic_vector(0 to 188); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_CARRYR: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal INT_SUMR: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_18_18 port map ( OPA(0 to 17) => MULTIPLICAND(0 to 17), OPB(0 to 17) => MULTIPLIER(0 to 17), SUMMAND(0 to 188) => PPBIT(0 to 188) ); W:WALLACE_18_18 port map ( SUMMAND(0 to 188) => PPBIT(0 to 188), CARRY(0 to 33) => INT_CARRY(1 to 34), SUM(0 to 34) => INT_SUM(0 to 34) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(35) <= LOGIC_ZERO; INT_CARRY(36) <= LOGIC_ZERO; INT_CARRY(37) <= LOGIC_ZERO; INT_CARRY(38) <= LOGIC_ZERO; INT_CARRY(39) <= LOGIC_ZERO; INT_CARRY(40) <= LOGIC_ZERO; INT_CARRY(41) <= LOGIC_ZERO; INT_CARRY(42) <= LOGIC_ZERO; INT_CARRY(43) <= LOGIC_ZERO; INT_CARRY(44) <= LOGIC_ZERO; INT_CARRY(45) <= LOGIC_ZERO; INT_CARRY(46) <= LOGIC_ZERO; INT_CARRY(47) <= LOGIC_ZERO; INT_CARRY(48) <= LOGIC_ZERO; INT_CARRY(49) <= LOGIC_ZERO; INT_CARRY(50) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(35) <= LOGIC_ZERO; INT_SUM(36) <= LOGIC_ZERO; INT_SUM(37) <= LOGIC_ZERO; INT_SUM(38) <= LOGIC_ZERO; INT_SUM(39) <= LOGIC_ZERO; INT_SUM(40) <= LOGIC_ZERO; INT_SUM(41) <= LOGIC_ZERO; INT_SUM(42) <= LOGIC_ZERO; INT_SUM(43) <= LOGIC_ZERO; INT_SUM(44) <= LOGIC_ZERO; INT_SUM(45) <= LOGIC_ZERO; INT_SUM(46) <= LOGIC_ZERO; INT_SUM(47) <= LOGIC_ZERO; INT_SUM(48) <= LOGIC_ZERO; INT_SUM(49) <= LOGIC_ZERO; INT_SUM(50) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; INT_SUMR(35 to 63) <= INT_SUM(35 to 63); INT_CARRYR(35 to 63) <= INT_CARRY(35 to 63); INT_CARRYR(0) <= INT_CARRY(0); reg : if MULPIPE /= 0 generate process (PHI) begin if rising_edge(PHI ) then if (holdn = '1') then INT_SUMR(0 to 34) <= INT_SUM(0 to 34); INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34); end if; end if; end process; end generate; noreg : if MULPIPE = 0 generate INT_SUMR(0 to 34) <= INT_SUM(0 to 34); INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34); end generate; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUMR(0 to 63), OPB(0 to 63) => INT_CARRYR(0 to 63), CIN => LOGIC_ZERO, PHI => PHI , SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_10 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 9); SUMMAND: out std_logic_vector(0 to 184) ); end BOOTHCODER_34_10; architecture BOOTHCODER of BOOTHCODER_34_10 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 19); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(40) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(45) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(50) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(55) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(60) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(65) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(70) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(75) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(85) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(95) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(100) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(105) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(110) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(115) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(120) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(125) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(130) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(135) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(140) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(145) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(150) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(155) ); SUMMAND(156) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(41) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(46) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(51) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(56) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(61) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(66) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(71) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(76) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(86) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(96) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(101) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(106) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(111) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(116) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(121) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(126) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(131) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(136) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(141) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(146) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(151) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(157) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(161) ); SUMMAND(162) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(166) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(42) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(47) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(52) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(57) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(62) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(67) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(72) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(77) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(87) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(97) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(102) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(107) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(112) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(117) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(122) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(127) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(132) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(137) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(142) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(147) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(152) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(158) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(163) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(167) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(170) ); SUMMAND(171) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(174) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(43) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(48) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(53) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(58) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(63) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(68) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(73) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(78) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(88) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(98) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(103) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(108) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(113) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(118) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(123) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(128) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(133) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(138) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(143) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(148) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(153) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(159) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(164) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(168) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(172) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(175) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(177) ); SUMMAND(178) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(180) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(44) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(49) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(54) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(59) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(64) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(69) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(74) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(79) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(89) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(99) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(104) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(109) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(114) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(119) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(124) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(129) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(134) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(139) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(144) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(149) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(154) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(165) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(169) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(173) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(176) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(179) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(181) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(182) ); SUMMAND(183) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(184) ); -- Begin partial product 5 end BOOTHCODER; ------------------------------------------------------------ -- END: Architectures used with the Modified Booth recoding ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the Wallace-tree ------------------------------------------------------------ -- -- Wallace tree architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_10 is port ( SUMMAND: in std_logic_vector(0 to 184); CARRY: out std_logic_vector(0 to 41); SUM: out std_logic_vector(0 to 42) ); end WALLACE_34_10; architecture WALLACE of WALLACE_34_10 is signal INT_CARRY: std_logic_vector(0 to 95); signal INT_SUM: std_logic_vector(0 to 133); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End HA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_CARRY(9), SAVE => INT_SUM(18), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin NO stage INT_SUM(19) <= INT_CARRY(10); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(18), DATA_B => INT_SUM(19), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_16:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(40), DATA_B => SUMMAND(41), DATA_C => SUMMAND(42), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End FA stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(43), DATA_B => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End HA stage ---- Begin FA stage FA_17:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(20), DATA_B => INT_SUM(21), DATA_C => INT_CARRY(12), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin NO stage INT_SUM(23) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(22), DATA_B => INT_SUM(23), DATA_C => INT_CARRY(14), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End FA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_19:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(24), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End HA stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(24), DATA_B => INT_SUM(25), DATA_C => INT_CARRY(15), SAVE => INT_SUM(26), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin NO stage INT_SUM(27) <= INT_CARRY(16); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_21:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(26), DATA_B => INT_SUM(27), DATA_C => INT_CARRY(17), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End FA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(50), DATA_B => SUMMAND(51), DATA_C => SUMMAND(52), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(53), DATA_B => SUMMAND(54), SAVE => INT_SUM(29), CARRY => INT_CARRY(22) ); ---- End HA stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(28), DATA_B => INT_SUM(29), DATA_C => INT_CARRY(18), SAVE => INT_SUM(30), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin NO stage INT_SUM(31) <= INT_CARRY(19); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(30), DATA_B => INT_SUM(31), DATA_C => INT_CARRY(20), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_25:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(55), DATA_B => SUMMAND(56), DATA_C => SUMMAND(57), SAVE => INT_SUM(32), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(58), DATA_B => SUMMAND(59), SAVE => INT_SUM(33), CARRY => INT_CARRY(25) ); ---- End HA stage ---- Begin FA stage FA_26:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(32), DATA_B => INT_SUM(33), DATA_C => INT_CARRY(21), SAVE => INT_SUM(34), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(35) <= INT_CARRY(22); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_CARRY(23), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_28:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(60), DATA_B => SUMMAND(61), DATA_C => SUMMAND(62), SAVE => INT_SUM(36), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), SAVE => INT_SUM(37), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(36), DATA_B => INT_SUM(37), DATA_C => INT_CARRY(24), SAVE => INT_SUM(38), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(39) <= INT_CARRY(25); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(38), DATA_B => INT_SUM(39), DATA_C => INT_CARRY(26), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(65), DATA_B => SUMMAND(66), DATA_C => SUMMAND(67), SAVE => INT_SUM(40), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(68), DATA_B => SUMMAND(69), SAVE => INT_SUM(41), CARRY => INT_CARRY(31) ); ---- End HA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(40), DATA_B => INT_SUM(41), DATA_C => INT_CARRY(27), SAVE => INT_SUM(42), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin NO stage INT_SUM(43) <= INT_CARRY(28); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(42), DATA_B => INT_SUM(43), DATA_C => INT_CARRY(29), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_34:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(70), DATA_B => SUMMAND(71), DATA_C => SUMMAND(72), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(73), DATA_B => SUMMAND(74), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(30), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(31); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(32), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End FA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End HA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_CARRY(33), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End FA stage ---- Begin NO stage INT_SUM(51) <= INT_CARRY(34); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(50), DATA_B => INT_SUM(51), DATA_C => INT_CARRY(35), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End FA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_40:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(52), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), SAVE => INT_SUM(53), CARRY => INT_CARRY(40) ); ---- End HA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(52), DATA_B => INT_SUM(53), DATA_C => INT_CARRY(36), SAVE => INT_SUM(54), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(55) <= INT_CARRY(37); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(54), DATA_B => INT_SUM(55), DATA_C => INT_CARRY(38), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End FA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(85), DATA_B => SUMMAND(86), DATA_C => SUMMAND(87), SAVE => INT_SUM(56), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(88), DATA_B => SUMMAND(89), SAVE => INT_SUM(57), CARRY => INT_CARRY(43) ); ---- End HA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(56), DATA_B => INT_SUM(57), DATA_C => INT_CARRY(39), SAVE => INT_SUM(58), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(59) <= INT_CARRY(40); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(58), DATA_B => INT_SUM(59), DATA_C => INT_CARRY(41), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_46:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(60), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), SAVE => INT_SUM(61), CARRY => INT_CARRY(46) ); ---- End HA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(60), DATA_B => INT_SUM(61), DATA_C => INT_CARRY(42), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin NO stage INT_SUM(63) <= INT_CARRY(43); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(44), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_49:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(95), DATA_B => SUMMAND(96), DATA_C => SUMMAND(97), SAVE => INT_SUM(64), CARRY => INT_CARRY(48) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(98), DATA_B => SUMMAND(99), SAVE => INT_SUM(65), CARRY => INT_CARRY(49) ); ---- End HA stage ---- Begin FA stage FA_50:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_CARRY(45), SAVE => INT_SUM(66), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin NO stage INT_SUM(67) <= INT_CARRY(46); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(66), DATA_B => INT_SUM(67), DATA_C => INT_CARRY(47), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(100), DATA_B => SUMMAND(101), DATA_C => SUMMAND(102), SAVE => INT_SUM(68), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(103), DATA_B => SUMMAND(104), SAVE => INT_SUM(69), CARRY => INT_CARRY(52) ); ---- End HA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(68), DATA_B => INT_SUM(69), DATA_C => INT_CARRY(48), SAVE => INT_SUM(70), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin NO stage INT_SUM(71) <= INT_CARRY(49); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(70), DATA_B => INT_SUM(71), DATA_C => INT_CARRY(50), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_55:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(72), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), SAVE => INT_SUM(73), CARRY => INT_CARRY(55) ); ---- End HA stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(72), DATA_B => INT_SUM(73), DATA_C => INT_CARRY(51), SAVE => INT_SUM(74), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin NO stage INT_SUM(75) <= INT_CARRY(52); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_57:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(74), DATA_B => INT_SUM(75), DATA_C => INT_CARRY(53), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112), SAVE => INT_SUM(76), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), SAVE => INT_SUM(77), CARRY => INT_CARRY(58) ); ---- End HA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(54), SAVE => INT_SUM(78), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(55); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(56), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End FA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_61:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117), SAVE => INT_SUM(80), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), SAVE => INT_SUM(81), CARRY => INT_CARRY(61) ); ---- End HA stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_CARRY(57), SAVE => INT_SUM(82), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin NO stage INT_SUM(83) <= INT_CARRY(58); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(59), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End FA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_64:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(84), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), SAVE => INT_SUM(85), CARRY => INT_CARRY(64) ); ---- End HA stage ---- Begin FA stage FA_65:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(60), SAVE => INT_SUM(86), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin NO stage INT_SUM(87) <= INT_CARRY(61); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(62), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End FA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_67:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(125), DATA_B => SUMMAND(126), DATA_C => SUMMAND(127), SAVE => INT_SUM(88), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(128), DATA_B => SUMMAND(129), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End HA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(88), DATA_B => INT_SUM(89), DATA_C => INT_CARRY(63), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(91) <= INT_CARRY(64); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(90), DATA_B => INT_SUM(91), DATA_C => INT_CARRY(65), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End FA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_70:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(130), DATA_B => SUMMAND(131), DATA_C => SUMMAND(132), SAVE => INT_SUM(92), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(133), DATA_B => SUMMAND(134), SAVE => INT_SUM(93), CARRY => INT_CARRY(70) ); ---- End HA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66), SAVE => INT_SUM(94), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(67); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), SAVE => INT_SUM(97), CARRY => INT_CARRY(73) ); ---- End HA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(69), SAVE => INT_SUM(98), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin NO stage INT_SUM(99) <= INT_CARRY(70); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(71), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_76:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(140), DATA_B => SUMMAND(141), DATA_C => SUMMAND(142), SAVE => INT_SUM(100), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), SAVE => INT_SUM(101), CARRY => INT_CARRY(76) ); ---- End HA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(72), SAVE => INT_SUM(102), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin NO stage INT_SUM(103) <= INT_CARRY(73); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(74), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End FA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_79:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(145), DATA_B => SUMMAND(146), DATA_C => SUMMAND(147), SAVE => INT_SUM(104), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), SAVE => INT_SUM(105), CARRY => INT_CARRY(79) ); ---- End HA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(104), DATA_B => INT_SUM(105), DATA_C => INT_CARRY(75), SAVE => INT_SUM(106), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin NO stage INT_SUM(107) <= INT_CARRY(76); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(77), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_82:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152), SAVE => INT_SUM(108), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), SAVE => INT_SUM(109), CARRY => INT_CARRY(82) ); ---- End HA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(78), SAVE => INT_SUM(110), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(111) <= INT_CARRY(79); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(80), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End FA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(155), DATA_B => SUMMAND(156), DATA_C => SUMMAND(157), SAVE => INT_SUM(112), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(158), DATA_B => SUMMAND(159), DATA_C => SUMMAND(160), SAVE => INT_SUM(113), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_CARRY(81), SAVE => INT_SUM(114), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin NO stage INT_SUM(115) <= INT_CARRY(82); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(114), DATA_B => INT_SUM(115), DATA_C => INT_CARRY(83), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_89:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(161), DATA_B => SUMMAND(162), DATA_C => SUMMAND(163), SAVE => INT_SUM(116), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(164), DATA_B => SUMMAND(165), SAVE => INT_SUM(117), CARRY => INT_CARRY(88) ); ---- End HA stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(84), SAVE => INT_SUM(118), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= INT_CARRY(85); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_91:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(86), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End FA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(166), DATA_B => SUMMAND(167), DATA_C => SUMMAND(168), SAVE => INT_SUM(120), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin NO stage INT_SUM(121) <= SUMMAND(169); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(87), SAVE => INT_SUM(122), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= INT_CARRY(88); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(89), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_95:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172), SAVE => INT_SUM(124), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin NO stage INT_SUM(125) <= SUMMAND(173); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(90), SAVE => INT_SUM(126), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(126), DATA_B => INT_CARRY(91), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End HA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_97:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(127), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin NO stage INT_SUM(128) <= INT_SUM(127); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(129) <= INT_CARRY(92); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(93), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_99:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(130), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin NO stage INT_SUM(131) <= INT_CARRY(94); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End HA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin NO stage INT_SUM(132) <= SUMMAND(180); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(133) <= SUMMAND(181); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(95), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin HA stage HA_35:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End HA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin NO stage SUM(42) <= SUMMAND(184); -- At Level 3 ---- End NO stage -- End WT-branch 43 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_10 is port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 9); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_34_10; ------------------------------------------------------------ -- End: Multiplier Entitiy architecture MULTIPLIER of MULTIPLIER_34_10 is signal PPBIT:std_logic_vector(0 to 184); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_10 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 9) => MULTIPLIER(0 to 9), SUMMAND(0 to 184) => PPBIT(0 to 184) ); W:WALLACE_34_10 port map ( SUMMAND(0 to 184) => PPBIT(0 to 184), CARRY(0 to 41) => INT_CARRY(1 to 42), SUM(0 to 42) => INT_SUM(0 to 42) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(43) <= LOGIC_ZERO; INT_CARRY(44) <= LOGIC_ZERO; INT_CARRY(45) <= LOGIC_ZERO; INT_CARRY(46) <= LOGIC_ZERO; INT_CARRY(47) <= LOGIC_ZERO; INT_CARRY(48) <= LOGIC_ZERO; INT_CARRY(49) <= LOGIC_ZERO; INT_CARRY(50) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(43) <= LOGIC_ZERO; INT_SUM(44) <= LOGIC_ZERO; INT_SUM(45) <= LOGIC_ZERO; INT_SUM(46) <= LOGIC_ZERO; INT_SUM(47) <= LOGIC_ZERO; INT_SUM(48) <= LOGIC_ZERO; INT_SUM(49) <= LOGIC_ZERO; INT_SUM(50) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUM(0 to 63), OPB(0 to 63) => INT_CARRY(0 to 63), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_9 is port(X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(8 downto 0); P: out std_logic_vector(41 downto 0)); end MUL_33_9; library ieee; use ieee.std_logic_1164.all; architecture A of MUL_33_9 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 9); signal Q: std_logic_vector(0 to 63); signal CLK: std_logic; begin U1: MULTIPLIER_34_10 port map(A,B,CLK,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(8); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); end A; ------------------------------------------------------------ -- START: Entities within the Wallace-tree ------------------------------------------------------------ -- -- Modified Booth algorithm architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_18 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 332) ); end BOOTHCODER_34_18; architecture BOOTHCODER of BOOTHCODER_34_18 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 35); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(108) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(117) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(126) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(135) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(144) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(153) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(162) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(171) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(180) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(189) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(198) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(207) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(216) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(225) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(234) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(243) ); SUMMAND(244) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(100) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(109) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(118) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(127) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(136) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(145) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(154) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(163) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(172) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(181) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(190) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(199) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(208) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(217) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(226) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(235) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(245) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(253) ); SUMMAND(254) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(262) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(101) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(110) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(119) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(128) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(137) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(146) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(155) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(164) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(173) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(182) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(191) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(200) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(209) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(218) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(227) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(236) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(246) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(255) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(263) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(270) ); SUMMAND(271) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(278) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(102) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(111) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(120) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(129) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(138) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(147) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(156) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(165) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(174) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(183) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(192) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(201) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(210) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(219) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(228) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(237) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(247) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(256) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(264) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(272) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(279) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(285) ); SUMMAND(286) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(292) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(103) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(112) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(121) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(130) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(139) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(148) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(157) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(166) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(175) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(184) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(193) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(202) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(211) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(220) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(229) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(238) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(248) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(257) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(265) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(273) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(280) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(287) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(293) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(298) ); SUMMAND(299) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(304) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_165:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_166:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_167:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_168:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_169:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_170:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_171:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_172:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(104) ); PPM_173:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(113) ); PPM_174:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(122) ); PPM_175:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(131) ); PPM_176:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(140) ); PPM_177:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(149) ); PPM_178:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(158) ); PPM_179:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(167) ); PPM_180:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(176) ); PPM_181:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(185) ); PPM_182:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(194) ); PPM_183:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(203) ); PPM_184:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(212) ); PPM_185:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(221) ); PPM_186:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(230) ); PPM_187:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(239) ); PPM_188:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(249) ); PPM_189:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(258) ); PPM_190:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(266) ); PPM_191:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(274) ); PPM_192:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(281) ); PPM_193:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(288) ); PPM_194:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(294) ); PPM_195:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(300) ); PPM_196:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(305) ); PPM_197:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(309) ); SUMMAND(310) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(314) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_198:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_199:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_200:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_201:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_202:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_203:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(105) ); PPM_204:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(114) ); PPM_205:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(123) ); PPM_206:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(132) ); PPM_207:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(141) ); PPM_208:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(150) ); PPM_209:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(159) ); PPM_210:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(168) ); PPM_211:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(177) ); PPM_212:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(186) ); PPM_213:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(195) ); PPM_214:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(204) ); PPM_215:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(213) ); PPM_216:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(222) ); PPM_217:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(231) ); PPM_218:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(240) ); PPM_219:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(250) ); PPM_220:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(259) ); PPM_221:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(267) ); PPM_222:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(275) ); PPM_223:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(282) ); PPM_224:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(289) ); PPM_225:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(295) ); PPM_226:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(301) ); PPM_227:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(306) ); PPM_228:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(311) ); PPM_229:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(315) ); PPM_230:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(318) ); SUMMAND(319) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(322) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_231:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_232:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_233:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_234:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(106) ); PPM_235:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(115) ); PPM_236:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(124) ); PPM_237:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(133) ); PPM_238:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(142) ); PPM_239:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(151) ); PPM_240:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(160) ); PPM_241:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(169) ); PPM_242:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(178) ); PPM_243:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(187) ); PPM_244:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(196) ); PPM_245:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(205) ); PPM_246:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(214) ); PPM_247:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(223) ); PPM_248:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(232) ); PPM_249:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(241) ); PPM_250:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(251) ); PPM_251:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(260) ); PPM_252:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(268) ); PPM_253:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(276) ); PPM_254:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(283) ); PPM_255:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(290) ); PPM_256:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(296) ); PPM_257:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(302) ); PPM_258:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(307) ); PPM_259:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(312) ); PPM_260:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(316) ); PPM_261:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(320) ); PPM_262:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(323) ); PPM_263:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(325) ); SUMMAND(326) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(328) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_264:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_265:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(107) ); PPM_266:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(116) ); PPM_267:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(125) ); PPM_268:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(134) ); PPM_269:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(143) ); PPM_270:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(152) ); PPM_271:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(161) ); PPM_272:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(170) ); PPM_273:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(179) ); PPM_274:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(188) ); PPM_275:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(197) ); PPM_276:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(206) ); PPM_277:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(215) ); PPM_278:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(224) ); PPM_279:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(233) ); PPM_280:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(242) ); PPM_281:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(252) ); PPM_282:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(261) ); PPM_283:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(269) ); PPM_284:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(277) ); PPM_285:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(284) ); PPM_286:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(291) ); PPM_287:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(297) ); PPM_288:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(303) ); PPM_289:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(308) ); PPM_290:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(313) ); PPM_291:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(317) ); PPM_292:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(321) ); PPM_293:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(324) ); PPM_294:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(327) ); PPM_295:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(329) ); PPM_296:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(330) ); SUMMAND(331) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(332) ); -- Begin partial product 9 end BOOTHCODER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_18 is port ( SUMMAND: in std_logic_vector(0 to 332); CARRY: out std_logic_vector(0 to 49); SUM: out std_logic_vector(0 to 50) ); end WALLACE_34_18; architecture WALLACE of WALLACE_34_18 is -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 226); signal INT_SUM: std_logic_vector(0 to 286); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(76), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(49), DATA_B => INT_CARRY(50), DATA_C => INT_CARRY(51), SAVE => INT_SUM(77), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(52), SAVE => INT_SUM(78), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(53); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(54), SAVE => INT_SUM(80), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(80), DATA_B => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End HA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_64:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), DATA_C => SUMMAND(110), SAVE => INT_SUM(81), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin FA stage FA_65:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(111), DATA_B => SUMMAND(112), DATA_C => SUMMAND(113), SAVE => INT_SUM(82), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(114), DATA_B => SUMMAND(115), DATA_C => SUMMAND(116), SAVE => INT_SUM(83), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(81), DATA_B => INT_SUM(82), DATA_C => INT_SUM(83), SAVE => INT_SUM(84), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58), SAVE => INT_SUM(85), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(59), SAVE => INT_SUM(86), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(87) <= INT_CARRY(60); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(61), SAVE => INT_SUM(88), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(62), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End HA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_71:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(117), DATA_B => SUMMAND(118), DATA_C => SUMMAND(119), SAVE => INT_SUM(89), CARRY => INT_CARRY(70) ); ---- End FA stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(90), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125), SAVE => INT_SUM(91), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91), SAVE => INT_SUM(92), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(63), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65), SAVE => INT_SUM(93), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66), SAVE => INT_SUM(94), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(67); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68), SAVE => INT_SUM(96), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(96), DATA_B => INT_CARRY(69), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End HA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_78:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(97), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin FA stage FA_79:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(98), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134), SAVE => INT_SUM(99), CARRY => INT_CARRY(79) ); ---- End FA stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(97), DATA_B => INT_SUM(98), DATA_C => INT_SUM(99), SAVE => INT_SUM(100), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin FA stage FA_82:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(70), DATA_B => INT_CARRY(71), DATA_C => INT_CARRY(72), SAVE => INT_SUM(101), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(73), SAVE => INT_SUM(102), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin NO stage INT_SUM(103) <= INT_CARRY(74); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(75), SAVE => INT_SUM(104), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(104), DATA_B => INT_CARRY(76), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End HA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(105), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140), SAVE => INT_SUM(106), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143), SAVE => INT_SUM(107), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_SUM(107), SAVE => INT_SUM(108), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(77), DATA_B => INT_CARRY(78), DATA_C => INT_CARRY(79), SAVE => INT_SUM(109), CARRY => INT_CARRY(88) ); ---- End FA stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(80), SAVE => INT_SUM(110), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(111) <= INT_CARRY(81); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_91:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(82), SAVE => INT_SUM(112), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(112), DATA_B => INT_CARRY(83), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End HA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146), SAVE => INT_SUM(113), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(147), DATA_B => SUMMAND(148), DATA_C => SUMMAND(149), SAVE => INT_SUM(114), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152), SAVE => INT_SUM(115), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_SUM(115), SAVE => INT_SUM(116), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86), SAVE => INT_SUM(117), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(87), SAVE => INT_SUM(118), CARRY => INT_CARRY(96) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= INT_CARRY(88); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(89), SAVE => INT_SUM(120), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(120), DATA_B => INT_CARRY(90), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End HA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_99:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), DATA_C => SUMMAND(155), SAVE => INT_SUM(121), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158), SAVE => INT_SUM(122), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin FA stage FA_101:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161), SAVE => INT_SUM(123), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(121), DATA_B => INT_SUM(122), DATA_C => INT_SUM(123), SAVE => INT_SUM(124), CARRY => INT_CARRY(101) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(91), DATA_B => INT_CARRY(92), DATA_C => INT_CARRY(93), SAVE => INT_SUM(125), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(94), SAVE => INT_SUM(126), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin NO stage INT_SUM(127) <= INT_CARRY(95); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_105:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(96), SAVE => INT_SUM(128), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(128), DATA_B => INT_CARRY(97), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End HA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_106:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164), SAVE => INT_SUM(129), CARRY => INT_CARRY(105) ); ---- End FA stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(130), CARRY => INT_CARRY(106) ); ---- End FA stage ---- Begin FA stage FA_108:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170), SAVE => INT_SUM(131), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_SUM(131), SAVE => INT_SUM(132), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(98), DATA_B => INT_CARRY(99), DATA_C => INT_CARRY(100), SAVE => INT_SUM(133), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin FA stage FA_111:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(101), SAVE => INT_SUM(134), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin NO stage INT_SUM(135) <= INT_CARRY(102); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(134), DATA_B => INT_SUM(135), DATA_C => INT_CARRY(103), SAVE => INT_SUM(136), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(136), DATA_B => INT_CARRY(104), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End HA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_113:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173), SAVE => INT_SUM(137), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin FA stage FA_114:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(138), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(139), CARRY => INT_CARRY(114) ); ---- End FA stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_SUM(139), SAVE => INT_SUM(140), CARRY => INT_CARRY(115) ); ---- End FA stage ---- Begin FA stage FA_117:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(105), DATA_B => INT_CARRY(106), DATA_C => INT_CARRY(107), SAVE => INT_SUM(141), CARRY => INT_CARRY(116) ); ---- End FA stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(108), SAVE => INT_SUM(142), CARRY => INT_CARRY(117) ); ---- End FA stage ---- Begin NO stage INT_SUM(143) <= INT_CARRY(109); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_119:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(110), SAVE => INT_SUM(144), CARRY => INT_CARRY(118) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(144), DATA_B => INT_CARRY(111), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_120:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), DATA_C => SUMMAND(182), SAVE => INT_SUM(145), CARRY => INT_CARRY(119) ); ---- End FA stage ---- Begin FA stage FA_121:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(183), DATA_B => SUMMAND(184), DATA_C => SUMMAND(185), SAVE => INT_SUM(146), CARRY => INT_CARRY(120) ); ---- End FA stage ---- Begin FA stage FA_122:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), DATA_C => SUMMAND(188), SAVE => INT_SUM(147), CARRY => INT_CARRY(121) ); ---- End FA stage ---- Begin FA stage FA_123:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_SUM(147), SAVE => INT_SUM(148), CARRY => INT_CARRY(122) ); ---- End FA stage ---- Begin FA stage FA_124:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(112), DATA_B => INT_CARRY(113), DATA_C => INT_CARRY(114), SAVE => INT_SUM(149), CARRY => INT_CARRY(123) ); ---- End FA stage ---- Begin FA stage FA_125:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(115), SAVE => INT_SUM(150), CARRY => INT_CARRY(124) ); ---- End FA stage ---- Begin NO stage INT_SUM(151) <= INT_CARRY(116); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_126:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(117), SAVE => INT_SUM(152), CARRY => INT_CARRY(125) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(152), DATA_B => INT_CARRY(118), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End HA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_127:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(189), DATA_B => SUMMAND(190), DATA_C => SUMMAND(191), SAVE => INT_SUM(153), CARRY => INT_CARRY(126) ); ---- End FA stage ---- Begin FA stage FA_128:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(192), DATA_B => SUMMAND(193), DATA_C => SUMMAND(194), SAVE => INT_SUM(154), CARRY => INT_CARRY(127) ); ---- End FA stage ---- Begin FA stage FA_129:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197), SAVE => INT_SUM(155), CARRY => INT_CARRY(128) ); ---- End FA stage ---- Begin FA stage FA_130:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_SUM(155), SAVE => INT_SUM(156), CARRY => INT_CARRY(129) ); ---- End FA stage ---- Begin FA stage FA_131:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(119), DATA_B => INT_CARRY(120), DATA_C => INT_CARRY(121), SAVE => INT_SUM(157), CARRY => INT_CARRY(130) ); ---- End FA stage ---- Begin FA stage FA_132:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(156), DATA_B => INT_SUM(157), DATA_C => INT_CARRY(122), SAVE => INT_SUM(158), CARRY => INT_CARRY(131) ); ---- End FA stage ---- Begin NO stage INT_SUM(159) <= INT_CARRY(123); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_133:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(158), DATA_B => INT_SUM(159), DATA_C => INT_CARRY(124), SAVE => INT_SUM(160), CARRY => INT_CARRY(132) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(160), DATA_B => INT_CARRY(125), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_134:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200), SAVE => INT_SUM(161), CARRY => INT_CARRY(133) ); ---- End FA stage ---- Begin FA stage FA_135:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203), SAVE => INT_SUM(162), CARRY => INT_CARRY(134) ); ---- End FA stage ---- Begin FA stage FA_136:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206), SAVE => INT_SUM(163), CARRY => INT_CARRY(135) ); ---- End FA stage ---- Begin FA stage FA_137:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(161), DATA_B => INT_SUM(162), DATA_C => INT_SUM(163), SAVE => INT_SUM(164), CARRY => INT_CARRY(136) ); ---- End FA stage ---- Begin FA stage FA_138:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(126), DATA_B => INT_CARRY(127), DATA_C => INT_CARRY(128), SAVE => INT_SUM(165), CARRY => INT_CARRY(137) ); ---- End FA stage ---- Begin FA stage FA_139:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(164), DATA_B => INT_SUM(165), DATA_C => INT_CARRY(129), SAVE => INT_SUM(166), CARRY => INT_CARRY(138) ); ---- End FA stage ---- Begin NO stage INT_SUM(167) <= INT_CARRY(130); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_140:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(131), SAVE => INT_SUM(168), CARRY => INT_CARRY(139) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(168), DATA_B => INT_CARRY(132), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End HA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_141:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209), SAVE => INT_SUM(169), CARRY => INT_CARRY(140) ); ---- End FA stage ---- Begin FA stage FA_142:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212), SAVE => INT_SUM(170), CARRY => INT_CARRY(141) ); ---- End FA stage ---- Begin FA stage FA_143:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215), SAVE => INT_SUM(171), CARRY => INT_CARRY(142) ); ---- End FA stage ---- Begin FA stage FA_144:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(169), DATA_B => INT_SUM(170), DATA_C => INT_SUM(171), SAVE => INT_SUM(172), CARRY => INT_CARRY(143) ); ---- End FA stage ---- Begin FA stage FA_145:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135), SAVE => INT_SUM(173), CARRY => INT_CARRY(144) ); ---- End FA stage ---- Begin FA stage FA_146:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(172), DATA_B => INT_SUM(173), DATA_C => INT_CARRY(136), SAVE => INT_SUM(174), CARRY => INT_CARRY(145) ); ---- End FA stage ---- Begin NO stage INT_SUM(175) <= INT_CARRY(137); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_147:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(174), DATA_B => INT_SUM(175), DATA_C => INT_CARRY(138), SAVE => INT_SUM(176), CARRY => INT_CARRY(146) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(176), DATA_B => INT_CARRY(139), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End HA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_148:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218), SAVE => INT_SUM(177), CARRY => INT_CARRY(147) ); ---- End FA stage ---- Begin FA stage FA_149:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221), SAVE => INT_SUM(178), CARRY => INT_CARRY(148) ); ---- End FA stage ---- Begin FA stage FA_150:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), DATA_C => SUMMAND(224), SAVE => INT_SUM(179), CARRY => INT_CARRY(149) ); ---- End FA stage ---- Begin FA stage FA_151:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(177), DATA_B => INT_SUM(178), DATA_C => INT_SUM(179), SAVE => INT_SUM(180), CARRY => INT_CARRY(150) ); ---- End FA stage ---- Begin FA stage FA_152:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(140), DATA_B => INT_CARRY(141), DATA_C => INT_CARRY(142), SAVE => INT_SUM(181), CARRY => INT_CARRY(151) ); ---- End FA stage ---- Begin FA stage FA_153:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), DATA_C => INT_CARRY(143), SAVE => INT_SUM(182), CARRY => INT_CARRY(152) ); ---- End FA stage ---- Begin NO stage INT_SUM(183) <= INT_CARRY(144); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_154:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_CARRY(145), SAVE => INT_SUM(184), CARRY => INT_CARRY(153) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(184), DATA_B => INT_CARRY(146), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End HA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_155:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(225), DATA_B => SUMMAND(226), DATA_C => SUMMAND(227), SAVE => INT_SUM(185), CARRY => INT_CARRY(154) ); ---- End FA stage ---- Begin FA stage FA_156:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(228), DATA_B => SUMMAND(229), DATA_C => SUMMAND(230), SAVE => INT_SUM(186), CARRY => INT_CARRY(155) ); ---- End FA stage ---- Begin FA stage FA_157:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(231), DATA_B => SUMMAND(232), DATA_C => SUMMAND(233), SAVE => INT_SUM(187), CARRY => INT_CARRY(156) ); ---- End FA stage ---- Begin FA stage FA_158:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_SUM(187), SAVE => INT_SUM(188), CARRY => INT_CARRY(157) ); ---- End FA stage ---- Begin FA stage FA_159:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(147), DATA_B => INT_CARRY(148), DATA_C => INT_CARRY(149), SAVE => INT_SUM(189), CARRY => INT_CARRY(158) ); ---- End FA stage ---- Begin FA stage FA_160:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(188), DATA_B => INT_SUM(189), DATA_C => INT_CARRY(150), SAVE => INT_SUM(190), CARRY => INT_CARRY(159) ); ---- End FA stage ---- Begin NO stage INT_SUM(191) <= INT_CARRY(151); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_161:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(190), DATA_B => INT_SUM(191), DATA_C => INT_CARRY(152), SAVE => INT_SUM(192), CARRY => INT_CARRY(160) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(192), DATA_B => INT_CARRY(153), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End HA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_162:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(234), DATA_B => SUMMAND(235), DATA_C => SUMMAND(236), SAVE => INT_SUM(193), CARRY => INT_CARRY(161) ); ---- End FA stage ---- Begin FA stage FA_163:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(237), DATA_B => SUMMAND(238), DATA_C => SUMMAND(239), SAVE => INT_SUM(194), CARRY => INT_CARRY(162) ); ---- End FA stage ---- Begin FA stage FA_164:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242), SAVE => INT_SUM(195), CARRY => INT_CARRY(163) ); ---- End FA stage ---- Begin FA stage FA_165:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(193), DATA_B => INT_SUM(194), DATA_C => INT_SUM(195), SAVE => INT_SUM(196), CARRY => INT_CARRY(164) ); ---- End FA stage ---- Begin FA stage FA_166:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(154), DATA_B => INT_CARRY(155), DATA_C => INT_CARRY(156), SAVE => INT_SUM(197), CARRY => INT_CARRY(165) ); ---- End FA stage ---- Begin FA stage FA_167:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(196), DATA_B => INT_SUM(197), DATA_C => INT_CARRY(157), SAVE => INT_SUM(198), CARRY => INT_CARRY(166) ); ---- End FA stage ---- Begin NO stage INT_SUM(199) <= INT_CARRY(158); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_168:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(198), DATA_B => INT_SUM(199), DATA_C => INT_CARRY(159), SAVE => INT_SUM(200), CARRY => INT_CARRY(167) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(200), DATA_B => INT_CARRY(160), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End HA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_169:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245), SAVE => INT_SUM(201), CARRY => INT_CARRY(168) ); ---- End FA stage ---- Begin FA stage FA_170:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248), SAVE => INT_SUM(202), CARRY => INT_CARRY(169) ); ---- End FA stage ---- Begin FA stage FA_171:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251), SAVE => INT_SUM(203), CARRY => INT_CARRY(170) ); ---- End FA stage ---- Begin NO stage INT_SUM(204) <= SUMMAND(252); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_172:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(201), DATA_B => INT_SUM(202), DATA_C => INT_SUM(203), SAVE => INT_SUM(205), CARRY => INT_CARRY(171) ); ---- End FA stage ---- Begin FA stage FA_173:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(204), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162), SAVE => INT_SUM(206), CARRY => INT_CARRY(172) ); ---- End FA stage ---- Begin NO stage INT_SUM(207) <= INT_CARRY(163); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_174:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207), SAVE => INT_SUM(208), CARRY => INT_CARRY(173) ); ---- End FA stage ---- Begin NO stage INT_SUM(209) <= INT_CARRY(164); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(210) <= INT_CARRY(165); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_175:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_SUM(210), SAVE => INT_SUM(211), CARRY => INT_CARRY(174) ); ---- End FA stage ---- Begin NO stage INT_SUM(212) <= INT_CARRY(166); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_176:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(211), DATA_B => INT_SUM(212), DATA_C => INT_CARRY(167), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_177:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(253), DATA_B => SUMMAND(254), DATA_C => SUMMAND(255), SAVE => INT_SUM(213), CARRY => INT_CARRY(175) ); ---- End FA stage ---- Begin FA stage FA_178:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(256), DATA_B => SUMMAND(257), DATA_C => SUMMAND(258), SAVE => INT_SUM(214), CARRY => INT_CARRY(176) ); ---- End FA stage ---- Begin FA stage FA_179:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(259), DATA_B => SUMMAND(260), DATA_C => SUMMAND(261), SAVE => INT_SUM(215), CARRY => INT_CARRY(177) ); ---- End FA stage ---- Begin FA stage FA_180:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(168), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170), SAVE => INT_SUM(216), CARRY => INT_CARRY(178) ); ---- End FA stage ---- Begin FA stage FA_181:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(213), DATA_B => INT_SUM(214), DATA_C => INT_SUM(215), SAVE => INT_SUM(217), CARRY => INT_CARRY(179) ); ---- End FA stage ---- Begin FA stage FA_182:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(216), DATA_B => INT_CARRY(171), DATA_C => INT_CARRY(172), SAVE => INT_SUM(218), CARRY => INT_CARRY(180) ); ---- End FA stage ---- Begin FA stage FA_183:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_CARRY(173), SAVE => INT_SUM(219), CARRY => INT_CARRY(181) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(219), DATA_B => INT_CARRY(174), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End HA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_184:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(262), DATA_B => SUMMAND(263), DATA_C => SUMMAND(264), SAVE => INT_SUM(220), CARRY => INT_CARRY(182) ); ---- End FA stage ---- Begin FA stage FA_185:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(265), DATA_B => SUMMAND(266), DATA_C => SUMMAND(267), SAVE => INT_SUM(221), CARRY => INT_CARRY(183) ); ---- End FA stage ---- Begin NO stage INT_SUM(222) <= SUMMAND(268); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(223) <= SUMMAND(269); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_186:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_SUM(222), SAVE => INT_SUM(224), CARRY => INT_CARRY(184) ); ---- End FA stage ---- Begin NO stage INT_SUM(225) <= INT_SUM(223); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_187:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(224), DATA_B => INT_SUM(225), DATA_C => INT_CARRY(175), SAVE => INT_SUM(226), CARRY => INT_CARRY(185) ); ---- End FA stage ---- Begin FA stage FA_188:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(176), DATA_B => INT_CARRY(177), DATA_C => INT_CARRY(178), SAVE => INT_SUM(227), CARRY => INT_CARRY(186) ); ---- End FA stage ---- Begin FA stage FA_189:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_CARRY(179), SAVE => INT_SUM(228), CARRY => INT_CARRY(187) ); ---- End FA stage ---- Begin NO stage INT_SUM(229) <= INT_CARRY(180); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_190:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(228), DATA_B => INT_SUM(229), DATA_C => INT_CARRY(181), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_191:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(270), DATA_B => SUMMAND(271), DATA_C => SUMMAND(272), SAVE => INT_SUM(230), CARRY => INT_CARRY(188) ); ---- End FA stage ---- Begin FA stage FA_192:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(273), DATA_B => SUMMAND(274), DATA_C => SUMMAND(275), SAVE => INT_SUM(231), CARRY => INT_CARRY(189) ); ---- End FA stage ---- Begin FA stage FA_193:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(276), DATA_B => SUMMAND(277), DATA_C => INT_CARRY(182), SAVE => INT_SUM(232), CARRY => INT_CARRY(190) ); ---- End FA stage ---- Begin NO stage INT_SUM(233) <= INT_CARRY(183); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_194:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(230), DATA_B => INT_SUM(231), DATA_C => INT_SUM(232), SAVE => INT_SUM(234), CARRY => INT_CARRY(191) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(233), DATA_B => INT_CARRY(184), SAVE => INT_SUM(235), CARRY => INT_CARRY(192) ); ---- End HA stage ---- Begin FA stage FA_195:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(234), DATA_B => INT_SUM(235), DATA_C => INT_CARRY(185), SAVE => INT_SUM(236), CARRY => INT_CARRY(193) ); ---- End FA stage ---- Begin NO stage INT_SUM(237) <= INT_CARRY(186); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_196:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_CARRY(187), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End FA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_197:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280), SAVE => INT_SUM(238), CARRY => INT_CARRY(194) ); ---- End FA stage ---- Begin FA stage FA_198:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283), SAVE => INT_SUM(239), CARRY => INT_CARRY(195) ); ---- End FA stage ---- Begin NO stage INT_SUM(240) <= SUMMAND(284); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_199:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(238), DATA_B => INT_SUM(239), DATA_C => INT_SUM(240), SAVE => INT_SUM(241), CARRY => INT_CARRY(196) ); ---- End FA stage ---- Begin FA stage FA_200:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190), SAVE => INT_SUM(242), CARRY => INT_CARRY(197) ); ---- End FA stage ---- Begin FA stage FA_201:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(241), DATA_B => INT_SUM(242), DATA_C => INT_CARRY(191), SAVE => INT_SUM(243), CARRY => INT_CARRY(198) ); ---- End FA stage ---- Begin NO stage INT_SUM(244) <= INT_CARRY(192); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_202:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(243), DATA_B => INT_SUM(244), DATA_C => INT_CARRY(193), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_203:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(285), DATA_B => SUMMAND(286), DATA_C => SUMMAND(287), SAVE => INT_SUM(245), CARRY => INT_CARRY(199) ); ---- End FA stage ---- Begin FA stage FA_204:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290), SAVE => INT_SUM(246), CARRY => INT_CARRY(200) ); ---- End FA stage ---- Begin NO stage INT_SUM(247) <= SUMMAND(291); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_205:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(245), DATA_B => INT_SUM(246), DATA_C => INT_SUM(247), SAVE => INT_SUM(248), CARRY => INT_CARRY(201) ); ---- End FA stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(194), DATA_B => INT_CARRY(195), SAVE => INT_SUM(249), CARRY => INT_CARRY(202) ); ---- End HA stage ---- Begin FA stage FA_206:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(248), DATA_B => INT_SUM(249), DATA_C => INT_CARRY(196), SAVE => INT_SUM(250), CARRY => INT_CARRY(203) ); ---- End FA stage ---- Begin NO stage INT_SUM(251) <= INT_CARRY(197); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_207:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(250), DATA_B => INT_SUM(251), DATA_C => INT_CARRY(198), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End FA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin FA stage FA_208:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(292), DATA_B => SUMMAND(293), DATA_C => SUMMAND(294), SAVE => INT_SUM(252), CARRY => INT_CARRY(204) ); ---- End FA stage ---- Begin FA stage FA_209:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(295), DATA_B => SUMMAND(296), DATA_C => SUMMAND(297), SAVE => INT_SUM(253), CARRY => INT_CARRY(205) ); ---- End FA stage ---- Begin FA stage FA_210:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(252), DATA_B => INT_SUM(253), DATA_C => INT_CARRY(199), SAVE => INT_SUM(254), CARRY => INT_CARRY(206) ); ---- End FA stage ---- Begin NO stage INT_SUM(255) <= INT_CARRY(200); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_211:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_CARRY(201), SAVE => INT_SUM(256), CARRY => INT_CARRY(207) ); ---- End FA stage ---- Begin NO stage INT_SUM(257) <= INT_CARRY(202); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_212:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(256), DATA_B => INT_SUM(257), DATA_C => INT_CARRY(203), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin FA stage FA_213:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(298), DATA_B => SUMMAND(299), DATA_C => SUMMAND(300), SAVE => INT_SUM(258), CARRY => INT_CARRY(208) ); ---- End FA stage ---- Begin FA stage FA_214:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(301), DATA_B => SUMMAND(302), DATA_C => SUMMAND(303), SAVE => INT_SUM(259), CARRY => INT_CARRY(209) ); ---- End FA stage ---- Begin FA stage FA_215:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(258), DATA_B => INT_SUM(259), DATA_C => INT_CARRY(204), SAVE => INT_SUM(260), CARRY => INT_CARRY(210) ); ---- End FA stage ---- Begin NO stage INT_SUM(261) <= INT_CARRY(205); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_216:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(206), SAVE => INT_SUM(262), CARRY => INT_CARRY(211) ); ---- End FA stage ---- Begin HA stage HA_35:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(262), DATA_B => INT_CARRY(207), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End HA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin FA stage FA_217:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(304), DATA_B => SUMMAND(305), DATA_C => SUMMAND(306), SAVE => INT_SUM(263), CARRY => INT_CARRY(212) ); ---- End FA stage ---- Begin HA stage HA_36:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(307), DATA_B => SUMMAND(308), SAVE => INT_SUM(264), CARRY => INT_CARRY(213) ); ---- End HA stage ---- Begin FA stage FA_218:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(263), DATA_B => INT_SUM(264), DATA_C => INT_CARRY(208), SAVE => INT_SUM(265), CARRY => INT_CARRY(214) ); ---- End FA stage ---- Begin NO stage INT_SUM(266) <= INT_CARRY(209); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_219:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(210), SAVE => INT_SUM(267), CARRY => INT_CARRY(215) ); ---- End FA stage ---- Begin HA stage HA_37:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(267), DATA_B => INT_CARRY(211), SAVE => SUM(42), CARRY => CARRY(42) ); ---- End HA stage -- End WT-branch 43 -- Begin WT-branch 44 ---- Begin FA stage FA_220:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311), SAVE => INT_SUM(268), CARRY => INT_CARRY(216) ); ---- End FA stage ---- Begin HA stage HA_38:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), SAVE => INT_SUM(269), CARRY => INT_CARRY(217) ); ---- End HA stage ---- Begin FA stage FA_221:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(268), DATA_B => INT_SUM(269), DATA_C => INT_CARRY(212), SAVE => INT_SUM(270), CARRY => INT_CARRY(218) ); ---- End FA stage ---- Begin NO stage INT_SUM(271) <= INT_CARRY(213); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_222:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(270), DATA_B => INT_SUM(271), DATA_C => INT_CARRY(214), SAVE => INT_SUM(272), CARRY => INT_CARRY(219) ); ---- End FA stage ---- Begin HA stage HA_39:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(272), DATA_B => INT_CARRY(215), SAVE => SUM(43), CARRY => CARRY(43) ); ---- End HA stage -- End WT-branch 44 -- Begin WT-branch 45 ---- Begin FA stage FA_223:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(314), DATA_B => SUMMAND(315), DATA_C => SUMMAND(316), SAVE => INT_SUM(273), CARRY => INT_CARRY(220) ); ---- End FA stage ---- Begin FA stage FA_224:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(317), DATA_B => INT_CARRY(216), DATA_C => INT_CARRY(217), SAVE => INT_SUM(274), CARRY => INT_CARRY(221) ); ---- End FA stage ---- Begin FA stage FA_225:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(273), DATA_B => INT_SUM(274), DATA_C => INT_CARRY(218), SAVE => INT_SUM(275), CARRY => INT_CARRY(222) ); ---- End FA stage ---- Begin HA stage HA_40:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(275), DATA_B => INT_CARRY(219), SAVE => SUM(44), CARRY => CARRY(44) ); ---- End HA stage -- End WT-branch 45 -- Begin WT-branch 46 ---- Begin FA stage FA_226:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320), SAVE => INT_SUM(276), CARRY => INT_CARRY(223) ); ---- End FA stage ---- Begin NO stage INT_SUM(277) <= SUMMAND(321); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_227:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(276), DATA_B => INT_SUM(277), DATA_C => INT_CARRY(220), SAVE => INT_SUM(278), CARRY => INT_CARRY(224) ); ---- End FA stage ---- Begin NO stage INT_SUM(279) <= INT_CARRY(221); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_228:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(278), DATA_B => INT_SUM(279), DATA_C => INT_CARRY(222), SAVE => SUM(45), CARRY => CARRY(45) ); ---- End FA stage -- End WT-branch 46 -- Begin WT-branch 47 ---- Begin FA stage FA_229:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(322), DATA_B => SUMMAND(323), DATA_C => SUMMAND(324), SAVE => INT_SUM(280), CARRY => INT_CARRY(225) ); ---- End FA stage ---- Begin NO stage INT_SUM(281) <= INT_SUM(280); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(282) <= INT_CARRY(223); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_230:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(281), DATA_B => INT_SUM(282), DATA_C => INT_CARRY(224), SAVE => SUM(46), CARRY => CARRY(46) ); ---- End FA stage -- End WT-branch 47 -- Begin WT-branch 48 ---- Begin FA stage FA_231:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(325), DATA_B => SUMMAND(326), DATA_C => SUMMAND(327), SAVE => INT_SUM(283), CARRY => INT_CARRY(226) ); ---- End FA stage ---- Begin NO stage INT_SUM(284) <= INT_CARRY(225); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_41:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(283), DATA_B => INT_SUM(284), SAVE => SUM(47), CARRY => CARRY(47) ); ---- End HA stage -- End WT-branch 48 -- Begin WT-branch 49 ---- Begin NO stage INT_SUM(285) <= SUMMAND(328); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(286) <= SUMMAND(329); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_232:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(285), DATA_B => INT_SUM(286), DATA_C => INT_CARRY(226), SAVE => SUM(48), CARRY => CARRY(48) ); ---- End FA stage -- End WT-branch 49 -- Begin WT-branch 50 ---- Begin HA stage HA_42:HALF_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(330), DATA_B => SUMMAND(331), SAVE => SUM(49), CARRY => CARRY(49) ); ---- End HA stage -- End WT-branch 50 -- Begin WT-branch 51 ---- Begin NO stage SUM(50) <= SUMMAND(332); -- At Level 5 ---- End NO stage -- End WT-branch 51 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_18 is port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_34_18; ------------------------------------------------------------ -- End: Multiplier Entitiy architecture MULTIPLIER of MULTIPLIER_34_18 is signal PPBIT:std_logic_vector(0 to 332); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_18 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 17) => MULTIPLIER(0 to 17), SUMMAND(0 to 332) => PPBIT(0 to 332) ); W:WALLACE_34_18 port map ( SUMMAND(0 to 332) => PPBIT(0 to 332), CARRY(0 to 49) => INT_CARRY(1 to 50), SUM(0 to 50) => INT_SUM(0 to 50) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUM(0 to 63), OPB(0 to 63) => INT_CARRY(0 to 63), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ -- -- Modgen multiplier created Fri Aug 16 16:29:15 2002 -- ------------------------------------------------------------ -- START: Multiplier Entitiy ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -- START: Top entity ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_17 is port(X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(16 downto 0); P: out std_logic_vector(49 downto 0)); end MUL_33_17; library ieee; use ieee.std_logic_1164.all; architecture A of MUL_33_17 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 17); signal Q: std_logic_vector(0 to 63); signal CLK: std_logic; begin U1: MULTIPLIER_34_18 port map(A,B,CLK,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(16); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); P(42) <= Q(42); P(43) <= Q(43); P(44) <= Q(44); P(45) <= Q(45); P(46) <= Q(46); P(47) <= Q(47); P(48) <= Q(48); P(49) <= Q(49); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_34 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 33); SUMMAND: out std_logic_vector(0 to 628) ); end BOOTHCODER_34_34; architecture BOOTHCODER of BOOTHCODER_34_34 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 67); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(110) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(120) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(132) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(143) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(156) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(168) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(182) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(195) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(210) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(224) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(240) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(255) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(272) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(288) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(306) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(323) ); SUMMAND(324) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(100) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(111) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(121) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(133) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(144) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(157) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(169) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(183) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(196) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(211) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(225) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(241) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(256) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(273) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(289) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(307) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(325) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(341) ); SUMMAND(342) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(358) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(101) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(112) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(122) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(134) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(145) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(158) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(170) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(184) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(197) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(212) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(226) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(242) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(257) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(274) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(290) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(308) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(326) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(343) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(359) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(374) ); SUMMAND(375) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(390) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(102) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(113) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(123) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(135) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(146) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(159) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(171) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(185) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(198) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(213) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(227) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(243) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(258) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(275) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(291) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(309) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(327) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(344) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(360) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(376) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(391) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(405) ); SUMMAND(406) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(420) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(103) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(114) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(124) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(136) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(147) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(172) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(186) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(199) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(214) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(228) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(244) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(259) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(276) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(292) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(310) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(328) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(345) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(361) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(377) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(392) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(407) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(421) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(434) ); SUMMAND(435) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(448) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_165:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_166:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_167:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_168:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_169:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_170:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_171:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_172:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(104) ); PPM_173:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(115) ); PPM_174:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(125) ); PPM_175:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(137) ); PPM_176:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(148) ); PPM_177:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(161) ); PPM_178:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(173) ); PPM_179:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(187) ); PPM_180:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(200) ); PPM_181:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(215) ); PPM_182:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(229) ); PPM_183:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(245) ); PPM_184:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(260) ); PPM_185:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(277) ); PPM_186:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(293) ); PPM_187:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(311) ); PPM_188:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(329) ); PPM_189:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(346) ); PPM_190:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(362) ); PPM_191:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(378) ); PPM_192:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(393) ); PPM_193:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(408) ); PPM_194:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(422) ); PPM_195:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(436) ); PPM_196:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(449) ); PPM_197:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(461) ); SUMMAND(462) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(474) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_198:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_199:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_200:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_201:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_202:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_203:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(105) ); PPM_204:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(116) ); PPM_205:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(126) ); PPM_206:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(138) ); PPM_207:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(149) ); PPM_208:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(162) ); PPM_209:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(174) ); PPM_210:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(188) ); PPM_211:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(201) ); PPM_212:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(216) ); PPM_213:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(230) ); PPM_214:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(246) ); PPM_215:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(261) ); PPM_216:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(278) ); PPM_217:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(294) ); PPM_218:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(312) ); PPM_219:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(330) ); PPM_220:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(347) ); PPM_221:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(363) ); PPM_222:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(379) ); PPM_223:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(394) ); PPM_224:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(409) ); PPM_225:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(423) ); PPM_226:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(437) ); PPM_227:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(450) ); PPM_228:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(463) ); PPM_229:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(475) ); PPM_230:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(486) ); SUMMAND(487) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(498) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_231:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_232:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_233:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_234:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(106) ); PPM_235:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(117) ); PPM_236:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(127) ); PPM_237:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(139) ); PPM_238:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(150) ); PPM_239:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(163) ); PPM_240:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(175) ); PPM_241:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(189) ); PPM_242:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(202) ); PPM_243:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(217) ); PPM_244:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(231) ); PPM_245:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(247) ); PPM_246:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(262) ); PPM_247:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(279) ); PPM_248:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(295) ); PPM_249:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(313) ); PPM_250:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(331) ); PPM_251:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(348) ); PPM_252:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(364) ); PPM_253:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(380) ); PPM_254:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(395) ); PPM_255:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(410) ); PPM_256:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(424) ); PPM_257:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(438) ); PPM_258:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(451) ); PPM_259:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(464) ); PPM_260:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(476) ); PPM_261:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(488) ); PPM_262:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(499) ); PPM_263:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(509) ); SUMMAND(510) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(520) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_264:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_265:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(107) ); PPM_266:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(118) ); PPM_267:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(128) ); PPM_268:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(140) ); PPM_269:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(151) ); PPM_270:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(164) ); PPM_271:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(176) ); PPM_272:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(190) ); PPM_273:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(203) ); PPM_274:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(218) ); PPM_275:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(232) ); PPM_276:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(248) ); PPM_277:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(263) ); PPM_278:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(280) ); PPM_279:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(296) ); PPM_280:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(314) ); PPM_281:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(332) ); PPM_282:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(349) ); PPM_283:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(365) ); PPM_284:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(381) ); PPM_285:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(396) ); PPM_286:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(411) ); PPM_287:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(425) ); PPM_288:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(439) ); PPM_289:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(452) ); PPM_290:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(465) ); PPM_291:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(477) ); PPM_292:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(489) ); PPM_293:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(500) ); PPM_294:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(511) ); PPM_295:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(521) ); PPM_296:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(530) ); SUMMAND(531) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(540) ); -- Begin partial product 9 -- Begin decoder block 10 DEC_9:DECODER -- Decoder of multiplier operand port map ( INA => OPB(17),INB => OPB(18),INC => OPB(19), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39) ); -- End decoder block 10 -- Begin partial product 10 PPL_9:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(108) ); RGATE_9:R_GATE port map ( INA => OPB(17),INB => OPB(18),INC => OPB(19), PPBIT => SUMMAND(109) ); PPM_297:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(119) ); PPM_298:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(129) ); PPM_299:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(141) ); PPM_300:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(152) ); PPM_301:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(165) ); PPM_302:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(177) ); PPM_303:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(191) ); PPM_304:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(204) ); PPM_305:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(219) ); PPM_306:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(233) ); PPM_307:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(249) ); PPM_308:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(264) ); PPM_309:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(281) ); PPM_310:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(297) ); PPM_311:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(315) ); PPM_312:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(333) ); PPM_313:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(350) ); PPM_314:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(366) ); PPM_315:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(382) ); PPM_316:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(397) ); PPM_317:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(412) ); PPM_318:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(426) ); PPM_319:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(440) ); PPM_320:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(453) ); PPM_321:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(466) ); PPM_322:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(478) ); PPM_323:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(490) ); PPM_324:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(501) ); PPM_325:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(512) ); PPM_326:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(522) ); PPM_327:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(532) ); PPM_328:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(541) ); PPM_329:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(549) ); SUMMAND(550) <= LOGIC_ONE; PPH_9:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(558) ); -- Begin partial product 10 -- Begin decoder block 11 DEC_10:DECODER -- Decoder of multiplier operand port map ( INA => OPB(19),INB => OPB(20),INC => OPB(21), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43) ); -- End decoder block 11 -- Begin partial product 11 PPL_10:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(130) ); RGATE_10:R_GATE port map ( INA => OPB(19),INB => OPB(20),INC => OPB(21), PPBIT => SUMMAND(131) ); PPM_330:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(142) ); PPM_331:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(153) ); PPM_332:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(166) ); PPM_333:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(178) ); PPM_334:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(192) ); PPM_335:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(205) ); PPM_336:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(220) ); PPM_337:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(234) ); PPM_338:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(250) ); PPM_339:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(265) ); PPM_340:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(282) ); PPM_341:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(298) ); PPM_342:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(316) ); PPM_343:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(334) ); PPM_344:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(351) ); PPM_345:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(367) ); PPM_346:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(383) ); PPM_347:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(398) ); PPM_348:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(413) ); PPM_349:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(427) ); PPM_350:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(441) ); PPM_351:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(454) ); PPM_352:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(467) ); PPM_353:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(479) ); PPM_354:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(491) ); PPM_355:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(502) ); PPM_356:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(513) ); PPM_357:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(523) ); PPM_358:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(533) ); PPM_359:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(542) ); PPM_360:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(551) ); PPM_361:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(559) ); PPM_362:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(566) ); SUMMAND(567) <= LOGIC_ONE; PPH_10:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(574) ); -- Begin partial product 11 -- Begin decoder block 12 DEC_11:DECODER -- Decoder of multiplier operand port map ( INA => OPB(21),INB => OPB(22),INC => OPB(23), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47) ); -- End decoder block 12 -- Begin partial product 12 PPL_11:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(154) ); RGATE_11:R_GATE port map ( INA => OPB(21),INB => OPB(22),INC => OPB(23), PPBIT => SUMMAND(155) ); PPM_363:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(167) ); PPM_364:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(179) ); PPM_365:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(193) ); PPM_366:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(206) ); PPM_367:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(221) ); PPM_368:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(235) ); PPM_369:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(251) ); PPM_370:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(266) ); PPM_371:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(283) ); PPM_372:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(299) ); PPM_373:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(317) ); PPM_374:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(335) ); PPM_375:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(352) ); PPM_376:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(368) ); PPM_377:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(384) ); PPM_378:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(399) ); PPM_379:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(414) ); PPM_380:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(428) ); PPM_381:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(442) ); PPM_382:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(455) ); PPM_383:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(468) ); PPM_384:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(480) ); PPM_385:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(492) ); PPM_386:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(503) ); PPM_387:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(514) ); PPM_388:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(524) ); PPM_389:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(534) ); PPM_390:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(543) ); PPM_391:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(552) ); PPM_392:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(560) ); PPM_393:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(568) ); PPM_394:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(575) ); PPM_395:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(581) ); SUMMAND(582) <= LOGIC_ONE; PPH_11:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(588) ); -- Begin partial product 12 -- Begin decoder block 13 DEC_12:DECODER -- Decoder of multiplier operand port map ( INA => OPB(23),INB => OPB(24),INC => OPB(25), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51) ); -- End decoder block 13 -- Begin partial product 13 PPL_12:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(180) ); RGATE_12:R_GATE port map ( INA => OPB(23),INB => OPB(24),INC => OPB(25), PPBIT => SUMMAND(181) ); PPM_396:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(194) ); PPM_397:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(207) ); PPM_398:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(222) ); PPM_399:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(236) ); PPM_400:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(252) ); PPM_401:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(267) ); PPM_402:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(284) ); PPM_403:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(300) ); PPM_404:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(318) ); PPM_405:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(336) ); PPM_406:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(353) ); PPM_407:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(369) ); PPM_408:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(385) ); PPM_409:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(400) ); PPM_410:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(415) ); PPM_411:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(429) ); PPM_412:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(443) ); PPM_413:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(456) ); PPM_414:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(469) ); PPM_415:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(481) ); PPM_416:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(493) ); PPM_417:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(504) ); PPM_418:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(515) ); PPM_419:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(525) ); PPM_420:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(535) ); PPM_421:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(544) ); PPM_422:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(553) ); PPM_423:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(561) ); PPM_424:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(569) ); PPM_425:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(576) ); PPM_426:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(583) ); PPM_427:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(589) ); PPM_428:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(594) ); SUMMAND(595) <= LOGIC_ONE; PPH_12:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(600) ); -- Begin partial product 13 -- Begin decoder block 14 DEC_13:DECODER -- Decoder of multiplier operand port map ( INA => OPB(25),INB => OPB(26),INC => OPB(27), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55) ); -- End decoder block 14 -- Begin partial product 14 PPL_13:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(208) ); RGATE_13:R_GATE port map ( INA => OPB(25),INB => OPB(26),INC => OPB(27), PPBIT => SUMMAND(209) ); PPM_429:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(223) ); PPM_430:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(237) ); PPM_431:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(253) ); PPM_432:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(268) ); PPM_433:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(285) ); PPM_434:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(301) ); PPM_435:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(319) ); PPM_436:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(337) ); PPM_437:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(354) ); PPM_438:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(370) ); PPM_439:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(386) ); PPM_440:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(401) ); PPM_441:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(416) ); PPM_442:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(430) ); PPM_443:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(444) ); PPM_444:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(457) ); PPM_445:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(470) ); PPM_446:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(482) ); PPM_447:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(494) ); PPM_448:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(505) ); PPM_449:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(516) ); PPM_450:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(526) ); PPM_451:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(536) ); PPM_452:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(545) ); PPM_453:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(554) ); PPM_454:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(562) ); PPM_455:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(570) ); PPM_456:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(577) ); PPM_457:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(584) ); PPM_458:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(590) ); PPM_459:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(596) ); PPM_460:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(601) ); PPM_461:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(605) ); SUMMAND(606) <= LOGIC_ONE; PPH_13:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(610) ); -- Begin partial product 14 -- Begin decoder block 15 DEC_14:DECODER -- Decoder of multiplier operand port map ( INA => OPB(27),INB => OPB(28),INC => OPB(29), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59) ); -- End decoder block 15 -- Begin partial product 15 PPL_14:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(238) ); RGATE_14:R_GATE port map ( INA => OPB(27),INB => OPB(28),INC => OPB(29), PPBIT => SUMMAND(239) ); PPM_462:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(254) ); PPM_463:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(269) ); PPM_464:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(286) ); PPM_465:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(302) ); PPM_466:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(320) ); PPM_467:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(338) ); PPM_468:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(355) ); PPM_469:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(371) ); PPM_470:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(387) ); PPM_471:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(402) ); PPM_472:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(417) ); PPM_473:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(431) ); PPM_474:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(445) ); PPM_475:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(458) ); PPM_476:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(471) ); PPM_477:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(483) ); PPM_478:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(495) ); PPM_479:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(506) ); PPM_480:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(517) ); PPM_481:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(527) ); PPM_482:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(537) ); PPM_483:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(546) ); PPM_484:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(555) ); PPM_485:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(563) ); PPM_486:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(571) ); PPM_487:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(578) ); PPM_488:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(585) ); PPM_489:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(591) ); PPM_490:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(597) ); PPM_491:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(602) ); PPM_492:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(607) ); PPM_493:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(611) ); PPM_494:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(614) ); SUMMAND(615) <= LOGIC_ONE; PPH_14:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(618) ); -- Begin partial product 15 -- Begin decoder block 16 DEC_15:DECODER -- Decoder of multiplier operand port map ( INA => OPB(29),INB => OPB(30),INC => OPB(31), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63) ); -- End decoder block 16 -- Begin partial product 16 PPL_15:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(270) ); RGATE_15:R_GATE port map ( INA => OPB(29),INB => OPB(30),INC => OPB(31), PPBIT => SUMMAND(271) ); PPM_495:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(287) ); PPM_496:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(303) ); PPM_497:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(321) ); PPM_498:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(339) ); PPM_499:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(356) ); PPM_500:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(372) ); PPM_501:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(388) ); PPM_502:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(403) ); PPM_503:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(418) ); PPM_504:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(432) ); PPM_505:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(446) ); PPM_506:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(459) ); PPM_507:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(472) ); PPM_508:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(484) ); PPM_509:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(496) ); PPM_510:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(507) ); PPM_511:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(518) ); PPM_512:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(528) ); PPM_513:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(538) ); PPM_514:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(547) ); PPM_515:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(556) ); PPM_516:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(564) ); PPM_517:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(572) ); PPM_518:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(579) ); PPM_519:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(586) ); PPM_520:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(592) ); PPM_521:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(598) ); PPM_522:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(603) ); PPM_523:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(608) ); PPM_524:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(612) ); PPM_525:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(616) ); PPM_526:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(619) ); PPM_527:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(621) ); SUMMAND(622) <= LOGIC_ONE; PPH_15:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(624) ); -- Begin partial product 16 -- Begin decoder block 17 DEC_16:DECODER -- Decoder of multiplier operand port map ( INA => OPB(31),INB => OPB(32),INC => OPB(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67) ); -- End decoder block 17 -- Begin partial product 17 PPL_16:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(304) ); RGATE_16:R_GATE port map ( INA => OPB(31),INB => OPB(32),INC => OPB(33), PPBIT => SUMMAND(305) ); PPM_528:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(322) ); PPM_529:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(340) ); PPM_530:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(357) ); PPM_531:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(373) ); PPM_532:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(389) ); PPM_533:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(404) ); PPM_534:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(419) ); PPM_535:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(433) ); PPM_536:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(447) ); PPM_537:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(460) ); PPM_538:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(473) ); PPM_539:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(485) ); PPM_540:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(497) ); PPM_541:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(508) ); PPM_542:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(519) ); PPM_543:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(529) ); PPM_544:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(539) ); PPM_545:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(548) ); PPM_546:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(557) ); PPM_547:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(565) ); PPM_548:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(573) ); PPM_549:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(580) ); PPM_550:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(587) ); PPM_551:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(593) ); PPM_552:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(599) ); PPM_553:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(604) ); PPM_554:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(609) ); PPM_555:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(613) ); PPM_556:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(617) ); PPM_557:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(620) ); PPM_558:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(623) ); PPM_559:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(625) ); PPM_560:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(626) ); SUMMAND(627) <= LOGIC_ONE; PPH_16:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(628) ); -- Begin partial product 17 end BOOTHCODER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_34 is port ( SUMMAND: in std_logic_vector(0 to 628); CARRY: out std_logic_vector(0 to 65); SUM: out std_logic_vector(0 to 66) ); end WALLACE_34_34; architecture WALLACE of WALLACE_34_34 is -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 486); signal INT_SUM: std_logic_vector(0 to 620); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin NO stage INT_SUM(76) <= SUMMAND(108); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(77) <= SUMMAND(109); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(78), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(49), SAVE => INT_SUM(79), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin NO stage INT_SUM(80) <= INT_CARRY(50); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(81) <= INT_CARRY(51); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_SUM(80), SAVE => INT_SUM(82), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(81), DATA_B => INT_CARRY(52), DATA_C => INT_CARRY(53), SAVE => INT_SUM(83), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin FA stage FA_64:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(54), SAVE => INT_SUM(84), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(84), DATA_B => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End HA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_65:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112), SAVE => INT_SUM(85), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), DATA_C => SUMMAND(115), SAVE => INT_SUM(86), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(116), DATA_B => SUMMAND(117), DATA_C => SUMMAND(118), SAVE => INT_SUM(87), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin NO stage INT_SUM(88) <= SUMMAND(119); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(56), DATA_C => INT_CARRY(57), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(91) <= INT_CARRY(58); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91), SAVE => INT_SUM(92), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(59), DATA_B => INT_CARRY(60), SAVE => INT_SUM(93), CARRY => INT_CARRY(70) ); ---- End HA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(61), SAVE => INT_SUM(94), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(62); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(63), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End FA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125), SAVE => INT_SUM(97), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(98), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(99), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_SUM(98), SAVE => INT_SUM(100), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(99), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65), SAVE => INT_SUM(101), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin NO stage INT_SUM(102) <= INT_CARRY(66); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_79:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_SUM(102), SAVE => INT_SUM(103), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(67), DATA_B => INT_CARRY(68), SAVE => INT_SUM(104), CARRY => INT_CARRY(79) ); ---- End HA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(103), DATA_B => INT_SUM(104), DATA_C => INT_CARRY(69), SAVE => INT_SUM(105), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin NO stage INT_SUM(106) <= INT_CARRY(70); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_CARRY(71), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_82:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134), SAVE => INT_SUM(107), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(108), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140), SAVE => INT_SUM(109), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(110) <= SUMMAND(141); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(111) <= SUMMAND(142); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_85:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(107), DATA_B => INT_SUM(108), DATA_C => INT_SUM(109), SAVE => INT_SUM(112), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(72), SAVE => INT_SUM(113), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(73), DATA_B => INT_CARRY(74), DATA_C => INT_CARRY(75), SAVE => INT_SUM(114), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_SUM(114), SAVE => INT_SUM(115), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), SAVE => INT_SUM(116), CARRY => INT_CARRY(88) ); ---- End HA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(78), SAVE => INT_SUM(117), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(118) <= INT_CARRY(79); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_CARRY(80), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_91:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), DATA_C => SUMMAND(145), SAVE => INT_SUM(119), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(146), DATA_B => SUMMAND(147), DATA_C => SUMMAND(148), SAVE => INT_SUM(120), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(149), DATA_B => SUMMAND(150), DATA_C => SUMMAND(151), SAVE => INT_SUM(121), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(152), DATA_B => SUMMAND(153), DATA_C => SUMMAND(154), SAVE => INT_SUM(122), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= SUMMAND(155); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(119), DATA_B => INT_SUM(120), DATA_C => INT_SUM(121), SAVE => INT_SUM(124), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(81), SAVE => INT_SUM(125), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83), SAVE => INT_SUM(126), CARRY => INT_CARRY(96) ); ---- End HA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_SUM(126), SAVE => INT_SUM(127), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86), SAVE => INT_SUM(128), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin FA stage FA_99:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(127), DATA_B => INT_SUM(128), DATA_C => INT_CARRY(87), SAVE => INT_SUM(129), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin NO stage INT_SUM(130) <= INT_CARRY(88); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_CARRY(89), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_101:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158), SAVE => INT_SUM(131), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161), SAVE => INT_SUM(132), CARRY => INT_CARRY(101) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164), SAVE => INT_SUM(133), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(134), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin FA stage FA_105:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(131), DATA_B => INT_SUM(132), DATA_C => INT_SUM(133), SAVE => INT_SUM(135), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin FA stage FA_106:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(134), DATA_B => INT_CARRY(90), DATA_C => INT_CARRY(91), SAVE => INT_SUM(136), CARRY => INT_CARRY(105) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(92), DATA_B => INT_CARRY(93), SAVE => INT_SUM(137), CARRY => INT_CARRY(106) ); ---- End HA stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_SUM(137), SAVE => INT_SUM(138), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin FA stage FA_108:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(94), DATA_B => INT_CARRY(95), DATA_C => INT_CARRY(96), SAVE => INT_SUM(139), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(138), DATA_B => INT_SUM(139), DATA_C => INT_CARRY(97), SAVE => INT_SUM(140), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin NO stage INT_SUM(141) <= INT_CARRY(98); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(99), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_111:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170), SAVE => INT_SUM(142), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173), SAVE => INT_SUM(143), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin FA stage FA_113:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(144), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin FA stage FA_114:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(145), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), SAVE => INT_SUM(146), CARRY => INT_CARRY(114) ); ---- End HA stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_SUM(144), SAVE => INT_SUM(147), CARRY => INT_CARRY(115) ); ---- End FA stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(100), SAVE => INT_SUM(148), CARRY => INT_CARRY(116) ); ---- End FA stage ---- Begin FA stage FA_117:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(101), DATA_B => INT_CARRY(102), DATA_C => INT_CARRY(103), SAVE => INT_SUM(149), CARRY => INT_CARRY(117) ); ---- End FA stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(147), DATA_B => INT_SUM(148), DATA_C => INT_SUM(149), SAVE => INT_SUM(150), CARRY => INT_CARRY(118) ); ---- End FA stage ---- Begin FA stage FA_119:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(104), DATA_B => INT_CARRY(105), DATA_C => INT_CARRY(106), SAVE => INT_SUM(151), CARRY => INT_CARRY(119) ); ---- End FA stage ---- Begin FA stage FA_120:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(107), SAVE => INT_SUM(152), CARRY => INT_CARRY(120) ); ---- End FA stage ---- Begin NO stage INT_SUM(153) <= INT_CARRY(108); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_121:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(152), DATA_B => INT_SUM(153), DATA_C => INT_CARRY(109), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_122:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), DATA_C => SUMMAND(184), SAVE => INT_SUM(154), CARRY => INT_CARRY(121) ); ---- End FA stage ---- Begin FA stage FA_123:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(185), DATA_B => SUMMAND(186), DATA_C => SUMMAND(187), SAVE => INT_SUM(155), CARRY => INT_CARRY(122) ); ---- End FA stage ---- Begin FA stage FA_124:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(188), DATA_B => SUMMAND(189), DATA_C => SUMMAND(190), SAVE => INT_SUM(156), CARRY => INT_CARRY(123) ); ---- End FA stage ---- Begin FA stage FA_125:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(191), DATA_B => SUMMAND(192), DATA_C => SUMMAND(193), SAVE => INT_SUM(157), CARRY => INT_CARRY(124) ); ---- End FA stage ---- Begin NO stage INT_SUM(158) <= SUMMAND(194); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_126:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(154), DATA_B => INT_SUM(155), DATA_C => INT_SUM(156), SAVE => INT_SUM(159), CARRY => INT_CARRY(125) ); ---- End FA stage ---- Begin FA stage FA_127:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(110), SAVE => INT_SUM(160), CARRY => INT_CARRY(126) ); ---- End FA stage ---- Begin FA stage FA_128:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(111), DATA_B => INT_CARRY(112), DATA_C => INT_CARRY(113), SAVE => INT_SUM(161), CARRY => INT_CARRY(127) ); ---- End FA stage ---- Begin NO stage INT_SUM(162) <= INT_CARRY(114); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_129:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(159), DATA_B => INT_SUM(160), DATA_C => INT_SUM(161), SAVE => INT_SUM(163), CARRY => INT_CARRY(128) ); ---- End FA stage ---- Begin FA stage FA_130:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(162), DATA_B => INT_CARRY(115), DATA_C => INT_CARRY(116), SAVE => INT_SUM(164), CARRY => INT_CARRY(129) ); ---- End FA stage ---- Begin NO stage INT_SUM(165) <= INT_CARRY(117); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_131:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(163), DATA_B => INT_SUM(164), DATA_C => INT_SUM(165), SAVE => INT_SUM(166), CARRY => INT_CARRY(130) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(118), DATA_B => INT_CARRY(119), SAVE => INT_SUM(167), CARRY => INT_CARRY(131) ); ---- End HA stage ---- Begin FA stage FA_132:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(120), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End FA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_133:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197), SAVE => INT_SUM(168), CARRY => INT_CARRY(132) ); ---- End FA stage ---- Begin FA stage FA_134:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200), SAVE => INT_SUM(169), CARRY => INT_CARRY(133) ); ---- End FA stage ---- Begin FA stage FA_135:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203), SAVE => INT_SUM(170), CARRY => INT_CARRY(134) ); ---- End FA stage ---- Begin FA stage FA_136:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206), SAVE => INT_SUM(171), CARRY => INT_CARRY(135) ); ---- End FA stage ---- Begin FA stage FA_137:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209), SAVE => INT_SUM(172), CARRY => INT_CARRY(136) ); ---- End FA stage ---- Begin FA stage FA_138:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(168), DATA_B => INT_SUM(169), DATA_C => INT_SUM(170), SAVE => INT_SUM(173), CARRY => INT_CARRY(137) ); ---- End FA stage ---- Begin FA stage FA_139:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(171), DATA_B => INT_SUM(172), DATA_C => INT_CARRY(121), SAVE => INT_SUM(174), CARRY => INT_CARRY(138) ); ---- End FA stage ---- Begin FA stage FA_140:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(122), DATA_B => INT_CARRY(123), DATA_C => INT_CARRY(124), SAVE => INT_SUM(175), CARRY => INT_CARRY(139) ); ---- End FA stage ---- Begin FA stage FA_141:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(173), DATA_B => INT_SUM(174), DATA_C => INT_SUM(175), SAVE => INT_SUM(176), CARRY => INT_CARRY(140) ); ---- End FA stage ---- Begin FA stage FA_142:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(125), DATA_B => INT_CARRY(126), DATA_C => INT_CARRY(127), SAVE => INT_SUM(177), CARRY => INT_CARRY(141) ); ---- End FA stage ---- Begin FA stage FA_143:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(176), DATA_B => INT_SUM(177), DATA_C => INT_CARRY(128), SAVE => INT_SUM(178), CARRY => INT_CARRY(142) ); ---- End FA stage ---- Begin NO stage INT_SUM(179) <= INT_CARRY(129); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_144:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(178), DATA_B => INT_SUM(179), DATA_C => INT_CARRY(130), SAVE => INT_SUM(180), CARRY => INT_CARRY(143) ); ---- End FA stage ---- Begin NO stage INT_SUM(181) <= INT_CARRY(131); -- At Level 5 ---- End NO stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_145:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212), SAVE => INT_SUM(182), CARRY => INT_CARRY(144) ); ---- End FA stage ---- Begin FA stage FA_146:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215), SAVE => INT_SUM(183), CARRY => INT_CARRY(145) ); ---- End FA stage ---- Begin FA stage FA_147:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218), SAVE => INT_SUM(184), CARRY => INT_CARRY(146) ); ---- End FA stage ---- Begin FA stage FA_148:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221), SAVE => INT_SUM(185), CARRY => INT_CARRY(147) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), SAVE => INT_SUM(186), CARRY => INT_CARRY(148) ); ---- End HA stage ---- Begin FA stage FA_149:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_SUM(184), SAVE => INT_SUM(187), CARRY => INT_CARRY(149) ); ---- End FA stage ---- Begin FA stage FA_150:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_CARRY(132), SAVE => INT_SUM(188), CARRY => INT_CARRY(150) ); ---- End FA stage ---- Begin FA stage FA_151:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135), SAVE => INT_SUM(189), CARRY => INT_CARRY(151) ); ---- End FA stage ---- Begin NO stage INT_SUM(190) <= INT_CARRY(136); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_152:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(187), DATA_B => INT_SUM(188), DATA_C => INT_SUM(189), SAVE => INT_SUM(191), CARRY => INT_CARRY(152) ); ---- End FA stage ---- Begin FA stage FA_153:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(190), DATA_B => INT_CARRY(137), DATA_C => INT_CARRY(138), SAVE => INT_SUM(192), CARRY => INT_CARRY(153) ); ---- End FA stage ---- Begin NO stage INT_SUM(193) <= INT_CARRY(139); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_154:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(191), DATA_B => INT_SUM(192), DATA_C => INT_SUM(193), SAVE => INT_SUM(194), CARRY => INT_CARRY(154) ); ---- End FA stage ---- Begin NO stage INT_SUM(195) <= INT_CARRY(140); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(196) <= INT_CARRY(141); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_155:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(194), DATA_B => INT_SUM(195), DATA_C => INT_SUM(196), SAVE => INT_SUM(197), CARRY => INT_CARRY(155) ); ---- End FA stage ---- Begin NO stage INT_SUM(198) <= INT_CARRY(142); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_156:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(197), DATA_B => INT_SUM(198), DATA_C => INT_CARRY(143), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End FA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_157:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(224), DATA_B => SUMMAND(225), DATA_C => SUMMAND(226), SAVE => INT_SUM(199), CARRY => INT_CARRY(156) ); ---- End FA stage ---- Begin FA stage FA_158:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(227), DATA_B => SUMMAND(228), DATA_C => SUMMAND(229), SAVE => INT_SUM(200), CARRY => INT_CARRY(157) ); ---- End FA stage ---- Begin FA stage FA_159:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(230), DATA_B => SUMMAND(231), DATA_C => SUMMAND(232), SAVE => INT_SUM(201), CARRY => INT_CARRY(158) ); ---- End FA stage ---- Begin FA stage FA_160:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(233), DATA_B => SUMMAND(234), DATA_C => SUMMAND(235), SAVE => INT_SUM(202), CARRY => INT_CARRY(159) ); ---- End FA stage ---- Begin FA stage FA_161:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(236), DATA_B => SUMMAND(237), DATA_C => SUMMAND(238), SAVE => INT_SUM(203), CARRY => INT_CARRY(160) ); ---- End FA stage ---- Begin NO stage INT_SUM(204) <= SUMMAND(239); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_162:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(199), DATA_B => INT_SUM(200), DATA_C => INT_SUM(201), SAVE => INT_SUM(205), CARRY => INT_CARRY(161) ); ---- End FA stage ---- Begin FA stage FA_163:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(202), DATA_B => INT_SUM(203), DATA_C => INT_SUM(204), SAVE => INT_SUM(206), CARRY => INT_CARRY(162) ); ---- End FA stage ---- Begin FA stage FA_164:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(144), DATA_B => INT_CARRY(145), DATA_C => INT_CARRY(146), SAVE => INT_SUM(207), CARRY => INT_CARRY(163) ); ---- End FA stage ---- Begin NO stage INT_SUM(208) <= INT_CARRY(147); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(209) <= INT_CARRY(148); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_165:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207), SAVE => INT_SUM(210), CARRY => INT_CARRY(164) ); ---- End FA stage ---- Begin FA stage FA_166:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_CARRY(149), SAVE => INT_SUM(211), CARRY => INT_CARRY(165) ); ---- End FA stage ---- Begin NO stage INT_SUM(212) <= INT_CARRY(150); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(213) <= INT_CARRY(151); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_167:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(210), DATA_B => INT_SUM(211), DATA_C => INT_SUM(212), SAVE => INT_SUM(214), CARRY => INT_CARRY(166) ); ---- End FA stage ---- Begin FA stage FA_168:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(213), DATA_B => INT_CARRY(152), DATA_C => INT_CARRY(153), SAVE => INT_SUM(215), CARRY => INT_CARRY(167) ); ---- End FA stage ---- Begin FA stage FA_169:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(214), DATA_B => INT_SUM(215), DATA_C => INT_CARRY(154), SAVE => INT_SUM(216), CARRY => INT_CARRY(168) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(216), DATA_B => INT_CARRY(155), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_170:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242), SAVE => INT_SUM(217), CARRY => INT_CARRY(169) ); ---- End FA stage ---- Begin FA stage FA_171:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245), SAVE => INT_SUM(218), CARRY => INT_CARRY(170) ); ---- End FA stage ---- Begin FA stage FA_172:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248), SAVE => INT_SUM(219), CARRY => INT_CARRY(171) ); ---- End FA stage ---- Begin FA stage FA_173:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251), SAVE => INT_SUM(220), CARRY => INT_CARRY(172) ); ---- End FA stage ---- Begin FA stage FA_174:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(252), DATA_B => SUMMAND(253), DATA_C => SUMMAND(254), SAVE => INT_SUM(221), CARRY => INT_CARRY(173) ); ---- End FA stage ---- Begin FA stage FA_175:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_SUM(219), SAVE => INT_SUM(222), CARRY => INT_CARRY(174) ); ---- End FA stage ---- Begin FA stage FA_176:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_CARRY(156), SAVE => INT_SUM(223), CARRY => INT_CARRY(175) ); ---- End FA stage ---- Begin FA stage FA_177:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(157), DATA_B => INT_CARRY(158), DATA_C => INT_CARRY(159), SAVE => INT_SUM(224), CARRY => INT_CARRY(176) ); ---- End FA stage ---- Begin NO stage INT_SUM(225) <= INT_CARRY(160); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_178:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(222), DATA_B => INT_SUM(223), DATA_C => INT_SUM(224), SAVE => INT_SUM(226), CARRY => INT_CARRY(177) ); ---- End FA stage ---- Begin FA stage FA_179:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(225), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162), SAVE => INT_SUM(227), CARRY => INT_CARRY(178) ); ---- End FA stage ---- Begin NO stage INT_SUM(228) <= INT_CARRY(163); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_180:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_SUM(228), SAVE => INT_SUM(229), CARRY => INT_CARRY(179) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(164), DATA_B => INT_CARRY(165), SAVE => INT_SUM(230), CARRY => INT_CARRY(180) ); ---- End HA stage ---- Begin FA stage FA_181:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(229), DATA_B => INT_SUM(230), DATA_C => INT_CARRY(166), SAVE => INT_SUM(231), CARRY => INT_CARRY(181) ); ---- End FA stage ---- Begin NO stage INT_SUM(232) <= INT_CARRY(167); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_182:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(231), DATA_B => INT_SUM(232), DATA_C => INT_CARRY(168), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_183:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(255), DATA_B => SUMMAND(256), DATA_C => SUMMAND(257), SAVE => INT_SUM(233), CARRY => INT_CARRY(182) ); ---- End FA stage ---- Begin FA stage FA_184:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(258), DATA_B => SUMMAND(259), DATA_C => SUMMAND(260), SAVE => INT_SUM(234), CARRY => INT_CARRY(183) ); ---- End FA stage ---- Begin FA stage FA_185:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(261), DATA_B => SUMMAND(262), DATA_C => SUMMAND(263), SAVE => INT_SUM(235), CARRY => INT_CARRY(184) ); ---- End FA stage ---- Begin FA stage FA_186:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(264), DATA_B => SUMMAND(265), DATA_C => SUMMAND(266), SAVE => INT_SUM(236), CARRY => INT_CARRY(185) ); ---- End FA stage ---- Begin FA stage FA_187:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(267), DATA_B => SUMMAND(268), DATA_C => SUMMAND(269), SAVE => INT_SUM(237), CARRY => INT_CARRY(186) ); ---- End FA stage ---- Begin NO stage INT_SUM(238) <= SUMMAND(270); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(239) <= SUMMAND(271); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_188:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(233), DATA_B => INT_SUM(234), DATA_C => INT_SUM(235), SAVE => INT_SUM(240), CARRY => INT_CARRY(187) ); ---- End FA stage ---- Begin FA stage FA_189:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_SUM(238), SAVE => INT_SUM(241), CARRY => INT_CARRY(188) ); ---- End FA stage ---- Begin FA stage FA_190:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(239), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170), SAVE => INT_SUM(242), CARRY => INT_CARRY(189) ); ---- End FA stage ---- Begin FA stage FA_191:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(171), DATA_B => INT_CARRY(172), DATA_C => INT_CARRY(173), SAVE => INT_SUM(243), CARRY => INT_CARRY(190) ); ---- End FA stage ---- Begin FA stage FA_192:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(240), DATA_B => INT_SUM(241), DATA_C => INT_SUM(242), SAVE => INT_SUM(244), CARRY => INT_CARRY(191) ); ---- End FA stage ---- Begin FA stage FA_193:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(243), DATA_B => INT_CARRY(174), DATA_C => INT_CARRY(175), SAVE => INT_SUM(245), CARRY => INT_CARRY(192) ); ---- End FA stage ---- Begin NO stage INT_SUM(246) <= INT_CARRY(176); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_194:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(244), DATA_B => INT_SUM(245), DATA_C => INT_SUM(246), SAVE => INT_SUM(247), CARRY => INT_CARRY(193) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(177), DATA_B => INT_CARRY(178), SAVE => INT_SUM(248), CARRY => INT_CARRY(194) ); ---- End HA stage ---- Begin FA stage FA_195:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(247), DATA_B => INT_SUM(248), DATA_C => INT_CARRY(179), SAVE => INT_SUM(249), CARRY => INT_CARRY(195) ); ---- End FA stage ---- Begin NO stage INT_SUM(250) <= INT_CARRY(180); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_196:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(249), DATA_B => INT_SUM(250), DATA_C => INT_CARRY(181), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_197:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(272), DATA_B => SUMMAND(273), DATA_C => SUMMAND(274), SAVE => INT_SUM(251), CARRY => INT_CARRY(196) ); ---- End FA stage ---- Begin FA stage FA_198:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(275), DATA_B => SUMMAND(276), DATA_C => SUMMAND(277), SAVE => INT_SUM(252), CARRY => INT_CARRY(197) ); ---- End FA stage ---- Begin FA stage FA_199:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280), SAVE => INT_SUM(253), CARRY => INT_CARRY(198) ); ---- End FA stage ---- Begin FA stage FA_200:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283), SAVE => INT_SUM(254), CARRY => INT_CARRY(199) ); ---- End FA stage ---- Begin FA stage FA_201:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(284), DATA_B => SUMMAND(285), DATA_C => SUMMAND(286), SAVE => INT_SUM(255), CARRY => INT_CARRY(200) ); ---- End FA stage ---- Begin NO stage INT_SUM(256) <= SUMMAND(287); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_202:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(251), DATA_B => INT_SUM(252), DATA_C => INT_SUM(253), SAVE => INT_SUM(257), CARRY => INT_CARRY(201) ); ---- End FA stage ---- Begin FA stage FA_203:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_SUM(256), SAVE => INT_SUM(258), CARRY => INT_CARRY(202) ); ---- End FA stage ---- Begin FA stage FA_204:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(182), DATA_B => INT_CARRY(183), DATA_C => INT_CARRY(184), SAVE => INT_SUM(259), CARRY => INT_CARRY(203) ); ---- End FA stage ---- Begin NO stage INT_SUM(260) <= INT_CARRY(185); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(261) <= INT_CARRY(186); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_205:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(257), DATA_B => INT_SUM(258), DATA_C => INT_SUM(259), SAVE => INT_SUM(262), CARRY => INT_CARRY(204) ); ---- End FA stage ---- Begin FA stage FA_206:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(187), SAVE => INT_SUM(263), CARRY => INT_CARRY(205) ); ---- End FA stage ---- Begin FA stage FA_207:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190), SAVE => INT_SUM(264), CARRY => INT_CARRY(206) ); ---- End FA stage ---- Begin FA stage FA_208:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(262), DATA_B => INT_SUM(263), DATA_C => INT_SUM(264), SAVE => INT_SUM(265), CARRY => INT_CARRY(207) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(191), DATA_B => INT_CARRY(192), SAVE => INT_SUM(266), CARRY => INT_CARRY(208) ); ---- End HA stage ---- Begin FA stage FA_209:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(193), SAVE => INT_SUM(267), CARRY => INT_CARRY(209) ); ---- End FA stage ---- Begin NO stage INT_SUM(268) <= INT_CARRY(194); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_210:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(267), DATA_B => INT_SUM(268), DATA_C => INT_CARRY(195), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End FA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_211:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290), SAVE => INT_SUM(269), CARRY => INT_CARRY(210) ); ---- End FA stage ---- Begin FA stage FA_212:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(291), DATA_B => SUMMAND(292), DATA_C => SUMMAND(293), SAVE => INT_SUM(270), CARRY => INT_CARRY(211) ); ---- End FA stage ---- Begin FA stage FA_213:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(294), DATA_B => SUMMAND(295), DATA_C => SUMMAND(296), SAVE => INT_SUM(271), CARRY => INT_CARRY(212) ); ---- End FA stage ---- Begin FA stage FA_214:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(297), DATA_B => SUMMAND(298), DATA_C => SUMMAND(299), SAVE => INT_SUM(272), CARRY => INT_CARRY(213) ); ---- End FA stage ---- Begin FA stage FA_215:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(300), DATA_B => SUMMAND(301), DATA_C => SUMMAND(302), SAVE => INT_SUM(273), CARRY => INT_CARRY(214) ); ---- End FA stage ---- Begin FA stage FA_216:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(303), DATA_B => SUMMAND(304), DATA_C => SUMMAND(305), SAVE => INT_SUM(274), CARRY => INT_CARRY(215) ); ---- End FA stage ---- Begin FA stage FA_217:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(269), DATA_B => INT_SUM(270), DATA_C => INT_SUM(271), SAVE => INT_SUM(275), CARRY => INT_CARRY(216) ); ---- End FA stage ---- Begin FA stage FA_218:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(272), DATA_B => INT_SUM(273), DATA_C => INT_SUM(274), SAVE => INT_SUM(276), CARRY => INT_CARRY(217) ); ---- End FA stage ---- Begin FA stage FA_219:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(196), DATA_B => INT_CARRY(197), DATA_C => INT_CARRY(198), SAVE => INT_SUM(277), CARRY => INT_CARRY(218) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(199), DATA_B => INT_CARRY(200), SAVE => INT_SUM(278), CARRY => INT_CARRY(219) ); ---- End HA stage ---- Begin FA stage FA_220:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(275), DATA_B => INT_SUM(276), DATA_C => INT_SUM(277), SAVE => INT_SUM(279), CARRY => INT_CARRY(220) ); ---- End FA stage ---- Begin FA stage FA_221:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(278), DATA_B => INT_CARRY(201), DATA_C => INT_CARRY(202), SAVE => INT_SUM(280), CARRY => INT_CARRY(221) ); ---- End FA stage ---- Begin NO stage INT_SUM(281) <= INT_CARRY(203); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_222:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(279), DATA_B => INT_SUM(280), DATA_C => INT_SUM(281), SAVE => INT_SUM(282), CARRY => INT_CARRY(222) ); ---- End FA stage ---- Begin FA stage FA_223:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(204), DATA_B => INT_CARRY(205), DATA_C => INT_CARRY(206), SAVE => INT_SUM(283), CARRY => INT_CARRY(223) ); ---- End FA stage ---- Begin FA stage FA_224:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(282), DATA_B => INT_SUM(283), DATA_C => INT_CARRY(207), SAVE => INT_SUM(284), CARRY => INT_CARRY(224) ); ---- End FA stage ---- Begin NO stage INT_SUM(285) <= INT_CARRY(208); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_225:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(284), DATA_B => INT_SUM(285), DATA_C => INT_CARRY(209), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_226:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(306), DATA_B => SUMMAND(307), DATA_C => SUMMAND(308), SAVE => INT_SUM(286), CARRY => INT_CARRY(225) ); ---- End FA stage ---- Begin FA stage FA_227:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311), SAVE => INT_SUM(287), CARRY => INT_CARRY(226) ); ---- End FA stage ---- Begin FA stage FA_228:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), DATA_C => SUMMAND(314), SAVE => INT_SUM(288), CARRY => INT_CARRY(227) ); ---- End FA stage ---- Begin FA stage FA_229:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(315), DATA_B => SUMMAND(316), DATA_C => SUMMAND(317), SAVE => INT_SUM(289), CARRY => INT_CARRY(228) ); ---- End FA stage ---- Begin FA stage FA_230:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320), SAVE => INT_SUM(290), CARRY => INT_CARRY(229) ); ---- End FA stage ---- Begin NO stage INT_SUM(291) <= SUMMAND(321); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(292) <= SUMMAND(322); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_231:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(286), DATA_B => INT_SUM(287), DATA_C => INT_SUM(288), SAVE => INT_SUM(293), CARRY => INT_CARRY(230) ); ---- End FA stage ---- Begin FA stage FA_232:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(289), DATA_B => INT_SUM(290), DATA_C => INT_SUM(291), SAVE => INT_SUM(294), CARRY => INT_CARRY(231) ); ---- End FA stage ---- Begin FA stage FA_233:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(292), DATA_B => INT_CARRY(210), DATA_C => INT_CARRY(211), SAVE => INT_SUM(295), CARRY => INT_CARRY(232) ); ---- End FA stage ---- Begin FA stage FA_234:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(212), DATA_B => INT_CARRY(213), DATA_C => INT_CARRY(214), SAVE => INT_SUM(296), CARRY => INT_CARRY(233) ); ---- End FA stage ---- Begin NO stage INT_SUM(297) <= INT_CARRY(215); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_235:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(293), DATA_B => INT_SUM(294), DATA_C => INT_SUM(295), SAVE => INT_SUM(298), CARRY => INT_CARRY(234) ); ---- End FA stage ---- Begin FA stage FA_236:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(296), DATA_B => INT_SUM(297), DATA_C => INT_CARRY(216), SAVE => INT_SUM(299), CARRY => INT_CARRY(235) ); ---- End FA stage ---- Begin FA stage FA_237:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(217), DATA_B => INT_CARRY(218), DATA_C => INT_CARRY(219), SAVE => INT_SUM(300), CARRY => INT_CARRY(236) ); ---- End FA stage ---- Begin FA stage FA_238:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(298), DATA_B => INT_SUM(299), DATA_C => INT_SUM(300), SAVE => INT_SUM(301), CARRY => INT_CARRY(237) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(220), DATA_B => INT_CARRY(221), SAVE => INT_SUM(302), CARRY => INT_CARRY(238) ); ---- End HA stage ---- Begin FA stage FA_239:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(301), DATA_B => INT_SUM(302), DATA_C => INT_CARRY(222), SAVE => INT_SUM(303), CARRY => INT_CARRY(239) ); ---- End FA stage ---- Begin NO stage INT_SUM(304) <= INT_CARRY(223); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_240:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(303), DATA_B => INT_SUM(304), DATA_C => INT_CARRY(224), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End FA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_241:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(323), DATA_B => SUMMAND(324), DATA_C => SUMMAND(325), SAVE => INT_SUM(305), CARRY => INT_CARRY(240) ); ---- End FA stage ---- Begin FA stage FA_242:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(326), DATA_B => SUMMAND(327), DATA_C => SUMMAND(328), SAVE => INT_SUM(306), CARRY => INT_CARRY(241) ); ---- End FA stage ---- Begin FA stage FA_243:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(329), DATA_B => SUMMAND(330), DATA_C => SUMMAND(331), SAVE => INT_SUM(307), CARRY => INT_CARRY(242) ); ---- End FA stage ---- Begin FA stage FA_244:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(332), DATA_B => SUMMAND(333), DATA_C => SUMMAND(334), SAVE => INT_SUM(308), CARRY => INT_CARRY(243) ); ---- End FA stage ---- Begin FA stage FA_245:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(335), DATA_B => SUMMAND(336), DATA_C => SUMMAND(337), SAVE => INT_SUM(309), CARRY => INT_CARRY(244) ); ---- End FA stage ---- Begin FA stage FA_246:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(338), DATA_B => SUMMAND(339), DATA_C => SUMMAND(340), SAVE => INT_SUM(310), CARRY => INT_CARRY(245) ); ---- End FA stage ---- Begin FA stage FA_247:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(305), DATA_B => INT_SUM(306), DATA_C => INT_SUM(307), SAVE => INT_SUM(311), CARRY => INT_CARRY(246) ); ---- End FA stage ---- Begin FA stage FA_248:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(308), DATA_B => INT_SUM(309), DATA_C => INT_SUM(310), SAVE => INT_SUM(312), CARRY => INT_CARRY(247) ); ---- End FA stage ---- Begin FA stage FA_249:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(225), DATA_B => INT_CARRY(226), DATA_C => INT_CARRY(227), SAVE => INT_SUM(313), CARRY => INT_CARRY(248) ); ---- End FA stage ---- Begin NO stage INT_SUM(314) <= INT_CARRY(228); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(315) <= INT_CARRY(229); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_250:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(311), DATA_B => INT_SUM(312), DATA_C => INT_SUM(313), SAVE => INT_SUM(316), CARRY => INT_CARRY(249) ); ---- End FA stage ---- Begin FA stage FA_251:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(314), DATA_B => INT_SUM(315), DATA_C => INT_CARRY(230), SAVE => INT_SUM(317), CARRY => INT_CARRY(250) ); ---- End FA stage ---- Begin FA stage FA_252:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(231), DATA_B => INT_CARRY(232), DATA_C => INT_CARRY(233), SAVE => INT_SUM(318), CARRY => INT_CARRY(251) ); ---- End FA stage ---- Begin FA stage FA_253:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(316), DATA_B => INT_SUM(317), DATA_C => INT_SUM(318), SAVE => INT_SUM(319), CARRY => INT_CARRY(252) ); ---- End FA stage ---- Begin FA stage FA_254:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(234), DATA_B => INT_CARRY(235), DATA_C => INT_CARRY(236), SAVE => INT_SUM(320), CARRY => INT_CARRY(253) ); ---- End FA stage ---- Begin FA stage FA_255:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(319), DATA_B => INT_SUM(320), DATA_C => INT_CARRY(237), SAVE => INT_SUM(321), CARRY => INT_CARRY(254) ); ---- End FA stage ---- Begin NO stage INT_SUM(322) <= INT_CARRY(238); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_256:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(321), DATA_B => INT_SUM(322), DATA_C => INT_CARRY(239), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_257:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(341), DATA_B => SUMMAND(342), DATA_C => SUMMAND(343), SAVE => INT_SUM(323), CARRY => INT_CARRY(255) ); ---- End FA stage ---- Begin FA stage FA_258:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(344), DATA_B => SUMMAND(345), DATA_C => SUMMAND(346), SAVE => INT_SUM(324), CARRY => INT_CARRY(256) ); ---- End FA stage ---- Begin FA stage FA_259:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(347), DATA_B => SUMMAND(348), DATA_C => SUMMAND(349), SAVE => INT_SUM(325), CARRY => INT_CARRY(257) ); ---- End FA stage ---- Begin FA stage FA_260:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(350), DATA_B => SUMMAND(351), DATA_C => SUMMAND(352), SAVE => INT_SUM(326), CARRY => INT_CARRY(258) ); ---- End FA stage ---- Begin FA stage FA_261:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(353), DATA_B => SUMMAND(354), DATA_C => SUMMAND(355), SAVE => INT_SUM(327), CARRY => INT_CARRY(259) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(356), DATA_B => SUMMAND(357), SAVE => INT_SUM(328), CARRY => INT_CARRY(260) ); ---- End HA stage ---- Begin FA stage FA_262:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(323), DATA_B => INT_SUM(324), DATA_C => INT_SUM(325), SAVE => INT_SUM(329), CARRY => INT_CARRY(261) ); ---- End FA stage ---- Begin FA stage FA_263:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(326), DATA_B => INT_SUM(327), DATA_C => INT_SUM(328), SAVE => INT_SUM(330), CARRY => INT_CARRY(262) ); ---- End FA stage ---- Begin FA stage FA_264:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(240), DATA_B => INT_CARRY(241), DATA_C => INT_CARRY(242), SAVE => INT_SUM(331), CARRY => INT_CARRY(263) ); ---- End FA stage ---- Begin FA stage FA_265:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(243), DATA_B => INT_CARRY(244), DATA_C => INT_CARRY(245), SAVE => INT_SUM(332), CARRY => INT_CARRY(264) ); ---- End FA stage ---- Begin FA stage FA_266:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(329), DATA_B => INT_SUM(330), DATA_C => INT_SUM(331), SAVE => INT_SUM(333), CARRY => INT_CARRY(265) ); ---- End FA stage ---- Begin FA stage FA_267:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(332), DATA_B => INT_CARRY(246), DATA_C => INT_CARRY(247), SAVE => INT_SUM(334), CARRY => INT_CARRY(266) ); ---- End FA stage ---- Begin NO stage INT_SUM(335) <= INT_CARRY(248); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_268:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(333), DATA_B => INT_SUM(334), DATA_C => INT_SUM(335), SAVE => INT_SUM(336), CARRY => INT_CARRY(267) ); ---- End FA stage ---- Begin FA stage FA_269:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(249), DATA_B => INT_CARRY(250), DATA_C => INT_CARRY(251), SAVE => INT_SUM(337), CARRY => INT_CARRY(268) ); ---- End FA stage ---- Begin FA stage FA_270:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(336), DATA_B => INT_SUM(337), DATA_C => INT_CARRY(252), SAVE => INT_SUM(338), CARRY => INT_CARRY(269) ); ---- End FA stage ---- Begin NO stage INT_SUM(339) <= INT_CARRY(253); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_271:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(338), DATA_B => INT_SUM(339), DATA_C => INT_CARRY(254), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End FA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_272:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(358), DATA_B => SUMMAND(359), DATA_C => SUMMAND(360), SAVE => INT_SUM(340), CARRY => INT_CARRY(270) ); ---- End FA stage ---- Begin FA stage FA_273:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(361), DATA_B => SUMMAND(362), DATA_C => SUMMAND(363), SAVE => INT_SUM(341), CARRY => INT_CARRY(271) ); ---- End FA stage ---- Begin FA stage FA_274:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(364), DATA_B => SUMMAND(365), DATA_C => SUMMAND(366), SAVE => INT_SUM(342), CARRY => INT_CARRY(272) ); ---- End FA stage ---- Begin FA stage FA_275:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(367), DATA_B => SUMMAND(368), DATA_C => SUMMAND(369), SAVE => INT_SUM(343), CARRY => INT_CARRY(273) ); ---- End FA stage ---- Begin FA stage FA_276:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(370), DATA_B => SUMMAND(371), DATA_C => SUMMAND(372), SAVE => INT_SUM(344), CARRY => INT_CARRY(274) ); ---- End FA stage ---- Begin NO stage INT_SUM(345) <= SUMMAND(373); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_277:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(340), DATA_B => INT_SUM(341), DATA_C => INT_SUM(342), SAVE => INT_SUM(346), CARRY => INT_CARRY(275) ); ---- End FA stage ---- Begin FA stage FA_278:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(343), DATA_B => INT_SUM(344), DATA_C => INT_SUM(345), SAVE => INT_SUM(347), CARRY => INT_CARRY(276) ); ---- End FA stage ---- Begin FA stage FA_279:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(255), DATA_B => INT_CARRY(256), DATA_C => INT_CARRY(257), SAVE => INT_SUM(348), CARRY => INT_CARRY(277) ); ---- End FA stage ---- Begin FA stage FA_280:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(258), DATA_B => INT_CARRY(259), DATA_C => INT_CARRY(260), SAVE => INT_SUM(349), CARRY => INT_CARRY(278) ); ---- End FA stage ---- Begin FA stage FA_281:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(346), DATA_B => INT_SUM(347), DATA_C => INT_SUM(348), SAVE => INT_SUM(350), CARRY => INT_CARRY(279) ); ---- End FA stage ---- Begin FA stage FA_282:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(349), DATA_B => INT_CARRY(261), DATA_C => INT_CARRY(262), SAVE => INT_SUM(351), CARRY => INT_CARRY(280) ); ---- End FA stage ---- Begin NO stage INT_SUM(352) <= INT_CARRY(263); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(353) <= INT_CARRY(264); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_283:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(350), DATA_B => INT_SUM(351), DATA_C => INT_SUM(352), SAVE => INT_SUM(354), CARRY => INT_CARRY(281) ); ---- End FA stage ---- Begin FA stage FA_284:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(353), DATA_B => INT_CARRY(265), DATA_C => INT_CARRY(266), SAVE => INT_SUM(355), CARRY => INT_CARRY(282) ); ---- End FA stage ---- Begin FA stage FA_285:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(354), DATA_B => INT_SUM(355), DATA_C => INT_CARRY(267), SAVE => INT_SUM(356), CARRY => INT_CARRY(283) ); ---- End FA stage ---- Begin NO stage INT_SUM(357) <= INT_CARRY(268); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_286:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(356), DATA_B => INT_SUM(357), DATA_C => INT_CARRY(269), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_287:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(374), DATA_B => SUMMAND(375), DATA_C => SUMMAND(376), SAVE => INT_SUM(358), CARRY => INT_CARRY(284) ); ---- End FA stage ---- Begin FA stage FA_288:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(377), DATA_B => SUMMAND(378), DATA_C => SUMMAND(379), SAVE => INT_SUM(359), CARRY => INT_CARRY(285) ); ---- End FA stage ---- Begin FA stage FA_289:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(380), DATA_B => SUMMAND(381), DATA_C => SUMMAND(382), SAVE => INT_SUM(360), CARRY => INT_CARRY(286) ); ---- End FA stage ---- Begin FA stage FA_290:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(383), DATA_B => SUMMAND(384), DATA_C => SUMMAND(385), SAVE => INT_SUM(361), CARRY => INT_CARRY(287) ); ---- End FA stage ---- Begin FA stage FA_291:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(386), DATA_B => SUMMAND(387), DATA_C => SUMMAND(388), SAVE => INT_SUM(362), CARRY => INT_CARRY(288) ); ---- End FA stage ---- Begin NO stage INT_SUM(363) <= SUMMAND(389); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_292:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(358), DATA_B => INT_SUM(359), DATA_C => INT_SUM(360), SAVE => INT_SUM(364), CARRY => INT_CARRY(289) ); ---- End FA stage ---- Begin FA stage FA_293:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(361), DATA_B => INT_SUM(362), DATA_C => INT_SUM(363), SAVE => INT_SUM(365), CARRY => INT_CARRY(290) ); ---- End FA stage ---- Begin FA stage FA_294:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(270), DATA_B => INT_CARRY(271), DATA_C => INT_CARRY(272), SAVE => INT_SUM(366), CARRY => INT_CARRY(291) ); ---- End FA stage ---- Begin NO stage INT_SUM(367) <= INT_CARRY(273); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(368) <= INT_CARRY(274); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_295:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(364), DATA_B => INT_SUM(365), DATA_C => INT_SUM(366), SAVE => INT_SUM(369), CARRY => INT_CARRY(292) ); ---- End FA stage ---- Begin FA stage FA_296:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(367), DATA_B => INT_SUM(368), DATA_C => INT_CARRY(275), SAVE => INT_SUM(370), CARRY => INT_CARRY(293) ); ---- End FA stage ---- Begin FA stage FA_297:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(276), DATA_B => INT_CARRY(277), DATA_C => INT_CARRY(278), SAVE => INT_SUM(371), CARRY => INT_CARRY(294) ); ---- End FA stage ---- Begin FA stage FA_298:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(369), DATA_B => INT_SUM(370), DATA_C => INT_SUM(371), SAVE => INT_SUM(372), CARRY => INT_CARRY(295) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(279), DATA_B => INT_CARRY(280), SAVE => INT_SUM(373), CARRY => INT_CARRY(296) ); ---- End HA stage ---- Begin FA stage FA_299:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(372), DATA_B => INT_SUM(373), DATA_C => INT_CARRY(281), SAVE => INT_SUM(374), CARRY => INT_CARRY(297) ); ---- End FA stage ---- Begin NO stage INT_SUM(375) <= INT_CARRY(282); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_300:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(374), DATA_B => INT_SUM(375), DATA_C => INT_CARRY(283), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End FA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_301:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(390), DATA_B => SUMMAND(391), DATA_C => SUMMAND(392), SAVE => INT_SUM(376), CARRY => INT_CARRY(298) ); ---- End FA stage ---- Begin FA stage FA_302:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(393), DATA_B => SUMMAND(394), DATA_C => SUMMAND(395), SAVE => INT_SUM(377), CARRY => INT_CARRY(299) ); ---- End FA stage ---- Begin FA stage FA_303:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(396), DATA_B => SUMMAND(397), DATA_C => SUMMAND(398), SAVE => INT_SUM(378), CARRY => INT_CARRY(300) ); ---- End FA stage ---- Begin FA stage FA_304:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(399), DATA_B => SUMMAND(400), DATA_C => SUMMAND(401), SAVE => INT_SUM(379), CARRY => INT_CARRY(301) ); ---- End FA stage ---- Begin FA stage FA_305:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(402), DATA_B => SUMMAND(403), DATA_C => SUMMAND(404), SAVE => INT_SUM(380), CARRY => INT_CARRY(302) ); ---- End FA stage ---- Begin FA stage FA_306:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(376), DATA_B => INT_SUM(377), DATA_C => INT_SUM(378), SAVE => INT_SUM(381), CARRY => INT_CARRY(303) ); ---- End FA stage ---- Begin FA stage FA_307:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(379), DATA_B => INT_SUM(380), DATA_C => INT_CARRY(284), SAVE => INT_SUM(382), CARRY => INT_CARRY(304) ); ---- End FA stage ---- Begin FA stage FA_308:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(285), DATA_B => INT_CARRY(286), DATA_C => INT_CARRY(287), SAVE => INT_SUM(383), CARRY => INT_CARRY(305) ); ---- End FA stage ---- Begin NO stage INT_SUM(384) <= INT_CARRY(288); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_309:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(381), DATA_B => INT_SUM(382), DATA_C => INT_SUM(383), SAVE => INT_SUM(385), CARRY => INT_CARRY(306) ); ---- End FA stage ---- Begin FA stage FA_310:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(384), DATA_B => INT_CARRY(289), DATA_C => INT_CARRY(290), SAVE => INT_SUM(386), CARRY => INT_CARRY(307) ); ---- End FA stage ---- Begin NO stage INT_SUM(387) <= INT_CARRY(291); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_311:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(385), DATA_B => INT_SUM(386), DATA_C => INT_SUM(387), SAVE => INT_SUM(388), CARRY => INT_CARRY(308) ); ---- End FA stage ---- Begin FA stage FA_312:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(292), DATA_B => INT_CARRY(293), DATA_C => INT_CARRY(294), SAVE => INT_SUM(389), CARRY => INT_CARRY(309) ); ---- End FA stage ---- Begin FA stage FA_313:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(388), DATA_B => INT_SUM(389), DATA_C => INT_CARRY(295), SAVE => INT_SUM(390), CARRY => INT_CARRY(310) ); ---- End FA stage ---- Begin NO stage INT_SUM(391) <= INT_CARRY(296); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_314:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(390), DATA_B => INT_SUM(391), DATA_C => INT_CARRY(297), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_315:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(405), DATA_B => SUMMAND(406), DATA_C => SUMMAND(407), SAVE => INT_SUM(392), CARRY => INT_CARRY(311) ); ---- End FA stage ---- Begin FA stage FA_316:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(408), DATA_B => SUMMAND(409), DATA_C => SUMMAND(410), SAVE => INT_SUM(393), CARRY => INT_CARRY(312) ); ---- End FA stage ---- Begin FA stage FA_317:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(411), DATA_B => SUMMAND(412), DATA_C => SUMMAND(413), SAVE => INT_SUM(394), CARRY => INT_CARRY(313) ); ---- End FA stage ---- Begin FA stage FA_318:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(414), DATA_B => SUMMAND(415), DATA_C => SUMMAND(416), SAVE => INT_SUM(395), CARRY => INT_CARRY(314) ); ---- End FA stage ---- Begin FA stage FA_319:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(417), DATA_B => SUMMAND(418), DATA_C => SUMMAND(419), SAVE => INT_SUM(396), CARRY => INT_CARRY(315) ); ---- End FA stage ---- Begin FA stage FA_320:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(392), DATA_B => INT_SUM(393), DATA_C => INT_SUM(394), SAVE => INT_SUM(397), CARRY => INT_CARRY(316) ); ---- End FA stage ---- Begin FA stage FA_321:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(395), DATA_B => INT_SUM(396), DATA_C => INT_CARRY(298), SAVE => INT_SUM(398), CARRY => INT_CARRY(317) ); ---- End FA stage ---- Begin FA stage FA_322:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(299), DATA_B => INT_CARRY(300), DATA_C => INT_CARRY(301), SAVE => INT_SUM(399), CARRY => INT_CARRY(318) ); ---- End FA stage ---- Begin NO stage INT_SUM(400) <= INT_CARRY(302); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_323:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(397), DATA_B => INT_SUM(398), DATA_C => INT_SUM(399), SAVE => INT_SUM(401), CARRY => INT_CARRY(319) ); ---- End FA stage ---- Begin FA stage FA_324:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(400), DATA_B => INT_CARRY(303), DATA_C => INT_CARRY(304), SAVE => INT_SUM(402), CARRY => INT_CARRY(320) ); ---- End FA stage ---- Begin NO stage INT_SUM(403) <= INT_CARRY(305); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_325:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(401), DATA_B => INT_SUM(402), DATA_C => INT_SUM(403), SAVE => INT_SUM(404), CARRY => INT_CARRY(321) ); ---- End FA stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(306), DATA_B => INT_CARRY(307), SAVE => INT_SUM(405), CARRY => INT_CARRY(322) ); ---- End HA stage ---- Begin FA stage FA_326:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(404), DATA_B => INT_SUM(405), DATA_C => INT_CARRY(308), SAVE => INT_SUM(406), CARRY => INT_CARRY(323) ); ---- End FA stage ---- Begin NO stage INT_SUM(407) <= INT_CARRY(309); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_327:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(406), DATA_B => INT_SUM(407), DATA_C => INT_CARRY(310), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End FA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin FA stage FA_328:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(420), DATA_B => SUMMAND(421), DATA_C => SUMMAND(422), SAVE => INT_SUM(408), CARRY => INT_CARRY(324) ); ---- End FA stage ---- Begin FA stage FA_329:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(423), DATA_B => SUMMAND(424), DATA_C => SUMMAND(425), SAVE => INT_SUM(409), CARRY => INT_CARRY(325) ); ---- End FA stage ---- Begin FA stage FA_330:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(426), DATA_B => SUMMAND(427), DATA_C => SUMMAND(428), SAVE => INT_SUM(410), CARRY => INT_CARRY(326) ); ---- End FA stage ---- Begin FA stage FA_331:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(429), DATA_B => SUMMAND(430), DATA_C => SUMMAND(431), SAVE => INT_SUM(411), CARRY => INT_CARRY(327) ); ---- End FA stage ---- Begin HA stage HA_35:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(432), DATA_B => SUMMAND(433), SAVE => INT_SUM(412), CARRY => INT_CARRY(328) ); ---- End HA stage ---- Begin FA stage FA_332:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(408), DATA_B => INT_SUM(409), DATA_C => INT_SUM(410), SAVE => INT_SUM(413), CARRY => INT_CARRY(329) ); ---- End FA stage ---- Begin FA stage FA_333:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(411), DATA_B => INT_SUM(412), DATA_C => INT_CARRY(311), SAVE => INT_SUM(414), CARRY => INT_CARRY(330) ); ---- End FA stage ---- Begin FA stage FA_334:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(312), DATA_B => INT_CARRY(313), DATA_C => INT_CARRY(314), SAVE => INT_SUM(415), CARRY => INT_CARRY(331) ); ---- End FA stage ---- Begin NO stage INT_SUM(416) <= INT_CARRY(315); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_335:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(413), DATA_B => INT_SUM(414), DATA_C => INT_SUM(415), SAVE => INT_SUM(417), CARRY => INT_CARRY(332) ); ---- End FA stage ---- Begin FA stage FA_336:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(416), DATA_B => INT_CARRY(316), DATA_C => INT_CARRY(317), SAVE => INT_SUM(418), CARRY => INT_CARRY(333) ); ---- End FA stage ---- Begin NO stage INT_SUM(419) <= INT_CARRY(318); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_337:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(417), DATA_B => INT_SUM(418), DATA_C => INT_SUM(419), SAVE => INT_SUM(420), CARRY => INT_CARRY(334) ); ---- End FA stage ---- Begin HA stage HA_36:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(319), DATA_B => INT_CARRY(320), SAVE => INT_SUM(421), CARRY => INT_CARRY(335) ); ---- End HA stage ---- Begin FA stage FA_338:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(420), DATA_B => INT_SUM(421), DATA_C => INT_CARRY(321), SAVE => INT_SUM(422), CARRY => INT_CARRY(336) ); ---- End FA stage ---- Begin NO stage INT_SUM(423) <= INT_CARRY(322); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_339:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(422), DATA_B => INT_SUM(423), DATA_C => INT_CARRY(323), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin FA stage FA_340:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(434), DATA_B => SUMMAND(435), DATA_C => SUMMAND(436), SAVE => INT_SUM(424), CARRY => INT_CARRY(337) ); ---- End FA stage ---- Begin FA stage FA_341:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(437), DATA_B => SUMMAND(438), DATA_C => SUMMAND(439), SAVE => INT_SUM(425), CARRY => INT_CARRY(338) ); ---- End FA stage ---- Begin FA stage FA_342:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(440), DATA_B => SUMMAND(441), DATA_C => SUMMAND(442), SAVE => INT_SUM(426), CARRY => INT_CARRY(339) ); ---- End FA stage ---- Begin FA stage FA_343:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(443), DATA_B => SUMMAND(444), DATA_C => SUMMAND(445), SAVE => INT_SUM(427), CARRY => INT_CARRY(340) ); ---- End FA stage ---- Begin HA stage HA_37:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(446), DATA_B => SUMMAND(447), SAVE => INT_SUM(428), CARRY => INT_CARRY(341) ); ---- End HA stage ---- Begin FA stage FA_344:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(424), DATA_B => INT_SUM(425), DATA_C => INT_SUM(426), SAVE => INT_SUM(429), CARRY => INT_CARRY(342) ); ---- End FA stage ---- Begin FA stage FA_345:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(427), DATA_B => INT_SUM(428), DATA_C => INT_CARRY(324), SAVE => INT_SUM(430), CARRY => INT_CARRY(343) ); ---- End FA stage ---- Begin FA stage FA_346:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(325), DATA_B => INT_CARRY(326), DATA_C => INT_CARRY(327), SAVE => INT_SUM(431), CARRY => INT_CARRY(344) ); ---- End FA stage ---- Begin NO stage INT_SUM(432) <= INT_CARRY(328); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_347:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(429), DATA_B => INT_SUM(430), DATA_C => INT_SUM(431), SAVE => INT_SUM(433), CARRY => INT_CARRY(345) ); ---- End FA stage ---- Begin FA stage FA_348:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(432), DATA_B => INT_CARRY(329), DATA_C => INT_CARRY(330), SAVE => INT_SUM(434), CARRY => INT_CARRY(346) ); ---- End FA stage ---- Begin NO stage INT_SUM(435) <= INT_CARRY(331); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_349:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(433), DATA_B => INT_SUM(434), DATA_C => INT_SUM(435), SAVE => INT_SUM(436), CARRY => INT_CARRY(347) ); ---- End FA stage ---- Begin HA stage HA_38:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(332), DATA_B => INT_CARRY(333), SAVE => INT_SUM(437), CARRY => INT_CARRY(348) ); ---- End HA stage ---- Begin FA stage FA_350:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(436), DATA_B => INT_SUM(437), DATA_C => INT_CARRY(334), SAVE => INT_SUM(438), CARRY => INT_CARRY(349) ); ---- End FA stage ---- Begin NO stage INT_SUM(439) <= INT_CARRY(335); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_351:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(438), DATA_B => INT_SUM(439), DATA_C => INT_CARRY(336), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End FA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin FA stage FA_352:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(448), DATA_B => SUMMAND(449), DATA_C => SUMMAND(450), SAVE => INT_SUM(440), CARRY => INT_CARRY(350) ); ---- End FA stage ---- Begin FA stage FA_353:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(451), DATA_B => SUMMAND(452), DATA_C => SUMMAND(453), SAVE => INT_SUM(441), CARRY => INT_CARRY(351) ); ---- End FA stage ---- Begin FA stage FA_354:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(454), DATA_B => SUMMAND(455), DATA_C => SUMMAND(456), SAVE => INT_SUM(442), CARRY => INT_CARRY(352) ); ---- End FA stage ---- Begin FA stage FA_355:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(457), DATA_B => SUMMAND(458), DATA_C => SUMMAND(459), SAVE => INT_SUM(443), CARRY => INT_CARRY(353) ); ---- End FA stage ---- Begin NO stage INT_SUM(444) <= SUMMAND(460); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_356:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(440), DATA_B => INT_SUM(441), DATA_C => INT_SUM(442), SAVE => INT_SUM(445), CARRY => INT_CARRY(354) ); ---- End FA stage ---- Begin FA stage FA_357:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(443), DATA_B => INT_SUM(444), DATA_C => INT_CARRY(337), SAVE => INT_SUM(446), CARRY => INT_CARRY(355) ); ---- End FA stage ---- Begin FA stage FA_358:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(338), DATA_B => INT_CARRY(339), DATA_C => INT_CARRY(340), SAVE => INT_SUM(447), CARRY => INT_CARRY(356) ); ---- End FA stage ---- Begin NO stage INT_SUM(448) <= INT_CARRY(341); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_359:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(445), DATA_B => INT_SUM(446), DATA_C => INT_SUM(447), SAVE => INT_SUM(449), CARRY => INT_CARRY(357) ); ---- End FA stage ---- Begin FA stage FA_360:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(448), DATA_B => INT_CARRY(342), DATA_C => INT_CARRY(343), SAVE => INT_SUM(450), CARRY => INT_CARRY(358) ); ---- End FA stage ---- Begin NO stage INT_SUM(451) <= INT_CARRY(344); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_361:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(449), DATA_B => INT_SUM(450), DATA_C => INT_SUM(451), SAVE => INT_SUM(452), CARRY => INT_CARRY(359) ); ---- End FA stage ---- Begin HA stage HA_39:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(345), DATA_B => INT_CARRY(346), SAVE => INT_SUM(453), CARRY => INT_CARRY(360) ); ---- End HA stage ---- Begin FA stage FA_362:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(452), DATA_B => INT_SUM(453), DATA_C => INT_CARRY(347), SAVE => INT_SUM(454), CARRY => INT_CARRY(361) ); ---- End FA stage ---- Begin NO stage INT_SUM(455) <= INT_CARRY(348); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_363:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(454), DATA_B => INT_SUM(455), DATA_C => INT_CARRY(349), SAVE => SUM(42), CARRY => CARRY(42) ); ---- End FA stage -- End WT-branch 43 -- Begin WT-branch 44 ---- Begin FA stage FA_364:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(461), DATA_B => SUMMAND(462), DATA_C => SUMMAND(463), SAVE => INT_SUM(456), CARRY => INT_CARRY(362) ); ---- End FA stage ---- Begin FA stage FA_365:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(464), DATA_B => SUMMAND(465), DATA_C => SUMMAND(466), SAVE => INT_SUM(457), CARRY => INT_CARRY(363) ); ---- End FA stage ---- Begin FA stage FA_366:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(467), DATA_B => SUMMAND(468), DATA_C => SUMMAND(469), SAVE => INT_SUM(458), CARRY => INT_CARRY(364) ); ---- End FA stage ---- Begin FA stage FA_367:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(470), DATA_B => SUMMAND(471), DATA_C => SUMMAND(472), SAVE => INT_SUM(459), CARRY => INT_CARRY(365) ); ---- End FA stage ---- Begin FA stage FA_368:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(473), DATA_B => INT_CARRY(350), DATA_C => INT_CARRY(351), SAVE => INT_SUM(460), CARRY => INT_CARRY(366) ); ---- End FA stage ---- Begin NO stage INT_SUM(461) <= INT_CARRY(352); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(462) <= INT_CARRY(353); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_369:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(456), DATA_B => INT_SUM(457), DATA_C => INT_SUM(458), SAVE => INT_SUM(463), CARRY => INT_CARRY(367) ); ---- End FA stage ---- Begin FA stage FA_370:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(459), DATA_B => INT_SUM(460), DATA_C => INT_SUM(461), SAVE => INT_SUM(464), CARRY => INT_CARRY(368) ); ---- End FA stage ---- Begin FA stage FA_371:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(462), DATA_B => INT_CARRY(354), DATA_C => INT_CARRY(355), SAVE => INT_SUM(465), CARRY => INT_CARRY(369) ); ---- End FA stage ---- Begin NO stage INT_SUM(466) <= INT_CARRY(356); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_372:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(463), DATA_B => INT_SUM(464), DATA_C => INT_SUM(465), SAVE => INT_SUM(467), CARRY => INT_CARRY(370) ); ---- End FA stage ---- Begin FA stage FA_373:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(466), DATA_B => INT_CARRY(357), DATA_C => INT_CARRY(358), SAVE => INT_SUM(468), CARRY => INT_CARRY(371) ); ---- End FA stage ---- Begin FA stage FA_374:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(467), DATA_B => INT_SUM(468), DATA_C => INT_CARRY(359), SAVE => INT_SUM(469), CARRY => INT_CARRY(372) ); ---- End FA stage ---- Begin NO stage INT_SUM(470) <= INT_CARRY(360); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_375:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(469), DATA_B => INT_SUM(470), DATA_C => INT_CARRY(361), SAVE => SUM(43), CARRY => CARRY(43) ); ---- End FA stage -- End WT-branch 44 -- Begin WT-branch 45 ---- Begin FA stage FA_376:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(474), DATA_B => SUMMAND(475), DATA_C => SUMMAND(476), SAVE => INT_SUM(471), CARRY => INT_CARRY(373) ); ---- End FA stage ---- Begin FA stage FA_377:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(477), DATA_B => SUMMAND(478), DATA_C => SUMMAND(479), SAVE => INT_SUM(472), CARRY => INT_CARRY(374) ); ---- End FA stage ---- Begin FA stage FA_378:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(480), DATA_B => SUMMAND(481), DATA_C => SUMMAND(482), SAVE => INT_SUM(473), CARRY => INT_CARRY(375) ); ---- End FA stage ---- Begin FA stage FA_379:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(483), DATA_B => SUMMAND(484), DATA_C => SUMMAND(485), SAVE => INT_SUM(474), CARRY => INT_CARRY(376) ); ---- End FA stage ---- Begin FA stage FA_380:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(471), DATA_B => INT_SUM(472), DATA_C => INT_SUM(473), SAVE => INT_SUM(475), CARRY => INT_CARRY(377) ); ---- End FA stage ---- Begin FA stage FA_381:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(474), DATA_B => INT_CARRY(362), DATA_C => INT_CARRY(363), SAVE => INT_SUM(476), CARRY => INT_CARRY(378) ); ---- End FA stage ---- Begin FA stage FA_382:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(364), DATA_B => INT_CARRY(365), DATA_C => INT_CARRY(366), SAVE => INT_SUM(477), CARRY => INT_CARRY(379) ); ---- End FA stage ---- Begin FA stage FA_383:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(475), DATA_B => INT_SUM(476), DATA_C => INT_SUM(477), SAVE => INT_SUM(478), CARRY => INT_CARRY(380) ); ---- End FA stage ---- Begin FA stage FA_384:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(367), DATA_B => INT_CARRY(368), DATA_C => INT_CARRY(369), SAVE => INT_SUM(479), CARRY => INT_CARRY(381) ); ---- End FA stage ---- Begin FA stage FA_385:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(478), DATA_B => INT_SUM(479), DATA_C => INT_CARRY(370), SAVE => INT_SUM(480), CARRY => INT_CARRY(382) ); ---- End FA stage ---- Begin NO stage INT_SUM(481) <= INT_CARRY(371); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_386:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(480), DATA_B => INT_SUM(481), DATA_C => INT_CARRY(372), SAVE => SUM(44), CARRY => CARRY(44) ); ---- End FA stage -- End WT-branch 45 -- Begin WT-branch 46 ---- Begin FA stage FA_387:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(486), DATA_B => SUMMAND(487), DATA_C => SUMMAND(488), SAVE => INT_SUM(482), CARRY => INT_CARRY(383) ); ---- End FA stage ---- Begin FA stage FA_388:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(489), DATA_B => SUMMAND(490), DATA_C => SUMMAND(491), SAVE => INT_SUM(483), CARRY => INT_CARRY(384) ); ---- End FA stage ---- Begin FA stage FA_389:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(492), DATA_B => SUMMAND(493), DATA_C => SUMMAND(494), SAVE => INT_SUM(484), CARRY => INT_CARRY(385) ); ---- End FA stage ---- Begin FA stage FA_390:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(495), DATA_B => SUMMAND(496), DATA_C => SUMMAND(497), SAVE => INT_SUM(485), CARRY => INT_CARRY(386) ); ---- End FA stage ---- Begin FA stage FA_391:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(482), DATA_B => INT_SUM(483), DATA_C => INT_SUM(484), SAVE => INT_SUM(486), CARRY => INT_CARRY(387) ); ---- End FA stage ---- Begin FA stage FA_392:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(485), DATA_B => INT_CARRY(373), DATA_C => INT_CARRY(374), SAVE => INT_SUM(487), CARRY => INT_CARRY(388) ); ---- End FA stage ---- Begin HA stage HA_40:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(375), DATA_B => INT_CARRY(376), SAVE => INT_SUM(488), CARRY => INT_CARRY(389) ); ---- End HA stage ---- Begin FA stage FA_393:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(486), DATA_B => INT_SUM(487), DATA_C => INT_SUM(488), SAVE => INT_SUM(489), CARRY => INT_CARRY(390) ); ---- End FA stage ---- Begin FA stage FA_394:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(377), DATA_B => INT_CARRY(378), DATA_C => INT_CARRY(379), SAVE => INT_SUM(490), CARRY => INT_CARRY(391) ); ---- End FA stage ---- Begin FA stage FA_395:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(489), DATA_B => INT_SUM(490), DATA_C => INT_CARRY(380), SAVE => INT_SUM(491), CARRY => INT_CARRY(392) ); ---- End FA stage ---- Begin NO stage INT_SUM(492) <= INT_CARRY(381); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_396:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(491), DATA_B => INT_SUM(492), DATA_C => INT_CARRY(382), SAVE => SUM(45), CARRY => CARRY(45) ); ---- End FA stage -- End WT-branch 46 -- Begin WT-branch 47 ---- Begin FA stage FA_397:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(498), DATA_B => SUMMAND(499), DATA_C => SUMMAND(500), SAVE => INT_SUM(493), CARRY => INT_CARRY(393) ); ---- End FA stage ---- Begin FA stage FA_398:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(501), DATA_B => SUMMAND(502), DATA_C => SUMMAND(503), SAVE => INT_SUM(494), CARRY => INT_CARRY(394) ); ---- End FA stage ---- Begin FA stage FA_399:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(504), DATA_B => SUMMAND(505), DATA_C => SUMMAND(506), SAVE => INT_SUM(495), CARRY => INT_CARRY(395) ); ---- End FA stage ---- Begin NO stage INT_SUM(496) <= SUMMAND(507); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(497) <= SUMMAND(508); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_400:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(493), DATA_B => INT_SUM(494), DATA_C => INT_SUM(495), SAVE => INT_SUM(498), CARRY => INT_CARRY(396) ); ---- End FA stage ---- Begin FA stage FA_401:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(496), DATA_B => INT_SUM(497), DATA_C => INT_CARRY(383), SAVE => INT_SUM(499), CARRY => INT_CARRY(397) ); ---- End FA stage ---- Begin FA stage FA_402:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(384), DATA_B => INT_CARRY(385), DATA_C => INT_CARRY(386), SAVE => INT_SUM(500), CARRY => INT_CARRY(398) ); ---- End FA stage ---- Begin FA stage FA_403:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(498), DATA_B => INT_SUM(499), DATA_C => INT_SUM(500), SAVE => INT_SUM(501), CARRY => INT_CARRY(399) ); ---- End FA stage ---- Begin FA stage FA_404:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(387), DATA_B => INT_CARRY(388), DATA_C => INT_CARRY(389), SAVE => INT_SUM(502), CARRY => INT_CARRY(400) ); ---- End FA stage ---- Begin FA stage FA_405:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(501), DATA_B => INT_SUM(502), DATA_C => INT_CARRY(390), SAVE => INT_SUM(503), CARRY => INT_CARRY(401) ); ---- End FA stage ---- Begin NO stage INT_SUM(504) <= INT_CARRY(391); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_406:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(503), DATA_B => INT_SUM(504), DATA_C => INT_CARRY(392), SAVE => SUM(46), CARRY => CARRY(46) ); ---- End FA stage -- End WT-branch 47 -- Begin WT-branch 48 ---- Begin FA stage FA_407:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(509), DATA_B => SUMMAND(510), DATA_C => SUMMAND(511), SAVE => INT_SUM(505), CARRY => INT_CARRY(402) ); ---- End FA stage ---- Begin FA stage FA_408:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(512), DATA_B => SUMMAND(513), DATA_C => SUMMAND(514), SAVE => INT_SUM(506), CARRY => INT_CARRY(403) ); ---- End FA stage ---- Begin FA stage FA_409:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(515), DATA_B => SUMMAND(516), DATA_C => SUMMAND(517), SAVE => INT_SUM(507), CARRY => INT_CARRY(404) ); ---- End FA stage ---- Begin HA stage HA_41:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(518), DATA_B => SUMMAND(519), SAVE => INT_SUM(508), CARRY => INT_CARRY(405) ); ---- End HA stage ---- Begin FA stage FA_410:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(505), DATA_B => INT_SUM(506), DATA_C => INT_SUM(507), SAVE => INT_SUM(509), CARRY => INT_CARRY(406) ); ---- End FA stage ---- Begin FA stage FA_411:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(508), DATA_B => INT_CARRY(393), DATA_C => INT_CARRY(394), SAVE => INT_SUM(510), CARRY => INT_CARRY(407) ); ---- End FA stage ---- Begin NO stage INT_SUM(511) <= INT_CARRY(395); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_412:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(509), DATA_B => INT_SUM(510), DATA_C => INT_SUM(511), SAVE => INT_SUM(512), CARRY => INT_CARRY(408) ); ---- End FA stage ---- Begin FA stage FA_413:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(396), DATA_B => INT_CARRY(397), DATA_C => INT_CARRY(398), SAVE => INT_SUM(513), CARRY => INT_CARRY(409) ); ---- End FA stage ---- Begin FA stage FA_414:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(512), DATA_B => INT_SUM(513), DATA_C => INT_CARRY(399), SAVE => INT_SUM(514), CARRY => INT_CARRY(410) ); ---- End FA stage ---- Begin NO stage INT_SUM(515) <= INT_CARRY(400); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_415:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(514), DATA_B => INT_SUM(515), DATA_C => INT_CARRY(401), SAVE => SUM(47), CARRY => CARRY(47) ); ---- End FA stage -- End WT-branch 48 -- Begin WT-branch 49 ---- Begin FA stage FA_416:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(520), DATA_B => SUMMAND(521), DATA_C => SUMMAND(522), SAVE => INT_SUM(516), CARRY => INT_CARRY(411) ); ---- End FA stage ---- Begin FA stage FA_417:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(523), DATA_B => SUMMAND(524), DATA_C => SUMMAND(525), SAVE => INT_SUM(517), CARRY => INT_CARRY(412) ); ---- End FA stage ---- Begin FA stage FA_418:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(526), DATA_B => SUMMAND(527), DATA_C => SUMMAND(528), SAVE => INT_SUM(518), CARRY => INT_CARRY(413) ); ---- End FA stage ---- Begin NO stage INT_SUM(519) <= SUMMAND(529); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_419:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(516), DATA_B => INT_SUM(517), DATA_C => INT_SUM(518), SAVE => INT_SUM(520), CARRY => INT_CARRY(414) ); ---- End FA stage ---- Begin FA stage FA_420:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(519), DATA_B => INT_CARRY(402), DATA_C => INT_CARRY(403), SAVE => INT_SUM(521), CARRY => INT_CARRY(415) ); ---- End FA stage ---- Begin NO stage INT_SUM(522) <= INT_CARRY(404); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(523) <= INT_CARRY(405); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_421:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(520), DATA_B => INT_SUM(521), DATA_C => INT_SUM(522), SAVE => INT_SUM(524), CARRY => INT_CARRY(416) ); ---- End FA stage ---- Begin FA stage FA_422:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(523), DATA_B => INT_CARRY(406), DATA_C => INT_CARRY(407), SAVE => INT_SUM(525), CARRY => INT_CARRY(417) ); ---- End FA stage ---- Begin FA stage FA_423:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(524), DATA_B => INT_SUM(525), DATA_C => INT_CARRY(408), SAVE => INT_SUM(526), CARRY => INT_CARRY(418) ); ---- End FA stage ---- Begin NO stage INT_SUM(527) <= INT_CARRY(409); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_424:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(526), DATA_B => INT_SUM(527), DATA_C => INT_CARRY(410), SAVE => SUM(48), CARRY => CARRY(48) ); ---- End FA stage -- End WT-branch 49 -- Begin WT-branch 50 ---- Begin FA stage FA_425:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(530), DATA_B => SUMMAND(531), DATA_C => SUMMAND(532), SAVE => INT_SUM(528), CARRY => INT_CARRY(419) ); ---- End FA stage ---- Begin FA stage FA_426:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(533), DATA_B => SUMMAND(534), DATA_C => SUMMAND(535), SAVE => INT_SUM(529), CARRY => INT_CARRY(420) ); ---- End FA stage ---- Begin FA stage FA_427:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(536), DATA_B => SUMMAND(537), DATA_C => SUMMAND(538), SAVE => INT_SUM(530), CARRY => INT_CARRY(421) ); ---- End FA stage ---- Begin NO stage INT_SUM(531) <= SUMMAND(539); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_428:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(528), DATA_B => INT_SUM(529), DATA_C => INT_SUM(530), SAVE => INT_SUM(532), CARRY => INT_CARRY(422) ); ---- End FA stage ---- Begin FA stage FA_429:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(531), DATA_B => INT_CARRY(411), DATA_C => INT_CARRY(412), SAVE => INT_SUM(533), CARRY => INT_CARRY(423) ); ---- End FA stage ---- Begin NO stage INT_SUM(534) <= INT_CARRY(413); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_430:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(532), DATA_B => INT_SUM(533), DATA_C => INT_SUM(534), SAVE => INT_SUM(535), CARRY => INT_CARRY(424) ); ---- End FA stage ---- Begin HA stage HA_42:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(414), DATA_B => INT_CARRY(415), SAVE => INT_SUM(536), CARRY => INT_CARRY(425) ); ---- End HA stage ---- Begin FA stage FA_431:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(535), DATA_B => INT_SUM(536), DATA_C => INT_CARRY(416), SAVE => INT_SUM(537), CARRY => INT_CARRY(426) ); ---- End FA stage ---- Begin NO stage INT_SUM(538) <= INT_CARRY(417); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_432:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(537), DATA_B => INT_SUM(538), DATA_C => INT_CARRY(418), SAVE => SUM(49), CARRY => CARRY(49) ); ---- End FA stage -- End WT-branch 50 -- Begin WT-branch 51 ---- Begin FA stage FA_433:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(540), DATA_B => SUMMAND(541), DATA_C => SUMMAND(542), SAVE => INT_SUM(539), CARRY => INT_CARRY(427) ); ---- End FA stage ---- Begin FA stage FA_434:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(543), DATA_B => SUMMAND(544), DATA_C => SUMMAND(545), SAVE => INT_SUM(540), CARRY => INT_CARRY(428) ); ---- End FA stage ---- Begin FA stage FA_435:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(546), DATA_B => SUMMAND(547), DATA_C => SUMMAND(548), SAVE => INT_SUM(541), CARRY => INT_CARRY(429) ); ---- End FA stage ---- Begin FA stage FA_436:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(539), DATA_B => INT_SUM(540), DATA_C => INT_SUM(541), SAVE => INT_SUM(542), CARRY => INT_CARRY(430) ); ---- End FA stage ---- Begin FA stage FA_437:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(419), DATA_B => INT_CARRY(420), DATA_C => INT_CARRY(421), SAVE => INT_SUM(543), CARRY => INT_CARRY(431) ); ---- End FA stage ---- Begin FA stage FA_438:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(542), DATA_B => INT_SUM(543), DATA_C => INT_CARRY(422), SAVE => INT_SUM(544), CARRY => INT_CARRY(432) ); ---- End FA stage ---- Begin NO stage INT_SUM(545) <= INT_CARRY(423); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_439:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(544), DATA_B => INT_SUM(545), DATA_C => INT_CARRY(424), SAVE => INT_SUM(546), CARRY => INT_CARRY(433) ); ---- End FA stage ---- Begin NO stage INT_SUM(547) <= INT_CARRY(425); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_440:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(546), DATA_B => INT_SUM(547), DATA_C => INT_CARRY(426), SAVE => SUM(50), CARRY => CARRY(50) ); ---- End FA stage -- End WT-branch 51 -- Begin WT-branch 52 ---- Begin FA stage FA_441:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(549), DATA_B => SUMMAND(550), DATA_C => SUMMAND(551), SAVE => INT_SUM(548), CARRY => INT_CARRY(434) ); ---- End FA stage ---- Begin FA stage FA_442:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(552), DATA_B => SUMMAND(553), DATA_C => SUMMAND(554), SAVE => INT_SUM(549), CARRY => INT_CARRY(435) ); ---- End FA stage ---- Begin FA stage FA_443:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(555), DATA_B => SUMMAND(556), DATA_C => SUMMAND(557), SAVE => INT_SUM(550), CARRY => INT_CARRY(436) ); ---- End FA stage ---- Begin FA stage FA_444:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(548), DATA_B => INT_SUM(549), DATA_C => INT_SUM(550), SAVE => INT_SUM(551), CARRY => INT_CARRY(437) ); ---- End FA stage ---- Begin FA stage FA_445:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(427), DATA_B => INT_CARRY(428), DATA_C => INT_CARRY(429), SAVE => INT_SUM(552), CARRY => INT_CARRY(438) ); ---- End FA stage ---- Begin FA stage FA_446:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(551), DATA_B => INT_SUM(552), DATA_C => INT_CARRY(430), SAVE => INT_SUM(553), CARRY => INT_CARRY(439) ); ---- End FA stage ---- Begin NO stage INT_SUM(554) <= INT_CARRY(431); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_447:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(553), DATA_B => INT_SUM(554), DATA_C => INT_CARRY(432), SAVE => INT_SUM(555), CARRY => INT_CARRY(440) ); ---- End FA stage ---- Begin HA stage HA_43:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(555), DATA_B => INT_CARRY(433), SAVE => SUM(51), CARRY => CARRY(51) ); ---- End HA stage -- End WT-branch 52 -- Begin WT-branch 53 ---- Begin FA stage FA_448:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(558), DATA_B => SUMMAND(559), DATA_C => SUMMAND(560), SAVE => INT_SUM(556), CARRY => INT_CARRY(441) ); ---- End FA stage ---- Begin FA stage FA_449:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(561), DATA_B => SUMMAND(562), DATA_C => SUMMAND(563), SAVE => INT_SUM(557), CARRY => INT_CARRY(442) ); ---- End FA stage ---- Begin FA stage FA_450:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(564), DATA_B => SUMMAND(565), DATA_C => INT_CARRY(434), SAVE => INT_SUM(558), CARRY => INT_CARRY(443) ); ---- End FA stage ---- Begin HA stage HA_44:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(435), DATA_B => INT_CARRY(436), SAVE => INT_SUM(559), CARRY => INT_CARRY(444) ); ---- End HA stage ---- Begin FA stage FA_451:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(556), DATA_B => INT_SUM(557), DATA_C => INT_SUM(558), SAVE => INT_SUM(560), CARRY => INT_CARRY(445) ); ---- End FA stage ---- Begin FA stage FA_452:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(559), DATA_B => INT_CARRY(437), DATA_C => INT_CARRY(438), SAVE => INT_SUM(561), CARRY => INT_CARRY(446) ); ---- End FA stage ---- Begin FA stage FA_453:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(560), DATA_B => INT_SUM(561), DATA_C => INT_CARRY(439), SAVE => INT_SUM(562), CARRY => INT_CARRY(447) ); ---- End FA stage ---- Begin HA stage HA_45:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(562), DATA_B => INT_CARRY(440), SAVE => SUM(52), CARRY => CARRY(52) ); ---- End HA stage -- End WT-branch 53 -- Begin WT-branch 54 ---- Begin FA stage FA_454:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(566), DATA_B => SUMMAND(567), DATA_C => SUMMAND(568), SAVE => INT_SUM(563), CARRY => INT_CARRY(448) ); ---- End FA stage ---- Begin FA stage FA_455:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(569), DATA_B => SUMMAND(570), DATA_C => SUMMAND(571), SAVE => INT_SUM(564), CARRY => INT_CARRY(449) ); ---- End FA stage ---- Begin NO stage INT_SUM(565) <= SUMMAND(572); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(566) <= SUMMAND(573); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_456:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(563), DATA_B => INT_SUM(564), DATA_C => INT_SUM(565), SAVE => INT_SUM(567), CARRY => INT_CARRY(450) ); ---- End FA stage ---- Begin NO stage INT_SUM(568) <= INT_SUM(566); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_457:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(567), DATA_B => INT_SUM(568), DATA_C => INT_CARRY(441), SAVE => INT_SUM(569), CARRY => INT_CARRY(451) ); ---- End FA stage ---- Begin FA stage FA_458:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(442), DATA_B => INT_CARRY(443), DATA_C => INT_CARRY(444), SAVE => INT_SUM(570), CARRY => INT_CARRY(452) ); ---- End FA stage ---- Begin FA stage FA_459:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(569), DATA_B => INT_SUM(570), DATA_C => INT_CARRY(445), SAVE => INT_SUM(571), CARRY => INT_CARRY(453) ); ---- End FA stage ---- Begin NO stage INT_SUM(572) <= INT_CARRY(446); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_460:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(571), DATA_B => INT_SUM(572), DATA_C => INT_CARRY(447), SAVE => SUM(53), CARRY => CARRY(53) ); ---- End FA stage -- End WT-branch 54 -- Begin WT-branch 55 ---- Begin FA stage FA_461:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(574), DATA_B => SUMMAND(575), DATA_C => SUMMAND(576), SAVE => INT_SUM(573), CARRY => INT_CARRY(454) ); ---- End FA stage ---- Begin FA stage FA_462:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(577), DATA_B => SUMMAND(578), DATA_C => SUMMAND(579), SAVE => INT_SUM(574), CARRY => INT_CARRY(455) ); ---- End FA stage ---- Begin FA stage FA_463:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(580), DATA_B => INT_CARRY(448), DATA_C => INT_CARRY(449), SAVE => INT_SUM(575), CARRY => INT_CARRY(456) ); ---- End FA stage ---- Begin FA stage FA_464:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(573), DATA_B => INT_SUM(574), DATA_C => INT_SUM(575), SAVE => INT_SUM(576), CARRY => INT_CARRY(457) ); ---- End FA stage ---- Begin NO stage INT_SUM(577) <= INT_CARRY(450); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_465:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(576), DATA_B => INT_SUM(577), DATA_C => INT_CARRY(451), SAVE => INT_SUM(578), CARRY => INT_CARRY(458) ); ---- End FA stage ---- Begin NO stage INT_SUM(579) <= INT_CARRY(452); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_466:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(578), DATA_B => INT_SUM(579), DATA_C => INT_CARRY(453), SAVE => SUM(54), CARRY => CARRY(54) ); ---- End FA stage -- End WT-branch 55 -- Begin WT-branch 56 ---- Begin FA stage FA_467:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(581), DATA_B => SUMMAND(582), DATA_C => SUMMAND(583), SAVE => INT_SUM(580), CARRY => INT_CARRY(459) ); ---- End FA stage ---- Begin FA stage FA_468:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(584), DATA_B => SUMMAND(585), DATA_C => SUMMAND(586), SAVE => INT_SUM(581), CARRY => INT_CARRY(460) ); ---- End FA stage ---- Begin NO stage INT_SUM(582) <= SUMMAND(587); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_469:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(580), DATA_B => INT_SUM(581), DATA_C => INT_SUM(582), SAVE => INT_SUM(583), CARRY => INT_CARRY(461) ); ---- End FA stage ---- Begin FA stage FA_470:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(454), DATA_B => INT_CARRY(455), DATA_C => INT_CARRY(456), SAVE => INT_SUM(584), CARRY => INT_CARRY(462) ); ---- End FA stage ---- Begin FA stage FA_471:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(583), DATA_B => INT_SUM(584), DATA_C => INT_CARRY(457), SAVE => INT_SUM(585), CARRY => INT_CARRY(463) ); ---- End FA stage ---- Begin HA stage HA_46:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(585), DATA_B => INT_CARRY(458), SAVE => SUM(55), CARRY => CARRY(55) ); ---- End HA stage -- End WT-branch 56 -- Begin WT-branch 57 ---- Begin FA stage FA_472:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(588), DATA_B => SUMMAND(589), DATA_C => SUMMAND(590), SAVE => INT_SUM(586), CARRY => INT_CARRY(464) ); ---- End FA stage ---- Begin FA stage FA_473:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(591), DATA_B => SUMMAND(592), DATA_C => SUMMAND(593), SAVE => INT_SUM(587), CARRY => INT_CARRY(465) ); ---- End FA stage ---- Begin FA stage FA_474:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(586), DATA_B => INT_SUM(587), DATA_C => INT_CARRY(459), SAVE => INT_SUM(588), CARRY => INT_CARRY(466) ); ---- End FA stage ---- Begin NO stage INT_SUM(589) <= INT_CARRY(460); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_475:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(588), DATA_B => INT_SUM(589), DATA_C => INT_CARRY(461), SAVE => INT_SUM(590), CARRY => INT_CARRY(467) ); ---- End FA stage ---- Begin NO stage INT_SUM(591) <= INT_CARRY(462); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_476:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(590), DATA_B => INT_SUM(591), DATA_C => INT_CARRY(463), SAVE => SUM(56), CARRY => CARRY(56) ); ---- End FA stage -- End WT-branch 57 -- Begin WT-branch 58 ---- Begin FA stage FA_477:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(594), DATA_B => SUMMAND(595), DATA_C => SUMMAND(596), SAVE => INT_SUM(592), CARRY => INT_CARRY(468) ); ---- End FA stage ---- Begin FA stage FA_478:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(597), DATA_B => SUMMAND(598), DATA_C => SUMMAND(599), SAVE => INT_SUM(593), CARRY => INT_CARRY(469) ); ---- End FA stage ---- Begin FA stage FA_479:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(592), DATA_B => INT_SUM(593), DATA_C => INT_CARRY(464), SAVE => INT_SUM(594), CARRY => INT_CARRY(470) ); ---- End FA stage ---- Begin NO stage INT_SUM(595) <= INT_CARRY(465); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_480:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(594), DATA_B => INT_SUM(595), DATA_C => INT_CARRY(466), SAVE => INT_SUM(596), CARRY => INT_CARRY(471) ); ---- End FA stage ---- Begin HA stage HA_47:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(596), DATA_B => INT_CARRY(467), SAVE => SUM(57), CARRY => CARRY(57) ); ---- End HA stage -- End WT-branch 58 -- Begin WT-branch 59 ---- Begin FA stage FA_481:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(600), DATA_B => SUMMAND(601), DATA_C => SUMMAND(602), SAVE => INT_SUM(597), CARRY => INT_CARRY(472) ); ---- End FA stage ---- Begin HA stage HA_48:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(603), DATA_B => SUMMAND(604), SAVE => INT_SUM(598), CARRY => INT_CARRY(473) ); ---- End HA stage ---- Begin FA stage FA_482:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(597), DATA_B => INT_SUM(598), DATA_C => INT_CARRY(468), SAVE => INT_SUM(599), CARRY => INT_CARRY(474) ); ---- End FA stage ---- Begin NO stage INT_SUM(600) <= INT_CARRY(469); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_483:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(599), DATA_B => INT_SUM(600), DATA_C => INT_CARRY(470), SAVE => INT_SUM(601), CARRY => INT_CARRY(475) ); ---- End FA stage ---- Begin HA stage HA_49:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(601), DATA_B => INT_CARRY(471), SAVE => SUM(58), CARRY => CARRY(58) ); ---- End HA stage -- End WT-branch 59 -- Begin WT-branch 60 ---- Begin FA stage FA_484:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(605), DATA_B => SUMMAND(606), DATA_C => SUMMAND(607), SAVE => INT_SUM(602), CARRY => INT_CARRY(476) ); ---- End FA stage ---- Begin HA stage HA_50:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(608), DATA_B => SUMMAND(609), SAVE => INT_SUM(603), CARRY => INT_CARRY(477) ); ---- End HA stage ---- Begin FA stage FA_485:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(602), DATA_B => INT_SUM(603), DATA_C => INT_CARRY(472), SAVE => INT_SUM(604), CARRY => INT_CARRY(478) ); ---- End FA stage ---- Begin NO stage INT_SUM(605) <= INT_CARRY(473); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_486:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(604), DATA_B => INT_SUM(605), DATA_C => INT_CARRY(474), SAVE => INT_SUM(606), CARRY => INT_CARRY(479) ); ---- End FA stage ---- Begin HA stage HA_51:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(606), DATA_B => INT_CARRY(475), SAVE => SUM(59), CARRY => CARRY(59) ); ---- End HA stage -- End WT-branch 60 -- Begin WT-branch 61 ---- Begin FA stage FA_487:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(610), DATA_B => SUMMAND(611), DATA_C => SUMMAND(612), SAVE => INT_SUM(607), CARRY => INT_CARRY(480) ); ---- End FA stage ---- Begin FA stage FA_488:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(613), DATA_B => INT_CARRY(476), DATA_C => INT_CARRY(477), SAVE => INT_SUM(608), CARRY => INT_CARRY(481) ); ---- End FA stage ---- Begin FA stage FA_489:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(607), DATA_B => INT_SUM(608), DATA_C => INT_CARRY(478), SAVE => INT_SUM(609), CARRY => INT_CARRY(482) ); ---- End FA stage ---- Begin HA stage HA_52:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(609), DATA_B => INT_CARRY(479), SAVE => SUM(60), CARRY => CARRY(60) ); ---- End HA stage -- End WT-branch 61 -- Begin WT-branch 62 ---- Begin FA stage FA_490:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(614), DATA_B => SUMMAND(615), DATA_C => SUMMAND(616), SAVE => INT_SUM(610), CARRY => INT_CARRY(483) ); ---- End FA stage ---- Begin NO stage INT_SUM(611) <= SUMMAND(617); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_491:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(610), DATA_B => INT_SUM(611), DATA_C => INT_CARRY(480), SAVE => INT_SUM(612), CARRY => INT_CARRY(484) ); ---- End FA stage ---- Begin NO stage INT_SUM(613) <= INT_CARRY(481); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_492:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(612), DATA_B => INT_SUM(613), DATA_C => INT_CARRY(482), SAVE => SUM(61), CARRY => CARRY(61) ); ---- End FA stage -- End WT-branch 62 -- Begin WT-branch 63 ---- Begin FA stage FA_493:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(618), DATA_B => SUMMAND(619), DATA_C => SUMMAND(620), SAVE => INT_SUM(614), CARRY => INT_CARRY(485) ); ---- End FA stage ---- Begin NO stage INT_SUM(615) <= INT_SUM(614); -- At Level 5 ---- End NO stage ---- Begin NO stage INT_SUM(616) <= INT_CARRY(483); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_494:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(615), DATA_B => INT_SUM(616), DATA_C => INT_CARRY(484), SAVE => SUM(62), CARRY => CARRY(62) ); ---- End FA stage -- End WT-branch 63 -- Begin WT-branch 64 ---- Begin FA stage FA_495:FULL_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(621), DATA_B => SUMMAND(622), DATA_C => SUMMAND(623), SAVE => INT_SUM(617), CARRY => INT_CARRY(486) ); ---- End FA stage ---- Begin NO stage INT_SUM(618) <= INT_CARRY(485); -- At Level 5 ---- End NO stage ---- Begin HA stage HA_53:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(617), DATA_B => INT_SUM(618), SAVE => SUM(63), CARRY => CARRY(63) ); ---- End HA stage -- End WT-branch 64 -- Begin WT-branch 65 ---- Begin NO stage INT_SUM(619) <= SUMMAND(624); -- At Level 5 ---- End NO stage ---- Begin NO stage INT_SUM(620) <= SUMMAND(625); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_496:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(619), DATA_B => INT_SUM(620), DATA_C => INT_CARRY(486), SAVE => SUM(64), CARRY => CARRY(64) ); ---- End FA stage -- End WT-branch 65 -- Begin WT-branch 66 ---- Begin HA stage HA_54:HALF_ADDER -- At Level 6 port map ( DATA_A => SUMMAND(626), DATA_B => SUMMAND(627), SAVE => SUM(65), CARRY => CARRY(65) ); ---- End HA stage -- End WT-branch 66 -- Begin WT-branch 67 ---- Begin NO stage SUM(66) <= SUMMAND(628); -- At Level 6 ---- End NO stage -- End WT-branch 67 end WALLACE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_34 is generic (mulpipe : integer := 0); port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 33); PHI: in std_logic; holdn: in std_logic; RESULT: out std_logic_vector(0 to 127) ); end MULTIPLIER_34_34; architecture MULTIPLIER of MULTIPLIER_34_34 is signal PPBIT:std_logic_vector(0 to 628); signal INT_CARRY: std_logic_vector(0 to 128); signal INT_SUM: std_logic_vector(0 to 127); signal LOGIC_ZERO: std_logic; signal INT_CARRYR: std_logic_vector(0 to 128); signal INT_SUMR: std_logic_vector(0 to 127); begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_34 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 33) => MULTIPLIER(0 to 33), SUMMAND(0 to 628) => PPBIT(0 to 628) ); W:WALLACE_34_34 port map ( SUMMAND(0 to 628) => PPBIT(0 to 628), CARRY(0 to 65) => INT_CARRY(1 to 66), SUM(0 to 66) => INT_SUM(0 to 66) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(67) <= LOGIC_ZERO; INT_CARRY(68) <= LOGIC_ZERO; INT_CARRY(69) <= LOGIC_ZERO; INT_CARRY(70) <= LOGIC_ZERO; INT_CARRY(71) <= LOGIC_ZERO; INT_CARRY(72) <= LOGIC_ZERO; INT_CARRY(73) <= LOGIC_ZERO; INT_CARRY(74) <= LOGIC_ZERO; INT_CARRY(75) <= LOGIC_ZERO; INT_CARRY(76) <= LOGIC_ZERO; INT_CARRY(77) <= LOGIC_ZERO; INT_CARRY(78) <= LOGIC_ZERO; INT_CARRY(79) <= LOGIC_ZERO; INT_CARRY(80) <= LOGIC_ZERO; INT_CARRY(81) <= LOGIC_ZERO; INT_CARRY(82) <= LOGIC_ZERO; INT_CARRY(83) <= LOGIC_ZERO; INT_CARRY(84) <= LOGIC_ZERO; INT_CARRY(85) <= LOGIC_ZERO; INT_CARRY(86) <= LOGIC_ZERO; INT_CARRY(87) <= LOGIC_ZERO; INT_CARRY(88) <= LOGIC_ZERO; INT_CARRY(89) <= LOGIC_ZERO; INT_CARRY(90) <= LOGIC_ZERO; INT_CARRY(91) <= LOGIC_ZERO; INT_CARRY(92) <= LOGIC_ZERO; INT_CARRY(93) <= LOGIC_ZERO; INT_CARRY(94) <= LOGIC_ZERO; INT_CARRY(95) <= LOGIC_ZERO; INT_CARRY(96) <= LOGIC_ZERO; INT_CARRY(97) <= LOGIC_ZERO; INT_CARRY(98) <= LOGIC_ZERO; INT_CARRY(99) <= LOGIC_ZERO; INT_CARRY(100) <= LOGIC_ZERO; INT_CARRY(101) <= LOGIC_ZERO; INT_CARRY(102) <= LOGIC_ZERO; INT_CARRY(103) <= LOGIC_ZERO; INT_CARRY(104) <= LOGIC_ZERO; INT_CARRY(105) <= LOGIC_ZERO; INT_CARRY(106) <= LOGIC_ZERO; INT_CARRY(107) <= LOGIC_ZERO; INT_CARRY(108) <= LOGIC_ZERO; INT_CARRY(109) <= LOGIC_ZERO; INT_CARRY(110) <= LOGIC_ZERO; INT_CARRY(111) <= LOGIC_ZERO; INT_CARRY(112) <= LOGIC_ZERO; INT_CARRY(113) <= LOGIC_ZERO; INT_CARRY(114) <= LOGIC_ZERO; INT_CARRY(115) <= LOGIC_ZERO; INT_CARRY(116) <= LOGIC_ZERO; INT_CARRY(117) <= LOGIC_ZERO; INT_CARRY(118) <= LOGIC_ZERO; INT_CARRY(119) <= LOGIC_ZERO; INT_CARRY(120) <= LOGIC_ZERO; INT_CARRY(121) <= LOGIC_ZERO; INT_CARRY(122) <= LOGIC_ZERO; INT_CARRY(123) <= LOGIC_ZERO; INT_CARRY(124) <= LOGIC_ZERO; INT_CARRY(125) <= LOGIC_ZERO; INT_CARRY(126) <= LOGIC_ZERO; INT_CARRY(127) <= LOGIC_ZERO; INT_SUM(67) <= LOGIC_ZERO; INT_SUM(68) <= LOGIC_ZERO; INT_SUM(69) <= LOGIC_ZERO; INT_SUM(70) <= LOGIC_ZERO; INT_SUM(71) <= LOGIC_ZERO; INT_SUM(72) <= LOGIC_ZERO; INT_SUM(73) <= LOGIC_ZERO; INT_SUM(74) <= LOGIC_ZERO; INT_SUM(75) <= LOGIC_ZERO; INT_SUM(76) <= LOGIC_ZERO; INT_SUM(77) <= LOGIC_ZERO; INT_SUM(78) <= LOGIC_ZERO; INT_SUM(79) <= LOGIC_ZERO; INT_SUM(80) <= LOGIC_ZERO; INT_SUM(81) <= LOGIC_ZERO; INT_SUM(82) <= LOGIC_ZERO; INT_SUM(83) <= LOGIC_ZERO; INT_SUM(84) <= LOGIC_ZERO; INT_SUM(85) <= LOGIC_ZERO; INT_SUM(86) <= LOGIC_ZERO; INT_SUM(87) <= LOGIC_ZERO; INT_SUM(88) <= LOGIC_ZERO; INT_SUM(89) <= LOGIC_ZERO; INT_SUM(90) <= LOGIC_ZERO; INT_SUM(91) <= LOGIC_ZERO; INT_SUM(92) <= LOGIC_ZERO; INT_SUM(93) <= LOGIC_ZERO; INT_SUM(94) <= LOGIC_ZERO; INT_SUM(95) <= LOGIC_ZERO; INT_SUM(96) <= LOGIC_ZERO; INT_SUM(97) <= LOGIC_ZERO; INT_SUM(98) <= LOGIC_ZERO; INT_SUM(99) <= LOGIC_ZERO; INT_SUM(100) <= LOGIC_ZERO; INT_SUM(101) <= LOGIC_ZERO; INT_SUM(102) <= LOGIC_ZERO; INT_SUM(103) <= LOGIC_ZERO; INT_SUM(104) <= LOGIC_ZERO; INT_SUM(105) <= LOGIC_ZERO; INT_SUM(106) <= LOGIC_ZERO; INT_SUM(107) <= LOGIC_ZERO; INT_SUM(108) <= LOGIC_ZERO; INT_SUM(109) <= LOGIC_ZERO; INT_SUM(110) <= LOGIC_ZERO; INT_SUM(111) <= LOGIC_ZERO; INT_SUM(112) <= LOGIC_ZERO; INT_SUM(113) <= LOGIC_ZERO; INT_SUM(114) <= LOGIC_ZERO; INT_SUM(115) <= LOGIC_ZERO; INT_SUM(116) <= LOGIC_ZERO; INT_SUM(117) <= LOGIC_ZERO; INT_SUM(118) <= LOGIC_ZERO; INT_SUM(119) <= LOGIC_ZERO; INT_SUM(120) <= LOGIC_ZERO; INT_SUM(121) <= LOGIC_ZERO; INT_SUM(122) <= LOGIC_ZERO; INT_SUM(123) <= LOGIC_ZERO; INT_SUM(124) <= LOGIC_ZERO; INT_SUM(125) <= LOGIC_ZERO; INT_SUM(126) <= LOGIC_ZERO; INT_SUM(127) <= LOGIC_ZERO; INT_SUMR(67 to 127) <= INT_SUM(67 to 127); INT_CARRYR(67 to 127) <= INT_CARRY(67 to 127); INT_CARRYR(0) <= INT_CARRY(0); reg : if MULPIPE /= 0 generate process (PHI) begin if rising_edge(PHI ) then if (holdn = '1') then INT_SUMR(0 to 66) <= INT_SUM(0 to 66); INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66); end if; end if; end process; end generate; noreg : if MULPIPE = 0 generate INT_SUMR(0 to 66) <= INT_SUM(0 to 66); INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66); end generate; D:DBLCADDER_128_128 port map ( OPA(0 to 127) => INT_SUMR(0 to 127), OPB(0 to 127) => INT_CARRYR(0 to 127), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 127) => RESULT(0 to 127) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ -- -- Modgen multiplier created Fri Aug 16 16:35:11 2002 -- ------------------------------------------------------------ -- START: Multiplier Entitiy ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -- START: Top entity ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_33 is generic (mulpipe : integer := 0); port(clk : in std_ulogic; holdn: in std_ulogic; X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(32 downto 0); P: out std_logic_vector(65 downto 0)); end MUL_33_33; architecture A of MUL_33_33 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 33); signal Q: std_logic_vector(0 to 127); begin U1: MULTIPLIER_34_34 generic map (mulpipe) port map(A,B,CLK, holdn ,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(17); B(18) <= Y(18); B(19) <= Y(19); B(20) <= Y(20); B(21) <= Y(21); B(22) <= Y(22); B(23) <= Y(23); B(24) <= Y(24); B(25) <= Y(25); B(26) <= Y(26); B(27) <= Y(27); B(28) <= Y(28); B(29) <= Y(29); B(30) <= Y(30); B(31) <= Y(31); B(32) <= Y(32); B(33) <= Y(32); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); P(42) <= Q(42); P(43) <= Q(43); P(44) <= Q(44); P(45) <= Q(45); P(46) <= Q(46); P(47) <= Q(47); P(48) <= Q(48); P(49) <= Q(49); P(50) <= Q(50); P(51) <= Q(51); P(52) <= Q(52); P(53) <= Q(53); P(54) <= Q(54); P(55) <= Q(55); P(56) <= Q(56); P(57) <= Q(57); P(58) <= Q(58); P(59) <= Q(59); P(60) <= Q(60); P(61) <= Q(61); P(62) <= Q(62); P(63) <= Q(63); P(64) <= Q(64); P(65) <= Q(65); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity ADD32 is port(X: in std_logic_vector(31 downto 0); Y: in std_logic_vector(31 downto 0); CI: in std_logic; S: out std_logic_vector(31 downto 0); CO: out std_logic); end ADD32; architecture A of ADD32 is signal A,B,Q: std_logic_vector(0 to 31); signal CLK: std_logic; begin U1: DBLCADDER_32_32 port map(A,B,CI,CLK,Q,CO); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); B(0) <= Y(0); A(1) <= X(1); B(1) <= Y(1); A(2) <= X(2); B(2) <= Y(2); A(3) <= X(3); B(3) <= Y(3); A(4) <= X(4); B(4) <= Y(4); A(5) <= X(5); B(5) <= Y(5); A(6) <= X(6); B(6) <= Y(6); A(7) <= X(7); B(7) <= Y(7); A(8) <= X(8); B(8) <= Y(8); A(9) <= X(9); B(9) <= Y(9); A(10) <= X(10); B(10) <= Y(10); A(11) <= X(11); B(11) <= Y(11); A(12) <= X(12); B(12) <= Y(12); A(13) <= X(13); B(13) <= Y(13); A(14) <= X(14); B(14) <= Y(14); A(15) <= X(15); B(15) <= Y(15); A(16) <= X(16); B(16) <= Y(16); A(17) <= X(17); B(17) <= Y(17); A(18) <= X(18); B(18) <= Y(18); A(19) <= X(19); B(19) <= Y(19); A(20) <= X(20); B(20) <= Y(20); A(21) <= X(21); B(21) <= Y(21); A(22) <= X(22); B(22) <= Y(22); A(23) <= X(23); B(23) <= Y(23); A(24) <= X(24); B(24) <= Y(24); A(25) <= X(25); B(25) <= Y(25); A(26) <= X(26); B(26) <= Y(26); A(27) <= X(27); B(27) <= Y(27); A(28) <= X(28); B(28) <= Y(28); A(29) <= X(29); B(29) <= Y(29); A(30) <= X(30); B(30) <= Y(30); A(31) <= X(31); B(31) <= Y(31); S(0) <= Q(0); S(1) <= Q(1); S(2) <= Q(2); S(3) <= Q(3); S(4) <= Q(4); S(5) <= Q(5); S(6) <= Q(6); S(7) <= Q(7); S(8) <= Q(8); S(9) <= Q(9); S(10) <= Q(10); S(11) <= Q(11); S(12) <= Q(12); S(13) <= Q(13); S(14) <= Q(14); S(15) <= Q(15); S(16) <= Q(16); S(17) <= Q(17); S(18) <= Q(18); S(19) <= Q(19); S(20) <= Q(20); S(21) <= Q(21); S(22) <= Q(22); S(23) <= Q(23); S(24) <= Q(24); S(25) <= Q(25); S(26) <= Q(26); S(27) <= Q(27); S(28) <= Q(28); S(29) <= Q(29); S(30) <= Q(30); S(31) <= Q(31); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_17_17 is generic (mulpipe : integer := 0); port(clk : in std_ulogic; holdn: in std_ulogic; X: in std_logic_vector(16 downto 0); Y: in std_logic_vector(16 downto 0); P: out std_logic_vector(33 downto 0)); end MUL_17_17; architecture A of MUL_17_17 is signal A: std_logic_vector(0 to 17); signal B: std_logic_vector(0 to 17); signal Q: std_logic_vector(0 to 63); begin U1: MULTIPLIER_18_18 generic map (mulpipe) port map(A,B,CLK, holdn, Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(16); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(16); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); end A;
----------------------------------------------------------------------------- -- File: leaves.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: A set of multipliers generated from the Arithmetic Module -- Generator at Norwegian University of Science and Technology. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; package blocks is component FLIPFLOP port ( DIN, CLK: in std_logic; DOUT: out std_logic ); end component; component DBLCADDER_32_32 port(OPA: in std_logic_vector(0 to 31); OPB: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; SUM: out std_logic_vector(0 to 31); COUT: out std_logic); end component; component FULL_ADDER port ( DATA_A, DATA_B, DATA_C: in std_logic; SAVE, CARRY: out std_logic ); end component; component HALF_ADDER port ( DATA_A, DATA_B: in std_logic; SAVE, CARRY: out std_logic ); end component; component R_GATE port ( INA, INB, INC: in std_logic; PPBIT: out std_logic ); end component; component DECODER port ( INA, INB, INC: in std_logic; TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic ); end component; component PP_LOW port ( ONEPOS, ONENEG, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end component; component PP_MIDDLE port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB, INC, IND: in std_logic; PPBIT: out std_logic ); end component; component PP_HIGH port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end component; component BLOCK0 port ( A,B,PHI: in std_logic; POUT,GOUT: out std_logic ); end component; component INVBLOCK port ( GIN,PHI:in std_logic; GOUT:out std_logic ); end component; component BLOCK1 port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end component; component BLOCK1A port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end component; component BLOCK2 port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end component; component BLOCK2A port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end component; component PRESTAGE_32 port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 31); GOUT: out std_logic_vector(0 to 32) ); end component; component XXOR1 port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end component; component XXOR2 port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end component; component DBLCTREE_32 port ( PIN:in std_logic_vector(0 to 31); GIN:in std_logic_vector(0 to 32); PHI:in std_logic; GOUT:out std_logic_vector(0 to 32); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_32 port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 32); SUM: out std_logic_vector(0 to 31); COUT: out std_logic ); end component; component DBLC_0_32 port ( PIN: in std_logic_vector(0 to 31); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 30); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_1_32 port ( PIN: in std_logic_vector(0 to 30); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 28); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_2_32 port ( PIN: in std_logic_vector(0 to 28); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 24); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_3_32 port ( PIN: in std_logic_vector(0 to 24); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 16); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_4_32 port ( PIN: in std_logic_vector(0 to 16); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 32) ); end component; component PRESTAGE_64 port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 63); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLCTREE_64 port ( PIN:in std_logic_vector(0 to 63); GIN:in std_logic_vector(0 to 64); PHI:in std_logic; GOUT:out std_logic_vector(0 to 64); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_64 port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 64); SUM: out std_logic_vector(0 to 63); COUT: out std_logic ); end component; component DBLC_0_64 port ( PIN: in std_logic_vector(0 to 63); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 62); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_1_64 port ( PIN: in std_logic_vector(0 to 62); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 60); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_2_64 port ( PIN: in std_logic_vector(0 to 60); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 56); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_3_64 port ( PIN: in std_logic_vector(0 to 56); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 48); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_4_64 port ( PIN: in std_logic_vector(0 to 48); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 32); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_5_64 port ( PIN: in std_logic_vector(0 to 32); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_0_128 port ( PIN: in std_logic_vector(0 to 127); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 126); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_1_128 port ( PIN: in std_logic_vector(0 to 126); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 124); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_2_128 port ( PIN: in std_logic_vector(0 to 124); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 120); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_3_128 port ( PIN: in std_logic_vector(0 to 120); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 112); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_4_128 port ( PIN: in std_logic_vector(0 to 112); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 96); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_5_128 port ( PIN: in std_logic_vector(0 to 96); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 64); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_6_128 port ( PIN: in std_logic_vector(0 to 64); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 128) ); end component; component PRESTAGE_128 port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 127); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLCTREE_128 port ( PIN:in std_logic_vector(0 to 127); GIN:in std_logic_vector(0 to 128); PHI:in std_logic; GOUT:out std_logic_vector(0 to 128); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_128 port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 128); SUM: out std_logic_vector(0 to 127); COUT: out std_logic ); end component; component BOOTHCODER_18_18 port ( OPA: in std_logic_vector(0 to 17); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 188) ); end component; component WALLACE_18_18 port ( SUMMAND: in std_logic_vector(0 to 188); CARRY: out std_logic_vector(0 to 33); SUM: out std_logic_vector(0 to 34) ); end component; component DBLCADDER_64_64 port ( OPA:in std_logic_vector(0 to 63); OPB:in std_logic_vector(0 to 63); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 63); COUT:out std_logic ); end component; component BOOTHCODER_34_10 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 9); SUMMAND: out std_logic_vector(0 to 184) ); end component; component WALLACE_34_10 port ( SUMMAND: in std_logic_vector(0 to 184); CARRY: out std_logic_vector(0 to 41); SUM: out std_logic_vector(0 to 42) ); end component; component BOOTHCODER_34_18 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 332) ); end component; component WALLACE_34_18 port ( SUMMAND: in std_logic_vector(0 to 332); CARRY: out std_logic_vector(0 to 49); SUM: out std_logic_vector(0 to 50) ); end component; component BOOTHCODER_34_34 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 33); SUMMAND: out std_logic_vector(0 to 628) ); end component; component WALLACE_34_34 port ( SUMMAND: in std_logic_vector(0 to 628); CARRY: out std_logic_vector(0 to 65); SUM: out std_logic_vector(0 to 66) ); end component; component DBLCADDER_128_128 port ( OPA:in std_logic_vector(0 to 127); OPB:in std_logic_vector(0 to 127); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 127); COUT:out std_logic ); end component; component MULTIPLIER_18_18 generic (mulpipe : integer := 0); port(MULTIPLICAND: in std_logic_vector(0 to 17); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_ulogic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_10 port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 9); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_18 port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_34 generic (mulpipe : integer := 0); port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 33); PHI: in std_logic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 127)); end component; end; ------------------------------------------------------------ -- START: Entities used within the Modified Booth Recoding ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity FLIPFLOP is port ( DIN: in std_logic; CLK: in std_logic; DOUT: out std_logic ); end FLIPFLOP; architecture FLIPFLOP of FLIPFLOP is begin process(CLK) begin if(CLK='1')and(CLK'event)then DOUT <= DIN; end if; end process; end FLIPFLOP; library ieee; use ieee.std_logic_1164.all; entity PP_LOW is port ( ONEPOS, ONENEG, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end PP_LOW; architecture PP_LOW of PP_LOW is begin PPBIT <= (ONEPOS and INA) or (ONENEG and INB) or TWONEG; end PP_LOW; library ieee; use ieee.std_logic_1164.all; entity PP_MIDDLE is port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB, INC, IND: in std_logic; PPBIT: out std_logic ); end PP_MIDDLE; architecture PP_MIDDLE of PP_MIDDLE is begin PPBIT <= not((not(INA and TWOPOS)) and (not(INB and TWONEG)) and (not(INC and ONEPOS)) and (not(IND and ONENEG))); end PP_MIDDLE; library ieee; use ieee.std_logic_1164.all; entity PP_HIGH is port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end PP_HIGH; architecture PP_HIGH of PP_HIGH is begin PPBIT <= not ((INA and ONEPOS) or (INB and ONENEG) or (INA and TWOPOS) or (INB and TWONEG)); end PP_HIGH; library ieee; use ieee.std_logic_1164.all; entity R_GATE is port ( INA, INB, INC: in std_logic; PPBIT: out std_logic ); end R_GATE; architecture R_GATE of R_GATE is begin PPBIT <= (not(INA and INB)) and INC; end R_GATE; library ieee; use ieee.std_logic_1164.all; entity DECODER is port ( INA, INB, INC: in std_logic; TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic ); end DECODER; architecture DECODER of DECODER is begin TWOPOS <= not(not(INA and INB and (not INC))); TWONEG <= not(not((not INA) and (not INB) and INC)); ONEPOS <= ((not INA) and INB and (not INC)) or ((not INC) and (not INB) and INA); ONENEG <= (INA and (not INB) and INC) or (INC and INB and (not INA)); end DECODER; library ieee; use ieee.std_logic_1164.all; entity FULL_ADDER is port ( DATA_A, DATA_B, DATA_C: in std_logic; SAVE, CARRY: out std_logic ); end FULL_ADDER; architecture FULL_ADDER of FULL_ADDER is signal TMP: std_logic; begin TMP <= DATA_A xor DATA_B; SAVE <= TMP xor DATA_C; CARRY <= not((not (TMP and DATA_C)) and (not (DATA_A and DATA_B))); end FULL_ADDER; library ieee; use ieee.std_logic_1164.all; entity HALF_ADDER is port ( DATA_A, DATA_B: in std_logic; SAVE, CARRY: out std_logic ); end HALF_ADDER; architecture HALF_ADDER of HALF_ADDER is begin SAVE <= DATA_A xor DATA_B; CARRY <= DATA_A and DATA_B; end HALF_ADDER; library ieee; use ieee.std_logic_1164.all; entity INVBLOCK is port ( GIN,PHI:in std_logic; GOUT:out std_logic ); end INVBLOCK; architecture INVBLOCK_regular of INVBLOCK is begin GOUT <= not GIN; end INVBLOCK_regular; library ieee; use ieee.std_logic_1164.all; entity XXOR1 is port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end XXOR1; architecture XXOR_regular of XXOR1 is begin SUM <= (not (A xor B)) xor GIN; end XXOR_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK0 is port ( A,B,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK0; architecture BLOCK0_regular of BLOCK0 is begin POUT <= not(A or B); GOUT <= not(A and B); end BLOCK0_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK1 is port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK1; architecture BLOCK1_regular of BLOCK1 is begin POUT <= not(PIN1 or PIN2); GOUT <= not(GIN2 and (PIN2 or GIN1)); end BLOCK1_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK2 is port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK2; architecture BLOCK2_regular of BLOCK2 is begin POUT <= not(PIN1 and PIN2); GOUT <= not(GIN2 or (PIN2 and GIN1)); end BLOCK2_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK1A is port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end BLOCK1A; architecture BLOCK1A_regular of BLOCK1A is begin GOUT <= not(GIN2 and (PIN2 or GIN1)); end BLOCK1A_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK2A is port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end BLOCK2A; architecture BLOCK2A_regular of BLOCK2A is begin GOUT <= not(GIN2 or (PIN2 and GIN1)); end BLOCK2A_regular; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_64 is port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 63); GOUT: out std_logic_vector(0 to 64) ); end PRESTAGE_64; architecture PRESTAGE of PRESTAGE_64 is begin -- PRESTAGE U1:for I in 0 to 63 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: Level 0 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_64 is port ( PIN: in std_logic_vector(0 to 63); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 62); GOUT: out std_logic_vector(0 to 64) ); end DBLC_0_64; architecture DBLC_0 of DBLC_0_64 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 64 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_64 is port ( PIN: in std_logic_vector(0 to 62); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 60); GOUT: out std_logic_vector(0 to 64) ); end DBLC_1_64; architecture DBLC_1 of DBLC_1_64 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 64 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_64 is port ( PIN: in std_logic_vector(0 to 60); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 56); GOUT: out std_logic_vector(0 to 64) ); end DBLC_2_64; architecture DBLC_2 of DBLC_2_64 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 64 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_64 is port ( PIN: in std_logic_vector(0 to 56); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 48); GOUT: out std_logic_vector(0 to 64) ); end DBLC_3_64; architecture DBLC_3 of DBLC_3_64 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 64 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_64 is port ( PIN: in std_logic_vector(0 to 48); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 32); GOUT: out std_logic_vector(0 to 64) ); end DBLC_4_64; architecture DBLC_4 of DBLC_4_64 is begin -- Architecture DBLC_4 U1: for I in 0 to 15 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 64 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; -- The DBLC-tree: Level 5 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_5_64 is port ( PIN: in std_logic_vector(0 to 32); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 64) ); end DBLC_5_64; architecture DBLC_5 of DBLC_5_64 is begin -- Architecture DBLC_5 U1: for I in 0 to 31 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 32 to 63 generate U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 64 to 64 generate U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I)); end generate U3; end DBLC_5; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_64 is port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 64); SUM: out std_logic_vector(0 to 63); COUT: out std_logic ); end XORSTAGE_64; architecture XORSTAGE of XORSTAGE_64 is begin -- XORSTAGE U2:for I in 0 to 63 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U1: BLOCK1A port map(PBIT,CARRY(0),CARRY(64),PHI,COUT); end XORSTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_64 is port ( PIN:in std_logic_vector(0 to 63); GIN:in std_logic_vector(0 to 64); PHI:in std_logic; GOUT:out std_logic_vector(0 to 64); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_64; architecture DBLCTREE of DBLCTREE_64 is signal INTPROP_0: std_logic_vector(0 to 62); signal INTGEN_0: std_logic_vector(0 to 64); signal INTPROP_1: std_logic_vector(0 to 60); signal INTGEN_1: std_logic_vector(0 to 64); signal INTPROP_2: std_logic_vector(0 to 56); signal INTGEN_2: std_logic_vector(0 to 64); signal INTPROP_3: std_logic_vector(0 to 48); signal INTGEN_3: std_logic_vector(0 to 64); signal INTPROP_4: std_logic_vector(0 to 32); signal INTGEN_4: std_logic_vector(0 to 64); begin -- Architecture DBLCTREE U_0: DBLC_0_64 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_64 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_64 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_64 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_64 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4); U_5: DBLC_5_64 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_64_64 is port ( OPA:in std_logic_vector(0 to 63); OPB:in std_logic_vector(0 to 63); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 63); COUT:out std_logic ); end DBLCADDER_64_64; architecture DBLCADDER of DBLCADDER_64_64 is signal INTPROP: std_logic_vector(0 to 63); signal INTGEN: std_logic_vector(0 to 64); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 64); begin -- Architecture DBLCADDER U1: PRESTAGE_64 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_64 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_64 port map(OPA(0 to 63),OPB(0 to 63),PBIT(0),PHI,CARRY(0 to 64),SUM,COUT); end DBLCADDER; ------------------------------------------------------------ -- END: Architectures used with the DBLC adder ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity XXOR2 is port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end XXOR2; architecture XXOR_true of XXOR2 is begin SUM <= (A xor B) xor GIN; end XXOR_true; -- -- Modgen adder created Fri Aug 16 14:47:23 2002 -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_32 is port ( PIN: in std_logic_vector(0 to 31); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 30); GOUT: out std_logic_vector(0 to 32) ); end DBLC_0_32; architecture DBLC_0 of DBLC_0_32 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 32 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_32 is port ( PIN: in std_logic_vector(0 to 30); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 28); GOUT: out std_logic_vector(0 to 32) ); end DBLC_1_32; architecture DBLC_1 of DBLC_1_32 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 32 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_32 is port ( PIN: in std_logic_vector(0 to 28); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 24); GOUT: out std_logic_vector(0 to 32) ); end DBLC_2_32; architecture DBLC_2 of DBLC_2_32 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 32 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_32 is port ( PIN: in std_logic_vector(0 to 24); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 16); GOUT: out std_logic_vector(0 to 32) ); end DBLC_3_32; architecture DBLC_3 of DBLC_3_32 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 32 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_32 is port ( PIN: in std_logic_vector(0 to 16); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 32) ); end DBLC_4_32; architecture DBLC_4 of DBLC_4_32 is begin -- Architecture DBLC_4 GOUT(0 to 15) <= GIN(0 to 15); U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 32 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_32 is port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 32); SUM: out std_logic_vector(0 to 31); COUT: out std_logic ); end XORSTAGE_32; architecture XORSTAGE of XORSTAGE_32 is begin -- XORSTAGE U2:for I in 0 to 15 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U3:for I in 16 to 31 generate U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U3; U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(32),PHI,COUT); end XORSTAGE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_32 is port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 31); GOUT: out std_logic_vector(0 to 32) ); end PRESTAGE_32; architecture PRESTAGE of PRESTAGE_32 is begin -- PRESTAGE U1:for I in 0 to 31 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_32 is port ( PIN:in std_logic_vector(0 to 31); GIN:in std_logic_vector(0 to 32); PHI:in std_logic; GOUT:out std_logic_vector(0 to 32); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_32; architecture DBLCTREE of DBLCTREE_32 is signal INTPROP_0: std_logic_vector(0 to 30); signal INTGEN_0: std_logic_vector(0 to 32); signal INTPROP_1: std_logic_vector(0 to 28); signal INTGEN_1: std_logic_vector(0 to 32); signal INTPROP_2: std_logic_vector(0 to 24); signal INTGEN_2: std_logic_vector(0 to 32); signal INTPROP_3: std_logic_vector(0 to 16); signal INTGEN_3: std_logic_vector(0 to 32); begin -- Architecture DBLCTREE U_0: DBLC_0_32 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_32 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_32 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_32 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_32 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_32_32 is port ( OPA:in std_logic_vector(0 to 31); OPB:in std_logic_vector(0 to 31); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 31); COUT:out std_logic ); end DBLCADDER_32_32; architecture DBLCADDER of DBLCADDER_32_32 is signal INTPROP: std_logic_vector(0 to 31); signal INTGEN: std_logic_vector(0 to 32); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 32); begin -- Architecture DBLCADDER U1: PRESTAGE_32 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_32 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_32 port map(OPA(0 to 31),OPB(0 to 31),PBIT(0),PHI,CARRY(0 to 32),SUM,COUT); end DBLCADDER; ------------------------------------------------------------ -- END: Architectures used with the DBLC adder ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_128 is port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 127); GOUT: out std_logic_vector(0 to 128) ); end PRESTAGE_128; architecture PRESTAGE of PRESTAGE_128 is begin -- PRESTAGE U1:for I in 0 to 127 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: Level 0 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_128 is port ( PIN: in std_logic_vector(0 to 127); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 126); GOUT: out std_logic_vector(0 to 128) ); end DBLC_0_128; architecture DBLC_0 of DBLC_0_128 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 128 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_128 is port ( PIN: in std_logic_vector(0 to 126); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 124); GOUT: out std_logic_vector(0 to 128) ); end DBLC_1_128; architecture DBLC_1 of DBLC_1_128 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 128 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_128 is port ( PIN: in std_logic_vector(0 to 124); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 120); GOUT: out std_logic_vector(0 to 128) ); end DBLC_2_128; architecture DBLC_2 of DBLC_2_128 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 128 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_128 is port ( PIN: in std_logic_vector(0 to 120); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 112); GOUT: out std_logic_vector(0 to 128) ); end DBLC_3_128; architecture DBLC_3 of DBLC_3_128 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 128 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_128 is port ( PIN: in std_logic_vector(0 to 112); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 96); GOUT: out std_logic_vector(0 to 128) ); end DBLC_4_128; architecture DBLC_4 of DBLC_4_128 is begin -- Architecture DBLC_4 U1: for I in 0 to 15 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 128 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; -- The DBLC-tree: Level 5 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_5_128 is port ( PIN: in std_logic_vector(0 to 96); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 64); GOUT: out std_logic_vector(0 to 128) ); end DBLC_5_128; architecture DBLC_5 of DBLC_5_128 is begin -- Architecture DBLC_5 U1: for I in 0 to 31 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 32 to 63 generate U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 64 to 128 generate U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I)); end generate U3; end DBLC_5; -- The DBLC-tree: Level 6 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_6_128 is port ( PIN: in std_logic_vector(0 to 64); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 128) ); end DBLC_6_128; architecture DBLC_6 of DBLC_6_128 is begin -- Architecture DBLC_6 GOUT(0 to 63) <= GIN(0 to 63); U2: for I in 64 to 127 generate U21: BLOCK1A port map(PIN(I-64),GIN(I-64),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 128 to 128 generate U31: BLOCK1 port map(PIN(I-128),PIN(I-64),GIN(I-64),GIN(I),PHI,POUT(I-128),GOUT(I)); end generate U3; end DBLC_6; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_128 is port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 128); SUM: out std_logic_vector(0 to 127); COUT: out std_logic ); end XORSTAGE_128; architecture XORSTAGE of XORSTAGE_128 is begin -- XORSTAGE U2:for I in 0 to 63 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U3:for I in 64 to 127 generate U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U3; U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(128),PHI,COUT); end XORSTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_128 is port ( PIN:in std_logic_vector(0 to 127); GIN:in std_logic_vector(0 to 128); PHI:in std_logic; GOUT:out std_logic_vector(0 to 128); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_128; architecture DBLCTREE of DBLCTREE_128 is signal INTPROP_0: std_logic_vector(0 to 126); signal INTGEN_0: std_logic_vector(0 to 128); signal INTPROP_1: std_logic_vector(0 to 124); signal INTGEN_1: std_logic_vector(0 to 128); signal INTPROP_2: std_logic_vector(0 to 120); signal INTGEN_2: std_logic_vector(0 to 128); signal INTPROP_3: std_logic_vector(0 to 112); signal INTGEN_3: std_logic_vector(0 to 128); signal INTPROP_4: std_logic_vector(0 to 96); signal INTGEN_4: std_logic_vector(0 to 128); signal INTPROP_5: std_logic_vector(0 to 64); signal INTGEN_5: std_logic_vector(0 to 128); begin -- Architecture DBLCTREE U_0: DBLC_0_128 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_128 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_128 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_128 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_128 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4); U_5: DBLC_5_128 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>INTPROP_5,GOUT=>INTGEN_5); U_6: DBLC_6_128 port map(PIN=>INTPROP_5,GIN=>INTGEN_5,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_128_128 is port ( OPA:in std_logic_vector(0 to 127); OPB:in std_logic_vector(0 to 127); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 127); COUT:out std_logic ); end DBLCADDER_128_128; architecture DBLCADDER of DBLCADDER_128_128 is signal INTPROP: std_logic_vector(0 to 127); signal INTGEN: std_logic_vector(0 to 128); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 128); begin -- Architecture DBLCADDER U1: PRESTAGE_128 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_128 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_128 port map(OPA(0 to 127),OPB(0 to 127),PBIT(0),PHI,CARRY(0 to 128),SUM,COUT); end DBLCADDER; -- -- Modified Booth algorithm architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_18_18 is port ( OPA: in std_logic_vector(0 to 17); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 188) ); end BOOTHCODER_18_18; ------------------------------------------------------------ -- END: Entities used within the Modified Booth Recoding ------------------------------------------------------------ architecture BOOTHCODER of BOOTHCODER_18_18 is -- Components used in the architecture -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 17); signal INT_MULTIPLIER: std_logic_vector(0 to 35); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); PPH_0:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); SUMMAND(100) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_17:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_18:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_19:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_20:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_21:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_22:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_23:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_24:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_25:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_26:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_27:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_28:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_29:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_30:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_31:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_32:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(101) ); PPM_33:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(109) ); SUMMAND(110) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(118) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_34:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_35:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_36:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_37:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_38:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_39:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_40:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_41:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_42:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_43:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_44:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_45:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_46:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_47:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(102) ); PPM_48:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(111) ); PPM_49:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(119) ); PPM_50:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(126) ); SUMMAND(127) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(134) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_51:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_52:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_53:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_54:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_55:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_56:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_57:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_58:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_59:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_60:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_61:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_62:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(103) ); PPM_63:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(112) ); PPM_64:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(120) ); PPM_65:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(128) ); PPM_66:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(135) ); PPM_67:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(141) ); SUMMAND(142) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(148) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_68:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_69:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_70:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_71:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_72:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_73:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_74:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_75:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_76:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_77:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(104) ); PPM_78:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(113) ); PPM_79:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(121) ); PPM_80:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(129) ); PPM_81:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(136) ); PPM_82:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(143) ); PPM_83:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(149) ); PPM_84:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(154) ); SUMMAND(155) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_85:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_86:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_87:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_88:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_89:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_90:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_91:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_92:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(105) ); PPM_93:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(114) ); PPM_94:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(122) ); PPM_95:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(130) ); PPM_96:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(137) ); PPM_97:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(144) ); PPM_98:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(150) ); PPM_99:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(156) ); PPM_100:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(161) ); PPM_101:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(165) ); SUMMAND(166) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(170) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_102:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_103:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_104:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_105:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_106:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_107:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(106) ); PPM_108:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(115) ); PPM_109:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(123) ); PPM_110:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(131) ); PPM_111:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(138) ); PPM_112:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(145) ); PPM_113:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(151) ); PPM_114:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(157) ); PPM_115:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(162) ); PPM_116:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(167) ); PPM_117:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(171) ); PPM_118:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(174) ); SUMMAND(175) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(178) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_119:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_120:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_121:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_122:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(107) ); PPM_123:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(116) ); PPM_124:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(124) ); PPM_125:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(132) ); PPM_126:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(139) ); PPM_127:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(146) ); PPM_128:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(152) ); PPM_129:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(158) ); PPM_130:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(163) ); PPM_131:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(168) ); PPM_132:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(172) ); PPM_133:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(176) ); PPM_134:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(179) ); PPM_135:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(181) ); SUMMAND(182) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(184) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_136:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_137:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(108) ); PPM_138:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(117) ); PPM_139:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(125) ); PPM_140:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(133) ); PPM_141:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(140) ); PPM_142:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(147) ); PPM_143:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(153) ); PPM_144:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(159) ); PPM_145:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(164) ); PPM_146:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(169) ); PPM_147:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(173) ); PPM_148:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(177) ); PPM_149:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(180) ); PPM_150:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(183) ); PPM_151:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(185) ); PPM_152:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(186) ); SUMMAND(187) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(188) ); -- Begin partial product 9 end BOOTHCODER; ------------------------------------------------------------ -- END: Architectures used with the Modified Booth recoding ------------------------------------------------------------ -- -- Wallace tree architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_18_18 is port ( SUMMAND: in std_logic_vector(0 to 188); CARRY: out std_logic_vector(0 to 33); SUM: out std_logic_vector(0 to 34) ); end WALLACE_18_18; ------------------------------------------------------------ -- END: Entities within the Wallace-tree ------------------------------------------------------------ architecture WALLACE of WALLACE_18_18 is -- Components used in the netlist -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 114); signal INT_SUM: std_logic_vector(0 to 158); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin NO stage INT_SUM(76) <= SUMMAND(108); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(77), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_CARRY(49), DATA_C => INT_CARRY(50), SAVE => INT_SUM(78), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(51); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(77), DATA_B => INT_SUM(78), DATA_C => INT_SUM(79), SAVE => INT_SUM(80), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin NO stage INT_SUM(81) <= INT_CARRY(52); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(82) <= INT_CARRY(53); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_SUM(82), SAVE => INT_SUM(83), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin NO stage INT_SUM(84) <= INT_CARRY(54); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_64:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(83), DATA_B => INT_SUM(84), DATA_C => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End FA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_65:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(109), DATA_B => SUMMAND(110), DATA_C => SUMMAND(111), SAVE => INT_SUM(85), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(112), DATA_B => SUMMAND(113), DATA_C => SUMMAND(114), SAVE => INT_SUM(86), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117), SAVE => INT_SUM(87), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58), SAVE => INT_SUM(88), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(59), DATA_C => INT_CARRY(60), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_CARRY(61), SAVE => INT_SUM(91), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(91), DATA_B => INT_CARRY(62), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End HA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_72:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), DATA_C => SUMMAND(120), SAVE => INT_SUM(92), CARRY => INT_CARRY(70) ); ---- End FA stage ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(121), DATA_B => SUMMAND(122), DATA_C => SUMMAND(123), SAVE => INT_SUM(93), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(94) <= SUMMAND(124); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(95) <= SUMMAND(125); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_SUM(94), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin NO stage INT_SUM(97) <= INT_SUM(95); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(63), SAVE => INT_SUM(98), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(64), DATA_B => INT_CARRY(65), DATA_C => INT_CARRY(66), SAVE => INT_SUM(99), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(67), SAVE => INT_SUM(100), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin NO stage INT_SUM(101) <= INT_CARRY(68); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(69), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_79:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(102), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(103), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => INT_CARRY(70), SAVE => INT_SUM(104), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin NO stage INT_SUM(105) <= INT_CARRY(71); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_82:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_SUM(104), SAVE => INT_SUM(106), CARRY => INT_CARRY(79) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(105), DATA_B => INT_CARRY(72), SAVE => INT_SUM(107), CARRY => INT_CARRY(80) ); ---- End HA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(73), SAVE => INT_SUM(108), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin NO stage INT_SUM(109) <= INT_CARRY(74); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(75), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(134), DATA_B => SUMMAND(135), DATA_C => SUMMAND(136), SAVE => INT_SUM(110), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(137), DATA_B => SUMMAND(138), DATA_C => SUMMAND(139), SAVE => INT_SUM(111), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(112) <= SUMMAND(140); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_SUM(112), SAVE => INT_SUM(113), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), DATA_C => INT_CARRY(78), SAVE => INT_SUM(114), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_CARRY(79), SAVE => INT_SUM(115), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin NO stage INT_SUM(116) <= INT_CARRY(80); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(81), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_91:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143), SAVE => INT_SUM(117), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin FA stage FA_92:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146), SAVE => INT_SUM(118), CARRY => INT_CARRY(88) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= SUMMAND(147); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_SUM(119), SAVE => INT_SUM(120), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83), SAVE => INT_SUM(121), CARRY => INT_CARRY(90) ); ---- End HA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(84), SAVE => INT_SUM(122), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= INT_CARRY(85); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(86), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), DATA_C => SUMMAND(150), SAVE => INT_SUM(124), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(151), DATA_B => SUMMAND(152), DATA_C => SUMMAND(153), SAVE => INT_SUM(125), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(87), SAVE => INT_SUM(126), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin NO stage INT_SUM(127) <= INT_CARRY(88); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_99:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(89), SAVE => INT_SUM(128), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin NO stage INT_SUM(129) <= INT_CARRY(90); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(91), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_101:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(154), DATA_B => SUMMAND(155), DATA_C => SUMMAND(156), SAVE => INT_SUM(130), CARRY => INT_CARRY(96) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(157), DATA_B => SUMMAND(158), DATA_C => SUMMAND(159), SAVE => INT_SUM(131), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), DATA_C => INT_CARRY(92), SAVE => INT_SUM(132), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin NO stage INT_SUM(133) <= INT_CARRY(93); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(94), SAVE => INT_SUM(134), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(134), DATA_B => INT_CARRY(95), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End HA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_105:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(160), DATA_B => SUMMAND(161), DATA_C => SUMMAND(162), SAVE => INT_SUM(135), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(163), DATA_B => SUMMAND(164), SAVE => INT_SUM(136), CARRY => INT_CARRY(101) ); ---- End HA stage ---- Begin FA stage FA_106:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_CARRY(96), SAVE => INT_SUM(137), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin NO stage INT_SUM(138) <= INT_CARRY(97); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_CARRY(98), SAVE => INT_SUM(139), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(139), DATA_B => INT_CARRY(99), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_108:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(140), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), SAVE => INT_SUM(141), CARRY => INT_CARRY(105) ); ---- End HA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(100), SAVE => INT_SUM(142), CARRY => INT_CARRY(106) ); ---- End FA stage ---- Begin NO stage INT_SUM(143) <= INT_CARRY(101); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(102), SAVE => INT_SUM(144), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(144), DATA_B => INT_CARRY(103), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End HA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_111:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172), SAVE => INT_SUM(145), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(173), DATA_B => INT_CARRY(104), DATA_C => INT_CARRY(105), SAVE => INT_SUM(146), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin FA stage FA_113:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(106), SAVE => INT_SUM(147), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(147), DATA_B => INT_CARRY(107), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_114:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(148), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin NO stage INT_SUM(149) <= SUMMAND(177); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(108), SAVE => INT_SUM(150), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin NO stage INT_SUM(151) <= INT_CARRY(109); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(110), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_117:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(178), DATA_B => SUMMAND(179), DATA_C => SUMMAND(180), SAVE => INT_SUM(152), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin NO stage INT_SUM(153) <= INT_SUM(152); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(154) <= INT_CARRY(111); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_CARRY(112), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_119:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(181), DATA_B => SUMMAND(182), DATA_C => SUMMAND(183), SAVE => INT_SUM(155), CARRY => INT_CARRY(114) ); ---- End FA stage ---- Begin NO stage INT_SUM(156) <= INT_CARRY(113); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(155), DATA_B => INT_SUM(156), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End HA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin NO stage INT_SUM(157) <= SUMMAND(184); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(158) <= SUMMAND(185); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_120:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(114), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin HA stage HA_26:HALF_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End HA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin NO stage SUM(34) <= SUMMAND(188); -- At Level 5 ---- End NO stage -- End WT-branch 35 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_18_18 is generic (mulpipe : integer := 0); port ( MULTIPLICAND: in std_logic_vector(0 to 17); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_ulogic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_18_18; architecture MULTIPLIER of MULTIPLIER_18_18 is signal PPBIT:std_logic_vector(0 to 188); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_CARRYR: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal INT_SUMR: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_18_18 port map ( OPA(0 to 17) => MULTIPLICAND(0 to 17), OPB(0 to 17) => MULTIPLIER(0 to 17), SUMMAND(0 to 188) => PPBIT(0 to 188) ); W:WALLACE_18_18 port map ( SUMMAND(0 to 188) => PPBIT(0 to 188), CARRY(0 to 33) => INT_CARRY(1 to 34), SUM(0 to 34) => INT_SUM(0 to 34) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(35) <= LOGIC_ZERO; INT_CARRY(36) <= LOGIC_ZERO; INT_CARRY(37) <= LOGIC_ZERO; INT_CARRY(38) <= LOGIC_ZERO; INT_CARRY(39) <= LOGIC_ZERO; INT_CARRY(40) <= LOGIC_ZERO; INT_CARRY(41) <= LOGIC_ZERO; INT_CARRY(42) <= LOGIC_ZERO; INT_CARRY(43) <= LOGIC_ZERO; INT_CARRY(44) <= LOGIC_ZERO; INT_CARRY(45) <= LOGIC_ZERO; INT_CARRY(46) <= LOGIC_ZERO; INT_CARRY(47) <= LOGIC_ZERO; INT_CARRY(48) <= LOGIC_ZERO; INT_CARRY(49) <= LOGIC_ZERO; INT_CARRY(50) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(35) <= LOGIC_ZERO; INT_SUM(36) <= LOGIC_ZERO; INT_SUM(37) <= LOGIC_ZERO; INT_SUM(38) <= LOGIC_ZERO; INT_SUM(39) <= LOGIC_ZERO; INT_SUM(40) <= LOGIC_ZERO; INT_SUM(41) <= LOGIC_ZERO; INT_SUM(42) <= LOGIC_ZERO; INT_SUM(43) <= LOGIC_ZERO; INT_SUM(44) <= LOGIC_ZERO; INT_SUM(45) <= LOGIC_ZERO; INT_SUM(46) <= LOGIC_ZERO; INT_SUM(47) <= LOGIC_ZERO; INT_SUM(48) <= LOGIC_ZERO; INT_SUM(49) <= LOGIC_ZERO; INT_SUM(50) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; INT_SUMR(35 to 63) <= INT_SUM(35 to 63); INT_CARRYR(35 to 63) <= INT_CARRY(35 to 63); INT_CARRYR(0) <= INT_CARRY(0); reg : if MULPIPE /= 0 generate process (PHI) begin if rising_edge(PHI ) then if (holdn = '1') then INT_SUMR(0 to 34) <= INT_SUM(0 to 34); INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34); end if; end if; end process; end generate; noreg : if MULPIPE = 0 generate INT_SUMR(0 to 34) <= INT_SUM(0 to 34); INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34); end generate; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUMR(0 to 63), OPB(0 to 63) => INT_CARRYR(0 to 63), CIN => LOGIC_ZERO, PHI => PHI , SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_10 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 9); SUMMAND: out std_logic_vector(0 to 184) ); end BOOTHCODER_34_10; architecture BOOTHCODER of BOOTHCODER_34_10 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 19); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(40) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(45) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(50) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(55) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(60) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(65) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(70) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(75) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(85) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(95) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(100) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(105) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(110) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(115) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(120) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(125) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(130) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(135) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(140) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(145) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(150) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(155) ); SUMMAND(156) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(41) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(46) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(51) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(56) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(61) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(66) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(71) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(76) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(86) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(96) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(101) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(106) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(111) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(116) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(121) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(126) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(131) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(136) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(141) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(146) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(151) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(157) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(161) ); SUMMAND(162) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(166) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(42) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(47) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(52) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(57) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(62) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(67) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(72) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(77) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(87) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(97) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(102) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(107) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(112) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(117) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(122) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(127) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(132) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(137) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(142) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(147) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(152) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(158) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(163) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(167) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(170) ); SUMMAND(171) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(174) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(43) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(48) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(53) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(58) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(63) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(68) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(73) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(78) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(88) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(98) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(103) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(108) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(113) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(118) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(123) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(128) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(133) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(138) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(143) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(148) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(153) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(159) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(164) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(168) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(172) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(175) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(177) ); SUMMAND(178) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(180) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(44) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(49) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(54) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(59) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(64) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(69) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(74) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(79) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(89) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(99) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(104) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(109) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(114) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(119) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(124) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(129) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(134) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(139) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(144) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(149) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(154) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(165) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(169) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(173) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(176) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(179) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(181) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(182) ); SUMMAND(183) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(184) ); -- Begin partial product 5 end BOOTHCODER; ------------------------------------------------------------ -- END: Architectures used with the Modified Booth recoding ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the Wallace-tree ------------------------------------------------------------ -- -- Wallace tree architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_10 is port ( SUMMAND: in std_logic_vector(0 to 184); CARRY: out std_logic_vector(0 to 41); SUM: out std_logic_vector(0 to 42) ); end WALLACE_34_10; architecture WALLACE of WALLACE_34_10 is signal INT_CARRY: std_logic_vector(0 to 95); signal INT_SUM: std_logic_vector(0 to 133); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End HA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_CARRY(9), SAVE => INT_SUM(18), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin NO stage INT_SUM(19) <= INT_CARRY(10); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(18), DATA_B => INT_SUM(19), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_16:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(40), DATA_B => SUMMAND(41), DATA_C => SUMMAND(42), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End FA stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(43), DATA_B => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End HA stage ---- Begin FA stage FA_17:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(20), DATA_B => INT_SUM(21), DATA_C => INT_CARRY(12), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin NO stage INT_SUM(23) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(22), DATA_B => INT_SUM(23), DATA_C => INT_CARRY(14), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End FA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_19:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(24), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End HA stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(24), DATA_B => INT_SUM(25), DATA_C => INT_CARRY(15), SAVE => INT_SUM(26), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin NO stage INT_SUM(27) <= INT_CARRY(16); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_21:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(26), DATA_B => INT_SUM(27), DATA_C => INT_CARRY(17), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End FA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(50), DATA_B => SUMMAND(51), DATA_C => SUMMAND(52), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(53), DATA_B => SUMMAND(54), SAVE => INT_SUM(29), CARRY => INT_CARRY(22) ); ---- End HA stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(28), DATA_B => INT_SUM(29), DATA_C => INT_CARRY(18), SAVE => INT_SUM(30), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin NO stage INT_SUM(31) <= INT_CARRY(19); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(30), DATA_B => INT_SUM(31), DATA_C => INT_CARRY(20), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_25:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(55), DATA_B => SUMMAND(56), DATA_C => SUMMAND(57), SAVE => INT_SUM(32), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(58), DATA_B => SUMMAND(59), SAVE => INT_SUM(33), CARRY => INT_CARRY(25) ); ---- End HA stage ---- Begin FA stage FA_26:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(32), DATA_B => INT_SUM(33), DATA_C => INT_CARRY(21), SAVE => INT_SUM(34), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(35) <= INT_CARRY(22); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_CARRY(23), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_28:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(60), DATA_B => SUMMAND(61), DATA_C => SUMMAND(62), SAVE => INT_SUM(36), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), SAVE => INT_SUM(37), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(36), DATA_B => INT_SUM(37), DATA_C => INT_CARRY(24), SAVE => INT_SUM(38), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(39) <= INT_CARRY(25); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(38), DATA_B => INT_SUM(39), DATA_C => INT_CARRY(26), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(65), DATA_B => SUMMAND(66), DATA_C => SUMMAND(67), SAVE => INT_SUM(40), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(68), DATA_B => SUMMAND(69), SAVE => INT_SUM(41), CARRY => INT_CARRY(31) ); ---- End HA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(40), DATA_B => INT_SUM(41), DATA_C => INT_CARRY(27), SAVE => INT_SUM(42), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin NO stage INT_SUM(43) <= INT_CARRY(28); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(42), DATA_B => INT_SUM(43), DATA_C => INT_CARRY(29), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_34:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(70), DATA_B => SUMMAND(71), DATA_C => SUMMAND(72), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(73), DATA_B => SUMMAND(74), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(30), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(31); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(32), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End FA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End HA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_CARRY(33), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End FA stage ---- Begin NO stage INT_SUM(51) <= INT_CARRY(34); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(50), DATA_B => INT_SUM(51), DATA_C => INT_CARRY(35), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End FA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_40:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(52), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), SAVE => INT_SUM(53), CARRY => INT_CARRY(40) ); ---- End HA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(52), DATA_B => INT_SUM(53), DATA_C => INT_CARRY(36), SAVE => INT_SUM(54), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(55) <= INT_CARRY(37); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(54), DATA_B => INT_SUM(55), DATA_C => INT_CARRY(38), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End FA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(85), DATA_B => SUMMAND(86), DATA_C => SUMMAND(87), SAVE => INT_SUM(56), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(88), DATA_B => SUMMAND(89), SAVE => INT_SUM(57), CARRY => INT_CARRY(43) ); ---- End HA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(56), DATA_B => INT_SUM(57), DATA_C => INT_CARRY(39), SAVE => INT_SUM(58), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(59) <= INT_CARRY(40); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(58), DATA_B => INT_SUM(59), DATA_C => INT_CARRY(41), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_46:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(60), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), SAVE => INT_SUM(61), CARRY => INT_CARRY(46) ); ---- End HA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(60), DATA_B => INT_SUM(61), DATA_C => INT_CARRY(42), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin NO stage INT_SUM(63) <= INT_CARRY(43); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(44), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_49:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(95), DATA_B => SUMMAND(96), DATA_C => SUMMAND(97), SAVE => INT_SUM(64), CARRY => INT_CARRY(48) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(98), DATA_B => SUMMAND(99), SAVE => INT_SUM(65), CARRY => INT_CARRY(49) ); ---- End HA stage ---- Begin FA stage FA_50:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_CARRY(45), SAVE => INT_SUM(66), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin NO stage INT_SUM(67) <= INT_CARRY(46); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(66), DATA_B => INT_SUM(67), DATA_C => INT_CARRY(47), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(100), DATA_B => SUMMAND(101), DATA_C => SUMMAND(102), SAVE => INT_SUM(68), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(103), DATA_B => SUMMAND(104), SAVE => INT_SUM(69), CARRY => INT_CARRY(52) ); ---- End HA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(68), DATA_B => INT_SUM(69), DATA_C => INT_CARRY(48), SAVE => INT_SUM(70), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin NO stage INT_SUM(71) <= INT_CARRY(49); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(70), DATA_B => INT_SUM(71), DATA_C => INT_CARRY(50), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_55:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(72), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), SAVE => INT_SUM(73), CARRY => INT_CARRY(55) ); ---- End HA stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(72), DATA_B => INT_SUM(73), DATA_C => INT_CARRY(51), SAVE => INT_SUM(74), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin NO stage INT_SUM(75) <= INT_CARRY(52); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_57:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(74), DATA_B => INT_SUM(75), DATA_C => INT_CARRY(53), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112), SAVE => INT_SUM(76), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), SAVE => INT_SUM(77), CARRY => INT_CARRY(58) ); ---- End HA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(54), SAVE => INT_SUM(78), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(55); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(56), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End FA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_61:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117), SAVE => INT_SUM(80), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), SAVE => INT_SUM(81), CARRY => INT_CARRY(61) ); ---- End HA stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_CARRY(57), SAVE => INT_SUM(82), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin NO stage INT_SUM(83) <= INT_CARRY(58); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(59), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End FA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_64:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(84), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), SAVE => INT_SUM(85), CARRY => INT_CARRY(64) ); ---- End HA stage ---- Begin FA stage FA_65:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(60), SAVE => INT_SUM(86), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin NO stage INT_SUM(87) <= INT_CARRY(61); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(62), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End FA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_67:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(125), DATA_B => SUMMAND(126), DATA_C => SUMMAND(127), SAVE => INT_SUM(88), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(128), DATA_B => SUMMAND(129), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End HA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(88), DATA_B => INT_SUM(89), DATA_C => INT_CARRY(63), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(91) <= INT_CARRY(64); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(90), DATA_B => INT_SUM(91), DATA_C => INT_CARRY(65), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End FA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_70:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(130), DATA_B => SUMMAND(131), DATA_C => SUMMAND(132), SAVE => INT_SUM(92), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(133), DATA_B => SUMMAND(134), SAVE => INT_SUM(93), CARRY => INT_CARRY(70) ); ---- End HA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66), SAVE => INT_SUM(94), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(67); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), SAVE => INT_SUM(97), CARRY => INT_CARRY(73) ); ---- End HA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(69), SAVE => INT_SUM(98), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin NO stage INT_SUM(99) <= INT_CARRY(70); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(71), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_76:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(140), DATA_B => SUMMAND(141), DATA_C => SUMMAND(142), SAVE => INT_SUM(100), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), SAVE => INT_SUM(101), CARRY => INT_CARRY(76) ); ---- End HA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(72), SAVE => INT_SUM(102), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin NO stage INT_SUM(103) <= INT_CARRY(73); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(74), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End FA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_79:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(145), DATA_B => SUMMAND(146), DATA_C => SUMMAND(147), SAVE => INT_SUM(104), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), SAVE => INT_SUM(105), CARRY => INT_CARRY(79) ); ---- End HA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(104), DATA_B => INT_SUM(105), DATA_C => INT_CARRY(75), SAVE => INT_SUM(106), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin NO stage INT_SUM(107) <= INT_CARRY(76); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(77), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_82:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152), SAVE => INT_SUM(108), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), SAVE => INT_SUM(109), CARRY => INT_CARRY(82) ); ---- End HA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(78), SAVE => INT_SUM(110), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(111) <= INT_CARRY(79); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(80), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End FA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(155), DATA_B => SUMMAND(156), DATA_C => SUMMAND(157), SAVE => INT_SUM(112), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(158), DATA_B => SUMMAND(159), DATA_C => SUMMAND(160), SAVE => INT_SUM(113), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_CARRY(81), SAVE => INT_SUM(114), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin NO stage INT_SUM(115) <= INT_CARRY(82); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(114), DATA_B => INT_SUM(115), DATA_C => INT_CARRY(83), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_89:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(161), DATA_B => SUMMAND(162), DATA_C => SUMMAND(163), SAVE => INT_SUM(116), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(164), DATA_B => SUMMAND(165), SAVE => INT_SUM(117), CARRY => INT_CARRY(88) ); ---- End HA stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(84), SAVE => INT_SUM(118), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= INT_CARRY(85); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_91:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(86), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End FA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(166), DATA_B => SUMMAND(167), DATA_C => SUMMAND(168), SAVE => INT_SUM(120), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin NO stage INT_SUM(121) <= SUMMAND(169); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(87), SAVE => INT_SUM(122), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= INT_CARRY(88); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(89), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_95:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172), SAVE => INT_SUM(124), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin NO stage INT_SUM(125) <= SUMMAND(173); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(90), SAVE => INT_SUM(126), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(126), DATA_B => INT_CARRY(91), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End HA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_97:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(127), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin NO stage INT_SUM(128) <= INT_SUM(127); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(129) <= INT_CARRY(92); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(93), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_99:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(130), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin NO stage INT_SUM(131) <= INT_CARRY(94); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End HA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin NO stage INT_SUM(132) <= SUMMAND(180); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(133) <= SUMMAND(181); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(95), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin HA stage HA_35:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End HA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin NO stage SUM(42) <= SUMMAND(184); -- At Level 3 ---- End NO stage -- End WT-branch 43 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_10 is port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 9); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_34_10; ------------------------------------------------------------ -- End: Multiplier Entitiy architecture MULTIPLIER of MULTIPLIER_34_10 is signal PPBIT:std_logic_vector(0 to 184); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_10 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 9) => MULTIPLIER(0 to 9), SUMMAND(0 to 184) => PPBIT(0 to 184) ); W:WALLACE_34_10 port map ( SUMMAND(0 to 184) => PPBIT(0 to 184), CARRY(0 to 41) => INT_CARRY(1 to 42), SUM(0 to 42) => INT_SUM(0 to 42) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(43) <= LOGIC_ZERO; INT_CARRY(44) <= LOGIC_ZERO; INT_CARRY(45) <= LOGIC_ZERO; INT_CARRY(46) <= LOGIC_ZERO; INT_CARRY(47) <= LOGIC_ZERO; INT_CARRY(48) <= LOGIC_ZERO; INT_CARRY(49) <= LOGIC_ZERO; INT_CARRY(50) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(43) <= LOGIC_ZERO; INT_SUM(44) <= LOGIC_ZERO; INT_SUM(45) <= LOGIC_ZERO; INT_SUM(46) <= LOGIC_ZERO; INT_SUM(47) <= LOGIC_ZERO; INT_SUM(48) <= LOGIC_ZERO; INT_SUM(49) <= LOGIC_ZERO; INT_SUM(50) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUM(0 to 63), OPB(0 to 63) => INT_CARRY(0 to 63), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_9 is port(X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(8 downto 0); P: out std_logic_vector(41 downto 0)); end MUL_33_9; library ieee; use ieee.std_logic_1164.all; architecture A of MUL_33_9 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 9); signal Q: std_logic_vector(0 to 63); signal CLK: std_logic; begin U1: MULTIPLIER_34_10 port map(A,B,CLK,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(8); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); end A; ------------------------------------------------------------ -- START: Entities within the Wallace-tree ------------------------------------------------------------ -- -- Modified Booth algorithm architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_18 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 332) ); end BOOTHCODER_34_18; architecture BOOTHCODER of BOOTHCODER_34_18 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 35); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(108) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(117) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(126) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(135) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(144) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(153) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(162) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(171) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(180) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(189) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(198) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(207) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(216) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(225) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(234) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(243) ); SUMMAND(244) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(100) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(109) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(118) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(127) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(136) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(145) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(154) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(163) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(172) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(181) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(190) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(199) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(208) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(217) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(226) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(235) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(245) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(253) ); SUMMAND(254) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(262) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(101) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(110) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(119) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(128) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(137) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(146) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(155) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(164) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(173) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(182) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(191) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(200) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(209) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(218) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(227) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(236) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(246) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(255) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(263) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(270) ); SUMMAND(271) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(278) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(102) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(111) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(120) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(129) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(138) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(147) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(156) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(165) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(174) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(183) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(192) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(201) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(210) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(219) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(228) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(237) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(247) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(256) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(264) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(272) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(279) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(285) ); SUMMAND(286) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(292) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(103) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(112) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(121) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(130) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(139) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(148) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(157) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(166) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(175) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(184) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(193) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(202) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(211) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(220) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(229) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(238) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(248) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(257) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(265) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(273) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(280) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(287) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(293) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(298) ); SUMMAND(299) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(304) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_165:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_166:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_167:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_168:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_169:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_170:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_171:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_172:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(104) ); PPM_173:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(113) ); PPM_174:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(122) ); PPM_175:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(131) ); PPM_176:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(140) ); PPM_177:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(149) ); PPM_178:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(158) ); PPM_179:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(167) ); PPM_180:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(176) ); PPM_181:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(185) ); PPM_182:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(194) ); PPM_183:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(203) ); PPM_184:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(212) ); PPM_185:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(221) ); PPM_186:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(230) ); PPM_187:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(239) ); PPM_188:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(249) ); PPM_189:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(258) ); PPM_190:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(266) ); PPM_191:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(274) ); PPM_192:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(281) ); PPM_193:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(288) ); PPM_194:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(294) ); PPM_195:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(300) ); PPM_196:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(305) ); PPM_197:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(309) ); SUMMAND(310) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(314) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_198:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_199:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_200:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_201:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_202:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_203:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(105) ); PPM_204:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(114) ); PPM_205:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(123) ); PPM_206:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(132) ); PPM_207:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(141) ); PPM_208:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(150) ); PPM_209:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(159) ); PPM_210:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(168) ); PPM_211:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(177) ); PPM_212:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(186) ); PPM_213:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(195) ); PPM_214:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(204) ); PPM_215:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(213) ); PPM_216:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(222) ); PPM_217:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(231) ); PPM_218:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(240) ); PPM_219:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(250) ); PPM_220:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(259) ); PPM_221:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(267) ); PPM_222:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(275) ); PPM_223:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(282) ); PPM_224:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(289) ); PPM_225:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(295) ); PPM_226:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(301) ); PPM_227:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(306) ); PPM_228:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(311) ); PPM_229:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(315) ); PPM_230:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(318) ); SUMMAND(319) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(322) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_231:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_232:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_233:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_234:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(106) ); PPM_235:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(115) ); PPM_236:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(124) ); PPM_237:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(133) ); PPM_238:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(142) ); PPM_239:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(151) ); PPM_240:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(160) ); PPM_241:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(169) ); PPM_242:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(178) ); PPM_243:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(187) ); PPM_244:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(196) ); PPM_245:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(205) ); PPM_246:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(214) ); PPM_247:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(223) ); PPM_248:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(232) ); PPM_249:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(241) ); PPM_250:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(251) ); PPM_251:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(260) ); PPM_252:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(268) ); PPM_253:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(276) ); PPM_254:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(283) ); PPM_255:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(290) ); PPM_256:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(296) ); PPM_257:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(302) ); PPM_258:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(307) ); PPM_259:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(312) ); PPM_260:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(316) ); PPM_261:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(320) ); PPM_262:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(323) ); PPM_263:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(325) ); SUMMAND(326) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(328) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_264:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_265:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(107) ); PPM_266:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(116) ); PPM_267:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(125) ); PPM_268:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(134) ); PPM_269:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(143) ); PPM_270:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(152) ); PPM_271:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(161) ); PPM_272:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(170) ); PPM_273:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(179) ); PPM_274:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(188) ); PPM_275:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(197) ); PPM_276:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(206) ); PPM_277:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(215) ); PPM_278:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(224) ); PPM_279:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(233) ); PPM_280:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(242) ); PPM_281:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(252) ); PPM_282:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(261) ); PPM_283:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(269) ); PPM_284:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(277) ); PPM_285:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(284) ); PPM_286:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(291) ); PPM_287:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(297) ); PPM_288:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(303) ); PPM_289:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(308) ); PPM_290:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(313) ); PPM_291:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(317) ); PPM_292:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(321) ); PPM_293:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(324) ); PPM_294:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(327) ); PPM_295:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(329) ); PPM_296:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(330) ); SUMMAND(331) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(332) ); -- Begin partial product 9 end BOOTHCODER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_18 is port ( SUMMAND: in std_logic_vector(0 to 332); CARRY: out std_logic_vector(0 to 49); SUM: out std_logic_vector(0 to 50) ); end WALLACE_34_18; architecture WALLACE of WALLACE_34_18 is -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 226); signal INT_SUM: std_logic_vector(0 to 286); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(76), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(49), DATA_B => INT_CARRY(50), DATA_C => INT_CARRY(51), SAVE => INT_SUM(77), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(52), SAVE => INT_SUM(78), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(53); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(54), SAVE => INT_SUM(80), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(80), DATA_B => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End HA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_64:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), DATA_C => SUMMAND(110), SAVE => INT_SUM(81), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin FA stage FA_65:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(111), DATA_B => SUMMAND(112), DATA_C => SUMMAND(113), SAVE => INT_SUM(82), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(114), DATA_B => SUMMAND(115), DATA_C => SUMMAND(116), SAVE => INT_SUM(83), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(81), DATA_B => INT_SUM(82), DATA_C => INT_SUM(83), SAVE => INT_SUM(84), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58), SAVE => INT_SUM(85), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(59), SAVE => INT_SUM(86), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(87) <= INT_CARRY(60); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(61), SAVE => INT_SUM(88), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(62), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End HA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_71:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(117), DATA_B => SUMMAND(118), DATA_C => SUMMAND(119), SAVE => INT_SUM(89), CARRY => INT_CARRY(70) ); ---- End FA stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(90), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125), SAVE => INT_SUM(91), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91), SAVE => INT_SUM(92), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(63), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65), SAVE => INT_SUM(93), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66), SAVE => INT_SUM(94), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(67); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68), SAVE => INT_SUM(96), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(96), DATA_B => INT_CARRY(69), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End HA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_78:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(97), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin FA stage FA_79:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(98), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134), SAVE => INT_SUM(99), CARRY => INT_CARRY(79) ); ---- End FA stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(97), DATA_B => INT_SUM(98), DATA_C => INT_SUM(99), SAVE => INT_SUM(100), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin FA stage FA_82:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(70), DATA_B => INT_CARRY(71), DATA_C => INT_CARRY(72), SAVE => INT_SUM(101), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(73), SAVE => INT_SUM(102), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin NO stage INT_SUM(103) <= INT_CARRY(74); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(75), SAVE => INT_SUM(104), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(104), DATA_B => INT_CARRY(76), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End HA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(105), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140), SAVE => INT_SUM(106), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143), SAVE => INT_SUM(107), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_SUM(107), SAVE => INT_SUM(108), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(77), DATA_B => INT_CARRY(78), DATA_C => INT_CARRY(79), SAVE => INT_SUM(109), CARRY => INT_CARRY(88) ); ---- End FA stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(80), SAVE => INT_SUM(110), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(111) <= INT_CARRY(81); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_91:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(82), SAVE => INT_SUM(112), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(112), DATA_B => INT_CARRY(83), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End HA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146), SAVE => INT_SUM(113), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(147), DATA_B => SUMMAND(148), DATA_C => SUMMAND(149), SAVE => INT_SUM(114), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152), SAVE => INT_SUM(115), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_SUM(115), SAVE => INT_SUM(116), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86), SAVE => INT_SUM(117), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(87), SAVE => INT_SUM(118), CARRY => INT_CARRY(96) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= INT_CARRY(88); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(89), SAVE => INT_SUM(120), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(120), DATA_B => INT_CARRY(90), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End HA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_99:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), DATA_C => SUMMAND(155), SAVE => INT_SUM(121), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158), SAVE => INT_SUM(122), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin FA stage FA_101:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161), SAVE => INT_SUM(123), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(121), DATA_B => INT_SUM(122), DATA_C => INT_SUM(123), SAVE => INT_SUM(124), CARRY => INT_CARRY(101) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(91), DATA_B => INT_CARRY(92), DATA_C => INT_CARRY(93), SAVE => INT_SUM(125), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(94), SAVE => INT_SUM(126), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin NO stage INT_SUM(127) <= INT_CARRY(95); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_105:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(96), SAVE => INT_SUM(128), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(128), DATA_B => INT_CARRY(97), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End HA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_106:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164), SAVE => INT_SUM(129), CARRY => INT_CARRY(105) ); ---- End FA stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(130), CARRY => INT_CARRY(106) ); ---- End FA stage ---- Begin FA stage FA_108:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170), SAVE => INT_SUM(131), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_SUM(131), SAVE => INT_SUM(132), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(98), DATA_B => INT_CARRY(99), DATA_C => INT_CARRY(100), SAVE => INT_SUM(133), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin FA stage FA_111:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(101), SAVE => INT_SUM(134), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin NO stage INT_SUM(135) <= INT_CARRY(102); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(134), DATA_B => INT_SUM(135), DATA_C => INT_CARRY(103), SAVE => INT_SUM(136), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(136), DATA_B => INT_CARRY(104), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End HA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_113:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173), SAVE => INT_SUM(137), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin FA stage FA_114:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(138), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(139), CARRY => INT_CARRY(114) ); ---- End FA stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_SUM(139), SAVE => INT_SUM(140), CARRY => INT_CARRY(115) ); ---- End FA stage ---- Begin FA stage FA_117:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(105), DATA_B => INT_CARRY(106), DATA_C => INT_CARRY(107), SAVE => INT_SUM(141), CARRY => INT_CARRY(116) ); ---- End FA stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(108), SAVE => INT_SUM(142), CARRY => INT_CARRY(117) ); ---- End FA stage ---- Begin NO stage INT_SUM(143) <= INT_CARRY(109); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_119:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(110), SAVE => INT_SUM(144), CARRY => INT_CARRY(118) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(144), DATA_B => INT_CARRY(111), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_120:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), DATA_C => SUMMAND(182), SAVE => INT_SUM(145), CARRY => INT_CARRY(119) ); ---- End FA stage ---- Begin FA stage FA_121:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(183), DATA_B => SUMMAND(184), DATA_C => SUMMAND(185), SAVE => INT_SUM(146), CARRY => INT_CARRY(120) ); ---- End FA stage ---- Begin FA stage FA_122:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), DATA_C => SUMMAND(188), SAVE => INT_SUM(147), CARRY => INT_CARRY(121) ); ---- End FA stage ---- Begin FA stage FA_123:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_SUM(147), SAVE => INT_SUM(148), CARRY => INT_CARRY(122) ); ---- End FA stage ---- Begin FA stage FA_124:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(112), DATA_B => INT_CARRY(113), DATA_C => INT_CARRY(114), SAVE => INT_SUM(149), CARRY => INT_CARRY(123) ); ---- End FA stage ---- Begin FA stage FA_125:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(115), SAVE => INT_SUM(150), CARRY => INT_CARRY(124) ); ---- End FA stage ---- Begin NO stage INT_SUM(151) <= INT_CARRY(116); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_126:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(117), SAVE => INT_SUM(152), CARRY => INT_CARRY(125) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(152), DATA_B => INT_CARRY(118), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End HA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_127:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(189), DATA_B => SUMMAND(190), DATA_C => SUMMAND(191), SAVE => INT_SUM(153), CARRY => INT_CARRY(126) ); ---- End FA stage ---- Begin FA stage FA_128:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(192), DATA_B => SUMMAND(193), DATA_C => SUMMAND(194), SAVE => INT_SUM(154), CARRY => INT_CARRY(127) ); ---- End FA stage ---- Begin FA stage FA_129:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197), SAVE => INT_SUM(155), CARRY => INT_CARRY(128) ); ---- End FA stage ---- Begin FA stage FA_130:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_SUM(155), SAVE => INT_SUM(156), CARRY => INT_CARRY(129) ); ---- End FA stage ---- Begin FA stage FA_131:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(119), DATA_B => INT_CARRY(120), DATA_C => INT_CARRY(121), SAVE => INT_SUM(157), CARRY => INT_CARRY(130) ); ---- End FA stage ---- Begin FA stage FA_132:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(156), DATA_B => INT_SUM(157), DATA_C => INT_CARRY(122), SAVE => INT_SUM(158), CARRY => INT_CARRY(131) ); ---- End FA stage ---- Begin NO stage INT_SUM(159) <= INT_CARRY(123); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_133:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(158), DATA_B => INT_SUM(159), DATA_C => INT_CARRY(124), SAVE => INT_SUM(160), CARRY => INT_CARRY(132) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(160), DATA_B => INT_CARRY(125), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_134:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200), SAVE => INT_SUM(161), CARRY => INT_CARRY(133) ); ---- End FA stage ---- Begin FA stage FA_135:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203), SAVE => INT_SUM(162), CARRY => INT_CARRY(134) ); ---- End FA stage ---- Begin FA stage FA_136:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206), SAVE => INT_SUM(163), CARRY => INT_CARRY(135) ); ---- End FA stage ---- Begin FA stage FA_137:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(161), DATA_B => INT_SUM(162), DATA_C => INT_SUM(163), SAVE => INT_SUM(164), CARRY => INT_CARRY(136) ); ---- End FA stage ---- Begin FA stage FA_138:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(126), DATA_B => INT_CARRY(127), DATA_C => INT_CARRY(128), SAVE => INT_SUM(165), CARRY => INT_CARRY(137) ); ---- End FA stage ---- Begin FA stage FA_139:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(164), DATA_B => INT_SUM(165), DATA_C => INT_CARRY(129), SAVE => INT_SUM(166), CARRY => INT_CARRY(138) ); ---- End FA stage ---- Begin NO stage INT_SUM(167) <= INT_CARRY(130); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_140:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(131), SAVE => INT_SUM(168), CARRY => INT_CARRY(139) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(168), DATA_B => INT_CARRY(132), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End HA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_141:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209), SAVE => INT_SUM(169), CARRY => INT_CARRY(140) ); ---- End FA stage ---- Begin FA stage FA_142:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212), SAVE => INT_SUM(170), CARRY => INT_CARRY(141) ); ---- End FA stage ---- Begin FA stage FA_143:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215), SAVE => INT_SUM(171), CARRY => INT_CARRY(142) ); ---- End FA stage ---- Begin FA stage FA_144:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(169), DATA_B => INT_SUM(170), DATA_C => INT_SUM(171), SAVE => INT_SUM(172), CARRY => INT_CARRY(143) ); ---- End FA stage ---- Begin FA stage FA_145:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135), SAVE => INT_SUM(173), CARRY => INT_CARRY(144) ); ---- End FA stage ---- Begin FA stage FA_146:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(172), DATA_B => INT_SUM(173), DATA_C => INT_CARRY(136), SAVE => INT_SUM(174), CARRY => INT_CARRY(145) ); ---- End FA stage ---- Begin NO stage INT_SUM(175) <= INT_CARRY(137); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_147:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(174), DATA_B => INT_SUM(175), DATA_C => INT_CARRY(138), SAVE => INT_SUM(176), CARRY => INT_CARRY(146) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(176), DATA_B => INT_CARRY(139), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End HA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_148:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218), SAVE => INT_SUM(177), CARRY => INT_CARRY(147) ); ---- End FA stage ---- Begin FA stage FA_149:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221), SAVE => INT_SUM(178), CARRY => INT_CARRY(148) ); ---- End FA stage ---- Begin FA stage FA_150:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), DATA_C => SUMMAND(224), SAVE => INT_SUM(179), CARRY => INT_CARRY(149) ); ---- End FA stage ---- Begin FA stage FA_151:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(177), DATA_B => INT_SUM(178), DATA_C => INT_SUM(179), SAVE => INT_SUM(180), CARRY => INT_CARRY(150) ); ---- End FA stage ---- Begin FA stage FA_152:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(140), DATA_B => INT_CARRY(141), DATA_C => INT_CARRY(142), SAVE => INT_SUM(181), CARRY => INT_CARRY(151) ); ---- End FA stage ---- Begin FA stage FA_153:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), DATA_C => INT_CARRY(143), SAVE => INT_SUM(182), CARRY => INT_CARRY(152) ); ---- End FA stage ---- Begin NO stage INT_SUM(183) <= INT_CARRY(144); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_154:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_CARRY(145), SAVE => INT_SUM(184), CARRY => INT_CARRY(153) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(184), DATA_B => INT_CARRY(146), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End HA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_155:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(225), DATA_B => SUMMAND(226), DATA_C => SUMMAND(227), SAVE => INT_SUM(185), CARRY => INT_CARRY(154) ); ---- End FA stage ---- Begin FA stage FA_156:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(228), DATA_B => SUMMAND(229), DATA_C => SUMMAND(230), SAVE => INT_SUM(186), CARRY => INT_CARRY(155) ); ---- End FA stage ---- Begin FA stage FA_157:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(231), DATA_B => SUMMAND(232), DATA_C => SUMMAND(233), SAVE => INT_SUM(187), CARRY => INT_CARRY(156) ); ---- End FA stage ---- Begin FA stage FA_158:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_SUM(187), SAVE => INT_SUM(188), CARRY => INT_CARRY(157) ); ---- End FA stage ---- Begin FA stage FA_159:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(147), DATA_B => INT_CARRY(148), DATA_C => INT_CARRY(149), SAVE => INT_SUM(189), CARRY => INT_CARRY(158) ); ---- End FA stage ---- Begin FA stage FA_160:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(188), DATA_B => INT_SUM(189), DATA_C => INT_CARRY(150), SAVE => INT_SUM(190), CARRY => INT_CARRY(159) ); ---- End FA stage ---- Begin NO stage INT_SUM(191) <= INT_CARRY(151); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_161:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(190), DATA_B => INT_SUM(191), DATA_C => INT_CARRY(152), SAVE => INT_SUM(192), CARRY => INT_CARRY(160) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(192), DATA_B => INT_CARRY(153), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End HA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_162:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(234), DATA_B => SUMMAND(235), DATA_C => SUMMAND(236), SAVE => INT_SUM(193), CARRY => INT_CARRY(161) ); ---- End FA stage ---- Begin FA stage FA_163:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(237), DATA_B => SUMMAND(238), DATA_C => SUMMAND(239), SAVE => INT_SUM(194), CARRY => INT_CARRY(162) ); ---- End FA stage ---- Begin FA stage FA_164:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242), SAVE => INT_SUM(195), CARRY => INT_CARRY(163) ); ---- End FA stage ---- Begin FA stage FA_165:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(193), DATA_B => INT_SUM(194), DATA_C => INT_SUM(195), SAVE => INT_SUM(196), CARRY => INT_CARRY(164) ); ---- End FA stage ---- Begin FA stage FA_166:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(154), DATA_B => INT_CARRY(155), DATA_C => INT_CARRY(156), SAVE => INT_SUM(197), CARRY => INT_CARRY(165) ); ---- End FA stage ---- Begin FA stage FA_167:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(196), DATA_B => INT_SUM(197), DATA_C => INT_CARRY(157), SAVE => INT_SUM(198), CARRY => INT_CARRY(166) ); ---- End FA stage ---- Begin NO stage INT_SUM(199) <= INT_CARRY(158); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_168:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(198), DATA_B => INT_SUM(199), DATA_C => INT_CARRY(159), SAVE => INT_SUM(200), CARRY => INT_CARRY(167) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(200), DATA_B => INT_CARRY(160), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End HA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_169:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245), SAVE => INT_SUM(201), CARRY => INT_CARRY(168) ); ---- End FA stage ---- Begin FA stage FA_170:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248), SAVE => INT_SUM(202), CARRY => INT_CARRY(169) ); ---- End FA stage ---- Begin FA stage FA_171:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251), SAVE => INT_SUM(203), CARRY => INT_CARRY(170) ); ---- End FA stage ---- Begin NO stage INT_SUM(204) <= SUMMAND(252); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_172:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(201), DATA_B => INT_SUM(202), DATA_C => INT_SUM(203), SAVE => INT_SUM(205), CARRY => INT_CARRY(171) ); ---- End FA stage ---- Begin FA stage FA_173:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(204), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162), SAVE => INT_SUM(206), CARRY => INT_CARRY(172) ); ---- End FA stage ---- Begin NO stage INT_SUM(207) <= INT_CARRY(163); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_174:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207), SAVE => INT_SUM(208), CARRY => INT_CARRY(173) ); ---- End FA stage ---- Begin NO stage INT_SUM(209) <= INT_CARRY(164); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(210) <= INT_CARRY(165); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_175:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_SUM(210), SAVE => INT_SUM(211), CARRY => INT_CARRY(174) ); ---- End FA stage ---- Begin NO stage INT_SUM(212) <= INT_CARRY(166); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_176:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(211), DATA_B => INT_SUM(212), DATA_C => INT_CARRY(167), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_177:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(253), DATA_B => SUMMAND(254), DATA_C => SUMMAND(255), SAVE => INT_SUM(213), CARRY => INT_CARRY(175) ); ---- End FA stage ---- Begin FA stage FA_178:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(256), DATA_B => SUMMAND(257), DATA_C => SUMMAND(258), SAVE => INT_SUM(214), CARRY => INT_CARRY(176) ); ---- End FA stage ---- Begin FA stage FA_179:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(259), DATA_B => SUMMAND(260), DATA_C => SUMMAND(261), SAVE => INT_SUM(215), CARRY => INT_CARRY(177) ); ---- End FA stage ---- Begin FA stage FA_180:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(168), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170), SAVE => INT_SUM(216), CARRY => INT_CARRY(178) ); ---- End FA stage ---- Begin FA stage FA_181:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(213), DATA_B => INT_SUM(214), DATA_C => INT_SUM(215), SAVE => INT_SUM(217), CARRY => INT_CARRY(179) ); ---- End FA stage ---- Begin FA stage FA_182:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(216), DATA_B => INT_CARRY(171), DATA_C => INT_CARRY(172), SAVE => INT_SUM(218), CARRY => INT_CARRY(180) ); ---- End FA stage ---- Begin FA stage FA_183:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_CARRY(173), SAVE => INT_SUM(219), CARRY => INT_CARRY(181) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(219), DATA_B => INT_CARRY(174), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End HA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_184:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(262), DATA_B => SUMMAND(263), DATA_C => SUMMAND(264), SAVE => INT_SUM(220), CARRY => INT_CARRY(182) ); ---- End FA stage ---- Begin FA stage FA_185:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(265), DATA_B => SUMMAND(266), DATA_C => SUMMAND(267), SAVE => INT_SUM(221), CARRY => INT_CARRY(183) ); ---- End FA stage ---- Begin NO stage INT_SUM(222) <= SUMMAND(268); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(223) <= SUMMAND(269); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_186:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_SUM(222), SAVE => INT_SUM(224), CARRY => INT_CARRY(184) ); ---- End FA stage ---- Begin NO stage INT_SUM(225) <= INT_SUM(223); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_187:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(224), DATA_B => INT_SUM(225), DATA_C => INT_CARRY(175), SAVE => INT_SUM(226), CARRY => INT_CARRY(185) ); ---- End FA stage ---- Begin FA stage FA_188:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(176), DATA_B => INT_CARRY(177), DATA_C => INT_CARRY(178), SAVE => INT_SUM(227), CARRY => INT_CARRY(186) ); ---- End FA stage ---- Begin FA stage FA_189:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_CARRY(179), SAVE => INT_SUM(228), CARRY => INT_CARRY(187) ); ---- End FA stage ---- Begin NO stage INT_SUM(229) <= INT_CARRY(180); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_190:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(228), DATA_B => INT_SUM(229), DATA_C => INT_CARRY(181), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_191:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(270), DATA_B => SUMMAND(271), DATA_C => SUMMAND(272), SAVE => INT_SUM(230), CARRY => INT_CARRY(188) ); ---- End FA stage ---- Begin FA stage FA_192:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(273), DATA_B => SUMMAND(274), DATA_C => SUMMAND(275), SAVE => INT_SUM(231), CARRY => INT_CARRY(189) ); ---- End FA stage ---- Begin FA stage FA_193:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(276), DATA_B => SUMMAND(277), DATA_C => INT_CARRY(182), SAVE => INT_SUM(232), CARRY => INT_CARRY(190) ); ---- End FA stage ---- Begin NO stage INT_SUM(233) <= INT_CARRY(183); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_194:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(230), DATA_B => INT_SUM(231), DATA_C => INT_SUM(232), SAVE => INT_SUM(234), CARRY => INT_CARRY(191) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(233), DATA_B => INT_CARRY(184), SAVE => INT_SUM(235), CARRY => INT_CARRY(192) ); ---- End HA stage ---- Begin FA stage FA_195:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(234), DATA_B => INT_SUM(235), DATA_C => INT_CARRY(185), SAVE => INT_SUM(236), CARRY => INT_CARRY(193) ); ---- End FA stage ---- Begin NO stage INT_SUM(237) <= INT_CARRY(186); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_196:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_CARRY(187), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End FA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_197:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280), SAVE => INT_SUM(238), CARRY => INT_CARRY(194) ); ---- End FA stage ---- Begin FA stage FA_198:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283), SAVE => INT_SUM(239), CARRY => INT_CARRY(195) ); ---- End FA stage ---- Begin NO stage INT_SUM(240) <= SUMMAND(284); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_199:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(238), DATA_B => INT_SUM(239), DATA_C => INT_SUM(240), SAVE => INT_SUM(241), CARRY => INT_CARRY(196) ); ---- End FA stage ---- Begin FA stage FA_200:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190), SAVE => INT_SUM(242), CARRY => INT_CARRY(197) ); ---- End FA stage ---- Begin FA stage FA_201:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(241), DATA_B => INT_SUM(242), DATA_C => INT_CARRY(191), SAVE => INT_SUM(243), CARRY => INT_CARRY(198) ); ---- End FA stage ---- Begin NO stage INT_SUM(244) <= INT_CARRY(192); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_202:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(243), DATA_B => INT_SUM(244), DATA_C => INT_CARRY(193), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_203:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(285), DATA_B => SUMMAND(286), DATA_C => SUMMAND(287), SAVE => INT_SUM(245), CARRY => INT_CARRY(199) ); ---- End FA stage ---- Begin FA stage FA_204:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290), SAVE => INT_SUM(246), CARRY => INT_CARRY(200) ); ---- End FA stage ---- Begin NO stage INT_SUM(247) <= SUMMAND(291); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_205:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(245), DATA_B => INT_SUM(246), DATA_C => INT_SUM(247), SAVE => INT_SUM(248), CARRY => INT_CARRY(201) ); ---- End FA stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(194), DATA_B => INT_CARRY(195), SAVE => INT_SUM(249), CARRY => INT_CARRY(202) ); ---- End HA stage ---- Begin FA stage FA_206:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(248), DATA_B => INT_SUM(249), DATA_C => INT_CARRY(196), SAVE => INT_SUM(250), CARRY => INT_CARRY(203) ); ---- End FA stage ---- Begin NO stage INT_SUM(251) <= INT_CARRY(197); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_207:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(250), DATA_B => INT_SUM(251), DATA_C => INT_CARRY(198), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End FA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin FA stage FA_208:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(292), DATA_B => SUMMAND(293), DATA_C => SUMMAND(294), SAVE => INT_SUM(252), CARRY => INT_CARRY(204) ); ---- End FA stage ---- Begin FA stage FA_209:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(295), DATA_B => SUMMAND(296), DATA_C => SUMMAND(297), SAVE => INT_SUM(253), CARRY => INT_CARRY(205) ); ---- End FA stage ---- Begin FA stage FA_210:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(252), DATA_B => INT_SUM(253), DATA_C => INT_CARRY(199), SAVE => INT_SUM(254), CARRY => INT_CARRY(206) ); ---- End FA stage ---- Begin NO stage INT_SUM(255) <= INT_CARRY(200); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_211:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_CARRY(201), SAVE => INT_SUM(256), CARRY => INT_CARRY(207) ); ---- End FA stage ---- Begin NO stage INT_SUM(257) <= INT_CARRY(202); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_212:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(256), DATA_B => INT_SUM(257), DATA_C => INT_CARRY(203), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin FA stage FA_213:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(298), DATA_B => SUMMAND(299), DATA_C => SUMMAND(300), SAVE => INT_SUM(258), CARRY => INT_CARRY(208) ); ---- End FA stage ---- Begin FA stage FA_214:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(301), DATA_B => SUMMAND(302), DATA_C => SUMMAND(303), SAVE => INT_SUM(259), CARRY => INT_CARRY(209) ); ---- End FA stage ---- Begin FA stage FA_215:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(258), DATA_B => INT_SUM(259), DATA_C => INT_CARRY(204), SAVE => INT_SUM(260), CARRY => INT_CARRY(210) ); ---- End FA stage ---- Begin NO stage INT_SUM(261) <= INT_CARRY(205); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_216:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(206), SAVE => INT_SUM(262), CARRY => INT_CARRY(211) ); ---- End FA stage ---- Begin HA stage HA_35:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(262), DATA_B => INT_CARRY(207), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End HA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin FA stage FA_217:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(304), DATA_B => SUMMAND(305), DATA_C => SUMMAND(306), SAVE => INT_SUM(263), CARRY => INT_CARRY(212) ); ---- End FA stage ---- Begin HA stage HA_36:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(307), DATA_B => SUMMAND(308), SAVE => INT_SUM(264), CARRY => INT_CARRY(213) ); ---- End HA stage ---- Begin FA stage FA_218:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(263), DATA_B => INT_SUM(264), DATA_C => INT_CARRY(208), SAVE => INT_SUM(265), CARRY => INT_CARRY(214) ); ---- End FA stage ---- Begin NO stage INT_SUM(266) <= INT_CARRY(209); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_219:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(210), SAVE => INT_SUM(267), CARRY => INT_CARRY(215) ); ---- End FA stage ---- Begin HA stage HA_37:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(267), DATA_B => INT_CARRY(211), SAVE => SUM(42), CARRY => CARRY(42) ); ---- End HA stage -- End WT-branch 43 -- Begin WT-branch 44 ---- Begin FA stage FA_220:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311), SAVE => INT_SUM(268), CARRY => INT_CARRY(216) ); ---- End FA stage ---- Begin HA stage HA_38:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), SAVE => INT_SUM(269), CARRY => INT_CARRY(217) ); ---- End HA stage ---- Begin FA stage FA_221:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(268), DATA_B => INT_SUM(269), DATA_C => INT_CARRY(212), SAVE => INT_SUM(270), CARRY => INT_CARRY(218) ); ---- End FA stage ---- Begin NO stage INT_SUM(271) <= INT_CARRY(213); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_222:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(270), DATA_B => INT_SUM(271), DATA_C => INT_CARRY(214), SAVE => INT_SUM(272), CARRY => INT_CARRY(219) ); ---- End FA stage ---- Begin HA stage HA_39:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(272), DATA_B => INT_CARRY(215), SAVE => SUM(43), CARRY => CARRY(43) ); ---- End HA stage -- End WT-branch 44 -- Begin WT-branch 45 ---- Begin FA stage FA_223:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(314), DATA_B => SUMMAND(315), DATA_C => SUMMAND(316), SAVE => INT_SUM(273), CARRY => INT_CARRY(220) ); ---- End FA stage ---- Begin FA stage FA_224:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(317), DATA_B => INT_CARRY(216), DATA_C => INT_CARRY(217), SAVE => INT_SUM(274), CARRY => INT_CARRY(221) ); ---- End FA stage ---- Begin FA stage FA_225:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(273), DATA_B => INT_SUM(274), DATA_C => INT_CARRY(218), SAVE => INT_SUM(275), CARRY => INT_CARRY(222) ); ---- End FA stage ---- Begin HA stage HA_40:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(275), DATA_B => INT_CARRY(219), SAVE => SUM(44), CARRY => CARRY(44) ); ---- End HA stage -- End WT-branch 45 -- Begin WT-branch 46 ---- Begin FA stage FA_226:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320), SAVE => INT_SUM(276), CARRY => INT_CARRY(223) ); ---- End FA stage ---- Begin NO stage INT_SUM(277) <= SUMMAND(321); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_227:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(276), DATA_B => INT_SUM(277), DATA_C => INT_CARRY(220), SAVE => INT_SUM(278), CARRY => INT_CARRY(224) ); ---- End FA stage ---- Begin NO stage INT_SUM(279) <= INT_CARRY(221); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_228:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(278), DATA_B => INT_SUM(279), DATA_C => INT_CARRY(222), SAVE => SUM(45), CARRY => CARRY(45) ); ---- End FA stage -- End WT-branch 46 -- Begin WT-branch 47 ---- Begin FA stage FA_229:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(322), DATA_B => SUMMAND(323), DATA_C => SUMMAND(324), SAVE => INT_SUM(280), CARRY => INT_CARRY(225) ); ---- End FA stage ---- Begin NO stage INT_SUM(281) <= INT_SUM(280); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(282) <= INT_CARRY(223); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_230:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(281), DATA_B => INT_SUM(282), DATA_C => INT_CARRY(224), SAVE => SUM(46), CARRY => CARRY(46) ); ---- End FA stage -- End WT-branch 47 -- Begin WT-branch 48 ---- Begin FA stage FA_231:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(325), DATA_B => SUMMAND(326), DATA_C => SUMMAND(327), SAVE => INT_SUM(283), CARRY => INT_CARRY(226) ); ---- End FA stage ---- Begin NO stage INT_SUM(284) <= INT_CARRY(225); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_41:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(283), DATA_B => INT_SUM(284), SAVE => SUM(47), CARRY => CARRY(47) ); ---- End HA stage -- End WT-branch 48 -- Begin WT-branch 49 ---- Begin NO stage INT_SUM(285) <= SUMMAND(328); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(286) <= SUMMAND(329); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_232:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(285), DATA_B => INT_SUM(286), DATA_C => INT_CARRY(226), SAVE => SUM(48), CARRY => CARRY(48) ); ---- End FA stage -- End WT-branch 49 -- Begin WT-branch 50 ---- Begin HA stage HA_42:HALF_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(330), DATA_B => SUMMAND(331), SAVE => SUM(49), CARRY => CARRY(49) ); ---- End HA stage -- End WT-branch 50 -- Begin WT-branch 51 ---- Begin NO stage SUM(50) <= SUMMAND(332); -- At Level 5 ---- End NO stage -- End WT-branch 51 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_18 is port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_34_18; ------------------------------------------------------------ -- End: Multiplier Entitiy architecture MULTIPLIER of MULTIPLIER_34_18 is signal PPBIT:std_logic_vector(0 to 332); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_18 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 17) => MULTIPLIER(0 to 17), SUMMAND(0 to 332) => PPBIT(0 to 332) ); W:WALLACE_34_18 port map ( SUMMAND(0 to 332) => PPBIT(0 to 332), CARRY(0 to 49) => INT_CARRY(1 to 50), SUM(0 to 50) => INT_SUM(0 to 50) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUM(0 to 63), OPB(0 to 63) => INT_CARRY(0 to 63), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ -- -- Modgen multiplier created Fri Aug 16 16:29:15 2002 -- ------------------------------------------------------------ -- START: Multiplier Entitiy ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -- START: Top entity ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_17 is port(X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(16 downto 0); P: out std_logic_vector(49 downto 0)); end MUL_33_17; library ieee; use ieee.std_logic_1164.all; architecture A of MUL_33_17 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 17); signal Q: std_logic_vector(0 to 63); signal CLK: std_logic; begin U1: MULTIPLIER_34_18 port map(A,B,CLK,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(16); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); P(42) <= Q(42); P(43) <= Q(43); P(44) <= Q(44); P(45) <= Q(45); P(46) <= Q(46); P(47) <= Q(47); P(48) <= Q(48); P(49) <= Q(49); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_34 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 33); SUMMAND: out std_logic_vector(0 to 628) ); end BOOTHCODER_34_34; architecture BOOTHCODER of BOOTHCODER_34_34 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 67); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(110) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(120) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(132) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(143) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(156) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(168) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(182) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(195) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(210) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(224) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(240) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(255) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(272) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(288) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(306) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(323) ); SUMMAND(324) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(100) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(111) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(121) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(133) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(144) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(157) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(169) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(183) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(196) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(211) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(225) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(241) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(256) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(273) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(289) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(307) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(325) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(341) ); SUMMAND(342) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(358) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(101) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(112) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(122) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(134) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(145) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(158) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(170) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(184) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(197) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(212) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(226) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(242) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(257) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(274) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(290) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(308) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(326) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(343) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(359) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(374) ); SUMMAND(375) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(390) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(102) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(113) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(123) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(135) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(146) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(159) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(171) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(185) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(198) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(213) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(227) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(243) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(258) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(275) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(291) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(309) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(327) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(344) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(360) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(376) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(391) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(405) ); SUMMAND(406) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(420) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(103) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(114) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(124) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(136) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(147) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(172) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(186) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(199) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(214) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(228) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(244) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(259) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(276) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(292) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(310) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(328) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(345) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(361) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(377) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(392) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(407) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(421) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(434) ); SUMMAND(435) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(448) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_165:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_166:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_167:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_168:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_169:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_170:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_171:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_172:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(104) ); PPM_173:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(115) ); PPM_174:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(125) ); PPM_175:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(137) ); PPM_176:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(148) ); PPM_177:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(161) ); PPM_178:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(173) ); PPM_179:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(187) ); PPM_180:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(200) ); PPM_181:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(215) ); PPM_182:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(229) ); PPM_183:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(245) ); PPM_184:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(260) ); PPM_185:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(277) ); PPM_186:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(293) ); PPM_187:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(311) ); PPM_188:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(329) ); PPM_189:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(346) ); PPM_190:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(362) ); PPM_191:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(378) ); PPM_192:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(393) ); PPM_193:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(408) ); PPM_194:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(422) ); PPM_195:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(436) ); PPM_196:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(449) ); PPM_197:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(461) ); SUMMAND(462) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(474) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_198:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_199:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_200:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_201:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_202:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_203:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(105) ); PPM_204:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(116) ); PPM_205:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(126) ); PPM_206:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(138) ); PPM_207:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(149) ); PPM_208:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(162) ); PPM_209:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(174) ); PPM_210:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(188) ); PPM_211:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(201) ); PPM_212:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(216) ); PPM_213:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(230) ); PPM_214:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(246) ); PPM_215:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(261) ); PPM_216:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(278) ); PPM_217:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(294) ); PPM_218:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(312) ); PPM_219:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(330) ); PPM_220:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(347) ); PPM_221:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(363) ); PPM_222:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(379) ); PPM_223:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(394) ); PPM_224:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(409) ); PPM_225:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(423) ); PPM_226:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(437) ); PPM_227:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(450) ); PPM_228:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(463) ); PPM_229:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(475) ); PPM_230:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(486) ); SUMMAND(487) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(498) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_231:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_232:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_233:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_234:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(106) ); PPM_235:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(117) ); PPM_236:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(127) ); PPM_237:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(139) ); PPM_238:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(150) ); PPM_239:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(163) ); PPM_240:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(175) ); PPM_241:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(189) ); PPM_242:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(202) ); PPM_243:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(217) ); PPM_244:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(231) ); PPM_245:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(247) ); PPM_246:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(262) ); PPM_247:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(279) ); PPM_248:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(295) ); PPM_249:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(313) ); PPM_250:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(331) ); PPM_251:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(348) ); PPM_252:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(364) ); PPM_253:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(380) ); PPM_254:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(395) ); PPM_255:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(410) ); PPM_256:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(424) ); PPM_257:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(438) ); PPM_258:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(451) ); PPM_259:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(464) ); PPM_260:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(476) ); PPM_261:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(488) ); PPM_262:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(499) ); PPM_263:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(509) ); SUMMAND(510) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(520) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_264:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_265:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(107) ); PPM_266:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(118) ); PPM_267:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(128) ); PPM_268:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(140) ); PPM_269:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(151) ); PPM_270:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(164) ); PPM_271:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(176) ); PPM_272:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(190) ); PPM_273:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(203) ); PPM_274:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(218) ); PPM_275:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(232) ); PPM_276:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(248) ); PPM_277:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(263) ); PPM_278:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(280) ); PPM_279:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(296) ); PPM_280:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(314) ); PPM_281:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(332) ); PPM_282:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(349) ); PPM_283:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(365) ); PPM_284:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(381) ); PPM_285:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(396) ); PPM_286:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(411) ); PPM_287:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(425) ); PPM_288:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(439) ); PPM_289:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(452) ); PPM_290:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(465) ); PPM_291:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(477) ); PPM_292:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(489) ); PPM_293:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(500) ); PPM_294:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(511) ); PPM_295:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(521) ); PPM_296:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(530) ); SUMMAND(531) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(540) ); -- Begin partial product 9 -- Begin decoder block 10 DEC_9:DECODER -- Decoder of multiplier operand port map ( INA => OPB(17),INB => OPB(18),INC => OPB(19), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39) ); -- End decoder block 10 -- Begin partial product 10 PPL_9:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(108) ); RGATE_9:R_GATE port map ( INA => OPB(17),INB => OPB(18),INC => OPB(19), PPBIT => SUMMAND(109) ); PPM_297:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(119) ); PPM_298:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(129) ); PPM_299:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(141) ); PPM_300:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(152) ); PPM_301:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(165) ); PPM_302:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(177) ); PPM_303:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(191) ); PPM_304:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(204) ); PPM_305:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(219) ); PPM_306:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(233) ); PPM_307:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(249) ); PPM_308:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(264) ); PPM_309:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(281) ); PPM_310:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(297) ); PPM_311:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(315) ); PPM_312:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(333) ); PPM_313:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(350) ); PPM_314:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(366) ); PPM_315:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(382) ); PPM_316:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(397) ); PPM_317:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(412) ); PPM_318:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(426) ); PPM_319:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(440) ); PPM_320:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(453) ); PPM_321:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(466) ); PPM_322:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(478) ); PPM_323:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(490) ); PPM_324:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(501) ); PPM_325:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(512) ); PPM_326:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(522) ); PPM_327:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(532) ); PPM_328:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(541) ); PPM_329:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(549) ); SUMMAND(550) <= LOGIC_ONE; PPH_9:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(558) ); -- Begin partial product 10 -- Begin decoder block 11 DEC_10:DECODER -- Decoder of multiplier operand port map ( INA => OPB(19),INB => OPB(20),INC => OPB(21), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43) ); -- End decoder block 11 -- Begin partial product 11 PPL_10:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(130) ); RGATE_10:R_GATE port map ( INA => OPB(19),INB => OPB(20),INC => OPB(21), PPBIT => SUMMAND(131) ); PPM_330:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(142) ); PPM_331:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(153) ); PPM_332:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(166) ); PPM_333:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(178) ); PPM_334:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(192) ); PPM_335:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(205) ); PPM_336:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(220) ); PPM_337:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(234) ); PPM_338:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(250) ); PPM_339:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(265) ); PPM_340:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(282) ); PPM_341:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(298) ); PPM_342:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(316) ); PPM_343:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(334) ); PPM_344:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(351) ); PPM_345:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(367) ); PPM_346:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(383) ); PPM_347:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(398) ); PPM_348:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(413) ); PPM_349:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(427) ); PPM_350:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(441) ); PPM_351:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(454) ); PPM_352:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(467) ); PPM_353:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(479) ); PPM_354:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(491) ); PPM_355:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(502) ); PPM_356:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(513) ); PPM_357:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(523) ); PPM_358:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(533) ); PPM_359:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(542) ); PPM_360:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(551) ); PPM_361:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(559) ); PPM_362:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(566) ); SUMMAND(567) <= LOGIC_ONE; PPH_10:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(574) ); -- Begin partial product 11 -- Begin decoder block 12 DEC_11:DECODER -- Decoder of multiplier operand port map ( INA => OPB(21),INB => OPB(22),INC => OPB(23), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47) ); -- End decoder block 12 -- Begin partial product 12 PPL_11:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(154) ); RGATE_11:R_GATE port map ( INA => OPB(21),INB => OPB(22),INC => OPB(23), PPBIT => SUMMAND(155) ); PPM_363:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(167) ); PPM_364:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(179) ); PPM_365:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(193) ); PPM_366:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(206) ); PPM_367:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(221) ); PPM_368:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(235) ); PPM_369:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(251) ); PPM_370:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(266) ); PPM_371:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(283) ); PPM_372:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(299) ); PPM_373:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(317) ); PPM_374:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(335) ); PPM_375:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(352) ); PPM_376:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(368) ); PPM_377:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(384) ); PPM_378:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(399) ); PPM_379:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(414) ); PPM_380:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(428) ); PPM_381:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(442) ); PPM_382:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(455) ); PPM_383:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(468) ); PPM_384:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(480) ); PPM_385:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(492) ); PPM_386:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(503) ); PPM_387:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(514) ); PPM_388:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(524) ); PPM_389:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(534) ); PPM_390:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(543) ); PPM_391:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(552) ); PPM_392:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(560) ); PPM_393:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(568) ); PPM_394:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(575) ); PPM_395:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(581) ); SUMMAND(582) <= LOGIC_ONE; PPH_11:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(588) ); -- Begin partial product 12 -- Begin decoder block 13 DEC_12:DECODER -- Decoder of multiplier operand port map ( INA => OPB(23),INB => OPB(24),INC => OPB(25), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51) ); -- End decoder block 13 -- Begin partial product 13 PPL_12:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(180) ); RGATE_12:R_GATE port map ( INA => OPB(23),INB => OPB(24),INC => OPB(25), PPBIT => SUMMAND(181) ); PPM_396:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(194) ); PPM_397:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(207) ); PPM_398:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(222) ); PPM_399:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(236) ); PPM_400:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(252) ); PPM_401:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(267) ); PPM_402:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(284) ); PPM_403:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(300) ); PPM_404:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(318) ); PPM_405:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(336) ); PPM_406:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(353) ); PPM_407:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(369) ); PPM_408:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(385) ); PPM_409:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(400) ); PPM_410:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(415) ); PPM_411:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(429) ); PPM_412:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(443) ); PPM_413:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(456) ); PPM_414:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(469) ); PPM_415:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(481) ); PPM_416:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(493) ); PPM_417:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(504) ); PPM_418:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(515) ); PPM_419:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(525) ); PPM_420:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(535) ); PPM_421:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(544) ); PPM_422:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(553) ); PPM_423:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(561) ); PPM_424:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(569) ); PPM_425:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(576) ); PPM_426:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(583) ); PPM_427:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(589) ); PPM_428:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(594) ); SUMMAND(595) <= LOGIC_ONE; PPH_12:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(600) ); -- Begin partial product 13 -- Begin decoder block 14 DEC_13:DECODER -- Decoder of multiplier operand port map ( INA => OPB(25),INB => OPB(26),INC => OPB(27), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55) ); -- End decoder block 14 -- Begin partial product 14 PPL_13:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(208) ); RGATE_13:R_GATE port map ( INA => OPB(25),INB => OPB(26),INC => OPB(27), PPBIT => SUMMAND(209) ); PPM_429:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(223) ); PPM_430:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(237) ); PPM_431:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(253) ); PPM_432:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(268) ); PPM_433:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(285) ); PPM_434:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(301) ); PPM_435:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(319) ); PPM_436:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(337) ); PPM_437:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(354) ); PPM_438:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(370) ); PPM_439:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(386) ); PPM_440:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(401) ); PPM_441:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(416) ); PPM_442:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(430) ); PPM_443:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(444) ); PPM_444:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(457) ); PPM_445:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(470) ); PPM_446:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(482) ); PPM_447:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(494) ); PPM_448:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(505) ); PPM_449:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(516) ); PPM_450:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(526) ); PPM_451:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(536) ); PPM_452:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(545) ); PPM_453:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(554) ); PPM_454:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(562) ); PPM_455:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(570) ); PPM_456:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(577) ); PPM_457:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(584) ); PPM_458:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(590) ); PPM_459:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(596) ); PPM_460:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(601) ); PPM_461:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(605) ); SUMMAND(606) <= LOGIC_ONE; PPH_13:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(610) ); -- Begin partial product 14 -- Begin decoder block 15 DEC_14:DECODER -- Decoder of multiplier operand port map ( INA => OPB(27),INB => OPB(28),INC => OPB(29), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59) ); -- End decoder block 15 -- Begin partial product 15 PPL_14:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(238) ); RGATE_14:R_GATE port map ( INA => OPB(27),INB => OPB(28),INC => OPB(29), PPBIT => SUMMAND(239) ); PPM_462:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(254) ); PPM_463:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(269) ); PPM_464:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(286) ); PPM_465:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(302) ); PPM_466:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(320) ); PPM_467:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(338) ); PPM_468:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(355) ); PPM_469:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(371) ); PPM_470:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(387) ); PPM_471:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(402) ); PPM_472:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(417) ); PPM_473:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(431) ); PPM_474:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(445) ); PPM_475:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(458) ); PPM_476:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(471) ); PPM_477:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(483) ); PPM_478:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(495) ); PPM_479:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(506) ); PPM_480:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(517) ); PPM_481:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(527) ); PPM_482:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(537) ); PPM_483:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(546) ); PPM_484:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(555) ); PPM_485:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(563) ); PPM_486:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(571) ); PPM_487:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(578) ); PPM_488:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(585) ); PPM_489:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(591) ); PPM_490:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(597) ); PPM_491:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(602) ); PPM_492:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(607) ); PPM_493:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(611) ); PPM_494:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(614) ); SUMMAND(615) <= LOGIC_ONE; PPH_14:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(618) ); -- Begin partial product 15 -- Begin decoder block 16 DEC_15:DECODER -- Decoder of multiplier operand port map ( INA => OPB(29),INB => OPB(30),INC => OPB(31), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63) ); -- End decoder block 16 -- Begin partial product 16 PPL_15:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(270) ); RGATE_15:R_GATE port map ( INA => OPB(29),INB => OPB(30),INC => OPB(31), PPBIT => SUMMAND(271) ); PPM_495:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(287) ); PPM_496:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(303) ); PPM_497:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(321) ); PPM_498:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(339) ); PPM_499:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(356) ); PPM_500:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(372) ); PPM_501:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(388) ); PPM_502:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(403) ); PPM_503:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(418) ); PPM_504:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(432) ); PPM_505:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(446) ); PPM_506:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(459) ); PPM_507:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(472) ); PPM_508:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(484) ); PPM_509:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(496) ); PPM_510:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(507) ); PPM_511:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(518) ); PPM_512:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(528) ); PPM_513:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(538) ); PPM_514:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(547) ); PPM_515:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(556) ); PPM_516:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(564) ); PPM_517:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(572) ); PPM_518:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(579) ); PPM_519:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(586) ); PPM_520:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(592) ); PPM_521:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(598) ); PPM_522:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(603) ); PPM_523:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(608) ); PPM_524:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(612) ); PPM_525:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(616) ); PPM_526:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(619) ); PPM_527:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(621) ); SUMMAND(622) <= LOGIC_ONE; PPH_15:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(624) ); -- Begin partial product 16 -- Begin decoder block 17 DEC_16:DECODER -- Decoder of multiplier operand port map ( INA => OPB(31),INB => OPB(32),INC => OPB(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67) ); -- End decoder block 17 -- Begin partial product 17 PPL_16:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(304) ); RGATE_16:R_GATE port map ( INA => OPB(31),INB => OPB(32),INC => OPB(33), PPBIT => SUMMAND(305) ); PPM_528:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(322) ); PPM_529:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(340) ); PPM_530:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(357) ); PPM_531:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(373) ); PPM_532:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(389) ); PPM_533:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(404) ); PPM_534:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(419) ); PPM_535:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(433) ); PPM_536:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(447) ); PPM_537:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(460) ); PPM_538:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(473) ); PPM_539:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(485) ); PPM_540:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(497) ); PPM_541:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(508) ); PPM_542:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(519) ); PPM_543:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(529) ); PPM_544:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(539) ); PPM_545:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(548) ); PPM_546:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(557) ); PPM_547:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(565) ); PPM_548:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(573) ); PPM_549:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(580) ); PPM_550:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(587) ); PPM_551:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(593) ); PPM_552:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(599) ); PPM_553:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(604) ); PPM_554:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(609) ); PPM_555:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(613) ); PPM_556:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(617) ); PPM_557:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(620) ); PPM_558:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(623) ); PPM_559:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(625) ); PPM_560:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(626) ); SUMMAND(627) <= LOGIC_ONE; PPH_16:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(628) ); -- Begin partial product 17 end BOOTHCODER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_34 is port ( SUMMAND: in std_logic_vector(0 to 628); CARRY: out std_logic_vector(0 to 65); SUM: out std_logic_vector(0 to 66) ); end WALLACE_34_34; architecture WALLACE of WALLACE_34_34 is -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 486); signal INT_SUM: std_logic_vector(0 to 620); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin NO stage INT_SUM(76) <= SUMMAND(108); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(77) <= SUMMAND(109); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(78), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(49), SAVE => INT_SUM(79), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin NO stage INT_SUM(80) <= INT_CARRY(50); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(81) <= INT_CARRY(51); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_SUM(80), SAVE => INT_SUM(82), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(81), DATA_B => INT_CARRY(52), DATA_C => INT_CARRY(53), SAVE => INT_SUM(83), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin FA stage FA_64:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(54), SAVE => INT_SUM(84), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(84), DATA_B => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End HA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_65:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112), SAVE => INT_SUM(85), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), DATA_C => SUMMAND(115), SAVE => INT_SUM(86), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(116), DATA_B => SUMMAND(117), DATA_C => SUMMAND(118), SAVE => INT_SUM(87), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin NO stage INT_SUM(88) <= SUMMAND(119); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(56), DATA_C => INT_CARRY(57), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(91) <= INT_CARRY(58); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91), SAVE => INT_SUM(92), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(59), DATA_B => INT_CARRY(60), SAVE => INT_SUM(93), CARRY => INT_CARRY(70) ); ---- End HA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(61), SAVE => INT_SUM(94), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(62); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(63), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End FA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125), SAVE => INT_SUM(97), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(98), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(99), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_SUM(98), SAVE => INT_SUM(100), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(99), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65), SAVE => INT_SUM(101), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin NO stage INT_SUM(102) <= INT_CARRY(66); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_79:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_SUM(102), SAVE => INT_SUM(103), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(67), DATA_B => INT_CARRY(68), SAVE => INT_SUM(104), CARRY => INT_CARRY(79) ); ---- End HA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(103), DATA_B => INT_SUM(104), DATA_C => INT_CARRY(69), SAVE => INT_SUM(105), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin NO stage INT_SUM(106) <= INT_CARRY(70); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_CARRY(71), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_82:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134), SAVE => INT_SUM(107), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(108), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140), SAVE => INT_SUM(109), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(110) <= SUMMAND(141); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(111) <= SUMMAND(142); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_85:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(107), DATA_B => INT_SUM(108), DATA_C => INT_SUM(109), SAVE => INT_SUM(112), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(72), SAVE => INT_SUM(113), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(73), DATA_B => INT_CARRY(74), DATA_C => INT_CARRY(75), SAVE => INT_SUM(114), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_SUM(114), SAVE => INT_SUM(115), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), SAVE => INT_SUM(116), CARRY => INT_CARRY(88) ); ---- End HA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(78), SAVE => INT_SUM(117), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(118) <= INT_CARRY(79); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_CARRY(80), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_91:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), DATA_C => SUMMAND(145), SAVE => INT_SUM(119), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(146), DATA_B => SUMMAND(147), DATA_C => SUMMAND(148), SAVE => INT_SUM(120), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(149), DATA_B => SUMMAND(150), DATA_C => SUMMAND(151), SAVE => INT_SUM(121), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(152), DATA_B => SUMMAND(153), DATA_C => SUMMAND(154), SAVE => INT_SUM(122), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= SUMMAND(155); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(119), DATA_B => INT_SUM(120), DATA_C => INT_SUM(121), SAVE => INT_SUM(124), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(81), SAVE => INT_SUM(125), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83), SAVE => INT_SUM(126), CARRY => INT_CARRY(96) ); ---- End HA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_SUM(126), SAVE => INT_SUM(127), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86), SAVE => INT_SUM(128), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin FA stage FA_99:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(127), DATA_B => INT_SUM(128), DATA_C => INT_CARRY(87), SAVE => INT_SUM(129), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin NO stage INT_SUM(130) <= INT_CARRY(88); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_CARRY(89), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_101:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158), SAVE => INT_SUM(131), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161), SAVE => INT_SUM(132), CARRY => INT_CARRY(101) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164), SAVE => INT_SUM(133), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(134), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin FA stage FA_105:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(131), DATA_B => INT_SUM(132), DATA_C => INT_SUM(133), SAVE => INT_SUM(135), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin FA stage FA_106:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(134), DATA_B => INT_CARRY(90), DATA_C => INT_CARRY(91), SAVE => INT_SUM(136), CARRY => INT_CARRY(105) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(92), DATA_B => INT_CARRY(93), SAVE => INT_SUM(137), CARRY => INT_CARRY(106) ); ---- End HA stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_SUM(137), SAVE => INT_SUM(138), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin FA stage FA_108:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(94), DATA_B => INT_CARRY(95), DATA_C => INT_CARRY(96), SAVE => INT_SUM(139), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(138), DATA_B => INT_SUM(139), DATA_C => INT_CARRY(97), SAVE => INT_SUM(140), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin NO stage INT_SUM(141) <= INT_CARRY(98); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(99), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_111:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170), SAVE => INT_SUM(142), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173), SAVE => INT_SUM(143), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin FA stage FA_113:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(144), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin FA stage FA_114:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(145), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), SAVE => INT_SUM(146), CARRY => INT_CARRY(114) ); ---- End HA stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_SUM(144), SAVE => INT_SUM(147), CARRY => INT_CARRY(115) ); ---- End FA stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(100), SAVE => INT_SUM(148), CARRY => INT_CARRY(116) ); ---- End FA stage ---- Begin FA stage FA_117:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(101), DATA_B => INT_CARRY(102), DATA_C => INT_CARRY(103), SAVE => INT_SUM(149), CARRY => INT_CARRY(117) ); ---- End FA stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(147), DATA_B => INT_SUM(148), DATA_C => INT_SUM(149), SAVE => INT_SUM(150), CARRY => INT_CARRY(118) ); ---- End FA stage ---- Begin FA stage FA_119:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(104), DATA_B => INT_CARRY(105), DATA_C => INT_CARRY(106), SAVE => INT_SUM(151), CARRY => INT_CARRY(119) ); ---- End FA stage ---- Begin FA stage FA_120:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(107), SAVE => INT_SUM(152), CARRY => INT_CARRY(120) ); ---- End FA stage ---- Begin NO stage INT_SUM(153) <= INT_CARRY(108); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_121:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(152), DATA_B => INT_SUM(153), DATA_C => INT_CARRY(109), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_122:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), DATA_C => SUMMAND(184), SAVE => INT_SUM(154), CARRY => INT_CARRY(121) ); ---- End FA stage ---- Begin FA stage FA_123:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(185), DATA_B => SUMMAND(186), DATA_C => SUMMAND(187), SAVE => INT_SUM(155), CARRY => INT_CARRY(122) ); ---- End FA stage ---- Begin FA stage FA_124:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(188), DATA_B => SUMMAND(189), DATA_C => SUMMAND(190), SAVE => INT_SUM(156), CARRY => INT_CARRY(123) ); ---- End FA stage ---- Begin FA stage FA_125:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(191), DATA_B => SUMMAND(192), DATA_C => SUMMAND(193), SAVE => INT_SUM(157), CARRY => INT_CARRY(124) ); ---- End FA stage ---- Begin NO stage INT_SUM(158) <= SUMMAND(194); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_126:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(154), DATA_B => INT_SUM(155), DATA_C => INT_SUM(156), SAVE => INT_SUM(159), CARRY => INT_CARRY(125) ); ---- End FA stage ---- Begin FA stage FA_127:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(110), SAVE => INT_SUM(160), CARRY => INT_CARRY(126) ); ---- End FA stage ---- Begin FA stage FA_128:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(111), DATA_B => INT_CARRY(112), DATA_C => INT_CARRY(113), SAVE => INT_SUM(161), CARRY => INT_CARRY(127) ); ---- End FA stage ---- Begin NO stage INT_SUM(162) <= INT_CARRY(114); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_129:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(159), DATA_B => INT_SUM(160), DATA_C => INT_SUM(161), SAVE => INT_SUM(163), CARRY => INT_CARRY(128) ); ---- End FA stage ---- Begin FA stage FA_130:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(162), DATA_B => INT_CARRY(115), DATA_C => INT_CARRY(116), SAVE => INT_SUM(164), CARRY => INT_CARRY(129) ); ---- End FA stage ---- Begin NO stage INT_SUM(165) <= INT_CARRY(117); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_131:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(163), DATA_B => INT_SUM(164), DATA_C => INT_SUM(165), SAVE => INT_SUM(166), CARRY => INT_CARRY(130) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(118), DATA_B => INT_CARRY(119), SAVE => INT_SUM(167), CARRY => INT_CARRY(131) ); ---- End HA stage ---- Begin FA stage FA_132:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(120), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End FA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_133:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197), SAVE => INT_SUM(168), CARRY => INT_CARRY(132) ); ---- End FA stage ---- Begin FA stage FA_134:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200), SAVE => INT_SUM(169), CARRY => INT_CARRY(133) ); ---- End FA stage ---- Begin FA stage FA_135:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203), SAVE => INT_SUM(170), CARRY => INT_CARRY(134) ); ---- End FA stage ---- Begin FA stage FA_136:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206), SAVE => INT_SUM(171), CARRY => INT_CARRY(135) ); ---- End FA stage ---- Begin FA stage FA_137:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209), SAVE => INT_SUM(172), CARRY => INT_CARRY(136) ); ---- End FA stage ---- Begin FA stage FA_138:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(168), DATA_B => INT_SUM(169), DATA_C => INT_SUM(170), SAVE => INT_SUM(173), CARRY => INT_CARRY(137) ); ---- End FA stage ---- Begin FA stage FA_139:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(171), DATA_B => INT_SUM(172), DATA_C => INT_CARRY(121), SAVE => INT_SUM(174), CARRY => INT_CARRY(138) ); ---- End FA stage ---- Begin FA stage FA_140:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(122), DATA_B => INT_CARRY(123), DATA_C => INT_CARRY(124), SAVE => INT_SUM(175), CARRY => INT_CARRY(139) ); ---- End FA stage ---- Begin FA stage FA_141:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(173), DATA_B => INT_SUM(174), DATA_C => INT_SUM(175), SAVE => INT_SUM(176), CARRY => INT_CARRY(140) ); ---- End FA stage ---- Begin FA stage FA_142:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(125), DATA_B => INT_CARRY(126), DATA_C => INT_CARRY(127), SAVE => INT_SUM(177), CARRY => INT_CARRY(141) ); ---- End FA stage ---- Begin FA stage FA_143:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(176), DATA_B => INT_SUM(177), DATA_C => INT_CARRY(128), SAVE => INT_SUM(178), CARRY => INT_CARRY(142) ); ---- End FA stage ---- Begin NO stage INT_SUM(179) <= INT_CARRY(129); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_144:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(178), DATA_B => INT_SUM(179), DATA_C => INT_CARRY(130), SAVE => INT_SUM(180), CARRY => INT_CARRY(143) ); ---- End FA stage ---- Begin NO stage INT_SUM(181) <= INT_CARRY(131); -- At Level 5 ---- End NO stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_145:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212), SAVE => INT_SUM(182), CARRY => INT_CARRY(144) ); ---- End FA stage ---- Begin FA stage FA_146:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215), SAVE => INT_SUM(183), CARRY => INT_CARRY(145) ); ---- End FA stage ---- Begin FA stage FA_147:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218), SAVE => INT_SUM(184), CARRY => INT_CARRY(146) ); ---- End FA stage ---- Begin FA stage FA_148:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221), SAVE => INT_SUM(185), CARRY => INT_CARRY(147) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), SAVE => INT_SUM(186), CARRY => INT_CARRY(148) ); ---- End HA stage ---- Begin FA stage FA_149:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_SUM(184), SAVE => INT_SUM(187), CARRY => INT_CARRY(149) ); ---- End FA stage ---- Begin FA stage FA_150:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_CARRY(132), SAVE => INT_SUM(188), CARRY => INT_CARRY(150) ); ---- End FA stage ---- Begin FA stage FA_151:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135), SAVE => INT_SUM(189), CARRY => INT_CARRY(151) ); ---- End FA stage ---- Begin NO stage INT_SUM(190) <= INT_CARRY(136); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_152:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(187), DATA_B => INT_SUM(188), DATA_C => INT_SUM(189), SAVE => INT_SUM(191), CARRY => INT_CARRY(152) ); ---- End FA stage ---- Begin FA stage FA_153:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(190), DATA_B => INT_CARRY(137), DATA_C => INT_CARRY(138), SAVE => INT_SUM(192), CARRY => INT_CARRY(153) ); ---- End FA stage ---- Begin NO stage INT_SUM(193) <= INT_CARRY(139); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_154:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(191), DATA_B => INT_SUM(192), DATA_C => INT_SUM(193), SAVE => INT_SUM(194), CARRY => INT_CARRY(154) ); ---- End FA stage ---- Begin NO stage INT_SUM(195) <= INT_CARRY(140); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(196) <= INT_CARRY(141); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_155:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(194), DATA_B => INT_SUM(195), DATA_C => INT_SUM(196), SAVE => INT_SUM(197), CARRY => INT_CARRY(155) ); ---- End FA stage ---- Begin NO stage INT_SUM(198) <= INT_CARRY(142); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_156:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(197), DATA_B => INT_SUM(198), DATA_C => INT_CARRY(143), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End FA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_157:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(224), DATA_B => SUMMAND(225), DATA_C => SUMMAND(226), SAVE => INT_SUM(199), CARRY => INT_CARRY(156) ); ---- End FA stage ---- Begin FA stage FA_158:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(227), DATA_B => SUMMAND(228), DATA_C => SUMMAND(229), SAVE => INT_SUM(200), CARRY => INT_CARRY(157) ); ---- End FA stage ---- Begin FA stage FA_159:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(230), DATA_B => SUMMAND(231), DATA_C => SUMMAND(232), SAVE => INT_SUM(201), CARRY => INT_CARRY(158) ); ---- End FA stage ---- Begin FA stage FA_160:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(233), DATA_B => SUMMAND(234), DATA_C => SUMMAND(235), SAVE => INT_SUM(202), CARRY => INT_CARRY(159) ); ---- End FA stage ---- Begin FA stage FA_161:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(236), DATA_B => SUMMAND(237), DATA_C => SUMMAND(238), SAVE => INT_SUM(203), CARRY => INT_CARRY(160) ); ---- End FA stage ---- Begin NO stage INT_SUM(204) <= SUMMAND(239); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_162:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(199), DATA_B => INT_SUM(200), DATA_C => INT_SUM(201), SAVE => INT_SUM(205), CARRY => INT_CARRY(161) ); ---- End FA stage ---- Begin FA stage FA_163:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(202), DATA_B => INT_SUM(203), DATA_C => INT_SUM(204), SAVE => INT_SUM(206), CARRY => INT_CARRY(162) ); ---- End FA stage ---- Begin FA stage FA_164:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(144), DATA_B => INT_CARRY(145), DATA_C => INT_CARRY(146), SAVE => INT_SUM(207), CARRY => INT_CARRY(163) ); ---- End FA stage ---- Begin NO stage INT_SUM(208) <= INT_CARRY(147); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(209) <= INT_CARRY(148); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_165:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207), SAVE => INT_SUM(210), CARRY => INT_CARRY(164) ); ---- End FA stage ---- Begin FA stage FA_166:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_CARRY(149), SAVE => INT_SUM(211), CARRY => INT_CARRY(165) ); ---- End FA stage ---- Begin NO stage INT_SUM(212) <= INT_CARRY(150); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(213) <= INT_CARRY(151); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_167:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(210), DATA_B => INT_SUM(211), DATA_C => INT_SUM(212), SAVE => INT_SUM(214), CARRY => INT_CARRY(166) ); ---- End FA stage ---- Begin FA stage FA_168:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(213), DATA_B => INT_CARRY(152), DATA_C => INT_CARRY(153), SAVE => INT_SUM(215), CARRY => INT_CARRY(167) ); ---- End FA stage ---- Begin FA stage FA_169:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(214), DATA_B => INT_SUM(215), DATA_C => INT_CARRY(154), SAVE => INT_SUM(216), CARRY => INT_CARRY(168) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(216), DATA_B => INT_CARRY(155), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_170:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242), SAVE => INT_SUM(217), CARRY => INT_CARRY(169) ); ---- End FA stage ---- Begin FA stage FA_171:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245), SAVE => INT_SUM(218), CARRY => INT_CARRY(170) ); ---- End FA stage ---- Begin FA stage FA_172:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248), SAVE => INT_SUM(219), CARRY => INT_CARRY(171) ); ---- End FA stage ---- Begin FA stage FA_173:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251), SAVE => INT_SUM(220), CARRY => INT_CARRY(172) ); ---- End FA stage ---- Begin FA stage FA_174:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(252), DATA_B => SUMMAND(253), DATA_C => SUMMAND(254), SAVE => INT_SUM(221), CARRY => INT_CARRY(173) ); ---- End FA stage ---- Begin FA stage FA_175:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_SUM(219), SAVE => INT_SUM(222), CARRY => INT_CARRY(174) ); ---- End FA stage ---- Begin FA stage FA_176:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_CARRY(156), SAVE => INT_SUM(223), CARRY => INT_CARRY(175) ); ---- End FA stage ---- Begin FA stage FA_177:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(157), DATA_B => INT_CARRY(158), DATA_C => INT_CARRY(159), SAVE => INT_SUM(224), CARRY => INT_CARRY(176) ); ---- End FA stage ---- Begin NO stage INT_SUM(225) <= INT_CARRY(160); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_178:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(222), DATA_B => INT_SUM(223), DATA_C => INT_SUM(224), SAVE => INT_SUM(226), CARRY => INT_CARRY(177) ); ---- End FA stage ---- Begin FA stage FA_179:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(225), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162), SAVE => INT_SUM(227), CARRY => INT_CARRY(178) ); ---- End FA stage ---- Begin NO stage INT_SUM(228) <= INT_CARRY(163); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_180:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_SUM(228), SAVE => INT_SUM(229), CARRY => INT_CARRY(179) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(164), DATA_B => INT_CARRY(165), SAVE => INT_SUM(230), CARRY => INT_CARRY(180) ); ---- End HA stage ---- Begin FA stage FA_181:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(229), DATA_B => INT_SUM(230), DATA_C => INT_CARRY(166), SAVE => INT_SUM(231), CARRY => INT_CARRY(181) ); ---- End FA stage ---- Begin NO stage INT_SUM(232) <= INT_CARRY(167); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_182:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(231), DATA_B => INT_SUM(232), DATA_C => INT_CARRY(168), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_183:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(255), DATA_B => SUMMAND(256), DATA_C => SUMMAND(257), SAVE => INT_SUM(233), CARRY => INT_CARRY(182) ); ---- End FA stage ---- Begin FA stage FA_184:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(258), DATA_B => SUMMAND(259), DATA_C => SUMMAND(260), SAVE => INT_SUM(234), CARRY => INT_CARRY(183) ); ---- End FA stage ---- Begin FA stage FA_185:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(261), DATA_B => SUMMAND(262), DATA_C => SUMMAND(263), SAVE => INT_SUM(235), CARRY => INT_CARRY(184) ); ---- End FA stage ---- Begin FA stage FA_186:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(264), DATA_B => SUMMAND(265), DATA_C => SUMMAND(266), SAVE => INT_SUM(236), CARRY => INT_CARRY(185) ); ---- End FA stage ---- Begin FA stage FA_187:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(267), DATA_B => SUMMAND(268), DATA_C => SUMMAND(269), SAVE => INT_SUM(237), CARRY => INT_CARRY(186) ); ---- End FA stage ---- Begin NO stage INT_SUM(238) <= SUMMAND(270); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(239) <= SUMMAND(271); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_188:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(233), DATA_B => INT_SUM(234), DATA_C => INT_SUM(235), SAVE => INT_SUM(240), CARRY => INT_CARRY(187) ); ---- End FA stage ---- Begin FA stage FA_189:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_SUM(238), SAVE => INT_SUM(241), CARRY => INT_CARRY(188) ); ---- End FA stage ---- Begin FA stage FA_190:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(239), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170), SAVE => INT_SUM(242), CARRY => INT_CARRY(189) ); ---- End FA stage ---- Begin FA stage FA_191:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(171), DATA_B => INT_CARRY(172), DATA_C => INT_CARRY(173), SAVE => INT_SUM(243), CARRY => INT_CARRY(190) ); ---- End FA stage ---- Begin FA stage FA_192:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(240), DATA_B => INT_SUM(241), DATA_C => INT_SUM(242), SAVE => INT_SUM(244), CARRY => INT_CARRY(191) ); ---- End FA stage ---- Begin FA stage FA_193:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(243), DATA_B => INT_CARRY(174), DATA_C => INT_CARRY(175), SAVE => INT_SUM(245), CARRY => INT_CARRY(192) ); ---- End FA stage ---- Begin NO stage INT_SUM(246) <= INT_CARRY(176); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_194:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(244), DATA_B => INT_SUM(245), DATA_C => INT_SUM(246), SAVE => INT_SUM(247), CARRY => INT_CARRY(193) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(177), DATA_B => INT_CARRY(178), SAVE => INT_SUM(248), CARRY => INT_CARRY(194) ); ---- End HA stage ---- Begin FA stage FA_195:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(247), DATA_B => INT_SUM(248), DATA_C => INT_CARRY(179), SAVE => INT_SUM(249), CARRY => INT_CARRY(195) ); ---- End FA stage ---- Begin NO stage INT_SUM(250) <= INT_CARRY(180); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_196:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(249), DATA_B => INT_SUM(250), DATA_C => INT_CARRY(181), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_197:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(272), DATA_B => SUMMAND(273), DATA_C => SUMMAND(274), SAVE => INT_SUM(251), CARRY => INT_CARRY(196) ); ---- End FA stage ---- Begin FA stage FA_198:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(275), DATA_B => SUMMAND(276), DATA_C => SUMMAND(277), SAVE => INT_SUM(252), CARRY => INT_CARRY(197) ); ---- End FA stage ---- Begin FA stage FA_199:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280), SAVE => INT_SUM(253), CARRY => INT_CARRY(198) ); ---- End FA stage ---- Begin FA stage FA_200:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283), SAVE => INT_SUM(254), CARRY => INT_CARRY(199) ); ---- End FA stage ---- Begin FA stage FA_201:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(284), DATA_B => SUMMAND(285), DATA_C => SUMMAND(286), SAVE => INT_SUM(255), CARRY => INT_CARRY(200) ); ---- End FA stage ---- Begin NO stage INT_SUM(256) <= SUMMAND(287); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_202:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(251), DATA_B => INT_SUM(252), DATA_C => INT_SUM(253), SAVE => INT_SUM(257), CARRY => INT_CARRY(201) ); ---- End FA stage ---- Begin FA stage FA_203:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_SUM(256), SAVE => INT_SUM(258), CARRY => INT_CARRY(202) ); ---- End FA stage ---- Begin FA stage FA_204:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(182), DATA_B => INT_CARRY(183), DATA_C => INT_CARRY(184), SAVE => INT_SUM(259), CARRY => INT_CARRY(203) ); ---- End FA stage ---- Begin NO stage INT_SUM(260) <= INT_CARRY(185); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(261) <= INT_CARRY(186); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_205:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(257), DATA_B => INT_SUM(258), DATA_C => INT_SUM(259), SAVE => INT_SUM(262), CARRY => INT_CARRY(204) ); ---- End FA stage ---- Begin FA stage FA_206:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(187), SAVE => INT_SUM(263), CARRY => INT_CARRY(205) ); ---- End FA stage ---- Begin FA stage FA_207:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190), SAVE => INT_SUM(264), CARRY => INT_CARRY(206) ); ---- End FA stage ---- Begin FA stage FA_208:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(262), DATA_B => INT_SUM(263), DATA_C => INT_SUM(264), SAVE => INT_SUM(265), CARRY => INT_CARRY(207) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(191), DATA_B => INT_CARRY(192), SAVE => INT_SUM(266), CARRY => INT_CARRY(208) ); ---- End HA stage ---- Begin FA stage FA_209:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(193), SAVE => INT_SUM(267), CARRY => INT_CARRY(209) ); ---- End FA stage ---- Begin NO stage INT_SUM(268) <= INT_CARRY(194); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_210:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(267), DATA_B => INT_SUM(268), DATA_C => INT_CARRY(195), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End FA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_211:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290), SAVE => INT_SUM(269), CARRY => INT_CARRY(210) ); ---- End FA stage ---- Begin FA stage FA_212:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(291), DATA_B => SUMMAND(292), DATA_C => SUMMAND(293), SAVE => INT_SUM(270), CARRY => INT_CARRY(211) ); ---- End FA stage ---- Begin FA stage FA_213:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(294), DATA_B => SUMMAND(295), DATA_C => SUMMAND(296), SAVE => INT_SUM(271), CARRY => INT_CARRY(212) ); ---- End FA stage ---- Begin FA stage FA_214:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(297), DATA_B => SUMMAND(298), DATA_C => SUMMAND(299), SAVE => INT_SUM(272), CARRY => INT_CARRY(213) ); ---- End FA stage ---- Begin FA stage FA_215:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(300), DATA_B => SUMMAND(301), DATA_C => SUMMAND(302), SAVE => INT_SUM(273), CARRY => INT_CARRY(214) ); ---- End FA stage ---- Begin FA stage FA_216:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(303), DATA_B => SUMMAND(304), DATA_C => SUMMAND(305), SAVE => INT_SUM(274), CARRY => INT_CARRY(215) ); ---- End FA stage ---- Begin FA stage FA_217:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(269), DATA_B => INT_SUM(270), DATA_C => INT_SUM(271), SAVE => INT_SUM(275), CARRY => INT_CARRY(216) ); ---- End FA stage ---- Begin FA stage FA_218:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(272), DATA_B => INT_SUM(273), DATA_C => INT_SUM(274), SAVE => INT_SUM(276), CARRY => INT_CARRY(217) ); ---- End FA stage ---- Begin FA stage FA_219:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(196), DATA_B => INT_CARRY(197), DATA_C => INT_CARRY(198), SAVE => INT_SUM(277), CARRY => INT_CARRY(218) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(199), DATA_B => INT_CARRY(200), SAVE => INT_SUM(278), CARRY => INT_CARRY(219) ); ---- End HA stage ---- Begin FA stage FA_220:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(275), DATA_B => INT_SUM(276), DATA_C => INT_SUM(277), SAVE => INT_SUM(279), CARRY => INT_CARRY(220) ); ---- End FA stage ---- Begin FA stage FA_221:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(278), DATA_B => INT_CARRY(201), DATA_C => INT_CARRY(202), SAVE => INT_SUM(280), CARRY => INT_CARRY(221) ); ---- End FA stage ---- Begin NO stage INT_SUM(281) <= INT_CARRY(203); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_222:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(279), DATA_B => INT_SUM(280), DATA_C => INT_SUM(281), SAVE => INT_SUM(282), CARRY => INT_CARRY(222) ); ---- End FA stage ---- Begin FA stage FA_223:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(204), DATA_B => INT_CARRY(205), DATA_C => INT_CARRY(206), SAVE => INT_SUM(283), CARRY => INT_CARRY(223) ); ---- End FA stage ---- Begin FA stage FA_224:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(282), DATA_B => INT_SUM(283), DATA_C => INT_CARRY(207), SAVE => INT_SUM(284), CARRY => INT_CARRY(224) ); ---- End FA stage ---- Begin NO stage INT_SUM(285) <= INT_CARRY(208); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_225:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(284), DATA_B => INT_SUM(285), DATA_C => INT_CARRY(209), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_226:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(306), DATA_B => SUMMAND(307), DATA_C => SUMMAND(308), SAVE => INT_SUM(286), CARRY => INT_CARRY(225) ); ---- End FA stage ---- Begin FA stage FA_227:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311), SAVE => INT_SUM(287), CARRY => INT_CARRY(226) ); ---- End FA stage ---- Begin FA stage FA_228:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), DATA_C => SUMMAND(314), SAVE => INT_SUM(288), CARRY => INT_CARRY(227) ); ---- End FA stage ---- Begin FA stage FA_229:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(315), DATA_B => SUMMAND(316), DATA_C => SUMMAND(317), SAVE => INT_SUM(289), CARRY => INT_CARRY(228) ); ---- End FA stage ---- Begin FA stage FA_230:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320), SAVE => INT_SUM(290), CARRY => INT_CARRY(229) ); ---- End FA stage ---- Begin NO stage INT_SUM(291) <= SUMMAND(321); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(292) <= SUMMAND(322); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_231:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(286), DATA_B => INT_SUM(287), DATA_C => INT_SUM(288), SAVE => INT_SUM(293), CARRY => INT_CARRY(230) ); ---- End FA stage ---- Begin FA stage FA_232:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(289), DATA_B => INT_SUM(290), DATA_C => INT_SUM(291), SAVE => INT_SUM(294), CARRY => INT_CARRY(231) ); ---- End FA stage ---- Begin FA stage FA_233:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(292), DATA_B => INT_CARRY(210), DATA_C => INT_CARRY(211), SAVE => INT_SUM(295), CARRY => INT_CARRY(232) ); ---- End FA stage ---- Begin FA stage FA_234:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(212), DATA_B => INT_CARRY(213), DATA_C => INT_CARRY(214), SAVE => INT_SUM(296), CARRY => INT_CARRY(233) ); ---- End FA stage ---- Begin NO stage INT_SUM(297) <= INT_CARRY(215); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_235:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(293), DATA_B => INT_SUM(294), DATA_C => INT_SUM(295), SAVE => INT_SUM(298), CARRY => INT_CARRY(234) ); ---- End FA stage ---- Begin FA stage FA_236:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(296), DATA_B => INT_SUM(297), DATA_C => INT_CARRY(216), SAVE => INT_SUM(299), CARRY => INT_CARRY(235) ); ---- End FA stage ---- Begin FA stage FA_237:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(217), DATA_B => INT_CARRY(218), DATA_C => INT_CARRY(219), SAVE => INT_SUM(300), CARRY => INT_CARRY(236) ); ---- End FA stage ---- Begin FA stage FA_238:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(298), DATA_B => INT_SUM(299), DATA_C => INT_SUM(300), SAVE => INT_SUM(301), CARRY => INT_CARRY(237) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(220), DATA_B => INT_CARRY(221), SAVE => INT_SUM(302), CARRY => INT_CARRY(238) ); ---- End HA stage ---- Begin FA stage FA_239:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(301), DATA_B => INT_SUM(302), DATA_C => INT_CARRY(222), SAVE => INT_SUM(303), CARRY => INT_CARRY(239) ); ---- End FA stage ---- Begin NO stage INT_SUM(304) <= INT_CARRY(223); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_240:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(303), DATA_B => INT_SUM(304), DATA_C => INT_CARRY(224), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End FA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_241:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(323), DATA_B => SUMMAND(324), DATA_C => SUMMAND(325), SAVE => INT_SUM(305), CARRY => INT_CARRY(240) ); ---- End FA stage ---- Begin FA stage FA_242:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(326), DATA_B => SUMMAND(327), DATA_C => SUMMAND(328), SAVE => INT_SUM(306), CARRY => INT_CARRY(241) ); ---- End FA stage ---- Begin FA stage FA_243:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(329), DATA_B => SUMMAND(330), DATA_C => SUMMAND(331), SAVE => INT_SUM(307), CARRY => INT_CARRY(242) ); ---- End FA stage ---- Begin FA stage FA_244:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(332), DATA_B => SUMMAND(333), DATA_C => SUMMAND(334), SAVE => INT_SUM(308), CARRY => INT_CARRY(243) ); ---- End FA stage ---- Begin FA stage FA_245:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(335), DATA_B => SUMMAND(336), DATA_C => SUMMAND(337), SAVE => INT_SUM(309), CARRY => INT_CARRY(244) ); ---- End FA stage ---- Begin FA stage FA_246:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(338), DATA_B => SUMMAND(339), DATA_C => SUMMAND(340), SAVE => INT_SUM(310), CARRY => INT_CARRY(245) ); ---- End FA stage ---- Begin FA stage FA_247:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(305), DATA_B => INT_SUM(306), DATA_C => INT_SUM(307), SAVE => INT_SUM(311), CARRY => INT_CARRY(246) ); ---- End FA stage ---- Begin FA stage FA_248:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(308), DATA_B => INT_SUM(309), DATA_C => INT_SUM(310), SAVE => INT_SUM(312), CARRY => INT_CARRY(247) ); ---- End FA stage ---- Begin FA stage FA_249:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(225), DATA_B => INT_CARRY(226), DATA_C => INT_CARRY(227), SAVE => INT_SUM(313), CARRY => INT_CARRY(248) ); ---- End FA stage ---- Begin NO stage INT_SUM(314) <= INT_CARRY(228); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(315) <= INT_CARRY(229); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_250:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(311), DATA_B => INT_SUM(312), DATA_C => INT_SUM(313), SAVE => INT_SUM(316), CARRY => INT_CARRY(249) ); ---- End FA stage ---- Begin FA stage FA_251:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(314), DATA_B => INT_SUM(315), DATA_C => INT_CARRY(230), SAVE => INT_SUM(317), CARRY => INT_CARRY(250) ); ---- End FA stage ---- Begin FA stage FA_252:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(231), DATA_B => INT_CARRY(232), DATA_C => INT_CARRY(233), SAVE => INT_SUM(318), CARRY => INT_CARRY(251) ); ---- End FA stage ---- Begin FA stage FA_253:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(316), DATA_B => INT_SUM(317), DATA_C => INT_SUM(318), SAVE => INT_SUM(319), CARRY => INT_CARRY(252) ); ---- End FA stage ---- Begin FA stage FA_254:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(234), DATA_B => INT_CARRY(235), DATA_C => INT_CARRY(236), SAVE => INT_SUM(320), CARRY => INT_CARRY(253) ); ---- End FA stage ---- Begin FA stage FA_255:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(319), DATA_B => INT_SUM(320), DATA_C => INT_CARRY(237), SAVE => INT_SUM(321), CARRY => INT_CARRY(254) ); ---- End FA stage ---- Begin NO stage INT_SUM(322) <= INT_CARRY(238); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_256:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(321), DATA_B => INT_SUM(322), DATA_C => INT_CARRY(239), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_257:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(341), DATA_B => SUMMAND(342), DATA_C => SUMMAND(343), SAVE => INT_SUM(323), CARRY => INT_CARRY(255) ); ---- End FA stage ---- Begin FA stage FA_258:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(344), DATA_B => SUMMAND(345), DATA_C => SUMMAND(346), SAVE => INT_SUM(324), CARRY => INT_CARRY(256) ); ---- End FA stage ---- Begin FA stage FA_259:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(347), DATA_B => SUMMAND(348), DATA_C => SUMMAND(349), SAVE => INT_SUM(325), CARRY => INT_CARRY(257) ); ---- End FA stage ---- Begin FA stage FA_260:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(350), DATA_B => SUMMAND(351), DATA_C => SUMMAND(352), SAVE => INT_SUM(326), CARRY => INT_CARRY(258) ); ---- End FA stage ---- Begin FA stage FA_261:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(353), DATA_B => SUMMAND(354), DATA_C => SUMMAND(355), SAVE => INT_SUM(327), CARRY => INT_CARRY(259) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(356), DATA_B => SUMMAND(357), SAVE => INT_SUM(328), CARRY => INT_CARRY(260) ); ---- End HA stage ---- Begin FA stage FA_262:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(323), DATA_B => INT_SUM(324), DATA_C => INT_SUM(325), SAVE => INT_SUM(329), CARRY => INT_CARRY(261) ); ---- End FA stage ---- Begin FA stage FA_263:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(326), DATA_B => INT_SUM(327), DATA_C => INT_SUM(328), SAVE => INT_SUM(330), CARRY => INT_CARRY(262) ); ---- End FA stage ---- Begin FA stage FA_264:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(240), DATA_B => INT_CARRY(241), DATA_C => INT_CARRY(242), SAVE => INT_SUM(331), CARRY => INT_CARRY(263) ); ---- End FA stage ---- Begin FA stage FA_265:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(243), DATA_B => INT_CARRY(244), DATA_C => INT_CARRY(245), SAVE => INT_SUM(332), CARRY => INT_CARRY(264) ); ---- End FA stage ---- Begin FA stage FA_266:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(329), DATA_B => INT_SUM(330), DATA_C => INT_SUM(331), SAVE => INT_SUM(333), CARRY => INT_CARRY(265) ); ---- End FA stage ---- Begin FA stage FA_267:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(332), DATA_B => INT_CARRY(246), DATA_C => INT_CARRY(247), SAVE => INT_SUM(334), CARRY => INT_CARRY(266) ); ---- End FA stage ---- Begin NO stage INT_SUM(335) <= INT_CARRY(248); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_268:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(333), DATA_B => INT_SUM(334), DATA_C => INT_SUM(335), SAVE => INT_SUM(336), CARRY => INT_CARRY(267) ); ---- End FA stage ---- Begin FA stage FA_269:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(249), DATA_B => INT_CARRY(250), DATA_C => INT_CARRY(251), SAVE => INT_SUM(337), CARRY => INT_CARRY(268) ); ---- End FA stage ---- Begin FA stage FA_270:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(336), DATA_B => INT_SUM(337), DATA_C => INT_CARRY(252), SAVE => INT_SUM(338), CARRY => INT_CARRY(269) ); ---- End FA stage ---- Begin NO stage INT_SUM(339) <= INT_CARRY(253); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_271:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(338), DATA_B => INT_SUM(339), DATA_C => INT_CARRY(254), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End FA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_272:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(358), DATA_B => SUMMAND(359), DATA_C => SUMMAND(360), SAVE => INT_SUM(340), CARRY => INT_CARRY(270) ); ---- End FA stage ---- Begin FA stage FA_273:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(361), DATA_B => SUMMAND(362), DATA_C => SUMMAND(363), SAVE => INT_SUM(341), CARRY => INT_CARRY(271) ); ---- End FA stage ---- Begin FA stage FA_274:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(364), DATA_B => SUMMAND(365), DATA_C => SUMMAND(366), SAVE => INT_SUM(342), CARRY => INT_CARRY(272) ); ---- End FA stage ---- Begin FA stage FA_275:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(367), DATA_B => SUMMAND(368), DATA_C => SUMMAND(369), SAVE => INT_SUM(343), CARRY => INT_CARRY(273) ); ---- End FA stage ---- Begin FA stage FA_276:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(370), DATA_B => SUMMAND(371), DATA_C => SUMMAND(372), SAVE => INT_SUM(344), CARRY => INT_CARRY(274) ); ---- End FA stage ---- Begin NO stage INT_SUM(345) <= SUMMAND(373); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_277:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(340), DATA_B => INT_SUM(341), DATA_C => INT_SUM(342), SAVE => INT_SUM(346), CARRY => INT_CARRY(275) ); ---- End FA stage ---- Begin FA stage FA_278:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(343), DATA_B => INT_SUM(344), DATA_C => INT_SUM(345), SAVE => INT_SUM(347), CARRY => INT_CARRY(276) ); ---- End FA stage ---- Begin FA stage FA_279:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(255), DATA_B => INT_CARRY(256), DATA_C => INT_CARRY(257), SAVE => INT_SUM(348), CARRY => INT_CARRY(277) ); ---- End FA stage ---- Begin FA stage FA_280:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(258), DATA_B => INT_CARRY(259), DATA_C => INT_CARRY(260), SAVE => INT_SUM(349), CARRY => INT_CARRY(278) ); ---- End FA stage ---- Begin FA stage FA_281:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(346), DATA_B => INT_SUM(347), DATA_C => INT_SUM(348), SAVE => INT_SUM(350), CARRY => INT_CARRY(279) ); ---- End FA stage ---- Begin FA stage FA_282:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(349), DATA_B => INT_CARRY(261), DATA_C => INT_CARRY(262), SAVE => INT_SUM(351), CARRY => INT_CARRY(280) ); ---- End FA stage ---- Begin NO stage INT_SUM(352) <= INT_CARRY(263); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(353) <= INT_CARRY(264); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_283:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(350), DATA_B => INT_SUM(351), DATA_C => INT_SUM(352), SAVE => INT_SUM(354), CARRY => INT_CARRY(281) ); ---- End FA stage ---- Begin FA stage FA_284:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(353), DATA_B => INT_CARRY(265), DATA_C => INT_CARRY(266), SAVE => INT_SUM(355), CARRY => INT_CARRY(282) ); ---- End FA stage ---- Begin FA stage FA_285:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(354), DATA_B => INT_SUM(355), DATA_C => INT_CARRY(267), SAVE => INT_SUM(356), CARRY => INT_CARRY(283) ); ---- End FA stage ---- Begin NO stage INT_SUM(357) <= INT_CARRY(268); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_286:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(356), DATA_B => INT_SUM(357), DATA_C => INT_CARRY(269), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_287:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(374), DATA_B => SUMMAND(375), DATA_C => SUMMAND(376), SAVE => INT_SUM(358), CARRY => INT_CARRY(284) ); ---- End FA stage ---- Begin FA stage FA_288:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(377), DATA_B => SUMMAND(378), DATA_C => SUMMAND(379), SAVE => INT_SUM(359), CARRY => INT_CARRY(285) ); ---- End FA stage ---- Begin FA stage FA_289:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(380), DATA_B => SUMMAND(381), DATA_C => SUMMAND(382), SAVE => INT_SUM(360), CARRY => INT_CARRY(286) ); ---- End FA stage ---- Begin FA stage FA_290:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(383), DATA_B => SUMMAND(384), DATA_C => SUMMAND(385), SAVE => INT_SUM(361), CARRY => INT_CARRY(287) ); ---- End FA stage ---- Begin FA stage FA_291:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(386), DATA_B => SUMMAND(387), DATA_C => SUMMAND(388), SAVE => INT_SUM(362), CARRY => INT_CARRY(288) ); ---- End FA stage ---- Begin NO stage INT_SUM(363) <= SUMMAND(389); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_292:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(358), DATA_B => INT_SUM(359), DATA_C => INT_SUM(360), SAVE => INT_SUM(364), CARRY => INT_CARRY(289) ); ---- End FA stage ---- Begin FA stage FA_293:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(361), DATA_B => INT_SUM(362), DATA_C => INT_SUM(363), SAVE => INT_SUM(365), CARRY => INT_CARRY(290) ); ---- End FA stage ---- Begin FA stage FA_294:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(270), DATA_B => INT_CARRY(271), DATA_C => INT_CARRY(272), SAVE => INT_SUM(366), CARRY => INT_CARRY(291) ); ---- End FA stage ---- Begin NO stage INT_SUM(367) <= INT_CARRY(273); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(368) <= INT_CARRY(274); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_295:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(364), DATA_B => INT_SUM(365), DATA_C => INT_SUM(366), SAVE => INT_SUM(369), CARRY => INT_CARRY(292) ); ---- End FA stage ---- Begin FA stage FA_296:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(367), DATA_B => INT_SUM(368), DATA_C => INT_CARRY(275), SAVE => INT_SUM(370), CARRY => INT_CARRY(293) ); ---- End FA stage ---- Begin FA stage FA_297:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(276), DATA_B => INT_CARRY(277), DATA_C => INT_CARRY(278), SAVE => INT_SUM(371), CARRY => INT_CARRY(294) ); ---- End FA stage ---- Begin FA stage FA_298:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(369), DATA_B => INT_SUM(370), DATA_C => INT_SUM(371), SAVE => INT_SUM(372), CARRY => INT_CARRY(295) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(279), DATA_B => INT_CARRY(280), SAVE => INT_SUM(373), CARRY => INT_CARRY(296) ); ---- End HA stage ---- Begin FA stage FA_299:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(372), DATA_B => INT_SUM(373), DATA_C => INT_CARRY(281), SAVE => INT_SUM(374), CARRY => INT_CARRY(297) ); ---- End FA stage ---- Begin NO stage INT_SUM(375) <= INT_CARRY(282); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_300:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(374), DATA_B => INT_SUM(375), DATA_C => INT_CARRY(283), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End FA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_301:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(390), DATA_B => SUMMAND(391), DATA_C => SUMMAND(392), SAVE => INT_SUM(376), CARRY => INT_CARRY(298) ); ---- End FA stage ---- Begin FA stage FA_302:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(393), DATA_B => SUMMAND(394), DATA_C => SUMMAND(395), SAVE => INT_SUM(377), CARRY => INT_CARRY(299) ); ---- End FA stage ---- Begin FA stage FA_303:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(396), DATA_B => SUMMAND(397), DATA_C => SUMMAND(398), SAVE => INT_SUM(378), CARRY => INT_CARRY(300) ); ---- End FA stage ---- Begin FA stage FA_304:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(399), DATA_B => SUMMAND(400), DATA_C => SUMMAND(401), SAVE => INT_SUM(379), CARRY => INT_CARRY(301) ); ---- End FA stage ---- Begin FA stage FA_305:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(402), DATA_B => SUMMAND(403), DATA_C => SUMMAND(404), SAVE => INT_SUM(380), CARRY => INT_CARRY(302) ); ---- End FA stage ---- Begin FA stage FA_306:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(376), DATA_B => INT_SUM(377), DATA_C => INT_SUM(378), SAVE => INT_SUM(381), CARRY => INT_CARRY(303) ); ---- End FA stage ---- Begin FA stage FA_307:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(379), DATA_B => INT_SUM(380), DATA_C => INT_CARRY(284), SAVE => INT_SUM(382), CARRY => INT_CARRY(304) ); ---- End FA stage ---- Begin FA stage FA_308:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(285), DATA_B => INT_CARRY(286), DATA_C => INT_CARRY(287), SAVE => INT_SUM(383), CARRY => INT_CARRY(305) ); ---- End FA stage ---- Begin NO stage INT_SUM(384) <= INT_CARRY(288); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_309:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(381), DATA_B => INT_SUM(382), DATA_C => INT_SUM(383), SAVE => INT_SUM(385), CARRY => INT_CARRY(306) ); ---- End FA stage ---- Begin FA stage FA_310:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(384), DATA_B => INT_CARRY(289), DATA_C => INT_CARRY(290), SAVE => INT_SUM(386), CARRY => INT_CARRY(307) ); ---- End FA stage ---- Begin NO stage INT_SUM(387) <= INT_CARRY(291); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_311:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(385), DATA_B => INT_SUM(386), DATA_C => INT_SUM(387), SAVE => INT_SUM(388), CARRY => INT_CARRY(308) ); ---- End FA stage ---- Begin FA stage FA_312:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(292), DATA_B => INT_CARRY(293), DATA_C => INT_CARRY(294), SAVE => INT_SUM(389), CARRY => INT_CARRY(309) ); ---- End FA stage ---- Begin FA stage FA_313:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(388), DATA_B => INT_SUM(389), DATA_C => INT_CARRY(295), SAVE => INT_SUM(390), CARRY => INT_CARRY(310) ); ---- End FA stage ---- Begin NO stage INT_SUM(391) <= INT_CARRY(296); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_314:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(390), DATA_B => INT_SUM(391), DATA_C => INT_CARRY(297), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_315:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(405), DATA_B => SUMMAND(406), DATA_C => SUMMAND(407), SAVE => INT_SUM(392), CARRY => INT_CARRY(311) ); ---- End FA stage ---- Begin FA stage FA_316:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(408), DATA_B => SUMMAND(409), DATA_C => SUMMAND(410), SAVE => INT_SUM(393), CARRY => INT_CARRY(312) ); ---- End FA stage ---- Begin FA stage FA_317:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(411), DATA_B => SUMMAND(412), DATA_C => SUMMAND(413), SAVE => INT_SUM(394), CARRY => INT_CARRY(313) ); ---- End FA stage ---- Begin FA stage FA_318:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(414), DATA_B => SUMMAND(415), DATA_C => SUMMAND(416), SAVE => INT_SUM(395), CARRY => INT_CARRY(314) ); ---- End FA stage ---- Begin FA stage FA_319:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(417), DATA_B => SUMMAND(418), DATA_C => SUMMAND(419), SAVE => INT_SUM(396), CARRY => INT_CARRY(315) ); ---- End FA stage ---- Begin FA stage FA_320:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(392), DATA_B => INT_SUM(393), DATA_C => INT_SUM(394), SAVE => INT_SUM(397), CARRY => INT_CARRY(316) ); ---- End FA stage ---- Begin FA stage FA_321:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(395), DATA_B => INT_SUM(396), DATA_C => INT_CARRY(298), SAVE => INT_SUM(398), CARRY => INT_CARRY(317) ); ---- End FA stage ---- Begin FA stage FA_322:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(299), DATA_B => INT_CARRY(300), DATA_C => INT_CARRY(301), SAVE => INT_SUM(399), CARRY => INT_CARRY(318) ); ---- End FA stage ---- Begin NO stage INT_SUM(400) <= INT_CARRY(302); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_323:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(397), DATA_B => INT_SUM(398), DATA_C => INT_SUM(399), SAVE => INT_SUM(401), CARRY => INT_CARRY(319) ); ---- End FA stage ---- Begin FA stage FA_324:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(400), DATA_B => INT_CARRY(303), DATA_C => INT_CARRY(304), SAVE => INT_SUM(402), CARRY => INT_CARRY(320) ); ---- End FA stage ---- Begin NO stage INT_SUM(403) <= INT_CARRY(305); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_325:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(401), DATA_B => INT_SUM(402), DATA_C => INT_SUM(403), SAVE => INT_SUM(404), CARRY => INT_CARRY(321) ); ---- End FA stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(306), DATA_B => INT_CARRY(307), SAVE => INT_SUM(405), CARRY => INT_CARRY(322) ); ---- End HA stage ---- Begin FA stage FA_326:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(404), DATA_B => INT_SUM(405), DATA_C => INT_CARRY(308), SAVE => INT_SUM(406), CARRY => INT_CARRY(323) ); ---- End FA stage ---- Begin NO stage INT_SUM(407) <= INT_CARRY(309); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_327:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(406), DATA_B => INT_SUM(407), DATA_C => INT_CARRY(310), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End FA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin FA stage FA_328:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(420), DATA_B => SUMMAND(421), DATA_C => SUMMAND(422), SAVE => INT_SUM(408), CARRY => INT_CARRY(324) ); ---- End FA stage ---- Begin FA stage FA_329:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(423), DATA_B => SUMMAND(424), DATA_C => SUMMAND(425), SAVE => INT_SUM(409), CARRY => INT_CARRY(325) ); ---- End FA stage ---- Begin FA stage FA_330:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(426), DATA_B => SUMMAND(427), DATA_C => SUMMAND(428), SAVE => INT_SUM(410), CARRY => INT_CARRY(326) ); ---- End FA stage ---- Begin FA stage FA_331:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(429), DATA_B => SUMMAND(430), DATA_C => SUMMAND(431), SAVE => INT_SUM(411), CARRY => INT_CARRY(327) ); ---- End FA stage ---- Begin HA stage HA_35:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(432), DATA_B => SUMMAND(433), SAVE => INT_SUM(412), CARRY => INT_CARRY(328) ); ---- End HA stage ---- Begin FA stage FA_332:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(408), DATA_B => INT_SUM(409), DATA_C => INT_SUM(410), SAVE => INT_SUM(413), CARRY => INT_CARRY(329) ); ---- End FA stage ---- Begin FA stage FA_333:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(411), DATA_B => INT_SUM(412), DATA_C => INT_CARRY(311), SAVE => INT_SUM(414), CARRY => INT_CARRY(330) ); ---- End FA stage ---- Begin FA stage FA_334:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(312), DATA_B => INT_CARRY(313), DATA_C => INT_CARRY(314), SAVE => INT_SUM(415), CARRY => INT_CARRY(331) ); ---- End FA stage ---- Begin NO stage INT_SUM(416) <= INT_CARRY(315); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_335:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(413), DATA_B => INT_SUM(414), DATA_C => INT_SUM(415), SAVE => INT_SUM(417), CARRY => INT_CARRY(332) ); ---- End FA stage ---- Begin FA stage FA_336:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(416), DATA_B => INT_CARRY(316), DATA_C => INT_CARRY(317), SAVE => INT_SUM(418), CARRY => INT_CARRY(333) ); ---- End FA stage ---- Begin NO stage INT_SUM(419) <= INT_CARRY(318); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_337:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(417), DATA_B => INT_SUM(418), DATA_C => INT_SUM(419), SAVE => INT_SUM(420), CARRY => INT_CARRY(334) ); ---- End FA stage ---- Begin HA stage HA_36:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(319), DATA_B => INT_CARRY(320), SAVE => INT_SUM(421), CARRY => INT_CARRY(335) ); ---- End HA stage ---- Begin FA stage FA_338:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(420), DATA_B => INT_SUM(421), DATA_C => INT_CARRY(321), SAVE => INT_SUM(422), CARRY => INT_CARRY(336) ); ---- End FA stage ---- Begin NO stage INT_SUM(423) <= INT_CARRY(322); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_339:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(422), DATA_B => INT_SUM(423), DATA_C => INT_CARRY(323), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin FA stage FA_340:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(434), DATA_B => SUMMAND(435), DATA_C => SUMMAND(436), SAVE => INT_SUM(424), CARRY => INT_CARRY(337) ); ---- End FA stage ---- Begin FA stage FA_341:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(437), DATA_B => SUMMAND(438), DATA_C => SUMMAND(439), SAVE => INT_SUM(425), CARRY => INT_CARRY(338) ); ---- End FA stage ---- Begin FA stage FA_342:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(440), DATA_B => SUMMAND(441), DATA_C => SUMMAND(442), SAVE => INT_SUM(426), CARRY => INT_CARRY(339) ); ---- End FA stage ---- Begin FA stage FA_343:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(443), DATA_B => SUMMAND(444), DATA_C => SUMMAND(445), SAVE => INT_SUM(427), CARRY => INT_CARRY(340) ); ---- End FA stage ---- Begin HA stage HA_37:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(446), DATA_B => SUMMAND(447), SAVE => INT_SUM(428), CARRY => INT_CARRY(341) ); ---- End HA stage ---- Begin FA stage FA_344:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(424), DATA_B => INT_SUM(425), DATA_C => INT_SUM(426), SAVE => INT_SUM(429), CARRY => INT_CARRY(342) ); ---- End FA stage ---- Begin FA stage FA_345:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(427), DATA_B => INT_SUM(428), DATA_C => INT_CARRY(324), SAVE => INT_SUM(430), CARRY => INT_CARRY(343) ); ---- End FA stage ---- Begin FA stage FA_346:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(325), DATA_B => INT_CARRY(326), DATA_C => INT_CARRY(327), SAVE => INT_SUM(431), CARRY => INT_CARRY(344) ); ---- End FA stage ---- Begin NO stage INT_SUM(432) <= INT_CARRY(328); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_347:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(429), DATA_B => INT_SUM(430), DATA_C => INT_SUM(431), SAVE => INT_SUM(433), CARRY => INT_CARRY(345) ); ---- End FA stage ---- Begin FA stage FA_348:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(432), DATA_B => INT_CARRY(329), DATA_C => INT_CARRY(330), SAVE => INT_SUM(434), CARRY => INT_CARRY(346) ); ---- End FA stage ---- Begin NO stage INT_SUM(435) <= INT_CARRY(331); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_349:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(433), DATA_B => INT_SUM(434), DATA_C => INT_SUM(435), SAVE => INT_SUM(436), CARRY => INT_CARRY(347) ); ---- End FA stage ---- Begin HA stage HA_38:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(332), DATA_B => INT_CARRY(333), SAVE => INT_SUM(437), CARRY => INT_CARRY(348) ); ---- End HA stage ---- Begin FA stage FA_350:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(436), DATA_B => INT_SUM(437), DATA_C => INT_CARRY(334), SAVE => INT_SUM(438), CARRY => INT_CARRY(349) ); ---- End FA stage ---- Begin NO stage INT_SUM(439) <= INT_CARRY(335); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_351:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(438), DATA_B => INT_SUM(439), DATA_C => INT_CARRY(336), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End FA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin FA stage FA_352:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(448), DATA_B => SUMMAND(449), DATA_C => SUMMAND(450), SAVE => INT_SUM(440), CARRY => INT_CARRY(350) ); ---- End FA stage ---- Begin FA stage FA_353:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(451), DATA_B => SUMMAND(452), DATA_C => SUMMAND(453), SAVE => INT_SUM(441), CARRY => INT_CARRY(351) ); ---- End FA stage ---- Begin FA stage FA_354:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(454), DATA_B => SUMMAND(455), DATA_C => SUMMAND(456), SAVE => INT_SUM(442), CARRY => INT_CARRY(352) ); ---- End FA stage ---- Begin FA stage FA_355:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(457), DATA_B => SUMMAND(458), DATA_C => SUMMAND(459), SAVE => INT_SUM(443), CARRY => INT_CARRY(353) ); ---- End FA stage ---- Begin NO stage INT_SUM(444) <= SUMMAND(460); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_356:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(440), DATA_B => INT_SUM(441), DATA_C => INT_SUM(442), SAVE => INT_SUM(445), CARRY => INT_CARRY(354) ); ---- End FA stage ---- Begin FA stage FA_357:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(443), DATA_B => INT_SUM(444), DATA_C => INT_CARRY(337), SAVE => INT_SUM(446), CARRY => INT_CARRY(355) ); ---- End FA stage ---- Begin FA stage FA_358:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(338), DATA_B => INT_CARRY(339), DATA_C => INT_CARRY(340), SAVE => INT_SUM(447), CARRY => INT_CARRY(356) ); ---- End FA stage ---- Begin NO stage INT_SUM(448) <= INT_CARRY(341); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_359:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(445), DATA_B => INT_SUM(446), DATA_C => INT_SUM(447), SAVE => INT_SUM(449), CARRY => INT_CARRY(357) ); ---- End FA stage ---- Begin FA stage FA_360:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(448), DATA_B => INT_CARRY(342), DATA_C => INT_CARRY(343), SAVE => INT_SUM(450), CARRY => INT_CARRY(358) ); ---- End FA stage ---- Begin NO stage INT_SUM(451) <= INT_CARRY(344); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_361:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(449), DATA_B => INT_SUM(450), DATA_C => INT_SUM(451), SAVE => INT_SUM(452), CARRY => INT_CARRY(359) ); ---- End FA stage ---- Begin HA stage HA_39:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(345), DATA_B => INT_CARRY(346), SAVE => INT_SUM(453), CARRY => INT_CARRY(360) ); ---- End HA stage ---- Begin FA stage FA_362:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(452), DATA_B => INT_SUM(453), DATA_C => INT_CARRY(347), SAVE => INT_SUM(454), CARRY => INT_CARRY(361) ); ---- End FA stage ---- Begin NO stage INT_SUM(455) <= INT_CARRY(348); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_363:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(454), DATA_B => INT_SUM(455), DATA_C => INT_CARRY(349), SAVE => SUM(42), CARRY => CARRY(42) ); ---- End FA stage -- End WT-branch 43 -- Begin WT-branch 44 ---- Begin FA stage FA_364:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(461), DATA_B => SUMMAND(462), DATA_C => SUMMAND(463), SAVE => INT_SUM(456), CARRY => INT_CARRY(362) ); ---- End FA stage ---- Begin FA stage FA_365:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(464), DATA_B => SUMMAND(465), DATA_C => SUMMAND(466), SAVE => INT_SUM(457), CARRY => INT_CARRY(363) ); ---- End FA stage ---- Begin FA stage FA_366:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(467), DATA_B => SUMMAND(468), DATA_C => SUMMAND(469), SAVE => INT_SUM(458), CARRY => INT_CARRY(364) ); ---- End FA stage ---- Begin FA stage FA_367:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(470), DATA_B => SUMMAND(471), DATA_C => SUMMAND(472), SAVE => INT_SUM(459), CARRY => INT_CARRY(365) ); ---- End FA stage ---- Begin FA stage FA_368:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(473), DATA_B => INT_CARRY(350), DATA_C => INT_CARRY(351), SAVE => INT_SUM(460), CARRY => INT_CARRY(366) ); ---- End FA stage ---- Begin NO stage INT_SUM(461) <= INT_CARRY(352); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(462) <= INT_CARRY(353); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_369:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(456), DATA_B => INT_SUM(457), DATA_C => INT_SUM(458), SAVE => INT_SUM(463), CARRY => INT_CARRY(367) ); ---- End FA stage ---- Begin FA stage FA_370:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(459), DATA_B => INT_SUM(460), DATA_C => INT_SUM(461), SAVE => INT_SUM(464), CARRY => INT_CARRY(368) ); ---- End FA stage ---- Begin FA stage FA_371:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(462), DATA_B => INT_CARRY(354), DATA_C => INT_CARRY(355), SAVE => INT_SUM(465), CARRY => INT_CARRY(369) ); ---- End FA stage ---- Begin NO stage INT_SUM(466) <= INT_CARRY(356); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_372:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(463), DATA_B => INT_SUM(464), DATA_C => INT_SUM(465), SAVE => INT_SUM(467), CARRY => INT_CARRY(370) ); ---- End FA stage ---- Begin FA stage FA_373:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(466), DATA_B => INT_CARRY(357), DATA_C => INT_CARRY(358), SAVE => INT_SUM(468), CARRY => INT_CARRY(371) ); ---- End FA stage ---- Begin FA stage FA_374:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(467), DATA_B => INT_SUM(468), DATA_C => INT_CARRY(359), SAVE => INT_SUM(469), CARRY => INT_CARRY(372) ); ---- End FA stage ---- Begin NO stage INT_SUM(470) <= INT_CARRY(360); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_375:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(469), DATA_B => INT_SUM(470), DATA_C => INT_CARRY(361), SAVE => SUM(43), CARRY => CARRY(43) ); ---- End FA stage -- End WT-branch 44 -- Begin WT-branch 45 ---- Begin FA stage FA_376:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(474), DATA_B => SUMMAND(475), DATA_C => SUMMAND(476), SAVE => INT_SUM(471), CARRY => INT_CARRY(373) ); ---- End FA stage ---- Begin FA stage FA_377:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(477), DATA_B => SUMMAND(478), DATA_C => SUMMAND(479), SAVE => INT_SUM(472), CARRY => INT_CARRY(374) ); ---- End FA stage ---- Begin FA stage FA_378:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(480), DATA_B => SUMMAND(481), DATA_C => SUMMAND(482), SAVE => INT_SUM(473), CARRY => INT_CARRY(375) ); ---- End FA stage ---- Begin FA stage FA_379:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(483), DATA_B => SUMMAND(484), DATA_C => SUMMAND(485), SAVE => INT_SUM(474), CARRY => INT_CARRY(376) ); ---- End FA stage ---- Begin FA stage FA_380:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(471), DATA_B => INT_SUM(472), DATA_C => INT_SUM(473), SAVE => INT_SUM(475), CARRY => INT_CARRY(377) ); ---- End FA stage ---- Begin FA stage FA_381:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(474), DATA_B => INT_CARRY(362), DATA_C => INT_CARRY(363), SAVE => INT_SUM(476), CARRY => INT_CARRY(378) ); ---- End FA stage ---- Begin FA stage FA_382:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(364), DATA_B => INT_CARRY(365), DATA_C => INT_CARRY(366), SAVE => INT_SUM(477), CARRY => INT_CARRY(379) ); ---- End FA stage ---- Begin FA stage FA_383:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(475), DATA_B => INT_SUM(476), DATA_C => INT_SUM(477), SAVE => INT_SUM(478), CARRY => INT_CARRY(380) ); ---- End FA stage ---- Begin FA stage FA_384:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(367), DATA_B => INT_CARRY(368), DATA_C => INT_CARRY(369), SAVE => INT_SUM(479), CARRY => INT_CARRY(381) ); ---- End FA stage ---- Begin FA stage FA_385:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(478), DATA_B => INT_SUM(479), DATA_C => INT_CARRY(370), SAVE => INT_SUM(480), CARRY => INT_CARRY(382) ); ---- End FA stage ---- Begin NO stage INT_SUM(481) <= INT_CARRY(371); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_386:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(480), DATA_B => INT_SUM(481), DATA_C => INT_CARRY(372), SAVE => SUM(44), CARRY => CARRY(44) ); ---- End FA stage -- End WT-branch 45 -- Begin WT-branch 46 ---- Begin FA stage FA_387:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(486), DATA_B => SUMMAND(487), DATA_C => SUMMAND(488), SAVE => INT_SUM(482), CARRY => INT_CARRY(383) ); ---- End FA stage ---- Begin FA stage FA_388:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(489), DATA_B => SUMMAND(490), DATA_C => SUMMAND(491), SAVE => INT_SUM(483), CARRY => INT_CARRY(384) ); ---- End FA stage ---- Begin FA stage FA_389:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(492), DATA_B => SUMMAND(493), DATA_C => SUMMAND(494), SAVE => INT_SUM(484), CARRY => INT_CARRY(385) ); ---- End FA stage ---- Begin FA stage FA_390:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(495), DATA_B => SUMMAND(496), DATA_C => SUMMAND(497), SAVE => INT_SUM(485), CARRY => INT_CARRY(386) ); ---- End FA stage ---- Begin FA stage FA_391:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(482), DATA_B => INT_SUM(483), DATA_C => INT_SUM(484), SAVE => INT_SUM(486), CARRY => INT_CARRY(387) ); ---- End FA stage ---- Begin FA stage FA_392:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(485), DATA_B => INT_CARRY(373), DATA_C => INT_CARRY(374), SAVE => INT_SUM(487), CARRY => INT_CARRY(388) ); ---- End FA stage ---- Begin HA stage HA_40:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(375), DATA_B => INT_CARRY(376), SAVE => INT_SUM(488), CARRY => INT_CARRY(389) ); ---- End HA stage ---- Begin FA stage FA_393:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(486), DATA_B => INT_SUM(487), DATA_C => INT_SUM(488), SAVE => INT_SUM(489), CARRY => INT_CARRY(390) ); ---- End FA stage ---- Begin FA stage FA_394:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(377), DATA_B => INT_CARRY(378), DATA_C => INT_CARRY(379), SAVE => INT_SUM(490), CARRY => INT_CARRY(391) ); ---- End FA stage ---- Begin FA stage FA_395:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(489), DATA_B => INT_SUM(490), DATA_C => INT_CARRY(380), SAVE => INT_SUM(491), CARRY => INT_CARRY(392) ); ---- End FA stage ---- Begin NO stage INT_SUM(492) <= INT_CARRY(381); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_396:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(491), DATA_B => INT_SUM(492), DATA_C => INT_CARRY(382), SAVE => SUM(45), CARRY => CARRY(45) ); ---- End FA stage -- End WT-branch 46 -- Begin WT-branch 47 ---- Begin FA stage FA_397:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(498), DATA_B => SUMMAND(499), DATA_C => SUMMAND(500), SAVE => INT_SUM(493), CARRY => INT_CARRY(393) ); ---- End FA stage ---- Begin FA stage FA_398:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(501), DATA_B => SUMMAND(502), DATA_C => SUMMAND(503), SAVE => INT_SUM(494), CARRY => INT_CARRY(394) ); ---- End FA stage ---- Begin FA stage FA_399:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(504), DATA_B => SUMMAND(505), DATA_C => SUMMAND(506), SAVE => INT_SUM(495), CARRY => INT_CARRY(395) ); ---- End FA stage ---- Begin NO stage INT_SUM(496) <= SUMMAND(507); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(497) <= SUMMAND(508); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_400:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(493), DATA_B => INT_SUM(494), DATA_C => INT_SUM(495), SAVE => INT_SUM(498), CARRY => INT_CARRY(396) ); ---- End FA stage ---- Begin FA stage FA_401:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(496), DATA_B => INT_SUM(497), DATA_C => INT_CARRY(383), SAVE => INT_SUM(499), CARRY => INT_CARRY(397) ); ---- End FA stage ---- Begin FA stage FA_402:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(384), DATA_B => INT_CARRY(385), DATA_C => INT_CARRY(386), SAVE => INT_SUM(500), CARRY => INT_CARRY(398) ); ---- End FA stage ---- Begin FA stage FA_403:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(498), DATA_B => INT_SUM(499), DATA_C => INT_SUM(500), SAVE => INT_SUM(501), CARRY => INT_CARRY(399) ); ---- End FA stage ---- Begin FA stage FA_404:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(387), DATA_B => INT_CARRY(388), DATA_C => INT_CARRY(389), SAVE => INT_SUM(502), CARRY => INT_CARRY(400) ); ---- End FA stage ---- Begin FA stage FA_405:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(501), DATA_B => INT_SUM(502), DATA_C => INT_CARRY(390), SAVE => INT_SUM(503), CARRY => INT_CARRY(401) ); ---- End FA stage ---- Begin NO stage INT_SUM(504) <= INT_CARRY(391); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_406:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(503), DATA_B => INT_SUM(504), DATA_C => INT_CARRY(392), SAVE => SUM(46), CARRY => CARRY(46) ); ---- End FA stage -- End WT-branch 47 -- Begin WT-branch 48 ---- Begin FA stage FA_407:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(509), DATA_B => SUMMAND(510), DATA_C => SUMMAND(511), SAVE => INT_SUM(505), CARRY => INT_CARRY(402) ); ---- End FA stage ---- Begin FA stage FA_408:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(512), DATA_B => SUMMAND(513), DATA_C => SUMMAND(514), SAVE => INT_SUM(506), CARRY => INT_CARRY(403) ); ---- End FA stage ---- Begin FA stage FA_409:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(515), DATA_B => SUMMAND(516), DATA_C => SUMMAND(517), SAVE => INT_SUM(507), CARRY => INT_CARRY(404) ); ---- End FA stage ---- Begin HA stage HA_41:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(518), DATA_B => SUMMAND(519), SAVE => INT_SUM(508), CARRY => INT_CARRY(405) ); ---- End HA stage ---- Begin FA stage FA_410:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(505), DATA_B => INT_SUM(506), DATA_C => INT_SUM(507), SAVE => INT_SUM(509), CARRY => INT_CARRY(406) ); ---- End FA stage ---- Begin FA stage FA_411:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(508), DATA_B => INT_CARRY(393), DATA_C => INT_CARRY(394), SAVE => INT_SUM(510), CARRY => INT_CARRY(407) ); ---- End FA stage ---- Begin NO stage INT_SUM(511) <= INT_CARRY(395); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_412:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(509), DATA_B => INT_SUM(510), DATA_C => INT_SUM(511), SAVE => INT_SUM(512), CARRY => INT_CARRY(408) ); ---- End FA stage ---- Begin FA stage FA_413:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(396), DATA_B => INT_CARRY(397), DATA_C => INT_CARRY(398), SAVE => INT_SUM(513), CARRY => INT_CARRY(409) ); ---- End FA stage ---- Begin FA stage FA_414:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(512), DATA_B => INT_SUM(513), DATA_C => INT_CARRY(399), SAVE => INT_SUM(514), CARRY => INT_CARRY(410) ); ---- End FA stage ---- Begin NO stage INT_SUM(515) <= INT_CARRY(400); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_415:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(514), DATA_B => INT_SUM(515), DATA_C => INT_CARRY(401), SAVE => SUM(47), CARRY => CARRY(47) ); ---- End FA stage -- End WT-branch 48 -- Begin WT-branch 49 ---- Begin FA stage FA_416:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(520), DATA_B => SUMMAND(521), DATA_C => SUMMAND(522), SAVE => INT_SUM(516), CARRY => INT_CARRY(411) ); ---- End FA stage ---- Begin FA stage FA_417:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(523), DATA_B => SUMMAND(524), DATA_C => SUMMAND(525), SAVE => INT_SUM(517), CARRY => INT_CARRY(412) ); ---- End FA stage ---- Begin FA stage FA_418:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(526), DATA_B => SUMMAND(527), DATA_C => SUMMAND(528), SAVE => INT_SUM(518), CARRY => INT_CARRY(413) ); ---- End FA stage ---- Begin NO stage INT_SUM(519) <= SUMMAND(529); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_419:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(516), DATA_B => INT_SUM(517), DATA_C => INT_SUM(518), SAVE => INT_SUM(520), CARRY => INT_CARRY(414) ); ---- End FA stage ---- Begin FA stage FA_420:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(519), DATA_B => INT_CARRY(402), DATA_C => INT_CARRY(403), SAVE => INT_SUM(521), CARRY => INT_CARRY(415) ); ---- End FA stage ---- Begin NO stage INT_SUM(522) <= INT_CARRY(404); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(523) <= INT_CARRY(405); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_421:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(520), DATA_B => INT_SUM(521), DATA_C => INT_SUM(522), SAVE => INT_SUM(524), CARRY => INT_CARRY(416) ); ---- End FA stage ---- Begin FA stage FA_422:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(523), DATA_B => INT_CARRY(406), DATA_C => INT_CARRY(407), SAVE => INT_SUM(525), CARRY => INT_CARRY(417) ); ---- End FA stage ---- Begin FA stage FA_423:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(524), DATA_B => INT_SUM(525), DATA_C => INT_CARRY(408), SAVE => INT_SUM(526), CARRY => INT_CARRY(418) ); ---- End FA stage ---- Begin NO stage INT_SUM(527) <= INT_CARRY(409); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_424:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(526), DATA_B => INT_SUM(527), DATA_C => INT_CARRY(410), SAVE => SUM(48), CARRY => CARRY(48) ); ---- End FA stage -- End WT-branch 49 -- Begin WT-branch 50 ---- Begin FA stage FA_425:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(530), DATA_B => SUMMAND(531), DATA_C => SUMMAND(532), SAVE => INT_SUM(528), CARRY => INT_CARRY(419) ); ---- End FA stage ---- Begin FA stage FA_426:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(533), DATA_B => SUMMAND(534), DATA_C => SUMMAND(535), SAVE => INT_SUM(529), CARRY => INT_CARRY(420) ); ---- End FA stage ---- Begin FA stage FA_427:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(536), DATA_B => SUMMAND(537), DATA_C => SUMMAND(538), SAVE => INT_SUM(530), CARRY => INT_CARRY(421) ); ---- End FA stage ---- Begin NO stage INT_SUM(531) <= SUMMAND(539); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_428:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(528), DATA_B => INT_SUM(529), DATA_C => INT_SUM(530), SAVE => INT_SUM(532), CARRY => INT_CARRY(422) ); ---- End FA stage ---- Begin FA stage FA_429:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(531), DATA_B => INT_CARRY(411), DATA_C => INT_CARRY(412), SAVE => INT_SUM(533), CARRY => INT_CARRY(423) ); ---- End FA stage ---- Begin NO stage INT_SUM(534) <= INT_CARRY(413); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_430:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(532), DATA_B => INT_SUM(533), DATA_C => INT_SUM(534), SAVE => INT_SUM(535), CARRY => INT_CARRY(424) ); ---- End FA stage ---- Begin HA stage HA_42:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(414), DATA_B => INT_CARRY(415), SAVE => INT_SUM(536), CARRY => INT_CARRY(425) ); ---- End HA stage ---- Begin FA stage FA_431:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(535), DATA_B => INT_SUM(536), DATA_C => INT_CARRY(416), SAVE => INT_SUM(537), CARRY => INT_CARRY(426) ); ---- End FA stage ---- Begin NO stage INT_SUM(538) <= INT_CARRY(417); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_432:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(537), DATA_B => INT_SUM(538), DATA_C => INT_CARRY(418), SAVE => SUM(49), CARRY => CARRY(49) ); ---- End FA stage -- End WT-branch 50 -- Begin WT-branch 51 ---- Begin FA stage FA_433:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(540), DATA_B => SUMMAND(541), DATA_C => SUMMAND(542), SAVE => INT_SUM(539), CARRY => INT_CARRY(427) ); ---- End FA stage ---- Begin FA stage FA_434:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(543), DATA_B => SUMMAND(544), DATA_C => SUMMAND(545), SAVE => INT_SUM(540), CARRY => INT_CARRY(428) ); ---- End FA stage ---- Begin FA stage FA_435:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(546), DATA_B => SUMMAND(547), DATA_C => SUMMAND(548), SAVE => INT_SUM(541), CARRY => INT_CARRY(429) ); ---- End FA stage ---- Begin FA stage FA_436:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(539), DATA_B => INT_SUM(540), DATA_C => INT_SUM(541), SAVE => INT_SUM(542), CARRY => INT_CARRY(430) ); ---- End FA stage ---- Begin FA stage FA_437:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(419), DATA_B => INT_CARRY(420), DATA_C => INT_CARRY(421), SAVE => INT_SUM(543), CARRY => INT_CARRY(431) ); ---- End FA stage ---- Begin FA stage FA_438:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(542), DATA_B => INT_SUM(543), DATA_C => INT_CARRY(422), SAVE => INT_SUM(544), CARRY => INT_CARRY(432) ); ---- End FA stage ---- Begin NO stage INT_SUM(545) <= INT_CARRY(423); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_439:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(544), DATA_B => INT_SUM(545), DATA_C => INT_CARRY(424), SAVE => INT_SUM(546), CARRY => INT_CARRY(433) ); ---- End FA stage ---- Begin NO stage INT_SUM(547) <= INT_CARRY(425); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_440:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(546), DATA_B => INT_SUM(547), DATA_C => INT_CARRY(426), SAVE => SUM(50), CARRY => CARRY(50) ); ---- End FA stage -- End WT-branch 51 -- Begin WT-branch 52 ---- Begin FA stage FA_441:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(549), DATA_B => SUMMAND(550), DATA_C => SUMMAND(551), SAVE => INT_SUM(548), CARRY => INT_CARRY(434) ); ---- End FA stage ---- Begin FA stage FA_442:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(552), DATA_B => SUMMAND(553), DATA_C => SUMMAND(554), SAVE => INT_SUM(549), CARRY => INT_CARRY(435) ); ---- End FA stage ---- Begin FA stage FA_443:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(555), DATA_B => SUMMAND(556), DATA_C => SUMMAND(557), SAVE => INT_SUM(550), CARRY => INT_CARRY(436) ); ---- End FA stage ---- Begin FA stage FA_444:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(548), DATA_B => INT_SUM(549), DATA_C => INT_SUM(550), SAVE => INT_SUM(551), CARRY => INT_CARRY(437) ); ---- End FA stage ---- Begin FA stage FA_445:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(427), DATA_B => INT_CARRY(428), DATA_C => INT_CARRY(429), SAVE => INT_SUM(552), CARRY => INT_CARRY(438) ); ---- End FA stage ---- Begin FA stage FA_446:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(551), DATA_B => INT_SUM(552), DATA_C => INT_CARRY(430), SAVE => INT_SUM(553), CARRY => INT_CARRY(439) ); ---- End FA stage ---- Begin NO stage INT_SUM(554) <= INT_CARRY(431); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_447:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(553), DATA_B => INT_SUM(554), DATA_C => INT_CARRY(432), SAVE => INT_SUM(555), CARRY => INT_CARRY(440) ); ---- End FA stage ---- Begin HA stage HA_43:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(555), DATA_B => INT_CARRY(433), SAVE => SUM(51), CARRY => CARRY(51) ); ---- End HA stage -- End WT-branch 52 -- Begin WT-branch 53 ---- Begin FA stage FA_448:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(558), DATA_B => SUMMAND(559), DATA_C => SUMMAND(560), SAVE => INT_SUM(556), CARRY => INT_CARRY(441) ); ---- End FA stage ---- Begin FA stage FA_449:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(561), DATA_B => SUMMAND(562), DATA_C => SUMMAND(563), SAVE => INT_SUM(557), CARRY => INT_CARRY(442) ); ---- End FA stage ---- Begin FA stage FA_450:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(564), DATA_B => SUMMAND(565), DATA_C => INT_CARRY(434), SAVE => INT_SUM(558), CARRY => INT_CARRY(443) ); ---- End FA stage ---- Begin HA stage HA_44:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(435), DATA_B => INT_CARRY(436), SAVE => INT_SUM(559), CARRY => INT_CARRY(444) ); ---- End HA stage ---- Begin FA stage FA_451:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(556), DATA_B => INT_SUM(557), DATA_C => INT_SUM(558), SAVE => INT_SUM(560), CARRY => INT_CARRY(445) ); ---- End FA stage ---- Begin FA stage FA_452:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(559), DATA_B => INT_CARRY(437), DATA_C => INT_CARRY(438), SAVE => INT_SUM(561), CARRY => INT_CARRY(446) ); ---- End FA stage ---- Begin FA stage FA_453:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(560), DATA_B => INT_SUM(561), DATA_C => INT_CARRY(439), SAVE => INT_SUM(562), CARRY => INT_CARRY(447) ); ---- End FA stage ---- Begin HA stage HA_45:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(562), DATA_B => INT_CARRY(440), SAVE => SUM(52), CARRY => CARRY(52) ); ---- End HA stage -- End WT-branch 53 -- Begin WT-branch 54 ---- Begin FA stage FA_454:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(566), DATA_B => SUMMAND(567), DATA_C => SUMMAND(568), SAVE => INT_SUM(563), CARRY => INT_CARRY(448) ); ---- End FA stage ---- Begin FA stage FA_455:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(569), DATA_B => SUMMAND(570), DATA_C => SUMMAND(571), SAVE => INT_SUM(564), CARRY => INT_CARRY(449) ); ---- End FA stage ---- Begin NO stage INT_SUM(565) <= SUMMAND(572); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(566) <= SUMMAND(573); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_456:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(563), DATA_B => INT_SUM(564), DATA_C => INT_SUM(565), SAVE => INT_SUM(567), CARRY => INT_CARRY(450) ); ---- End FA stage ---- Begin NO stage INT_SUM(568) <= INT_SUM(566); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_457:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(567), DATA_B => INT_SUM(568), DATA_C => INT_CARRY(441), SAVE => INT_SUM(569), CARRY => INT_CARRY(451) ); ---- End FA stage ---- Begin FA stage FA_458:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(442), DATA_B => INT_CARRY(443), DATA_C => INT_CARRY(444), SAVE => INT_SUM(570), CARRY => INT_CARRY(452) ); ---- End FA stage ---- Begin FA stage FA_459:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(569), DATA_B => INT_SUM(570), DATA_C => INT_CARRY(445), SAVE => INT_SUM(571), CARRY => INT_CARRY(453) ); ---- End FA stage ---- Begin NO stage INT_SUM(572) <= INT_CARRY(446); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_460:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(571), DATA_B => INT_SUM(572), DATA_C => INT_CARRY(447), SAVE => SUM(53), CARRY => CARRY(53) ); ---- End FA stage -- End WT-branch 54 -- Begin WT-branch 55 ---- Begin FA stage FA_461:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(574), DATA_B => SUMMAND(575), DATA_C => SUMMAND(576), SAVE => INT_SUM(573), CARRY => INT_CARRY(454) ); ---- End FA stage ---- Begin FA stage FA_462:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(577), DATA_B => SUMMAND(578), DATA_C => SUMMAND(579), SAVE => INT_SUM(574), CARRY => INT_CARRY(455) ); ---- End FA stage ---- Begin FA stage FA_463:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(580), DATA_B => INT_CARRY(448), DATA_C => INT_CARRY(449), SAVE => INT_SUM(575), CARRY => INT_CARRY(456) ); ---- End FA stage ---- Begin FA stage FA_464:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(573), DATA_B => INT_SUM(574), DATA_C => INT_SUM(575), SAVE => INT_SUM(576), CARRY => INT_CARRY(457) ); ---- End FA stage ---- Begin NO stage INT_SUM(577) <= INT_CARRY(450); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_465:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(576), DATA_B => INT_SUM(577), DATA_C => INT_CARRY(451), SAVE => INT_SUM(578), CARRY => INT_CARRY(458) ); ---- End FA stage ---- Begin NO stage INT_SUM(579) <= INT_CARRY(452); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_466:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(578), DATA_B => INT_SUM(579), DATA_C => INT_CARRY(453), SAVE => SUM(54), CARRY => CARRY(54) ); ---- End FA stage -- End WT-branch 55 -- Begin WT-branch 56 ---- Begin FA stage FA_467:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(581), DATA_B => SUMMAND(582), DATA_C => SUMMAND(583), SAVE => INT_SUM(580), CARRY => INT_CARRY(459) ); ---- End FA stage ---- Begin FA stage FA_468:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(584), DATA_B => SUMMAND(585), DATA_C => SUMMAND(586), SAVE => INT_SUM(581), CARRY => INT_CARRY(460) ); ---- End FA stage ---- Begin NO stage INT_SUM(582) <= SUMMAND(587); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_469:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(580), DATA_B => INT_SUM(581), DATA_C => INT_SUM(582), SAVE => INT_SUM(583), CARRY => INT_CARRY(461) ); ---- End FA stage ---- Begin FA stage FA_470:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(454), DATA_B => INT_CARRY(455), DATA_C => INT_CARRY(456), SAVE => INT_SUM(584), CARRY => INT_CARRY(462) ); ---- End FA stage ---- Begin FA stage FA_471:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(583), DATA_B => INT_SUM(584), DATA_C => INT_CARRY(457), SAVE => INT_SUM(585), CARRY => INT_CARRY(463) ); ---- End FA stage ---- Begin HA stage HA_46:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(585), DATA_B => INT_CARRY(458), SAVE => SUM(55), CARRY => CARRY(55) ); ---- End HA stage -- End WT-branch 56 -- Begin WT-branch 57 ---- Begin FA stage FA_472:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(588), DATA_B => SUMMAND(589), DATA_C => SUMMAND(590), SAVE => INT_SUM(586), CARRY => INT_CARRY(464) ); ---- End FA stage ---- Begin FA stage FA_473:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(591), DATA_B => SUMMAND(592), DATA_C => SUMMAND(593), SAVE => INT_SUM(587), CARRY => INT_CARRY(465) ); ---- End FA stage ---- Begin FA stage FA_474:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(586), DATA_B => INT_SUM(587), DATA_C => INT_CARRY(459), SAVE => INT_SUM(588), CARRY => INT_CARRY(466) ); ---- End FA stage ---- Begin NO stage INT_SUM(589) <= INT_CARRY(460); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_475:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(588), DATA_B => INT_SUM(589), DATA_C => INT_CARRY(461), SAVE => INT_SUM(590), CARRY => INT_CARRY(467) ); ---- End FA stage ---- Begin NO stage INT_SUM(591) <= INT_CARRY(462); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_476:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(590), DATA_B => INT_SUM(591), DATA_C => INT_CARRY(463), SAVE => SUM(56), CARRY => CARRY(56) ); ---- End FA stage -- End WT-branch 57 -- Begin WT-branch 58 ---- Begin FA stage FA_477:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(594), DATA_B => SUMMAND(595), DATA_C => SUMMAND(596), SAVE => INT_SUM(592), CARRY => INT_CARRY(468) ); ---- End FA stage ---- Begin FA stage FA_478:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(597), DATA_B => SUMMAND(598), DATA_C => SUMMAND(599), SAVE => INT_SUM(593), CARRY => INT_CARRY(469) ); ---- End FA stage ---- Begin FA stage FA_479:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(592), DATA_B => INT_SUM(593), DATA_C => INT_CARRY(464), SAVE => INT_SUM(594), CARRY => INT_CARRY(470) ); ---- End FA stage ---- Begin NO stage INT_SUM(595) <= INT_CARRY(465); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_480:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(594), DATA_B => INT_SUM(595), DATA_C => INT_CARRY(466), SAVE => INT_SUM(596), CARRY => INT_CARRY(471) ); ---- End FA stage ---- Begin HA stage HA_47:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(596), DATA_B => INT_CARRY(467), SAVE => SUM(57), CARRY => CARRY(57) ); ---- End HA stage -- End WT-branch 58 -- Begin WT-branch 59 ---- Begin FA stage FA_481:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(600), DATA_B => SUMMAND(601), DATA_C => SUMMAND(602), SAVE => INT_SUM(597), CARRY => INT_CARRY(472) ); ---- End FA stage ---- Begin HA stage HA_48:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(603), DATA_B => SUMMAND(604), SAVE => INT_SUM(598), CARRY => INT_CARRY(473) ); ---- End HA stage ---- Begin FA stage FA_482:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(597), DATA_B => INT_SUM(598), DATA_C => INT_CARRY(468), SAVE => INT_SUM(599), CARRY => INT_CARRY(474) ); ---- End FA stage ---- Begin NO stage INT_SUM(600) <= INT_CARRY(469); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_483:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(599), DATA_B => INT_SUM(600), DATA_C => INT_CARRY(470), SAVE => INT_SUM(601), CARRY => INT_CARRY(475) ); ---- End FA stage ---- Begin HA stage HA_49:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(601), DATA_B => INT_CARRY(471), SAVE => SUM(58), CARRY => CARRY(58) ); ---- End HA stage -- End WT-branch 59 -- Begin WT-branch 60 ---- Begin FA stage FA_484:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(605), DATA_B => SUMMAND(606), DATA_C => SUMMAND(607), SAVE => INT_SUM(602), CARRY => INT_CARRY(476) ); ---- End FA stage ---- Begin HA stage HA_50:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(608), DATA_B => SUMMAND(609), SAVE => INT_SUM(603), CARRY => INT_CARRY(477) ); ---- End HA stage ---- Begin FA stage FA_485:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(602), DATA_B => INT_SUM(603), DATA_C => INT_CARRY(472), SAVE => INT_SUM(604), CARRY => INT_CARRY(478) ); ---- End FA stage ---- Begin NO stage INT_SUM(605) <= INT_CARRY(473); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_486:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(604), DATA_B => INT_SUM(605), DATA_C => INT_CARRY(474), SAVE => INT_SUM(606), CARRY => INT_CARRY(479) ); ---- End FA stage ---- Begin HA stage HA_51:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(606), DATA_B => INT_CARRY(475), SAVE => SUM(59), CARRY => CARRY(59) ); ---- End HA stage -- End WT-branch 60 -- Begin WT-branch 61 ---- Begin FA stage FA_487:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(610), DATA_B => SUMMAND(611), DATA_C => SUMMAND(612), SAVE => INT_SUM(607), CARRY => INT_CARRY(480) ); ---- End FA stage ---- Begin FA stage FA_488:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(613), DATA_B => INT_CARRY(476), DATA_C => INT_CARRY(477), SAVE => INT_SUM(608), CARRY => INT_CARRY(481) ); ---- End FA stage ---- Begin FA stage FA_489:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(607), DATA_B => INT_SUM(608), DATA_C => INT_CARRY(478), SAVE => INT_SUM(609), CARRY => INT_CARRY(482) ); ---- End FA stage ---- Begin HA stage HA_52:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(609), DATA_B => INT_CARRY(479), SAVE => SUM(60), CARRY => CARRY(60) ); ---- End HA stage -- End WT-branch 61 -- Begin WT-branch 62 ---- Begin FA stage FA_490:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(614), DATA_B => SUMMAND(615), DATA_C => SUMMAND(616), SAVE => INT_SUM(610), CARRY => INT_CARRY(483) ); ---- End FA stage ---- Begin NO stage INT_SUM(611) <= SUMMAND(617); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_491:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(610), DATA_B => INT_SUM(611), DATA_C => INT_CARRY(480), SAVE => INT_SUM(612), CARRY => INT_CARRY(484) ); ---- End FA stage ---- Begin NO stage INT_SUM(613) <= INT_CARRY(481); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_492:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(612), DATA_B => INT_SUM(613), DATA_C => INT_CARRY(482), SAVE => SUM(61), CARRY => CARRY(61) ); ---- End FA stage -- End WT-branch 62 -- Begin WT-branch 63 ---- Begin FA stage FA_493:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(618), DATA_B => SUMMAND(619), DATA_C => SUMMAND(620), SAVE => INT_SUM(614), CARRY => INT_CARRY(485) ); ---- End FA stage ---- Begin NO stage INT_SUM(615) <= INT_SUM(614); -- At Level 5 ---- End NO stage ---- Begin NO stage INT_SUM(616) <= INT_CARRY(483); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_494:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(615), DATA_B => INT_SUM(616), DATA_C => INT_CARRY(484), SAVE => SUM(62), CARRY => CARRY(62) ); ---- End FA stage -- End WT-branch 63 -- Begin WT-branch 64 ---- Begin FA stage FA_495:FULL_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(621), DATA_B => SUMMAND(622), DATA_C => SUMMAND(623), SAVE => INT_SUM(617), CARRY => INT_CARRY(486) ); ---- End FA stage ---- Begin NO stage INT_SUM(618) <= INT_CARRY(485); -- At Level 5 ---- End NO stage ---- Begin HA stage HA_53:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(617), DATA_B => INT_SUM(618), SAVE => SUM(63), CARRY => CARRY(63) ); ---- End HA stage -- End WT-branch 64 -- Begin WT-branch 65 ---- Begin NO stage INT_SUM(619) <= SUMMAND(624); -- At Level 5 ---- End NO stage ---- Begin NO stage INT_SUM(620) <= SUMMAND(625); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_496:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(619), DATA_B => INT_SUM(620), DATA_C => INT_CARRY(486), SAVE => SUM(64), CARRY => CARRY(64) ); ---- End FA stage -- End WT-branch 65 -- Begin WT-branch 66 ---- Begin HA stage HA_54:HALF_ADDER -- At Level 6 port map ( DATA_A => SUMMAND(626), DATA_B => SUMMAND(627), SAVE => SUM(65), CARRY => CARRY(65) ); ---- End HA stage -- End WT-branch 66 -- Begin WT-branch 67 ---- Begin NO stage SUM(66) <= SUMMAND(628); -- At Level 6 ---- End NO stage -- End WT-branch 67 end WALLACE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_34 is generic (mulpipe : integer := 0); port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 33); PHI: in std_logic; holdn: in std_logic; RESULT: out std_logic_vector(0 to 127) ); end MULTIPLIER_34_34; architecture MULTIPLIER of MULTIPLIER_34_34 is signal PPBIT:std_logic_vector(0 to 628); signal INT_CARRY: std_logic_vector(0 to 128); signal INT_SUM: std_logic_vector(0 to 127); signal LOGIC_ZERO: std_logic; signal INT_CARRYR: std_logic_vector(0 to 128); signal INT_SUMR: std_logic_vector(0 to 127); begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_34 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 33) => MULTIPLIER(0 to 33), SUMMAND(0 to 628) => PPBIT(0 to 628) ); W:WALLACE_34_34 port map ( SUMMAND(0 to 628) => PPBIT(0 to 628), CARRY(0 to 65) => INT_CARRY(1 to 66), SUM(0 to 66) => INT_SUM(0 to 66) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(67) <= LOGIC_ZERO; INT_CARRY(68) <= LOGIC_ZERO; INT_CARRY(69) <= LOGIC_ZERO; INT_CARRY(70) <= LOGIC_ZERO; INT_CARRY(71) <= LOGIC_ZERO; INT_CARRY(72) <= LOGIC_ZERO; INT_CARRY(73) <= LOGIC_ZERO; INT_CARRY(74) <= LOGIC_ZERO; INT_CARRY(75) <= LOGIC_ZERO; INT_CARRY(76) <= LOGIC_ZERO; INT_CARRY(77) <= LOGIC_ZERO; INT_CARRY(78) <= LOGIC_ZERO; INT_CARRY(79) <= LOGIC_ZERO; INT_CARRY(80) <= LOGIC_ZERO; INT_CARRY(81) <= LOGIC_ZERO; INT_CARRY(82) <= LOGIC_ZERO; INT_CARRY(83) <= LOGIC_ZERO; INT_CARRY(84) <= LOGIC_ZERO; INT_CARRY(85) <= LOGIC_ZERO; INT_CARRY(86) <= LOGIC_ZERO; INT_CARRY(87) <= LOGIC_ZERO; INT_CARRY(88) <= LOGIC_ZERO; INT_CARRY(89) <= LOGIC_ZERO; INT_CARRY(90) <= LOGIC_ZERO; INT_CARRY(91) <= LOGIC_ZERO; INT_CARRY(92) <= LOGIC_ZERO; INT_CARRY(93) <= LOGIC_ZERO; INT_CARRY(94) <= LOGIC_ZERO; INT_CARRY(95) <= LOGIC_ZERO; INT_CARRY(96) <= LOGIC_ZERO; INT_CARRY(97) <= LOGIC_ZERO; INT_CARRY(98) <= LOGIC_ZERO; INT_CARRY(99) <= LOGIC_ZERO; INT_CARRY(100) <= LOGIC_ZERO; INT_CARRY(101) <= LOGIC_ZERO; INT_CARRY(102) <= LOGIC_ZERO; INT_CARRY(103) <= LOGIC_ZERO; INT_CARRY(104) <= LOGIC_ZERO; INT_CARRY(105) <= LOGIC_ZERO; INT_CARRY(106) <= LOGIC_ZERO; INT_CARRY(107) <= LOGIC_ZERO; INT_CARRY(108) <= LOGIC_ZERO; INT_CARRY(109) <= LOGIC_ZERO; INT_CARRY(110) <= LOGIC_ZERO; INT_CARRY(111) <= LOGIC_ZERO; INT_CARRY(112) <= LOGIC_ZERO; INT_CARRY(113) <= LOGIC_ZERO; INT_CARRY(114) <= LOGIC_ZERO; INT_CARRY(115) <= LOGIC_ZERO; INT_CARRY(116) <= LOGIC_ZERO; INT_CARRY(117) <= LOGIC_ZERO; INT_CARRY(118) <= LOGIC_ZERO; INT_CARRY(119) <= LOGIC_ZERO; INT_CARRY(120) <= LOGIC_ZERO; INT_CARRY(121) <= LOGIC_ZERO; INT_CARRY(122) <= LOGIC_ZERO; INT_CARRY(123) <= LOGIC_ZERO; INT_CARRY(124) <= LOGIC_ZERO; INT_CARRY(125) <= LOGIC_ZERO; INT_CARRY(126) <= LOGIC_ZERO; INT_CARRY(127) <= LOGIC_ZERO; INT_SUM(67) <= LOGIC_ZERO; INT_SUM(68) <= LOGIC_ZERO; INT_SUM(69) <= LOGIC_ZERO; INT_SUM(70) <= LOGIC_ZERO; INT_SUM(71) <= LOGIC_ZERO; INT_SUM(72) <= LOGIC_ZERO; INT_SUM(73) <= LOGIC_ZERO; INT_SUM(74) <= LOGIC_ZERO; INT_SUM(75) <= LOGIC_ZERO; INT_SUM(76) <= LOGIC_ZERO; INT_SUM(77) <= LOGIC_ZERO; INT_SUM(78) <= LOGIC_ZERO; INT_SUM(79) <= LOGIC_ZERO; INT_SUM(80) <= LOGIC_ZERO; INT_SUM(81) <= LOGIC_ZERO; INT_SUM(82) <= LOGIC_ZERO; INT_SUM(83) <= LOGIC_ZERO; INT_SUM(84) <= LOGIC_ZERO; INT_SUM(85) <= LOGIC_ZERO; INT_SUM(86) <= LOGIC_ZERO; INT_SUM(87) <= LOGIC_ZERO; INT_SUM(88) <= LOGIC_ZERO; INT_SUM(89) <= LOGIC_ZERO; INT_SUM(90) <= LOGIC_ZERO; INT_SUM(91) <= LOGIC_ZERO; INT_SUM(92) <= LOGIC_ZERO; INT_SUM(93) <= LOGIC_ZERO; INT_SUM(94) <= LOGIC_ZERO; INT_SUM(95) <= LOGIC_ZERO; INT_SUM(96) <= LOGIC_ZERO; INT_SUM(97) <= LOGIC_ZERO; INT_SUM(98) <= LOGIC_ZERO; INT_SUM(99) <= LOGIC_ZERO; INT_SUM(100) <= LOGIC_ZERO; INT_SUM(101) <= LOGIC_ZERO; INT_SUM(102) <= LOGIC_ZERO; INT_SUM(103) <= LOGIC_ZERO; INT_SUM(104) <= LOGIC_ZERO; INT_SUM(105) <= LOGIC_ZERO; INT_SUM(106) <= LOGIC_ZERO; INT_SUM(107) <= LOGIC_ZERO; INT_SUM(108) <= LOGIC_ZERO; INT_SUM(109) <= LOGIC_ZERO; INT_SUM(110) <= LOGIC_ZERO; INT_SUM(111) <= LOGIC_ZERO; INT_SUM(112) <= LOGIC_ZERO; INT_SUM(113) <= LOGIC_ZERO; INT_SUM(114) <= LOGIC_ZERO; INT_SUM(115) <= LOGIC_ZERO; INT_SUM(116) <= LOGIC_ZERO; INT_SUM(117) <= LOGIC_ZERO; INT_SUM(118) <= LOGIC_ZERO; INT_SUM(119) <= LOGIC_ZERO; INT_SUM(120) <= LOGIC_ZERO; INT_SUM(121) <= LOGIC_ZERO; INT_SUM(122) <= LOGIC_ZERO; INT_SUM(123) <= LOGIC_ZERO; INT_SUM(124) <= LOGIC_ZERO; INT_SUM(125) <= LOGIC_ZERO; INT_SUM(126) <= LOGIC_ZERO; INT_SUM(127) <= LOGIC_ZERO; INT_SUMR(67 to 127) <= INT_SUM(67 to 127); INT_CARRYR(67 to 127) <= INT_CARRY(67 to 127); INT_CARRYR(0) <= INT_CARRY(0); reg : if MULPIPE /= 0 generate process (PHI) begin if rising_edge(PHI ) then if (holdn = '1') then INT_SUMR(0 to 66) <= INT_SUM(0 to 66); INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66); end if; end if; end process; end generate; noreg : if MULPIPE = 0 generate INT_SUMR(0 to 66) <= INT_SUM(0 to 66); INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66); end generate; D:DBLCADDER_128_128 port map ( OPA(0 to 127) => INT_SUMR(0 to 127), OPB(0 to 127) => INT_CARRYR(0 to 127), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 127) => RESULT(0 to 127) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ -- -- Modgen multiplier created Fri Aug 16 16:35:11 2002 -- ------------------------------------------------------------ -- START: Multiplier Entitiy ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -- START: Top entity ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_33 is generic (mulpipe : integer := 0); port(clk : in std_ulogic; holdn: in std_ulogic; X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(32 downto 0); P: out std_logic_vector(65 downto 0)); end MUL_33_33; architecture A of MUL_33_33 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 33); signal Q: std_logic_vector(0 to 127); begin U1: MULTIPLIER_34_34 generic map (mulpipe) port map(A,B,CLK, holdn ,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(17); B(18) <= Y(18); B(19) <= Y(19); B(20) <= Y(20); B(21) <= Y(21); B(22) <= Y(22); B(23) <= Y(23); B(24) <= Y(24); B(25) <= Y(25); B(26) <= Y(26); B(27) <= Y(27); B(28) <= Y(28); B(29) <= Y(29); B(30) <= Y(30); B(31) <= Y(31); B(32) <= Y(32); B(33) <= Y(32); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); P(42) <= Q(42); P(43) <= Q(43); P(44) <= Q(44); P(45) <= Q(45); P(46) <= Q(46); P(47) <= Q(47); P(48) <= Q(48); P(49) <= Q(49); P(50) <= Q(50); P(51) <= Q(51); P(52) <= Q(52); P(53) <= Q(53); P(54) <= Q(54); P(55) <= Q(55); P(56) <= Q(56); P(57) <= Q(57); P(58) <= Q(58); P(59) <= Q(59); P(60) <= Q(60); P(61) <= Q(61); P(62) <= Q(62); P(63) <= Q(63); P(64) <= Q(64); P(65) <= Q(65); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity ADD32 is port(X: in std_logic_vector(31 downto 0); Y: in std_logic_vector(31 downto 0); CI: in std_logic; S: out std_logic_vector(31 downto 0); CO: out std_logic); end ADD32; architecture A of ADD32 is signal A,B,Q: std_logic_vector(0 to 31); signal CLK: std_logic; begin U1: DBLCADDER_32_32 port map(A,B,CI,CLK,Q,CO); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); B(0) <= Y(0); A(1) <= X(1); B(1) <= Y(1); A(2) <= X(2); B(2) <= Y(2); A(3) <= X(3); B(3) <= Y(3); A(4) <= X(4); B(4) <= Y(4); A(5) <= X(5); B(5) <= Y(5); A(6) <= X(6); B(6) <= Y(6); A(7) <= X(7); B(7) <= Y(7); A(8) <= X(8); B(8) <= Y(8); A(9) <= X(9); B(9) <= Y(9); A(10) <= X(10); B(10) <= Y(10); A(11) <= X(11); B(11) <= Y(11); A(12) <= X(12); B(12) <= Y(12); A(13) <= X(13); B(13) <= Y(13); A(14) <= X(14); B(14) <= Y(14); A(15) <= X(15); B(15) <= Y(15); A(16) <= X(16); B(16) <= Y(16); A(17) <= X(17); B(17) <= Y(17); A(18) <= X(18); B(18) <= Y(18); A(19) <= X(19); B(19) <= Y(19); A(20) <= X(20); B(20) <= Y(20); A(21) <= X(21); B(21) <= Y(21); A(22) <= X(22); B(22) <= Y(22); A(23) <= X(23); B(23) <= Y(23); A(24) <= X(24); B(24) <= Y(24); A(25) <= X(25); B(25) <= Y(25); A(26) <= X(26); B(26) <= Y(26); A(27) <= X(27); B(27) <= Y(27); A(28) <= X(28); B(28) <= Y(28); A(29) <= X(29); B(29) <= Y(29); A(30) <= X(30); B(30) <= Y(30); A(31) <= X(31); B(31) <= Y(31); S(0) <= Q(0); S(1) <= Q(1); S(2) <= Q(2); S(3) <= Q(3); S(4) <= Q(4); S(5) <= Q(5); S(6) <= Q(6); S(7) <= Q(7); S(8) <= Q(8); S(9) <= Q(9); S(10) <= Q(10); S(11) <= Q(11); S(12) <= Q(12); S(13) <= Q(13); S(14) <= Q(14); S(15) <= Q(15); S(16) <= Q(16); S(17) <= Q(17); S(18) <= Q(18); S(19) <= Q(19); S(20) <= Q(20); S(21) <= Q(21); S(22) <= Q(22); S(23) <= Q(23); S(24) <= Q(24); S(25) <= Q(25); S(26) <= Q(26); S(27) <= Q(27); S(28) <= Q(28); S(29) <= Q(29); S(30) <= Q(30); S(31) <= Q(31); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_17_17 is generic (mulpipe : integer := 0); port(clk : in std_ulogic; holdn: in std_ulogic; X: in std_logic_vector(16 downto 0); Y: in std_logic_vector(16 downto 0); P: out std_logic_vector(33 downto 0)); end MUL_17_17; architecture A of MUL_17_17 is signal A: std_logic_vector(0 to 17); signal B: std_logic_vector(0 to 17); signal Q: std_logic_vector(0 to 63); begin U1: MULTIPLIER_18_18 generic map (mulpipe) port map(A,B,CLK, holdn, Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(16); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(16); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); end A;
----------------------------------------------------------------------------- -- File: leaves.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: A set of multipliers generated from the Arithmetic Module -- Generator at Norwegian University of Science and Technology. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; package blocks is component FLIPFLOP port ( DIN, CLK: in std_logic; DOUT: out std_logic ); end component; component DBLCADDER_32_32 port(OPA: in std_logic_vector(0 to 31); OPB: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; SUM: out std_logic_vector(0 to 31); COUT: out std_logic); end component; component FULL_ADDER port ( DATA_A, DATA_B, DATA_C: in std_logic; SAVE, CARRY: out std_logic ); end component; component HALF_ADDER port ( DATA_A, DATA_B: in std_logic; SAVE, CARRY: out std_logic ); end component; component R_GATE port ( INA, INB, INC: in std_logic; PPBIT: out std_logic ); end component; component DECODER port ( INA, INB, INC: in std_logic; TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic ); end component; component PP_LOW port ( ONEPOS, ONENEG, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end component; component PP_MIDDLE port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB, INC, IND: in std_logic; PPBIT: out std_logic ); end component; component PP_HIGH port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end component; component BLOCK0 port ( A,B,PHI: in std_logic; POUT,GOUT: out std_logic ); end component; component INVBLOCK port ( GIN,PHI:in std_logic; GOUT:out std_logic ); end component; component BLOCK1 port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end component; component BLOCK1A port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end component; component BLOCK2 port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end component; component BLOCK2A port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end component; component PRESTAGE_32 port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 31); GOUT: out std_logic_vector(0 to 32) ); end component; component XXOR1 port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end component; component XXOR2 port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end component; component DBLCTREE_32 port ( PIN:in std_logic_vector(0 to 31); GIN:in std_logic_vector(0 to 32); PHI:in std_logic; GOUT:out std_logic_vector(0 to 32); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_32 port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 32); SUM: out std_logic_vector(0 to 31); COUT: out std_logic ); end component; component DBLC_0_32 port ( PIN: in std_logic_vector(0 to 31); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 30); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_1_32 port ( PIN: in std_logic_vector(0 to 30); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 28); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_2_32 port ( PIN: in std_logic_vector(0 to 28); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 24); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_3_32 port ( PIN: in std_logic_vector(0 to 24); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 16); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_4_32 port ( PIN: in std_logic_vector(0 to 16); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 32) ); end component; component PRESTAGE_64 port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 63); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLCTREE_64 port ( PIN:in std_logic_vector(0 to 63); GIN:in std_logic_vector(0 to 64); PHI:in std_logic; GOUT:out std_logic_vector(0 to 64); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_64 port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 64); SUM: out std_logic_vector(0 to 63); COUT: out std_logic ); end component; component DBLC_0_64 port ( PIN: in std_logic_vector(0 to 63); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 62); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_1_64 port ( PIN: in std_logic_vector(0 to 62); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 60); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_2_64 port ( PIN: in std_logic_vector(0 to 60); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 56); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_3_64 port ( PIN: in std_logic_vector(0 to 56); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 48); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_4_64 port ( PIN: in std_logic_vector(0 to 48); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 32); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_5_64 port ( PIN: in std_logic_vector(0 to 32); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_0_128 port ( PIN: in std_logic_vector(0 to 127); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 126); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_1_128 port ( PIN: in std_logic_vector(0 to 126); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 124); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_2_128 port ( PIN: in std_logic_vector(0 to 124); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 120); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_3_128 port ( PIN: in std_logic_vector(0 to 120); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 112); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_4_128 port ( PIN: in std_logic_vector(0 to 112); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 96); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_5_128 port ( PIN: in std_logic_vector(0 to 96); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 64); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_6_128 port ( PIN: in std_logic_vector(0 to 64); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 128) ); end component; component PRESTAGE_128 port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 127); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLCTREE_128 port ( PIN:in std_logic_vector(0 to 127); GIN:in std_logic_vector(0 to 128); PHI:in std_logic; GOUT:out std_logic_vector(0 to 128); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_128 port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 128); SUM: out std_logic_vector(0 to 127); COUT: out std_logic ); end component; component BOOTHCODER_18_18 port ( OPA: in std_logic_vector(0 to 17); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 188) ); end component; component WALLACE_18_18 port ( SUMMAND: in std_logic_vector(0 to 188); CARRY: out std_logic_vector(0 to 33); SUM: out std_logic_vector(0 to 34) ); end component; component DBLCADDER_64_64 port ( OPA:in std_logic_vector(0 to 63); OPB:in std_logic_vector(0 to 63); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 63); COUT:out std_logic ); end component; component BOOTHCODER_34_10 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 9); SUMMAND: out std_logic_vector(0 to 184) ); end component; component WALLACE_34_10 port ( SUMMAND: in std_logic_vector(0 to 184); CARRY: out std_logic_vector(0 to 41); SUM: out std_logic_vector(0 to 42) ); end component; component BOOTHCODER_34_18 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 332) ); end component; component WALLACE_34_18 port ( SUMMAND: in std_logic_vector(0 to 332); CARRY: out std_logic_vector(0 to 49); SUM: out std_logic_vector(0 to 50) ); end component; component BOOTHCODER_34_34 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 33); SUMMAND: out std_logic_vector(0 to 628) ); end component; component WALLACE_34_34 port ( SUMMAND: in std_logic_vector(0 to 628); CARRY: out std_logic_vector(0 to 65); SUM: out std_logic_vector(0 to 66) ); end component; component DBLCADDER_128_128 port ( OPA:in std_logic_vector(0 to 127); OPB:in std_logic_vector(0 to 127); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 127); COUT:out std_logic ); end component; component MULTIPLIER_18_18 generic (mulpipe : integer := 0); port(MULTIPLICAND: in std_logic_vector(0 to 17); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_ulogic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_10 port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 9); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_18 port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_34 generic (mulpipe : integer := 0); port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 33); PHI: in std_logic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 127)); end component; end; ------------------------------------------------------------ -- START: Entities used within the Modified Booth Recoding ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity FLIPFLOP is port ( DIN: in std_logic; CLK: in std_logic; DOUT: out std_logic ); end FLIPFLOP; architecture FLIPFLOP of FLIPFLOP is begin process(CLK) begin if(CLK='1')and(CLK'event)then DOUT <= DIN; end if; end process; end FLIPFLOP; library ieee; use ieee.std_logic_1164.all; entity PP_LOW is port ( ONEPOS, ONENEG, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end PP_LOW; architecture PP_LOW of PP_LOW is begin PPBIT <= (ONEPOS and INA) or (ONENEG and INB) or TWONEG; end PP_LOW; library ieee; use ieee.std_logic_1164.all; entity PP_MIDDLE is port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB, INC, IND: in std_logic; PPBIT: out std_logic ); end PP_MIDDLE; architecture PP_MIDDLE of PP_MIDDLE is begin PPBIT <= not((not(INA and TWOPOS)) and (not(INB and TWONEG)) and (not(INC and ONEPOS)) and (not(IND and ONENEG))); end PP_MIDDLE; library ieee; use ieee.std_logic_1164.all; entity PP_HIGH is port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end PP_HIGH; architecture PP_HIGH of PP_HIGH is begin PPBIT <= not ((INA and ONEPOS) or (INB and ONENEG) or (INA and TWOPOS) or (INB and TWONEG)); end PP_HIGH; library ieee; use ieee.std_logic_1164.all; entity R_GATE is port ( INA, INB, INC: in std_logic; PPBIT: out std_logic ); end R_GATE; architecture R_GATE of R_GATE is begin PPBIT <= (not(INA and INB)) and INC; end R_GATE; library ieee; use ieee.std_logic_1164.all; entity DECODER is port ( INA, INB, INC: in std_logic; TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic ); end DECODER; architecture DECODER of DECODER is begin TWOPOS <= not(not(INA and INB and (not INC))); TWONEG <= not(not((not INA) and (not INB) and INC)); ONEPOS <= ((not INA) and INB and (not INC)) or ((not INC) and (not INB) and INA); ONENEG <= (INA and (not INB) and INC) or (INC and INB and (not INA)); end DECODER; library ieee; use ieee.std_logic_1164.all; entity FULL_ADDER is port ( DATA_A, DATA_B, DATA_C: in std_logic; SAVE, CARRY: out std_logic ); end FULL_ADDER; architecture FULL_ADDER of FULL_ADDER is signal TMP: std_logic; begin TMP <= DATA_A xor DATA_B; SAVE <= TMP xor DATA_C; CARRY <= not((not (TMP and DATA_C)) and (not (DATA_A and DATA_B))); end FULL_ADDER; library ieee; use ieee.std_logic_1164.all; entity HALF_ADDER is port ( DATA_A, DATA_B: in std_logic; SAVE, CARRY: out std_logic ); end HALF_ADDER; architecture HALF_ADDER of HALF_ADDER is begin SAVE <= DATA_A xor DATA_B; CARRY <= DATA_A and DATA_B; end HALF_ADDER; library ieee; use ieee.std_logic_1164.all; entity INVBLOCK is port ( GIN,PHI:in std_logic; GOUT:out std_logic ); end INVBLOCK; architecture INVBLOCK_regular of INVBLOCK is begin GOUT <= not GIN; end INVBLOCK_regular; library ieee; use ieee.std_logic_1164.all; entity XXOR1 is port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end XXOR1; architecture XXOR_regular of XXOR1 is begin SUM <= (not (A xor B)) xor GIN; end XXOR_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK0 is port ( A,B,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK0; architecture BLOCK0_regular of BLOCK0 is begin POUT <= not(A or B); GOUT <= not(A and B); end BLOCK0_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK1 is port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK1; architecture BLOCK1_regular of BLOCK1 is begin POUT <= not(PIN1 or PIN2); GOUT <= not(GIN2 and (PIN2 or GIN1)); end BLOCK1_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK2 is port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK2; architecture BLOCK2_regular of BLOCK2 is begin POUT <= not(PIN1 and PIN2); GOUT <= not(GIN2 or (PIN2 and GIN1)); end BLOCK2_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK1A is port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end BLOCK1A; architecture BLOCK1A_regular of BLOCK1A is begin GOUT <= not(GIN2 and (PIN2 or GIN1)); end BLOCK1A_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK2A is port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end BLOCK2A; architecture BLOCK2A_regular of BLOCK2A is begin GOUT <= not(GIN2 or (PIN2 and GIN1)); end BLOCK2A_regular; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_64 is port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 63); GOUT: out std_logic_vector(0 to 64) ); end PRESTAGE_64; architecture PRESTAGE of PRESTAGE_64 is begin -- PRESTAGE U1:for I in 0 to 63 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: Level 0 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_64 is port ( PIN: in std_logic_vector(0 to 63); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 62); GOUT: out std_logic_vector(0 to 64) ); end DBLC_0_64; architecture DBLC_0 of DBLC_0_64 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 64 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_64 is port ( PIN: in std_logic_vector(0 to 62); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 60); GOUT: out std_logic_vector(0 to 64) ); end DBLC_1_64; architecture DBLC_1 of DBLC_1_64 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 64 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_64 is port ( PIN: in std_logic_vector(0 to 60); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 56); GOUT: out std_logic_vector(0 to 64) ); end DBLC_2_64; architecture DBLC_2 of DBLC_2_64 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 64 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_64 is port ( PIN: in std_logic_vector(0 to 56); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 48); GOUT: out std_logic_vector(0 to 64) ); end DBLC_3_64; architecture DBLC_3 of DBLC_3_64 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 64 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_64 is port ( PIN: in std_logic_vector(0 to 48); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 32); GOUT: out std_logic_vector(0 to 64) ); end DBLC_4_64; architecture DBLC_4 of DBLC_4_64 is begin -- Architecture DBLC_4 U1: for I in 0 to 15 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 64 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; -- The DBLC-tree: Level 5 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_5_64 is port ( PIN: in std_logic_vector(0 to 32); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 64) ); end DBLC_5_64; architecture DBLC_5 of DBLC_5_64 is begin -- Architecture DBLC_5 U1: for I in 0 to 31 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 32 to 63 generate U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 64 to 64 generate U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I)); end generate U3; end DBLC_5; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_64 is port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 64); SUM: out std_logic_vector(0 to 63); COUT: out std_logic ); end XORSTAGE_64; architecture XORSTAGE of XORSTAGE_64 is begin -- XORSTAGE U2:for I in 0 to 63 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U1: BLOCK1A port map(PBIT,CARRY(0),CARRY(64),PHI,COUT); end XORSTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_64 is port ( PIN:in std_logic_vector(0 to 63); GIN:in std_logic_vector(0 to 64); PHI:in std_logic; GOUT:out std_logic_vector(0 to 64); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_64; architecture DBLCTREE of DBLCTREE_64 is signal INTPROP_0: std_logic_vector(0 to 62); signal INTGEN_0: std_logic_vector(0 to 64); signal INTPROP_1: std_logic_vector(0 to 60); signal INTGEN_1: std_logic_vector(0 to 64); signal INTPROP_2: std_logic_vector(0 to 56); signal INTGEN_2: std_logic_vector(0 to 64); signal INTPROP_3: std_logic_vector(0 to 48); signal INTGEN_3: std_logic_vector(0 to 64); signal INTPROP_4: std_logic_vector(0 to 32); signal INTGEN_4: std_logic_vector(0 to 64); begin -- Architecture DBLCTREE U_0: DBLC_0_64 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_64 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_64 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_64 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_64 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4); U_5: DBLC_5_64 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_64_64 is port ( OPA:in std_logic_vector(0 to 63); OPB:in std_logic_vector(0 to 63); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 63); COUT:out std_logic ); end DBLCADDER_64_64; architecture DBLCADDER of DBLCADDER_64_64 is signal INTPROP: std_logic_vector(0 to 63); signal INTGEN: std_logic_vector(0 to 64); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 64); begin -- Architecture DBLCADDER U1: PRESTAGE_64 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_64 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_64 port map(OPA(0 to 63),OPB(0 to 63),PBIT(0),PHI,CARRY(0 to 64),SUM,COUT); end DBLCADDER; ------------------------------------------------------------ -- END: Architectures used with the DBLC adder ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity XXOR2 is port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end XXOR2; architecture XXOR_true of XXOR2 is begin SUM <= (A xor B) xor GIN; end XXOR_true; -- -- Modgen adder created Fri Aug 16 14:47:23 2002 -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_32 is port ( PIN: in std_logic_vector(0 to 31); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 30); GOUT: out std_logic_vector(0 to 32) ); end DBLC_0_32; architecture DBLC_0 of DBLC_0_32 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 32 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_32 is port ( PIN: in std_logic_vector(0 to 30); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 28); GOUT: out std_logic_vector(0 to 32) ); end DBLC_1_32; architecture DBLC_1 of DBLC_1_32 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 32 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_32 is port ( PIN: in std_logic_vector(0 to 28); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 24); GOUT: out std_logic_vector(0 to 32) ); end DBLC_2_32; architecture DBLC_2 of DBLC_2_32 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 32 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_32 is port ( PIN: in std_logic_vector(0 to 24); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 16); GOUT: out std_logic_vector(0 to 32) ); end DBLC_3_32; architecture DBLC_3 of DBLC_3_32 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 32 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_32 is port ( PIN: in std_logic_vector(0 to 16); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 32) ); end DBLC_4_32; architecture DBLC_4 of DBLC_4_32 is begin -- Architecture DBLC_4 GOUT(0 to 15) <= GIN(0 to 15); U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 32 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_32 is port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 32); SUM: out std_logic_vector(0 to 31); COUT: out std_logic ); end XORSTAGE_32; architecture XORSTAGE of XORSTAGE_32 is begin -- XORSTAGE U2:for I in 0 to 15 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U3:for I in 16 to 31 generate U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U3; U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(32),PHI,COUT); end XORSTAGE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_32 is port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 31); GOUT: out std_logic_vector(0 to 32) ); end PRESTAGE_32; architecture PRESTAGE of PRESTAGE_32 is begin -- PRESTAGE U1:for I in 0 to 31 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_32 is port ( PIN:in std_logic_vector(0 to 31); GIN:in std_logic_vector(0 to 32); PHI:in std_logic; GOUT:out std_logic_vector(0 to 32); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_32; architecture DBLCTREE of DBLCTREE_32 is signal INTPROP_0: std_logic_vector(0 to 30); signal INTGEN_0: std_logic_vector(0 to 32); signal INTPROP_1: std_logic_vector(0 to 28); signal INTGEN_1: std_logic_vector(0 to 32); signal INTPROP_2: std_logic_vector(0 to 24); signal INTGEN_2: std_logic_vector(0 to 32); signal INTPROP_3: std_logic_vector(0 to 16); signal INTGEN_3: std_logic_vector(0 to 32); begin -- Architecture DBLCTREE U_0: DBLC_0_32 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_32 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_32 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_32 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_32 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_32_32 is port ( OPA:in std_logic_vector(0 to 31); OPB:in std_logic_vector(0 to 31); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 31); COUT:out std_logic ); end DBLCADDER_32_32; architecture DBLCADDER of DBLCADDER_32_32 is signal INTPROP: std_logic_vector(0 to 31); signal INTGEN: std_logic_vector(0 to 32); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 32); begin -- Architecture DBLCADDER U1: PRESTAGE_32 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_32 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_32 port map(OPA(0 to 31),OPB(0 to 31),PBIT(0),PHI,CARRY(0 to 32),SUM,COUT); end DBLCADDER; ------------------------------------------------------------ -- END: Architectures used with the DBLC adder ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_128 is port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 127); GOUT: out std_logic_vector(0 to 128) ); end PRESTAGE_128; architecture PRESTAGE of PRESTAGE_128 is begin -- PRESTAGE U1:for I in 0 to 127 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: Level 0 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_128 is port ( PIN: in std_logic_vector(0 to 127); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 126); GOUT: out std_logic_vector(0 to 128) ); end DBLC_0_128; architecture DBLC_0 of DBLC_0_128 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 128 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_128 is port ( PIN: in std_logic_vector(0 to 126); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 124); GOUT: out std_logic_vector(0 to 128) ); end DBLC_1_128; architecture DBLC_1 of DBLC_1_128 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 128 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_128 is port ( PIN: in std_logic_vector(0 to 124); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 120); GOUT: out std_logic_vector(0 to 128) ); end DBLC_2_128; architecture DBLC_2 of DBLC_2_128 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 128 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_128 is port ( PIN: in std_logic_vector(0 to 120); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 112); GOUT: out std_logic_vector(0 to 128) ); end DBLC_3_128; architecture DBLC_3 of DBLC_3_128 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 128 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_128 is port ( PIN: in std_logic_vector(0 to 112); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 96); GOUT: out std_logic_vector(0 to 128) ); end DBLC_4_128; architecture DBLC_4 of DBLC_4_128 is begin -- Architecture DBLC_4 U1: for I in 0 to 15 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 128 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; -- The DBLC-tree: Level 5 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_5_128 is port ( PIN: in std_logic_vector(0 to 96); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 64); GOUT: out std_logic_vector(0 to 128) ); end DBLC_5_128; architecture DBLC_5 of DBLC_5_128 is begin -- Architecture DBLC_5 U1: for I in 0 to 31 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 32 to 63 generate U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 64 to 128 generate U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I)); end generate U3; end DBLC_5; -- The DBLC-tree: Level 6 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_6_128 is port ( PIN: in std_logic_vector(0 to 64); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 128) ); end DBLC_6_128; architecture DBLC_6 of DBLC_6_128 is begin -- Architecture DBLC_6 GOUT(0 to 63) <= GIN(0 to 63); U2: for I in 64 to 127 generate U21: BLOCK1A port map(PIN(I-64),GIN(I-64),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 128 to 128 generate U31: BLOCK1 port map(PIN(I-128),PIN(I-64),GIN(I-64),GIN(I),PHI,POUT(I-128),GOUT(I)); end generate U3; end DBLC_6; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_128 is port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 128); SUM: out std_logic_vector(0 to 127); COUT: out std_logic ); end XORSTAGE_128; architecture XORSTAGE of XORSTAGE_128 is begin -- XORSTAGE U2:for I in 0 to 63 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U3:for I in 64 to 127 generate U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U3; U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(128),PHI,COUT); end XORSTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_128 is port ( PIN:in std_logic_vector(0 to 127); GIN:in std_logic_vector(0 to 128); PHI:in std_logic; GOUT:out std_logic_vector(0 to 128); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_128; architecture DBLCTREE of DBLCTREE_128 is signal INTPROP_0: std_logic_vector(0 to 126); signal INTGEN_0: std_logic_vector(0 to 128); signal INTPROP_1: std_logic_vector(0 to 124); signal INTGEN_1: std_logic_vector(0 to 128); signal INTPROP_2: std_logic_vector(0 to 120); signal INTGEN_2: std_logic_vector(0 to 128); signal INTPROP_3: std_logic_vector(0 to 112); signal INTGEN_3: std_logic_vector(0 to 128); signal INTPROP_4: std_logic_vector(0 to 96); signal INTGEN_4: std_logic_vector(0 to 128); signal INTPROP_5: std_logic_vector(0 to 64); signal INTGEN_5: std_logic_vector(0 to 128); begin -- Architecture DBLCTREE U_0: DBLC_0_128 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_128 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_128 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_128 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_128 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4); U_5: DBLC_5_128 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>INTPROP_5,GOUT=>INTGEN_5); U_6: DBLC_6_128 port map(PIN=>INTPROP_5,GIN=>INTGEN_5,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_128_128 is port ( OPA:in std_logic_vector(0 to 127); OPB:in std_logic_vector(0 to 127); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 127); COUT:out std_logic ); end DBLCADDER_128_128; architecture DBLCADDER of DBLCADDER_128_128 is signal INTPROP: std_logic_vector(0 to 127); signal INTGEN: std_logic_vector(0 to 128); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 128); begin -- Architecture DBLCADDER U1: PRESTAGE_128 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_128 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_128 port map(OPA(0 to 127),OPB(0 to 127),PBIT(0),PHI,CARRY(0 to 128),SUM,COUT); end DBLCADDER; -- -- Modified Booth algorithm architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_18_18 is port ( OPA: in std_logic_vector(0 to 17); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 188) ); end BOOTHCODER_18_18; ------------------------------------------------------------ -- END: Entities used within the Modified Booth Recoding ------------------------------------------------------------ architecture BOOTHCODER of BOOTHCODER_18_18 is -- Components used in the architecture -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 17); signal INT_MULTIPLIER: std_logic_vector(0 to 35); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); PPH_0:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); SUMMAND(100) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_17:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_18:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_19:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_20:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_21:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_22:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_23:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_24:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_25:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_26:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_27:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_28:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_29:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_30:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_31:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_32:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(101) ); PPM_33:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(109) ); SUMMAND(110) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(118) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_34:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_35:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_36:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_37:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_38:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_39:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_40:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_41:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_42:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_43:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_44:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_45:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_46:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_47:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(102) ); PPM_48:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(111) ); PPM_49:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(119) ); PPM_50:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(126) ); SUMMAND(127) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(134) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_51:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_52:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_53:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_54:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_55:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_56:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_57:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_58:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_59:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_60:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_61:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_62:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(103) ); PPM_63:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(112) ); PPM_64:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(120) ); PPM_65:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(128) ); PPM_66:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(135) ); PPM_67:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(141) ); SUMMAND(142) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(148) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_68:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_69:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_70:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_71:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_72:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_73:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_74:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_75:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_76:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_77:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(104) ); PPM_78:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(113) ); PPM_79:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(121) ); PPM_80:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(129) ); PPM_81:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(136) ); PPM_82:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(143) ); PPM_83:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(149) ); PPM_84:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(154) ); SUMMAND(155) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_85:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_86:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_87:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_88:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_89:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_90:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_91:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_92:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(105) ); PPM_93:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(114) ); PPM_94:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(122) ); PPM_95:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(130) ); PPM_96:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(137) ); PPM_97:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(144) ); PPM_98:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(150) ); PPM_99:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(156) ); PPM_100:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(161) ); PPM_101:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(165) ); SUMMAND(166) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(170) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_102:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_103:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_104:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_105:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_106:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_107:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(106) ); PPM_108:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(115) ); PPM_109:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(123) ); PPM_110:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(131) ); PPM_111:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(138) ); PPM_112:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(145) ); PPM_113:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(151) ); PPM_114:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(157) ); PPM_115:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(162) ); PPM_116:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(167) ); PPM_117:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(171) ); PPM_118:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(174) ); SUMMAND(175) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(178) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_119:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_120:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_121:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_122:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(107) ); PPM_123:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(116) ); PPM_124:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(124) ); PPM_125:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(132) ); PPM_126:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(139) ); PPM_127:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(146) ); PPM_128:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(152) ); PPM_129:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(158) ); PPM_130:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(163) ); PPM_131:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(168) ); PPM_132:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(172) ); PPM_133:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(176) ); PPM_134:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(179) ); PPM_135:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(181) ); SUMMAND(182) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(184) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_136:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_137:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(108) ); PPM_138:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(117) ); PPM_139:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(125) ); PPM_140:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(133) ); PPM_141:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(140) ); PPM_142:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(147) ); PPM_143:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(153) ); PPM_144:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(159) ); PPM_145:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(164) ); PPM_146:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(169) ); PPM_147:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(173) ); PPM_148:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(177) ); PPM_149:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(180) ); PPM_150:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(183) ); PPM_151:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(185) ); PPM_152:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(186) ); SUMMAND(187) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(188) ); -- Begin partial product 9 end BOOTHCODER; ------------------------------------------------------------ -- END: Architectures used with the Modified Booth recoding ------------------------------------------------------------ -- -- Wallace tree architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_18_18 is port ( SUMMAND: in std_logic_vector(0 to 188); CARRY: out std_logic_vector(0 to 33); SUM: out std_logic_vector(0 to 34) ); end WALLACE_18_18; ------------------------------------------------------------ -- END: Entities within the Wallace-tree ------------------------------------------------------------ architecture WALLACE of WALLACE_18_18 is -- Components used in the netlist -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 114); signal INT_SUM: std_logic_vector(0 to 158); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin NO stage INT_SUM(76) <= SUMMAND(108); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(77), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_CARRY(49), DATA_C => INT_CARRY(50), SAVE => INT_SUM(78), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(51); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(77), DATA_B => INT_SUM(78), DATA_C => INT_SUM(79), SAVE => INT_SUM(80), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin NO stage INT_SUM(81) <= INT_CARRY(52); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(82) <= INT_CARRY(53); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_SUM(82), SAVE => INT_SUM(83), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin NO stage INT_SUM(84) <= INT_CARRY(54); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_64:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(83), DATA_B => INT_SUM(84), DATA_C => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End FA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_65:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(109), DATA_B => SUMMAND(110), DATA_C => SUMMAND(111), SAVE => INT_SUM(85), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(112), DATA_B => SUMMAND(113), DATA_C => SUMMAND(114), SAVE => INT_SUM(86), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117), SAVE => INT_SUM(87), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58), SAVE => INT_SUM(88), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(59), DATA_C => INT_CARRY(60), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_CARRY(61), SAVE => INT_SUM(91), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(91), DATA_B => INT_CARRY(62), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End HA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_72:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), DATA_C => SUMMAND(120), SAVE => INT_SUM(92), CARRY => INT_CARRY(70) ); ---- End FA stage ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(121), DATA_B => SUMMAND(122), DATA_C => SUMMAND(123), SAVE => INT_SUM(93), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(94) <= SUMMAND(124); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(95) <= SUMMAND(125); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_SUM(94), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin NO stage INT_SUM(97) <= INT_SUM(95); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(63), SAVE => INT_SUM(98), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(64), DATA_B => INT_CARRY(65), DATA_C => INT_CARRY(66), SAVE => INT_SUM(99), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(67), SAVE => INT_SUM(100), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin NO stage INT_SUM(101) <= INT_CARRY(68); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(69), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_79:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(102), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(103), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => INT_CARRY(70), SAVE => INT_SUM(104), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin NO stage INT_SUM(105) <= INT_CARRY(71); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_82:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_SUM(104), SAVE => INT_SUM(106), CARRY => INT_CARRY(79) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(105), DATA_B => INT_CARRY(72), SAVE => INT_SUM(107), CARRY => INT_CARRY(80) ); ---- End HA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(73), SAVE => INT_SUM(108), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin NO stage INT_SUM(109) <= INT_CARRY(74); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(75), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(134), DATA_B => SUMMAND(135), DATA_C => SUMMAND(136), SAVE => INT_SUM(110), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(137), DATA_B => SUMMAND(138), DATA_C => SUMMAND(139), SAVE => INT_SUM(111), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(112) <= SUMMAND(140); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_SUM(112), SAVE => INT_SUM(113), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), DATA_C => INT_CARRY(78), SAVE => INT_SUM(114), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_CARRY(79), SAVE => INT_SUM(115), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin NO stage INT_SUM(116) <= INT_CARRY(80); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(81), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_91:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143), SAVE => INT_SUM(117), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin FA stage FA_92:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146), SAVE => INT_SUM(118), CARRY => INT_CARRY(88) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= SUMMAND(147); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_SUM(119), SAVE => INT_SUM(120), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83), SAVE => INT_SUM(121), CARRY => INT_CARRY(90) ); ---- End HA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(84), SAVE => INT_SUM(122), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= INT_CARRY(85); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(86), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), DATA_C => SUMMAND(150), SAVE => INT_SUM(124), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(151), DATA_B => SUMMAND(152), DATA_C => SUMMAND(153), SAVE => INT_SUM(125), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(87), SAVE => INT_SUM(126), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin NO stage INT_SUM(127) <= INT_CARRY(88); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_99:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(89), SAVE => INT_SUM(128), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin NO stage INT_SUM(129) <= INT_CARRY(90); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(91), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_101:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(154), DATA_B => SUMMAND(155), DATA_C => SUMMAND(156), SAVE => INT_SUM(130), CARRY => INT_CARRY(96) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(157), DATA_B => SUMMAND(158), DATA_C => SUMMAND(159), SAVE => INT_SUM(131), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), DATA_C => INT_CARRY(92), SAVE => INT_SUM(132), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin NO stage INT_SUM(133) <= INT_CARRY(93); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(94), SAVE => INT_SUM(134), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(134), DATA_B => INT_CARRY(95), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End HA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_105:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(160), DATA_B => SUMMAND(161), DATA_C => SUMMAND(162), SAVE => INT_SUM(135), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(163), DATA_B => SUMMAND(164), SAVE => INT_SUM(136), CARRY => INT_CARRY(101) ); ---- End HA stage ---- Begin FA stage FA_106:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_CARRY(96), SAVE => INT_SUM(137), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin NO stage INT_SUM(138) <= INT_CARRY(97); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_CARRY(98), SAVE => INT_SUM(139), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(139), DATA_B => INT_CARRY(99), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_108:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(140), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), SAVE => INT_SUM(141), CARRY => INT_CARRY(105) ); ---- End HA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(100), SAVE => INT_SUM(142), CARRY => INT_CARRY(106) ); ---- End FA stage ---- Begin NO stage INT_SUM(143) <= INT_CARRY(101); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(102), SAVE => INT_SUM(144), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(144), DATA_B => INT_CARRY(103), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End HA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_111:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172), SAVE => INT_SUM(145), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(173), DATA_B => INT_CARRY(104), DATA_C => INT_CARRY(105), SAVE => INT_SUM(146), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin FA stage FA_113:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(106), SAVE => INT_SUM(147), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(147), DATA_B => INT_CARRY(107), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_114:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(148), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin NO stage INT_SUM(149) <= SUMMAND(177); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(108), SAVE => INT_SUM(150), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin NO stage INT_SUM(151) <= INT_CARRY(109); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(110), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_117:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(178), DATA_B => SUMMAND(179), DATA_C => SUMMAND(180), SAVE => INT_SUM(152), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin NO stage INT_SUM(153) <= INT_SUM(152); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(154) <= INT_CARRY(111); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_CARRY(112), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_119:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(181), DATA_B => SUMMAND(182), DATA_C => SUMMAND(183), SAVE => INT_SUM(155), CARRY => INT_CARRY(114) ); ---- End FA stage ---- Begin NO stage INT_SUM(156) <= INT_CARRY(113); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(155), DATA_B => INT_SUM(156), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End HA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin NO stage INT_SUM(157) <= SUMMAND(184); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(158) <= SUMMAND(185); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_120:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(114), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin HA stage HA_26:HALF_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End HA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin NO stage SUM(34) <= SUMMAND(188); -- At Level 5 ---- End NO stage -- End WT-branch 35 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_18_18 is generic (mulpipe : integer := 0); port ( MULTIPLICAND: in std_logic_vector(0 to 17); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_ulogic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_18_18; architecture MULTIPLIER of MULTIPLIER_18_18 is signal PPBIT:std_logic_vector(0 to 188); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_CARRYR: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal INT_SUMR: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_18_18 port map ( OPA(0 to 17) => MULTIPLICAND(0 to 17), OPB(0 to 17) => MULTIPLIER(0 to 17), SUMMAND(0 to 188) => PPBIT(0 to 188) ); W:WALLACE_18_18 port map ( SUMMAND(0 to 188) => PPBIT(0 to 188), CARRY(0 to 33) => INT_CARRY(1 to 34), SUM(0 to 34) => INT_SUM(0 to 34) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(35) <= LOGIC_ZERO; INT_CARRY(36) <= LOGIC_ZERO; INT_CARRY(37) <= LOGIC_ZERO; INT_CARRY(38) <= LOGIC_ZERO; INT_CARRY(39) <= LOGIC_ZERO; INT_CARRY(40) <= LOGIC_ZERO; INT_CARRY(41) <= LOGIC_ZERO; INT_CARRY(42) <= LOGIC_ZERO; INT_CARRY(43) <= LOGIC_ZERO; INT_CARRY(44) <= LOGIC_ZERO; INT_CARRY(45) <= LOGIC_ZERO; INT_CARRY(46) <= LOGIC_ZERO; INT_CARRY(47) <= LOGIC_ZERO; INT_CARRY(48) <= LOGIC_ZERO; INT_CARRY(49) <= LOGIC_ZERO; INT_CARRY(50) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(35) <= LOGIC_ZERO; INT_SUM(36) <= LOGIC_ZERO; INT_SUM(37) <= LOGIC_ZERO; INT_SUM(38) <= LOGIC_ZERO; INT_SUM(39) <= LOGIC_ZERO; INT_SUM(40) <= LOGIC_ZERO; INT_SUM(41) <= LOGIC_ZERO; INT_SUM(42) <= LOGIC_ZERO; INT_SUM(43) <= LOGIC_ZERO; INT_SUM(44) <= LOGIC_ZERO; INT_SUM(45) <= LOGIC_ZERO; INT_SUM(46) <= LOGIC_ZERO; INT_SUM(47) <= LOGIC_ZERO; INT_SUM(48) <= LOGIC_ZERO; INT_SUM(49) <= LOGIC_ZERO; INT_SUM(50) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; INT_SUMR(35 to 63) <= INT_SUM(35 to 63); INT_CARRYR(35 to 63) <= INT_CARRY(35 to 63); INT_CARRYR(0) <= INT_CARRY(0); reg : if MULPIPE /= 0 generate process (PHI) begin if rising_edge(PHI ) then if (holdn = '1') then INT_SUMR(0 to 34) <= INT_SUM(0 to 34); INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34); end if; end if; end process; end generate; noreg : if MULPIPE = 0 generate INT_SUMR(0 to 34) <= INT_SUM(0 to 34); INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34); end generate; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUMR(0 to 63), OPB(0 to 63) => INT_CARRYR(0 to 63), CIN => LOGIC_ZERO, PHI => PHI , SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_10 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 9); SUMMAND: out std_logic_vector(0 to 184) ); end BOOTHCODER_34_10; architecture BOOTHCODER of BOOTHCODER_34_10 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 19); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(40) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(45) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(50) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(55) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(60) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(65) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(70) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(75) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(85) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(95) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(100) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(105) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(110) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(115) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(120) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(125) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(130) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(135) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(140) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(145) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(150) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(155) ); SUMMAND(156) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(41) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(46) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(51) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(56) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(61) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(66) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(71) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(76) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(86) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(96) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(101) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(106) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(111) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(116) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(121) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(126) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(131) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(136) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(141) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(146) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(151) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(157) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(161) ); SUMMAND(162) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(166) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(42) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(47) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(52) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(57) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(62) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(67) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(72) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(77) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(87) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(97) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(102) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(107) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(112) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(117) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(122) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(127) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(132) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(137) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(142) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(147) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(152) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(158) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(163) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(167) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(170) ); SUMMAND(171) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(174) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(43) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(48) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(53) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(58) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(63) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(68) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(73) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(78) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(88) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(98) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(103) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(108) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(113) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(118) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(123) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(128) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(133) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(138) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(143) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(148) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(153) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(159) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(164) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(168) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(172) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(175) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(177) ); SUMMAND(178) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(180) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(44) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(49) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(54) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(59) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(64) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(69) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(74) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(79) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(89) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(99) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(104) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(109) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(114) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(119) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(124) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(129) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(134) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(139) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(144) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(149) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(154) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(165) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(169) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(173) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(176) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(179) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(181) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(182) ); SUMMAND(183) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(184) ); -- Begin partial product 5 end BOOTHCODER; ------------------------------------------------------------ -- END: Architectures used with the Modified Booth recoding ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the Wallace-tree ------------------------------------------------------------ -- -- Wallace tree architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_10 is port ( SUMMAND: in std_logic_vector(0 to 184); CARRY: out std_logic_vector(0 to 41); SUM: out std_logic_vector(0 to 42) ); end WALLACE_34_10; architecture WALLACE of WALLACE_34_10 is signal INT_CARRY: std_logic_vector(0 to 95); signal INT_SUM: std_logic_vector(0 to 133); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End HA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_CARRY(9), SAVE => INT_SUM(18), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin NO stage INT_SUM(19) <= INT_CARRY(10); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(18), DATA_B => INT_SUM(19), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_16:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(40), DATA_B => SUMMAND(41), DATA_C => SUMMAND(42), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End FA stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(43), DATA_B => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End HA stage ---- Begin FA stage FA_17:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(20), DATA_B => INT_SUM(21), DATA_C => INT_CARRY(12), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin NO stage INT_SUM(23) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(22), DATA_B => INT_SUM(23), DATA_C => INT_CARRY(14), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End FA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_19:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(24), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End HA stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(24), DATA_B => INT_SUM(25), DATA_C => INT_CARRY(15), SAVE => INT_SUM(26), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin NO stage INT_SUM(27) <= INT_CARRY(16); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_21:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(26), DATA_B => INT_SUM(27), DATA_C => INT_CARRY(17), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End FA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(50), DATA_B => SUMMAND(51), DATA_C => SUMMAND(52), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(53), DATA_B => SUMMAND(54), SAVE => INT_SUM(29), CARRY => INT_CARRY(22) ); ---- End HA stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(28), DATA_B => INT_SUM(29), DATA_C => INT_CARRY(18), SAVE => INT_SUM(30), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin NO stage INT_SUM(31) <= INT_CARRY(19); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(30), DATA_B => INT_SUM(31), DATA_C => INT_CARRY(20), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_25:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(55), DATA_B => SUMMAND(56), DATA_C => SUMMAND(57), SAVE => INT_SUM(32), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(58), DATA_B => SUMMAND(59), SAVE => INT_SUM(33), CARRY => INT_CARRY(25) ); ---- End HA stage ---- Begin FA stage FA_26:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(32), DATA_B => INT_SUM(33), DATA_C => INT_CARRY(21), SAVE => INT_SUM(34), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(35) <= INT_CARRY(22); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_CARRY(23), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_28:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(60), DATA_B => SUMMAND(61), DATA_C => SUMMAND(62), SAVE => INT_SUM(36), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), SAVE => INT_SUM(37), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(36), DATA_B => INT_SUM(37), DATA_C => INT_CARRY(24), SAVE => INT_SUM(38), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(39) <= INT_CARRY(25); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(38), DATA_B => INT_SUM(39), DATA_C => INT_CARRY(26), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(65), DATA_B => SUMMAND(66), DATA_C => SUMMAND(67), SAVE => INT_SUM(40), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(68), DATA_B => SUMMAND(69), SAVE => INT_SUM(41), CARRY => INT_CARRY(31) ); ---- End HA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(40), DATA_B => INT_SUM(41), DATA_C => INT_CARRY(27), SAVE => INT_SUM(42), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin NO stage INT_SUM(43) <= INT_CARRY(28); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(42), DATA_B => INT_SUM(43), DATA_C => INT_CARRY(29), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_34:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(70), DATA_B => SUMMAND(71), DATA_C => SUMMAND(72), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(73), DATA_B => SUMMAND(74), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(30), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(31); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(32), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End FA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End HA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_CARRY(33), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End FA stage ---- Begin NO stage INT_SUM(51) <= INT_CARRY(34); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(50), DATA_B => INT_SUM(51), DATA_C => INT_CARRY(35), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End FA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_40:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(52), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), SAVE => INT_SUM(53), CARRY => INT_CARRY(40) ); ---- End HA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(52), DATA_B => INT_SUM(53), DATA_C => INT_CARRY(36), SAVE => INT_SUM(54), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(55) <= INT_CARRY(37); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(54), DATA_B => INT_SUM(55), DATA_C => INT_CARRY(38), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End FA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(85), DATA_B => SUMMAND(86), DATA_C => SUMMAND(87), SAVE => INT_SUM(56), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(88), DATA_B => SUMMAND(89), SAVE => INT_SUM(57), CARRY => INT_CARRY(43) ); ---- End HA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(56), DATA_B => INT_SUM(57), DATA_C => INT_CARRY(39), SAVE => INT_SUM(58), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(59) <= INT_CARRY(40); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(58), DATA_B => INT_SUM(59), DATA_C => INT_CARRY(41), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_46:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(60), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), SAVE => INT_SUM(61), CARRY => INT_CARRY(46) ); ---- End HA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(60), DATA_B => INT_SUM(61), DATA_C => INT_CARRY(42), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin NO stage INT_SUM(63) <= INT_CARRY(43); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(44), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_49:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(95), DATA_B => SUMMAND(96), DATA_C => SUMMAND(97), SAVE => INT_SUM(64), CARRY => INT_CARRY(48) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(98), DATA_B => SUMMAND(99), SAVE => INT_SUM(65), CARRY => INT_CARRY(49) ); ---- End HA stage ---- Begin FA stage FA_50:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_CARRY(45), SAVE => INT_SUM(66), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin NO stage INT_SUM(67) <= INT_CARRY(46); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(66), DATA_B => INT_SUM(67), DATA_C => INT_CARRY(47), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(100), DATA_B => SUMMAND(101), DATA_C => SUMMAND(102), SAVE => INT_SUM(68), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(103), DATA_B => SUMMAND(104), SAVE => INT_SUM(69), CARRY => INT_CARRY(52) ); ---- End HA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(68), DATA_B => INT_SUM(69), DATA_C => INT_CARRY(48), SAVE => INT_SUM(70), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin NO stage INT_SUM(71) <= INT_CARRY(49); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(70), DATA_B => INT_SUM(71), DATA_C => INT_CARRY(50), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_55:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(72), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), SAVE => INT_SUM(73), CARRY => INT_CARRY(55) ); ---- End HA stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(72), DATA_B => INT_SUM(73), DATA_C => INT_CARRY(51), SAVE => INT_SUM(74), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin NO stage INT_SUM(75) <= INT_CARRY(52); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_57:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(74), DATA_B => INT_SUM(75), DATA_C => INT_CARRY(53), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112), SAVE => INT_SUM(76), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), SAVE => INT_SUM(77), CARRY => INT_CARRY(58) ); ---- End HA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(54), SAVE => INT_SUM(78), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(55); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(56), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End FA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_61:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117), SAVE => INT_SUM(80), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), SAVE => INT_SUM(81), CARRY => INT_CARRY(61) ); ---- End HA stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_CARRY(57), SAVE => INT_SUM(82), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin NO stage INT_SUM(83) <= INT_CARRY(58); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(59), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End FA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_64:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(84), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), SAVE => INT_SUM(85), CARRY => INT_CARRY(64) ); ---- End HA stage ---- Begin FA stage FA_65:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(60), SAVE => INT_SUM(86), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin NO stage INT_SUM(87) <= INT_CARRY(61); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(62), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End FA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_67:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(125), DATA_B => SUMMAND(126), DATA_C => SUMMAND(127), SAVE => INT_SUM(88), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(128), DATA_B => SUMMAND(129), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End HA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(88), DATA_B => INT_SUM(89), DATA_C => INT_CARRY(63), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(91) <= INT_CARRY(64); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(90), DATA_B => INT_SUM(91), DATA_C => INT_CARRY(65), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End FA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_70:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(130), DATA_B => SUMMAND(131), DATA_C => SUMMAND(132), SAVE => INT_SUM(92), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(133), DATA_B => SUMMAND(134), SAVE => INT_SUM(93), CARRY => INT_CARRY(70) ); ---- End HA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66), SAVE => INT_SUM(94), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(67); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), SAVE => INT_SUM(97), CARRY => INT_CARRY(73) ); ---- End HA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(69), SAVE => INT_SUM(98), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin NO stage INT_SUM(99) <= INT_CARRY(70); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(71), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_76:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(140), DATA_B => SUMMAND(141), DATA_C => SUMMAND(142), SAVE => INT_SUM(100), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), SAVE => INT_SUM(101), CARRY => INT_CARRY(76) ); ---- End HA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(72), SAVE => INT_SUM(102), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin NO stage INT_SUM(103) <= INT_CARRY(73); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(74), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End FA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_79:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(145), DATA_B => SUMMAND(146), DATA_C => SUMMAND(147), SAVE => INT_SUM(104), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), SAVE => INT_SUM(105), CARRY => INT_CARRY(79) ); ---- End HA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(104), DATA_B => INT_SUM(105), DATA_C => INT_CARRY(75), SAVE => INT_SUM(106), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin NO stage INT_SUM(107) <= INT_CARRY(76); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(77), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_82:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152), SAVE => INT_SUM(108), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), SAVE => INT_SUM(109), CARRY => INT_CARRY(82) ); ---- End HA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(78), SAVE => INT_SUM(110), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(111) <= INT_CARRY(79); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(80), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End FA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(155), DATA_B => SUMMAND(156), DATA_C => SUMMAND(157), SAVE => INT_SUM(112), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(158), DATA_B => SUMMAND(159), DATA_C => SUMMAND(160), SAVE => INT_SUM(113), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_CARRY(81), SAVE => INT_SUM(114), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin NO stage INT_SUM(115) <= INT_CARRY(82); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(114), DATA_B => INT_SUM(115), DATA_C => INT_CARRY(83), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_89:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(161), DATA_B => SUMMAND(162), DATA_C => SUMMAND(163), SAVE => INT_SUM(116), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(164), DATA_B => SUMMAND(165), SAVE => INT_SUM(117), CARRY => INT_CARRY(88) ); ---- End HA stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(84), SAVE => INT_SUM(118), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= INT_CARRY(85); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_91:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(86), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End FA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(166), DATA_B => SUMMAND(167), DATA_C => SUMMAND(168), SAVE => INT_SUM(120), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin NO stage INT_SUM(121) <= SUMMAND(169); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(87), SAVE => INT_SUM(122), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= INT_CARRY(88); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(89), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_95:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172), SAVE => INT_SUM(124), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin NO stage INT_SUM(125) <= SUMMAND(173); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(90), SAVE => INT_SUM(126), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(126), DATA_B => INT_CARRY(91), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End HA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_97:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(127), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin NO stage INT_SUM(128) <= INT_SUM(127); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(129) <= INT_CARRY(92); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(93), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_99:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(130), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin NO stage INT_SUM(131) <= INT_CARRY(94); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End HA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin NO stage INT_SUM(132) <= SUMMAND(180); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(133) <= SUMMAND(181); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(95), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin HA stage HA_35:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End HA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin NO stage SUM(42) <= SUMMAND(184); -- At Level 3 ---- End NO stage -- End WT-branch 43 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_10 is port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 9); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_34_10; ------------------------------------------------------------ -- End: Multiplier Entitiy architecture MULTIPLIER of MULTIPLIER_34_10 is signal PPBIT:std_logic_vector(0 to 184); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_10 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 9) => MULTIPLIER(0 to 9), SUMMAND(0 to 184) => PPBIT(0 to 184) ); W:WALLACE_34_10 port map ( SUMMAND(0 to 184) => PPBIT(0 to 184), CARRY(0 to 41) => INT_CARRY(1 to 42), SUM(0 to 42) => INT_SUM(0 to 42) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(43) <= LOGIC_ZERO; INT_CARRY(44) <= LOGIC_ZERO; INT_CARRY(45) <= LOGIC_ZERO; INT_CARRY(46) <= LOGIC_ZERO; INT_CARRY(47) <= LOGIC_ZERO; INT_CARRY(48) <= LOGIC_ZERO; INT_CARRY(49) <= LOGIC_ZERO; INT_CARRY(50) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(43) <= LOGIC_ZERO; INT_SUM(44) <= LOGIC_ZERO; INT_SUM(45) <= LOGIC_ZERO; INT_SUM(46) <= LOGIC_ZERO; INT_SUM(47) <= LOGIC_ZERO; INT_SUM(48) <= LOGIC_ZERO; INT_SUM(49) <= LOGIC_ZERO; INT_SUM(50) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUM(0 to 63), OPB(0 to 63) => INT_CARRY(0 to 63), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_9 is port(X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(8 downto 0); P: out std_logic_vector(41 downto 0)); end MUL_33_9; library ieee; use ieee.std_logic_1164.all; architecture A of MUL_33_9 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 9); signal Q: std_logic_vector(0 to 63); signal CLK: std_logic; begin U1: MULTIPLIER_34_10 port map(A,B,CLK,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(8); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); end A; ------------------------------------------------------------ -- START: Entities within the Wallace-tree ------------------------------------------------------------ -- -- Modified Booth algorithm architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_18 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 332) ); end BOOTHCODER_34_18; architecture BOOTHCODER of BOOTHCODER_34_18 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 35); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(108) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(117) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(126) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(135) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(144) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(153) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(162) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(171) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(180) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(189) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(198) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(207) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(216) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(225) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(234) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(243) ); SUMMAND(244) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(100) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(109) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(118) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(127) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(136) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(145) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(154) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(163) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(172) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(181) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(190) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(199) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(208) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(217) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(226) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(235) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(245) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(253) ); SUMMAND(254) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(262) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(101) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(110) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(119) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(128) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(137) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(146) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(155) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(164) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(173) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(182) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(191) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(200) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(209) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(218) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(227) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(236) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(246) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(255) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(263) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(270) ); SUMMAND(271) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(278) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(102) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(111) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(120) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(129) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(138) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(147) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(156) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(165) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(174) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(183) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(192) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(201) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(210) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(219) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(228) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(237) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(247) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(256) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(264) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(272) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(279) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(285) ); SUMMAND(286) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(292) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(103) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(112) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(121) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(130) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(139) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(148) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(157) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(166) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(175) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(184) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(193) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(202) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(211) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(220) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(229) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(238) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(248) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(257) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(265) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(273) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(280) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(287) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(293) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(298) ); SUMMAND(299) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(304) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_165:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_166:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_167:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_168:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_169:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_170:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_171:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_172:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(104) ); PPM_173:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(113) ); PPM_174:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(122) ); PPM_175:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(131) ); PPM_176:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(140) ); PPM_177:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(149) ); PPM_178:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(158) ); PPM_179:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(167) ); PPM_180:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(176) ); PPM_181:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(185) ); PPM_182:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(194) ); PPM_183:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(203) ); PPM_184:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(212) ); PPM_185:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(221) ); PPM_186:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(230) ); PPM_187:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(239) ); PPM_188:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(249) ); PPM_189:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(258) ); PPM_190:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(266) ); PPM_191:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(274) ); PPM_192:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(281) ); PPM_193:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(288) ); PPM_194:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(294) ); PPM_195:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(300) ); PPM_196:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(305) ); PPM_197:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(309) ); SUMMAND(310) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(314) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_198:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_199:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_200:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_201:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_202:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_203:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(105) ); PPM_204:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(114) ); PPM_205:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(123) ); PPM_206:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(132) ); PPM_207:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(141) ); PPM_208:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(150) ); PPM_209:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(159) ); PPM_210:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(168) ); PPM_211:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(177) ); PPM_212:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(186) ); PPM_213:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(195) ); PPM_214:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(204) ); PPM_215:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(213) ); PPM_216:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(222) ); PPM_217:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(231) ); PPM_218:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(240) ); PPM_219:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(250) ); PPM_220:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(259) ); PPM_221:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(267) ); PPM_222:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(275) ); PPM_223:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(282) ); PPM_224:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(289) ); PPM_225:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(295) ); PPM_226:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(301) ); PPM_227:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(306) ); PPM_228:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(311) ); PPM_229:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(315) ); PPM_230:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(318) ); SUMMAND(319) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(322) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_231:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_232:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_233:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_234:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(106) ); PPM_235:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(115) ); PPM_236:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(124) ); PPM_237:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(133) ); PPM_238:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(142) ); PPM_239:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(151) ); PPM_240:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(160) ); PPM_241:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(169) ); PPM_242:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(178) ); PPM_243:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(187) ); PPM_244:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(196) ); PPM_245:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(205) ); PPM_246:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(214) ); PPM_247:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(223) ); PPM_248:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(232) ); PPM_249:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(241) ); PPM_250:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(251) ); PPM_251:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(260) ); PPM_252:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(268) ); PPM_253:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(276) ); PPM_254:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(283) ); PPM_255:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(290) ); PPM_256:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(296) ); PPM_257:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(302) ); PPM_258:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(307) ); PPM_259:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(312) ); PPM_260:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(316) ); PPM_261:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(320) ); PPM_262:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(323) ); PPM_263:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(325) ); SUMMAND(326) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(328) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_264:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_265:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(107) ); PPM_266:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(116) ); PPM_267:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(125) ); PPM_268:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(134) ); PPM_269:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(143) ); PPM_270:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(152) ); PPM_271:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(161) ); PPM_272:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(170) ); PPM_273:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(179) ); PPM_274:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(188) ); PPM_275:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(197) ); PPM_276:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(206) ); PPM_277:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(215) ); PPM_278:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(224) ); PPM_279:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(233) ); PPM_280:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(242) ); PPM_281:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(252) ); PPM_282:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(261) ); PPM_283:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(269) ); PPM_284:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(277) ); PPM_285:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(284) ); PPM_286:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(291) ); PPM_287:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(297) ); PPM_288:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(303) ); PPM_289:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(308) ); PPM_290:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(313) ); PPM_291:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(317) ); PPM_292:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(321) ); PPM_293:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(324) ); PPM_294:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(327) ); PPM_295:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(329) ); PPM_296:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(330) ); SUMMAND(331) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(332) ); -- Begin partial product 9 end BOOTHCODER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_18 is port ( SUMMAND: in std_logic_vector(0 to 332); CARRY: out std_logic_vector(0 to 49); SUM: out std_logic_vector(0 to 50) ); end WALLACE_34_18; architecture WALLACE of WALLACE_34_18 is -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 226); signal INT_SUM: std_logic_vector(0 to 286); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(76), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(49), DATA_B => INT_CARRY(50), DATA_C => INT_CARRY(51), SAVE => INT_SUM(77), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(52), SAVE => INT_SUM(78), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(53); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(54), SAVE => INT_SUM(80), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(80), DATA_B => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End HA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_64:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), DATA_C => SUMMAND(110), SAVE => INT_SUM(81), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin FA stage FA_65:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(111), DATA_B => SUMMAND(112), DATA_C => SUMMAND(113), SAVE => INT_SUM(82), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(114), DATA_B => SUMMAND(115), DATA_C => SUMMAND(116), SAVE => INT_SUM(83), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(81), DATA_B => INT_SUM(82), DATA_C => INT_SUM(83), SAVE => INT_SUM(84), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58), SAVE => INT_SUM(85), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(59), SAVE => INT_SUM(86), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(87) <= INT_CARRY(60); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(61), SAVE => INT_SUM(88), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(62), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End HA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_71:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(117), DATA_B => SUMMAND(118), DATA_C => SUMMAND(119), SAVE => INT_SUM(89), CARRY => INT_CARRY(70) ); ---- End FA stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(90), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125), SAVE => INT_SUM(91), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91), SAVE => INT_SUM(92), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(63), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65), SAVE => INT_SUM(93), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66), SAVE => INT_SUM(94), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(67); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68), SAVE => INT_SUM(96), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(96), DATA_B => INT_CARRY(69), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End HA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_78:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(97), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin FA stage FA_79:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(98), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134), SAVE => INT_SUM(99), CARRY => INT_CARRY(79) ); ---- End FA stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(97), DATA_B => INT_SUM(98), DATA_C => INT_SUM(99), SAVE => INT_SUM(100), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin FA stage FA_82:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(70), DATA_B => INT_CARRY(71), DATA_C => INT_CARRY(72), SAVE => INT_SUM(101), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(73), SAVE => INT_SUM(102), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin NO stage INT_SUM(103) <= INT_CARRY(74); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(75), SAVE => INT_SUM(104), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(104), DATA_B => INT_CARRY(76), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End HA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(105), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140), SAVE => INT_SUM(106), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143), SAVE => INT_SUM(107), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_SUM(107), SAVE => INT_SUM(108), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(77), DATA_B => INT_CARRY(78), DATA_C => INT_CARRY(79), SAVE => INT_SUM(109), CARRY => INT_CARRY(88) ); ---- End FA stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(80), SAVE => INT_SUM(110), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(111) <= INT_CARRY(81); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_91:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(82), SAVE => INT_SUM(112), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(112), DATA_B => INT_CARRY(83), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End HA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146), SAVE => INT_SUM(113), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(147), DATA_B => SUMMAND(148), DATA_C => SUMMAND(149), SAVE => INT_SUM(114), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152), SAVE => INT_SUM(115), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_SUM(115), SAVE => INT_SUM(116), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86), SAVE => INT_SUM(117), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(87), SAVE => INT_SUM(118), CARRY => INT_CARRY(96) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= INT_CARRY(88); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(89), SAVE => INT_SUM(120), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(120), DATA_B => INT_CARRY(90), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End HA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_99:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), DATA_C => SUMMAND(155), SAVE => INT_SUM(121), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158), SAVE => INT_SUM(122), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin FA stage FA_101:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161), SAVE => INT_SUM(123), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(121), DATA_B => INT_SUM(122), DATA_C => INT_SUM(123), SAVE => INT_SUM(124), CARRY => INT_CARRY(101) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(91), DATA_B => INT_CARRY(92), DATA_C => INT_CARRY(93), SAVE => INT_SUM(125), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(94), SAVE => INT_SUM(126), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin NO stage INT_SUM(127) <= INT_CARRY(95); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_105:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(96), SAVE => INT_SUM(128), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(128), DATA_B => INT_CARRY(97), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End HA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_106:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164), SAVE => INT_SUM(129), CARRY => INT_CARRY(105) ); ---- End FA stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(130), CARRY => INT_CARRY(106) ); ---- End FA stage ---- Begin FA stage FA_108:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170), SAVE => INT_SUM(131), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_SUM(131), SAVE => INT_SUM(132), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(98), DATA_B => INT_CARRY(99), DATA_C => INT_CARRY(100), SAVE => INT_SUM(133), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin FA stage FA_111:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(101), SAVE => INT_SUM(134), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin NO stage INT_SUM(135) <= INT_CARRY(102); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(134), DATA_B => INT_SUM(135), DATA_C => INT_CARRY(103), SAVE => INT_SUM(136), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(136), DATA_B => INT_CARRY(104), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End HA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_113:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173), SAVE => INT_SUM(137), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin FA stage FA_114:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(138), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(139), CARRY => INT_CARRY(114) ); ---- End FA stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_SUM(139), SAVE => INT_SUM(140), CARRY => INT_CARRY(115) ); ---- End FA stage ---- Begin FA stage FA_117:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(105), DATA_B => INT_CARRY(106), DATA_C => INT_CARRY(107), SAVE => INT_SUM(141), CARRY => INT_CARRY(116) ); ---- End FA stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(108), SAVE => INT_SUM(142), CARRY => INT_CARRY(117) ); ---- End FA stage ---- Begin NO stage INT_SUM(143) <= INT_CARRY(109); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_119:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(110), SAVE => INT_SUM(144), CARRY => INT_CARRY(118) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(144), DATA_B => INT_CARRY(111), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_120:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), DATA_C => SUMMAND(182), SAVE => INT_SUM(145), CARRY => INT_CARRY(119) ); ---- End FA stage ---- Begin FA stage FA_121:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(183), DATA_B => SUMMAND(184), DATA_C => SUMMAND(185), SAVE => INT_SUM(146), CARRY => INT_CARRY(120) ); ---- End FA stage ---- Begin FA stage FA_122:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), DATA_C => SUMMAND(188), SAVE => INT_SUM(147), CARRY => INT_CARRY(121) ); ---- End FA stage ---- Begin FA stage FA_123:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_SUM(147), SAVE => INT_SUM(148), CARRY => INT_CARRY(122) ); ---- End FA stage ---- Begin FA stage FA_124:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(112), DATA_B => INT_CARRY(113), DATA_C => INT_CARRY(114), SAVE => INT_SUM(149), CARRY => INT_CARRY(123) ); ---- End FA stage ---- Begin FA stage FA_125:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(115), SAVE => INT_SUM(150), CARRY => INT_CARRY(124) ); ---- End FA stage ---- Begin NO stage INT_SUM(151) <= INT_CARRY(116); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_126:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(117), SAVE => INT_SUM(152), CARRY => INT_CARRY(125) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(152), DATA_B => INT_CARRY(118), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End HA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_127:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(189), DATA_B => SUMMAND(190), DATA_C => SUMMAND(191), SAVE => INT_SUM(153), CARRY => INT_CARRY(126) ); ---- End FA stage ---- Begin FA stage FA_128:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(192), DATA_B => SUMMAND(193), DATA_C => SUMMAND(194), SAVE => INT_SUM(154), CARRY => INT_CARRY(127) ); ---- End FA stage ---- Begin FA stage FA_129:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197), SAVE => INT_SUM(155), CARRY => INT_CARRY(128) ); ---- End FA stage ---- Begin FA stage FA_130:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_SUM(155), SAVE => INT_SUM(156), CARRY => INT_CARRY(129) ); ---- End FA stage ---- Begin FA stage FA_131:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(119), DATA_B => INT_CARRY(120), DATA_C => INT_CARRY(121), SAVE => INT_SUM(157), CARRY => INT_CARRY(130) ); ---- End FA stage ---- Begin FA stage FA_132:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(156), DATA_B => INT_SUM(157), DATA_C => INT_CARRY(122), SAVE => INT_SUM(158), CARRY => INT_CARRY(131) ); ---- End FA stage ---- Begin NO stage INT_SUM(159) <= INT_CARRY(123); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_133:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(158), DATA_B => INT_SUM(159), DATA_C => INT_CARRY(124), SAVE => INT_SUM(160), CARRY => INT_CARRY(132) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(160), DATA_B => INT_CARRY(125), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_134:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200), SAVE => INT_SUM(161), CARRY => INT_CARRY(133) ); ---- End FA stage ---- Begin FA stage FA_135:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203), SAVE => INT_SUM(162), CARRY => INT_CARRY(134) ); ---- End FA stage ---- Begin FA stage FA_136:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206), SAVE => INT_SUM(163), CARRY => INT_CARRY(135) ); ---- End FA stage ---- Begin FA stage FA_137:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(161), DATA_B => INT_SUM(162), DATA_C => INT_SUM(163), SAVE => INT_SUM(164), CARRY => INT_CARRY(136) ); ---- End FA stage ---- Begin FA stage FA_138:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(126), DATA_B => INT_CARRY(127), DATA_C => INT_CARRY(128), SAVE => INT_SUM(165), CARRY => INT_CARRY(137) ); ---- End FA stage ---- Begin FA stage FA_139:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(164), DATA_B => INT_SUM(165), DATA_C => INT_CARRY(129), SAVE => INT_SUM(166), CARRY => INT_CARRY(138) ); ---- End FA stage ---- Begin NO stage INT_SUM(167) <= INT_CARRY(130); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_140:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(131), SAVE => INT_SUM(168), CARRY => INT_CARRY(139) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(168), DATA_B => INT_CARRY(132), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End HA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_141:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209), SAVE => INT_SUM(169), CARRY => INT_CARRY(140) ); ---- End FA stage ---- Begin FA stage FA_142:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212), SAVE => INT_SUM(170), CARRY => INT_CARRY(141) ); ---- End FA stage ---- Begin FA stage FA_143:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215), SAVE => INT_SUM(171), CARRY => INT_CARRY(142) ); ---- End FA stage ---- Begin FA stage FA_144:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(169), DATA_B => INT_SUM(170), DATA_C => INT_SUM(171), SAVE => INT_SUM(172), CARRY => INT_CARRY(143) ); ---- End FA stage ---- Begin FA stage FA_145:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135), SAVE => INT_SUM(173), CARRY => INT_CARRY(144) ); ---- End FA stage ---- Begin FA stage FA_146:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(172), DATA_B => INT_SUM(173), DATA_C => INT_CARRY(136), SAVE => INT_SUM(174), CARRY => INT_CARRY(145) ); ---- End FA stage ---- Begin NO stage INT_SUM(175) <= INT_CARRY(137); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_147:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(174), DATA_B => INT_SUM(175), DATA_C => INT_CARRY(138), SAVE => INT_SUM(176), CARRY => INT_CARRY(146) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(176), DATA_B => INT_CARRY(139), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End HA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_148:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218), SAVE => INT_SUM(177), CARRY => INT_CARRY(147) ); ---- End FA stage ---- Begin FA stage FA_149:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221), SAVE => INT_SUM(178), CARRY => INT_CARRY(148) ); ---- End FA stage ---- Begin FA stage FA_150:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), DATA_C => SUMMAND(224), SAVE => INT_SUM(179), CARRY => INT_CARRY(149) ); ---- End FA stage ---- Begin FA stage FA_151:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(177), DATA_B => INT_SUM(178), DATA_C => INT_SUM(179), SAVE => INT_SUM(180), CARRY => INT_CARRY(150) ); ---- End FA stage ---- Begin FA stage FA_152:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(140), DATA_B => INT_CARRY(141), DATA_C => INT_CARRY(142), SAVE => INT_SUM(181), CARRY => INT_CARRY(151) ); ---- End FA stage ---- Begin FA stage FA_153:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), DATA_C => INT_CARRY(143), SAVE => INT_SUM(182), CARRY => INT_CARRY(152) ); ---- End FA stage ---- Begin NO stage INT_SUM(183) <= INT_CARRY(144); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_154:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_CARRY(145), SAVE => INT_SUM(184), CARRY => INT_CARRY(153) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(184), DATA_B => INT_CARRY(146), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End HA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_155:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(225), DATA_B => SUMMAND(226), DATA_C => SUMMAND(227), SAVE => INT_SUM(185), CARRY => INT_CARRY(154) ); ---- End FA stage ---- Begin FA stage FA_156:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(228), DATA_B => SUMMAND(229), DATA_C => SUMMAND(230), SAVE => INT_SUM(186), CARRY => INT_CARRY(155) ); ---- End FA stage ---- Begin FA stage FA_157:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(231), DATA_B => SUMMAND(232), DATA_C => SUMMAND(233), SAVE => INT_SUM(187), CARRY => INT_CARRY(156) ); ---- End FA stage ---- Begin FA stage FA_158:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_SUM(187), SAVE => INT_SUM(188), CARRY => INT_CARRY(157) ); ---- End FA stage ---- Begin FA stage FA_159:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(147), DATA_B => INT_CARRY(148), DATA_C => INT_CARRY(149), SAVE => INT_SUM(189), CARRY => INT_CARRY(158) ); ---- End FA stage ---- Begin FA stage FA_160:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(188), DATA_B => INT_SUM(189), DATA_C => INT_CARRY(150), SAVE => INT_SUM(190), CARRY => INT_CARRY(159) ); ---- End FA stage ---- Begin NO stage INT_SUM(191) <= INT_CARRY(151); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_161:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(190), DATA_B => INT_SUM(191), DATA_C => INT_CARRY(152), SAVE => INT_SUM(192), CARRY => INT_CARRY(160) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(192), DATA_B => INT_CARRY(153), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End HA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_162:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(234), DATA_B => SUMMAND(235), DATA_C => SUMMAND(236), SAVE => INT_SUM(193), CARRY => INT_CARRY(161) ); ---- End FA stage ---- Begin FA stage FA_163:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(237), DATA_B => SUMMAND(238), DATA_C => SUMMAND(239), SAVE => INT_SUM(194), CARRY => INT_CARRY(162) ); ---- End FA stage ---- Begin FA stage FA_164:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242), SAVE => INT_SUM(195), CARRY => INT_CARRY(163) ); ---- End FA stage ---- Begin FA stage FA_165:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(193), DATA_B => INT_SUM(194), DATA_C => INT_SUM(195), SAVE => INT_SUM(196), CARRY => INT_CARRY(164) ); ---- End FA stage ---- Begin FA stage FA_166:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(154), DATA_B => INT_CARRY(155), DATA_C => INT_CARRY(156), SAVE => INT_SUM(197), CARRY => INT_CARRY(165) ); ---- End FA stage ---- Begin FA stage FA_167:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(196), DATA_B => INT_SUM(197), DATA_C => INT_CARRY(157), SAVE => INT_SUM(198), CARRY => INT_CARRY(166) ); ---- End FA stage ---- Begin NO stage INT_SUM(199) <= INT_CARRY(158); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_168:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(198), DATA_B => INT_SUM(199), DATA_C => INT_CARRY(159), SAVE => INT_SUM(200), CARRY => INT_CARRY(167) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(200), DATA_B => INT_CARRY(160), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End HA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_169:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245), SAVE => INT_SUM(201), CARRY => INT_CARRY(168) ); ---- End FA stage ---- Begin FA stage FA_170:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248), SAVE => INT_SUM(202), CARRY => INT_CARRY(169) ); ---- End FA stage ---- Begin FA stage FA_171:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251), SAVE => INT_SUM(203), CARRY => INT_CARRY(170) ); ---- End FA stage ---- Begin NO stage INT_SUM(204) <= SUMMAND(252); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_172:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(201), DATA_B => INT_SUM(202), DATA_C => INT_SUM(203), SAVE => INT_SUM(205), CARRY => INT_CARRY(171) ); ---- End FA stage ---- Begin FA stage FA_173:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(204), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162), SAVE => INT_SUM(206), CARRY => INT_CARRY(172) ); ---- End FA stage ---- Begin NO stage INT_SUM(207) <= INT_CARRY(163); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_174:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207), SAVE => INT_SUM(208), CARRY => INT_CARRY(173) ); ---- End FA stage ---- Begin NO stage INT_SUM(209) <= INT_CARRY(164); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(210) <= INT_CARRY(165); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_175:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_SUM(210), SAVE => INT_SUM(211), CARRY => INT_CARRY(174) ); ---- End FA stage ---- Begin NO stage INT_SUM(212) <= INT_CARRY(166); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_176:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(211), DATA_B => INT_SUM(212), DATA_C => INT_CARRY(167), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_177:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(253), DATA_B => SUMMAND(254), DATA_C => SUMMAND(255), SAVE => INT_SUM(213), CARRY => INT_CARRY(175) ); ---- End FA stage ---- Begin FA stage FA_178:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(256), DATA_B => SUMMAND(257), DATA_C => SUMMAND(258), SAVE => INT_SUM(214), CARRY => INT_CARRY(176) ); ---- End FA stage ---- Begin FA stage FA_179:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(259), DATA_B => SUMMAND(260), DATA_C => SUMMAND(261), SAVE => INT_SUM(215), CARRY => INT_CARRY(177) ); ---- End FA stage ---- Begin FA stage FA_180:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(168), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170), SAVE => INT_SUM(216), CARRY => INT_CARRY(178) ); ---- End FA stage ---- Begin FA stage FA_181:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(213), DATA_B => INT_SUM(214), DATA_C => INT_SUM(215), SAVE => INT_SUM(217), CARRY => INT_CARRY(179) ); ---- End FA stage ---- Begin FA stage FA_182:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(216), DATA_B => INT_CARRY(171), DATA_C => INT_CARRY(172), SAVE => INT_SUM(218), CARRY => INT_CARRY(180) ); ---- End FA stage ---- Begin FA stage FA_183:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_CARRY(173), SAVE => INT_SUM(219), CARRY => INT_CARRY(181) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(219), DATA_B => INT_CARRY(174), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End HA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_184:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(262), DATA_B => SUMMAND(263), DATA_C => SUMMAND(264), SAVE => INT_SUM(220), CARRY => INT_CARRY(182) ); ---- End FA stage ---- Begin FA stage FA_185:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(265), DATA_B => SUMMAND(266), DATA_C => SUMMAND(267), SAVE => INT_SUM(221), CARRY => INT_CARRY(183) ); ---- End FA stage ---- Begin NO stage INT_SUM(222) <= SUMMAND(268); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(223) <= SUMMAND(269); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_186:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_SUM(222), SAVE => INT_SUM(224), CARRY => INT_CARRY(184) ); ---- End FA stage ---- Begin NO stage INT_SUM(225) <= INT_SUM(223); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_187:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(224), DATA_B => INT_SUM(225), DATA_C => INT_CARRY(175), SAVE => INT_SUM(226), CARRY => INT_CARRY(185) ); ---- End FA stage ---- Begin FA stage FA_188:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(176), DATA_B => INT_CARRY(177), DATA_C => INT_CARRY(178), SAVE => INT_SUM(227), CARRY => INT_CARRY(186) ); ---- End FA stage ---- Begin FA stage FA_189:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_CARRY(179), SAVE => INT_SUM(228), CARRY => INT_CARRY(187) ); ---- End FA stage ---- Begin NO stage INT_SUM(229) <= INT_CARRY(180); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_190:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(228), DATA_B => INT_SUM(229), DATA_C => INT_CARRY(181), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_191:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(270), DATA_B => SUMMAND(271), DATA_C => SUMMAND(272), SAVE => INT_SUM(230), CARRY => INT_CARRY(188) ); ---- End FA stage ---- Begin FA stage FA_192:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(273), DATA_B => SUMMAND(274), DATA_C => SUMMAND(275), SAVE => INT_SUM(231), CARRY => INT_CARRY(189) ); ---- End FA stage ---- Begin FA stage FA_193:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(276), DATA_B => SUMMAND(277), DATA_C => INT_CARRY(182), SAVE => INT_SUM(232), CARRY => INT_CARRY(190) ); ---- End FA stage ---- Begin NO stage INT_SUM(233) <= INT_CARRY(183); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_194:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(230), DATA_B => INT_SUM(231), DATA_C => INT_SUM(232), SAVE => INT_SUM(234), CARRY => INT_CARRY(191) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(233), DATA_B => INT_CARRY(184), SAVE => INT_SUM(235), CARRY => INT_CARRY(192) ); ---- End HA stage ---- Begin FA stage FA_195:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(234), DATA_B => INT_SUM(235), DATA_C => INT_CARRY(185), SAVE => INT_SUM(236), CARRY => INT_CARRY(193) ); ---- End FA stage ---- Begin NO stage INT_SUM(237) <= INT_CARRY(186); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_196:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_CARRY(187), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End FA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_197:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280), SAVE => INT_SUM(238), CARRY => INT_CARRY(194) ); ---- End FA stage ---- Begin FA stage FA_198:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283), SAVE => INT_SUM(239), CARRY => INT_CARRY(195) ); ---- End FA stage ---- Begin NO stage INT_SUM(240) <= SUMMAND(284); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_199:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(238), DATA_B => INT_SUM(239), DATA_C => INT_SUM(240), SAVE => INT_SUM(241), CARRY => INT_CARRY(196) ); ---- End FA stage ---- Begin FA stage FA_200:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190), SAVE => INT_SUM(242), CARRY => INT_CARRY(197) ); ---- End FA stage ---- Begin FA stage FA_201:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(241), DATA_B => INT_SUM(242), DATA_C => INT_CARRY(191), SAVE => INT_SUM(243), CARRY => INT_CARRY(198) ); ---- End FA stage ---- Begin NO stage INT_SUM(244) <= INT_CARRY(192); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_202:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(243), DATA_B => INT_SUM(244), DATA_C => INT_CARRY(193), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_203:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(285), DATA_B => SUMMAND(286), DATA_C => SUMMAND(287), SAVE => INT_SUM(245), CARRY => INT_CARRY(199) ); ---- End FA stage ---- Begin FA stage FA_204:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290), SAVE => INT_SUM(246), CARRY => INT_CARRY(200) ); ---- End FA stage ---- Begin NO stage INT_SUM(247) <= SUMMAND(291); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_205:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(245), DATA_B => INT_SUM(246), DATA_C => INT_SUM(247), SAVE => INT_SUM(248), CARRY => INT_CARRY(201) ); ---- End FA stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(194), DATA_B => INT_CARRY(195), SAVE => INT_SUM(249), CARRY => INT_CARRY(202) ); ---- End HA stage ---- Begin FA stage FA_206:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(248), DATA_B => INT_SUM(249), DATA_C => INT_CARRY(196), SAVE => INT_SUM(250), CARRY => INT_CARRY(203) ); ---- End FA stage ---- Begin NO stage INT_SUM(251) <= INT_CARRY(197); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_207:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(250), DATA_B => INT_SUM(251), DATA_C => INT_CARRY(198), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End FA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin FA stage FA_208:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(292), DATA_B => SUMMAND(293), DATA_C => SUMMAND(294), SAVE => INT_SUM(252), CARRY => INT_CARRY(204) ); ---- End FA stage ---- Begin FA stage FA_209:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(295), DATA_B => SUMMAND(296), DATA_C => SUMMAND(297), SAVE => INT_SUM(253), CARRY => INT_CARRY(205) ); ---- End FA stage ---- Begin FA stage FA_210:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(252), DATA_B => INT_SUM(253), DATA_C => INT_CARRY(199), SAVE => INT_SUM(254), CARRY => INT_CARRY(206) ); ---- End FA stage ---- Begin NO stage INT_SUM(255) <= INT_CARRY(200); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_211:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_CARRY(201), SAVE => INT_SUM(256), CARRY => INT_CARRY(207) ); ---- End FA stage ---- Begin NO stage INT_SUM(257) <= INT_CARRY(202); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_212:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(256), DATA_B => INT_SUM(257), DATA_C => INT_CARRY(203), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin FA stage FA_213:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(298), DATA_B => SUMMAND(299), DATA_C => SUMMAND(300), SAVE => INT_SUM(258), CARRY => INT_CARRY(208) ); ---- End FA stage ---- Begin FA stage FA_214:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(301), DATA_B => SUMMAND(302), DATA_C => SUMMAND(303), SAVE => INT_SUM(259), CARRY => INT_CARRY(209) ); ---- End FA stage ---- Begin FA stage FA_215:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(258), DATA_B => INT_SUM(259), DATA_C => INT_CARRY(204), SAVE => INT_SUM(260), CARRY => INT_CARRY(210) ); ---- End FA stage ---- Begin NO stage INT_SUM(261) <= INT_CARRY(205); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_216:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(206), SAVE => INT_SUM(262), CARRY => INT_CARRY(211) ); ---- End FA stage ---- Begin HA stage HA_35:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(262), DATA_B => INT_CARRY(207), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End HA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin FA stage FA_217:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(304), DATA_B => SUMMAND(305), DATA_C => SUMMAND(306), SAVE => INT_SUM(263), CARRY => INT_CARRY(212) ); ---- End FA stage ---- Begin HA stage HA_36:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(307), DATA_B => SUMMAND(308), SAVE => INT_SUM(264), CARRY => INT_CARRY(213) ); ---- End HA stage ---- Begin FA stage FA_218:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(263), DATA_B => INT_SUM(264), DATA_C => INT_CARRY(208), SAVE => INT_SUM(265), CARRY => INT_CARRY(214) ); ---- End FA stage ---- Begin NO stage INT_SUM(266) <= INT_CARRY(209); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_219:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(210), SAVE => INT_SUM(267), CARRY => INT_CARRY(215) ); ---- End FA stage ---- Begin HA stage HA_37:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(267), DATA_B => INT_CARRY(211), SAVE => SUM(42), CARRY => CARRY(42) ); ---- End HA stage -- End WT-branch 43 -- Begin WT-branch 44 ---- Begin FA stage FA_220:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311), SAVE => INT_SUM(268), CARRY => INT_CARRY(216) ); ---- End FA stage ---- Begin HA stage HA_38:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), SAVE => INT_SUM(269), CARRY => INT_CARRY(217) ); ---- End HA stage ---- Begin FA stage FA_221:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(268), DATA_B => INT_SUM(269), DATA_C => INT_CARRY(212), SAVE => INT_SUM(270), CARRY => INT_CARRY(218) ); ---- End FA stage ---- Begin NO stage INT_SUM(271) <= INT_CARRY(213); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_222:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(270), DATA_B => INT_SUM(271), DATA_C => INT_CARRY(214), SAVE => INT_SUM(272), CARRY => INT_CARRY(219) ); ---- End FA stage ---- Begin HA stage HA_39:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(272), DATA_B => INT_CARRY(215), SAVE => SUM(43), CARRY => CARRY(43) ); ---- End HA stage -- End WT-branch 44 -- Begin WT-branch 45 ---- Begin FA stage FA_223:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(314), DATA_B => SUMMAND(315), DATA_C => SUMMAND(316), SAVE => INT_SUM(273), CARRY => INT_CARRY(220) ); ---- End FA stage ---- Begin FA stage FA_224:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(317), DATA_B => INT_CARRY(216), DATA_C => INT_CARRY(217), SAVE => INT_SUM(274), CARRY => INT_CARRY(221) ); ---- End FA stage ---- Begin FA stage FA_225:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(273), DATA_B => INT_SUM(274), DATA_C => INT_CARRY(218), SAVE => INT_SUM(275), CARRY => INT_CARRY(222) ); ---- End FA stage ---- Begin HA stage HA_40:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(275), DATA_B => INT_CARRY(219), SAVE => SUM(44), CARRY => CARRY(44) ); ---- End HA stage -- End WT-branch 45 -- Begin WT-branch 46 ---- Begin FA stage FA_226:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320), SAVE => INT_SUM(276), CARRY => INT_CARRY(223) ); ---- End FA stage ---- Begin NO stage INT_SUM(277) <= SUMMAND(321); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_227:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(276), DATA_B => INT_SUM(277), DATA_C => INT_CARRY(220), SAVE => INT_SUM(278), CARRY => INT_CARRY(224) ); ---- End FA stage ---- Begin NO stage INT_SUM(279) <= INT_CARRY(221); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_228:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(278), DATA_B => INT_SUM(279), DATA_C => INT_CARRY(222), SAVE => SUM(45), CARRY => CARRY(45) ); ---- End FA stage -- End WT-branch 46 -- Begin WT-branch 47 ---- Begin FA stage FA_229:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(322), DATA_B => SUMMAND(323), DATA_C => SUMMAND(324), SAVE => INT_SUM(280), CARRY => INT_CARRY(225) ); ---- End FA stage ---- Begin NO stage INT_SUM(281) <= INT_SUM(280); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(282) <= INT_CARRY(223); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_230:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(281), DATA_B => INT_SUM(282), DATA_C => INT_CARRY(224), SAVE => SUM(46), CARRY => CARRY(46) ); ---- End FA stage -- End WT-branch 47 -- Begin WT-branch 48 ---- Begin FA stage FA_231:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(325), DATA_B => SUMMAND(326), DATA_C => SUMMAND(327), SAVE => INT_SUM(283), CARRY => INT_CARRY(226) ); ---- End FA stage ---- Begin NO stage INT_SUM(284) <= INT_CARRY(225); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_41:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(283), DATA_B => INT_SUM(284), SAVE => SUM(47), CARRY => CARRY(47) ); ---- End HA stage -- End WT-branch 48 -- Begin WT-branch 49 ---- Begin NO stage INT_SUM(285) <= SUMMAND(328); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(286) <= SUMMAND(329); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_232:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(285), DATA_B => INT_SUM(286), DATA_C => INT_CARRY(226), SAVE => SUM(48), CARRY => CARRY(48) ); ---- End FA stage -- End WT-branch 49 -- Begin WT-branch 50 ---- Begin HA stage HA_42:HALF_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(330), DATA_B => SUMMAND(331), SAVE => SUM(49), CARRY => CARRY(49) ); ---- End HA stage -- End WT-branch 50 -- Begin WT-branch 51 ---- Begin NO stage SUM(50) <= SUMMAND(332); -- At Level 5 ---- End NO stage -- End WT-branch 51 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_18 is port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_34_18; ------------------------------------------------------------ -- End: Multiplier Entitiy architecture MULTIPLIER of MULTIPLIER_34_18 is signal PPBIT:std_logic_vector(0 to 332); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_18 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 17) => MULTIPLIER(0 to 17), SUMMAND(0 to 332) => PPBIT(0 to 332) ); W:WALLACE_34_18 port map ( SUMMAND(0 to 332) => PPBIT(0 to 332), CARRY(0 to 49) => INT_CARRY(1 to 50), SUM(0 to 50) => INT_SUM(0 to 50) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUM(0 to 63), OPB(0 to 63) => INT_CARRY(0 to 63), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ -- -- Modgen multiplier created Fri Aug 16 16:29:15 2002 -- ------------------------------------------------------------ -- START: Multiplier Entitiy ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -- START: Top entity ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_17 is port(X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(16 downto 0); P: out std_logic_vector(49 downto 0)); end MUL_33_17; library ieee; use ieee.std_logic_1164.all; architecture A of MUL_33_17 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 17); signal Q: std_logic_vector(0 to 63); signal CLK: std_logic; begin U1: MULTIPLIER_34_18 port map(A,B,CLK,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(16); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); P(42) <= Q(42); P(43) <= Q(43); P(44) <= Q(44); P(45) <= Q(45); P(46) <= Q(46); P(47) <= Q(47); P(48) <= Q(48); P(49) <= Q(49); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_34 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 33); SUMMAND: out std_logic_vector(0 to 628) ); end BOOTHCODER_34_34; architecture BOOTHCODER of BOOTHCODER_34_34 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 67); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(110) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(120) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(132) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(143) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(156) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(168) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(182) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(195) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(210) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(224) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(240) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(255) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(272) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(288) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(306) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(323) ); SUMMAND(324) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(100) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(111) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(121) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(133) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(144) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(157) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(169) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(183) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(196) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(211) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(225) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(241) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(256) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(273) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(289) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(307) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(325) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(341) ); SUMMAND(342) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(358) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(101) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(112) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(122) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(134) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(145) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(158) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(170) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(184) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(197) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(212) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(226) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(242) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(257) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(274) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(290) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(308) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(326) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(343) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(359) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(374) ); SUMMAND(375) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(390) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(102) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(113) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(123) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(135) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(146) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(159) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(171) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(185) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(198) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(213) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(227) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(243) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(258) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(275) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(291) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(309) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(327) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(344) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(360) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(376) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(391) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(405) ); SUMMAND(406) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(420) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(103) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(114) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(124) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(136) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(147) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(172) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(186) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(199) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(214) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(228) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(244) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(259) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(276) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(292) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(310) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(328) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(345) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(361) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(377) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(392) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(407) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(421) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(434) ); SUMMAND(435) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(448) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_165:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_166:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_167:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_168:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_169:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_170:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_171:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_172:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(104) ); PPM_173:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(115) ); PPM_174:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(125) ); PPM_175:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(137) ); PPM_176:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(148) ); PPM_177:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(161) ); PPM_178:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(173) ); PPM_179:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(187) ); PPM_180:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(200) ); PPM_181:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(215) ); PPM_182:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(229) ); PPM_183:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(245) ); PPM_184:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(260) ); PPM_185:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(277) ); PPM_186:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(293) ); PPM_187:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(311) ); PPM_188:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(329) ); PPM_189:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(346) ); PPM_190:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(362) ); PPM_191:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(378) ); PPM_192:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(393) ); PPM_193:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(408) ); PPM_194:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(422) ); PPM_195:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(436) ); PPM_196:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(449) ); PPM_197:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(461) ); SUMMAND(462) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(474) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_198:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_199:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_200:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_201:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_202:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_203:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(105) ); PPM_204:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(116) ); PPM_205:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(126) ); PPM_206:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(138) ); PPM_207:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(149) ); PPM_208:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(162) ); PPM_209:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(174) ); PPM_210:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(188) ); PPM_211:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(201) ); PPM_212:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(216) ); PPM_213:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(230) ); PPM_214:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(246) ); PPM_215:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(261) ); PPM_216:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(278) ); PPM_217:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(294) ); PPM_218:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(312) ); PPM_219:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(330) ); PPM_220:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(347) ); PPM_221:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(363) ); PPM_222:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(379) ); PPM_223:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(394) ); PPM_224:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(409) ); PPM_225:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(423) ); PPM_226:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(437) ); PPM_227:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(450) ); PPM_228:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(463) ); PPM_229:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(475) ); PPM_230:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(486) ); SUMMAND(487) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(498) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_231:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_232:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_233:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_234:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(106) ); PPM_235:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(117) ); PPM_236:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(127) ); PPM_237:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(139) ); PPM_238:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(150) ); PPM_239:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(163) ); PPM_240:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(175) ); PPM_241:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(189) ); PPM_242:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(202) ); PPM_243:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(217) ); PPM_244:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(231) ); PPM_245:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(247) ); PPM_246:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(262) ); PPM_247:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(279) ); PPM_248:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(295) ); PPM_249:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(313) ); PPM_250:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(331) ); PPM_251:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(348) ); PPM_252:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(364) ); PPM_253:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(380) ); PPM_254:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(395) ); PPM_255:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(410) ); PPM_256:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(424) ); PPM_257:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(438) ); PPM_258:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(451) ); PPM_259:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(464) ); PPM_260:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(476) ); PPM_261:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(488) ); PPM_262:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(499) ); PPM_263:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(509) ); SUMMAND(510) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(520) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_264:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_265:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(107) ); PPM_266:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(118) ); PPM_267:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(128) ); PPM_268:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(140) ); PPM_269:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(151) ); PPM_270:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(164) ); PPM_271:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(176) ); PPM_272:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(190) ); PPM_273:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(203) ); PPM_274:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(218) ); PPM_275:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(232) ); PPM_276:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(248) ); PPM_277:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(263) ); PPM_278:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(280) ); PPM_279:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(296) ); PPM_280:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(314) ); PPM_281:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(332) ); PPM_282:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(349) ); PPM_283:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(365) ); PPM_284:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(381) ); PPM_285:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(396) ); PPM_286:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(411) ); PPM_287:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(425) ); PPM_288:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(439) ); PPM_289:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(452) ); PPM_290:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(465) ); PPM_291:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(477) ); PPM_292:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(489) ); PPM_293:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(500) ); PPM_294:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(511) ); PPM_295:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(521) ); PPM_296:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(530) ); SUMMAND(531) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(540) ); -- Begin partial product 9 -- Begin decoder block 10 DEC_9:DECODER -- Decoder of multiplier operand port map ( INA => OPB(17),INB => OPB(18),INC => OPB(19), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39) ); -- End decoder block 10 -- Begin partial product 10 PPL_9:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(108) ); RGATE_9:R_GATE port map ( INA => OPB(17),INB => OPB(18),INC => OPB(19), PPBIT => SUMMAND(109) ); PPM_297:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(119) ); PPM_298:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(129) ); PPM_299:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(141) ); PPM_300:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(152) ); PPM_301:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(165) ); PPM_302:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(177) ); PPM_303:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(191) ); PPM_304:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(204) ); PPM_305:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(219) ); PPM_306:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(233) ); PPM_307:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(249) ); PPM_308:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(264) ); PPM_309:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(281) ); PPM_310:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(297) ); PPM_311:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(315) ); PPM_312:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(333) ); PPM_313:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(350) ); PPM_314:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(366) ); PPM_315:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(382) ); PPM_316:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(397) ); PPM_317:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(412) ); PPM_318:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(426) ); PPM_319:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(440) ); PPM_320:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(453) ); PPM_321:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(466) ); PPM_322:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(478) ); PPM_323:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(490) ); PPM_324:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(501) ); PPM_325:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(512) ); PPM_326:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(522) ); PPM_327:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(532) ); PPM_328:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(541) ); PPM_329:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(549) ); SUMMAND(550) <= LOGIC_ONE; PPH_9:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(558) ); -- Begin partial product 10 -- Begin decoder block 11 DEC_10:DECODER -- Decoder of multiplier operand port map ( INA => OPB(19),INB => OPB(20),INC => OPB(21), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43) ); -- End decoder block 11 -- Begin partial product 11 PPL_10:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(130) ); RGATE_10:R_GATE port map ( INA => OPB(19),INB => OPB(20),INC => OPB(21), PPBIT => SUMMAND(131) ); PPM_330:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(142) ); PPM_331:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(153) ); PPM_332:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(166) ); PPM_333:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(178) ); PPM_334:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(192) ); PPM_335:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(205) ); PPM_336:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(220) ); PPM_337:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(234) ); PPM_338:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(250) ); PPM_339:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(265) ); PPM_340:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(282) ); PPM_341:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(298) ); PPM_342:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(316) ); PPM_343:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(334) ); PPM_344:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(351) ); PPM_345:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(367) ); PPM_346:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(383) ); PPM_347:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(398) ); PPM_348:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(413) ); PPM_349:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(427) ); PPM_350:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(441) ); PPM_351:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(454) ); PPM_352:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(467) ); PPM_353:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(479) ); PPM_354:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(491) ); PPM_355:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(502) ); PPM_356:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(513) ); PPM_357:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(523) ); PPM_358:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(533) ); PPM_359:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(542) ); PPM_360:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(551) ); PPM_361:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(559) ); PPM_362:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(566) ); SUMMAND(567) <= LOGIC_ONE; PPH_10:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(574) ); -- Begin partial product 11 -- Begin decoder block 12 DEC_11:DECODER -- Decoder of multiplier operand port map ( INA => OPB(21),INB => OPB(22),INC => OPB(23), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47) ); -- End decoder block 12 -- Begin partial product 12 PPL_11:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(154) ); RGATE_11:R_GATE port map ( INA => OPB(21),INB => OPB(22),INC => OPB(23), PPBIT => SUMMAND(155) ); PPM_363:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(167) ); PPM_364:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(179) ); PPM_365:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(193) ); PPM_366:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(206) ); PPM_367:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(221) ); PPM_368:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(235) ); PPM_369:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(251) ); PPM_370:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(266) ); PPM_371:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(283) ); PPM_372:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(299) ); PPM_373:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(317) ); PPM_374:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(335) ); PPM_375:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(352) ); PPM_376:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(368) ); PPM_377:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(384) ); PPM_378:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(399) ); PPM_379:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(414) ); PPM_380:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(428) ); PPM_381:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(442) ); PPM_382:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(455) ); PPM_383:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(468) ); PPM_384:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(480) ); PPM_385:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(492) ); PPM_386:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(503) ); PPM_387:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(514) ); PPM_388:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(524) ); PPM_389:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(534) ); PPM_390:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(543) ); PPM_391:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(552) ); PPM_392:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(560) ); PPM_393:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(568) ); PPM_394:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(575) ); PPM_395:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(581) ); SUMMAND(582) <= LOGIC_ONE; PPH_11:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(588) ); -- Begin partial product 12 -- Begin decoder block 13 DEC_12:DECODER -- Decoder of multiplier operand port map ( INA => OPB(23),INB => OPB(24),INC => OPB(25), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51) ); -- End decoder block 13 -- Begin partial product 13 PPL_12:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(180) ); RGATE_12:R_GATE port map ( INA => OPB(23),INB => OPB(24),INC => OPB(25), PPBIT => SUMMAND(181) ); PPM_396:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(194) ); PPM_397:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(207) ); PPM_398:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(222) ); PPM_399:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(236) ); PPM_400:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(252) ); PPM_401:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(267) ); PPM_402:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(284) ); PPM_403:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(300) ); PPM_404:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(318) ); PPM_405:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(336) ); PPM_406:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(353) ); PPM_407:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(369) ); PPM_408:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(385) ); PPM_409:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(400) ); PPM_410:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(415) ); PPM_411:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(429) ); PPM_412:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(443) ); PPM_413:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(456) ); PPM_414:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(469) ); PPM_415:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(481) ); PPM_416:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(493) ); PPM_417:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(504) ); PPM_418:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(515) ); PPM_419:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(525) ); PPM_420:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(535) ); PPM_421:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(544) ); PPM_422:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(553) ); PPM_423:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(561) ); PPM_424:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(569) ); PPM_425:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(576) ); PPM_426:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(583) ); PPM_427:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(589) ); PPM_428:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(594) ); SUMMAND(595) <= LOGIC_ONE; PPH_12:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(600) ); -- Begin partial product 13 -- Begin decoder block 14 DEC_13:DECODER -- Decoder of multiplier operand port map ( INA => OPB(25),INB => OPB(26),INC => OPB(27), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55) ); -- End decoder block 14 -- Begin partial product 14 PPL_13:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(208) ); RGATE_13:R_GATE port map ( INA => OPB(25),INB => OPB(26),INC => OPB(27), PPBIT => SUMMAND(209) ); PPM_429:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(223) ); PPM_430:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(237) ); PPM_431:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(253) ); PPM_432:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(268) ); PPM_433:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(285) ); PPM_434:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(301) ); PPM_435:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(319) ); PPM_436:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(337) ); PPM_437:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(354) ); PPM_438:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(370) ); PPM_439:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(386) ); PPM_440:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(401) ); PPM_441:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(416) ); PPM_442:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(430) ); PPM_443:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(444) ); PPM_444:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(457) ); PPM_445:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(470) ); PPM_446:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(482) ); PPM_447:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(494) ); PPM_448:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(505) ); PPM_449:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(516) ); PPM_450:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(526) ); PPM_451:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(536) ); PPM_452:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(545) ); PPM_453:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(554) ); PPM_454:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(562) ); PPM_455:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(570) ); PPM_456:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(577) ); PPM_457:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(584) ); PPM_458:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(590) ); PPM_459:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(596) ); PPM_460:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(601) ); PPM_461:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(605) ); SUMMAND(606) <= LOGIC_ONE; PPH_13:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(610) ); -- Begin partial product 14 -- Begin decoder block 15 DEC_14:DECODER -- Decoder of multiplier operand port map ( INA => OPB(27),INB => OPB(28),INC => OPB(29), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59) ); -- End decoder block 15 -- Begin partial product 15 PPL_14:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(238) ); RGATE_14:R_GATE port map ( INA => OPB(27),INB => OPB(28),INC => OPB(29), PPBIT => SUMMAND(239) ); PPM_462:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(254) ); PPM_463:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(269) ); PPM_464:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(286) ); PPM_465:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(302) ); PPM_466:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(320) ); PPM_467:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(338) ); PPM_468:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(355) ); PPM_469:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(371) ); PPM_470:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(387) ); PPM_471:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(402) ); PPM_472:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(417) ); PPM_473:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(431) ); PPM_474:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(445) ); PPM_475:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(458) ); PPM_476:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(471) ); PPM_477:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(483) ); PPM_478:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(495) ); PPM_479:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(506) ); PPM_480:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(517) ); PPM_481:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(527) ); PPM_482:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(537) ); PPM_483:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(546) ); PPM_484:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(555) ); PPM_485:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(563) ); PPM_486:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(571) ); PPM_487:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(578) ); PPM_488:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(585) ); PPM_489:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(591) ); PPM_490:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(597) ); PPM_491:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(602) ); PPM_492:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(607) ); PPM_493:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(611) ); PPM_494:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(614) ); SUMMAND(615) <= LOGIC_ONE; PPH_14:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(618) ); -- Begin partial product 15 -- Begin decoder block 16 DEC_15:DECODER -- Decoder of multiplier operand port map ( INA => OPB(29),INB => OPB(30),INC => OPB(31), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63) ); -- End decoder block 16 -- Begin partial product 16 PPL_15:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(270) ); RGATE_15:R_GATE port map ( INA => OPB(29),INB => OPB(30),INC => OPB(31), PPBIT => SUMMAND(271) ); PPM_495:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(287) ); PPM_496:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(303) ); PPM_497:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(321) ); PPM_498:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(339) ); PPM_499:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(356) ); PPM_500:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(372) ); PPM_501:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(388) ); PPM_502:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(403) ); PPM_503:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(418) ); PPM_504:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(432) ); PPM_505:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(446) ); PPM_506:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(459) ); PPM_507:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(472) ); PPM_508:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(484) ); PPM_509:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(496) ); PPM_510:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(507) ); PPM_511:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(518) ); PPM_512:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(528) ); PPM_513:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(538) ); PPM_514:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(547) ); PPM_515:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(556) ); PPM_516:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(564) ); PPM_517:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(572) ); PPM_518:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(579) ); PPM_519:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(586) ); PPM_520:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(592) ); PPM_521:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(598) ); PPM_522:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(603) ); PPM_523:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(608) ); PPM_524:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(612) ); PPM_525:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(616) ); PPM_526:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(619) ); PPM_527:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(621) ); SUMMAND(622) <= LOGIC_ONE; PPH_15:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(624) ); -- Begin partial product 16 -- Begin decoder block 17 DEC_16:DECODER -- Decoder of multiplier operand port map ( INA => OPB(31),INB => OPB(32),INC => OPB(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67) ); -- End decoder block 17 -- Begin partial product 17 PPL_16:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(304) ); RGATE_16:R_GATE port map ( INA => OPB(31),INB => OPB(32),INC => OPB(33), PPBIT => SUMMAND(305) ); PPM_528:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(322) ); PPM_529:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(340) ); PPM_530:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(357) ); PPM_531:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(373) ); PPM_532:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(389) ); PPM_533:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(404) ); PPM_534:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(419) ); PPM_535:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(433) ); PPM_536:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(447) ); PPM_537:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(460) ); PPM_538:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(473) ); PPM_539:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(485) ); PPM_540:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(497) ); PPM_541:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(508) ); PPM_542:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(519) ); PPM_543:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(529) ); PPM_544:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(539) ); PPM_545:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(548) ); PPM_546:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(557) ); PPM_547:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(565) ); PPM_548:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(573) ); PPM_549:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(580) ); PPM_550:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(587) ); PPM_551:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(593) ); PPM_552:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(599) ); PPM_553:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(604) ); PPM_554:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(609) ); PPM_555:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(613) ); PPM_556:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(617) ); PPM_557:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(620) ); PPM_558:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(623) ); PPM_559:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(625) ); PPM_560:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(626) ); SUMMAND(627) <= LOGIC_ONE; PPH_16:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(628) ); -- Begin partial product 17 end BOOTHCODER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_34 is port ( SUMMAND: in std_logic_vector(0 to 628); CARRY: out std_logic_vector(0 to 65); SUM: out std_logic_vector(0 to 66) ); end WALLACE_34_34; architecture WALLACE of WALLACE_34_34 is -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 486); signal INT_SUM: std_logic_vector(0 to 620); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin NO stage INT_SUM(76) <= SUMMAND(108); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(77) <= SUMMAND(109); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(78), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(49), SAVE => INT_SUM(79), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin NO stage INT_SUM(80) <= INT_CARRY(50); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(81) <= INT_CARRY(51); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_SUM(80), SAVE => INT_SUM(82), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(81), DATA_B => INT_CARRY(52), DATA_C => INT_CARRY(53), SAVE => INT_SUM(83), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin FA stage FA_64:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(54), SAVE => INT_SUM(84), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(84), DATA_B => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End HA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_65:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112), SAVE => INT_SUM(85), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), DATA_C => SUMMAND(115), SAVE => INT_SUM(86), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(116), DATA_B => SUMMAND(117), DATA_C => SUMMAND(118), SAVE => INT_SUM(87), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin NO stage INT_SUM(88) <= SUMMAND(119); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(56), DATA_C => INT_CARRY(57), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(91) <= INT_CARRY(58); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91), SAVE => INT_SUM(92), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(59), DATA_B => INT_CARRY(60), SAVE => INT_SUM(93), CARRY => INT_CARRY(70) ); ---- End HA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(61), SAVE => INT_SUM(94), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(62); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(63), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End FA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125), SAVE => INT_SUM(97), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(98), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(99), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_SUM(98), SAVE => INT_SUM(100), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(99), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65), SAVE => INT_SUM(101), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin NO stage INT_SUM(102) <= INT_CARRY(66); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_79:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_SUM(102), SAVE => INT_SUM(103), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(67), DATA_B => INT_CARRY(68), SAVE => INT_SUM(104), CARRY => INT_CARRY(79) ); ---- End HA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(103), DATA_B => INT_SUM(104), DATA_C => INT_CARRY(69), SAVE => INT_SUM(105), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin NO stage INT_SUM(106) <= INT_CARRY(70); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_CARRY(71), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_82:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134), SAVE => INT_SUM(107), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(108), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140), SAVE => INT_SUM(109), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(110) <= SUMMAND(141); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(111) <= SUMMAND(142); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_85:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(107), DATA_B => INT_SUM(108), DATA_C => INT_SUM(109), SAVE => INT_SUM(112), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(72), SAVE => INT_SUM(113), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(73), DATA_B => INT_CARRY(74), DATA_C => INT_CARRY(75), SAVE => INT_SUM(114), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_SUM(114), SAVE => INT_SUM(115), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), SAVE => INT_SUM(116), CARRY => INT_CARRY(88) ); ---- End HA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(78), SAVE => INT_SUM(117), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(118) <= INT_CARRY(79); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_CARRY(80), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_91:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), DATA_C => SUMMAND(145), SAVE => INT_SUM(119), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(146), DATA_B => SUMMAND(147), DATA_C => SUMMAND(148), SAVE => INT_SUM(120), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(149), DATA_B => SUMMAND(150), DATA_C => SUMMAND(151), SAVE => INT_SUM(121), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(152), DATA_B => SUMMAND(153), DATA_C => SUMMAND(154), SAVE => INT_SUM(122), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= SUMMAND(155); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(119), DATA_B => INT_SUM(120), DATA_C => INT_SUM(121), SAVE => INT_SUM(124), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(81), SAVE => INT_SUM(125), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83), SAVE => INT_SUM(126), CARRY => INT_CARRY(96) ); ---- End HA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_SUM(126), SAVE => INT_SUM(127), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86), SAVE => INT_SUM(128), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin FA stage FA_99:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(127), DATA_B => INT_SUM(128), DATA_C => INT_CARRY(87), SAVE => INT_SUM(129), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin NO stage INT_SUM(130) <= INT_CARRY(88); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_CARRY(89), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_101:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158), SAVE => INT_SUM(131), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161), SAVE => INT_SUM(132), CARRY => INT_CARRY(101) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164), SAVE => INT_SUM(133), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(134), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin FA stage FA_105:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(131), DATA_B => INT_SUM(132), DATA_C => INT_SUM(133), SAVE => INT_SUM(135), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin FA stage FA_106:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(134), DATA_B => INT_CARRY(90), DATA_C => INT_CARRY(91), SAVE => INT_SUM(136), CARRY => INT_CARRY(105) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(92), DATA_B => INT_CARRY(93), SAVE => INT_SUM(137), CARRY => INT_CARRY(106) ); ---- End HA stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_SUM(137), SAVE => INT_SUM(138), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin FA stage FA_108:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(94), DATA_B => INT_CARRY(95), DATA_C => INT_CARRY(96), SAVE => INT_SUM(139), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(138), DATA_B => INT_SUM(139), DATA_C => INT_CARRY(97), SAVE => INT_SUM(140), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin NO stage INT_SUM(141) <= INT_CARRY(98); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(99), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_111:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170), SAVE => INT_SUM(142), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173), SAVE => INT_SUM(143), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin FA stage FA_113:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(144), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin FA stage FA_114:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(145), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), SAVE => INT_SUM(146), CARRY => INT_CARRY(114) ); ---- End HA stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_SUM(144), SAVE => INT_SUM(147), CARRY => INT_CARRY(115) ); ---- End FA stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(100), SAVE => INT_SUM(148), CARRY => INT_CARRY(116) ); ---- End FA stage ---- Begin FA stage FA_117:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(101), DATA_B => INT_CARRY(102), DATA_C => INT_CARRY(103), SAVE => INT_SUM(149), CARRY => INT_CARRY(117) ); ---- End FA stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(147), DATA_B => INT_SUM(148), DATA_C => INT_SUM(149), SAVE => INT_SUM(150), CARRY => INT_CARRY(118) ); ---- End FA stage ---- Begin FA stage FA_119:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(104), DATA_B => INT_CARRY(105), DATA_C => INT_CARRY(106), SAVE => INT_SUM(151), CARRY => INT_CARRY(119) ); ---- End FA stage ---- Begin FA stage FA_120:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(107), SAVE => INT_SUM(152), CARRY => INT_CARRY(120) ); ---- End FA stage ---- Begin NO stage INT_SUM(153) <= INT_CARRY(108); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_121:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(152), DATA_B => INT_SUM(153), DATA_C => INT_CARRY(109), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_122:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), DATA_C => SUMMAND(184), SAVE => INT_SUM(154), CARRY => INT_CARRY(121) ); ---- End FA stage ---- Begin FA stage FA_123:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(185), DATA_B => SUMMAND(186), DATA_C => SUMMAND(187), SAVE => INT_SUM(155), CARRY => INT_CARRY(122) ); ---- End FA stage ---- Begin FA stage FA_124:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(188), DATA_B => SUMMAND(189), DATA_C => SUMMAND(190), SAVE => INT_SUM(156), CARRY => INT_CARRY(123) ); ---- End FA stage ---- Begin FA stage FA_125:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(191), DATA_B => SUMMAND(192), DATA_C => SUMMAND(193), SAVE => INT_SUM(157), CARRY => INT_CARRY(124) ); ---- End FA stage ---- Begin NO stage INT_SUM(158) <= SUMMAND(194); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_126:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(154), DATA_B => INT_SUM(155), DATA_C => INT_SUM(156), SAVE => INT_SUM(159), CARRY => INT_CARRY(125) ); ---- End FA stage ---- Begin FA stage FA_127:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(110), SAVE => INT_SUM(160), CARRY => INT_CARRY(126) ); ---- End FA stage ---- Begin FA stage FA_128:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(111), DATA_B => INT_CARRY(112), DATA_C => INT_CARRY(113), SAVE => INT_SUM(161), CARRY => INT_CARRY(127) ); ---- End FA stage ---- Begin NO stage INT_SUM(162) <= INT_CARRY(114); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_129:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(159), DATA_B => INT_SUM(160), DATA_C => INT_SUM(161), SAVE => INT_SUM(163), CARRY => INT_CARRY(128) ); ---- End FA stage ---- Begin FA stage FA_130:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(162), DATA_B => INT_CARRY(115), DATA_C => INT_CARRY(116), SAVE => INT_SUM(164), CARRY => INT_CARRY(129) ); ---- End FA stage ---- Begin NO stage INT_SUM(165) <= INT_CARRY(117); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_131:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(163), DATA_B => INT_SUM(164), DATA_C => INT_SUM(165), SAVE => INT_SUM(166), CARRY => INT_CARRY(130) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(118), DATA_B => INT_CARRY(119), SAVE => INT_SUM(167), CARRY => INT_CARRY(131) ); ---- End HA stage ---- Begin FA stage FA_132:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(120), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End FA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_133:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197), SAVE => INT_SUM(168), CARRY => INT_CARRY(132) ); ---- End FA stage ---- Begin FA stage FA_134:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200), SAVE => INT_SUM(169), CARRY => INT_CARRY(133) ); ---- End FA stage ---- Begin FA stage FA_135:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203), SAVE => INT_SUM(170), CARRY => INT_CARRY(134) ); ---- End FA stage ---- Begin FA stage FA_136:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206), SAVE => INT_SUM(171), CARRY => INT_CARRY(135) ); ---- End FA stage ---- Begin FA stage FA_137:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209), SAVE => INT_SUM(172), CARRY => INT_CARRY(136) ); ---- End FA stage ---- Begin FA stage FA_138:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(168), DATA_B => INT_SUM(169), DATA_C => INT_SUM(170), SAVE => INT_SUM(173), CARRY => INT_CARRY(137) ); ---- End FA stage ---- Begin FA stage FA_139:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(171), DATA_B => INT_SUM(172), DATA_C => INT_CARRY(121), SAVE => INT_SUM(174), CARRY => INT_CARRY(138) ); ---- End FA stage ---- Begin FA stage FA_140:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(122), DATA_B => INT_CARRY(123), DATA_C => INT_CARRY(124), SAVE => INT_SUM(175), CARRY => INT_CARRY(139) ); ---- End FA stage ---- Begin FA stage FA_141:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(173), DATA_B => INT_SUM(174), DATA_C => INT_SUM(175), SAVE => INT_SUM(176), CARRY => INT_CARRY(140) ); ---- End FA stage ---- Begin FA stage FA_142:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(125), DATA_B => INT_CARRY(126), DATA_C => INT_CARRY(127), SAVE => INT_SUM(177), CARRY => INT_CARRY(141) ); ---- End FA stage ---- Begin FA stage FA_143:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(176), DATA_B => INT_SUM(177), DATA_C => INT_CARRY(128), SAVE => INT_SUM(178), CARRY => INT_CARRY(142) ); ---- End FA stage ---- Begin NO stage INT_SUM(179) <= INT_CARRY(129); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_144:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(178), DATA_B => INT_SUM(179), DATA_C => INT_CARRY(130), SAVE => INT_SUM(180), CARRY => INT_CARRY(143) ); ---- End FA stage ---- Begin NO stage INT_SUM(181) <= INT_CARRY(131); -- At Level 5 ---- End NO stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_145:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212), SAVE => INT_SUM(182), CARRY => INT_CARRY(144) ); ---- End FA stage ---- Begin FA stage FA_146:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215), SAVE => INT_SUM(183), CARRY => INT_CARRY(145) ); ---- End FA stage ---- Begin FA stage FA_147:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218), SAVE => INT_SUM(184), CARRY => INT_CARRY(146) ); ---- End FA stage ---- Begin FA stage FA_148:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221), SAVE => INT_SUM(185), CARRY => INT_CARRY(147) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), SAVE => INT_SUM(186), CARRY => INT_CARRY(148) ); ---- End HA stage ---- Begin FA stage FA_149:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_SUM(184), SAVE => INT_SUM(187), CARRY => INT_CARRY(149) ); ---- End FA stage ---- Begin FA stage FA_150:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_CARRY(132), SAVE => INT_SUM(188), CARRY => INT_CARRY(150) ); ---- End FA stage ---- Begin FA stage FA_151:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135), SAVE => INT_SUM(189), CARRY => INT_CARRY(151) ); ---- End FA stage ---- Begin NO stage INT_SUM(190) <= INT_CARRY(136); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_152:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(187), DATA_B => INT_SUM(188), DATA_C => INT_SUM(189), SAVE => INT_SUM(191), CARRY => INT_CARRY(152) ); ---- End FA stage ---- Begin FA stage FA_153:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(190), DATA_B => INT_CARRY(137), DATA_C => INT_CARRY(138), SAVE => INT_SUM(192), CARRY => INT_CARRY(153) ); ---- End FA stage ---- Begin NO stage INT_SUM(193) <= INT_CARRY(139); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_154:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(191), DATA_B => INT_SUM(192), DATA_C => INT_SUM(193), SAVE => INT_SUM(194), CARRY => INT_CARRY(154) ); ---- End FA stage ---- Begin NO stage INT_SUM(195) <= INT_CARRY(140); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(196) <= INT_CARRY(141); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_155:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(194), DATA_B => INT_SUM(195), DATA_C => INT_SUM(196), SAVE => INT_SUM(197), CARRY => INT_CARRY(155) ); ---- End FA stage ---- Begin NO stage INT_SUM(198) <= INT_CARRY(142); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_156:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(197), DATA_B => INT_SUM(198), DATA_C => INT_CARRY(143), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End FA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_157:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(224), DATA_B => SUMMAND(225), DATA_C => SUMMAND(226), SAVE => INT_SUM(199), CARRY => INT_CARRY(156) ); ---- End FA stage ---- Begin FA stage FA_158:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(227), DATA_B => SUMMAND(228), DATA_C => SUMMAND(229), SAVE => INT_SUM(200), CARRY => INT_CARRY(157) ); ---- End FA stage ---- Begin FA stage FA_159:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(230), DATA_B => SUMMAND(231), DATA_C => SUMMAND(232), SAVE => INT_SUM(201), CARRY => INT_CARRY(158) ); ---- End FA stage ---- Begin FA stage FA_160:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(233), DATA_B => SUMMAND(234), DATA_C => SUMMAND(235), SAVE => INT_SUM(202), CARRY => INT_CARRY(159) ); ---- End FA stage ---- Begin FA stage FA_161:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(236), DATA_B => SUMMAND(237), DATA_C => SUMMAND(238), SAVE => INT_SUM(203), CARRY => INT_CARRY(160) ); ---- End FA stage ---- Begin NO stage INT_SUM(204) <= SUMMAND(239); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_162:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(199), DATA_B => INT_SUM(200), DATA_C => INT_SUM(201), SAVE => INT_SUM(205), CARRY => INT_CARRY(161) ); ---- End FA stage ---- Begin FA stage FA_163:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(202), DATA_B => INT_SUM(203), DATA_C => INT_SUM(204), SAVE => INT_SUM(206), CARRY => INT_CARRY(162) ); ---- End FA stage ---- Begin FA stage FA_164:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(144), DATA_B => INT_CARRY(145), DATA_C => INT_CARRY(146), SAVE => INT_SUM(207), CARRY => INT_CARRY(163) ); ---- End FA stage ---- Begin NO stage INT_SUM(208) <= INT_CARRY(147); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(209) <= INT_CARRY(148); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_165:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207), SAVE => INT_SUM(210), CARRY => INT_CARRY(164) ); ---- End FA stage ---- Begin FA stage FA_166:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_CARRY(149), SAVE => INT_SUM(211), CARRY => INT_CARRY(165) ); ---- End FA stage ---- Begin NO stage INT_SUM(212) <= INT_CARRY(150); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(213) <= INT_CARRY(151); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_167:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(210), DATA_B => INT_SUM(211), DATA_C => INT_SUM(212), SAVE => INT_SUM(214), CARRY => INT_CARRY(166) ); ---- End FA stage ---- Begin FA stage FA_168:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(213), DATA_B => INT_CARRY(152), DATA_C => INT_CARRY(153), SAVE => INT_SUM(215), CARRY => INT_CARRY(167) ); ---- End FA stage ---- Begin FA stage FA_169:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(214), DATA_B => INT_SUM(215), DATA_C => INT_CARRY(154), SAVE => INT_SUM(216), CARRY => INT_CARRY(168) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(216), DATA_B => INT_CARRY(155), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_170:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242), SAVE => INT_SUM(217), CARRY => INT_CARRY(169) ); ---- End FA stage ---- Begin FA stage FA_171:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245), SAVE => INT_SUM(218), CARRY => INT_CARRY(170) ); ---- End FA stage ---- Begin FA stage FA_172:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248), SAVE => INT_SUM(219), CARRY => INT_CARRY(171) ); ---- End FA stage ---- Begin FA stage FA_173:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251), SAVE => INT_SUM(220), CARRY => INT_CARRY(172) ); ---- End FA stage ---- Begin FA stage FA_174:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(252), DATA_B => SUMMAND(253), DATA_C => SUMMAND(254), SAVE => INT_SUM(221), CARRY => INT_CARRY(173) ); ---- End FA stage ---- Begin FA stage FA_175:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_SUM(219), SAVE => INT_SUM(222), CARRY => INT_CARRY(174) ); ---- End FA stage ---- Begin FA stage FA_176:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_CARRY(156), SAVE => INT_SUM(223), CARRY => INT_CARRY(175) ); ---- End FA stage ---- Begin FA stage FA_177:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(157), DATA_B => INT_CARRY(158), DATA_C => INT_CARRY(159), SAVE => INT_SUM(224), CARRY => INT_CARRY(176) ); ---- End FA stage ---- Begin NO stage INT_SUM(225) <= INT_CARRY(160); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_178:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(222), DATA_B => INT_SUM(223), DATA_C => INT_SUM(224), SAVE => INT_SUM(226), CARRY => INT_CARRY(177) ); ---- End FA stage ---- Begin FA stage FA_179:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(225), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162), SAVE => INT_SUM(227), CARRY => INT_CARRY(178) ); ---- End FA stage ---- Begin NO stage INT_SUM(228) <= INT_CARRY(163); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_180:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_SUM(228), SAVE => INT_SUM(229), CARRY => INT_CARRY(179) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(164), DATA_B => INT_CARRY(165), SAVE => INT_SUM(230), CARRY => INT_CARRY(180) ); ---- End HA stage ---- Begin FA stage FA_181:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(229), DATA_B => INT_SUM(230), DATA_C => INT_CARRY(166), SAVE => INT_SUM(231), CARRY => INT_CARRY(181) ); ---- End FA stage ---- Begin NO stage INT_SUM(232) <= INT_CARRY(167); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_182:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(231), DATA_B => INT_SUM(232), DATA_C => INT_CARRY(168), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_183:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(255), DATA_B => SUMMAND(256), DATA_C => SUMMAND(257), SAVE => INT_SUM(233), CARRY => INT_CARRY(182) ); ---- End FA stage ---- Begin FA stage FA_184:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(258), DATA_B => SUMMAND(259), DATA_C => SUMMAND(260), SAVE => INT_SUM(234), CARRY => INT_CARRY(183) ); ---- End FA stage ---- Begin FA stage FA_185:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(261), DATA_B => SUMMAND(262), DATA_C => SUMMAND(263), SAVE => INT_SUM(235), CARRY => INT_CARRY(184) ); ---- End FA stage ---- Begin FA stage FA_186:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(264), DATA_B => SUMMAND(265), DATA_C => SUMMAND(266), SAVE => INT_SUM(236), CARRY => INT_CARRY(185) ); ---- End FA stage ---- Begin FA stage FA_187:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(267), DATA_B => SUMMAND(268), DATA_C => SUMMAND(269), SAVE => INT_SUM(237), CARRY => INT_CARRY(186) ); ---- End FA stage ---- Begin NO stage INT_SUM(238) <= SUMMAND(270); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(239) <= SUMMAND(271); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_188:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(233), DATA_B => INT_SUM(234), DATA_C => INT_SUM(235), SAVE => INT_SUM(240), CARRY => INT_CARRY(187) ); ---- End FA stage ---- Begin FA stage FA_189:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_SUM(238), SAVE => INT_SUM(241), CARRY => INT_CARRY(188) ); ---- End FA stage ---- Begin FA stage FA_190:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(239), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170), SAVE => INT_SUM(242), CARRY => INT_CARRY(189) ); ---- End FA stage ---- Begin FA stage FA_191:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(171), DATA_B => INT_CARRY(172), DATA_C => INT_CARRY(173), SAVE => INT_SUM(243), CARRY => INT_CARRY(190) ); ---- End FA stage ---- Begin FA stage FA_192:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(240), DATA_B => INT_SUM(241), DATA_C => INT_SUM(242), SAVE => INT_SUM(244), CARRY => INT_CARRY(191) ); ---- End FA stage ---- Begin FA stage FA_193:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(243), DATA_B => INT_CARRY(174), DATA_C => INT_CARRY(175), SAVE => INT_SUM(245), CARRY => INT_CARRY(192) ); ---- End FA stage ---- Begin NO stage INT_SUM(246) <= INT_CARRY(176); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_194:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(244), DATA_B => INT_SUM(245), DATA_C => INT_SUM(246), SAVE => INT_SUM(247), CARRY => INT_CARRY(193) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(177), DATA_B => INT_CARRY(178), SAVE => INT_SUM(248), CARRY => INT_CARRY(194) ); ---- End HA stage ---- Begin FA stage FA_195:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(247), DATA_B => INT_SUM(248), DATA_C => INT_CARRY(179), SAVE => INT_SUM(249), CARRY => INT_CARRY(195) ); ---- End FA stage ---- Begin NO stage INT_SUM(250) <= INT_CARRY(180); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_196:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(249), DATA_B => INT_SUM(250), DATA_C => INT_CARRY(181), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_197:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(272), DATA_B => SUMMAND(273), DATA_C => SUMMAND(274), SAVE => INT_SUM(251), CARRY => INT_CARRY(196) ); ---- End FA stage ---- Begin FA stage FA_198:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(275), DATA_B => SUMMAND(276), DATA_C => SUMMAND(277), SAVE => INT_SUM(252), CARRY => INT_CARRY(197) ); ---- End FA stage ---- Begin FA stage FA_199:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280), SAVE => INT_SUM(253), CARRY => INT_CARRY(198) ); ---- End FA stage ---- Begin FA stage FA_200:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283), SAVE => INT_SUM(254), CARRY => INT_CARRY(199) ); ---- End FA stage ---- Begin FA stage FA_201:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(284), DATA_B => SUMMAND(285), DATA_C => SUMMAND(286), SAVE => INT_SUM(255), CARRY => INT_CARRY(200) ); ---- End FA stage ---- Begin NO stage INT_SUM(256) <= SUMMAND(287); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_202:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(251), DATA_B => INT_SUM(252), DATA_C => INT_SUM(253), SAVE => INT_SUM(257), CARRY => INT_CARRY(201) ); ---- End FA stage ---- Begin FA stage FA_203:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_SUM(256), SAVE => INT_SUM(258), CARRY => INT_CARRY(202) ); ---- End FA stage ---- Begin FA stage FA_204:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(182), DATA_B => INT_CARRY(183), DATA_C => INT_CARRY(184), SAVE => INT_SUM(259), CARRY => INT_CARRY(203) ); ---- End FA stage ---- Begin NO stage INT_SUM(260) <= INT_CARRY(185); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(261) <= INT_CARRY(186); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_205:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(257), DATA_B => INT_SUM(258), DATA_C => INT_SUM(259), SAVE => INT_SUM(262), CARRY => INT_CARRY(204) ); ---- End FA stage ---- Begin FA stage FA_206:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(187), SAVE => INT_SUM(263), CARRY => INT_CARRY(205) ); ---- End FA stage ---- Begin FA stage FA_207:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190), SAVE => INT_SUM(264), CARRY => INT_CARRY(206) ); ---- End FA stage ---- Begin FA stage FA_208:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(262), DATA_B => INT_SUM(263), DATA_C => INT_SUM(264), SAVE => INT_SUM(265), CARRY => INT_CARRY(207) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(191), DATA_B => INT_CARRY(192), SAVE => INT_SUM(266), CARRY => INT_CARRY(208) ); ---- End HA stage ---- Begin FA stage FA_209:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(193), SAVE => INT_SUM(267), CARRY => INT_CARRY(209) ); ---- End FA stage ---- Begin NO stage INT_SUM(268) <= INT_CARRY(194); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_210:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(267), DATA_B => INT_SUM(268), DATA_C => INT_CARRY(195), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End FA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_211:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290), SAVE => INT_SUM(269), CARRY => INT_CARRY(210) ); ---- End FA stage ---- Begin FA stage FA_212:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(291), DATA_B => SUMMAND(292), DATA_C => SUMMAND(293), SAVE => INT_SUM(270), CARRY => INT_CARRY(211) ); ---- End FA stage ---- Begin FA stage FA_213:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(294), DATA_B => SUMMAND(295), DATA_C => SUMMAND(296), SAVE => INT_SUM(271), CARRY => INT_CARRY(212) ); ---- End FA stage ---- Begin FA stage FA_214:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(297), DATA_B => SUMMAND(298), DATA_C => SUMMAND(299), SAVE => INT_SUM(272), CARRY => INT_CARRY(213) ); ---- End FA stage ---- Begin FA stage FA_215:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(300), DATA_B => SUMMAND(301), DATA_C => SUMMAND(302), SAVE => INT_SUM(273), CARRY => INT_CARRY(214) ); ---- End FA stage ---- Begin FA stage FA_216:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(303), DATA_B => SUMMAND(304), DATA_C => SUMMAND(305), SAVE => INT_SUM(274), CARRY => INT_CARRY(215) ); ---- End FA stage ---- Begin FA stage FA_217:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(269), DATA_B => INT_SUM(270), DATA_C => INT_SUM(271), SAVE => INT_SUM(275), CARRY => INT_CARRY(216) ); ---- End FA stage ---- Begin FA stage FA_218:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(272), DATA_B => INT_SUM(273), DATA_C => INT_SUM(274), SAVE => INT_SUM(276), CARRY => INT_CARRY(217) ); ---- End FA stage ---- Begin FA stage FA_219:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(196), DATA_B => INT_CARRY(197), DATA_C => INT_CARRY(198), SAVE => INT_SUM(277), CARRY => INT_CARRY(218) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(199), DATA_B => INT_CARRY(200), SAVE => INT_SUM(278), CARRY => INT_CARRY(219) ); ---- End HA stage ---- Begin FA stage FA_220:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(275), DATA_B => INT_SUM(276), DATA_C => INT_SUM(277), SAVE => INT_SUM(279), CARRY => INT_CARRY(220) ); ---- End FA stage ---- Begin FA stage FA_221:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(278), DATA_B => INT_CARRY(201), DATA_C => INT_CARRY(202), SAVE => INT_SUM(280), CARRY => INT_CARRY(221) ); ---- End FA stage ---- Begin NO stage INT_SUM(281) <= INT_CARRY(203); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_222:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(279), DATA_B => INT_SUM(280), DATA_C => INT_SUM(281), SAVE => INT_SUM(282), CARRY => INT_CARRY(222) ); ---- End FA stage ---- Begin FA stage FA_223:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(204), DATA_B => INT_CARRY(205), DATA_C => INT_CARRY(206), SAVE => INT_SUM(283), CARRY => INT_CARRY(223) ); ---- End FA stage ---- Begin FA stage FA_224:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(282), DATA_B => INT_SUM(283), DATA_C => INT_CARRY(207), SAVE => INT_SUM(284), CARRY => INT_CARRY(224) ); ---- End FA stage ---- Begin NO stage INT_SUM(285) <= INT_CARRY(208); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_225:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(284), DATA_B => INT_SUM(285), DATA_C => INT_CARRY(209), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_226:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(306), DATA_B => SUMMAND(307), DATA_C => SUMMAND(308), SAVE => INT_SUM(286), CARRY => INT_CARRY(225) ); ---- End FA stage ---- Begin FA stage FA_227:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311), SAVE => INT_SUM(287), CARRY => INT_CARRY(226) ); ---- End FA stage ---- Begin FA stage FA_228:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), DATA_C => SUMMAND(314), SAVE => INT_SUM(288), CARRY => INT_CARRY(227) ); ---- End FA stage ---- Begin FA stage FA_229:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(315), DATA_B => SUMMAND(316), DATA_C => SUMMAND(317), SAVE => INT_SUM(289), CARRY => INT_CARRY(228) ); ---- End FA stage ---- Begin FA stage FA_230:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320), SAVE => INT_SUM(290), CARRY => INT_CARRY(229) ); ---- End FA stage ---- Begin NO stage INT_SUM(291) <= SUMMAND(321); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(292) <= SUMMAND(322); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_231:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(286), DATA_B => INT_SUM(287), DATA_C => INT_SUM(288), SAVE => INT_SUM(293), CARRY => INT_CARRY(230) ); ---- End FA stage ---- Begin FA stage FA_232:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(289), DATA_B => INT_SUM(290), DATA_C => INT_SUM(291), SAVE => INT_SUM(294), CARRY => INT_CARRY(231) ); ---- End FA stage ---- Begin FA stage FA_233:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(292), DATA_B => INT_CARRY(210), DATA_C => INT_CARRY(211), SAVE => INT_SUM(295), CARRY => INT_CARRY(232) ); ---- End FA stage ---- Begin FA stage FA_234:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(212), DATA_B => INT_CARRY(213), DATA_C => INT_CARRY(214), SAVE => INT_SUM(296), CARRY => INT_CARRY(233) ); ---- End FA stage ---- Begin NO stage INT_SUM(297) <= INT_CARRY(215); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_235:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(293), DATA_B => INT_SUM(294), DATA_C => INT_SUM(295), SAVE => INT_SUM(298), CARRY => INT_CARRY(234) ); ---- End FA stage ---- Begin FA stage FA_236:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(296), DATA_B => INT_SUM(297), DATA_C => INT_CARRY(216), SAVE => INT_SUM(299), CARRY => INT_CARRY(235) ); ---- End FA stage ---- Begin FA stage FA_237:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(217), DATA_B => INT_CARRY(218), DATA_C => INT_CARRY(219), SAVE => INT_SUM(300), CARRY => INT_CARRY(236) ); ---- End FA stage ---- Begin FA stage FA_238:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(298), DATA_B => INT_SUM(299), DATA_C => INT_SUM(300), SAVE => INT_SUM(301), CARRY => INT_CARRY(237) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(220), DATA_B => INT_CARRY(221), SAVE => INT_SUM(302), CARRY => INT_CARRY(238) ); ---- End HA stage ---- Begin FA stage FA_239:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(301), DATA_B => INT_SUM(302), DATA_C => INT_CARRY(222), SAVE => INT_SUM(303), CARRY => INT_CARRY(239) ); ---- End FA stage ---- Begin NO stage INT_SUM(304) <= INT_CARRY(223); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_240:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(303), DATA_B => INT_SUM(304), DATA_C => INT_CARRY(224), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End FA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_241:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(323), DATA_B => SUMMAND(324), DATA_C => SUMMAND(325), SAVE => INT_SUM(305), CARRY => INT_CARRY(240) ); ---- End FA stage ---- Begin FA stage FA_242:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(326), DATA_B => SUMMAND(327), DATA_C => SUMMAND(328), SAVE => INT_SUM(306), CARRY => INT_CARRY(241) ); ---- End FA stage ---- Begin FA stage FA_243:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(329), DATA_B => SUMMAND(330), DATA_C => SUMMAND(331), SAVE => INT_SUM(307), CARRY => INT_CARRY(242) ); ---- End FA stage ---- Begin FA stage FA_244:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(332), DATA_B => SUMMAND(333), DATA_C => SUMMAND(334), SAVE => INT_SUM(308), CARRY => INT_CARRY(243) ); ---- End FA stage ---- Begin FA stage FA_245:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(335), DATA_B => SUMMAND(336), DATA_C => SUMMAND(337), SAVE => INT_SUM(309), CARRY => INT_CARRY(244) ); ---- End FA stage ---- Begin FA stage FA_246:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(338), DATA_B => SUMMAND(339), DATA_C => SUMMAND(340), SAVE => INT_SUM(310), CARRY => INT_CARRY(245) ); ---- End FA stage ---- Begin FA stage FA_247:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(305), DATA_B => INT_SUM(306), DATA_C => INT_SUM(307), SAVE => INT_SUM(311), CARRY => INT_CARRY(246) ); ---- End FA stage ---- Begin FA stage FA_248:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(308), DATA_B => INT_SUM(309), DATA_C => INT_SUM(310), SAVE => INT_SUM(312), CARRY => INT_CARRY(247) ); ---- End FA stage ---- Begin FA stage FA_249:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(225), DATA_B => INT_CARRY(226), DATA_C => INT_CARRY(227), SAVE => INT_SUM(313), CARRY => INT_CARRY(248) ); ---- End FA stage ---- Begin NO stage INT_SUM(314) <= INT_CARRY(228); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(315) <= INT_CARRY(229); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_250:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(311), DATA_B => INT_SUM(312), DATA_C => INT_SUM(313), SAVE => INT_SUM(316), CARRY => INT_CARRY(249) ); ---- End FA stage ---- Begin FA stage FA_251:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(314), DATA_B => INT_SUM(315), DATA_C => INT_CARRY(230), SAVE => INT_SUM(317), CARRY => INT_CARRY(250) ); ---- End FA stage ---- Begin FA stage FA_252:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(231), DATA_B => INT_CARRY(232), DATA_C => INT_CARRY(233), SAVE => INT_SUM(318), CARRY => INT_CARRY(251) ); ---- End FA stage ---- Begin FA stage FA_253:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(316), DATA_B => INT_SUM(317), DATA_C => INT_SUM(318), SAVE => INT_SUM(319), CARRY => INT_CARRY(252) ); ---- End FA stage ---- Begin FA stage FA_254:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(234), DATA_B => INT_CARRY(235), DATA_C => INT_CARRY(236), SAVE => INT_SUM(320), CARRY => INT_CARRY(253) ); ---- End FA stage ---- Begin FA stage FA_255:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(319), DATA_B => INT_SUM(320), DATA_C => INT_CARRY(237), SAVE => INT_SUM(321), CARRY => INT_CARRY(254) ); ---- End FA stage ---- Begin NO stage INT_SUM(322) <= INT_CARRY(238); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_256:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(321), DATA_B => INT_SUM(322), DATA_C => INT_CARRY(239), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_257:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(341), DATA_B => SUMMAND(342), DATA_C => SUMMAND(343), SAVE => INT_SUM(323), CARRY => INT_CARRY(255) ); ---- End FA stage ---- Begin FA stage FA_258:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(344), DATA_B => SUMMAND(345), DATA_C => SUMMAND(346), SAVE => INT_SUM(324), CARRY => INT_CARRY(256) ); ---- End FA stage ---- Begin FA stage FA_259:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(347), DATA_B => SUMMAND(348), DATA_C => SUMMAND(349), SAVE => INT_SUM(325), CARRY => INT_CARRY(257) ); ---- End FA stage ---- Begin FA stage FA_260:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(350), DATA_B => SUMMAND(351), DATA_C => SUMMAND(352), SAVE => INT_SUM(326), CARRY => INT_CARRY(258) ); ---- End FA stage ---- Begin FA stage FA_261:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(353), DATA_B => SUMMAND(354), DATA_C => SUMMAND(355), SAVE => INT_SUM(327), CARRY => INT_CARRY(259) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(356), DATA_B => SUMMAND(357), SAVE => INT_SUM(328), CARRY => INT_CARRY(260) ); ---- End HA stage ---- Begin FA stage FA_262:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(323), DATA_B => INT_SUM(324), DATA_C => INT_SUM(325), SAVE => INT_SUM(329), CARRY => INT_CARRY(261) ); ---- End FA stage ---- Begin FA stage FA_263:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(326), DATA_B => INT_SUM(327), DATA_C => INT_SUM(328), SAVE => INT_SUM(330), CARRY => INT_CARRY(262) ); ---- End FA stage ---- Begin FA stage FA_264:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(240), DATA_B => INT_CARRY(241), DATA_C => INT_CARRY(242), SAVE => INT_SUM(331), CARRY => INT_CARRY(263) ); ---- End FA stage ---- Begin FA stage FA_265:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(243), DATA_B => INT_CARRY(244), DATA_C => INT_CARRY(245), SAVE => INT_SUM(332), CARRY => INT_CARRY(264) ); ---- End FA stage ---- Begin FA stage FA_266:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(329), DATA_B => INT_SUM(330), DATA_C => INT_SUM(331), SAVE => INT_SUM(333), CARRY => INT_CARRY(265) ); ---- End FA stage ---- Begin FA stage FA_267:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(332), DATA_B => INT_CARRY(246), DATA_C => INT_CARRY(247), SAVE => INT_SUM(334), CARRY => INT_CARRY(266) ); ---- End FA stage ---- Begin NO stage INT_SUM(335) <= INT_CARRY(248); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_268:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(333), DATA_B => INT_SUM(334), DATA_C => INT_SUM(335), SAVE => INT_SUM(336), CARRY => INT_CARRY(267) ); ---- End FA stage ---- Begin FA stage FA_269:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(249), DATA_B => INT_CARRY(250), DATA_C => INT_CARRY(251), SAVE => INT_SUM(337), CARRY => INT_CARRY(268) ); ---- End FA stage ---- Begin FA stage FA_270:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(336), DATA_B => INT_SUM(337), DATA_C => INT_CARRY(252), SAVE => INT_SUM(338), CARRY => INT_CARRY(269) ); ---- End FA stage ---- Begin NO stage INT_SUM(339) <= INT_CARRY(253); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_271:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(338), DATA_B => INT_SUM(339), DATA_C => INT_CARRY(254), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End FA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_272:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(358), DATA_B => SUMMAND(359), DATA_C => SUMMAND(360), SAVE => INT_SUM(340), CARRY => INT_CARRY(270) ); ---- End FA stage ---- Begin FA stage FA_273:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(361), DATA_B => SUMMAND(362), DATA_C => SUMMAND(363), SAVE => INT_SUM(341), CARRY => INT_CARRY(271) ); ---- End FA stage ---- Begin FA stage FA_274:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(364), DATA_B => SUMMAND(365), DATA_C => SUMMAND(366), SAVE => INT_SUM(342), CARRY => INT_CARRY(272) ); ---- End FA stage ---- Begin FA stage FA_275:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(367), DATA_B => SUMMAND(368), DATA_C => SUMMAND(369), SAVE => INT_SUM(343), CARRY => INT_CARRY(273) ); ---- End FA stage ---- Begin FA stage FA_276:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(370), DATA_B => SUMMAND(371), DATA_C => SUMMAND(372), SAVE => INT_SUM(344), CARRY => INT_CARRY(274) ); ---- End FA stage ---- Begin NO stage INT_SUM(345) <= SUMMAND(373); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_277:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(340), DATA_B => INT_SUM(341), DATA_C => INT_SUM(342), SAVE => INT_SUM(346), CARRY => INT_CARRY(275) ); ---- End FA stage ---- Begin FA stage FA_278:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(343), DATA_B => INT_SUM(344), DATA_C => INT_SUM(345), SAVE => INT_SUM(347), CARRY => INT_CARRY(276) ); ---- End FA stage ---- Begin FA stage FA_279:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(255), DATA_B => INT_CARRY(256), DATA_C => INT_CARRY(257), SAVE => INT_SUM(348), CARRY => INT_CARRY(277) ); ---- End FA stage ---- Begin FA stage FA_280:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(258), DATA_B => INT_CARRY(259), DATA_C => INT_CARRY(260), SAVE => INT_SUM(349), CARRY => INT_CARRY(278) ); ---- End FA stage ---- Begin FA stage FA_281:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(346), DATA_B => INT_SUM(347), DATA_C => INT_SUM(348), SAVE => INT_SUM(350), CARRY => INT_CARRY(279) ); ---- End FA stage ---- Begin FA stage FA_282:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(349), DATA_B => INT_CARRY(261), DATA_C => INT_CARRY(262), SAVE => INT_SUM(351), CARRY => INT_CARRY(280) ); ---- End FA stage ---- Begin NO stage INT_SUM(352) <= INT_CARRY(263); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(353) <= INT_CARRY(264); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_283:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(350), DATA_B => INT_SUM(351), DATA_C => INT_SUM(352), SAVE => INT_SUM(354), CARRY => INT_CARRY(281) ); ---- End FA stage ---- Begin FA stage FA_284:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(353), DATA_B => INT_CARRY(265), DATA_C => INT_CARRY(266), SAVE => INT_SUM(355), CARRY => INT_CARRY(282) ); ---- End FA stage ---- Begin FA stage FA_285:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(354), DATA_B => INT_SUM(355), DATA_C => INT_CARRY(267), SAVE => INT_SUM(356), CARRY => INT_CARRY(283) ); ---- End FA stage ---- Begin NO stage INT_SUM(357) <= INT_CARRY(268); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_286:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(356), DATA_B => INT_SUM(357), DATA_C => INT_CARRY(269), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_287:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(374), DATA_B => SUMMAND(375), DATA_C => SUMMAND(376), SAVE => INT_SUM(358), CARRY => INT_CARRY(284) ); ---- End FA stage ---- Begin FA stage FA_288:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(377), DATA_B => SUMMAND(378), DATA_C => SUMMAND(379), SAVE => INT_SUM(359), CARRY => INT_CARRY(285) ); ---- End FA stage ---- Begin FA stage FA_289:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(380), DATA_B => SUMMAND(381), DATA_C => SUMMAND(382), SAVE => INT_SUM(360), CARRY => INT_CARRY(286) ); ---- End FA stage ---- Begin FA stage FA_290:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(383), DATA_B => SUMMAND(384), DATA_C => SUMMAND(385), SAVE => INT_SUM(361), CARRY => INT_CARRY(287) ); ---- End FA stage ---- Begin FA stage FA_291:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(386), DATA_B => SUMMAND(387), DATA_C => SUMMAND(388), SAVE => INT_SUM(362), CARRY => INT_CARRY(288) ); ---- End FA stage ---- Begin NO stage INT_SUM(363) <= SUMMAND(389); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_292:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(358), DATA_B => INT_SUM(359), DATA_C => INT_SUM(360), SAVE => INT_SUM(364), CARRY => INT_CARRY(289) ); ---- End FA stage ---- Begin FA stage FA_293:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(361), DATA_B => INT_SUM(362), DATA_C => INT_SUM(363), SAVE => INT_SUM(365), CARRY => INT_CARRY(290) ); ---- End FA stage ---- Begin FA stage FA_294:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(270), DATA_B => INT_CARRY(271), DATA_C => INT_CARRY(272), SAVE => INT_SUM(366), CARRY => INT_CARRY(291) ); ---- End FA stage ---- Begin NO stage INT_SUM(367) <= INT_CARRY(273); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(368) <= INT_CARRY(274); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_295:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(364), DATA_B => INT_SUM(365), DATA_C => INT_SUM(366), SAVE => INT_SUM(369), CARRY => INT_CARRY(292) ); ---- End FA stage ---- Begin FA stage FA_296:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(367), DATA_B => INT_SUM(368), DATA_C => INT_CARRY(275), SAVE => INT_SUM(370), CARRY => INT_CARRY(293) ); ---- End FA stage ---- Begin FA stage FA_297:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(276), DATA_B => INT_CARRY(277), DATA_C => INT_CARRY(278), SAVE => INT_SUM(371), CARRY => INT_CARRY(294) ); ---- End FA stage ---- Begin FA stage FA_298:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(369), DATA_B => INT_SUM(370), DATA_C => INT_SUM(371), SAVE => INT_SUM(372), CARRY => INT_CARRY(295) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(279), DATA_B => INT_CARRY(280), SAVE => INT_SUM(373), CARRY => INT_CARRY(296) ); ---- End HA stage ---- Begin FA stage FA_299:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(372), DATA_B => INT_SUM(373), DATA_C => INT_CARRY(281), SAVE => INT_SUM(374), CARRY => INT_CARRY(297) ); ---- End FA stage ---- Begin NO stage INT_SUM(375) <= INT_CARRY(282); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_300:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(374), DATA_B => INT_SUM(375), DATA_C => INT_CARRY(283), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End FA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_301:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(390), DATA_B => SUMMAND(391), DATA_C => SUMMAND(392), SAVE => INT_SUM(376), CARRY => INT_CARRY(298) ); ---- End FA stage ---- Begin FA stage FA_302:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(393), DATA_B => SUMMAND(394), DATA_C => SUMMAND(395), SAVE => INT_SUM(377), CARRY => INT_CARRY(299) ); ---- End FA stage ---- Begin FA stage FA_303:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(396), DATA_B => SUMMAND(397), DATA_C => SUMMAND(398), SAVE => INT_SUM(378), CARRY => INT_CARRY(300) ); ---- End FA stage ---- Begin FA stage FA_304:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(399), DATA_B => SUMMAND(400), DATA_C => SUMMAND(401), SAVE => INT_SUM(379), CARRY => INT_CARRY(301) ); ---- End FA stage ---- Begin FA stage FA_305:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(402), DATA_B => SUMMAND(403), DATA_C => SUMMAND(404), SAVE => INT_SUM(380), CARRY => INT_CARRY(302) ); ---- End FA stage ---- Begin FA stage FA_306:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(376), DATA_B => INT_SUM(377), DATA_C => INT_SUM(378), SAVE => INT_SUM(381), CARRY => INT_CARRY(303) ); ---- End FA stage ---- Begin FA stage FA_307:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(379), DATA_B => INT_SUM(380), DATA_C => INT_CARRY(284), SAVE => INT_SUM(382), CARRY => INT_CARRY(304) ); ---- End FA stage ---- Begin FA stage FA_308:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(285), DATA_B => INT_CARRY(286), DATA_C => INT_CARRY(287), SAVE => INT_SUM(383), CARRY => INT_CARRY(305) ); ---- End FA stage ---- Begin NO stage INT_SUM(384) <= INT_CARRY(288); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_309:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(381), DATA_B => INT_SUM(382), DATA_C => INT_SUM(383), SAVE => INT_SUM(385), CARRY => INT_CARRY(306) ); ---- End FA stage ---- Begin FA stage FA_310:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(384), DATA_B => INT_CARRY(289), DATA_C => INT_CARRY(290), SAVE => INT_SUM(386), CARRY => INT_CARRY(307) ); ---- End FA stage ---- Begin NO stage INT_SUM(387) <= INT_CARRY(291); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_311:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(385), DATA_B => INT_SUM(386), DATA_C => INT_SUM(387), SAVE => INT_SUM(388), CARRY => INT_CARRY(308) ); ---- End FA stage ---- Begin FA stage FA_312:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(292), DATA_B => INT_CARRY(293), DATA_C => INT_CARRY(294), SAVE => INT_SUM(389), CARRY => INT_CARRY(309) ); ---- End FA stage ---- Begin FA stage FA_313:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(388), DATA_B => INT_SUM(389), DATA_C => INT_CARRY(295), SAVE => INT_SUM(390), CARRY => INT_CARRY(310) ); ---- End FA stage ---- Begin NO stage INT_SUM(391) <= INT_CARRY(296); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_314:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(390), DATA_B => INT_SUM(391), DATA_C => INT_CARRY(297), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_315:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(405), DATA_B => SUMMAND(406), DATA_C => SUMMAND(407), SAVE => INT_SUM(392), CARRY => INT_CARRY(311) ); ---- End FA stage ---- Begin FA stage FA_316:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(408), DATA_B => SUMMAND(409), DATA_C => SUMMAND(410), SAVE => INT_SUM(393), CARRY => INT_CARRY(312) ); ---- End FA stage ---- Begin FA stage FA_317:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(411), DATA_B => SUMMAND(412), DATA_C => SUMMAND(413), SAVE => INT_SUM(394), CARRY => INT_CARRY(313) ); ---- End FA stage ---- Begin FA stage FA_318:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(414), DATA_B => SUMMAND(415), DATA_C => SUMMAND(416), SAVE => INT_SUM(395), CARRY => INT_CARRY(314) ); ---- End FA stage ---- Begin FA stage FA_319:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(417), DATA_B => SUMMAND(418), DATA_C => SUMMAND(419), SAVE => INT_SUM(396), CARRY => INT_CARRY(315) ); ---- End FA stage ---- Begin FA stage FA_320:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(392), DATA_B => INT_SUM(393), DATA_C => INT_SUM(394), SAVE => INT_SUM(397), CARRY => INT_CARRY(316) ); ---- End FA stage ---- Begin FA stage FA_321:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(395), DATA_B => INT_SUM(396), DATA_C => INT_CARRY(298), SAVE => INT_SUM(398), CARRY => INT_CARRY(317) ); ---- End FA stage ---- Begin FA stage FA_322:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(299), DATA_B => INT_CARRY(300), DATA_C => INT_CARRY(301), SAVE => INT_SUM(399), CARRY => INT_CARRY(318) ); ---- End FA stage ---- Begin NO stage INT_SUM(400) <= INT_CARRY(302); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_323:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(397), DATA_B => INT_SUM(398), DATA_C => INT_SUM(399), SAVE => INT_SUM(401), CARRY => INT_CARRY(319) ); ---- End FA stage ---- Begin FA stage FA_324:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(400), DATA_B => INT_CARRY(303), DATA_C => INT_CARRY(304), SAVE => INT_SUM(402), CARRY => INT_CARRY(320) ); ---- End FA stage ---- Begin NO stage INT_SUM(403) <= INT_CARRY(305); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_325:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(401), DATA_B => INT_SUM(402), DATA_C => INT_SUM(403), SAVE => INT_SUM(404), CARRY => INT_CARRY(321) ); ---- End FA stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(306), DATA_B => INT_CARRY(307), SAVE => INT_SUM(405), CARRY => INT_CARRY(322) ); ---- End HA stage ---- Begin FA stage FA_326:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(404), DATA_B => INT_SUM(405), DATA_C => INT_CARRY(308), SAVE => INT_SUM(406), CARRY => INT_CARRY(323) ); ---- End FA stage ---- Begin NO stage INT_SUM(407) <= INT_CARRY(309); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_327:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(406), DATA_B => INT_SUM(407), DATA_C => INT_CARRY(310), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End FA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin FA stage FA_328:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(420), DATA_B => SUMMAND(421), DATA_C => SUMMAND(422), SAVE => INT_SUM(408), CARRY => INT_CARRY(324) ); ---- End FA stage ---- Begin FA stage FA_329:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(423), DATA_B => SUMMAND(424), DATA_C => SUMMAND(425), SAVE => INT_SUM(409), CARRY => INT_CARRY(325) ); ---- End FA stage ---- Begin FA stage FA_330:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(426), DATA_B => SUMMAND(427), DATA_C => SUMMAND(428), SAVE => INT_SUM(410), CARRY => INT_CARRY(326) ); ---- End FA stage ---- Begin FA stage FA_331:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(429), DATA_B => SUMMAND(430), DATA_C => SUMMAND(431), SAVE => INT_SUM(411), CARRY => INT_CARRY(327) ); ---- End FA stage ---- Begin HA stage HA_35:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(432), DATA_B => SUMMAND(433), SAVE => INT_SUM(412), CARRY => INT_CARRY(328) ); ---- End HA stage ---- Begin FA stage FA_332:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(408), DATA_B => INT_SUM(409), DATA_C => INT_SUM(410), SAVE => INT_SUM(413), CARRY => INT_CARRY(329) ); ---- End FA stage ---- Begin FA stage FA_333:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(411), DATA_B => INT_SUM(412), DATA_C => INT_CARRY(311), SAVE => INT_SUM(414), CARRY => INT_CARRY(330) ); ---- End FA stage ---- Begin FA stage FA_334:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(312), DATA_B => INT_CARRY(313), DATA_C => INT_CARRY(314), SAVE => INT_SUM(415), CARRY => INT_CARRY(331) ); ---- End FA stage ---- Begin NO stage INT_SUM(416) <= INT_CARRY(315); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_335:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(413), DATA_B => INT_SUM(414), DATA_C => INT_SUM(415), SAVE => INT_SUM(417), CARRY => INT_CARRY(332) ); ---- End FA stage ---- Begin FA stage FA_336:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(416), DATA_B => INT_CARRY(316), DATA_C => INT_CARRY(317), SAVE => INT_SUM(418), CARRY => INT_CARRY(333) ); ---- End FA stage ---- Begin NO stage INT_SUM(419) <= INT_CARRY(318); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_337:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(417), DATA_B => INT_SUM(418), DATA_C => INT_SUM(419), SAVE => INT_SUM(420), CARRY => INT_CARRY(334) ); ---- End FA stage ---- Begin HA stage HA_36:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(319), DATA_B => INT_CARRY(320), SAVE => INT_SUM(421), CARRY => INT_CARRY(335) ); ---- End HA stage ---- Begin FA stage FA_338:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(420), DATA_B => INT_SUM(421), DATA_C => INT_CARRY(321), SAVE => INT_SUM(422), CARRY => INT_CARRY(336) ); ---- End FA stage ---- Begin NO stage INT_SUM(423) <= INT_CARRY(322); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_339:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(422), DATA_B => INT_SUM(423), DATA_C => INT_CARRY(323), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin FA stage FA_340:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(434), DATA_B => SUMMAND(435), DATA_C => SUMMAND(436), SAVE => INT_SUM(424), CARRY => INT_CARRY(337) ); ---- End FA stage ---- Begin FA stage FA_341:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(437), DATA_B => SUMMAND(438), DATA_C => SUMMAND(439), SAVE => INT_SUM(425), CARRY => INT_CARRY(338) ); ---- End FA stage ---- Begin FA stage FA_342:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(440), DATA_B => SUMMAND(441), DATA_C => SUMMAND(442), SAVE => INT_SUM(426), CARRY => INT_CARRY(339) ); ---- End FA stage ---- Begin FA stage FA_343:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(443), DATA_B => SUMMAND(444), DATA_C => SUMMAND(445), SAVE => INT_SUM(427), CARRY => INT_CARRY(340) ); ---- End FA stage ---- Begin HA stage HA_37:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(446), DATA_B => SUMMAND(447), SAVE => INT_SUM(428), CARRY => INT_CARRY(341) ); ---- End HA stage ---- Begin FA stage FA_344:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(424), DATA_B => INT_SUM(425), DATA_C => INT_SUM(426), SAVE => INT_SUM(429), CARRY => INT_CARRY(342) ); ---- End FA stage ---- Begin FA stage FA_345:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(427), DATA_B => INT_SUM(428), DATA_C => INT_CARRY(324), SAVE => INT_SUM(430), CARRY => INT_CARRY(343) ); ---- End FA stage ---- Begin FA stage FA_346:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(325), DATA_B => INT_CARRY(326), DATA_C => INT_CARRY(327), SAVE => INT_SUM(431), CARRY => INT_CARRY(344) ); ---- End FA stage ---- Begin NO stage INT_SUM(432) <= INT_CARRY(328); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_347:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(429), DATA_B => INT_SUM(430), DATA_C => INT_SUM(431), SAVE => INT_SUM(433), CARRY => INT_CARRY(345) ); ---- End FA stage ---- Begin FA stage FA_348:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(432), DATA_B => INT_CARRY(329), DATA_C => INT_CARRY(330), SAVE => INT_SUM(434), CARRY => INT_CARRY(346) ); ---- End FA stage ---- Begin NO stage INT_SUM(435) <= INT_CARRY(331); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_349:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(433), DATA_B => INT_SUM(434), DATA_C => INT_SUM(435), SAVE => INT_SUM(436), CARRY => INT_CARRY(347) ); ---- End FA stage ---- Begin HA stage HA_38:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(332), DATA_B => INT_CARRY(333), SAVE => INT_SUM(437), CARRY => INT_CARRY(348) ); ---- End HA stage ---- Begin FA stage FA_350:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(436), DATA_B => INT_SUM(437), DATA_C => INT_CARRY(334), SAVE => INT_SUM(438), CARRY => INT_CARRY(349) ); ---- End FA stage ---- Begin NO stage INT_SUM(439) <= INT_CARRY(335); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_351:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(438), DATA_B => INT_SUM(439), DATA_C => INT_CARRY(336), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End FA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin FA stage FA_352:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(448), DATA_B => SUMMAND(449), DATA_C => SUMMAND(450), SAVE => INT_SUM(440), CARRY => INT_CARRY(350) ); ---- End FA stage ---- Begin FA stage FA_353:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(451), DATA_B => SUMMAND(452), DATA_C => SUMMAND(453), SAVE => INT_SUM(441), CARRY => INT_CARRY(351) ); ---- End FA stage ---- Begin FA stage FA_354:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(454), DATA_B => SUMMAND(455), DATA_C => SUMMAND(456), SAVE => INT_SUM(442), CARRY => INT_CARRY(352) ); ---- End FA stage ---- Begin FA stage FA_355:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(457), DATA_B => SUMMAND(458), DATA_C => SUMMAND(459), SAVE => INT_SUM(443), CARRY => INT_CARRY(353) ); ---- End FA stage ---- Begin NO stage INT_SUM(444) <= SUMMAND(460); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_356:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(440), DATA_B => INT_SUM(441), DATA_C => INT_SUM(442), SAVE => INT_SUM(445), CARRY => INT_CARRY(354) ); ---- End FA stage ---- Begin FA stage FA_357:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(443), DATA_B => INT_SUM(444), DATA_C => INT_CARRY(337), SAVE => INT_SUM(446), CARRY => INT_CARRY(355) ); ---- End FA stage ---- Begin FA stage FA_358:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(338), DATA_B => INT_CARRY(339), DATA_C => INT_CARRY(340), SAVE => INT_SUM(447), CARRY => INT_CARRY(356) ); ---- End FA stage ---- Begin NO stage INT_SUM(448) <= INT_CARRY(341); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_359:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(445), DATA_B => INT_SUM(446), DATA_C => INT_SUM(447), SAVE => INT_SUM(449), CARRY => INT_CARRY(357) ); ---- End FA stage ---- Begin FA stage FA_360:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(448), DATA_B => INT_CARRY(342), DATA_C => INT_CARRY(343), SAVE => INT_SUM(450), CARRY => INT_CARRY(358) ); ---- End FA stage ---- Begin NO stage INT_SUM(451) <= INT_CARRY(344); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_361:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(449), DATA_B => INT_SUM(450), DATA_C => INT_SUM(451), SAVE => INT_SUM(452), CARRY => INT_CARRY(359) ); ---- End FA stage ---- Begin HA stage HA_39:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(345), DATA_B => INT_CARRY(346), SAVE => INT_SUM(453), CARRY => INT_CARRY(360) ); ---- End HA stage ---- Begin FA stage FA_362:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(452), DATA_B => INT_SUM(453), DATA_C => INT_CARRY(347), SAVE => INT_SUM(454), CARRY => INT_CARRY(361) ); ---- End FA stage ---- Begin NO stage INT_SUM(455) <= INT_CARRY(348); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_363:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(454), DATA_B => INT_SUM(455), DATA_C => INT_CARRY(349), SAVE => SUM(42), CARRY => CARRY(42) ); ---- End FA stage -- End WT-branch 43 -- Begin WT-branch 44 ---- Begin FA stage FA_364:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(461), DATA_B => SUMMAND(462), DATA_C => SUMMAND(463), SAVE => INT_SUM(456), CARRY => INT_CARRY(362) ); ---- End FA stage ---- Begin FA stage FA_365:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(464), DATA_B => SUMMAND(465), DATA_C => SUMMAND(466), SAVE => INT_SUM(457), CARRY => INT_CARRY(363) ); ---- End FA stage ---- Begin FA stage FA_366:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(467), DATA_B => SUMMAND(468), DATA_C => SUMMAND(469), SAVE => INT_SUM(458), CARRY => INT_CARRY(364) ); ---- End FA stage ---- Begin FA stage FA_367:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(470), DATA_B => SUMMAND(471), DATA_C => SUMMAND(472), SAVE => INT_SUM(459), CARRY => INT_CARRY(365) ); ---- End FA stage ---- Begin FA stage FA_368:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(473), DATA_B => INT_CARRY(350), DATA_C => INT_CARRY(351), SAVE => INT_SUM(460), CARRY => INT_CARRY(366) ); ---- End FA stage ---- Begin NO stage INT_SUM(461) <= INT_CARRY(352); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(462) <= INT_CARRY(353); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_369:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(456), DATA_B => INT_SUM(457), DATA_C => INT_SUM(458), SAVE => INT_SUM(463), CARRY => INT_CARRY(367) ); ---- End FA stage ---- Begin FA stage FA_370:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(459), DATA_B => INT_SUM(460), DATA_C => INT_SUM(461), SAVE => INT_SUM(464), CARRY => INT_CARRY(368) ); ---- End FA stage ---- Begin FA stage FA_371:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(462), DATA_B => INT_CARRY(354), DATA_C => INT_CARRY(355), SAVE => INT_SUM(465), CARRY => INT_CARRY(369) ); ---- End FA stage ---- Begin NO stage INT_SUM(466) <= INT_CARRY(356); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_372:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(463), DATA_B => INT_SUM(464), DATA_C => INT_SUM(465), SAVE => INT_SUM(467), CARRY => INT_CARRY(370) ); ---- End FA stage ---- Begin FA stage FA_373:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(466), DATA_B => INT_CARRY(357), DATA_C => INT_CARRY(358), SAVE => INT_SUM(468), CARRY => INT_CARRY(371) ); ---- End FA stage ---- Begin FA stage FA_374:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(467), DATA_B => INT_SUM(468), DATA_C => INT_CARRY(359), SAVE => INT_SUM(469), CARRY => INT_CARRY(372) ); ---- End FA stage ---- Begin NO stage INT_SUM(470) <= INT_CARRY(360); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_375:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(469), DATA_B => INT_SUM(470), DATA_C => INT_CARRY(361), SAVE => SUM(43), CARRY => CARRY(43) ); ---- End FA stage -- End WT-branch 44 -- Begin WT-branch 45 ---- Begin FA stage FA_376:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(474), DATA_B => SUMMAND(475), DATA_C => SUMMAND(476), SAVE => INT_SUM(471), CARRY => INT_CARRY(373) ); ---- End FA stage ---- Begin FA stage FA_377:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(477), DATA_B => SUMMAND(478), DATA_C => SUMMAND(479), SAVE => INT_SUM(472), CARRY => INT_CARRY(374) ); ---- End FA stage ---- Begin FA stage FA_378:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(480), DATA_B => SUMMAND(481), DATA_C => SUMMAND(482), SAVE => INT_SUM(473), CARRY => INT_CARRY(375) ); ---- End FA stage ---- Begin FA stage FA_379:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(483), DATA_B => SUMMAND(484), DATA_C => SUMMAND(485), SAVE => INT_SUM(474), CARRY => INT_CARRY(376) ); ---- End FA stage ---- Begin FA stage FA_380:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(471), DATA_B => INT_SUM(472), DATA_C => INT_SUM(473), SAVE => INT_SUM(475), CARRY => INT_CARRY(377) ); ---- End FA stage ---- Begin FA stage FA_381:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(474), DATA_B => INT_CARRY(362), DATA_C => INT_CARRY(363), SAVE => INT_SUM(476), CARRY => INT_CARRY(378) ); ---- End FA stage ---- Begin FA stage FA_382:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(364), DATA_B => INT_CARRY(365), DATA_C => INT_CARRY(366), SAVE => INT_SUM(477), CARRY => INT_CARRY(379) ); ---- End FA stage ---- Begin FA stage FA_383:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(475), DATA_B => INT_SUM(476), DATA_C => INT_SUM(477), SAVE => INT_SUM(478), CARRY => INT_CARRY(380) ); ---- End FA stage ---- Begin FA stage FA_384:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(367), DATA_B => INT_CARRY(368), DATA_C => INT_CARRY(369), SAVE => INT_SUM(479), CARRY => INT_CARRY(381) ); ---- End FA stage ---- Begin FA stage FA_385:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(478), DATA_B => INT_SUM(479), DATA_C => INT_CARRY(370), SAVE => INT_SUM(480), CARRY => INT_CARRY(382) ); ---- End FA stage ---- Begin NO stage INT_SUM(481) <= INT_CARRY(371); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_386:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(480), DATA_B => INT_SUM(481), DATA_C => INT_CARRY(372), SAVE => SUM(44), CARRY => CARRY(44) ); ---- End FA stage -- End WT-branch 45 -- Begin WT-branch 46 ---- Begin FA stage FA_387:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(486), DATA_B => SUMMAND(487), DATA_C => SUMMAND(488), SAVE => INT_SUM(482), CARRY => INT_CARRY(383) ); ---- End FA stage ---- Begin FA stage FA_388:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(489), DATA_B => SUMMAND(490), DATA_C => SUMMAND(491), SAVE => INT_SUM(483), CARRY => INT_CARRY(384) ); ---- End FA stage ---- Begin FA stage FA_389:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(492), DATA_B => SUMMAND(493), DATA_C => SUMMAND(494), SAVE => INT_SUM(484), CARRY => INT_CARRY(385) ); ---- End FA stage ---- Begin FA stage FA_390:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(495), DATA_B => SUMMAND(496), DATA_C => SUMMAND(497), SAVE => INT_SUM(485), CARRY => INT_CARRY(386) ); ---- End FA stage ---- Begin FA stage FA_391:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(482), DATA_B => INT_SUM(483), DATA_C => INT_SUM(484), SAVE => INT_SUM(486), CARRY => INT_CARRY(387) ); ---- End FA stage ---- Begin FA stage FA_392:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(485), DATA_B => INT_CARRY(373), DATA_C => INT_CARRY(374), SAVE => INT_SUM(487), CARRY => INT_CARRY(388) ); ---- End FA stage ---- Begin HA stage HA_40:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(375), DATA_B => INT_CARRY(376), SAVE => INT_SUM(488), CARRY => INT_CARRY(389) ); ---- End HA stage ---- Begin FA stage FA_393:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(486), DATA_B => INT_SUM(487), DATA_C => INT_SUM(488), SAVE => INT_SUM(489), CARRY => INT_CARRY(390) ); ---- End FA stage ---- Begin FA stage FA_394:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(377), DATA_B => INT_CARRY(378), DATA_C => INT_CARRY(379), SAVE => INT_SUM(490), CARRY => INT_CARRY(391) ); ---- End FA stage ---- Begin FA stage FA_395:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(489), DATA_B => INT_SUM(490), DATA_C => INT_CARRY(380), SAVE => INT_SUM(491), CARRY => INT_CARRY(392) ); ---- End FA stage ---- Begin NO stage INT_SUM(492) <= INT_CARRY(381); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_396:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(491), DATA_B => INT_SUM(492), DATA_C => INT_CARRY(382), SAVE => SUM(45), CARRY => CARRY(45) ); ---- End FA stage -- End WT-branch 46 -- Begin WT-branch 47 ---- Begin FA stage FA_397:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(498), DATA_B => SUMMAND(499), DATA_C => SUMMAND(500), SAVE => INT_SUM(493), CARRY => INT_CARRY(393) ); ---- End FA stage ---- Begin FA stage FA_398:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(501), DATA_B => SUMMAND(502), DATA_C => SUMMAND(503), SAVE => INT_SUM(494), CARRY => INT_CARRY(394) ); ---- End FA stage ---- Begin FA stage FA_399:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(504), DATA_B => SUMMAND(505), DATA_C => SUMMAND(506), SAVE => INT_SUM(495), CARRY => INT_CARRY(395) ); ---- End FA stage ---- Begin NO stage INT_SUM(496) <= SUMMAND(507); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(497) <= SUMMAND(508); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_400:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(493), DATA_B => INT_SUM(494), DATA_C => INT_SUM(495), SAVE => INT_SUM(498), CARRY => INT_CARRY(396) ); ---- End FA stage ---- Begin FA stage FA_401:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(496), DATA_B => INT_SUM(497), DATA_C => INT_CARRY(383), SAVE => INT_SUM(499), CARRY => INT_CARRY(397) ); ---- End FA stage ---- Begin FA stage FA_402:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(384), DATA_B => INT_CARRY(385), DATA_C => INT_CARRY(386), SAVE => INT_SUM(500), CARRY => INT_CARRY(398) ); ---- End FA stage ---- Begin FA stage FA_403:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(498), DATA_B => INT_SUM(499), DATA_C => INT_SUM(500), SAVE => INT_SUM(501), CARRY => INT_CARRY(399) ); ---- End FA stage ---- Begin FA stage FA_404:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(387), DATA_B => INT_CARRY(388), DATA_C => INT_CARRY(389), SAVE => INT_SUM(502), CARRY => INT_CARRY(400) ); ---- End FA stage ---- Begin FA stage FA_405:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(501), DATA_B => INT_SUM(502), DATA_C => INT_CARRY(390), SAVE => INT_SUM(503), CARRY => INT_CARRY(401) ); ---- End FA stage ---- Begin NO stage INT_SUM(504) <= INT_CARRY(391); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_406:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(503), DATA_B => INT_SUM(504), DATA_C => INT_CARRY(392), SAVE => SUM(46), CARRY => CARRY(46) ); ---- End FA stage -- End WT-branch 47 -- Begin WT-branch 48 ---- Begin FA stage FA_407:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(509), DATA_B => SUMMAND(510), DATA_C => SUMMAND(511), SAVE => INT_SUM(505), CARRY => INT_CARRY(402) ); ---- End FA stage ---- Begin FA stage FA_408:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(512), DATA_B => SUMMAND(513), DATA_C => SUMMAND(514), SAVE => INT_SUM(506), CARRY => INT_CARRY(403) ); ---- End FA stage ---- Begin FA stage FA_409:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(515), DATA_B => SUMMAND(516), DATA_C => SUMMAND(517), SAVE => INT_SUM(507), CARRY => INT_CARRY(404) ); ---- End FA stage ---- Begin HA stage HA_41:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(518), DATA_B => SUMMAND(519), SAVE => INT_SUM(508), CARRY => INT_CARRY(405) ); ---- End HA stage ---- Begin FA stage FA_410:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(505), DATA_B => INT_SUM(506), DATA_C => INT_SUM(507), SAVE => INT_SUM(509), CARRY => INT_CARRY(406) ); ---- End FA stage ---- Begin FA stage FA_411:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(508), DATA_B => INT_CARRY(393), DATA_C => INT_CARRY(394), SAVE => INT_SUM(510), CARRY => INT_CARRY(407) ); ---- End FA stage ---- Begin NO stage INT_SUM(511) <= INT_CARRY(395); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_412:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(509), DATA_B => INT_SUM(510), DATA_C => INT_SUM(511), SAVE => INT_SUM(512), CARRY => INT_CARRY(408) ); ---- End FA stage ---- Begin FA stage FA_413:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(396), DATA_B => INT_CARRY(397), DATA_C => INT_CARRY(398), SAVE => INT_SUM(513), CARRY => INT_CARRY(409) ); ---- End FA stage ---- Begin FA stage FA_414:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(512), DATA_B => INT_SUM(513), DATA_C => INT_CARRY(399), SAVE => INT_SUM(514), CARRY => INT_CARRY(410) ); ---- End FA stage ---- Begin NO stage INT_SUM(515) <= INT_CARRY(400); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_415:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(514), DATA_B => INT_SUM(515), DATA_C => INT_CARRY(401), SAVE => SUM(47), CARRY => CARRY(47) ); ---- End FA stage -- End WT-branch 48 -- Begin WT-branch 49 ---- Begin FA stage FA_416:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(520), DATA_B => SUMMAND(521), DATA_C => SUMMAND(522), SAVE => INT_SUM(516), CARRY => INT_CARRY(411) ); ---- End FA stage ---- Begin FA stage FA_417:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(523), DATA_B => SUMMAND(524), DATA_C => SUMMAND(525), SAVE => INT_SUM(517), CARRY => INT_CARRY(412) ); ---- End FA stage ---- Begin FA stage FA_418:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(526), DATA_B => SUMMAND(527), DATA_C => SUMMAND(528), SAVE => INT_SUM(518), CARRY => INT_CARRY(413) ); ---- End FA stage ---- Begin NO stage INT_SUM(519) <= SUMMAND(529); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_419:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(516), DATA_B => INT_SUM(517), DATA_C => INT_SUM(518), SAVE => INT_SUM(520), CARRY => INT_CARRY(414) ); ---- End FA stage ---- Begin FA stage FA_420:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(519), DATA_B => INT_CARRY(402), DATA_C => INT_CARRY(403), SAVE => INT_SUM(521), CARRY => INT_CARRY(415) ); ---- End FA stage ---- Begin NO stage INT_SUM(522) <= INT_CARRY(404); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(523) <= INT_CARRY(405); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_421:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(520), DATA_B => INT_SUM(521), DATA_C => INT_SUM(522), SAVE => INT_SUM(524), CARRY => INT_CARRY(416) ); ---- End FA stage ---- Begin FA stage FA_422:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(523), DATA_B => INT_CARRY(406), DATA_C => INT_CARRY(407), SAVE => INT_SUM(525), CARRY => INT_CARRY(417) ); ---- End FA stage ---- Begin FA stage FA_423:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(524), DATA_B => INT_SUM(525), DATA_C => INT_CARRY(408), SAVE => INT_SUM(526), CARRY => INT_CARRY(418) ); ---- End FA stage ---- Begin NO stage INT_SUM(527) <= INT_CARRY(409); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_424:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(526), DATA_B => INT_SUM(527), DATA_C => INT_CARRY(410), SAVE => SUM(48), CARRY => CARRY(48) ); ---- End FA stage -- End WT-branch 49 -- Begin WT-branch 50 ---- Begin FA stage FA_425:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(530), DATA_B => SUMMAND(531), DATA_C => SUMMAND(532), SAVE => INT_SUM(528), CARRY => INT_CARRY(419) ); ---- End FA stage ---- Begin FA stage FA_426:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(533), DATA_B => SUMMAND(534), DATA_C => SUMMAND(535), SAVE => INT_SUM(529), CARRY => INT_CARRY(420) ); ---- End FA stage ---- Begin FA stage FA_427:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(536), DATA_B => SUMMAND(537), DATA_C => SUMMAND(538), SAVE => INT_SUM(530), CARRY => INT_CARRY(421) ); ---- End FA stage ---- Begin NO stage INT_SUM(531) <= SUMMAND(539); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_428:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(528), DATA_B => INT_SUM(529), DATA_C => INT_SUM(530), SAVE => INT_SUM(532), CARRY => INT_CARRY(422) ); ---- End FA stage ---- Begin FA stage FA_429:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(531), DATA_B => INT_CARRY(411), DATA_C => INT_CARRY(412), SAVE => INT_SUM(533), CARRY => INT_CARRY(423) ); ---- End FA stage ---- Begin NO stage INT_SUM(534) <= INT_CARRY(413); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_430:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(532), DATA_B => INT_SUM(533), DATA_C => INT_SUM(534), SAVE => INT_SUM(535), CARRY => INT_CARRY(424) ); ---- End FA stage ---- Begin HA stage HA_42:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(414), DATA_B => INT_CARRY(415), SAVE => INT_SUM(536), CARRY => INT_CARRY(425) ); ---- End HA stage ---- Begin FA stage FA_431:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(535), DATA_B => INT_SUM(536), DATA_C => INT_CARRY(416), SAVE => INT_SUM(537), CARRY => INT_CARRY(426) ); ---- End FA stage ---- Begin NO stage INT_SUM(538) <= INT_CARRY(417); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_432:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(537), DATA_B => INT_SUM(538), DATA_C => INT_CARRY(418), SAVE => SUM(49), CARRY => CARRY(49) ); ---- End FA stage -- End WT-branch 50 -- Begin WT-branch 51 ---- Begin FA stage FA_433:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(540), DATA_B => SUMMAND(541), DATA_C => SUMMAND(542), SAVE => INT_SUM(539), CARRY => INT_CARRY(427) ); ---- End FA stage ---- Begin FA stage FA_434:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(543), DATA_B => SUMMAND(544), DATA_C => SUMMAND(545), SAVE => INT_SUM(540), CARRY => INT_CARRY(428) ); ---- End FA stage ---- Begin FA stage FA_435:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(546), DATA_B => SUMMAND(547), DATA_C => SUMMAND(548), SAVE => INT_SUM(541), CARRY => INT_CARRY(429) ); ---- End FA stage ---- Begin FA stage FA_436:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(539), DATA_B => INT_SUM(540), DATA_C => INT_SUM(541), SAVE => INT_SUM(542), CARRY => INT_CARRY(430) ); ---- End FA stage ---- Begin FA stage FA_437:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(419), DATA_B => INT_CARRY(420), DATA_C => INT_CARRY(421), SAVE => INT_SUM(543), CARRY => INT_CARRY(431) ); ---- End FA stage ---- Begin FA stage FA_438:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(542), DATA_B => INT_SUM(543), DATA_C => INT_CARRY(422), SAVE => INT_SUM(544), CARRY => INT_CARRY(432) ); ---- End FA stage ---- Begin NO stage INT_SUM(545) <= INT_CARRY(423); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_439:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(544), DATA_B => INT_SUM(545), DATA_C => INT_CARRY(424), SAVE => INT_SUM(546), CARRY => INT_CARRY(433) ); ---- End FA stage ---- Begin NO stage INT_SUM(547) <= INT_CARRY(425); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_440:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(546), DATA_B => INT_SUM(547), DATA_C => INT_CARRY(426), SAVE => SUM(50), CARRY => CARRY(50) ); ---- End FA stage -- End WT-branch 51 -- Begin WT-branch 52 ---- Begin FA stage FA_441:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(549), DATA_B => SUMMAND(550), DATA_C => SUMMAND(551), SAVE => INT_SUM(548), CARRY => INT_CARRY(434) ); ---- End FA stage ---- Begin FA stage FA_442:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(552), DATA_B => SUMMAND(553), DATA_C => SUMMAND(554), SAVE => INT_SUM(549), CARRY => INT_CARRY(435) ); ---- End FA stage ---- Begin FA stage FA_443:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(555), DATA_B => SUMMAND(556), DATA_C => SUMMAND(557), SAVE => INT_SUM(550), CARRY => INT_CARRY(436) ); ---- End FA stage ---- Begin FA stage FA_444:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(548), DATA_B => INT_SUM(549), DATA_C => INT_SUM(550), SAVE => INT_SUM(551), CARRY => INT_CARRY(437) ); ---- End FA stage ---- Begin FA stage FA_445:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(427), DATA_B => INT_CARRY(428), DATA_C => INT_CARRY(429), SAVE => INT_SUM(552), CARRY => INT_CARRY(438) ); ---- End FA stage ---- Begin FA stage FA_446:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(551), DATA_B => INT_SUM(552), DATA_C => INT_CARRY(430), SAVE => INT_SUM(553), CARRY => INT_CARRY(439) ); ---- End FA stage ---- Begin NO stage INT_SUM(554) <= INT_CARRY(431); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_447:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(553), DATA_B => INT_SUM(554), DATA_C => INT_CARRY(432), SAVE => INT_SUM(555), CARRY => INT_CARRY(440) ); ---- End FA stage ---- Begin HA stage HA_43:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(555), DATA_B => INT_CARRY(433), SAVE => SUM(51), CARRY => CARRY(51) ); ---- End HA stage -- End WT-branch 52 -- Begin WT-branch 53 ---- Begin FA stage FA_448:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(558), DATA_B => SUMMAND(559), DATA_C => SUMMAND(560), SAVE => INT_SUM(556), CARRY => INT_CARRY(441) ); ---- End FA stage ---- Begin FA stage FA_449:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(561), DATA_B => SUMMAND(562), DATA_C => SUMMAND(563), SAVE => INT_SUM(557), CARRY => INT_CARRY(442) ); ---- End FA stage ---- Begin FA stage FA_450:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(564), DATA_B => SUMMAND(565), DATA_C => INT_CARRY(434), SAVE => INT_SUM(558), CARRY => INT_CARRY(443) ); ---- End FA stage ---- Begin HA stage HA_44:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(435), DATA_B => INT_CARRY(436), SAVE => INT_SUM(559), CARRY => INT_CARRY(444) ); ---- End HA stage ---- Begin FA stage FA_451:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(556), DATA_B => INT_SUM(557), DATA_C => INT_SUM(558), SAVE => INT_SUM(560), CARRY => INT_CARRY(445) ); ---- End FA stage ---- Begin FA stage FA_452:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(559), DATA_B => INT_CARRY(437), DATA_C => INT_CARRY(438), SAVE => INT_SUM(561), CARRY => INT_CARRY(446) ); ---- End FA stage ---- Begin FA stage FA_453:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(560), DATA_B => INT_SUM(561), DATA_C => INT_CARRY(439), SAVE => INT_SUM(562), CARRY => INT_CARRY(447) ); ---- End FA stage ---- Begin HA stage HA_45:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(562), DATA_B => INT_CARRY(440), SAVE => SUM(52), CARRY => CARRY(52) ); ---- End HA stage -- End WT-branch 53 -- Begin WT-branch 54 ---- Begin FA stage FA_454:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(566), DATA_B => SUMMAND(567), DATA_C => SUMMAND(568), SAVE => INT_SUM(563), CARRY => INT_CARRY(448) ); ---- End FA stage ---- Begin FA stage FA_455:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(569), DATA_B => SUMMAND(570), DATA_C => SUMMAND(571), SAVE => INT_SUM(564), CARRY => INT_CARRY(449) ); ---- End FA stage ---- Begin NO stage INT_SUM(565) <= SUMMAND(572); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(566) <= SUMMAND(573); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_456:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(563), DATA_B => INT_SUM(564), DATA_C => INT_SUM(565), SAVE => INT_SUM(567), CARRY => INT_CARRY(450) ); ---- End FA stage ---- Begin NO stage INT_SUM(568) <= INT_SUM(566); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_457:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(567), DATA_B => INT_SUM(568), DATA_C => INT_CARRY(441), SAVE => INT_SUM(569), CARRY => INT_CARRY(451) ); ---- End FA stage ---- Begin FA stage FA_458:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(442), DATA_B => INT_CARRY(443), DATA_C => INT_CARRY(444), SAVE => INT_SUM(570), CARRY => INT_CARRY(452) ); ---- End FA stage ---- Begin FA stage FA_459:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(569), DATA_B => INT_SUM(570), DATA_C => INT_CARRY(445), SAVE => INT_SUM(571), CARRY => INT_CARRY(453) ); ---- End FA stage ---- Begin NO stage INT_SUM(572) <= INT_CARRY(446); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_460:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(571), DATA_B => INT_SUM(572), DATA_C => INT_CARRY(447), SAVE => SUM(53), CARRY => CARRY(53) ); ---- End FA stage -- End WT-branch 54 -- Begin WT-branch 55 ---- Begin FA stage FA_461:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(574), DATA_B => SUMMAND(575), DATA_C => SUMMAND(576), SAVE => INT_SUM(573), CARRY => INT_CARRY(454) ); ---- End FA stage ---- Begin FA stage FA_462:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(577), DATA_B => SUMMAND(578), DATA_C => SUMMAND(579), SAVE => INT_SUM(574), CARRY => INT_CARRY(455) ); ---- End FA stage ---- Begin FA stage FA_463:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(580), DATA_B => INT_CARRY(448), DATA_C => INT_CARRY(449), SAVE => INT_SUM(575), CARRY => INT_CARRY(456) ); ---- End FA stage ---- Begin FA stage FA_464:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(573), DATA_B => INT_SUM(574), DATA_C => INT_SUM(575), SAVE => INT_SUM(576), CARRY => INT_CARRY(457) ); ---- End FA stage ---- Begin NO stage INT_SUM(577) <= INT_CARRY(450); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_465:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(576), DATA_B => INT_SUM(577), DATA_C => INT_CARRY(451), SAVE => INT_SUM(578), CARRY => INT_CARRY(458) ); ---- End FA stage ---- Begin NO stage INT_SUM(579) <= INT_CARRY(452); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_466:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(578), DATA_B => INT_SUM(579), DATA_C => INT_CARRY(453), SAVE => SUM(54), CARRY => CARRY(54) ); ---- End FA stage -- End WT-branch 55 -- Begin WT-branch 56 ---- Begin FA stage FA_467:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(581), DATA_B => SUMMAND(582), DATA_C => SUMMAND(583), SAVE => INT_SUM(580), CARRY => INT_CARRY(459) ); ---- End FA stage ---- Begin FA stage FA_468:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(584), DATA_B => SUMMAND(585), DATA_C => SUMMAND(586), SAVE => INT_SUM(581), CARRY => INT_CARRY(460) ); ---- End FA stage ---- Begin NO stage INT_SUM(582) <= SUMMAND(587); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_469:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(580), DATA_B => INT_SUM(581), DATA_C => INT_SUM(582), SAVE => INT_SUM(583), CARRY => INT_CARRY(461) ); ---- End FA stage ---- Begin FA stage FA_470:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(454), DATA_B => INT_CARRY(455), DATA_C => INT_CARRY(456), SAVE => INT_SUM(584), CARRY => INT_CARRY(462) ); ---- End FA stage ---- Begin FA stage FA_471:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(583), DATA_B => INT_SUM(584), DATA_C => INT_CARRY(457), SAVE => INT_SUM(585), CARRY => INT_CARRY(463) ); ---- End FA stage ---- Begin HA stage HA_46:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(585), DATA_B => INT_CARRY(458), SAVE => SUM(55), CARRY => CARRY(55) ); ---- End HA stage -- End WT-branch 56 -- Begin WT-branch 57 ---- Begin FA stage FA_472:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(588), DATA_B => SUMMAND(589), DATA_C => SUMMAND(590), SAVE => INT_SUM(586), CARRY => INT_CARRY(464) ); ---- End FA stage ---- Begin FA stage FA_473:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(591), DATA_B => SUMMAND(592), DATA_C => SUMMAND(593), SAVE => INT_SUM(587), CARRY => INT_CARRY(465) ); ---- End FA stage ---- Begin FA stage FA_474:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(586), DATA_B => INT_SUM(587), DATA_C => INT_CARRY(459), SAVE => INT_SUM(588), CARRY => INT_CARRY(466) ); ---- End FA stage ---- Begin NO stage INT_SUM(589) <= INT_CARRY(460); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_475:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(588), DATA_B => INT_SUM(589), DATA_C => INT_CARRY(461), SAVE => INT_SUM(590), CARRY => INT_CARRY(467) ); ---- End FA stage ---- Begin NO stage INT_SUM(591) <= INT_CARRY(462); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_476:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(590), DATA_B => INT_SUM(591), DATA_C => INT_CARRY(463), SAVE => SUM(56), CARRY => CARRY(56) ); ---- End FA stage -- End WT-branch 57 -- Begin WT-branch 58 ---- Begin FA stage FA_477:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(594), DATA_B => SUMMAND(595), DATA_C => SUMMAND(596), SAVE => INT_SUM(592), CARRY => INT_CARRY(468) ); ---- End FA stage ---- Begin FA stage FA_478:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(597), DATA_B => SUMMAND(598), DATA_C => SUMMAND(599), SAVE => INT_SUM(593), CARRY => INT_CARRY(469) ); ---- End FA stage ---- Begin FA stage FA_479:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(592), DATA_B => INT_SUM(593), DATA_C => INT_CARRY(464), SAVE => INT_SUM(594), CARRY => INT_CARRY(470) ); ---- End FA stage ---- Begin NO stage INT_SUM(595) <= INT_CARRY(465); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_480:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(594), DATA_B => INT_SUM(595), DATA_C => INT_CARRY(466), SAVE => INT_SUM(596), CARRY => INT_CARRY(471) ); ---- End FA stage ---- Begin HA stage HA_47:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(596), DATA_B => INT_CARRY(467), SAVE => SUM(57), CARRY => CARRY(57) ); ---- End HA stage -- End WT-branch 58 -- Begin WT-branch 59 ---- Begin FA stage FA_481:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(600), DATA_B => SUMMAND(601), DATA_C => SUMMAND(602), SAVE => INT_SUM(597), CARRY => INT_CARRY(472) ); ---- End FA stage ---- Begin HA stage HA_48:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(603), DATA_B => SUMMAND(604), SAVE => INT_SUM(598), CARRY => INT_CARRY(473) ); ---- End HA stage ---- Begin FA stage FA_482:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(597), DATA_B => INT_SUM(598), DATA_C => INT_CARRY(468), SAVE => INT_SUM(599), CARRY => INT_CARRY(474) ); ---- End FA stage ---- Begin NO stage INT_SUM(600) <= INT_CARRY(469); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_483:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(599), DATA_B => INT_SUM(600), DATA_C => INT_CARRY(470), SAVE => INT_SUM(601), CARRY => INT_CARRY(475) ); ---- End FA stage ---- Begin HA stage HA_49:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(601), DATA_B => INT_CARRY(471), SAVE => SUM(58), CARRY => CARRY(58) ); ---- End HA stage -- End WT-branch 59 -- Begin WT-branch 60 ---- Begin FA stage FA_484:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(605), DATA_B => SUMMAND(606), DATA_C => SUMMAND(607), SAVE => INT_SUM(602), CARRY => INT_CARRY(476) ); ---- End FA stage ---- Begin HA stage HA_50:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(608), DATA_B => SUMMAND(609), SAVE => INT_SUM(603), CARRY => INT_CARRY(477) ); ---- End HA stage ---- Begin FA stage FA_485:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(602), DATA_B => INT_SUM(603), DATA_C => INT_CARRY(472), SAVE => INT_SUM(604), CARRY => INT_CARRY(478) ); ---- End FA stage ---- Begin NO stage INT_SUM(605) <= INT_CARRY(473); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_486:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(604), DATA_B => INT_SUM(605), DATA_C => INT_CARRY(474), SAVE => INT_SUM(606), CARRY => INT_CARRY(479) ); ---- End FA stage ---- Begin HA stage HA_51:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(606), DATA_B => INT_CARRY(475), SAVE => SUM(59), CARRY => CARRY(59) ); ---- End HA stage -- End WT-branch 60 -- Begin WT-branch 61 ---- Begin FA stage FA_487:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(610), DATA_B => SUMMAND(611), DATA_C => SUMMAND(612), SAVE => INT_SUM(607), CARRY => INT_CARRY(480) ); ---- End FA stage ---- Begin FA stage FA_488:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(613), DATA_B => INT_CARRY(476), DATA_C => INT_CARRY(477), SAVE => INT_SUM(608), CARRY => INT_CARRY(481) ); ---- End FA stage ---- Begin FA stage FA_489:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(607), DATA_B => INT_SUM(608), DATA_C => INT_CARRY(478), SAVE => INT_SUM(609), CARRY => INT_CARRY(482) ); ---- End FA stage ---- Begin HA stage HA_52:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(609), DATA_B => INT_CARRY(479), SAVE => SUM(60), CARRY => CARRY(60) ); ---- End HA stage -- End WT-branch 61 -- Begin WT-branch 62 ---- Begin FA stage FA_490:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(614), DATA_B => SUMMAND(615), DATA_C => SUMMAND(616), SAVE => INT_SUM(610), CARRY => INT_CARRY(483) ); ---- End FA stage ---- Begin NO stage INT_SUM(611) <= SUMMAND(617); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_491:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(610), DATA_B => INT_SUM(611), DATA_C => INT_CARRY(480), SAVE => INT_SUM(612), CARRY => INT_CARRY(484) ); ---- End FA stage ---- Begin NO stage INT_SUM(613) <= INT_CARRY(481); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_492:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(612), DATA_B => INT_SUM(613), DATA_C => INT_CARRY(482), SAVE => SUM(61), CARRY => CARRY(61) ); ---- End FA stage -- End WT-branch 62 -- Begin WT-branch 63 ---- Begin FA stage FA_493:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(618), DATA_B => SUMMAND(619), DATA_C => SUMMAND(620), SAVE => INT_SUM(614), CARRY => INT_CARRY(485) ); ---- End FA stage ---- Begin NO stage INT_SUM(615) <= INT_SUM(614); -- At Level 5 ---- End NO stage ---- Begin NO stage INT_SUM(616) <= INT_CARRY(483); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_494:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(615), DATA_B => INT_SUM(616), DATA_C => INT_CARRY(484), SAVE => SUM(62), CARRY => CARRY(62) ); ---- End FA stage -- End WT-branch 63 -- Begin WT-branch 64 ---- Begin FA stage FA_495:FULL_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(621), DATA_B => SUMMAND(622), DATA_C => SUMMAND(623), SAVE => INT_SUM(617), CARRY => INT_CARRY(486) ); ---- End FA stage ---- Begin NO stage INT_SUM(618) <= INT_CARRY(485); -- At Level 5 ---- End NO stage ---- Begin HA stage HA_53:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(617), DATA_B => INT_SUM(618), SAVE => SUM(63), CARRY => CARRY(63) ); ---- End HA stage -- End WT-branch 64 -- Begin WT-branch 65 ---- Begin NO stage INT_SUM(619) <= SUMMAND(624); -- At Level 5 ---- End NO stage ---- Begin NO stage INT_SUM(620) <= SUMMAND(625); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_496:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(619), DATA_B => INT_SUM(620), DATA_C => INT_CARRY(486), SAVE => SUM(64), CARRY => CARRY(64) ); ---- End FA stage -- End WT-branch 65 -- Begin WT-branch 66 ---- Begin HA stage HA_54:HALF_ADDER -- At Level 6 port map ( DATA_A => SUMMAND(626), DATA_B => SUMMAND(627), SAVE => SUM(65), CARRY => CARRY(65) ); ---- End HA stage -- End WT-branch 66 -- Begin WT-branch 67 ---- Begin NO stage SUM(66) <= SUMMAND(628); -- At Level 6 ---- End NO stage -- End WT-branch 67 end WALLACE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_34 is generic (mulpipe : integer := 0); port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 33); PHI: in std_logic; holdn: in std_logic; RESULT: out std_logic_vector(0 to 127) ); end MULTIPLIER_34_34; architecture MULTIPLIER of MULTIPLIER_34_34 is signal PPBIT:std_logic_vector(0 to 628); signal INT_CARRY: std_logic_vector(0 to 128); signal INT_SUM: std_logic_vector(0 to 127); signal LOGIC_ZERO: std_logic; signal INT_CARRYR: std_logic_vector(0 to 128); signal INT_SUMR: std_logic_vector(0 to 127); begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_34 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 33) => MULTIPLIER(0 to 33), SUMMAND(0 to 628) => PPBIT(0 to 628) ); W:WALLACE_34_34 port map ( SUMMAND(0 to 628) => PPBIT(0 to 628), CARRY(0 to 65) => INT_CARRY(1 to 66), SUM(0 to 66) => INT_SUM(0 to 66) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(67) <= LOGIC_ZERO; INT_CARRY(68) <= LOGIC_ZERO; INT_CARRY(69) <= LOGIC_ZERO; INT_CARRY(70) <= LOGIC_ZERO; INT_CARRY(71) <= LOGIC_ZERO; INT_CARRY(72) <= LOGIC_ZERO; INT_CARRY(73) <= LOGIC_ZERO; INT_CARRY(74) <= LOGIC_ZERO; INT_CARRY(75) <= LOGIC_ZERO; INT_CARRY(76) <= LOGIC_ZERO; INT_CARRY(77) <= LOGIC_ZERO; INT_CARRY(78) <= LOGIC_ZERO; INT_CARRY(79) <= LOGIC_ZERO; INT_CARRY(80) <= LOGIC_ZERO; INT_CARRY(81) <= LOGIC_ZERO; INT_CARRY(82) <= LOGIC_ZERO; INT_CARRY(83) <= LOGIC_ZERO; INT_CARRY(84) <= LOGIC_ZERO; INT_CARRY(85) <= LOGIC_ZERO; INT_CARRY(86) <= LOGIC_ZERO; INT_CARRY(87) <= LOGIC_ZERO; INT_CARRY(88) <= LOGIC_ZERO; INT_CARRY(89) <= LOGIC_ZERO; INT_CARRY(90) <= LOGIC_ZERO; INT_CARRY(91) <= LOGIC_ZERO; INT_CARRY(92) <= LOGIC_ZERO; INT_CARRY(93) <= LOGIC_ZERO; INT_CARRY(94) <= LOGIC_ZERO; INT_CARRY(95) <= LOGIC_ZERO; INT_CARRY(96) <= LOGIC_ZERO; INT_CARRY(97) <= LOGIC_ZERO; INT_CARRY(98) <= LOGIC_ZERO; INT_CARRY(99) <= LOGIC_ZERO; INT_CARRY(100) <= LOGIC_ZERO; INT_CARRY(101) <= LOGIC_ZERO; INT_CARRY(102) <= LOGIC_ZERO; INT_CARRY(103) <= LOGIC_ZERO; INT_CARRY(104) <= LOGIC_ZERO; INT_CARRY(105) <= LOGIC_ZERO; INT_CARRY(106) <= LOGIC_ZERO; INT_CARRY(107) <= LOGIC_ZERO; INT_CARRY(108) <= LOGIC_ZERO; INT_CARRY(109) <= LOGIC_ZERO; INT_CARRY(110) <= LOGIC_ZERO; INT_CARRY(111) <= LOGIC_ZERO; INT_CARRY(112) <= LOGIC_ZERO; INT_CARRY(113) <= LOGIC_ZERO; INT_CARRY(114) <= LOGIC_ZERO; INT_CARRY(115) <= LOGIC_ZERO; INT_CARRY(116) <= LOGIC_ZERO; INT_CARRY(117) <= LOGIC_ZERO; INT_CARRY(118) <= LOGIC_ZERO; INT_CARRY(119) <= LOGIC_ZERO; INT_CARRY(120) <= LOGIC_ZERO; INT_CARRY(121) <= LOGIC_ZERO; INT_CARRY(122) <= LOGIC_ZERO; INT_CARRY(123) <= LOGIC_ZERO; INT_CARRY(124) <= LOGIC_ZERO; INT_CARRY(125) <= LOGIC_ZERO; INT_CARRY(126) <= LOGIC_ZERO; INT_CARRY(127) <= LOGIC_ZERO; INT_SUM(67) <= LOGIC_ZERO; INT_SUM(68) <= LOGIC_ZERO; INT_SUM(69) <= LOGIC_ZERO; INT_SUM(70) <= LOGIC_ZERO; INT_SUM(71) <= LOGIC_ZERO; INT_SUM(72) <= LOGIC_ZERO; INT_SUM(73) <= LOGIC_ZERO; INT_SUM(74) <= LOGIC_ZERO; INT_SUM(75) <= LOGIC_ZERO; INT_SUM(76) <= LOGIC_ZERO; INT_SUM(77) <= LOGIC_ZERO; INT_SUM(78) <= LOGIC_ZERO; INT_SUM(79) <= LOGIC_ZERO; INT_SUM(80) <= LOGIC_ZERO; INT_SUM(81) <= LOGIC_ZERO; INT_SUM(82) <= LOGIC_ZERO; INT_SUM(83) <= LOGIC_ZERO; INT_SUM(84) <= LOGIC_ZERO; INT_SUM(85) <= LOGIC_ZERO; INT_SUM(86) <= LOGIC_ZERO; INT_SUM(87) <= LOGIC_ZERO; INT_SUM(88) <= LOGIC_ZERO; INT_SUM(89) <= LOGIC_ZERO; INT_SUM(90) <= LOGIC_ZERO; INT_SUM(91) <= LOGIC_ZERO; INT_SUM(92) <= LOGIC_ZERO; INT_SUM(93) <= LOGIC_ZERO; INT_SUM(94) <= LOGIC_ZERO; INT_SUM(95) <= LOGIC_ZERO; INT_SUM(96) <= LOGIC_ZERO; INT_SUM(97) <= LOGIC_ZERO; INT_SUM(98) <= LOGIC_ZERO; INT_SUM(99) <= LOGIC_ZERO; INT_SUM(100) <= LOGIC_ZERO; INT_SUM(101) <= LOGIC_ZERO; INT_SUM(102) <= LOGIC_ZERO; INT_SUM(103) <= LOGIC_ZERO; INT_SUM(104) <= LOGIC_ZERO; INT_SUM(105) <= LOGIC_ZERO; INT_SUM(106) <= LOGIC_ZERO; INT_SUM(107) <= LOGIC_ZERO; INT_SUM(108) <= LOGIC_ZERO; INT_SUM(109) <= LOGIC_ZERO; INT_SUM(110) <= LOGIC_ZERO; INT_SUM(111) <= LOGIC_ZERO; INT_SUM(112) <= LOGIC_ZERO; INT_SUM(113) <= LOGIC_ZERO; INT_SUM(114) <= LOGIC_ZERO; INT_SUM(115) <= LOGIC_ZERO; INT_SUM(116) <= LOGIC_ZERO; INT_SUM(117) <= LOGIC_ZERO; INT_SUM(118) <= LOGIC_ZERO; INT_SUM(119) <= LOGIC_ZERO; INT_SUM(120) <= LOGIC_ZERO; INT_SUM(121) <= LOGIC_ZERO; INT_SUM(122) <= LOGIC_ZERO; INT_SUM(123) <= LOGIC_ZERO; INT_SUM(124) <= LOGIC_ZERO; INT_SUM(125) <= LOGIC_ZERO; INT_SUM(126) <= LOGIC_ZERO; INT_SUM(127) <= LOGIC_ZERO; INT_SUMR(67 to 127) <= INT_SUM(67 to 127); INT_CARRYR(67 to 127) <= INT_CARRY(67 to 127); INT_CARRYR(0) <= INT_CARRY(0); reg : if MULPIPE /= 0 generate process (PHI) begin if rising_edge(PHI ) then if (holdn = '1') then INT_SUMR(0 to 66) <= INT_SUM(0 to 66); INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66); end if; end if; end process; end generate; noreg : if MULPIPE = 0 generate INT_SUMR(0 to 66) <= INT_SUM(0 to 66); INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66); end generate; D:DBLCADDER_128_128 port map ( OPA(0 to 127) => INT_SUMR(0 to 127), OPB(0 to 127) => INT_CARRYR(0 to 127), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 127) => RESULT(0 to 127) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ -- -- Modgen multiplier created Fri Aug 16 16:35:11 2002 -- ------------------------------------------------------------ -- START: Multiplier Entitiy ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -- START: Top entity ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_33 is generic (mulpipe : integer := 0); port(clk : in std_ulogic; holdn: in std_ulogic; X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(32 downto 0); P: out std_logic_vector(65 downto 0)); end MUL_33_33; architecture A of MUL_33_33 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 33); signal Q: std_logic_vector(0 to 127); begin U1: MULTIPLIER_34_34 generic map (mulpipe) port map(A,B,CLK, holdn ,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(17); B(18) <= Y(18); B(19) <= Y(19); B(20) <= Y(20); B(21) <= Y(21); B(22) <= Y(22); B(23) <= Y(23); B(24) <= Y(24); B(25) <= Y(25); B(26) <= Y(26); B(27) <= Y(27); B(28) <= Y(28); B(29) <= Y(29); B(30) <= Y(30); B(31) <= Y(31); B(32) <= Y(32); B(33) <= Y(32); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); P(42) <= Q(42); P(43) <= Q(43); P(44) <= Q(44); P(45) <= Q(45); P(46) <= Q(46); P(47) <= Q(47); P(48) <= Q(48); P(49) <= Q(49); P(50) <= Q(50); P(51) <= Q(51); P(52) <= Q(52); P(53) <= Q(53); P(54) <= Q(54); P(55) <= Q(55); P(56) <= Q(56); P(57) <= Q(57); P(58) <= Q(58); P(59) <= Q(59); P(60) <= Q(60); P(61) <= Q(61); P(62) <= Q(62); P(63) <= Q(63); P(64) <= Q(64); P(65) <= Q(65); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity ADD32 is port(X: in std_logic_vector(31 downto 0); Y: in std_logic_vector(31 downto 0); CI: in std_logic; S: out std_logic_vector(31 downto 0); CO: out std_logic); end ADD32; architecture A of ADD32 is signal A,B,Q: std_logic_vector(0 to 31); signal CLK: std_logic; begin U1: DBLCADDER_32_32 port map(A,B,CI,CLK,Q,CO); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); B(0) <= Y(0); A(1) <= X(1); B(1) <= Y(1); A(2) <= X(2); B(2) <= Y(2); A(3) <= X(3); B(3) <= Y(3); A(4) <= X(4); B(4) <= Y(4); A(5) <= X(5); B(5) <= Y(5); A(6) <= X(6); B(6) <= Y(6); A(7) <= X(7); B(7) <= Y(7); A(8) <= X(8); B(8) <= Y(8); A(9) <= X(9); B(9) <= Y(9); A(10) <= X(10); B(10) <= Y(10); A(11) <= X(11); B(11) <= Y(11); A(12) <= X(12); B(12) <= Y(12); A(13) <= X(13); B(13) <= Y(13); A(14) <= X(14); B(14) <= Y(14); A(15) <= X(15); B(15) <= Y(15); A(16) <= X(16); B(16) <= Y(16); A(17) <= X(17); B(17) <= Y(17); A(18) <= X(18); B(18) <= Y(18); A(19) <= X(19); B(19) <= Y(19); A(20) <= X(20); B(20) <= Y(20); A(21) <= X(21); B(21) <= Y(21); A(22) <= X(22); B(22) <= Y(22); A(23) <= X(23); B(23) <= Y(23); A(24) <= X(24); B(24) <= Y(24); A(25) <= X(25); B(25) <= Y(25); A(26) <= X(26); B(26) <= Y(26); A(27) <= X(27); B(27) <= Y(27); A(28) <= X(28); B(28) <= Y(28); A(29) <= X(29); B(29) <= Y(29); A(30) <= X(30); B(30) <= Y(30); A(31) <= X(31); B(31) <= Y(31); S(0) <= Q(0); S(1) <= Q(1); S(2) <= Q(2); S(3) <= Q(3); S(4) <= Q(4); S(5) <= Q(5); S(6) <= Q(6); S(7) <= Q(7); S(8) <= Q(8); S(9) <= Q(9); S(10) <= Q(10); S(11) <= Q(11); S(12) <= Q(12); S(13) <= Q(13); S(14) <= Q(14); S(15) <= Q(15); S(16) <= Q(16); S(17) <= Q(17); S(18) <= Q(18); S(19) <= Q(19); S(20) <= Q(20); S(21) <= Q(21); S(22) <= Q(22); S(23) <= Q(23); S(24) <= Q(24); S(25) <= Q(25); S(26) <= Q(26); S(27) <= Q(27); S(28) <= Q(28); S(29) <= Q(29); S(30) <= Q(30); S(31) <= Q(31); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_17_17 is generic (mulpipe : integer := 0); port(clk : in std_ulogic; holdn: in std_ulogic; X: in std_logic_vector(16 downto 0); Y: in std_logic_vector(16 downto 0); P: out std_logic_vector(33 downto 0)); end MUL_17_17; architecture A of MUL_17_17 is signal A: std_logic_vector(0 to 17); signal B: std_logic_vector(0 to 17); signal Q: std_logic_vector(0 to 63); begin U1: MULTIPLIER_18_18 generic map (mulpipe) port map(A,B,CLK, holdn, Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(16); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(16); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); end A;
----------------------------------------------------------------------------- -- File: leaves.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: A set of multipliers generated from the Arithmetic Module -- Generator at Norwegian University of Science and Technology. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; package blocks is component FLIPFLOP port ( DIN, CLK: in std_logic; DOUT: out std_logic ); end component; component DBLCADDER_32_32 port(OPA: in std_logic_vector(0 to 31); OPB: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; SUM: out std_logic_vector(0 to 31); COUT: out std_logic); end component; component FULL_ADDER port ( DATA_A, DATA_B, DATA_C: in std_logic; SAVE, CARRY: out std_logic ); end component; component HALF_ADDER port ( DATA_A, DATA_B: in std_logic; SAVE, CARRY: out std_logic ); end component; component R_GATE port ( INA, INB, INC: in std_logic; PPBIT: out std_logic ); end component; component DECODER port ( INA, INB, INC: in std_logic; TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic ); end component; component PP_LOW port ( ONEPOS, ONENEG, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end component; component PP_MIDDLE port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB, INC, IND: in std_logic; PPBIT: out std_logic ); end component; component PP_HIGH port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end component; component BLOCK0 port ( A,B,PHI: in std_logic; POUT,GOUT: out std_logic ); end component; component INVBLOCK port ( GIN,PHI:in std_logic; GOUT:out std_logic ); end component; component BLOCK1 port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end component; component BLOCK1A port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end component; component BLOCK2 port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end component; component BLOCK2A port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end component; component PRESTAGE_32 port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 31); GOUT: out std_logic_vector(0 to 32) ); end component; component XXOR1 port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end component; component XXOR2 port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end component; component DBLCTREE_32 port ( PIN:in std_logic_vector(0 to 31); GIN:in std_logic_vector(0 to 32); PHI:in std_logic; GOUT:out std_logic_vector(0 to 32); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_32 port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 32); SUM: out std_logic_vector(0 to 31); COUT: out std_logic ); end component; component DBLC_0_32 port ( PIN: in std_logic_vector(0 to 31); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 30); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_1_32 port ( PIN: in std_logic_vector(0 to 30); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 28); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_2_32 port ( PIN: in std_logic_vector(0 to 28); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 24); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_3_32 port ( PIN: in std_logic_vector(0 to 24); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 16); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_4_32 port ( PIN: in std_logic_vector(0 to 16); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 32) ); end component; component PRESTAGE_64 port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 63); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLCTREE_64 port ( PIN:in std_logic_vector(0 to 63); GIN:in std_logic_vector(0 to 64); PHI:in std_logic; GOUT:out std_logic_vector(0 to 64); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_64 port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 64); SUM: out std_logic_vector(0 to 63); COUT: out std_logic ); end component; component DBLC_0_64 port ( PIN: in std_logic_vector(0 to 63); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 62); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_1_64 port ( PIN: in std_logic_vector(0 to 62); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 60); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_2_64 port ( PIN: in std_logic_vector(0 to 60); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 56); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_3_64 port ( PIN: in std_logic_vector(0 to 56); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 48); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_4_64 port ( PIN: in std_logic_vector(0 to 48); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 32); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_5_64 port ( PIN: in std_logic_vector(0 to 32); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_0_128 port ( PIN: in std_logic_vector(0 to 127); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 126); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_1_128 port ( PIN: in std_logic_vector(0 to 126); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 124); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_2_128 port ( PIN: in std_logic_vector(0 to 124); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 120); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_3_128 port ( PIN: in std_logic_vector(0 to 120); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 112); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_4_128 port ( PIN: in std_logic_vector(0 to 112); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 96); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_5_128 port ( PIN: in std_logic_vector(0 to 96); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 64); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_6_128 port ( PIN: in std_logic_vector(0 to 64); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 128) ); end component; component PRESTAGE_128 port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 127); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLCTREE_128 port ( PIN:in std_logic_vector(0 to 127); GIN:in std_logic_vector(0 to 128); PHI:in std_logic; GOUT:out std_logic_vector(0 to 128); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_128 port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 128); SUM: out std_logic_vector(0 to 127); COUT: out std_logic ); end component; component BOOTHCODER_18_18 port ( OPA: in std_logic_vector(0 to 17); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 188) ); end component; component WALLACE_18_18 port ( SUMMAND: in std_logic_vector(0 to 188); CARRY: out std_logic_vector(0 to 33); SUM: out std_logic_vector(0 to 34) ); end component; component DBLCADDER_64_64 port ( OPA:in std_logic_vector(0 to 63); OPB:in std_logic_vector(0 to 63); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 63); COUT:out std_logic ); end component; component BOOTHCODER_34_10 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 9); SUMMAND: out std_logic_vector(0 to 184) ); end component; component WALLACE_34_10 port ( SUMMAND: in std_logic_vector(0 to 184); CARRY: out std_logic_vector(0 to 41); SUM: out std_logic_vector(0 to 42) ); end component; component BOOTHCODER_34_18 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 332) ); end component; component WALLACE_34_18 port ( SUMMAND: in std_logic_vector(0 to 332); CARRY: out std_logic_vector(0 to 49); SUM: out std_logic_vector(0 to 50) ); end component; component BOOTHCODER_34_34 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 33); SUMMAND: out std_logic_vector(0 to 628) ); end component; component WALLACE_34_34 port ( SUMMAND: in std_logic_vector(0 to 628); CARRY: out std_logic_vector(0 to 65); SUM: out std_logic_vector(0 to 66) ); end component; component DBLCADDER_128_128 port ( OPA:in std_logic_vector(0 to 127); OPB:in std_logic_vector(0 to 127); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 127); COUT:out std_logic ); end component; component MULTIPLIER_18_18 generic (mulpipe : integer := 0); port(MULTIPLICAND: in std_logic_vector(0 to 17); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_ulogic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_10 port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 9); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_18 port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_34 generic (mulpipe : integer := 0); port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 33); PHI: in std_logic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 127)); end component; end; ------------------------------------------------------------ -- START: Entities used within the Modified Booth Recoding ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity FLIPFLOP is port ( DIN: in std_logic; CLK: in std_logic; DOUT: out std_logic ); end FLIPFLOP; architecture FLIPFLOP of FLIPFLOP is begin process(CLK) begin if(CLK='1')and(CLK'event)then DOUT <= DIN; end if; end process; end FLIPFLOP; library ieee; use ieee.std_logic_1164.all; entity PP_LOW is port ( ONEPOS, ONENEG, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end PP_LOW; architecture PP_LOW of PP_LOW is begin PPBIT <= (ONEPOS and INA) or (ONENEG and INB) or TWONEG; end PP_LOW; library ieee; use ieee.std_logic_1164.all; entity PP_MIDDLE is port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB, INC, IND: in std_logic; PPBIT: out std_logic ); end PP_MIDDLE; architecture PP_MIDDLE of PP_MIDDLE is begin PPBIT <= not((not(INA and TWOPOS)) and (not(INB and TWONEG)) and (not(INC and ONEPOS)) and (not(IND and ONENEG))); end PP_MIDDLE; library ieee; use ieee.std_logic_1164.all; entity PP_HIGH is port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end PP_HIGH; architecture PP_HIGH of PP_HIGH is begin PPBIT <= not ((INA and ONEPOS) or (INB and ONENEG) or (INA and TWOPOS) or (INB and TWONEG)); end PP_HIGH; library ieee; use ieee.std_logic_1164.all; entity R_GATE is port ( INA, INB, INC: in std_logic; PPBIT: out std_logic ); end R_GATE; architecture R_GATE of R_GATE is begin PPBIT <= (not(INA and INB)) and INC; end R_GATE; library ieee; use ieee.std_logic_1164.all; entity DECODER is port ( INA, INB, INC: in std_logic; TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic ); end DECODER; architecture DECODER of DECODER is begin TWOPOS <= not(not(INA and INB and (not INC))); TWONEG <= not(not((not INA) and (not INB) and INC)); ONEPOS <= ((not INA) and INB and (not INC)) or ((not INC) and (not INB) and INA); ONENEG <= (INA and (not INB) and INC) or (INC and INB and (not INA)); end DECODER; library ieee; use ieee.std_logic_1164.all; entity FULL_ADDER is port ( DATA_A, DATA_B, DATA_C: in std_logic; SAVE, CARRY: out std_logic ); end FULL_ADDER; architecture FULL_ADDER of FULL_ADDER is signal TMP: std_logic; begin TMP <= DATA_A xor DATA_B; SAVE <= TMP xor DATA_C; CARRY <= not((not (TMP and DATA_C)) and (not (DATA_A and DATA_B))); end FULL_ADDER; library ieee; use ieee.std_logic_1164.all; entity HALF_ADDER is port ( DATA_A, DATA_B: in std_logic; SAVE, CARRY: out std_logic ); end HALF_ADDER; architecture HALF_ADDER of HALF_ADDER is begin SAVE <= DATA_A xor DATA_B; CARRY <= DATA_A and DATA_B; end HALF_ADDER; library ieee; use ieee.std_logic_1164.all; entity INVBLOCK is port ( GIN,PHI:in std_logic; GOUT:out std_logic ); end INVBLOCK; architecture INVBLOCK_regular of INVBLOCK is begin GOUT <= not GIN; end INVBLOCK_regular; library ieee; use ieee.std_logic_1164.all; entity XXOR1 is port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end XXOR1; architecture XXOR_regular of XXOR1 is begin SUM <= (not (A xor B)) xor GIN; end XXOR_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK0 is port ( A,B,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK0; architecture BLOCK0_regular of BLOCK0 is begin POUT <= not(A or B); GOUT <= not(A and B); end BLOCK0_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK1 is port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK1; architecture BLOCK1_regular of BLOCK1 is begin POUT <= not(PIN1 or PIN2); GOUT <= not(GIN2 and (PIN2 or GIN1)); end BLOCK1_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK2 is port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK2; architecture BLOCK2_regular of BLOCK2 is begin POUT <= not(PIN1 and PIN2); GOUT <= not(GIN2 or (PIN2 and GIN1)); end BLOCK2_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK1A is port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end BLOCK1A; architecture BLOCK1A_regular of BLOCK1A is begin GOUT <= not(GIN2 and (PIN2 or GIN1)); end BLOCK1A_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK2A is port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end BLOCK2A; architecture BLOCK2A_regular of BLOCK2A is begin GOUT <= not(GIN2 or (PIN2 and GIN1)); end BLOCK2A_regular; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_64 is port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 63); GOUT: out std_logic_vector(0 to 64) ); end PRESTAGE_64; architecture PRESTAGE of PRESTAGE_64 is begin -- PRESTAGE U1:for I in 0 to 63 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: Level 0 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_64 is port ( PIN: in std_logic_vector(0 to 63); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 62); GOUT: out std_logic_vector(0 to 64) ); end DBLC_0_64; architecture DBLC_0 of DBLC_0_64 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 64 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_64 is port ( PIN: in std_logic_vector(0 to 62); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 60); GOUT: out std_logic_vector(0 to 64) ); end DBLC_1_64; architecture DBLC_1 of DBLC_1_64 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 64 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_64 is port ( PIN: in std_logic_vector(0 to 60); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 56); GOUT: out std_logic_vector(0 to 64) ); end DBLC_2_64; architecture DBLC_2 of DBLC_2_64 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 64 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_64 is port ( PIN: in std_logic_vector(0 to 56); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 48); GOUT: out std_logic_vector(0 to 64) ); end DBLC_3_64; architecture DBLC_3 of DBLC_3_64 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 64 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_64 is port ( PIN: in std_logic_vector(0 to 48); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 32); GOUT: out std_logic_vector(0 to 64) ); end DBLC_4_64; architecture DBLC_4 of DBLC_4_64 is begin -- Architecture DBLC_4 U1: for I in 0 to 15 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 64 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; -- The DBLC-tree: Level 5 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_5_64 is port ( PIN: in std_logic_vector(0 to 32); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 64) ); end DBLC_5_64; architecture DBLC_5 of DBLC_5_64 is begin -- Architecture DBLC_5 U1: for I in 0 to 31 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 32 to 63 generate U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 64 to 64 generate U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I)); end generate U3; end DBLC_5; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_64 is port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 64); SUM: out std_logic_vector(0 to 63); COUT: out std_logic ); end XORSTAGE_64; architecture XORSTAGE of XORSTAGE_64 is begin -- XORSTAGE U2:for I in 0 to 63 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U1: BLOCK1A port map(PBIT,CARRY(0),CARRY(64),PHI,COUT); end XORSTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_64 is port ( PIN:in std_logic_vector(0 to 63); GIN:in std_logic_vector(0 to 64); PHI:in std_logic; GOUT:out std_logic_vector(0 to 64); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_64; architecture DBLCTREE of DBLCTREE_64 is signal INTPROP_0: std_logic_vector(0 to 62); signal INTGEN_0: std_logic_vector(0 to 64); signal INTPROP_1: std_logic_vector(0 to 60); signal INTGEN_1: std_logic_vector(0 to 64); signal INTPROP_2: std_logic_vector(0 to 56); signal INTGEN_2: std_logic_vector(0 to 64); signal INTPROP_3: std_logic_vector(0 to 48); signal INTGEN_3: std_logic_vector(0 to 64); signal INTPROP_4: std_logic_vector(0 to 32); signal INTGEN_4: std_logic_vector(0 to 64); begin -- Architecture DBLCTREE U_0: DBLC_0_64 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_64 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_64 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_64 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_64 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4); U_5: DBLC_5_64 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_64_64 is port ( OPA:in std_logic_vector(0 to 63); OPB:in std_logic_vector(0 to 63); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 63); COUT:out std_logic ); end DBLCADDER_64_64; architecture DBLCADDER of DBLCADDER_64_64 is signal INTPROP: std_logic_vector(0 to 63); signal INTGEN: std_logic_vector(0 to 64); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 64); begin -- Architecture DBLCADDER U1: PRESTAGE_64 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_64 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_64 port map(OPA(0 to 63),OPB(0 to 63),PBIT(0),PHI,CARRY(0 to 64),SUM,COUT); end DBLCADDER; ------------------------------------------------------------ -- END: Architectures used with the DBLC adder ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity XXOR2 is port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end XXOR2; architecture XXOR_true of XXOR2 is begin SUM <= (A xor B) xor GIN; end XXOR_true; -- -- Modgen adder created Fri Aug 16 14:47:23 2002 -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_32 is port ( PIN: in std_logic_vector(0 to 31); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 30); GOUT: out std_logic_vector(0 to 32) ); end DBLC_0_32; architecture DBLC_0 of DBLC_0_32 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 32 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_32 is port ( PIN: in std_logic_vector(0 to 30); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 28); GOUT: out std_logic_vector(0 to 32) ); end DBLC_1_32; architecture DBLC_1 of DBLC_1_32 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 32 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_32 is port ( PIN: in std_logic_vector(0 to 28); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 24); GOUT: out std_logic_vector(0 to 32) ); end DBLC_2_32; architecture DBLC_2 of DBLC_2_32 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 32 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_32 is port ( PIN: in std_logic_vector(0 to 24); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 16); GOUT: out std_logic_vector(0 to 32) ); end DBLC_3_32; architecture DBLC_3 of DBLC_3_32 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 32 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_32 is port ( PIN: in std_logic_vector(0 to 16); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 32) ); end DBLC_4_32; architecture DBLC_4 of DBLC_4_32 is begin -- Architecture DBLC_4 GOUT(0 to 15) <= GIN(0 to 15); U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 32 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_32 is port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 32); SUM: out std_logic_vector(0 to 31); COUT: out std_logic ); end XORSTAGE_32; architecture XORSTAGE of XORSTAGE_32 is begin -- XORSTAGE U2:for I in 0 to 15 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U3:for I in 16 to 31 generate U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U3; U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(32),PHI,COUT); end XORSTAGE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_32 is port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 31); GOUT: out std_logic_vector(0 to 32) ); end PRESTAGE_32; architecture PRESTAGE of PRESTAGE_32 is begin -- PRESTAGE U1:for I in 0 to 31 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_32 is port ( PIN:in std_logic_vector(0 to 31); GIN:in std_logic_vector(0 to 32); PHI:in std_logic; GOUT:out std_logic_vector(0 to 32); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_32; architecture DBLCTREE of DBLCTREE_32 is signal INTPROP_0: std_logic_vector(0 to 30); signal INTGEN_0: std_logic_vector(0 to 32); signal INTPROP_1: std_logic_vector(0 to 28); signal INTGEN_1: std_logic_vector(0 to 32); signal INTPROP_2: std_logic_vector(0 to 24); signal INTGEN_2: std_logic_vector(0 to 32); signal INTPROP_3: std_logic_vector(0 to 16); signal INTGEN_3: std_logic_vector(0 to 32); begin -- Architecture DBLCTREE U_0: DBLC_0_32 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_32 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_32 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_32 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_32 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_32_32 is port ( OPA:in std_logic_vector(0 to 31); OPB:in std_logic_vector(0 to 31); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 31); COUT:out std_logic ); end DBLCADDER_32_32; architecture DBLCADDER of DBLCADDER_32_32 is signal INTPROP: std_logic_vector(0 to 31); signal INTGEN: std_logic_vector(0 to 32); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 32); begin -- Architecture DBLCADDER U1: PRESTAGE_32 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_32 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_32 port map(OPA(0 to 31),OPB(0 to 31),PBIT(0),PHI,CARRY(0 to 32),SUM,COUT); end DBLCADDER; ------------------------------------------------------------ -- END: Architectures used with the DBLC adder ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_128 is port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 127); GOUT: out std_logic_vector(0 to 128) ); end PRESTAGE_128; architecture PRESTAGE of PRESTAGE_128 is begin -- PRESTAGE U1:for I in 0 to 127 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: Level 0 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_128 is port ( PIN: in std_logic_vector(0 to 127); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 126); GOUT: out std_logic_vector(0 to 128) ); end DBLC_0_128; architecture DBLC_0 of DBLC_0_128 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 128 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_128 is port ( PIN: in std_logic_vector(0 to 126); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 124); GOUT: out std_logic_vector(0 to 128) ); end DBLC_1_128; architecture DBLC_1 of DBLC_1_128 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 128 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_128 is port ( PIN: in std_logic_vector(0 to 124); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 120); GOUT: out std_logic_vector(0 to 128) ); end DBLC_2_128; architecture DBLC_2 of DBLC_2_128 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 128 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_128 is port ( PIN: in std_logic_vector(0 to 120); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 112); GOUT: out std_logic_vector(0 to 128) ); end DBLC_3_128; architecture DBLC_3 of DBLC_3_128 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 128 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_128 is port ( PIN: in std_logic_vector(0 to 112); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 96); GOUT: out std_logic_vector(0 to 128) ); end DBLC_4_128; architecture DBLC_4 of DBLC_4_128 is begin -- Architecture DBLC_4 U1: for I in 0 to 15 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 128 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; -- The DBLC-tree: Level 5 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_5_128 is port ( PIN: in std_logic_vector(0 to 96); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 64); GOUT: out std_logic_vector(0 to 128) ); end DBLC_5_128; architecture DBLC_5 of DBLC_5_128 is begin -- Architecture DBLC_5 U1: for I in 0 to 31 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 32 to 63 generate U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 64 to 128 generate U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I)); end generate U3; end DBLC_5; -- The DBLC-tree: Level 6 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_6_128 is port ( PIN: in std_logic_vector(0 to 64); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 128) ); end DBLC_6_128; architecture DBLC_6 of DBLC_6_128 is begin -- Architecture DBLC_6 GOUT(0 to 63) <= GIN(0 to 63); U2: for I in 64 to 127 generate U21: BLOCK1A port map(PIN(I-64),GIN(I-64),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 128 to 128 generate U31: BLOCK1 port map(PIN(I-128),PIN(I-64),GIN(I-64),GIN(I),PHI,POUT(I-128),GOUT(I)); end generate U3; end DBLC_6; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_128 is port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 128); SUM: out std_logic_vector(0 to 127); COUT: out std_logic ); end XORSTAGE_128; architecture XORSTAGE of XORSTAGE_128 is begin -- XORSTAGE U2:for I in 0 to 63 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U3:for I in 64 to 127 generate U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U3; U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(128),PHI,COUT); end XORSTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_128 is port ( PIN:in std_logic_vector(0 to 127); GIN:in std_logic_vector(0 to 128); PHI:in std_logic; GOUT:out std_logic_vector(0 to 128); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_128; architecture DBLCTREE of DBLCTREE_128 is signal INTPROP_0: std_logic_vector(0 to 126); signal INTGEN_0: std_logic_vector(0 to 128); signal INTPROP_1: std_logic_vector(0 to 124); signal INTGEN_1: std_logic_vector(0 to 128); signal INTPROP_2: std_logic_vector(0 to 120); signal INTGEN_2: std_logic_vector(0 to 128); signal INTPROP_3: std_logic_vector(0 to 112); signal INTGEN_3: std_logic_vector(0 to 128); signal INTPROP_4: std_logic_vector(0 to 96); signal INTGEN_4: std_logic_vector(0 to 128); signal INTPROP_5: std_logic_vector(0 to 64); signal INTGEN_5: std_logic_vector(0 to 128); begin -- Architecture DBLCTREE U_0: DBLC_0_128 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_128 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_128 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_128 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_128 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4); U_5: DBLC_5_128 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>INTPROP_5,GOUT=>INTGEN_5); U_6: DBLC_6_128 port map(PIN=>INTPROP_5,GIN=>INTGEN_5,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_128_128 is port ( OPA:in std_logic_vector(0 to 127); OPB:in std_logic_vector(0 to 127); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 127); COUT:out std_logic ); end DBLCADDER_128_128; architecture DBLCADDER of DBLCADDER_128_128 is signal INTPROP: std_logic_vector(0 to 127); signal INTGEN: std_logic_vector(0 to 128); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 128); begin -- Architecture DBLCADDER U1: PRESTAGE_128 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_128 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_128 port map(OPA(0 to 127),OPB(0 to 127),PBIT(0),PHI,CARRY(0 to 128),SUM,COUT); end DBLCADDER; -- -- Modified Booth algorithm architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_18_18 is port ( OPA: in std_logic_vector(0 to 17); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 188) ); end BOOTHCODER_18_18; ------------------------------------------------------------ -- END: Entities used within the Modified Booth Recoding ------------------------------------------------------------ architecture BOOTHCODER of BOOTHCODER_18_18 is -- Components used in the architecture -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 17); signal INT_MULTIPLIER: std_logic_vector(0 to 35); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); PPH_0:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); SUMMAND(100) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_17:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_18:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_19:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_20:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_21:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_22:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_23:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_24:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_25:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_26:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_27:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_28:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_29:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_30:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_31:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_32:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(101) ); PPM_33:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(109) ); SUMMAND(110) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(118) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_34:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_35:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_36:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_37:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_38:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_39:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_40:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_41:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_42:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_43:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_44:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_45:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_46:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_47:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(102) ); PPM_48:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(111) ); PPM_49:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(119) ); PPM_50:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(126) ); SUMMAND(127) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(134) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_51:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_52:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_53:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_54:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_55:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_56:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_57:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_58:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_59:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_60:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_61:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_62:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(103) ); PPM_63:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(112) ); PPM_64:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(120) ); PPM_65:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(128) ); PPM_66:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(135) ); PPM_67:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(141) ); SUMMAND(142) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(148) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_68:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_69:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_70:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_71:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_72:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_73:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_74:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_75:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_76:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_77:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(104) ); PPM_78:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(113) ); PPM_79:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(121) ); PPM_80:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(129) ); PPM_81:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(136) ); PPM_82:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(143) ); PPM_83:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(149) ); PPM_84:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(154) ); SUMMAND(155) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_85:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_86:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_87:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_88:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_89:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_90:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_91:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_92:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(105) ); PPM_93:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(114) ); PPM_94:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(122) ); PPM_95:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(130) ); PPM_96:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(137) ); PPM_97:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(144) ); PPM_98:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(150) ); PPM_99:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(156) ); PPM_100:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(161) ); PPM_101:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(165) ); SUMMAND(166) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(170) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_102:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_103:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_104:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_105:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_106:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_107:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(106) ); PPM_108:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(115) ); PPM_109:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(123) ); PPM_110:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(131) ); PPM_111:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(138) ); PPM_112:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(145) ); PPM_113:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(151) ); PPM_114:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(157) ); PPM_115:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(162) ); PPM_116:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(167) ); PPM_117:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(171) ); PPM_118:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(174) ); SUMMAND(175) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(178) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_119:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_120:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_121:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_122:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(107) ); PPM_123:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(116) ); PPM_124:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(124) ); PPM_125:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(132) ); PPM_126:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(139) ); PPM_127:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(146) ); PPM_128:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(152) ); PPM_129:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(158) ); PPM_130:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(163) ); PPM_131:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(168) ); PPM_132:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(172) ); PPM_133:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(176) ); PPM_134:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(179) ); PPM_135:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(181) ); SUMMAND(182) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(184) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_136:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_137:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(108) ); PPM_138:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(117) ); PPM_139:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(125) ); PPM_140:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(133) ); PPM_141:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(140) ); PPM_142:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(147) ); PPM_143:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(153) ); PPM_144:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(159) ); PPM_145:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(164) ); PPM_146:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(169) ); PPM_147:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(173) ); PPM_148:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(177) ); PPM_149:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(180) ); PPM_150:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(183) ); PPM_151:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(185) ); PPM_152:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(186) ); SUMMAND(187) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(188) ); -- Begin partial product 9 end BOOTHCODER; ------------------------------------------------------------ -- END: Architectures used with the Modified Booth recoding ------------------------------------------------------------ -- -- Wallace tree architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_18_18 is port ( SUMMAND: in std_logic_vector(0 to 188); CARRY: out std_logic_vector(0 to 33); SUM: out std_logic_vector(0 to 34) ); end WALLACE_18_18; ------------------------------------------------------------ -- END: Entities within the Wallace-tree ------------------------------------------------------------ architecture WALLACE of WALLACE_18_18 is -- Components used in the netlist -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 114); signal INT_SUM: std_logic_vector(0 to 158); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin NO stage INT_SUM(76) <= SUMMAND(108); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(77), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_CARRY(49), DATA_C => INT_CARRY(50), SAVE => INT_SUM(78), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(51); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(77), DATA_B => INT_SUM(78), DATA_C => INT_SUM(79), SAVE => INT_SUM(80), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin NO stage INT_SUM(81) <= INT_CARRY(52); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(82) <= INT_CARRY(53); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_SUM(82), SAVE => INT_SUM(83), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin NO stage INT_SUM(84) <= INT_CARRY(54); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_64:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(83), DATA_B => INT_SUM(84), DATA_C => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End FA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_65:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(109), DATA_B => SUMMAND(110), DATA_C => SUMMAND(111), SAVE => INT_SUM(85), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(112), DATA_B => SUMMAND(113), DATA_C => SUMMAND(114), SAVE => INT_SUM(86), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117), SAVE => INT_SUM(87), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58), SAVE => INT_SUM(88), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(59), DATA_C => INT_CARRY(60), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_CARRY(61), SAVE => INT_SUM(91), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(91), DATA_B => INT_CARRY(62), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End HA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_72:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), DATA_C => SUMMAND(120), SAVE => INT_SUM(92), CARRY => INT_CARRY(70) ); ---- End FA stage ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(121), DATA_B => SUMMAND(122), DATA_C => SUMMAND(123), SAVE => INT_SUM(93), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(94) <= SUMMAND(124); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(95) <= SUMMAND(125); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_SUM(94), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin NO stage INT_SUM(97) <= INT_SUM(95); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(63), SAVE => INT_SUM(98), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(64), DATA_B => INT_CARRY(65), DATA_C => INT_CARRY(66), SAVE => INT_SUM(99), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(67), SAVE => INT_SUM(100), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin NO stage INT_SUM(101) <= INT_CARRY(68); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(69), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_79:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(102), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(103), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => INT_CARRY(70), SAVE => INT_SUM(104), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin NO stage INT_SUM(105) <= INT_CARRY(71); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_82:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_SUM(104), SAVE => INT_SUM(106), CARRY => INT_CARRY(79) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(105), DATA_B => INT_CARRY(72), SAVE => INT_SUM(107), CARRY => INT_CARRY(80) ); ---- End HA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(73), SAVE => INT_SUM(108), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin NO stage INT_SUM(109) <= INT_CARRY(74); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(75), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(134), DATA_B => SUMMAND(135), DATA_C => SUMMAND(136), SAVE => INT_SUM(110), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(137), DATA_B => SUMMAND(138), DATA_C => SUMMAND(139), SAVE => INT_SUM(111), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(112) <= SUMMAND(140); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_SUM(112), SAVE => INT_SUM(113), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), DATA_C => INT_CARRY(78), SAVE => INT_SUM(114), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_CARRY(79), SAVE => INT_SUM(115), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin NO stage INT_SUM(116) <= INT_CARRY(80); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(81), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_91:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143), SAVE => INT_SUM(117), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin FA stage FA_92:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146), SAVE => INT_SUM(118), CARRY => INT_CARRY(88) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= SUMMAND(147); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_SUM(119), SAVE => INT_SUM(120), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83), SAVE => INT_SUM(121), CARRY => INT_CARRY(90) ); ---- End HA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(84), SAVE => INT_SUM(122), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= INT_CARRY(85); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(86), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), DATA_C => SUMMAND(150), SAVE => INT_SUM(124), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(151), DATA_B => SUMMAND(152), DATA_C => SUMMAND(153), SAVE => INT_SUM(125), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(87), SAVE => INT_SUM(126), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin NO stage INT_SUM(127) <= INT_CARRY(88); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_99:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(89), SAVE => INT_SUM(128), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin NO stage INT_SUM(129) <= INT_CARRY(90); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(91), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_101:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(154), DATA_B => SUMMAND(155), DATA_C => SUMMAND(156), SAVE => INT_SUM(130), CARRY => INT_CARRY(96) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(157), DATA_B => SUMMAND(158), DATA_C => SUMMAND(159), SAVE => INT_SUM(131), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), DATA_C => INT_CARRY(92), SAVE => INT_SUM(132), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin NO stage INT_SUM(133) <= INT_CARRY(93); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(94), SAVE => INT_SUM(134), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(134), DATA_B => INT_CARRY(95), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End HA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_105:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(160), DATA_B => SUMMAND(161), DATA_C => SUMMAND(162), SAVE => INT_SUM(135), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(163), DATA_B => SUMMAND(164), SAVE => INT_SUM(136), CARRY => INT_CARRY(101) ); ---- End HA stage ---- Begin FA stage FA_106:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_CARRY(96), SAVE => INT_SUM(137), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin NO stage INT_SUM(138) <= INT_CARRY(97); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_CARRY(98), SAVE => INT_SUM(139), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(139), DATA_B => INT_CARRY(99), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_108:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(140), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), SAVE => INT_SUM(141), CARRY => INT_CARRY(105) ); ---- End HA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(100), SAVE => INT_SUM(142), CARRY => INT_CARRY(106) ); ---- End FA stage ---- Begin NO stage INT_SUM(143) <= INT_CARRY(101); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(102), SAVE => INT_SUM(144), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(144), DATA_B => INT_CARRY(103), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End HA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_111:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172), SAVE => INT_SUM(145), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(173), DATA_B => INT_CARRY(104), DATA_C => INT_CARRY(105), SAVE => INT_SUM(146), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin FA stage FA_113:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(106), SAVE => INT_SUM(147), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(147), DATA_B => INT_CARRY(107), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_114:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(148), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin NO stage INT_SUM(149) <= SUMMAND(177); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(108), SAVE => INT_SUM(150), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin NO stage INT_SUM(151) <= INT_CARRY(109); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(110), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_117:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(178), DATA_B => SUMMAND(179), DATA_C => SUMMAND(180), SAVE => INT_SUM(152), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin NO stage INT_SUM(153) <= INT_SUM(152); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(154) <= INT_CARRY(111); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_CARRY(112), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_119:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(181), DATA_B => SUMMAND(182), DATA_C => SUMMAND(183), SAVE => INT_SUM(155), CARRY => INT_CARRY(114) ); ---- End FA stage ---- Begin NO stage INT_SUM(156) <= INT_CARRY(113); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(155), DATA_B => INT_SUM(156), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End HA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin NO stage INT_SUM(157) <= SUMMAND(184); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(158) <= SUMMAND(185); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_120:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(114), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin HA stage HA_26:HALF_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End HA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin NO stage SUM(34) <= SUMMAND(188); -- At Level 5 ---- End NO stage -- End WT-branch 35 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_18_18 is generic (mulpipe : integer := 0); port ( MULTIPLICAND: in std_logic_vector(0 to 17); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_ulogic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_18_18; architecture MULTIPLIER of MULTIPLIER_18_18 is signal PPBIT:std_logic_vector(0 to 188); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_CARRYR: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal INT_SUMR: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_18_18 port map ( OPA(0 to 17) => MULTIPLICAND(0 to 17), OPB(0 to 17) => MULTIPLIER(0 to 17), SUMMAND(0 to 188) => PPBIT(0 to 188) ); W:WALLACE_18_18 port map ( SUMMAND(0 to 188) => PPBIT(0 to 188), CARRY(0 to 33) => INT_CARRY(1 to 34), SUM(0 to 34) => INT_SUM(0 to 34) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(35) <= LOGIC_ZERO; INT_CARRY(36) <= LOGIC_ZERO; INT_CARRY(37) <= LOGIC_ZERO; INT_CARRY(38) <= LOGIC_ZERO; INT_CARRY(39) <= LOGIC_ZERO; INT_CARRY(40) <= LOGIC_ZERO; INT_CARRY(41) <= LOGIC_ZERO; INT_CARRY(42) <= LOGIC_ZERO; INT_CARRY(43) <= LOGIC_ZERO; INT_CARRY(44) <= LOGIC_ZERO; INT_CARRY(45) <= LOGIC_ZERO; INT_CARRY(46) <= LOGIC_ZERO; INT_CARRY(47) <= LOGIC_ZERO; INT_CARRY(48) <= LOGIC_ZERO; INT_CARRY(49) <= LOGIC_ZERO; INT_CARRY(50) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(35) <= LOGIC_ZERO; INT_SUM(36) <= LOGIC_ZERO; INT_SUM(37) <= LOGIC_ZERO; INT_SUM(38) <= LOGIC_ZERO; INT_SUM(39) <= LOGIC_ZERO; INT_SUM(40) <= LOGIC_ZERO; INT_SUM(41) <= LOGIC_ZERO; INT_SUM(42) <= LOGIC_ZERO; INT_SUM(43) <= LOGIC_ZERO; INT_SUM(44) <= LOGIC_ZERO; INT_SUM(45) <= LOGIC_ZERO; INT_SUM(46) <= LOGIC_ZERO; INT_SUM(47) <= LOGIC_ZERO; INT_SUM(48) <= LOGIC_ZERO; INT_SUM(49) <= LOGIC_ZERO; INT_SUM(50) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; INT_SUMR(35 to 63) <= INT_SUM(35 to 63); INT_CARRYR(35 to 63) <= INT_CARRY(35 to 63); INT_CARRYR(0) <= INT_CARRY(0); reg : if MULPIPE /= 0 generate process (PHI) begin if rising_edge(PHI ) then if (holdn = '1') then INT_SUMR(0 to 34) <= INT_SUM(0 to 34); INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34); end if; end if; end process; end generate; noreg : if MULPIPE = 0 generate INT_SUMR(0 to 34) <= INT_SUM(0 to 34); INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34); end generate; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUMR(0 to 63), OPB(0 to 63) => INT_CARRYR(0 to 63), CIN => LOGIC_ZERO, PHI => PHI , SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_10 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 9); SUMMAND: out std_logic_vector(0 to 184) ); end BOOTHCODER_34_10; architecture BOOTHCODER of BOOTHCODER_34_10 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 19); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(40) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(45) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(50) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(55) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(60) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(65) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(70) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(75) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(85) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(95) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(100) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(105) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(110) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(115) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(120) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(125) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(130) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(135) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(140) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(145) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(150) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(155) ); SUMMAND(156) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(41) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(46) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(51) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(56) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(61) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(66) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(71) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(76) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(86) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(96) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(101) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(106) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(111) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(116) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(121) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(126) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(131) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(136) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(141) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(146) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(151) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(157) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(161) ); SUMMAND(162) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(166) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(42) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(47) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(52) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(57) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(62) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(67) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(72) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(77) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(87) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(97) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(102) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(107) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(112) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(117) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(122) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(127) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(132) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(137) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(142) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(147) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(152) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(158) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(163) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(167) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(170) ); SUMMAND(171) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(174) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(43) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(48) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(53) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(58) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(63) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(68) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(73) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(78) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(88) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(98) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(103) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(108) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(113) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(118) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(123) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(128) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(133) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(138) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(143) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(148) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(153) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(159) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(164) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(168) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(172) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(175) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(177) ); SUMMAND(178) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(180) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(44) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(49) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(54) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(59) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(64) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(69) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(74) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(79) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(89) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(99) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(104) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(109) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(114) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(119) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(124) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(129) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(134) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(139) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(144) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(149) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(154) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(165) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(169) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(173) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(176) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(179) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(181) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(182) ); SUMMAND(183) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(184) ); -- Begin partial product 5 end BOOTHCODER; ------------------------------------------------------------ -- END: Architectures used with the Modified Booth recoding ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the Wallace-tree ------------------------------------------------------------ -- -- Wallace tree architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_10 is port ( SUMMAND: in std_logic_vector(0 to 184); CARRY: out std_logic_vector(0 to 41); SUM: out std_logic_vector(0 to 42) ); end WALLACE_34_10; architecture WALLACE of WALLACE_34_10 is signal INT_CARRY: std_logic_vector(0 to 95); signal INT_SUM: std_logic_vector(0 to 133); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End HA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_CARRY(9), SAVE => INT_SUM(18), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin NO stage INT_SUM(19) <= INT_CARRY(10); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(18), DATA_B => INT_SUM(19), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_16:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(40), DATA_B => SUMMAND(41), DATA_C => SUMMAND(42), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End FA stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(43), DATA_B => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End HA stage ---- Begin FA stage FA_17:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(20), DATA_B => INT_SUM(21), DATA_C => INT_CARRY(12), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin NO stage INT_SUM(23) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(22), DATA_B => INT_SUM(23), DATA_C => INT_CARRY(14), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End FA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_19:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(24), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End HA stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(24), DATA_B => INT_SUM(25), DATA_C => INT_CARRY(15), SAVE => INT_SUM(26), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin NO stage INT_SUM(27) <= INT_CARRY(16); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_21:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(26), DATA_B => INT_SUM(27), DATA_C => INT_CARRY(17), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End FA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(50), DATA_B => SUMMAND(51), DATA_C => SUMMAND(52), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(53), DATA_B => SUMMAND(54), SAVE => INT_SUM(29), CARRY => INT_CARRY(22) ); ---- End HA stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(28), DATA_B => INT_SUM(29), DATA_C => INT_CARRY(18), SAVE => INT_SUM(30), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin NO stage INT_SUM(31) <= INT_CARRY(19); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(30), DATA_B => INT_SUM(31), DATA_C => INT_CARRY(20), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_25:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(55), DATA_B => SUMMAND(56), DATA_C => SUMMAND(57), SAVE => INT_SUM(32), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(58), DATA_B => SUMMAND(59), SAVE => INT_SUM(33), CARRY => INT_CARRY(25) ); ---- End HA stage ---- Begin FA stage FA_26:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(32), DATA_B => INT_SUM(33), DATA_C => INT_CARRY(21), SAVE => INT_SUM(34), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(35) <= INT_CARRY(22); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_CARRY(23), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_28:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(60), DATA_B => SUMMAND(61), DATA_C => SUMMAND(62), SAVE => INT_SUM(36), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), SAVE => INT_SUM(37), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(36), DATA_B => INT_SUM(37), DATA_C => INT_CARRY(24), SAVE => INT_SUM(38), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(39) <= INT_CARRY(25); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(38), DATA_B => INT_SUM(39), DATA_C => INT_CARRY(26), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(65), DATA_B => SUMMAND(66), DATA_C => SUMMAND(67), SAVE => INT_SUM(40), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(68), DATA_B => SUMMAND(69), SAVE => INT_SUM(41), CARRY => INT_CARRY(31) ); ---- End HA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(40), DATA_B => INT_SUM(41), DATA_C => INT_CARRY(27), SAVE => INT_SUM(42), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin NO stage INT_SUM(43) <= INT_CARRY(28); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(42), DATA_B => INT_SUM(43), DATA_C => INT_CARRY(29), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_34:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(70), DATA_B => SUMMAND(71), DATA_C => SUMMAND(72), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(73), DATA_B => SUMMAND(74), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(30), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(31); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(32), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End FA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End HA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_CARRY(33), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End FA stage ---- Begin NO stage INT_SUM(51) <= INT_CARRY(34); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(50), DATA_B => INT_SUM(51), DATA_C => INT_CARRY(35), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End FA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_40:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(52), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), SAVE => INT_SUM(53), CARRY => INT_CARRY(40) ); ---- End HA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(52), DATA_B => INT_SUM(53), DATA_C => INT_CARRY(36), SAVE => INT_SUM(54), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(55) <= INT_CARRY(37); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(54), DATA_B => INT_SUM(55), DATA_C => INT_CARRY(38), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End FA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(85), DATA_B => SUMMAND(86), DATA_C => SUMMAND(87), SAVE => INT_SUM(56), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(88), DATA_B => SUMMAND(89), SAVE => INT_SUM(57), CARRY => INT_CARRY(43) ); ---- End HA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(56), DATA_B => INT_SUM(57), DATA_C => INT_CARRY(39), SAVE => INT_SUM(58), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(59) <= INT_CARRY(40); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(58), DATA_B => INT_SUM(59), DATA_C => INT_CARRY(41), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_46:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(60), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), SAVE => INT_SUM(61), CARRY => INT_CARRY(46) ); ---- End HA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(60), DATA_B => INT_SUM(61), DATA_C => INT_CARRY(42), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin NO stage INT_SUM(63) <= INT_CARRY(43); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(44), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_49:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(95), DATA_B => SUMMAND(96), DATA_C => SUMMAND(97), SAVE => INT_SUM(64), CARRY => INT_CARRY(48) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(98), DATA_B => SUMMAND(99), SAVE => INT_SUM(65), CARRY => INT_CARRY(49) ); ---- End HA stage ---- Begin FA stage FA_50:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_CARRY(45), SAVE => INT_SUM(66), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin NO stage INT_SUM(67) <= INT_CARRY(46); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(66), DATA_B => INT_SUM(67), DATA_C => INT_CARRY(47), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(100), DATA_B => SUMMAND(101), DATA_C => SUMMAND(102), SAVE => INT_SUM(68), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(103), DATA_B => SUMMAND(104), SAVE => INT_SUM(69), CARRY => INT_CARRY(52) ); ---- End HA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(68), DATA_B => INT_SUM(69), DATA_C => INT_CARRY(48), SAVE => INT_SUM(70), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin NO stage INT_SUM(71) <= INT_CARRY(49); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(70), DATA_B => INT_SUM(71), DATA_C => INT_CARRY(50), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_55:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(72), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), SAVE => INT_SUM(73), CARRY => INT_CARRY(55) ); ---- End HA stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(72), DATA_B => INT_SUM(73), DATA_C => INT_CARRY(51), SAVE => INT_SUM(74), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin NO stage INT_SUM(75) <= INT_CARRY(52); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_57:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(74), DATA_B => INT_SUM(75), DATA_C => INT_CARRY(53), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112), SAVE => INT_SUM(76), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), SAVE => INT_SUM(77), CARRY => INT_CARRY(58) ); ---- End HA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(54), SAVE => INT_SUM(78), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(55); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(56), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End FA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_61:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117), SAVE => INT_SUM(80), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), SAVE => INT_SUM(81), CARRY => INT_CARRY(61) ); ---- End HA stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_CARRY(57), SAVE => INT_SUM(82), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin NO stage INT_SUM(83) <= INT_CARRY(58); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(59), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End FA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_64:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(84), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), SAVE => INT_SUM(85), CARRY => INT_CARRY(64) ); ---- End HA stage ---- Begin FA stage FA_65:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(60), SAVE => INT_SUM(86), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin NO stage INT_SUM(87) <= INT_CARRY(61); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(62), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End FA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_67:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(125), DATA_B => SUMMAND(126), DATA_C => SUMMAND(127), SAVE => INT_SUM(88), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(128), DATA_B => SUMMAND(129), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End HA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(88), DATA_B => INT_SUM(89), DATA_C => INT_CARRY(63), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(91) <= INT_CARRY(64); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(90), DATA_B => INT_SUM(91), DATA_C => INT_CARRY(65), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End FA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_70:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(130), DATA_B => SUMMAND(131), DATA_C => SUMMAND(132), SAVE => INT_SUM(92), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(133), DATA_B => SUMMAND(134), SAVE => INT_SUM(93), CARRY => INT_CARRY(70) ); ---- End HA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66), SAVE => INT_SUM(94), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(67); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), SAVE => INT_SUM(97), CARRY => INT_CARRY(73) ); ---- End HA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(69), SAVE => INT_SUM(98), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin NO stage INT_SUM(99) <= INT_CARRY(70); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(71), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_76:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(140), DATA_B => SUMMAND(141), DATA_C => SUMMAND(142), SAVE => INT_SUM(100), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), SAVE => INT_SUM(101), CARRY => INT_CARRY(76) ); ---- End HA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(72), SAVE => INT_SUM(102), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin NO stage INT_SUM(103) <= INT_CARRY(73); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(74), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End FA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_79:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(145), DATA_B => SUMMAND(146), DATA_C => SUMMAND(147), SAVE => INT_SUM(104), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), SAVE => INT_SUM(105), CARRY => INT_CARRY(79) ); ---- End HA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(104), DATA_B => INT_SUM(105), DATA_C => INT_CARRY(75), SAVE => INT_SUM(106), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin NO stage INT_SUM(107) <= INT_CARRY(76); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(77), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_82:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152), SAVE => INT_SUM(108), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), SAVE => INT_SUM(109), CARRY => INT_CARRY(82) ); ---- End HA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(78), SAVE => INT_SUM(110), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(111) <= INT_CARRY(79); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(80), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End FA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(155), DATA_B => SUMMAND(156), DATA_C => SUMMAND(157), SAVE => INT_SUM(112), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(158), DATA_B => SUMMAND(159), DATA_C => SUMMAND(160), SAVE => INT_SUM(113), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_CARRY(81), SAVE => INT_SUM(114), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin NO stage INT_SUM(115) <= INT_CARRY(82); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(114), DATA_B => INT_SUM(115), DATA_C => INT_CARRY(83), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_89:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(161), DATA_B => SUMMAND(162), DATA_C => SUMMAND(163), SAVE => INT_SUM(116), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(164), DATA_B => SUMMAND(165), SAVE => INT_SUM(117), CARRY => INT_CARRY(88) ); ---- End HA stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(84), SAVE => INT_SUM(118), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= INT_CARRY(85); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_91:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(86), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End FA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(166), DATA_B => SUMMAND(167), DATA_C => SUMMAND(168), SAVE => INT_SUM(120), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin NO stage INT_SUM(121) <= SUMMAND(169); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(87), SAVE => INT_SUM(122), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= INT_CARRY(88); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(89), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_95:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172), SAVE => INT_SUM(124), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin NO stage INT_SUM(125) <= SUMMAND(173); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(90), SAVE => INT_SUM(126), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(126), DATA_B => INT_CARRY(91), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End HA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_97:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(127), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin NO stage INT_SUM(128) <= INT_SUM(127); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(129) <= INT_CARRY(92); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(93), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_99:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(130), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin NO stage INT_SUM(131) <= INT_CARRY(94); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End HA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin NO stage INT_SUM(132) <= SUMMAND(180); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(133) <= SUMMAND(181); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(95), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin HA stage HA_35:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End HA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin NO stage SUM(42) <= SUMMAND(184); -- At Level 3 ---- End NO stage -- End WT-branch 43 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_10 is port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 9); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_34_10; ------------------------------------------------------------ -- End: Multiplier Entitiy architecture MULTIPLIER of MULTIPLIER_34_10 is signal PPBIT:std_logic_vector(0 to 184); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_10 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 9) => MULTIPLIER(0 to 9), SUMMAND(0 to 184) => PPBIT(0 to 184) ); W:WALLACE_34_10 port map ( SUMMAND(0 to 184) => PPBIT(0 to 184), CARRY(0 to 41) => INT_CARRY(1 to 42), SUM(0 to 42) => INT_SUM(0 to 42) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(43) <= LOGIC_ZERO; INT_CARRY(44) <= LOGIC_ZERO; INT_CARRY(45) <= LOGIC_ZERO; INT_CARRY(46) <= LOGIC_ZERO; INT_CARRY(47) <= LOGIC_ZERO; INT_CARRY(48) <= LOGIC_ZERO; INT_CARRY(49) <= LOGIC_ZERO; INT_CARRY(50) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(43) <= LOGIC_ZERO; INT_SUM(44) <= LOGIC_ZERO; INT_SUM(45) <= LOGIC_ZERO; INT_SUM(46) <= LOGIC_ZERO; INT_SUM(47) <= LOGIC_ZERO; INT_SUM(48) <= LOGIC_ZERO; INT_SUM(49) <= LOGIC_ZERO; INT_SUM(50) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUM(0 to 63), OPB(0 to 63) => INT_CARRY(0 to 63), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_9 is port(X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(8 downto 0); P: out std_logic_vector(41 downto 0)); end MUL_33_9; library ieee; use ieee.std_logic_1164.all; architecture A of MUL_33_9 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 9); signal Q: std_logic_vector(0 to 63); signal CLK: std_logic; begin U1: MULTIPLIER_34_10 port map(A,B,CLK,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(8); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); end A; ------------------------------------------------------------ -- START: Entities within the Wallace-tree ------------------------------------------------------------ -- -- Modified Booth algorithm architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_18 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 332) ); end BOOTHCODER_34_18; architecture BOOTHCODER of BOOTHCODER_34_18 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 35); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(108) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(117) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(126) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(135) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(144) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(153) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(162) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(171) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(180) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(189) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(198) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(207) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(216) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(225) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(234) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(243) ); SUMMAND(244) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(100) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(109) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(118) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(127) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(136) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(145) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(154) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(163) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(172) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(181) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(190) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(199) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(208) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(217) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(226) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(235) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(245) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(253) ); SUMMAND(254) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(262) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(101) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(110) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(119) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(128) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(137) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(146) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(155) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(164) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(173) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(182) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(191) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(200) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(209) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(218) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(227) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(236) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(246) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(255) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(263) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(270) ); SUMMAND(271) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(278) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(102) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(111) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(120) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(129) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(138) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(147) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(156) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(165) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(174) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(183) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(192) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(201) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(210) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(219) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(228) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(237) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(247) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(256) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(264) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(272) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(279) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(285) ); SUMMAND(286) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(292) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(103) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(112) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(121) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(130) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(139) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(148) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(157) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(166) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(175) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(184) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(193) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(202) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(211) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(220) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(229) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(238) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(248) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(257) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(265) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(273) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(280) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(287) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(293) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(298) ); SUMMAND(299) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(304) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_165:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_166:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_167:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_168:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_169:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_170:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_171:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_172:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(104) ); PPM_173:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(113) ); PPM_174:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(122) ); PPM_175:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(131) ); PPM_176:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(140) ); PPM_177:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(149) ); PPM_178:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(158) ); PPM_179:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(167) ); PPM_180:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(176) ); PPM_181:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(185) ); PPM_182:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(194) ); PPM_183:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(203) ); PPM_184:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(212) ); PPM_185:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(221) ); PPM_186:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(230) ); PPM_187:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(239) ); PPM_188:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(249) ); PPM_189:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(258) ); PPM_190:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(266) ); PPM_191:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(274) ); PPM_192:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(281) ); PPM_193:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(288) ); PPM_194:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(294) ); PPM_195:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(300) ); PPM_196:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(305) ); PPM_197:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(309) ); SUMMAND(310) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(314) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_198:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_199:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_200:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_201:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_202:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_203:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(105) ); PPM_204:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(114) ); PPM_205:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(123) ); PPM_206:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(132) ); PPM_207:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(141) ); PPM_208:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(150) ); PPM_209:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(159) ); PPM_210:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(168) ); PPM_211:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(177) ); PPM_212:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(186) ); PPM_213:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(195) ); PPM_214:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(204) ); PPM_215:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(213) ); PPM_216:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(222) ); PPM_217:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(231) ); PPM_218:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(240) ); PPM_219:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(250) ); PPM_220:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(259) ); PPM_221:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(267) ); PPM_222:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(275) ); PPM_223:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(282) ); PPM_224:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(289) ); PPM_225:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(295) ); PPM_226:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(301) ); PPM_227:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(306) ); PPM_228:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(311) ); PPM_229:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(315) ); PPM_230:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(318) ); SUMMAND(319) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(322) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_231:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_232:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_233:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_234:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(106) ); PPM_235:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(115) ); PPM_236:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(124) ); PPM_237:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(133) ); PPM_238:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(142) ); PPM_239:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(151) ); PPM_240:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(160) ); PPM_241:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(169) ); PPM_242:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(178) ); PPM_243:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(187) ); PPM_244:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(196) ); PPM_245:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(205) ); PPM_246:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(214) ); PPM_247:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(223) ); PPM_248:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(232) ); PPM_249:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(241) ); PPM_250:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(251) ); PPM_251:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(260) ); PPM_252:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(268) ); PPM_253:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(276) ); PPM_254:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(283) ); PPM_255:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(290) ); PPM_256:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(296) ); PPM_257:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(302) ); PPM_258:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(307) ); PPM_259:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(312) ); PPM_260:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(316) ); PPM_261:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(320) ); PPM_262:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(323) ); PPM_263:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(325) ); SUMMAND(326) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(328) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_264:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_265:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(107) ); PPM_266:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(116) ); PPM_267:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(125) ); PPM_268:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(134) ); PPM_269:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(143) ); PPM_270:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(152) ); PPM_271:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(161) ); PPM_272:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(170) ); PPM_273:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(179) ); PPM_274:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(188) ); PPM_275:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(197) ); PPM_276:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(206) ); PPM_277:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(215) ); PPM_278:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(224) ); PPM_279:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(233) ); PPM_280:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(242) ); PPM_281:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(252) ); PPM_282:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(261) ); PPM_283:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(269) ); PPM_284:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(277) ); PPM_285:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(284) ); PPM_286:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(291) ); PPM_287:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(297) ); PPM_288:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(303) ); PPM_289:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(308) ); PPM_290:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(313) ); PPM_291:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(317) ); PPM_292:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(321) ); PPM_293:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(324) ); PPM_294:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(327) ); PPM_295:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(329) ); PPM_296:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(330) ); SUMMAND(331) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(332) ); -- Begin partial product 9 end BOOTHCODER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_18 is port ( SUMMAND: in std_logic_vector(0 to 332); CARRY: out std_logic_vector(0 to 49); SUM: out std_logic_vector(0 to 50) ); end WALLACE_34_18; architecture WALLACE of WALLACE_34_18 is -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 226); signal INT_SUM: std_logic_vector(0 to 286); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(76), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(49), DATA_B => INT_CARRY(50), DATA_C => INT_CARRY(51), SAVE => INT_SUM(77), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(52), SAVE => INT_SUM(78), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(53); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(54), SAVE => INT_SUM(80), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(80), DATA_B => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End HA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_64:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), DATA_C => SUMMAND(110), SAVE => INT_SUM(81), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin FA stage FA_65:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(111), DATA_B => SUMMAND(112), DATA_C => SUMMAND(113), SAVE => INT_SUM(82), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(114), DATA_B => SUMMAND(115), DATA_C => SUMMAND(116), SAVE => INT_SUM(83), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(81), DATA_B => INT_SUM(82), DATA_C => INT_SUM(83), SAVE => INT_SUM(84), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58), SAVE => INT_SUM(85), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(59), SAVE => INT_SUM(86), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(87) <= INT_CARRY(60); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(61), SAVE => INT_SUM(88), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(62), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End HA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_71:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(117), DATA_B => SUMMAND(118), DATA_C => SUMMAND(119), SAVE => INT_SUM(89), CARRY => INT_CARRY(70) ); ---- End FA stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(90), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125), SAVE => INT_SUM(91), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91), SAVE => INT_SUM(92), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(63), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65), SAVE => INT_SUM(93), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66), SAVE => INT_SUM(94), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(67); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68), SAVE => INT_SUM(96), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(96), DATA_B => INT_CARRY(69), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End HA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_78:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(97), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin FA stage FA_79:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(98), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134), SAVE => INT_SUM(99), CARRY => INT_CARRY(79) ); ---- End FA stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(97), DATA_B => INT_SUM(98), DATA_C => INT_SUM(99), SAVE => INT_SUM(100), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin FA stage FA_82:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(70), DATA_B => INT_CARRY(71), DATA_C => INT_CARRY(72), SAVE => INT_SUM(101), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(73), SAVE => INT_SUM(102), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin NO stage INT_SUM(103) <= INT_CARRY(74); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(75), SAVE => INT_SUM(104), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(104), DATA_B => INT_CARRY(76), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End HA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(105), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140), SAVE => INT_SUM(106), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143), SAVE => INT_SUM(107), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_SUM(107), SAVE => INT_SUM(108), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(77), DATA_B => INT_CARRY(78), DATA_C => INT_CARRY(79), SAVE => INT_SUM(109), CARRY => INT_CARRY(88) ); ---- End FA stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(80), SAVE => INT_SUM(110), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(111) <= INT_CARRY(81); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_91:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(82), SAVE => INT_SUM(112), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(112), DATA_B => INT_CARRY(83), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End HA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146), SAVE => INT_SUM(113), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(147), DATA_B => SUMMAND(148), DATA_C => SUMMAND(149), SAVE => INT_SUM(114), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152), SAVE => INT_SUM(115), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_SUM(115), SAVE => INT_SUM(116), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86), SAVE => INT_SUM(117), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(87), SAVE => INT_SUM(118), CARRY => INT_CARRY(96) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= INT_CARRY(88); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(89), SAVE => INT_SUM(120), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(120), DATA_B => INT_CARRY(90), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End HA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_99:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), DATA_C => SUMMAND(155), SAVE => INT_SUM(121), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158), SAVE => INT_SUM(122), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin FA stage FA_101:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161), SAVE => INT_SUM(123), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(121), DATA_B => INT_SUM(122), DATA_C => INT_SUM(123), SAVE => INT_SUM(124), CARRY => INT_CARRY(101) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(91), DATA_B => INT_CARRY(92), DATA_C => INT_CARRY(93), SAVE => INT_SUM(125), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(94), SAVE => INT_SUM(126), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin NO stage INT_SUM(127) <= INT_CARRY(95); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_105:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(96), SAVE => INT_SUM(128), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(128), DATA_B => INT_CARRY(97), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End HA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_106:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164), SAVE => INT_SUM(129), CARRY => INT_CARRY(105) ); ---- End FA stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(130), CARRY => INT_CARRY(106) ); ---- End FA stage ---- Begin FA stage FA_108:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170), SAVE => INT_SUM(131), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_SUM(131), SAVE => INT_SUM(132), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(98), DATA_B => INT_CARRY(99), DATA_C => INT_CARRY(100), SAVE => INT_SUM(133), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin FA stage FA_111:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(101), SAVE => INT_SUM(134), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin NO stage INT_SUM(135) <= INT_CARRY(102); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(134), DATA_B => INT_SUM(135), DATA_C => INT_CARRY(103), SAVE => INT_SUM(136), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(136), DATA_B => INT_CARRY(104), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End HA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_113:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173), SAVE => INT_SUM(137), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin FA stage FA_114:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(138), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(139), CARRY => INT_CARRY(114) ); ---- End FA stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_SUM(139), SAVE => INT_SUM(140), CARRY => INT_CARRY(115) ); ---- End FA stage ---- Begin FA stage FA_117:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(105), DATA_B => INT_CARRY(106), DATA_C => INT_CARRY(107), SAVE => INT_SUM(141), CARRY => INT_CARRY(116) ); ---- End FA stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(108), SAVE => INT_SUM(142), CARRY => INT_CARRY(117) ); ---- End FA stage ---- Begin NO stage INT_SUM(143) <= INT_CARRY(109); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_119:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(110), SAVE => INT_SUM(144), CARRY => INT_CARRY(118) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(144), DATA_B => INT_CARRY(111), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_120:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), DATA_C => SUMMAND(182), SAVE => INT_SUM(145), CARRY => INT_CARRY(119) ); ---- End FA stage ---- Begin FA stage FA_121:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(183), DATA_B => SUMMAND(184), DATA_C => SUMMAND(185), SAVE => INT_SUM(146), CARRY => INT_CARRY(120) ); ---- End FA stage ---- Begin FA stage FA_122:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), DATA_C => SUMMAND(188), SAVE => INT_SUM(147), CARRY => INT_CARRY(121) ); ---- End FA stage ---- Begin FA stage FA_123:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_SUM(147), SAVE => INT_SUM(148), CARRY => INT_CARRY(122) ); ---- End FA stage ---- Begin FA stage FA_124:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(112), DATA_B => INT_CARRY(113), DATA_C => INT_CARRY(114), SAVE => INT_SUM(149), CARRY => INT_CARRY(123) ); ---- End FA stage ---- Begin FA stage FA_125:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(115), SAVE => INT_SUM(150), CARRY => INT_CARRY(124) ); ---- End FA stage ---- Begin NO stage INT_SUM(151) <= INT_CARRY(116); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_126:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(117), SAVE => INT_SUM(152), CARRY => INT_CARRY(125) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(152), DATA_B => INT_CARRY(118), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End HA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_127:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(189), DATA_B => SUMMAND(190), DATA_C => SUMMAND(191), SAVE => INT_SUM(153), CARRY => INT_CARRY(126) ); ---- End FA stage ---- Begin FA stage FA_128:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(192), DATA_B => SUMMAND(193), DATA_C => SUMMAND(194), SAVE => INT_SUM(154), CARRY => INT_CARRY(127) ); ---- End FA stage ---- Begin FA stage FA_129:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197), SAVE => INT_SUM(155), CARRY => INT_CARRY(128) ); ---- End FA stage ---- Begin FA stage FA_130:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_SUM(155), SAVE => INT_SUM(156), CARRY => INT_CARRY(129) ); ---- End FA stage ---- Begin FA stage FA_131:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(119), DATA_B => INT_CARRY(120), DATA_C => INT_CARRY(121), SAVE => INT_SUM(157), CARRY => INT_CARRY(130) ); ---- End FA stage ---- Begin FA stage FA_132:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(156), DATA_B => INT_SUM(157), DATA_C => INT_CARRY(122), SAVE => INT_SUM(158), CARRY => INT_CARRY(131) ); ---- End FA stage ---- Begin NO stage INT_SUM(159) <= INT_CARRY(123); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_133:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(158), DATA_B => INT_SUM(159), DATA_C => INT_CARRY(124), SAVE => INT_SUM(160), CARRY => INT_CARRY(132) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(160), DATA_B => INT_CARRY(125), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_134:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200), SAVE => INT_SUM(161), CARRY => INT_CARRY(133) ); ---- End FA stage ---- Begin FA stage FA_135:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203), SAVE => INT_SUM(162), CARRY => INT_CARRY(134) ); ---- End FA stage ---- Begin FA stage FA_136:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206), SAVE => INT_SUM(163), CARRY => INT_CARRY(135) ); ---- End FA stage ---- Begin FA stage FA_137:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(161), DATA_B => INT_SUM(162), DATA_C => INT_SUM(163), SAVE => INT_SUM(164), CARRY => INT_CARRY(136) ); ---- End FA stage ---- Begin FA stage FA_138:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(126), DATA_B => INT_CARRY(127), DATA_C => INT_CARRY(128), SAVE => INT_SUM(165), CARRY => INT_CARRY(137) ); ---- End FA stage ---- Begin FA stage FA_139:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(164), DATA_B => INT_SUM(165), DATA_C => INT_CARRY(129), SAVE => INT_SUM(166), CARRY => INT_CARRY(138) ); ---- End FA stage ---- Begin NO stage INT_SUM(167) <= INT_CARRY(130); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_140:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(131), SAVE => INT_SUM(168), CARRY => INT_CARRY(139) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(168), DATA_B => INT_CARRY(132), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End HA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_141:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209), SAVE => INT_SUM(169), CARRY => INT_CARRY(140) ); ---- End FA stage ---- Begin FA stage FA_142:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212), SAVE => INT_SUM(170), CARRY => INT_CARRY(141) ); ---- End FA stage ---- Begin FA stage FA_143:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215), SAVE => INT_SUM(171), CARRY => INT_CARRY(142) ); ---- End FA stage ---- Begin FA stage FA_144:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(169), DATA_B => INT_SUM(170), DATA_C => INT_SUM(171), SAVE => INT_SUM(172), CARRY => INT_CARRY(143) ); ---- End FA stage ---- Begin FA stage FA_145:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135), SAVE => INT_SUM(173), CARRY => INT_CARRY(144) ); ---- End FA stage ---- Begin FA stage FA_146:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(172), DATA_B => INT_SUM(173), DATA_C => INT_CARRY(136), SAVE => INT_SUM(174), CARRY => INT_CARRY(145) ); ---- End FA stage ---- Begin NO stage INT_SUM(175) <= INT_CARRY(137); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_147:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(174), DATA_B => INT_SUM(175), DATA_C => INT_CARRY(138), SAVE => INT_SUM(176), CARRY => INT_CARRY(146) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(176), DATA_B => INT_CARRY(139), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End HA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_148:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218), SAVE => INT_SUM(177), CARRY => INT_CARRY(147) ); ---- End FA stage ---- Begin FA stage FA_149:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221), SAVE => INT_SUM(178), CARRY => INT_CARRY(148) ); ---- End FA stage ---- Begin FA stage FA_150:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), DATA_C => SUMMAND(224), SAVE => INT_SUM(179), CARRY => INT_CARRY(149) ); ---- End FA stage ---- Begin FA stage FA_151:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(177), DATA_B => INT_SUM(178), DATA_C => INT_SUM(179), SAVE => INT_SUM(180), CARRY => INT_CARRY(150) ); ---- End FA stage ---- Begin FA stage FA_152:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(140), DATA_B => INT_CARRY(141), DATA_C => INT_CARRY(142), SAVE => INT_SUM(181), CARRY => INT_CARRY(151) ); ---- End FA stage ---- Begin FA stage FA_153:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), DATA_C => INT_CARRY(143), SAVE => INT_SUM(182), CARRY => INT_CARRY(152) ); ---- End FA stage ---- Begin NO stage INT_SUM(183) <= INT_CARRY(144); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_154:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_CARRY(145), SAVE => INT_SUM(184), CARRY => INT_CARRY(153) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(184), DATA_B => INT_CARRY(146), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End HA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_155:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(225), DATA_B => SUMMAND(226), DATA_C => SUMMAND(227), SAVE => INT_SUM(185), CARRY => INT_CARRY(154) ); ---- End FA stage ---- Begin FA stage FA_156:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(228), DATA_B => SUMMAND(229), DATA_C => SUMMAND(230), SAVE => INT_SUM(186), CARRY => INT_CARRY(155) ); ---- End FA stage ---- Begin FA stage FA_157:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(231), DATA_B => SUMMAND(232), DATA_C => SUMMAND(233), SAVE => INT_SUM(187), CARRY => INT_CARRY(156) ); ---- End FA stage ---- Begin FA stage FA_158:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_SUM(187), SAVE => INT_SUM(188), CARRY => INT_CARRY(157) ); ---- End FA stage ---- Begin FA stage FA_159:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(147), DATA_B => INT_CARRY(148), DATA_C => INT_CARRY(149), SAVE => INT_SUM(189), CARRY => INT_CARRY(158) ); ---- End FA stage ---- Begin FA stage FA_160:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(188), DATA_B => INT_SUM(189), DATA_C => INT_CARRY(150), SAVE => INT_SUM(190), CARRY => INT_CARRY(159) ); ---- End FA stage ---- Begin NO stage INT_SUM(191) <= INT_CARRY(151); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_161:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(190), DATA_B => INT_SUM(191), DATA_C => INT_CARRY(152), SAVE => INT_SUM(192), CARRY => INT_CARRY(160) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(192), DATA_B => INT_CARRY(153), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End HA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_162:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(234), DATA_B => SUMMAND(235), DATA_C => SUMMAND(236), SAVE => INT_SUM(193), CARRY => INT_CARRY(161) ); ---- End FA stage ---- Begin FA stage FA_163:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(237), DATA_B => SUMMAND(238), DATA_C => SUMMAND(239), SAVE => INT_SUM(194), CARRY => INT_CARRY(162) ); ---- End FA stage ---- Begin FA stage FA_164:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242), SAVE => INT_SUM(195), CARRY => INT_CARRY(163) ); ---- End FA stage ---- Begin FA stage FA_165:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(193), DATA_B => INT_SUM(194), DATA_C => INT_SUM(195), SAVE => INT_SUM(196), CARRY => INT_CARRY(164) ); ---- End FA stage ---- Begin FA stage FA_166:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(154), DATA_B => INT_CARRY(155), DATA_C => INT_CARRY(156), SAVE => INT_SUM(197), CARRY => INT_CARRY(165) ); ---- End FA stage ---- Begin FA stage FA_167:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(196), DATA_B => INT_SUM(197), DATA_C => INT_CARRY(157), SAVE => INT_SUM(198), CARRY => INT_CARRY(166) ); ---- End FA stage ---- Begin NO stage INT_SUM(199) <= INT_CARRY(158); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_168:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(198), DATA_B => INT_SUM(199), DATA_C => INT_CARRY(159), SAVE => INT_SUM(200), CARRY => INT_CARRY(167) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(200), DATA_B => INT_CARRY(160), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End HA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_169:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245), SAVE => INT_SUM(201), CARRY => INT_CARRY(168) ); ---- End FA stage ---- Begin FA stage FA_170:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248), SAVE => INT_SUM(202), CARRY => INT_CARRY(169) ); ---- End FA stage ---- Begin FA stage FA_171:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251), SAVE => INT_SUM(203), CARRY => INT_CARRY(170) ); ---- End FA stage ---- Begin NO stage INT_SUM(204) <= SUMMAND(252); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_172:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(201), DATA_B => INT_SUM(202), DATA_C => INT_SUM(203), SAVE => INT_SUM(205), CARRY => INT_CARRY(171) ); ---- End FA stage ---- Begin FA stage FA_173:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(204), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162), SAVE => INT_SUM(206), CARRY => INT_CARRY(172) ); ---- End FA stage ---- Begin NO stage INT_SUM(207) <= INT_CARRY(163); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_174:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207), SAVE => INT_SUM(208), CARRY => INT_CARRY(173) ); ---- End FA stage ---- Begin NO stage INT_SUM(209) <= INT_CARRY(164); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(210) <= INT_CARRY(165); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_175:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_SUM(210), SAVE => INT_SUM(211), CARRY => INT_CARRY(174) ); ---- End FA stage ---- Begin NO stage INT_SUM(212) <= INT_CARRY(166); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_176:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(211), DATA_B => INT_SUM(212), DATA_C => INT_CARRY(167), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_177:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(253), DATA_B => SUMMAND(254), DATA_C => SUMMAND(255), SAVE => INT_SUM(213), CARRY => INT_CARRY(175) ); ---- End FA stage ---- Begin FA stage FA_178:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(256), DATA_B => SUMMAND(257), DATA_C => SUMMAND(258), SAVE => INT_SUM(214), CARRY => INT_CARRY(176) ); ---- End FA stage ---- Begin FA stage FA_179:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(259), DATA_B => SUMMAND(260), DATA_C => SUMMAND(261), SAVE => INT_SUM(215), CARRY => INT_CARRY(177) ); ---- End FA stage ---- Begin FA stage FA_180:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(168), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170), SAVE => INT_SUM(216), CARRY => INT_CARRY(178) ); ---- End FA stage ---- Begin FA stage FA_181:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(213), DATA_B => INT_SUM(214), DATA_C => INT_SUM(215), SAVE => INT_SUM(217), CARRY => INT_CARRY(179) ); ---- End FA stage ---- Begin FA stage FA_182:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(216), DATA_B => INT_CARRY(171), DATA_C => INT_CARRY(172), SAVE => INT_SUM(218), CARRY => INT_CARRY(180) ); ---- End FA stage ---- Begin FA stage FA_183:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_CARRY(173), SAVE => INT_SUM(219), CARRY => INT_CARRY(181) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(219), DATA_B => INT_CARRY(174), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End HA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_184:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(262), DATA_B => SUMMAND(263), DATA_C => SUMMAND(264), SAVE => INT_SUM(220), CARRY => INT_CARRY(182) ); ---- End FA stage ---- Begin FA stage FA_185:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(265), DATA_B => SUMMAND(266), DATA_C => SUMMAND(267), SAVE => INT_SUM(221), CARRY => INT_CARRY(183) ); ---- End FA stage ---- Begin NO stage INT_SUM(222) <= SUMMAND(268); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(223) <= SUMMAND(269); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_186:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_SUM(222), SAVE => INT_SUM(224), CARRY => INT_CARRY(184) ); ---- End FA stage ---- Begin NO stage INT_SUM(225) <= INT_SUM(223); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_187:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(224), DATA_B => INT_SUM(225), DATA_C => INT_CARRY(175), SAVE => INT_SUM(226), CARRY => INT_CARRY(185) ); ---- End FA stage ---- Begin FA stage FA_188:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(176), DATA_B => INT_CARRY(177), DATA_C => INT_CARRY(178), SAVE => INT_SUM(227), CARRY => INT_CARRY(186) ); ---- End FA stage ---- Begin FA stage FA_189:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_CARRY(179), SAVE => INT_SUM(228), CARRY => INT_CARRY(187) ); ---- End FA stage ---- Begin NO stage INT_SUM(229) <= INT_CARRY(180); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_190:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(228), DATA_B => INT_SUM(229), DATA_C => INT_CARRY(181), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_191:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(270), DATA_B => SUMMAND(271), DATA_C => SUMMAND(272), SAVE => INT_SUM(230), CARRY => INT_CARRY(188) ); ---- End FA stage ---- Begin FA stage FA_192:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(273), DATA_B => SUMMAND(274), DATA_C => SUMMAND(275), SAVE => INT_SUM(231), CARRY => INT_CARRY(189) ); ---- End FA stage ---- Begin FA stage FA_193:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(276), DATA_B => SUMMAND(277), DATA_C => INT_CARRY(182), SAVE => INT_SUM(232), CARRY => INT_CARRY(190) ); ---- End FA stage ---- Begin NO stage INT_SUM(233) <= INT_CARRY(183); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_194:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(230), DATA_B => INT_SUM(231), DATA_C => INT_SUM(232), SAVE => INT_SUM(234), CARRY => INT_CARRY(191) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(233), DATA_B => INT_CARRY(184), SAVE => INT_SUM(235), CARRY => INT_CARRY(192) ); ---- End HA stage ---- Begin FA stage FA_195:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(234), DATA_B => INT_SUM(235), DATA_C => INT_CARRY(185), SAVE => INT_SUM(236), CARRY => INT_CARRY(193) ); ---- End FA stage ---- Begin NO stage INT_SUM(237) <= INT_CARRY(186); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_196:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_CARRY(187), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End FA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_197:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280), SAVE => INT_SUM(238), CARRY => INT_CARRY(194) ); ---- End FA stage ---- Begin FA stage FA_198:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283), SAVE => INT_SUM(239), CARRY => INT_CARRY(195) ); ---- End FA stage ---- Begin NO stage INT_SUM(240) <= SUMMAND(284); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_199:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(238), DATA_B => INT_SUM(239), DATA_C => INT_SUM(240), SAVE => INT_SUM(241), CARRY => INT_CARRY(196) ); ---- End FA stage ---- Begin FA stage FA_200:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190), SAVE => INT_SUM(242), CARRY => INT_CARRY(197) ); ---- End FA stage ---- Begin FA stage FA_201:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(241), DATA_B => INT_SUM(242), DATA_C => INT_CARRY(191), SAVE => INT_SUM(243), CARRY => INT_CARRY(198) ); ---- End FA stage ---- Begin NO stage INT_SUM(244) <= INT_CARRY(192); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_202:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(243), DATA_B => INT_SUM(244), DATA_C => INT_CARRY(193), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_203:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(285), DATA_B => SUMMAND(286), DATA_C => SUMMAND(287), SAVE => INT_SUM(245), CARRY => INT_CARRY(199) ); ---- End FA stage ---- Begin FA stage FA_204:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290), SAVE => INT_SUM(246), CARRY => INT_CARRY(200) ); ---- End FA stage ---- Begin NO stage INT_SUM(247) <= SUMMAND(291); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_205:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(245), DATA_B => INT_SUM(246), DATA_C => INT_SUM(247), SAVE => INT_SUM(248), CARRY => INT_CARRY(201) ); ---- End FA stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(194), DATA_B => INT_CARRY(195), SAVE => INT_SUM(249), CARRY => INT_CARRY(202) ); ---- End HA stage ---- Begin FA stage FA_206:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(248), DATA_B => INT_SUM(249), DATA_C => INT_CARRY(196), SAVE => INT_SUM(250), CARRY => INT_CARRY(203) ); ---- End FA stage ---- Begin NO stage INT_SUM(251) <= INT_CARRY(197); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_207:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(250), DATA_B => INT_SUM(251), DATA_C => INT_CARRY(198), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End FA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin FA stage FA_208:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(292), DATA_B => SUMMAND(293), DATA_C => SUMMAND(294), SAVE => INT_SUM(252), CARRY => INT_CARRY(204) ); ---- End FA stage ---- Begin FA stage FA_209:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(295), DATA_B => SUMMAND(296), DATA_C => SUMMAND(297), SAVE => INT_SUM(253), CARRY => INT_CARRY(205) ); ---- End FA stage ---- Begin FA stage FA_210:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(252), DATA_B => INT_SUM(253), DATA_C => INT_CARRY(199), SAVE => INT_SUM(254), CARRY => INT_CARRY(206) ); ---- End FA stage ---- Begin NO stage INT_SUM(255) <= INT_CARRY(200); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_211:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_CARRY(201), SAVE => INT_SUM(256), CARRY => INT_CARRY(207) ); ---- End FA stage ---- Begin NO stage INT_SUM(257) <= INT_CARRY(202); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_212:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(256), DATA_B => INT_SUM(257), DATA_C => INT_CARRY(203), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin FA stage FA_213:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(298), DATA_B => SUMMAND(299), DATA_C => SUMMAND(300), SAVE => INT_SUM(258), CARRY => INT_CARRY(208) ); ---- End FA stage ---- Begin FA stage FA_214:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(301), DATA_B => SUMMAND(302), DATA_C => SUMMAND(303), SAVE => INT_SUM(259), CARRY => INT_CARRY(209) ); ---- End FA stage ---- Begin FA stage FA_215:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(258), DATA_B => INT_SUM(259), DATA_C => INT_CARRY(204), SAVE => INT_SUM(260), CARRY => INT_CARRY(210) ); ---- End FA stage ---- Begin NO stage INT_SUM(261) <= INT_CARRY(205); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_216:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(206), SAVE => INT_SUM(262), CARRY => INT_CARRY(211) ); ---- End FA stage ---- Begin HA stage HA_35:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(262), DATA_B => INT_CARRY(207), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End HA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin FA stage FA_217:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(304), DATA_B => SUMMAND(305), DATA_C => SUMMAND(306), SAVE => INT_SUM(263), CARRY => INT_CARRY(212) ); ---- End FA stage ---- Begin HA stage HA_36:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(307), DATA_B => SUMMAND(308), SAVE => INT_SUM(264), CARRY => INT_CARRY(213) ); ---- End HA stage ---- Begin FA stage FA_218:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(263), DATA_B => INT_SUM(264), DATA_C => INT_CARRY(208), SAVE => INT_SUM(265), CARRY => INT_CARRY(214) ); ---- End FA stage ---- Begin NO stage INT_SUM(266) <= INT_CARRY(209); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_219:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(210), SAVE => INT_SUM(267), CARRY => INT_CARRY(215) ); ---- End FA stage ---- Begin HA stage HA_37:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(267), DATA_B => INT_CARRY(211), SAVE => SUM(42), CARRY => CARRY(42) ); ---- End HA stage -- End WT-branch 43 -- Begin WT-branch 44 ---- Begin FA stage FA_220:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311), SAVE => INT_SUM(268), CARRY => INT_CARRY(216) ); ---- End FA stage ---- Begin HA stage HA_38:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), SAVE => INT_SUM(269), CARRY => INT_CARRY(217) ); ---- End HA stage ---- Begin FA stage FA_221:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(268), DATA_B => INT_SUM(269), DATA_C => INT_CARRY(212), SAVE => INT_SUM(270), CARRY => INT_CARRY(218) ); ---- End FA stage ---- Begin NO stage INT_SUM(271) <= INT_CARRY(213); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_222:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(270), DATA_B => INT_SUM(271), DATA_C => INT_CARRY(214), SAVE => INT_SUM(272), CARRY => INT_CARRY(219) ); ---- End FA stage ---- Begin HA stage HA_39:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(272), DATA_B => INT_CARRY(215), SAVE => SUM(43), CARRY => CARRY(43) ); ---- End HA stage -- End WT-branch 44 -- Begin WT-branch 45 ---- Begin FA stage FA_223:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(314), DATA_B => SUMMAND(315), DATA_C => SUMMAND(316), SAVE => INT_SUM(273), CARRY => INT_CARRY(220) ); ---- End FA stage ---- Begin FA stage FA_224:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(317), DATA_B => INT_CARRY(216), DATA_C => INT_CARRY(217), SAVE => INT_SUM(274), CARRY => INT_CARRY(221) ); ---- End FA stage ---- Begin FA stage FA_225:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(273), DATA_B => INT_SUM(274), DATA_C => INT_CARRY(218), SAVE => INT_SUM(275), CARRY => INT_CARRY(222) ); ---- End FA stage ---- Begin HA stage HA_40:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(275), DATA_B => INT_CARRY(219), SAVE => SUM(44), CARRY => CARRY(44) ); ---- End HA stage -- End WT-branch 45 -- Begin WT-branch 46 ---- Begin FA stage FA_226:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320), SAVE => INT_SUM(276), CARRY => INT_CARRY(223) ); ---- End FA stage ---- Begin NO stage INT_SUM(277) <= SUMMAND(321); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_227:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(276), DATA_B => INT_SUM(277), DATA_C => INT_CARRY(220), SAVE => INT_SUM(278), CARRY => INT_CARRY(224) ); ---- End FA stage ---- Begin NO stage INT_SUM(279) <= INT_CARRY(221); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_228:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(278), DATA_B => INT_SUM(279), DATA_C => INT_CARRY(222), SAVE => SUM(45), CARRY => CARRY(45) ); ---- End FA stage -- End WT-branch 46 -- Begin WT-branch 47 ---- Begin FA stage FA_229:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(322), DATA_B => SUMMAND(323), DATA_C => SUMMAND(324), SAVE => INT_SUM(280), CARRY => INT_CARRY(225) ); ---- End FA stage ---- Begin NO stage INT_SUM(281) <= INT_SUM(280); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(282) <= INT_CARRY(223); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_230:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(281), DATA_B => INT_SUM(282), DATA_C => INT_CARRY(224), SAVE => SUM(46), CARRY => CARRY(46) ); ---- End FA stage -- End WT-branch 47 -- Begin WT-branch 48 ---- Begin FA stage FA_231:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(325), DATA_B => SUMMAND(326), DATA_C => SUMMAND(327), SAVE => INT_SUM(283), CARRY => INT_CARRY(226) ); ---- End FA stage ---- Begin NO stage INT_SUM(284) <= INT_CARRY(225); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_41:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(283), DATA_B => INT_SUM(284), SAVE => SUM(47), CARRY => CARRY(47) ); ---- End HA stage -- End WT-branch 48 -- Begin WT-branch 49 ---- Begin NO stage INT_SUM(285) <= SUMMAND(328); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(286) <= SUMMAND(329); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_232:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(285), DATA_B => INT_SUM(286), DATA_C => INT_CARRY(226), SAVE => SUM(48), CARRY => CARRY(48) ); ---- End FA stage -- End WT-branch 49 -- Begin WT-branch 50 ---- Begin HA stage HA_42:HALF_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(330), DATA_B => SUMMAND(331), SAVE => SUM(49), CARRY => CARRY(49) ); ---- End HA stage -- End WT-branch 50 -- Begin WT-branch 51 ---- Begin NO stage SUM(50) <= SUMMAND(332); -- At Level 5 ---- End NO stage -- End WT-branch 51 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_18 is port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_34_18; ------------------------------------------------------------ -- End: Multiplier Entitiy architecture MULTIPLIER of MULTIPLIER_34_18 is signal PPBIT:std_logic_vector(0 to 332); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_18 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 17) => MULTIPLIER(0 to 17), SUMMAND(0 to 332) => PPBIT(0 to 332) ); W:WALLACE_34_18 port map ( SUMMAND(0 to 332) => PPBIT(0 to 332), CARRY(0 to 49) => INT_CARRY(1 to 50), SUM(0 to 50) => INT_SUM(0 to 50) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUM(0 to 63), OPB(0 to 63) => INT_CARRY(0 to 63), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ -- -- Modgen multiplier created Fri Aug 16 16:29:15 2002 -- ------------------------------------------------------------ -- START: Multiplier Entitiy ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -- START: Top entity ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_17 is port(X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(16 downto 0); P: out std_logic_vector(49 downto 0)); end MUL_33_17; library ieee; use ieee.std_logic_1164.all; architecture A of MUL_33_17 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 17); signal Q: std_logic_vector(0 to 63); signal CLK: std_logic; begin U1: MULTIPLIER_34_18 port map(A,B,CLK,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(16); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); P(42) <= Q(42); P(43) <= Q(43); P(44) <= Q(44); P(45) <= Q(45); P(46) <= Q(46); P(47) <= Q(47); P(48) <= Q(48); P(49) <= Q(49); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_34 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 33); SUMMAND: out std_logic_vector(0 to 628) ); end BOOTHCODER_34_34; architecture BOOTHCODER of BOOTHCODER_34_34 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 67); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(110) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(120) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(132) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(143) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(156) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(168) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(182) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(195) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(210) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(224) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(240) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(255) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(272) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(288) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(306) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(323) ); SUMMAND(324) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(100) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(111) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(121) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(133) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(144) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(157) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(169) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(183) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(196) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(211) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(225) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(241) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(256) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(273) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(289) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(307) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(325) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(341) ); SUMMAND(342) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(358) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(101) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(112) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(122) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(134) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(145) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(158) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(170) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(184) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(197) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(212) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(226) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(242) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(257) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(274) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(290) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(308) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(326) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(343) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(359) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(374) ); SUMMAND(375) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(390) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(102) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(113) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(123) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(135) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(146) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(159) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(171) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(185) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(198) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(213) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(227) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(243) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(258) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(275) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(291) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(309) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(327) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(344) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(360) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(376) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(391) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(405) ); SUMMAND(406) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(420) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(103) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(114) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(124) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(136) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(147) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(172) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(186) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(199) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(214) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(228) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(244) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(259) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(276) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(292) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(310) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(328) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(345) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(361) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(377) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(392) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(407) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(421) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(434) ); SUMMAND(435) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(448) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_165:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_166:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_167:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_168:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_169:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_170:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_171:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_172:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(104) ); PPM_173:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(115) ); PPM_174:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(125) ); PPM_175:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(137) ); PPM_176:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(148) ); PPM_177:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(161) ); PPM_178:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(173) ); PPM_179:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(187) ); PPM_180:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(200) ); PPM_181:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(215) ); PPM_182:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(229) ); PPM_183:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(245) ); PPM_184:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(260) ); PPM_185:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(277) ); PPM_186:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(293) ); PPM_187:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(311) ); PPM_188:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(329) ); PPM_189:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(346) ); PPM_190:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(362) ); PPM_191:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(378) ); PPM_192:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(393) ); PPM_193:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(408) ); PPM_194:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(422) ); PPM_195:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(436) ); PPM_196:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(449) ); PPM_197:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(461) ); SUMMAND(462) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(474) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_198:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_199:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_200:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_201:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_202:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_203:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(105) ); PPM_204:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(116) ); PPM_205:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(126) ); PPM_206:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(138) ); PPM_207:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(149) ); PPM_208:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(162) ); PPM_209:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(174) ); PPM_210:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(188) ); PPM_211:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(201) ); PPM_212:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(216) ); PPM_213:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(230) ); PPM_214:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(246) ); PPM_215:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(261) ); PPM_216:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(278) ); PPM_217:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(294) ); PPM_218:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(312) ); PPM_219:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(330) ); PPM_220:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(347) ); PPM_221:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(363) ); PPM_222:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(379) ); PPM_223:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(394) ); PPM_224:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(409) ); PPM_225:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(423) ); PPM_226:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(437) ); PPM_227:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(450) ); PPM_228:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(463) ); PPM_229:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(475) ); PPM_230:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(486) ); SUMMAND(487) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(498) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_231:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_232:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_233:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_234:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(106) ); PPM_235:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(117) ); PPM_236:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(127) ); PPM_237:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(139) ); PPM_238:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(150) ); PPM_239:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(163) ); PPM_240:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(175) ); PPM_241:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(189) ); PPM_242:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(202) ); PPM_243:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(217) ); PPM_244:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(231) ); PPM_245:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(247) ); PPM_246:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(262) ); PPM_247:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(279) ); PPM_248:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(295) ); PPM_249:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(313) ); PPM_250:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(331) ); PPM_251:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(348) ); PPM_252:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(364) ); PPM_253:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(380) ); PPM_254:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(395) ); PPM_255:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(410) ); PPM_256:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(424) ); PPM_257:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(438) ); PPM_258:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(451) ); PPM_259:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(464) ); PPM_260:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(476) ); PPM_261:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(488) ); PPM_262:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(499) ); PPM_263:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(509) ); SUMMAND(510) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(520) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_264:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_265:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(107) ); PPM_266:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(118) ); PPM_267:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(128) ); PPM_268:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(140) ); PPM_269:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(151) ); PPM_270:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(164) ); PPM_271:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(176) ); PPM_272:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(190) ); PPM_273:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(203) ); PPM_274:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(218) ); PPM_275:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(232) ); PPM_276:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(248) ); PPM_277:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(263) ); PPM_278:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(280) ); PPM_279:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(296) ); PPM_280:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(314) ); PPM_281:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(332) ); PPM_282:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(349) ); PPM_283:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(365) ); PPM_284:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(381) ); PPM_285:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(396) ); PPM_286:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(411) ); PPM_287:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(425) ); PPM_288:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(439) ); PPM_289:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(452) ); PPM_290:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(465) ); PPM_291:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(477) ); PPM_292:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(489) ); PPM_293:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(500) ); PPM_294:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(511) ); PPM_295:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(521) ); PPM_296:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(530) ); SUMMAND(531) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(540) ); -- Begin partial product 9 -- Begin decoder block 10 DEC_9:DECODER -- Decoder of multiplier operand port map ( INA => OPB(17),INB => OPB(18),INC => OPB(19), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39) ); -- End decoder block 10 -- Begin partial product 10 PPL_9:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(108) ); RGATE_9:R_GATE port map ( INA => OPB(17),INB => OPB(18),INC => OPB(19), PPBIT => SUMMAND(109) ); PPM_297:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(119) ); PPM_298:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(129) ); PPM_299:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(141) ); PPM_300:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(152) ); PPM_301:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(165) ); PPM_302:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(177) ); PPM_303:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(191) ); PPM_304:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(204) ); PPM_305:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(219) ); PPM_306:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(233) ); PPM_307:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(249) ); PPM_308:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(264) ); PPM_309:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(281) ); PPM_310:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(297) ); PPM_311:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(315) ); PPM_312:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(333) ); PPM_313:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(350) ); PPM_314:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(366) ); PPM_315:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(382) ); PPM_316:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(397) ); PPM_317:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(412) ); PPM_318:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(426) ); PPM_319:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(440) ); PPM_320:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(453) ); PPM_321:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(466) ); PPM_322:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(478) ); PPM_323:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(490) ); PPM_324:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(501) ); PPM_325:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(512) ); PPM_326:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(522) ); PPM_327:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(532) ); PPM_328:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(541) ); PPM_329:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(549) ); SUMMAND(550) <= LOGIC_ONE; PPH_9:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(558) ); -- Begin partial product 10 -- Begin decoder block 11 DEC_10:DECODER -- Decoder of multiplier operand port map ( INA => OPB(19),INB => OPB(20),INC => OPB(21), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43) ); -- End decoder block 11 -- Begin partial product 11 PPL_10:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(130) ); RGATE_10:R_GATE port map ( INA => OPB(19),INB => OPB(20),INC => OPB(21), PPBIT => SUMMAND(131) ); PPM_330:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(142) ); PPM_331:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(153) ); PPM_332:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(166) ); PPM_333:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(178) ); PPM_334:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(192) ); PPM_335:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(205) ); PPM_336:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(220) ); PPM_337:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(234) ); PPM_338:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(250) ); PPM_339:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(265) ); PPM_340:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(282) ); PPM_341:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(298) ); PPM_342:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(316) ); PPM_343:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(334) ); PPM_344:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(351) ); PPM_345:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(367) ); PPM_346:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(383) ); PPM_347:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(398) ); PPM_348:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(413) ); PPM_349:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(427) ); PPM_350:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(441) ); PPM_351:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(454) ); PPM_352:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(467) ); PPM_353:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(479) ); PPM_354:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(491) ); PPM_355:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(502) ); PPM_356:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(513) ); PPM_357:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(523) ); PPM_358:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(533) ); PPM_359:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(542) ); PPM_360:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(551) ); PPM_361:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(559) ); PPM_362:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(566) ); SUMMAND(567) <= LOGIC_ONE; PPH_10:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(574) ); -- Begin partial product 11 -- Begin decoder block 12 DEC_11:DECODER -- Decoder of multiplier operand port map ( INA => OPB(21),INB => OPB(22),INC => OPB(23), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47) ); -- End decoder block 12 -- Begin partial product 12 PPL_11:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(154) ); RGATE_11:R_GATE port map ( INA => OPB(21),INB => OPB(22),INC => OPB(23), PPBIT => SUMMAND(155) ); PPM_363:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(167) ); PPM_364:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(179) ); PPM_365:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(193) ); PPM_366:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(206) ); PPM_367:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(221) ); PPM_368:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(235) ); PPM_369:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(251) ); PPM_370:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(266) ); PPM_371:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(283) ); PPM_372:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(299) ); PPM_373:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(317) ); PPM_374:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(335) ); PPM_375:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(352) ); PPM_376:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(368) ); PPM_377:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(384) ); PPM_378:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(399) ); PPM_379:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(414) ); PPM_380:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(428) ); PPM_381:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(442) ); PPM_382:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(455) ); PPM_383:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(468) ); PPM_384:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(480) ); PPM_385:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(492) ); PPM_386:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(503) ); PPM_387:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(514) ); PPM_388:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(524) ); PPM_389:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(534) ); PPM_390:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(543) ); PPM_391:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(552) ); PPM_392:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(560) ); PPM_393:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(568) ); PPM_394:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(575) ); PPM_395:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(581) ); SUMMAND(582) <= LOGIC_ONE; PPH_11:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(588) ); -- Begin partial product 12 -- Begin decoder block 13 DEC_12:DECODER -- Decoder of multiplier operand port map ( INA => OPB(23),INB => OPB(24),INC => OPB(25), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51) ); -- End decoder block 13 -- Begin partial product 13 PPL_12:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(180) ); RGATE_12:R_GATE port map ( INA => OPB(23),INB => OPB(24),INC => OPB(25), PPBIT => SUMMAND(181) ); PPM_396:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(194) ); PPM_397:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(207) ); PPM_398:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(222) ); PPM_399:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(236) ); PPM_400:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(252) ); PPM_401:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(267) ); PPM_402:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(284) ); PPM_403:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(300) ); PPM_404:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(318) ); PPM_405:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(336) ); PPM_406:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(353) ); PPM_407:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(369) ); PPM_408:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(385) ); PPM_409:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(400) ); PPM_410:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(415) ); PPM_411:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(429) ); PPM_412:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(443) ); PPM_413:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(456) ); PPM_414:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(469) ); PPM_415:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(481) ); PPM_416:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(493) ); PPM_417:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(504) ); PPM_418:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(515) ); PPM_419:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(525) ); PPM_420:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(535) ); PPM_421:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(544) ); PPM_422:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(553) ); PPM_423:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(561) ); PPM_424:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(569) ); PPM_425:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(576) ); PPM_426:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(583) ); PPM_427:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(589) ); PPM_428:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(594) ); SUMMAND(595) <= LOGIC_ONE; PPH_12:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(600) ); -- Begin partial product 13 -- Begin decoder block 14 DEC_13:DECODER -- Decoder of multiplier operand port map ( INA => OPB(25),INB => OPB(26),INC => OPB(27), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55) ); -- End decoder block 14 -- Begin partial product 14 PPL_13:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(208) ); RGATE_13:R_GATE port map ( INA => OPB(25),INB => OPB(26),INC => OPB(27), PPBIT => SUMMAND(209) ); PPM_429:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(223) ); PPM_430:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(237) ); PPM_431:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(253) ); PPM_432:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(268) ); PPM_433:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(285) ); PPM_434:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(301) ); PPM_435:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(319) ); PPM_436:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(337) ); PPM_437:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(354) ); PPM_438:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(370) ); PPM_439:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(386) ); PPM_440:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(401) ); PPM_441:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(416) ); PPM_442:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(430) ); PPM_443:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(444) ); PPM_444:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(457) ); PPM_445:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(470) ); PPM_446:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(482) ); PPM_447:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(494) ); PPM_448:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(505) ); PPM_449:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(516) ); PPM_450:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(526) ); PPM_451:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(536) ); PPM_452:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(545) ); PPM_453:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(554) ); PPM_454:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(562) ); PPM_455:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(570) ); PPM_456:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(577) ); PPM_457:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(584) ); PPM_458:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(590) ); PPM_459:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(596) ); PPM_460:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(601) ); PPM_461:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(605) ); SUMMAND(606) <= LOGIC_ONE; PPH_13:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(610) ); -- Begin partial product 14 -- Begin decoder block 15 DEC_14:DECODER -- Decoder of multiplier operand port map ( INA => OPB(27),INB => OPB(28),INC => OPB(29), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59) ); -- End decoder block 15 -- Begin partial product 15 PPL_14:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(238) ); RGATE_14:R_GATE port map ( INA => OPB(27),INB => OPB(28),INC => OPB(29), PPBIT => SUMMAND(239) ); PPM_462:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(254) ); PPM_463:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(269) ); PPM_464:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(286) ); PPM_465:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(302) ); PPM_466:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(320) ); PPM_467:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(338) ); PPM_468:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(355) ); PPM_469:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(371) ); PPM_470:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(387) ); PPM_471:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(402) ); PPM_472:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(417) ); PPM_473:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(431) ); PPM_474:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(445) ); PPM_475:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(458) ); PPM_476:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(471) ); PPM_477:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(483) ); PPM_478:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(495) ); PPM_479:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(506) ); PPM_480:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(517) ); PPM_481:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(527) ); PPM_482:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(537) ); PPM_483:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(546) ); PPM_484:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(555) ); PPM_485:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(563) ); PPM_486:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(571) ); PPM_487:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(578) ); PPM_488:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(585) ); PPM_489:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(591) ); PPM_490:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(597) ); PPM_491:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(602) ); PPM_492:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(607) ); PPM_493:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(611) ); PPM_494:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(614) ); SUMMAND(615) <= LOGIC_ONE; PPH_14:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(618) ); -- Begin partial product 15 -- Begin decoder block 16 DEC_15:DECODER -- Decoder of multiplier operand port map ( INA => OPB(29),INB => OPB(30),INC => OPB(31), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63) ); -- End decoder block 16 -- Begin partial product 16 PPL_15:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(270) ); RGATE_15:R_GATE port map ( INA => OPB(29),INB => OPB(30),INC => OPB(31), PPBIT => SUMMAND(271) ); PPM_495:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(287) ); PPM_496:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(303) ); PPM_497:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(321) ); PPM_498:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(339) ); PPM_499:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(356) ); PPM_500:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(372) ); PPM_501:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(388) ); PPM_502:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(403) ); PPM_503:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(418) ); PPM_504:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(432) ); PPM_505:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(446) ); PPM_506:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(459) ); PPM_507:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(472) ); PPM_508:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(484) ); PPM_509:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(496) ); PPM_510:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(507) ); PPM_511:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(518) ); PPM_512:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(528) ); PPM_513:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(538) ); PPM_514:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(547) ); PPM_515:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(556) ); PPM_516:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(564) ); PPM_517:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(572) ); PPM_518:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(579) ); PPM_519:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(586) ); PPM_520:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(592) ); PPM_521:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(598) ); PPM_522:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(603) ); PPM_523:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(608) ); PPM_524:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(612) ); PPM_525:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(616) ); PPM_526:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(619) ); PPM_527:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(621) ); SUMMAND(622) <= LOGIC_ONE; PPH_15:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(624) ); -- Begin partial product 16 -- Begin decoder block 17 DEC_16:DECODER -- Decoder of multiplier operand port map ( INA => OPB(31),INB => OPB(32),INC => OPB(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67) ); -- End decoder block 17 -- Begin partial product 17 PPL_16:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(304) ); RGATE_16:R_GATE port map ( INA => OPB(31),INB => OPB(32),INC => OPB(33), PPBIT => SUMMAND(305) ); PPM_528:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(322) ); PPM_529:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(340) ); PPM_530:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(357) ); PPM_531:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(373) ); PPM_532:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(389) ); PPM_533:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(404) ); PPM_534:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(419) ); PPM_535:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(433) ); PPM_536:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(447) ); PPM_537:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(460) ); PPM_538:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(473) ); PPM_539:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(485) ); PPM_540:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(497) ); PPM_541:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(508) ); PPM_542:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(519) ); PPM_543:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(529) ); PPM_544:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(539) ); PPM_545:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(548) ); PPM_546:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(557) ); PPM_547:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(565) ); PPM_548:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(573) ); PPM_549:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(580) ); PPM_550:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(587) ); PPM_551:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(593) ); PPM_552:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(599) ); PPM_553:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(604) ); PPM_554:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(609) ); PPM_555:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(613) ); PPM_556:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(617) ); PPM_557:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(620) ); PPM_558:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(623) ); PPM_559:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(625) ); PPM_560:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(626) ); SUMMAND(627) <= LOGIC_ONE; PPH_16:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(628) ); -- Begin partial product 17 end BOOTHCODER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_34 is port ( SUMMAND: in std_logic_vector(0 to 628); CARRY: out std_logic_vector(0 to 65); SUM: out std_logic_vector(0 to 66) ); end WALLACE_34_34; architecture WALLACE of WALLACE_34_34 is -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 486); signal INT_SUM: std_logic_vector(0 to 620); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin NO stage INT_SUM(76) <= SUMMAND(108); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(77) <= SUMMAND(109); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(78), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(49), SAVE => INT_SUM(79), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin NO stage INT_SUM(80) <= INT_CARRY(50); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(81) <= INT_CARRY(51); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_SUM(80), SAVE => INT_SUM(82), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(81), DATA_B => INT_CARRY(52), DATA_C => INT_CARRY(53), SAVE => INT_SUM(83), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin FA stage FA_64:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(54), SAVE => INT_SUM(84), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(84), DATA_B => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End HA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_65:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112), SAVE => INT_SUM(85), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), DATA_C => SUMMAND(115), SAVE => INT_SUM(86), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(116), DATA_B => SUMMAND(117), DATA_C => SUMMAND(118), SAVE => INT_SUM(87), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin NO stage INT_SUM(88) <= SUMMAND(119); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(56), DATA_C => INT_CARRY(57), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(91) <= INT_CARRY(58); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91), SAVE => INT_SUM(92), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(59), DATA_B => INT_CARRY(60), SAVE => INT_SUM(93), CARRY => INT_CARRY(70) ); ---- End HA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(61), SAVE => INT_SUM(94), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(62); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(63), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End FA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125), SAVE => INT_SUM(97), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(98), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(99), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_SUM(98), SAVE => INT_SUM(100), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(99), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65), SAVE => INT_SUM(101), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin NO stage INT_SUM(102) <= INT_CARRY(66); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_79:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_SUM(102), SAVE => INT_SUM(103), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(67), DATA_B => INT_CARRY(68), SAVE => INT_SUM(104), CARRY => INT_CARRY(79) ); ---- End HA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(103), DATA_B => INT_SUM(104), DATA_C => INT_CARRY(69), SAVE => INT_SUM(105), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin NO stage INT_SUM(106) <= INT_CARRY(70); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_CARRY(71), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_82:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134), SAVE => INT_SUM(107), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(108), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140), SAVE => INT_SUM(109), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(110) <= SUMMAND(141); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(111) <= SUMMAND(142); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_85:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(107), DATA_B => INT_SUM(108), DATA_C => INT_SUM(109), SAVE => INT_SUM(112), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(72), SAVE => INT_SUM(113), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(73), DATA_B => INT_CARRY(74), DATA_C => INT_CARRY(75), SAVE => INT_SUM(114), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_SUM(114), SAVE => INT_SUM(115), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), SAVE => INT_SUM(116), CARRY => INT_CARRY(88) ); ---- End HA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(78), SAVE => INT_SUM(117), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(118) <= INT_CARRY(79); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_CARRY(80), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_91:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), DATA_C => SUMMAND(145), SAVE => INT_SUM(119), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(146), DATA_B => SUMMAND(147), DATA_C => SUMMAND(148), SAVE => INT_SUM(120), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(149), DATA_B => SUMMAND(150), DATA_C => SUMMAND(151), SAVE => INT_SUM(121), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(152), DATA_B => SUMMAND(153), DATA_C => SUMMAND(154), SAVE => INT_SUM(122), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= SUMMAND(155); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(119), DATA_B => INT_SUM(120), DATA_C => INT_SUM(121), SAVE => INT_SUM(124), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(81), SAVE => INT_SUM(125), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83), SAVE => INT_SUM(126), CARRY => INT_CARRY(96) ); ---- End HA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_SUM(126), SAVE => INT_SUM(127), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86), SAVE => INT_SUM(128), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin FA stage FA_99:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(127), DATA_B => INT_SUM(128), DATA_C => INT_CARRY(87), SAVE => INT_SUM(129), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin NO stage INT_SUM(130) <= INT_CARRY(88); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_CARRY(89), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_101:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158), SAVE => INT_SUM(131), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161), SAVE => INT_SUM(132), CARRY => INT_CARRY(101) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164), SAVE => INT_SUM(133), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(134), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin FA stage FA_105:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(131), DATA_B => INT_SUM(132), DATA_C => INT_SUM(133), SAVE => INT_SUM(135), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin FA stage FA_106:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(134), DATA_B => INT_CARRY(90), DATA_C => INT_CARRY(91), SAVE => INT_SUM(136), CARRY => INT_CARRY(105) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(92), DATA_B => INT_CARRY(93), SAVE => INT_SUM(137), CARRY => INT_CARRY(106) ); ---- End HA stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_SUM(137), SAVE => INT_SUM(138), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin FA stage FA_108:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(94), DATA_B => INT_CARRY(95), DATA_C => INT_CARRY(96), SAVE => INT_SUM(139), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(138), DATA_B => INT_SUM(139), DATA_C => INT_CARRY(97), SAVE => INT_SUM(140), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin NO stage INT_SUM(141) <= INT_CARRY(98); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(99), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_111:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170), SAVE => INT_SUM(142), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173), SAVE => INT_SUM(143), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin FA stage FA_113:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(144), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin FA stage FA_114:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(145), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), SAVE => INT_SUM(146), CARRY => INT_CARRY(114) ); ---- End HA stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_SUM(144), SAVE => INT_SUM(147), CARRY => INT_CARRY(115) ); ---- End FA stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(100), SAVE => INT_SUM(148), CARRY => INT_CARRY(116) ); ---- End FA stage ---- Begin FA stage FA_117:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(101), DATA_B => INT_CARRY(102), DATA_C => INT_CARRY(103), SAVE => INT_SUM(149), CARRY => INT_CARRY(117) ); ---- End FA stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(147), DATA_B => INT_SUM(148), DATA_C => INT_SUM(149), SAVE => INT_SUM(150), CARRY => INT_CARRY(118) ); ---- End FA stage ---- Begin FA stage FA_119:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(104), DATA_B => INT_CARRY(105), DATA_C => INT_CARRY(106), SAVE => INT_SUM(151), CARRY => INT_CARRY(119) ); ---- End FA stage ---- Begin FA stage FA_120:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(107), SAVE => INT_SUM(152), CARRY => INT_CARRY(120) ); ---- End FA stage ---- Begin NO stage INT_SUM(153) <= INT_CARRY(108); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_121:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(152), DATA_B => INT_SUM(153), DATA_C => INT_CARRY(109), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_122:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), DATA_C => SUMMAND(184), SAVE => INT_SUM(154), CARRY => INT_CARRY(121) ); ---- End FA stage ---- Begin FA stage FA_123:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(185), DATA_B => SUMMAND(186), DATA_C => SUMMAND(187), SAVE => INT_SUM(155), CARRY => INT_CARRY(122) ); ---- End FA stage ---- Begin FA stage FA_124:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(188), DATA_B => SUMMAND(189), DATA_C => SUMMAND(190), SAVE => INT_SUM(156), CARRY => INT_CARRY(123) ); ---- End FA stage ---- Begin FA stage FA_125:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(191), DATA_B => SUMMAND(192), DATA_C => SUMMAND(193), SAVE => INT_SUM(157), CARRY => INT_CARRY(124) ); ---- End FA stage ---- Begin NO stage INT_SUM(158) <= SUMMAND(194); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_126:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(154), DATA_B => INT_SUM(155), DATA_C => INT_SUM(156), SAVE => INT_SUM(159), CARRY => INT_CARRY(125) ); ---- End FA stage ---- Begin FA stage FA_127:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(110), SAVE => INT_SUM(160), CARRY => INT_CARRY(126) ); ---- End FA stage ---- Begin FA stage FA_128:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(111), DATA_B => INT_CARRY(112), DATA_C => INT_CARRY(113), SAVE => INT_SUM(161), CARRY => INT_CARRY(127) ); ---- End FA stage ---- Begin NO stage INT_SUM(162) <= INT_CARRY(114); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_129:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(159), DATA_B => INT_SUM(160), DATA_C => INT_SUM(161), SAVE => INT_SUM(163), CARRY => INT_CARRY(128) ); ---- End FA stage ---- Begin FA stage FA_130:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(162), DATA_B => INT_CARRY(115), DATA_C => INT_CARRY(116), SAVE => INT_SUM(164), CARRY => INT_CARRY(129) ); ---- End FA stage ---- Begin NO stage INT_SUM(165) <= INT_CARRY(117); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_131:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(163), DATA_B => INT_SUM(164), DATA_C => INT_SUM(165), SAVE => INT_SUM(166), CARRY => INT_CARRY(130) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(118), DATA_B => INT_CARRY(119), SAVE => INT_SUM(167), CARRY => INT_CARRY(131) ); ---- End HA stage ---- Begin FA stage FA_132:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(120), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End FA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_133:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197), SAVE => INT_SUM(168), CARRY => INT_CARRY(132) ); ---- End FA stage ---- Begin FA stage FA_134:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200), SAVE => INT_SUM(169), CARRY => INT_CARRY(133) ); ---- End FA stage ---- Begin FA stage FA_135:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203), SAVE => INT_SUM(170), CARRY => INT_CARRY(134) ); ---- End FA stage ---- Begin FA stage FA_136:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206), SAVE => INT_SUM(171), CARRY => INT_CARRY(135) ); ---- End FA stage ---- Begin FA stage FA_137:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209), SAVE => INT_SUM(172), CARRY => INT_CARRY(136) ); ---- End FA stage ---- Begin FA stage FA_138:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(168), DATA_B => INT_SUM(169), DATA_C => INT_SUM(170), SAVE => INT_SUM(173), CARRY => INT_CARRY(137) ); ---- End FA stage ---- Begin FA stage FA_139:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(171), DATA_B => INT_SUM(172), DATA_C => INT_CARRY(121), SAVE => INT_SUM(174), CARRY => INT_CARRY(138) ); ---- End FA stage ---- Begin FA stage FA_140:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(122), DATA_B => INT_CARRY(123), DATA_C => INT_CARRY(124), SAVE => INT_SUM(175), CARRY => INT_CARRY(139) ); ---- End FA stage ---- Begin FA stage FA_141:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(173), DATA_B => INT_SUM(174), DATA_C => INT_SUM(175), SAVE => INT_SUM(176), CARRY => INT_CARRY(140) ); ---- End FA stage ---- Begin FA stage FA_142:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(125), DATA_B => INT_CARRY(126), DATA_C => INT_CARRY(127), SAVE => INT_SUM(177), CARRY => INT_CARRY(141) ); ---- End FA stage ---- Begin FA stage FA_143:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(176), DATA_B => INT_SUM(177), DATA_C => INT_CARRY(128), SAVE => INT_SUM(178), CARRY => INT_CARRY(142) ); ---- End FA stage ---- Begin NO stage INT_SUM(179) <= INT_CARRY(129); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_144:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(178), DATA_B => INT_SUM(179), DATA_C => INT_CARRY(130), SAVE => INT_SUM(180), CARRY => INT_CARRY(143) ); ---- End FA stage ---- Begin NO stage INT_SUM(181) <= INT_CARRY(131); -- At Level 5 ---- End NO stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_145:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212), SAVE => INT_SUM(182), CARRY => INT_CARRY(144) ); ---- End FA stage ---- Begin FA stage FA_146:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215), SAVE => INT_SUM(183), CARRY => INT_CARRY(145) ); ---- End FA stage ---- Begin FA stage FA_147:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218), SAVE => INT_SUM(184), CARRY => INT_CARRY(146) ); ---- End FA stage ---- Begin FA stage FA_148:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221), SAVE => INT_SUM(185), CARRY => INT_CARRY(147) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), SAVE => INT_SUM(186), CARRY => INT_CARRY(148) ); ---- End HA stage ---- Begin FA stage FA_149:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_SUM(184), SAVE => INT_SUM(187), CARRY => INT_CARRY(149) ); ---- End FA stage ---- Begin FA stage FA_150:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_CARRY(132), SAVE => INT_SUM(188), CARRY => INT_CARRY(150) ); ---- End FA stage ---- Begin FA stage FA_151:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135), SAVE => INT_SUM(189), CARRY => INT_CARRY(151) ); ---- End FA stage ---- Begin NO stage INT_SUM(190) <= INT_CARRY(136); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_152:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(187), DATA_B => INT_SUM(188), DATA_C => INT_SUM(189), SAVE => INT_SUM(191), CARRY => INT_CARRY(152) ); ---- End FA stage ---- Begin FA stage FA_153:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(190), DATA_B => INT_CARRY(137), DATA_C => INT_CARRY(138), SAVE => INT_SUM(192), CARRY => INT_CARRY(153) ); ---- End FA stage ---- Begin NO stage INT_SUM(193) <= INT_CARRY(139); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_154:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(191), DATA_B => INT_SUM(192), DATA_C => INT_SUM(193), SAVE => INT_SUM(194), CARRY => INT_CARRY(154) ); ---- End FA stage ---- Begin NO stage INT_SUM(195) <= INT_CARRY(140); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(196) <= INT_CARRY(141); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_155:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(194), DATA_B => INT_SUM(195), DATA_C => INT_SUM(196), SAVE => INT_SUM(197), CARRY => INT_CARRY(155) ); ---- End FA stage ---- Begin NO stage INT_SUM(198) <= INT_CARRY(142); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_156:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(197), DATA_B => INT_SUM(198), DATA_C => INT_CARRY(143), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End FA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_157:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(224), DATA_B => SUMMAND(225), DATA_C => SUMMAND(226), SAVE => INT_SUM(199), CARRY => INT_CARRY(156) ); ---- End FA stage ---- Begin FA stage FA_158:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(227), DATA_B => SUMMAND(228), DATA_C => SUMMAND(229), SAVE => INT_SUM(200), CARRY => INT_CARRY(157) ); ---- End FA stage ---- Begin FA stage FA_159:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(230), DATA_B => SUMMAND(231), DATA_C => SUMMAND(232), SAVE => INT_SUM(201), CARRY => INT_CARRY(158) ); ---- End FA stage ---- Begin FA stage FA_160:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(233), DATA_B => SUMMAND(234), DATA_C => SUMMAND(235), SAVE => INT_SUM(202), CARRY => INT_CARRY(159) ); ---- End FA stage ---- Begin FA stage FA_161:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(236), DATA_B => SUMMAND(237), DATA_C => SUMMAND(238), SAVE => INT_SUM(203), CARRY => INT_CARRY(160) ); ---- End FA stage ---- Begin NO stage INT_SUM(204) <= SUMMAND(239); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_162:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(199), DATA_B => INT_SUM(200), DATA_C => INT_SUM(201), SAVE => INT_SUM(205), CARRY => INT_CARRY(161) ); ---- End FA stage ---- Begin FA stage FA_163:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(202), DATA_B => INT_SUM(203), DATA_C => INT_SUM(204), SAVE => INT_SUM(206), CARRY => INT_CARRY(162) ); ---- End FA stage ---- Begin FA stage FA_164:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(144), DATA_B => INT_CARRY(145), DATA_C => INT_CARRY(146), SAVE => INT_SUM(207), CARRY => INT_CARRY(163) ); ---- End FA stage ---- Begin NO stage INT_SUM(208) <= INT_CARRY(147); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(209) <= INT_CARRY(148); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_165:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207), SAVE => INT_SUM(210), CARRY => INT_CARRY(164) ); ---- End FA stage ---- Begin FA stage FA_166:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_CARRY(149), SAVE => INT_SUM(211), CARRY => INT_CARRY(165) ); ---- End FA stage ---- Begin NO stage INT_SUM(212) <= INT_CARRY(150); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(213) <= INT_CARRY(151); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_167:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(210), DATA_B => INT_SUM(211), DATA_C => INT_SUM(212), SAVE => INT_SUM(214), CARRY => INT_CARRY(166) ); ---- End FA stage ---- Begin FA stage FA_168:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(213), DATA_B => INT_CARRY(152), DATA_C => INT_CARRY(153), SAVE => INT_SUM(215), CARRY => INT_CARRY(167) ); ---- End FA stage ---- Begin FA stage FA_169:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(214), DATA_B => INT_SUM(215), DATA_C => INT_CARRY(154), SAVE => INT_SUM(216), CARRY => INT_CARRY(168) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(216), DATA_B => INT_CARRY(155), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_170:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242), SAVE => INT_SUM(217), CARRY => INT_CARRY(169) ); ---- End FA stage ---- Begin FA stage FA_171:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245), SAVE => INT_SUM(218), CARRY => INT_CARRY(170) ); ---- End FA stage ---- Begin FA stage FA_172:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248), SAVE => INT_SUM(219), CARRY => INT_CARRY(171) ); ---- End FA stage ---- Begin FA stage FA_173:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251), SAVE => INT_SUM(220), CARRY => INT_CARRY(172) ); ---- End FA stage ---- Begin FA stage FA_174:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(252), DATA_B => SUMMAND(253), DATA_C => SUMMAND(254), SAVE => INT_SUM(221), CARRY => INT_CARRY(173) ); ---- End FA stage ---- Begin FA stage FA_175:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_SUM(219), SAVE => INT_SUM(222), CARRY => INT_CARRY(174) ); ---- End FA stage ---- Begin FA stage FA_176:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_CARRY(156), SAVE => INT_SUM(223), CARRY => INT_CARRY(175) ); ---- End FA stage ---- Begin FA stage FA_177:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(157), DATA_B => INT_CARRY(158), DATA_C => INT_CARRY(159), SAVE => INT_SUM(224), CARRY => INT_CARRY(176) ); ---- End FA stage ---- Begin NO stage INT_SUM(225) <= INT_CARRY(160); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_178:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(222), DATA_B => INT_SUM(223), DATA_C => INT_SUM(224), SAVE => INT_SUM(226), CARRY => INT_CARRY(177) ); ---- End FA stage ---- Begin FA stage FA_179:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(225), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162), SAVE => INT_SUM(227), CARRY => INT_CARRY(178) ); ---- End FA stage ---- Begin NO stage INT_SUM(228) <= INT_CARRY(163); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_180:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_SUM(228), SAVE => INT_SUM(229), CARRY => INT_CARRY(179) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(164), DATA_B => INT_CARRY(165), SAVE => INT_SUM(230), CARRY => INT_CARRY(180) ); ---- End HA stage ---- Begin FA stage FA_181:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(229), DATA_B => INT_SUM(230), DATA_C => INT_CARRY(166), SAVE => INT_SUM(231), CARRY => INT_CARRY(181) ); ---- End FA stage ---- Begin NO stage INT_SUM(232) <= INT_CARRY(167); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_182:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(231), DATA_B => INT_SUM(232), DATA_C => INT_CARRY(168), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_183:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(255), DATA_B => SUMMAND(256), DATA_C => SUMMAND(257), SAVE => INT_SUM(233), CARRY => INT_CARRY(182) ); ---- End FA stage ---- Begin FA stage FA_184:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(258), DATA_B => SUMMAND(259), DATA_C => SUMMAND(260), SAVE => INT_SUM(234), CARRY => INT_CARRY(183) ); ---- End FA stage ---- Begin FA stage FA_185:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(261), DATA_B => SUMMAND(262), DATA_C => SUMMAND(263), SAVE => INT_SUM(235), CARRY => INT_CARRY(184) ); ---- End FA stage ---- Begin FA stage FA_186:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(264), DATA_B => SUMMAND(265), DATA_C => SUMMAND(266), SAVE => INT_SUM(236), CARRY => INT_CARRY(185) ); ---- End FA stage ---- Begin FA stage FA_187:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(267), DATA_B => SUMMAND(268), DATA_C => SUMMAND(269), SAVE => INT_SUM(237), CARRY => INT_CARRY(186) ); ---- End FA stage ---- Begin NO stage INT_SUM(238) <= SUMMAND(270); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(239) <= SUMMAND(271); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_188:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(233), DATA_B => INT_SUM(234), DATA_C => INT_SUM(235), SAVE => INT_SUM(240), CARRY => INT_CARRY(187) ); ---- End FA stage ---- Begin FA stage FA_189:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_SUM(238), SAVE => INT_SUM(241), CARRY => INT_CARRY(188) ); ---- End FA stage ---- Begin FA stage FA_190:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(239), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170), SAVE => INT_SUM(242), CARRY => INT_CARRY(189) ); ---- End FA stage ---- Begin FA stage FA_191:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(171), DATA_B => INT_CARRY(172), DATA_C => INT_CARRY(173), SAVE => INT_SUM(243), CARRY => INT_CARRY(190) ); ---- End FA stage ---- Begin FA stage FA_192:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(240), DATA_B => INT_SUM(241), DATA_C => INT_SUM(242), SAVE => INT_SUM(244), CARRY => INT_CARRY(191) ); ---- End FA stage ---- Begin FA stage FA_193:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(243), DATA_B => INT_CARRY(174), DATA_C => INT_CARRY(175), SAVE => INT_SUM(245), CARRY => INT_CARRY(192) ); ---- End FA stage ---- Begin NO stage INT_SUM(246) <= INT_CARRY(176); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_194:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(244), DATA_B => INT_SUM(245), DATA_C => INT_SUM(246), SAVE => INT_SUM(247), CARRY => INT_CARRY(193) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(177), DATA_B => INT_CARRY(178), SAVE => INT_SUM(248), CARRY => INT_CARRY(194) ); ---- End HA stage ---- Begin FA stage FA_195:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(247), DATA_B => INT_SUM(248), DATA_C => INT_CARRY(179), SAVE => INT_SUM(249), CARRY => INT_CARRY(195) ); ---- End FA stage ---- Begin NO stage INT_SUM(250) <= INT_CARRY(180); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_196:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(249), DATA_B => INT_SUM(250), DATA_C => INT_CARRY(181), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_197:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(272), DATA_B => SUMMAND(273), DATA_C => SUMMAND(274), SAVE => INT_SUM(251), CARRY => INT_CARRY(196) ); ---- End FA stage ---- Begin FA stage FA_198:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(275), DATA_B => SUMMAND(276), DATA_C => SUMMAND(277), SAVE => INT_SUM(252), CARRY => INT_CARRY(197) ); ---- End FA stage ---- Begin FA stage FA_199:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280), SAVE => INT_SUM(253), CARRY => INT_CARRY(198) ); ---- End FA stage ---- Begin FA stage FA_200:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283), SAVE => INT_SUM(254), CARRY => INT_CARRY(199) ); ---- End FA stage ---- Begin FA stage FA_201:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(284), DATA_B => SUMMAND(285), DATA_C => SUMMAND(286), SAVE => INT_SUM(255), CARRY => INT_CARRY(200) ); ---- End FA stage ---- Begin NO stage INT_SUM(256) <= SUMMAND(287); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_202:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(251), DATA_B => INT_SUM(252), DATA_C => INT_SUM(253), SAVE => INT_SUM(257), CARRY => INT_CARRY(201) ); ---- End FA stage ---- Begin FA stage FA_203:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_SUM(256), SAVE => INT_SUM(258), CARRY => INT_CARRY(202) ); ---- End FA stage ---- Begin FA stage FA_204:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(182), DATA_B => INT_CARRY(183), DATA_C => INT_CARRY(184), SAVE => INT_SUM(259), CARRY => INT_CARRY(203) ); ---- End FA stage ---- Begin NO stage INT_SUM(260) <= INT_CARRY(185); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(261) <= INT_CARRY(186); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_205:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(257), DATA_B => INT_SUM(258), DATA_C => INT_SUM(259), SAVE => INT_SUM(262), CARRY => INT_CARRY(204) ); ---- End FA stage ---- Begin FA stage FA_206:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(187), SAVE => INT_SUM(263), CARRY => INT_CARRY(205) ); ---- End FA stage ---- Begin FA stage FA_207:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190), SAVE => INT_SUM(264), CARRY => INT_CARRY(206) ); ---- End FA stage ---- Begin FA stage FA_208:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(262), DATA_B => INT_SUM(263), DATA_C => INT_SUM(264), SAVE => INT_SUM(265), CARRY => INT_CARRY(207) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(191), DATA_B => INT_CARRY(192), SAVE => INT_SUM(266), CARRY => INT_CARRY(208) ); ---- End HA stage ---- Begin FA stage FA_209:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(193), SAVE => INT_SUM(267), CARRY => INT_CARRY(209) ); ---- End FA stage ---- Begin NO stage INT_SUM(268) <= INT_CARRY(194); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_210:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(267), DATA_B => INT_SUM(268), DATA_C => INT_CARRY(195), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End FA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_211:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290), SAVE => INT_SUM(269), CARRY => INT_CARRY(210) ); ---- End FA stage ---- Begin FA stage FA_212:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(291), DATA_B => SUMMAND(292), DATA_C => SUMMAND(293), SAVE => INT_SUM(270), CARRY => INT_CARRY(211) ); ---- End FA stage ---- Begin FA stage FA_213:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(294), DATA_B => SUMMAND(295), DATA_C => SUMMAND(296), SAVE => INT_SUM(271), CARRY => INT_CARRY(212) ); ---- End FA stage ---- Begin FA stage FA_214:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(297), DATA_B => SUMMAND(298), DATA_C => SUMMAND(299), SAVE => INT_SUM(272), CARRY => INT_CARRY(213) ); ---- End FA stage ---- Begin FA stage FA_215:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(300), DATA_B => SUMMAND(301), DATA_C => SUMMAND(302), SAVE => INT_SUM(273), CARRY => INT_CARRY(214) ); ---- End FA stage ---- Begin FA stage FA_216:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(303), DATA_B => SUMMAND(304), DATA_C => SUMMAND(305), SAVE => INT_SUM(274), CARRY => INT_CARRY(215) ); ---- End FA stage ---- Begin FA stage FA_217:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(269), DATA_B => INT_SUM(270), DATA_C => INT_SUM(271), SAVE => INT_SUM(275), CARRY => INT_CARRY(216) ); ---- End FA stage ---- Begin FA stage FA_218:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(272), DATA_B => INT_SUM(273), DATA_C => INT_SUM(274), SAVE => INT_SUM(276), CARRY => INT_CARRY(217) ); ---- End FA stage ---- Begin FA stage FA_219:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(196), DATA_B => INT_CARRY(197), DATA_C => INT_CARRY(198), SAVE => INT_SUM(277), CARRY => INT_CARRY(218) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(199), DATA_B => INT_CARRY(200), SAVE => INT_SUM(278), CARRY => INT_CARRY(219) ); ---- End HA stage ---- Begin FA stage FA_220:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(275), DATA_B => INT_SUM(276), DATA_C => INT_SUM(277), SAVE => INT_SUM(279), CARRY => INT_CARRY(220) ); ---- End FA stage ---- Begin FA stage FA_221:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(278), DATA_B => INT_CARRY(201), DATA_C => INT_CARRY(202), SAVE => INT_SUM(280), CARRY => INT_CARRY(221) ); ---- End FA stage ---- Begin NO stage INT_SUM(281) <= INT_CARRY(203); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_222:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(279), DATA_B => INT_SUM(280), DATA_C => INT_SUM(281), SAVE => INT_SUM(282), CARRY => INT_CARRY(222) ); ---- End FA stage ---- Begin FA stage FA_223:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(204), DATA_B => INT_CARRY(205), DATA_C => INT_CARRY(206), SAVE => INT_SUM(283), CARRY => INT_CARRY(223) ); ---- End FA stage ---- Begin FA stage FA_224:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(282), DATA_B => INT_SUM(283), DATA_C => INT_CARRY(207), SAVE => INT_SUM(284), CARRY => INT_CARRY(224) ); ---- End FA stage ---- Begin NO stage INT_SUM(285) <= INT_CARRY(208); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_225:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(284), DATA_B => INT_SUM(285), DATA_C => INT_CARRY(209), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_226:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(306), DATA_B => SUMMAND(307), DATA_C => SUMMAND(308), SAVE => INT_SUM(286), CARRY => INT_CARRY(225) ); ---- End FA stage ---- Begin FA stage FA_227:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311), SAVE => INT_SUM(287), CARRY => INT_CARRY(226) ); ---- End FA stage ---- Begin FA stage FA_228:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), DATA_C => SUMMAND(314), SAVE => INT_SUM(288), CARRY => INT_CARRY(227) ); ---- End FA stage ---- Begin FA stage FA_229:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(315), DATA_B => SUMMAND(316), DATA_C => SUMMAND(317), SAVE => INT_SUM(289), CARRY => INT_CARRY(228) ); ---- End FA stage ---- Begin FA stage FA_230:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320), SAVE => INT_SUM(290), CARRY => INT_CARRY(229) ); ---- End FA stage ---- Begin NO stage INT_SUM(291) <= SUMMAND(321); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(292) <= SUMMAND(322); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_231:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(286), DATA_B => INT_SUM(287), DATA_C => INT_SUM(288), SAVE => INT_SUM(293), CARRY => INT_CARRY(230) ); ---- End FA stage ---- Begin FA stage FA_232:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(289), DATA_B => INT_SUM(290), DATA_C => INT_SUM(291), SAVE => INT_SUM(294), CARRY => INT_CARRY(231) ); ---- End FA stage ---- Begin FA stage FA_233:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(292), DATA_B => INT_CARRY(210), DATA_C => INT_CARRY(211), SAVE => INT_SUM(295), CARRY => INT_CARRY(232) ); ---- End FA stage ---- Begin FA stage FA_234:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(212), DATA_B => INT_CARRY(213), DATA_C => INT_CARRY(214), SAVE => INT_SUM(296), CARRY => INT_CARRY(233) ); ---- End FA stage ---- Begin NO stage INT_SUM(297) <= INT_CARRY(215); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_235:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(293), DATA_B => INT_SUM(294), DATA_C => INT_SUM(295), SAVE => INT_SUM(298), CARRY => INT_CARRY(234) ); ---- End FA stage ---- Begin FA stage FA_236:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(296), DATA_B => INT_SUM(297), DATA_C => INT_CARRY(216), SAVE => INT_SUM(299), CARRY => INT_CARRY(235) ); ---- End FA stage ---- Begin FA stage FA_237:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(217), DATA_B => INT_CARRY(218), DATA_C => INT_CARRY(219), SAVE => INT_SUM(300), CARRY => INT_CARRY(236) ); ---- End FA stage ---- Begin FA stage FA_238:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(298), DATA_B => INT_SUM(299), DATA_C => INT_SUM(300), SAVE => INT_SUM(301), CARRY => INT_CARRY(237) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(220), DATA_B => INT_CARRY(221), SAVE => INT_SUM(302), CARRY => INT_CARRY(238) ); ---- End HA stage ---- Begin FA stage FA_239:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(301), DATA_B => INT_SUM(302), DATA_C => INT_CARRY(222), SAVE => INT_SUM(303), CARRY => INT_CARRY(239) ); ---- End FA stage ---- Begin NO stage INT_SUM(304) <= INT_CARRY(223); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_240:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(303), DATA_B => INT_SUM(304), DATA_C => INT_CARRY(224), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End FA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_241:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(323), DATA_B => SUMMAND(324), DATA_C => SUMMAND(325), SAVE => INT_SUM(305), CARRY => INT_CARRY(240) ); ---- End FA stage ---- Begin FA stage FA_242:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(326), DATA_B => SUMMAND(327), DATA_C => SUMMAND(328), SAVE => INT_SUM(306), CARRY => INT_CARRY(241) ); ---- End FA stage ---- Begin FA stage FA_243:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(329), DATA_B => SUMMAND(330), DATA_C => SUMMAND(331), SAVE => INT_SUM(307), CARRY => INT_CARRY(242) ); ---- End FA stage ---- Begin FA stage FA_244:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(332), DATA_B => SUMMAND(333), DATA_C => SUMMAND(334), SAVE => INT_SUM(308), CARRY => INT_CARRY(243) ); ---- End FA stage ---- Begin FA stage FA_245:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(335), DATA_B => SUMMAND(336), DATA_C => SUMMAND(337), SAVE => INT_SUM(309), CARRY => INT_CARRY(244) ); ---- End FA stage ---- Begin FA stage FA_246:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(338), DATA_B => SUMMAND(339), DATA_C => SUMMAND(340), SAVE => INT_SUM(310), CARRY => INT_CARRY(245) ); ---- End FA stage ---- Begin FA stage FA_247:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(305), DATA_B => INT_SUM(306), DATA_C => INT_SUM(307), SAVE => INT_SUM(311), CARRY => INT_CARRY(246) ); ---- End FA stage ---- Begin FA stage FA_248:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(308), DATA_B => INT_SUM(309), DATA_C => INT_SUM(310), SAVE => INT_SUM(312), CARRY => INT_CARRY(247) ); ---- End FA stage ---- Begin FA stage FA_249:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(225), DATA_B => INT_CARRY(226), DATA_C => INT_CARRY(227), SAVE => INT_SUM(313), CARRY => INT_CARRY(248) ); ---- End FA stage ---- Begin NO stage INT_SUM(314) <= INT_CARRY(228); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(315) <= INT_CARRY(229); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_250:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(311), DATA_B => INT_SUM(312), DATA_C => INT_SUM(313), SAVE => INT_SUM(316), CARRY => INT_CARRY(249) ); ---- End FA stage ---- Begin FA stage FA_251:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(314), DATA_B => INT_SUM(315), DATA_C => INT_CARRY(230), SAVE => INT_SUM(317), CARRY => INT_CARRY(250) ); ---- End FA stage ---- Begin FA stage FA_252:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(231), DATA_B => INT_CARRY(232), DATA_C => INT_CARRY(233), SAVE => INT_SUM(318), CARRY => INT_CARRY(251) ); ---- End FA stage ---- Begin FA stage FA_253:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(316), DATA_B => INT_SUM(317), DATA_C => INT_SUM(318), SAVE => INT_SUM(319), CARRY => INT_CARRY(252) ); ---- End FA stage ---- Begin FA stage FA_254:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(234), DATA_B => INT_CARRY(235), DATA_C => INT_CARRY(236), SAVE => INT_SUM(320), CARRY => INT_CARRY(253) ); ---- End FA stage ---- Begin FA stage FA_255:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(319), DATA_B => INT_SUM(320), DATA_C => INT_CARRY(237), SAVE => INT_SUM(321), CARRY => INT_CARRY(254) ); ---- End FA stage ---- Begin NO stage INT_SUM(322) <= INT_CARRY(238); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_256:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(321), DATA_B => INT_SUM(322), DATA_C => INT_CARRY(239), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_257:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(341), DATA_B => SUMMAND(342), DATA_C => SUMMAND(343), SAVE => INT_SUM(323), CARRY => INT_CARRY(255) ); ---- End FA stage ---- Begin FA stage FA_258:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(344), DATA_B => SUMMAND(345), DATA_C => SUMMAND(346), SAVE => INT_SUM(324), CARRY => INT_CARRY(256) ); ---- End FA stage ---- Begin FA stage FA_259:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(347), DATA_B => SUMMAND(348), DATA_C => SUMMAND(349), SAVE => INT_SUM(325), CARRY => INT_CARRY(257) ); ---- End FA stage ---- Begin FA stage FA_260:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(350), DATA_B => SUMMAND(351), DATA_C => SUMMAND(352), SAVE => INT_SUM(326), CARRY => INT_CARRY(258) ); ---- End FA stage ---- Begin FA stage FA_261:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(353), DATA_B => SUMMAND(354), DATA_C => SUMMAND(355), SAVE => INT_SUM(327), CARRY => INT_CARRY(259) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(356), DATA_B => SUMMAND(357), SAVE => INT_SUM(328), CARRY => INT_CARRY(260) ); ---- End HA stage ---- Begin FA stage FA_262:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(323), DATA_B => INT_SUM(324), DATA_C => INT_SUM(325), SAVE => INT_SUM(329), CARRY => INT_CARRY(261) ); ---- End FA stage ---- Begin FA stage FA_263:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(326), DATA_B => INT_SUM(327), DATA_C => INT_SUM(328), SAVE => INT_SUM(330), CARRY => INT_CARRY(262) ); ---- End FA stage ---- Begin FA stage FA_264:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(240), DATA_B => INT_CARRY(241), DATA_C => INT_CARRY(242), SAVE => INT_SUM(331), CARRY => INT_CARRY(263) ); ---- End FA stage ---- Begin FA stage FA_265:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(243), DATA_B => INT_CARRY(244), DATA_C => INT_CARRY(245), SAVE => INT_SUM(332), CARRY => INT_CARRY(264) ); ---- End FA stage ---- Begin FA stage FA_266:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(329), DATA_B => INT_SUM(330), DATA_C => INT_SUM(331), SAVE => INT_SUM(333), CARRY => INT_CARRY(265) ); ---- End FA stage ---- Begin FA stage FA_267:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(332), DATA_B => INT_CARRY(246), DATA_C => INT_CARRY(247), SAVE => INT_SUM(334), CARRY => INT_CARRY(266) ); ---- End FA stage ---- Begin NO stage INT_SUM(335) <= INT_CARRY(248); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_268:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(333), DATA_B => INT_SUM(334), DATA_C => INT_SUM(335), SAVE => INT_SUM(336), CARRY => INT_CARRY(267) ); ---- End FA stage ---- Begin FA stage FA_269:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(249), DATA_B => INT_CARRY(250), DATA_C => INT_CARRY(251), SAVE => INT_SUM(337), CARRY => INT_CARRY(268) ); ---- End FA stage ---- Begin FA stage FA_270:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(336), DATA_B => INT_SUM(337), DATA_C => INT_CARRY(252), SAVE => INT_SUM(338), CARRY => INT_CARRY(269) ); ---- End FA stage ---- Begin NO stage INT_SUM(339) <= INT_CARRY(253); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_271:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(338), DATA_B => INT_SUM(339), DATA_C => INT_CARRY(254), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End FA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_272:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(358), DATA_B => SUMMAND(359), DATA_C => SUMMAND(360), SAVE => INT_SUM(340), CARRY => INT_CARRY(270) ); ---- End FA stage ---- Begin FA stage FA_273:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(361), DATA_B => SUMMAND(362), DATA_C => SUMMAND(363), SAVE => INT_SUM(341), CARRY => INT_CARRY(271) ); ---- End FA stage ---- Begin FA stage FA_274:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(364), DATA_B => SUMMAND(365), DATA_C => SUMMAND(366), SAVE => INT_SUM(342), CARRY => INT_CARRY(272) ); ---- End FA stage ---- Begin FA stage FA_275:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(367), DATA_B => SUMMAND(368), DATA_C => SUMMAND(369), SAVE => INT_SUM(343), CARRY => INT_CARRY(273) ); ---- End FA stage ---- Begin FA stage FA_276:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(370), DATA_B => SUMMAND(371), DATA_C => SUMMAND(372), SAVE => INT_SUM(344), CARRY => INT_CARRY(274) ); ---- End FA stage ---- Begin NO stage INT_SUM(345) <= SUMMAND(373); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_277:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(340), DATA_B => INT_SUM(341), DATA_C => INT_SUM(342), SAVE => INT_SUM(346), CARRY => INT_CARRY(275) ); ---- End FA stage ---- Begin FA stage FA_278:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(343), DATA_B => INT_SUM(344), DATA_C => INT_SUM(345), SAVE => INT_SUM(347), CARRY => INT_CARRY(276) ); ---- End FA stage ---- Begin FA stage FA_279:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(255), DATA_B => INT_CARRY(256), DATA_C => INT_CARRY(257), SAVE => INT_SUM(348), CARRY => INT_CARRY(277) ); ---- End FA stage ---- Begin FA stage FA_280:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(258), DATA_B => INT_CARRY(259), DATA_C => INT_CARRY(260), SAVE => INT_SUM(349), CARRY => INT_CARRY(278) ); ---- End FA stage ---- Begin FA stage FA_281:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(346), DATA_B => INT_SUM(347), DATA_C => INT_SUM(348), SAVE => INT_SUM(350), CARRY => INT_CARRY(279) ); ---- End FA stage ---- Begin FA stage FA_282:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(349), DATA_B => INT_CARRY(261), DATA_C => INT_CARRY(262), SAVE => INT_SUM(351), CARRY => INT_CARRY(280) ); ---- End FA stage ---- Begin NO stage INT_SUM(352) <= INT_CARRY(263); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(353) <= INT_CARRY(264); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_283:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(350), DATA_B => INT_SUM(351), DATA_C => INT_SUM(352), SAVE => INT_SUM(354), CARRY => INT_CARRY(281) ); ---- End FA stage ---- Begin FA stage FA_284:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(353), DATA_B => INT_CARRY(265), DATA_C => INT_CARRY(266), SAVE => INT_SUM(355), CARRY => INT_CARRY(282) ); ---- End FA stage ---- Begin FA stage FA_285:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(354), DATA_B => INT_SUM(355), DATA_C => INT_CARRY(267), SAVE => INT_SUM(356), CARRY => INT_CARRY(283) ); ---- End FA stage ---- Begin NO stage INT_SUM(357) <= INT_CARRY(268); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_286:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(356), DATA_B => INT_SUM(357), DATA_C => INT_CARRY(269), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_287:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(374), DATA_B => SUMMAND(375), DATA_C => SUMMAND(376), SAVE => INT_SUM(358), CARRY => INT_CARRY(284) ); ---- End FA stage ---- Begin FA stage FA_288:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(377), DATA_B => SUMMAND(378), DATA_C => SUMMAND(379), SAVE => INT_SUM(359), CARRY => INT_CARRY(285) ); ---- End FA stage ---- Begin FA stage FA_289:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(380), DATA_B => SUMMAND(381), DATA_C => SUMMAND(382), SAVE => INT_SUM(360), CARRY => INT_CARRY(286) ); ---- End FA stage ---- Begin FA stage FA_290:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(383), DATA_B => SUMMAND(384), DATA_C => SUMMAND(385), SAVE => INT_SUM(361), CARRY => INT_CARRY(287) ); ---- End FA stage ---- Begin FA stage FA_291:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(386), DATA_B => SUMMAND(387), DATA_C => SUMMAND(388), SAVE => INT_SUM(362), CARRY => INT_CARRY(288) ); ---- End FA stage ---- Begin NO stage INT_SUM(363) <= SUMMAND(389); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_292:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(358), DATA_B => INT_SUM(359), DATA_C => INT_SUM(360), SAVE => INT_SUM(364), CARRY => INT_CARRY(289) ); ---- End FA stage ---- Begin FA stage FA_293:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(361), DATA_B => INT_SUM(362), DATA_C => INT_SUM(363), SAVE => INT_SUM(365), CARRY => INT_CARRY(290) ); ---- End FA stage ---- Begin FA stage FA_294:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(270), DATA_B => INT_CARRY(271), DATA_C => INT_CARRY(272), SAVE => INT_SUM(366), CARRY => INT_CARRY(291) ); ---- End FA stage ---- Begin NO stage INT_SUM(367) <= INT_CARRY(273); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(368) <= INT_CARRY(274); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_295:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(364), DATA_B => INT_SUM(365), DATA_C => INT_SUM(366), SAVE => INT_SUM(369), CARRY => INT_CARRY(292) ); ---- End FA stage ---- Begin FA stage FA_296:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(367), DATA_B => INT_SUM(368), DATA_C => INT_CARRY(275), SAVE => INT_SUM(370), CARRY => INT_CARRY(293) ); ---- End FA stage ---- Begin FA stage FA_297:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(276), DATA_B => INT_CARRY(277), DATA_C => INT_CARRY(278), SAVE => INT_SUM(371), CARRY => INT_CARRY(294) ); ---- End FA stage ---- Begin FA stage FA_298:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(369), DATA_B => INT_SUM(370), DATA_C => INT_SUM(371), SAVE => INT_SUM(372), CARRY => INT_CARRY(295) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(279), DATA_B => INT_CARRY(280), SAVE => INT_SUM(373), CARRY => INT_CARRY(296) ); ---- End HA stage ---- Begin FA stage FA_299:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(372), DATA_B => INT_SUM(373), DATA_C => INT_CARRY(281), SAVE => INT_SUM(374), CARRY => INT_CARRY(297) ); ---- End FA stage ---- Begin NO stage INT_SUM(375) <= INT_CARRY(282); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_300:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(374), DATA_B => INT_SUM(375), DATA_C => INT_CARRY(283), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End FA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_301:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(390), DATA_B => SUMMAND(391), DATA_C => SUMMAND(392), SAVE => INT_SUM(376), CARRY => INT_CARRY(298) ); ---- End FA stage ---- Begin FA stage FA_302:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(393), DATA_B => SUMMAND(394), DATA_C => SUMMAND(395), SAVE => INT_SUM(377), CARRY => INT_CARRY(299) ); ---- End FA stage ---- Begin FA stage FA_303:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(396), DATA_B => SUMMAND(397), DATA_C => SUMMAND(398), SAVE => INT_SUM(378), CARRY => INT_CARRY(300) ); ---- End FA stage ---- Begin FA stage FA_304:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(399), DATA_B => SUMMAND(400), DATA_C => SUMMAND(401), SAVE => INT_SUM(379), CARRY => INT_CARRY(301) ); ---- End FA stage ---- Begin FA stage FA_305:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(402), DATA_B => SUMMAND(403), DATA_C => SUMMAND(404), SAVE => INT_SUM(380), CARRY => INT_CARRY(302) ); ---- End FA stage ---- Begin FA stage FA_306:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(376), DATA_B => INT_SUM(377), DATA_C => INT_SUM(378), SAVE => INT_SUM(381), CARRY => INT_CARRY(303) ); ---- End FA stage ---- Begin FA stage FA_307:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(379), DATA_B => INT_SUM(380), DATA_C => INT_CARRY(284), SAVE => INT_SUM(382), CARRY => INT_CARRY(304) ); ---- End FA stage ---- Begin FA stage FA_308:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(285), DATA_B => INT_CARRY(286), DATA_C => INT_CARRY(287), SAVE => INT_SUM(383), CARRY => INT_CARRY(305) ); ---- End FA stage ---- Begin NO stage INT_SUM(384) <= INT_CARRY(288); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_309:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(381), DATA_B => INT_SUM(382), DATA_C => INT_SUM(383), SAVE => INT_SUM(385), CARRY => INT_CARRY(306) ); ---- End FA stage ---- Begin FA stage FA_310:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(384), DATA_B => INT_CARRY(289), DATA_C => INT_CARRY(290), SAVE => INT_SUM(386), CARRY => INT_CARRY(307) ); ---- End FA stage ---- Begin NO stage INT_SUM(387) <= INT_CARRY(291); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_311:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(385), DATA_B => INT_SUM(386), DATA_C => INT_SUM(387), SAVE => INT_SUM(388), CARRY => INT_CARRY(308) ); ---- End FA stage ---- Begin FA stage FA_312:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(292), DATA_B => INT_CARRY(293), DATA_C => INT_CARRY(294), SAVE => INT_SUM(389), CARRY => INT_CARRY(309) ); ---- End FA stage ---- Begin FA stage FA_313:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(388), DATA_B => INT_SUM(389), DATA_C => INT_CARRY(295), SAVE => INT_SUM(390), CARRY => INT_CARRY(310) ); ---- End FA stage ---- Begin NO stage INT_SUM(391) <= INT_CARRY(296); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_314:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(390), DATA_B => INT_SUM(391), DATA_C => INT_CARRY(297), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_315:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(405), DATA_B => SUMMAND(406), DATA_C => SUMMAND(407), SAVE => INT_SUM(392), CARRY => INT_CARRY(311) ); ---- End FA stage ---- Begin FA stage FA_316:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(408), DATA_B => SUMMAND(409), DATA_C => SUMMAND(410), SAVE => INT_SUM(393), CARRY => INT_CARRY(312) ); ---- End FA stage ---- Begin FA stage FA_317:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(411), DATA_B => SUMMAND(412), DATA_C => SUMMAND(413), SAVE => INT_SUM(394), CARRY => INT_CARRY(313) ); ---- End FA stage ---- Begin FA stage FA_318:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(414), DATA_B => SUMMAND(415), DATA_C => SUMMAND(416), SAVE => INT_SUM(395), CARRY => INT_CARRY(314) ); ---- End FA stage ---- Begin FA stage FA_319:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(417), DATA_B => SUMMAND(418), DATA_C => SUMMAND(419), SAVE => INT_SUM(396), CARRY => INT_CARRY(315) ); ---- End FA stage ---- Begin FA stage FA_320:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(392), DATA_B => INT_SUM(393), DATA_C => INT_SUM(394), SAVE => INT_SUM(397), CARRY => INT_CARRY(316) ); ---- End FA stage ---- Begin FA stage FA_321:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(395), DATA_B => INT_SUM(396), DATA_C => INT_CARRY(298), SAVE => INT_SUM(398), CARRY => INT_CARRY(317) ); ---- End FA stage ---- Begin FA stage FA_322:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(299), DATA_B => INT_CARRY(300), DATA_C => INT_CARRY(301), SAVE => INT_SUM(399), CARRY => INT_CARRY(318) ); ---- End FA stage ---- Begin NO stage INT_SUM(400) <= INT_CARRY(302); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_323:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(397), DATA_B => INT_SUM(398), DATA_C => INT_SUM(399), SAVE => INT_SUM(401), CARRY => INT_CARRY(319) ); ---- End FA stage ---- Begin FA stage FA_324:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(400), DATA_B => INT_CARRY(303), DATA_C => INT_CARRY(304), SAVE => INT_SUM(402), CARRY => INT_CARRY(320) ); ---- End FA stage ---- Begin NO stage INT_SUM(403) <= INT_CARRY(305); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_325:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(401), DATA_B => INT_SUM(402), DATA_C => INT_SUM(403), SAVE => INT_SUM(404), CARRY => INT_CARRY(321) ); ---- End FA stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(306), DATA_B => INT_CARRY(307), SAVE => INT_SUM(405), CARRY => INT_CARRY(322) ); ---- End HA stage ---- Begin FA stage FA_326:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(404), DATA_B => INT_SUM(405), DATA_C => INT_CARRY(308), SAVE => INT_SUM(406), CARRY => INT_CARRY(323) ); ---- End FA stage ---- Begin NO stage INT_SUM(407) <= INT_CARRY(309); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_327:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(406), DATA_B => INT_SUM(407), DATA_C => INT_CARRY(310), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End FA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin FA stage FA_328:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(420), DATA_B => SUMMAND(421), DATA_C => SUMMAND(422), SAVE => INT_SUM(408), CARRY => INT_CARRY(324) ); ---- End FA stage ---- Begin FA stage FA_329:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(423), DATA_B => SUMMAND(424), DATA_C => SUMMAND(425), SAVE => INT_SUM(409), CARRY => INT_CARRY(325) ); ---- End FA stage ---- Begin FA stage FA_330:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(426), DATA_B => SUMMAND(427), DATA_C => SUMMAND(428), SAVE => INT_SUM(410), CARRY => INT_CARRY(326) ); ---- End FA stage ---- Begin FA stage FA_331:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(429), DATA_B => SUMMAND(430), DATA_C => SUMMAND(431), SAVE => INT_SUM(411), CARRY => INT_CARRY(327) ); ---- End FA stage ---- Begin HA stage HA_35:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(432), DATA_B => SUMMAND(433), SAVE => INT_SUM(412), CARRY => INT_CARRY(328) ); ---- End HA stage ---- Begin FA stage FA_332:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(408), DATA_B => INT_SUM(409), DATA_C => INT_SUM(410), SAVE => INT_SUM(413), CARRY => INT_CARRY(329) ); ---- End FA stage ---- Begin FA stage FA_333:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(411), DATA_B => INT_SUM(412), DATA_C => INT_CARRY(311), SAVE => INT_SUM(414), CARRY => INT_CARRY(330) ); ---- End FA stage ---- Begin FA stage FA_334:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(312), DATA_B => INT_CARRY(313), DATA_C => INT_CARRY(314), SAVE => INT_SUM(415), CARRY => INT_CARRY(331) ); ---- End FA stage ---- Begin NO stage INT_SUM(416) <= INT_CARRY(315); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_335:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(413), DATA_B => INT_SUM(414), DATA_C => INT_SUM(415), SAVE => INT_SUM(417), CARRY => INT_CARRY(332) ); ---- End FA stage ---- Begin FA stage FA_336:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(416), DATA_B => INT_CARRY(316), DATA_C => INT_CARRY(317), SAVE => INT_SUM(418), CARRY => INT_CARRY(333) ); ---- End FA stage ---- Begin NO stage INT_SUM(419) <= INT_CARRY(318); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_337:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(417), DATA_B => INT_SUM(418), DATA_C => INT_SUM(419), SAVE => INT_SUM(420), CARRY => INT_CARRY(334) ); ---- End FA stage ---- Begin HA stage HA_36:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(319), DATA_B => INT_CARRY(320), SAVE => INT_SUM(421), CARRY => INT_CARRY(335) ); ---- End HA stage ---- Begin FA stage FA_338:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(420), DATA_B => INT_SUM(421), DATA_C => INT_CARRY(321), SAVE => INT_SUM(422), CARRY => INT_CARRY(336) ); ---- End FA stage ---- Begin NO stage INT_SUM(423) <= INT_CARRY(322); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_339:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(422), DATA_B => INT_SUM(423), DATA_C => INT_CARRY(323), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin FA stage FA_340:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(434), DATA_B => SUMMAND(435), DATA_C => SUMMAND(436), SAVE => INT_SUM(424), CARRY => INT_CARRY(337) ); ---- End FA stage ---- Begin FA stage FA_341:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(437), DATA_B => SUMMAND(438), DATA_C => SUMMAND(439), SAVE => INT_SUM(425), CARRY => INT_CARRY(338) ); ---- End FA stage ---- Begin FA stage FA_342:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(440), DATA_B => SUMMAND(441), DATA_C => SUMMAND(442), SAVE => INT_SUM(426), CARRY => INT_CARRY(339) ); ---- End FA stage ---- Begin FA stage FA_343:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(443), DATA_B => SUMMAND(444), DATA_C => SUMMAND(445), SAVE => INT_SUM(427), CARRY => INT_CARRY(340) ); ---- End FA stage ---- Begin HA stage HA_37:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(446), DATA_B => SUMMAND(447), SAVE => INT_SUM(428), CARRY => INT_CARRY(341) ); ---- End HA stage ---- Begin FA stage FA_344:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(424), DATA_B => INT_SUM(425), DATA_C => INT_SUM(426), SAVE => INT_SUM(429), CARRY => INT_CARRY(342) ); ---- End FA stage ---- Begin FA stage FA_345:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(427), DATA_B => INT_SUM(428), DATA_C => INT_CARRY(324), SAVE => INT_SUM(430), CARRY => INT_CARRY(343) ); ---- End FA stage ---- Begin FA stage FA_346:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(325), DATA_B => INT_CARRY(326), DATA_C => INT_CARRY(327), SAVE => INT_SUM(431), CARRY => INT_CARRY(344) ); ---- End FA stage ---- Begin NO stage INT_SUM(432) <= INT_CARRY(328); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_347:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(429), DATA_B => INT_SUM(430), DATA_C => INT_SUM(431), SAVE => INT_SUM(433), CARRY => INT_CARRY(345) ); ---- End FA stage ---- Begin FA stage FA_348:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(432), DATA_B => INT_CARRY(329), DATA_C => INT_CARRY(330), SAVE => INT_SUM(434), CARRY => INT_CARRY(346) ); ---- End FA stage ---- Begin NO stage INT_SUM(435) <= INT_CARRY(331); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_349:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(433), DATA_B => INT_SUM(434), DATA_C => INT_SUM(435), SAVE => INT_SUM(436), CARRY => INT_CARRY(347) ); ---- End FA stage ---- Begin HA stage HA_38:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(332), DATA_B => INT_CARRY(333), SAVE => INT_SUM(437), CARRY => INT_CARRY(348) ); ---- End HA stage ---- Begin FA stage FA_350:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(436), DATA_B => INT_SUM(437), DATA_C => INT_CARRY(334), SAVE => INT_SUM(438), CARRY => INT_CARRY(349) ); ---- End FA stage ---- Begin NO stage INT_SUM(439) <= INT_CARRY(335); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_351:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(438), DATA_B => INT_SUM(439), DATA_C => INT_CARRY(336), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End FA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin FA stage FA_352:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(448), DATA_B => SUMMAND(449), DATA_C => SUMMAND(450), SAVE => INT_SUM(440), CARRY => INT_CARRY(350) ); ---- End FA stage ---- Begin FA stage FA_353:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(451), DATA_B => SUMMAND(452), DATA_C => SUMMAND(453), SAVE => INT_SUM(441), CARRY => INT_CARRY(351) ); ---- End FA stage ---- Begin FA stage FA_354:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(454), DATA_B => SUMMAND(455), DATA_C => SUMMAND(456), SAVE => INT_SUM(442), CARRY => INT_CARRY(352) ); ---- End FA stage ---- Begin FA stage FA_355:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(457), DATA_B => SUMMAND(458), DATA_C => SUMMAND(459), SAVE => INT_SUM(443), CARRY => INT_CARRY(353) ); ---- End FA stage ---- Begin NO stage INT_SUM(444) <= SUMMAND(460); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_356:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(440), DATA_B => INT_SUM(441), DATA_C => INT_SUM(442), SAVE => INT_SUM(445), CARRY => INT_CARRY(354) ); ---- End FA stage ---- Begin FA stage FA_357:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(443), DATA_B => INT_SUM(444), DATA_C => INT_CARRY(337), SAVE => INT_SUM(446), CARRY => INT_CARRY(355) ); ---- End FA stage ---- Begin FA stage FA_358:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(338), DATA_B => INT_CARRY(339), DATA_C => INT_CARRY(340), SAVE => INT_SUM(447), CARRY => INT_CARRY(356) ); ---- End FA stage ---- Begin NO stage INT_SUM(448) <= INT_CARRY(341); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_359:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(445), DATA_B => INT_SUM(446), DATA_C => INT_SUM(447), SAVE => INT_SUM(449), CARRY => INT_CARRY(357) ); ---- End FA stage ---- Begin FA stage FA_360:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(448), DATA_B => INT_CARRY(342), DATA_C => INT_CARRY(343), SAVE => INT_SUM(450), CARRY => INT_CARRY(358) ); ---- End FA stage ---- Begin NO stage INT_SUM(451) <= INT_CARRY(344); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_361:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(449), DATA_B => INT_SUM(450), DATA_C => INT_SUM(451), SAVE => INT_SUM(452), CARRY => INT_CARRY(359) ); ---- End FA stage ---- Begin HA stage HA_39:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(345), DATA_B => INT_CARRY(346), SAVE => INT_SUM(453), CARRY => INT_CARRY(360) ); ---- End HA stage ---- Begin FA stage FA_362:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(452), DATA_B => INT_SUM(453), DATA_C => INT_CARRY(347), SAVE => INT_SUM(454), CARRY => INT_CARRY(361) ); ---- End FA stage ---- Begin NO stage INT_SUM(455) <= INT_CARRY(348); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_363:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(454), DATA_B => INT_SUM(455), DATA_C => INT_CARRY(349), SAVE => SUM(42), CARRY => CARRY(42) ); ---- End FA stage -- End WT-branch 43 -- Begin WT-branch 44 ---- Begin FA stage FA_364:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(461), DATA_B => SUMMAND(462), DATA_C => SUMMAND(463), SAVE => INT_SUM(456), CARRY => INT_CARRY(362) ); ---- End FA stage ---- Begin FA stage FA_365:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(464), DATA_B => SUMMAND(465), DATA_C => SUMMAND(466), SAVE => INT_SUM(457), CARRY => INT_CARRY(363) ); ---- End FA stage ---- Begin FA stage FA_366:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(467), DATA_B => SUMMAND(468), DATA_C => SUMMAND(469), SAVE => INT_SUM(458), CARRY => INT_CARRY(364) ); ---- End FA stage ---- Begin FA stage FA_367:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(470), DATA_B => SUMMAND(471), DATA_C => SUMMAND(472), SAVE => INT_SUM(459), CARRY => INT_CARRY(365) ); ---- End FA stage ---- Begin FA stage FA_368:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(473), DATA_B => INT_CARRY(350), DATA_C => INT_CARRY(351), SAVE => INT_SUM(460), CARRY => INT_CARRY(366) ); ---- End FA stage ---- Begin NO stage INT_SUM(461) <= INT_CARRY(352); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(462) <= INT_CARRY(353); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_369:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(456), DATA_B => INT_SUM(457), DATA_C => INT_SUM(458), SAVE => INT_SUM(463), CARRY => INT_CARRY(367) ); ---- End FA stage ---- Begin FA stage FA_370:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(459), DATA_B => INT_SUM(460), DATA_C => INT_SUM(461), SAVE => INT_SUM(464), CARRY => INT_CARRY(368) ); ---- End FA stage ---- Begin FA stage FA_371:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(462), DATA_B => INT_CARRY(354), DATA_C => INT_CARRY(355), SAVE => INT_SUM(465), CARRY => INT_CARRY(369) ); ---- End FA stage ---- Begin NO stage INT_SUM(466) <= INT_CARRY(356); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_372:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(463), DATA_B => INT_SUM(464), DATA_C => INT_SUM(465), SAVE => INT_SUM(467), CARRY => INT_CARRY(370) ); ---- End FA stage ---- Begin FA stage FA_373:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(466), DATA_B => INT_CARRY(357), DATA_C => INT_CARRY(358), SAVE => INT_SUM(468), CARRY => INT_CARRY(371) ); ---- End FA stage ---- Begin FA stage FA_374:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(467), DATA_B => INT_SUM(468), DATA_C => INT_CARRY(359), SAVE => INT_SUM(469), CARRY => INT_CARRY(372) ); ---- End FA stage ---- Begin NO stage INT_SUM(470) <= INT_CARRY(360); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_375:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(469), DATA_B => INT_SUM(470), DATA_C => INT_CARRY(361), SAVE => SUM(43), CARRY => CARRY(43) ); ---- End FA stage -- End WT-branch 44 -- Begin WT-branch 45 ---- Begin FA stage FA_376:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(474), DATA_B => SUMMAND(475), DATA_C => SUMMAND(476), SAVE => INT_SUM(471), CARRY => INT_CARRY(373) ); ---- End FA stage ---- Begin FA stage FA_377:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(477), DATA_B => SUMMAND(478), DATA_C => SUMMAND(479), SAVE => INT_SUM(472), CARRY => INT_CARRY(374) ); ---- End FA stage ---- Begin FA stage FA_378:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(480), DATA_B => SUMMAND(481), DATA_C => SUMMAND(482), SAVE => INT_SUM(473), CARRY => INT_CARRY(375) ); ---- End FA stage ---- Begin FA stage FA_379:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(483), DATA_B => SUMMAND(484), DATA_C => SUMMAND(485), SAVE => INT_SUM(474), CARRY => INT_CARRY(376) ); ---- End FA stage ---- Begin FA stage FA_380:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(471), DATA_B => INT_SUM(472), DATA_C => INT_SUM(473), SAVE => INT_SUM(475), CARRY => INT_CARRY(377) ); ---- End FA stage ---- Begin FA stage FA_381:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(474), DATA_B => INT_CARRY(362), DATA_C => INT_CARRY(363), SAVE => INT_SUM(476), CARRY => INT_CARRY(378) ); ---- End FA stage ---- Begin FA stage FA_382:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(364), DATA_B => INT_CARRY(365), DATA_C => INT_CARRY(366), SAVE => INT_SUM(477), CARRY => INT_CARRY(379) ); ---- End FA stage ---- Begin FA stage FA_383:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(475), DATA_B => INT_SUM(476), DATA_C => INT_SUM(477), SAVE => INT_SUM(478), CARRY => INT_CARRY(380) ); ---- End FA stage ---- Begin FA stage FA_384:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(367), DATA_B => INT_CARRY(368), DATA_C => INT_CARRY(369), SAVE => INT_SUM(479), CARRY => INT_CARRY(381) ); ---- End FA stage ---- Begin FA stage FA_385:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(478), DATA_B => INT_SUM(479), DATA_C => INT_CARRY(370), SAVE => INT_SUM(480), CARRY => INT_CARRY(382) ); ---- End FA stage ---- Begin NO stage INT_SUM(481) <= INT_CARRY(371); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_386:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(480), DATA_B => INT_SUM(481), DATA_C => INT_CARRY(372), SAVE => SUM(44), CARRY => CARRY(44) ); ---- End FA stage -- End WT-branch 45 -- Begin WT-branch 46 ---- Begin FA stage FA_387:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(486), DATA_B => SUMMAND(487), DATA_C => SUMMAND(488), SAVE => INT_SUM(482), CARRY => INT_CARRY(383) ); ---- End FA stage ---- Begin FA stage FA_388:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(489), DATA_B => SUMMAND(490), DATA_C => SUMMAND(491), SAVE => INT_SUM(483), CARRY => INT_CARRY(384) ); ---- End FA stage ---- Begin FA stage FA_389:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(492), DATA_B => SUMMAND(493), DATA_C => SUMMAND(494), SAVE => INT_SUM(484), CARRY => INT_CARRY(385) ); ---- End FA stage ---- Begin FA stage FA_390:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(495), DATA_B => SUMMAND(496), DATA_C => SUMMAND(497), SAVE => INT_SUM(485), CARRY => INT_CARRY(386) ); ---- End FA stage ---- Begin FA stage FA_391:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(482), DATA_B => INT_SUM(483), DATA_C => INT_SUM(484), SAVE => INT_SUM(486), CARRY => INT_CARRY(387) ); ---- End FA stage ---- Begin FA stage FA_392:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(485), DATA_B => INT_CARRY(373), DATA_C => INT_CARRY(374), SAVE => INT_SUM(487), CARRY => INT_CARRY(388) ); ---- End FA stage ---- Begin HA stage HA_40:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(375), DATA_B => INT_CARRY(376), SAVE => INT_SUM(488), CARRY => INT_CARRY(389) ); ---- End HA stage ---- Begin FA stage FA_393:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(486), DATA_B => INT_SUM(487), DATA_C => INT_SUM(488), SAVE => INT_SUM(489), CARRY => INT_CARRY(390) ); ---- End FA stage ---- Begin FA stage FA_394:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(377), DATA_B => INT_CARRY(378), DATA_C => INT_CARRY(379), SAVE => INT_SUM(490), CARRY => INT_CARRY(391) ); ---- End FA stage ---- Begin FA stage FA_395:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(489), DATA_B => INT_SUM(490), DATA_C => INT_CARRY(380), SAVE => INT_SUM(491), CARRY => INT_CARRY(392) ); ---- End FA stage ---- Begin NO stage INT_SUM(492) <= INT_CARRY(381); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_396:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(491), DATA_B => INT_SUM(492), DATA_C => INT_CARRY(382), SAVE => SUM(45), CARRY => CARRY(45) ); ---- End FA stage -- End WT-branch 46 -- Begin WT-branch 47 ---- Begin FA stage FA_397:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(498), DATA_B => SUMMAND(499), DATA_C => SUMMAND(500), SAVE => INT_SUM(493), CARRY => INT_CARRY(393) ); ---- End FA stage ---- Begin FA stage FA_398:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(501), DATA_B => SUMMAND(502), DATA_C => SUMMAND(503), SAVE => INT_SUM(494), CARRY => INT_CARRY(394) ); ---- End FA stage ---- Begin FA stage FA_399:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(504), DATA_B => SUMMAND(505), DATA_C => SUMMAND(506), SAVE => INT_SUM(495), CARRY => INT_CARRY(395) ); ---- End FA stage ---- Begin NO stage INT_SUM(496) <= SUMMAND(507); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(497) <= SUMMAND(508); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_400:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(493), DATA_B => INT_SUM(494), DATA_C => INT_SUM(495), SAVE => INT_SUM(498), CARRY => INT_CARRY(396) ); ---- End FA stage ---- Begin FA stage FA_401:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(496), DATA_B => INT_SUM(497), DATA_C => INT_CARRY(383), SAVE => INT_SUM(499), CARRY => INT_CARRY(397) ); ---- End FA stage ---- Begin FA stage FA_402:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(384), DATA_B => INT_CARRY(385), DATA_C => INT_CARRY(386), SAVE => INT_SUM(500), CARRY => INT_CARRY(398) ); ---- End FA stage ---- Begin FA stage FA_403:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(498), DATA_B => INT_SUM(499), DATA_C => INT_SUM(500), SAVE => INT_SUM(501), CARRY => INT_CARRY(399) ); ---- End FA stage ---- Begin FA stage FA_404:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(387), DATA_B => INT_CARRY(388), DATA_C => INT_CARRY(389), SAVE => INT_SUM(502), CARRY => INT_CARRY(400) ); ---- End FA stage ---- Begin FA stage FA_405:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(501), DATA_B => INT_SUM(502), DATA_C => INT_CARRY(390), SAVE => INT_SUM(503), CARRY => INT_CARRY(401) ); ---- End FA stage ---- Begin NO stage INT_SUM(504) <= INT_CARRY(391); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_406:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(503), DATA_B => INT_SUM(504), DATA_C => INT_CARRY(392), SAVE => SUM(46), CARRY => CARRY(46) ); ---- End FA stage -- End WT-branch 47 -- Begin WT-branch 48 ---- Begin FA stage FA_407:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(509), DATA_B => SUMMAND(510), DATA_C => SUMMAND(511), SAVE => INT_SUM(505), CARRY => INT_CARRY(402) ); ---- End FA stage ---- Begin FA stage FA_408:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(512), DATA_B => SUMMAND(513), DATA_C => SUMMAND(514), SAVE => INT_SUM(506), CARRY => INT_CARRY(403) ); ---- End FA stage ---- Begin FA stage FA_409:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(515), DATA_B => SUMMAND(516), DATA_C => SUMMAND(517), SAVE => INT_SUM(507), CARRY => INT_CARRY(404) ); ---- End FA stage ---- Begin HA stage HA_41:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(518), DATA_B => SUMMAND(519), SAVE => INT_SUM(508), CARRY => INT_CARRY(405) ); ---- End HA stage ---- Begin FA stage FA_410:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(505), DATA_B => INT_SUM(506), DATA_C => INT_SUM(507), SAVE => INT_SUM(509), CARRY => INT_CARRY(406) ); ---- End FA stage ---- Begin FA stage FA_411:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(508), DATA_B => INT_CARRY(393), DATA_C => INT_CARRY(394), SAVE => INT_SUM(510), CARRY => INT_CARRY(407) ); ---- End FA stage ---- Begin NO stage INT_SUM(511) <= INT_CARRY(395); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_412:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(509), DATA_B => INT_SUM(510), DATA_C => INT_SUM(511), SAVE => INT_SUM(512), CARRY => INT_CARRY(408) ); ---- End FA stage ---- Begin FA stage FA_413:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(396), DATA_B => INT_CARRY(397), DATA_C => INT_CARRY(398), SAVE => INT_SUM(513), CARRY => INT_CARRY(409) ); ---- End FA stage ---- Begin FA stage FA_414:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(512), DATA_B => INT_SUM(513), DATA_C => INT_CARRY(399), SAVE => INT_SUM(514), CARRY => INT_CARRY(410) ); ---- End FA stage ---- Begin NO stage INT_SUM(515) <= INT_CARRY(400); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_415:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(514), DATA_B => INT_SUM(515), DATA_C => INT_CARRY(401), SAVE => SUM(47), CARRY => CARRY(47) ); ---- End FA stage -- End WT-branch 48 -- Begin WT-branch 49 ---- Begin FA stage FA_416:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(520), DATA_B => SUMMAND(521), DATA_C => SUMMAND(522), SAVE => INT_SUM(516), CARRY => INT_CARRY(411) ); ---- End FA stage ---- Begin FA stage FA_417:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(523), DATA_B => SUMMAND(524), DATA_C => SUMMAND(525), SAVE => INT_SUM(517), CARRY => INT_CARRY(412) ); ---- End FA stage ---- Begin FA stage FA_418:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(526), DATA_B => SUMMAND(527), DATA_C => SUMMAND(528), SAVE => INT_SUM(518), CARRY => INT_CARRY(413) ); ---- End FA stage ---- Begin NO stage INT_SUM(519) <= SUMMAND(529); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_419:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(516), DATA_B => INT_SUM(517), DATA_C => INT_SUM(518), SAVE => INT_SUM(520), CARRY => INT_CARRY(414) ); ---- End FA stage ---- Begin FA stage FA_420:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(519), DATA_B => INT_CARRY(402), DATA_C => INT_CARRY(403), SAVE => INT_SUM(521), CARRY => INT_CARRY(415) ); ---- End FA stage ---- Begin NO stage INT_SUM(522) <= INT_CARRY(404); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(523) <= INT_CARRY(405); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_421:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(520), DATA_B => INT_SUM(521), DATA_C => INT_SUM(522), SAVE => INT_SUM(524), CARRY => INT_CARRY(416) ); ---- End FA stage ---- Begin FA stage FA_422:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(523), DATA_B => INT_CARRY(406), DATA_C => INT_CARRY(407), SAVE => INT_SUM(525), CARRY => INT_CARRY(417) ); ---- End FA stage ---- Begin FA stage FA_423:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(524), DATA_B => INT_SUM(525), DATA_C => INT_CARRY(408), SAVE => INT_SUM(526), CARRY => INT_CARRY(418) ); ---- End FA stage ---- Begin NO stage INT_SUM(527) <= INT_CARRY(409); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_424:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(526), DATA_B => INT_SUM(527), DATA_C => INT_CARRY(410), SAVE => SUM(48), CARRY => CARRY(48) ); ---- End FA stage -- End WT-branch 49 -- Begin WT-branch 50 ---- Begin FA stage FA_425:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(530), DATA_B => SUMMAND(531), DATA_C => SUMMAND(532), SAVE => INT_SUM(528), CARRY => INT_CARRY(419) ); ---- End FA stage ---- Begin FA stage FA_426:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(533), DATA_B => SUMMAND(534), DATA_C => SUMMAND(535), SAVE => INT_SUM(529), CARRY => INT_CARRY(420) ); ---- End FA stage ---- Begin FA stage FA_427:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(536), DATA_B => SUMMAND(537), DATA_C => SUMMAND(538), SAVE => INT_SUM(530), CARRY => INT_CARRY(421) ); ---- End FA stage ---- Begin NO stage INT_SUM(531) <= SUMMAND(539); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_428:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(528), DATA_B => INT_SUM(529), DATA_C => INT_SUM(530), SAVE => INT_SUM(532), CARRY => INT_CARRY(422) ); ---- End FA stage ---- Begin FA stage FA_429:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(531), DATA_B => INT_CARRY(411), DATA_C => INT_CARRY(412), SAVE => INT_SUM(533), CARRY => INT_CARRY(423) ); ---- End FA stage ---- Begin NO stage INT_SUM(534) <= INT_CARRY(413); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_430:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(532), DATA_B => INT_SUM(533), DATA_C => INT_SUM(534), SAVE => INT_SUM(535), CARRY => INT_CARRY(424) ); ---- End FA stage ---- Begin HA stage HA_42:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(414), DATA_B => INT_CARRY(415), SAVE => INT_SUM(536), CARRY => INT_CARRY(425) ); ---- End HA stage ---- Begin FA stage FA_431:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(535), DATA_B => INT_SUM(536), DATA_C => INT_CARRY(416), SAVE => INT_SUM(537), CARRY => INT_CARRY(426) ); ---- End FA stage ---- Begin NO stage INT_SUM(538) <= INT_CARRY(417); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_432:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(537), DATA_B => INT_SUM(538), DATA_C => INT_CARRY(418), SAVE => SUM(49), CARRY => CARRY(49) ); ---- End FA stage -- End WT-branch 50 -- Begin WT-branch 51 ---- Begin FA stage FA_433:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(540), DATA_B => SUMMAND(541), DATA_C => SUMMAND(542), SAVE => INT_SUM(539), CARRY => INT_CARRY(427) ); ---- End FA stage ---- Begin FA stage FA_434:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(543), DATA_B => SUMMAND(544), DATA_C => SUMMAND(545), SAVE => INT_SUM(540), CARRY => INT_CARRY(428) ); ---- End FA stage ---- Begin FA stage FA_435:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(546), DATA_B => SUMMAND(547), DATA_C => SUMMAND(548), SAVE => INT_SUM(541), CARRY => INT_CARRY(429) ); ---- End FA stage ---- Begin FA stage FA_436:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(539), DATA_B => INT_SUM(540), DATA_C => INT_SUM(541), SAVE => INT_SUM(542), CARRY => INT_CARRY(430) ); ---- End FA stage ---- Begin FA stage FA_437:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(419), DATA_B => INT_CARRY(420), DATA_C => INT_CARRY(421), SAVE => INT_SUM(543), CARRY => INT_CARRY(431) ); ---- End FA stage ---- Begin FA stage FA_438:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(542), DATA_B => INT_SUM(543), DATA_C => INT_CARRY(422), SAVE => INT_SUM(544), CARRY => INT_CARRY(432) ); ---- End FA stage ---- Begin NO stage INT_SUM(545) <= INT_CARRY(423); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_439:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(544), DATA_B => INT_SUM(545), DATA_C => INT_CARRY(424), SAVE => INT_SUM(546), CARRY => INT_CARRY(433) ); ---- End FA stage ---- Begin NO stage INT_SUM(547) <= INT_CARRY(425); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_440:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(546), DATA_B => INT_SUM(547), DATA_C => INT_CARRY(426), SAVE => SUM(50), CARRY => CARRY(50) ); ---- End FA stage -- End WT-branch 51 -- Begin WT-branch 52 ---- Begin FA stage FA_441:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(549), DATA_B => SUMMAND(550), DATA_C => SUMMAND(551), SAVE => INT_SUM(548), CARRY => INT_CARRY(434) ); ---- End FA stage ---- Begin FA stage FA_442:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(552), DATA_B => SUMMAND(553), DATA_C => SUMMAND(554), SAVE => INT_SUM(549), CARRY => INT_CARRY(435) ); ---- End FA stage ---- Begin FA stage FA_443:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(555), DATA_B => SUMMAND(556), DATA_C => SUMMAND(557), SAVE => INT_SUM(550), CARRY => INT_CARRY(436) ); ---- End FA stage ---- Begin FA stage FA_444:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(548), DATA_B => INT_SUM(549), DATA_C => INT_SUM(550), SAVE => INT_SUM(551), CARRY => INT_CARRY(437) ); ---- End FA stage ---- Begin FA stage FA_445:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(427), DATA_B => INT_CARRY(428), DATA_C => INT_CARRY(429), SAVE => INT_SUM(552), CARRY => INT_CARRY(438) ); ---- End FA stage ---- Begin FA stage FA_446:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(551), DATA_B => INT_SUM(552), DATA_C => INT_CARRY(430), SAVE => INT_SUM(553), CARRY => INT_CARRY(439) ); ---- End FA stage ---- Begin NO stage INT_SUM(554) <= INT_CARRY(431); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_447:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(553), DATA_B => INT_SUM(554), DATA_C => INT_CARRY(432), SAVE => INT_SUM(555), CARRY => INT_CARRY(440) ); ---- End FA stage ---- Begin HA stage HA_43:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(555), DATA_B => INT_CARRY(433), SAVE => SUM(51), CARRY => CARRY(51) ); ---- End HA stage -- End WT-branch 52 -- Begin WT-branch 53 ---- Begin FA stage FA_448:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(558), DATA_B => SUMMAND(559), DATA_C => SUMMAND(560), SAVE => INT_SUM(556), CARRY => INT_CARRY(441) ); ---- End FA stage ---- Begin FA stage FA_449:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(561), DATA_B => SUMMAND(562), DATA_C => SUMMAND(563), SAVE => INT_SUM(557), CARRY => INT_CARRY(442) ); ---- End FA stage ---- Begin FA stage FA_450:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(564), DATA_B => SUMMAND(565), DATA_C => INT_CARRY(434), SAVE => INT_SUM(558), CARRY => INT_CARRY(443) ); ---- End FA stage ---- Begin HA stage HA_44:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(435), DATA_B => INT_CARRY(436), SAVE => INT_SUM(559), CARRY => INT_CARRY(444) ); ---- End HA stage ---- Begin FA stage FA_451:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(556), DATA_B => INT_SUM(557), DATA_C => INT_SUM(558), SAVE => INT_SUM(560), CARRY => INT_CARRY(445) ); ---- End FA stage ---- Begin FA stage FA_452:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(559), DATA_B => INT_CARRY(437), DATA_C => INT_CARRY(438), SAVE => INT_SUM(561), CARRY => INT_CARRY(446) ); ---- End FA stage ---- Begin FA stage FA_453:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(560), DATA_B => INT_SUM(561), DATA_C => INT_CARRY(439), SAVE => INT_SUM(562), CARRY => INT_CARRY(447) ); ---- End FA stage ---- Begin HA stage HA_45:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(562), DATA_B => INT_CARRY(440), SAVE => SUM(52), CARRY => CARRY(52) ); ---- End HA stage -- End WT-branch 53 -- Begin WT-branch 54 ---- Begin FA stage FA_454:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(566), DATA_B => SUMMAND(567), DATA_C => SUMMAND(568), SAVE => INT_SUM(563), CARRY => INT_CARRY(448) ); ---- End FA stage ---- Begin FA stage FA_455:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(569), DATA_B => SUMMAND(570), DATA_C => SUMMAND(571), SAVE => INT_SUM(564), CARRY => INT_CARRY(449) ); ---- End FA stage ---- Begin NO stage INT_SUM(565) <= SUMMAND(572); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(566) <= SUMMAND(573); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_456:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(563), DATA_B => INT_SUM(564), DATA_C => INT_SUM(565), SAVE => INT_SUM(567), CARRY => INT_CARRY(450) ); ---- End FA stage ---- Begin NO stage INT_SUM(568) <= INT_SUM(566); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_457:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(567), DATA_B => INT_SUM(568), DATA_C => INT_CARRY(441), SAVE => INT_SUM(569), CARRY => INT_CARRY(451) ); ---- End FA stage ---- Begin FA stage FA_458:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(442), DATA_B => INT_CARRY(443), DATA_C => INT_CARRY(444), SAVE => INT_SUM(570), CARRY => INT_CARRY(452) ); ---- End FA stage ---- Begin FA stage FA_459:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(569), DATA_B => INT_SUM(570), DATA_C => INT_CARRY(445), SAVE => INT_SUM(571), CARRY => INT_CARRY(453) ); ---- End FA stage ---- Begin NO stage INT_SUM(572) <= INT_CARRY(446); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_460:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(571), DATA_B => INT_SUM(572), DATA_C => INT_CARRY(447), SAVE => SUM(53), CARRY => CARRY(53) ); ---- End FA stage -- End WT-branch 54 -- Begin WT-branch 55 ---- Begin FA stage FA_461:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(574), DATA_B => SUMMAND(575), DATA_C => SUMMAND(576), SAVE => INT_SUM(573), CARRY => INT_CARRY(454) ); ---- End FA stage ---- Begin FA stage FA_462:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(577), DATA_B => SUMMAND(578), DATA_C => SUMMAND(579), SAVE => INT_SUM(574), CARRY => INT_CARRY(455) ); ---- End FA stage ---- Begin FA stage FA_463:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(580), DATA_B => INT_CARRY(448), DATA_C => INT_CARRY(449), SAVE => INT_SUM(575), CARRY => INT_CARRY(456) ); ---- End FA stage ---- Begin FA stage FA_464:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(573), DATA_B => INT_SUM(574), DATA_C => INT_SUM(575), SAVE => INT_SUM(576), CARRY => INT_CARRY(457) ); ---- End FA stage ---- Begin NO stage INT_SUM(577) <= INT_CARRY(450); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_465:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(576), DATA_B => INT_SUM(577), DATA_C => INT_CARRY(451), SAVE => INT_SUM(578), CARRY => INT_CARRY(458) ); ---- End FA stage ---- Begin NO stage INT_SUM(579) <= INT_CARRY(452); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_466:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(578), DATA_B => INT_SUM(579), DATA_C => INT_CARRY(453), SAVE => SUM(54), CARRY => CARRY(54) ); ---- End FA stage -- End WT-branch 55 -- Begin WT-branch 56 ---- Begin FA stage FA_467:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(581), DATA_B => SUMMAND(582), DATA_C => SUMMAND(583), SAVE => INT_SUM(580), CARRY => INT_CARRY(459) ); ---- End FA stage ---- Begin FA stage FA_468:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(584), DATA_B => SUMMAND(585), DATA_C => SUMMAND(586), SAVE => INT_SUM(581), CARRY => INT_CARRY(460) ); ---- End FA stage ---- Begin NO stage INT_SUM(582) <= SUMMAND(587); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_469:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(580), DATA_B => INT_SUM(581), DATA_C => INT_SUM(582), SAVE => INT_SUM(583), CARRY => INT_CARRY(461) ); ---- End FA stage ---- Begin FA stage FA_470:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(454), DATA_B => INT_CARRY(455), DATA_C => INT_CARRY(456), SAVE => INT_SUM(584), CARRY => INT_CARRY(462) ); ---- End FA stage ---- Begin FA stage FA_471:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(583), DATA_B => INT_SUM(584), DATA_C => INT_CARRY(457), SAVE => INT_SUM(585), CARRY => INT_CARRY(463) ); ---- End FA stage ---- Begin HA stage HA_46:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(585), DATA_B => INT_CARRY(458), SAVE => SUM(55), CARRY => CARRY(55) ); ---- End HA stage -- End WT-branch 56 -- Begin WT-branch 57 ---- Begin FA stage FA_472:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(588), DATA_B => SUMMAND(589), DATA_C => SUMMAND(590), SAVE => INT_SUM(586), CARRY => INT_CARRY(464) ); ---- End FA stage ---- Begin FA stage FA_473:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(591), DATA_B => SUMMAND(592), DATA_C => SUMMAND(593), SAVE => INT_SUM(587), CARRY => INT_CARRY(465) ); ---- End FA stage ---- Begin FA stage FA_474:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(586), DATA_B => INT_SUM(587), DATA_C => INT_CARRY(459), SAVE => INT_SUM(588), CARRY => INT_CARRY(466) ); ---- End FA stage ---- Begin NO stage INT_SUM(589) <= INT_CARRY(460); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_475:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(588), DATA_B => INT_SUM(589), DATA_C => INT_CARRY(461), SAVE => INT_SUM(590), CARRY => INT_CARRY(467) ); ---- End FA stage ---- Begin NO stage INT_SUM(591) <= INT_CARRY(462); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_476:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(590), DATA_B => INT_SUM(591), DATA_C => INT_CARRY(463), SAVE => SUM(56), CARRY => CARRY(56) ); ---- End FA stage -- End WT-branch 57 -- Begin WT-branch 58 ---- Begin FA stage FA_477:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(594), DATA_B => SUMMAND(595), DATA_C => SUMMAND(596), SAVE => INT_SUM(592), CARRY => INT_CARRY(468) ); ---- End FA stage ---- Begin FA stage FA_478:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(597), DATA_B => SUMMAND(598), DATA_C => SUMMAND(599), SAVE => INT_SUM(593), CARRY => INT_CARRY(469) ); ---- End FA stage ---- Begin FA stage FA_479:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(592), DATA_B => INT_SUM(593), DATA_C => INT_CARRY(464), SAVE => INT_SUM(594), CARRY => INT_CARRY(470) ); ---- End FA stage ---- Begin NO stage INT_SUM(595) <= INT_CARRY(465); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_480:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(594), DATA_B => INT_SUM(595), DATA_C => INT_CARRY(466), SAVE => INT_SUM(596), CARRY => INT_CARRY(471) ); ---- End FA stage ---- Begin HA stage HA_47:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(596), DATA_B => INT_CARRY(467), SAVE => SUM(57), CARRY => CARRY(57) ); ---- End HA stage -- End WT-branch 58 -- Begin WT-branch 59 ---- Begin FA stage FA_481:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(600), DATA_B => SUMMAND(601), DATA_C => SUMMAND(602), SAVE => INT_SUM(597), CARRY => INT_CARRY(472) ); ---- End FA stage ---- Begin HA stage HA_48:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(603), DATA_B => SUMMAND(604), SAVE => INT_SUM(598), CARRY => INT_CARRY(473) ); ---- End HA stage ---- Begin FA stage FA_482:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(597), DATA_B => INT_SUM(598), DATA_C => INT_CARRY(468), SAVE => INT_SUM(599), CARRY => INT_CARRY(474) ); ---- End FA stage ---- Begin NO stage INT_SUM(600) <= INT_CARRY(469); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_483:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(599), DATA_B => INT_SUM(600), DATA_C => INT_CARRY(470), SAVE => INT_SUM(601), CARRY => INT_CARRY(475) ); ---- End FA stage ---- Begin HA stage HA_49:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(601), DATA_B => INT_CARRY(471), SAVE => SUM(58), CARRY => CARRY(58) ); ---- End HA stage -- End WT-branch 59 -- Begin WT-branch 60 ---- Begin FA stage FA_484:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(605), DATA_B => SUMMAND(606), DATA_C => SUMMAND(607), SAVE => INT_SUM(602), CARRY => INT_CARRY(476) ); ---- End FA stage ---- Begin HA stage HA_50:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(608), DATA_B => SUMMAND(609), SAVE => INT_SUM(603), CARRY => INT_CARRY(477) ); ---- End HA stage ---- Begin FA stage FA_485:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(602), DATA_B => INT_SUM(603), DATA_C => INT_CARRY(472), SAVE => INT_SUM(604), CARRY => INT_CARRY(478) ); ---- End FA stage ---- Begin NO stage INT_SUM(605) <= INT_CARRY(473); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_486:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(604), DATA_B => INT_SUM(605), DATA_C => INT_CARRY(474), SAVE => INT_SUM(606), CARRY => INT_CARRY(479) ); ---- End FA stage ---- Begin HA stage HA_51:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(606), DATA_B => INT_CARRY(475), SAVE => SUM(59), CARRY => CARRY(59) ); ---- End HA stage -- End WT-branch 60 -- Begin WT-branch 61 ---- Begin FA stage FA_487:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(610), DATA_B => SUMMAND(611), DATA_C => SUMMAND(612), SAVE => INT_SUM(607), CARRY => INT_CARRY(480) ); ---- End FA stage ---- Begin FA stage FA_488:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(613), DATA_B => INT_CARRY(476), DATA_C => INT_CARRY(477), SAVE => INT_SUM(608), CARRY => INT_CARRY(481) ); ---- End FA stage ---- Begin FA stage FA_489:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(607), DATA_B => INT_SUM(608), DATA_C => INT_CARRY(478), SAVE => INT_SUM(609), CARRY => INT_CARRY(482) ); ---- End FA stage ---- Begin HA stage HA_52:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(609), DATA_B => INT_CARRY(479), SAVE => SUM(60), CARRY => CARRY(60) ); ---- End HA stage -- End WT-branch 61 -- Begin WT-branch 62 ---- Begin FA stage FA_490:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(614), DATA_B => SUMMAND(615), DATA_C => SUMMAND(616), SAVE => INT_SUM(610), CARRY => INT_CARRY(483) ); ---- End FA stage ---- Begin NO stage INT_SUM(611) <= SUMMAND(617); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_491:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(610), DATA_B => INT_SUM(611), DATA_C => INT_CARRY(480), SAVE => INT_SUM(612), CARRY => INT_CARRY(484) ); ---- End FA stage ---- Begin NO stage INT_SUM(613) <= INT_CARRY(481); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_492:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(612), DATA_B => INT_SUM(613), DATA_C => INT_CARRY(482), SAVE => SUM(61), CARRY => CARRY(61) ); ---- End FA stage -- End WT-branch 62 -- Begin WT-branch 63 ---- Begin FA stage FA_493:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(618), DATA_B => SUMMAND(619), DATA_C => SUMMAND(620), SAVE => INT_SUM(614), CARRY => INT_CARRY(485) ); ---- End FA stage ---- Begin NO stage INT_SUM(615) <= INT_SUM(614); -- At Level 5 ---- End NO stage ---- Begin NO stage INT_SUM(616) <= INT_CARRY(483); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_494:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(615), DATA_B => INT_SUM(616), DATA_C => INT_CARRY(484), SAVE => SUM(62), CARRY => CARRY(62) ); ---- End FA stage -- End WT-branch 63 -- Begin WT-branch 64 ---- Begin FA stage FA_495:FULL_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(621), DATA_B => SUMMAND(622), DATA_C => SUMMAND(623), SAVE => INT_SUM(617), CARRY => INT_CARRY(486) ); ---- End FA stage ---- Begin NO stage INT_SUM(618) <= INT_CARRY(485); -- At Level 5 ---- End NO stage ---- Begin HA stage HA_53:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(617), DATA_B => INT_SUM(618), SAVE => SUM(63), CARRY => CARRY(63) ); ---- End HA stage -- End WT-branch 64 -- Begin WT-branch 65 ---- Begin NO stage INT_SUM(619) <= SUMMAND(624); -- At Level 5 ---- End NO stage ---- Begin NO stage INT_SUM(620) <= SUMMAND(625); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_496:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(619), DATA_B => INT_SUM(620), DATA_C => INT_CARRY(486), SAVE => SUM(64), CARRY => CARRY(64) ); ---- End FA stage -- End WT-branch 65 -- Begin WT-branch 66 ---- Begin HA stage HA_54:HALF_ADDER -- At Level 6 port map ( DATA_A => SUMMAND(626), DATA_B => SUMMAND(627), SAVE => SUM(65), CARRY => CARRY(65) ); ---- End HA stage -- End WT-branch 66 -- Begin WT-branch 67 ---- Begin NO stage SUM(66) <= SUMMAND(628); -- At Level 6 ---- End NO stage -- End WT-branch 67 end WALLACE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_34 is generic (mulpipe : integer := 0); port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 33); PHI: in std_logic; holdn: in std_logic; RESULT: out std_logic_vector(0 to 127) ); end MULTIPLIER_34_34; architecture MULTIPLIER of MULTIPLIER_34_34 is signal PPBIT:std_logic_vector(0 to 628); signal INT_CARRY: std_logic_vector(0 to 128); signal INT_SUM: std_logic_vector(0 to 127); signal LOGIC_ZERO: std_logic; signal INT_CARRYR: std_logic_vector(0 to 128); signal INT_SUMR: std_logic_vector(0 to 127); begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_34 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 33) => MULTIPLIER(0 to 33), SUMMAND(0 to 628) => PPBIT(0 to 628) ); W:WALLACE_34_34 port map ( SUMMAND(0 to 628) => PPBIT(0 to 628), CARRY(0 to 65) => INT_CARRY(1 to 66), SUM(0 to 66) => INT_SUM(0 to 66) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(67) <= LOGIC_ZERO; INT_CARRY(68) <= LOGIC_ZERO; INT_CARRY(69) <= LOGIC_ZERO; INT_CARRY(70) <= LOGIC_ZERO; INT_CARRY(71) <= LOGIC_ZERO; INT_CARRY(72) <= LOGIC_ZERO; INT_CARRY(73) <= LOGIC_ZERO; INT_CARRY(74) <= LOGIC_ZERO; INT_CARRY(75) <= LOGIC_ZERO; INT_CARRY(76) <= LOGIC_ZERO; INT_CARRY(77) <= LOGIC_ZERO; INT_CARRY(78) <= LOGIC_ZERO; INT_CARRY(79) <= LOGIC_ZERO; INT_CARRY(80) <= LOGIC_ZERO; INT_CARRY(81) <= LOGIC_ZERO; INT_CARRY(82) <= LOGIC_ZERO; INT_CARRY(83) <= LOGIC_ZERO; INT_CARRY(84) <= LOGIC_ZERO; INT_CARRY(85) <= LOGIC_ZERO; INT_CARRY(86) <= LOGIC_ZERO; INT_CARRY(87) <= LOGIC_ZERO; INT_CARRY(88) <= LOGIC_ZERO; INT_CARRY(89) <= LOGIC_ZERO; INT_CARRY(90) <= LOGIC_ZERO; INT_CARRY(91) <= LOGIC_ZERO; INT_CARRY(92) <= LOGIC_ZERO; INT_CARRY(93) <= LOGIC_ZERO; INT_CARRY(94) <= LOGIC_ZERO; INT_CARRY(95) <= LOGIC_ZERO; INT_CARRY(96) <= LOGIC_ZERO; INT_CARRY(97) <= LOGIC_ZERO; INT_CARRY(98) <= LOGIC_ZERO; INT_CARRY(99) <= LOGIC_ZERO; INT_CARRY(100) <= LOGIC_ZERO; INT_CARRY(101) <= LOGIC_ZERO; INT_CARRY(102) <= LOGIC_ZERO; INT_CARRY(103) <= LOGIC_ZERO; INT_CARRY(104) <= LOGIC_ZERO; INT_CARRY(105) <= LOGIC_ZERO; INT_CARRY(106) <= LOGIC_ZERO; INT_CARRY(107) <= LOGIC_ZERO; INT_CARRY(108) <= LOGIC_ZERO; INT_CARRY(109) <= LOGIC_ZERO; INT_CARRY(110) <= LOGIC_ZERO; INT_CARRY(111) <= LOGIC_ZERO; INT_CARRY(112) <= LOGIC_ZERO; INT_CARRY(113) <= LOGIC_ZERO; INT_CARRY(114) <= LOGIC_ZERO; INT_CARRY(115) <= LOGIC_ZERO; INT_CARRY(116) <= LOGIC_ZERO; INT_CARRY(117) <= LOGIC_ZERO; INT_CARRY(118) <= LOGIC_ZERO; INT_CARRY(119) <= LOGIC_ZERO; INT_CARRY(120) <= LOGIC_ZERO; INT_CARRY(121) <= LOGIC_ZERO; INT_CARRY(122) <= LOGIC_ZERO; INT_CARRY(123) <= LOGIC_ZERO; INT_CARRY(124) <= LOGIC_ZERO; INT_CARRY(125) <= LOGIC_ZERO; INT_CARRY(126) <= LOGIC_ZERO; INT_CARRY(127) <= LOGIC_ZERO; INT_SUM(67) <= LOGIC_ZERO; INT_SUM(68) <= LOGIC_ZERO; INT_SUM(69) <= LOGIC_ZERO; INT_SUM(70) <= LOGIC_ZERO; INT_SUM(71) <= LOGIC_ZERO; INT_SUM(72) <= LOGIC_ZERO; INT_SUM(73) <= LOGIC_ZERO; INT_SUM(74) <= LOGIC_ZERO; INT_SUM(75) <= LOGIC_ZERO; INT_SUM(76) <= LOGIC_ZERO; INT_SUM(77) <= LOGIC_ZERO; INT_SUM(78) <= LOGIC_ZERO; INT_SUM(79) <= LOGIC_ZERO; INT_SUM(80) <= LOGIC_ZERO; INT_SUM(81) <= LOGIC_ZERO; INT_SUM(82) <= LOGIC_ZERO; INT_SUM(83) <= LOGIC_ZERO; INT_SUM(84) <= LOGIC_ZERO; INT_SUM(85) <= LOGIC_ZERO; INT_SUM(86) <= LOGIC_ZERO; INT_SUM(87) <= LOGIC_ZERO; INT_SUM(88) <= LOGIC_ZERO; INT_SUM(89) <= LOGIC_ZERO; INT_SUM(90) <= LOGIC_ZERO; INT_SUM(91) <= LOGIC_ZERO; INT_SUM(92) <= LOGIC_ZERO; INT_SUM(93) <= LOGIC_ZERO; INT_SUM(94) <= LOGIC_ZERO; INT_SUM(95) <= LOGIC_ZERO; INT_SUM(96) <= LOGIC_ZERO; INT_SUM(97) <= LOGIC_ZERO; INT_SUM(98) <= LOGIC_ZERO; INT_SUM(99) <= LOGIC_ZERO; INT_SUM(100) <= LOGIC_ZERO; INT_SUM(101) <= LOGIC_ZERO; INT_SUM(102) <= LOGIC_ZERO; INT_SUM(103) <= LOGIC_ZERO; INT_SUM(104) <= LOGIC_ZERO; INT_SUM(105) <= LOGIC_ZERO; INT_SUM(106) <= LOGIC_ZERO; INT_SUM(107) <= LOGIC_ZERO; INT_SUM(108) <= LOGIC_ZERO; INT_SUM(109) <= LOGIC_ZERO; INT_SUM(110) <= LOGIC_ZERO; INT_SUM(111) <= LOGIC_ZERO; INT_SUM(112) <= LOGIC_ZERO; INT_SUM(113) <= LOGIC_ZERO; INT_SUM(114) <= LOGIC_ZERO; INT_SUM(115) <= LOGIC_ZERO; INT_SUM(116) <= LOGIC_ZERO; INT_SUM(117) <= LOGIC_ZERO; INT_SUM(118) <= LOGIC_ZERO; INT_SUM(119) <= LOGIC_ZERO; INT_SUM(120) <= LOGIC_ZERO; INT_SUM(121) <= LOGIC_ZERO; INT_SUM(122) <= LOGIC_ZERO; INT_SUM(123) <= LOGIC_ZERO; INT_SUM(124) <= LOGIC_ZERO; INT_SUM(125) <= LOGIC_ZERO; INT_SUM(126) <= LOGIC_ZERO; INT_SUM(127) <= LOGIC_ZERO; INT_SUMR(67 to 127) <= INT_SUM(67 to 127); INT_CARRYR(67 to 127) <= INT_CARRY(67 to 127); INT_CARRYR(0) <= INT_CARRY(0); reg : if MULPIPE /= 0 generate process (PHI) begin if rising_edge(PHI ) then if (holdn = '1') then INT_SUMR(0 to 66) <= INT_SUM(0 to 66); INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66); end if; end if; end process; end generate; noreg : if MULPIPE = 0 generate INT_SUMR(0 to 66) <= INT_SUM(0 to 66); INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66); end generate; D:DBLCADDER_128_128 port map ( OPA(0 to 127) => INT_SUMR(0 to 127), OPB(0 to 127) => INT_CARRYR(0 to 127), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 127) => RESULT(0 to 127) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ -- -- Modgen multiplier created Fri Aug 16 16:35:11 2002 -- ------------------------------------------------------------ -- START: Multiplier Entitiy ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -- START: Top entity ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_33 is generic (mulpipe : integer := 0); port(clk : in std_ulogic; holdn: in std_ulogic; X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(32 downto 0); P: out std_logic_vector(65 downto 0)); end MUL_33_33; architecture A of MUL_33_33 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 33); signal Q: std_logic_vector(0 to 127); begin U1: MULTIPLIER_34_34 generic map (mulpipe) port map(A,B,CLK, holdn ,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(17); B(18) <= Y(18); B(19) <= Y(19); B(20) <= Y(20); B(21) <= Y(21); B(22) <= Y(22); B(23) <= Y(23); B(24) <= Y(24); B(25) <= Y(25); B(26) <= Y(26); B(27) <= Y(27); B(28) <= Y(28); B(29) <= Y(29); B(30) <= Y(30); B(31) <= Y(31); B(32) <= Y(32); B(33) <= Y(32); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); P(42) <= Q(42); P(43) <= Q(43); P(44) <= Q(44); P(45) <= Q(45); P(46) <= Q(46); P(47) <= Q(47); P(48) <= Q(48); P(49) <= Q(49); P(50) <= Q(50); P(51) <= Q(51); P(52) <= Q(52); P(53) <= Q(53); P(54) <= Q(54); P(55) <= Q(55); P(56) <= Q(56); P(57) <= Q(57); P(58) <= Q(58); P(59) <= Q(59); P(60) <= Q(60); P(61) <= Q(61); P(62) <= Q(62); P(63) <= Q(63); P(64) <= Q(64); P(65) <= Q(65); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity ADD32 is port(X: in std_logic_vector(31 downto 0); Y: in std_logic_vector(31 downto 0); CI: in std_logic; S: out std_logic_vector(31 downto 0); CO: out std_logic); end ADD32; architecture A of ADD32 is signal A,B,Q: std_logic_vector(0 to 31); signal CLK: std_logic; begin U1: DBLCADDER_32_32 port map(A,B,CI,CLK,Q,CO); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); B(0) <= Y(0); A(1) <= X(1); B(1) <= Y(1); A(2) <= X(2); B(2) <= Y(2); A(3) <= X(3); B(3) <= Y(3); A(4) <= X(4); B(4) <= Y(4); A(5) <= X(5); B(5) <= Y(5); A(6) <= X(6); B(6) <= Y(6); A(7) <= X(7); B(7) <= Y(7); A(8) <= X(8); B(8) <= Y(8); A(9) <= X(9); B(9) <= Y(9); A(10) <= X(10); B(10) <= Y(10); A(11) <= X(11); B(11) <= Y(11); A(12) <= X(12); B(12) <= Y(12); A(13) <= X(13); B(13) <= Y(13); A(14) <= X(14); B(14) <= Y(14); A(15) <= X(15); B(15) <= Y(15); A(16) <= X(16); B(16) <= Y(16); A(17) <= X(17); B(17) <= Y(17); A(18) <= X(18); B(18) <= Y(18); A(19) <= X(19); B(19) <= Y(19); A(20) <= X(20); B(20) <= Y(20); A(21) <= X(21); B(21) <= Y(21); A(22) <= X(22); B(22) <= Y(22); A(23) <= X(23); B(23) <= Y(23); A(24) <= X(24); B(24) <= Y(24); A(25) <= X(25); B(25) <= Y(25); A(26) <= X(26); B(26) <= Y(26); A(27) <= X(27); B(27) <= Y(27); A(28) <= X(28); B(28) <= Y(28); A(29) <= X(29); B(29) <= Y(29); A(30) <= X(30); B(30) <= Y(30); A(31) <= X(31); B(31) <= Y(31); S(0) <= Q(0); S(1) <= Q(1); S(2) <= Q(2); S(3) <= Q(3); S(4) <= Q(4); S(5) <= Q(5); S(6) <= Q(6); S(7) <= Q(7); S(8) <= Q(8); S(9) <= Q(9); S(10) <= Q(10); S(11) <= Q(11); S(12) <= Q(12); S(13) <= Q(13); S(14) <= Q(14); S(15) <= Q(15); S(16) <= Q(16); S(17) <= Q(17); S(18) <= Q(18); S(19) <= Q(19); S(20) <= Q(20); S(21) <= Q(21); S(22) <= Q(22); S(23) <= Q(23); S(24) <= Q(24); S(25) <= Q(25); S(26) <= Q(26); S(27) <= Q(27); S(28) <= Q(28); S(29) <= Q(29); S(30) <= Q(30); S(31) <= Q(31); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_17_17 is generic (mulpipe : integer := 0); port(clk : in std_ulogic; holdn: in std_ulogic; X: in std_logic_vector(16 downto 0); Y: in std_logic_vector(16 downto 0); P: out std_logic_vector(33 downto 0)); end MUL_17_17; architecture A of MUL_17_17 is signal A: std_logic_vector(0 to 17); signal B: std_logic_vector(0 to 17); signal Q: std_logic_vector(0 to 63); begin U1: MULTIPLIER_18_18 generic map (mulpipe) port map(A,B,CLK, holdn, Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(16); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(16); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); end A;
----------------------------------------------------------------------------- -- File: leaves.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: A set of multipliers generated from the Arithmetic Module -- Generator at Norwegian University of Science and Technology. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; package blocks is component FLIPFLOP port ( DIN, CLK: in std_logic; DOUT: out std_logic ); end component; component DBLCADDER_32_32 port(OPA: in std_logic_vector(0 to 31); OPB: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; SUM: out std_logic_vector(0 to 31); COUT: out std_logic); end component; component FULL_ADDER port ( DATA_A, DATA_B, DATA_C: in std_logic; SAVE, CARRY: out std_logic ); end component; component HALF_ADDER port ( DATA_A, DATA_B: in std_logic; SAVE, CARRY: out std_logic ); end component; component R_GATE port ( INA, INB, INC: in std_logic; PPBIT: out std_logic ); end component; component DECODER port ( INA, INB, INC: in std_logic; TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic ); end component; component PP_LOW port ( ONEPOS, ONENEG, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end component; component PP_MIDDLE port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB, INC, IND: in std_logic; PPBIT: out std_logic ); end component; component PP_HIGH port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end component; component BLOCK0 port ( A,B,PHI: in std_logic; POUT,GOUT: out std_logic ); end component; component INVBLOCK port ( GIN,PHI:in std_logic; GOUT:out std_logic ); end component; component BLOCK1 port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end component; component BLOCK1A port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end component; component BLOCK2 port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end component; component BLOCK2A port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end component; component PRESTAGE_32 port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 31); GOUT: out std_logic_vector(0 to 32) ); end component; component XXOR1 port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end component; component XXOR2 port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end component; component DBLCTREE_32 port ( PIN:in std_logic_vector(0 to 31); GIN:in std_logic_vector(0 to 32); PHI:in std_logic; GOUT:out std_logic_vector(0 to 32); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_32 port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 32); SUM: out std_logic_vector(0 to 31); COUT: out std_logic ); end component; component DBLC_0_32 port ( PIN: in std_logic_vector(0 to 31); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 30); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_1_32 port ( PIN: in std_logic_vector(0 to 30); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 28); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_2_32 port ( PIN: in std_logic_vector(0 to 28); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 24); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_3_32 port ( PIN: in std_logic_vector(0 to 24); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 16); GOUT: out std_logic_vector(0 to 32) ); end component; component DBLC_4_32 port ( PIN: in std_logic_vector(0 to 16); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 32) ); end component; component PRESTAGE_64 port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 63); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLCTREE_64 port ( PIN:in std_logic_vector(0 to 63); GIN:in std_logic_vector(0 to 64); PHI:in std_logic; GOUT:out std_logic_vector(0 to 64); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_64 port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 64); SUM: out std_logic_vector(0 to 63); COUT: out std_logic ); end component; component DBLC_0_64 port ( PIN: in std_logic_vector(0 to 63); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 62); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_1_64 port ( PIN: in std_logic_vector(0 to 62); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 60); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_2_64 port ( PIN: in std_logic_vector(0 to 60); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 56); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_3_64 port ( PIN: in std_logic_vector(0 to 56); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 48); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_4_64 port ( PIN: in std_logic_vector(0 to 48); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 32); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_5_64 port ( PIN: in std_logic_vector(0 to 32); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 64) ); end component; component DBLC_0_128 port ( PIN: in std_logic_vector(0 to 127); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 126); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_1_128 port ( PIN: in std_logic_vector(0 to 126); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 124); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_2_128 port ( PIN: in std_logic_vector(0 to 124); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 120); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_3_128 port ( PIN: in std_logic_vector(0 to 120); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 112); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_4_128 port ( PIN: in std_logic_vector(0 to 112); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 96); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_5_128 port ( PIN: in std_logic_vector(0 to 96); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 64); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLC_6_128 port ( PIN: in std_logic_vector(0 to 64); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 128) ); end component; component PRESTAGE_128 port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 127); GOUT: out std_logic_vector(0 to 128) ); end component; component DBLCTREE_128 port ( PIN:in std_logic_vector(0 to 127); GIN:in std_logic_vector(0 to 128); PHI:in std_logic; GOUT:out std_logic_vector(0 to 128); POUT:out std_logic_vector(0 to 0) ); end component; component XORSTAGE_128 port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); PBIT: in std_logic; PHI: in std_logic; CARRY: in std_logic_vector(0 to 128); SUM: out std_logic_vector(0 to 127); COUT: out std_logic ); end component; component BOOTHCODER_18_18 port ( OPA: in std_logic_vector(0 to 17); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 188) ); end component; component WALLACE_18_18 port ( SUMMAND: in std_logic_vector(0 to 188); CARRY: out std_logic_vector(0 to 33); SUM: out std_logic_vector(0 to 34) ); end component; component DBLCADDER_64_64 port ( OPA:in std_logic_vector(0 to 63); OPB:in std_logic_vector(0 to 63); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 63); COUT:out std_logic ); end component; component BOOTHCODER_34_10 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 9); SUMMAND: out std_logic_vector(0 to 184) ); end component; component WALLACE_34_10 port ( SUMMAND: in std_logic_vector(0 to 184); CARRY: out std_logic_vector(0 to 41); SUM: out std_logic_vector(0 to 42) ); end component; component BOOTHCODER_34_18 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 332) ); end component; component WALLACE_34_18 port ( SUMMAND: in std_logic_vector(0 to 332); CARRY: out std_logic_vector(0 to 49); SUM: out std_logic_vector(0 to 50) ); end component; component BOOTHCODER_34_34 port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 33); SUMMAND: out std_logic_vector(0 to 628) ); end component; component WALLACE_34_34 port ( SUMMAND: in std_logic_vector(0 to 628); CARRY: out std_logic_vector(0 to 65); SUM: out std_logic_vector(0 to 66) ); end component; component DBLCADDER_128_128 port ( OPA:in std_logic_vector(0 to 127); OPB:in std_logic_vector(0 to 127); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 127); COUT:out std_logic ); end component; component MULTIPLIER_18_18 generic (mulpipe : integer := 0); port(MULTIPLICAND: in std_logic_vector(0 to 17); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_ulogic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_10 port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 9); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_18 port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63)); end component; component MULTIPLIER_34_34 generic (mulpipe : integer := 0); port(MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 33); PHI: in std_logic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 127)); end component; end; ------------------------------------------------------------ -- START: Entities used within the Modified Booth Recoding ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity FLIPFLOP is port ( DIN: in std_logic; CLK: in std_logic; DOUT: out std_logic ); end FLIPFLOP; architecture FLIPFLOP of FLIPFLOP is begin process(CLK) begin if(CLK='1')and(CLK'event)then DOUT <= DIN; end if; end process; end FLIPFLOP; library ieee; use ieee.std_logic_1164.all; entity PP_LOW is port ( ONEPOS, ONENEG, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end PP_LOW; architecture PP_LOW of PP_LOW is begin PPBIT <= (ONEPOS and INA) or (ONENEG and INB) or TWONEG; end PP_LOW; library ieee; use ieee.std_logic_1164.all; entity PP_MIDDLE is port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB, INC, IND: in std_logic; PPBIT: out std_logic ); end PP_MIDDLE; architecture PP_MIDDLE of PP_MIDDLE is begin PPBIT <= not((not(INA and TWOPOS)) and (not(INB and TWONEG)) and (not(INC and ONEPOS)) and (not(IND and ONENEG))); end PP_MIDDLE; library ieee; use ieee.std_logic_1164.all; entity PP_HIGH is port ( ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic; INA, INB: in std_logic; PPBIT: out std_logic ); end PP_HIGH; architecture PP_HIGH of PP_HIGH is begin PPBIT <= not ((INA and ONEPOS) or (INB and ONENEG) or (INA and TWOPOS) or (INB and TWONEG)); end PP_HIGH; library ieee; use ieee.std_logic_1164.all; entity R_GATE is port ( INA, INB, INC: in std_logic; PPBIT: out std_logic ); end R_GATE; architecture R_GATE of R_GATE is begin PPBIT <= (not(INA and INB)) and INC; end R_GATE; library ieee; use ieee.std_logic_1164.all; entity DECODER is port ( INA, INB, INC: in std_logic; TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic ); end DECODER; architecture DECODER of DECODER is begin TWOPOS <= not(not(INA and INB and (not INC))); TWONEG <= not(not((not INA) and (not INB) and INC)); ONEPOS <= ((not INA) and INB and (not INC)) or ((not INC) and (not INB) and INA); ONENEG <= (INA and (not INB) and INC) or (INC and INB and (not INA)); end DECODER; library ieee; use ieee.std_logic_1164.all; entity FULL_ADDER is port ( DATA_A, DATA_B, DATA_C: in std_logic; SAVE, CARRY: out std_logic ); end FULL_ADDER; architecture FULL_ADDER of FULL_ADDER is signal TMP: std_logic; begin TMP <= DATA_A xor DATA_B; SAVE <= TMP xor DATA_C; CARRY <= not((not (TMP and DATA_C)) and (not (DATA_A and DATA_B))); end FULL_ADDER; library ieee; use ieee.std_logic_1164.all; entity HALF_ADDER is port ( DATA_A, DATA_B: in std_logic; SAVE, CARRY: out std_logic ); end HALF_ADDER; architecture HALF_ADDER of HALF_ADDER is begin SAVE <= DATA_A xor DATA_B; CARRY <= DATA_A and DATA_B; end HALF_ADDER; library ieee; use ieee.std_logic_1164.all; entity INVBLOCK is port ( GIN,PHI:in std_logic; GOUT:out std_logic ); end INVBLOCK; architecture INVBLOCK_regular of INVBLOCK is begin GOUT <= not GIN; end INVBLOCK_regular; library ieee; use ieee.std_logic_1164.all; entity XXOR1 is port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end XXOR1; architecture XXOR_regular of XXOR1 is begin SUM <= (not (A xor B)) xor GIN; end XXOR_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK0 is port ( A,B,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK0; architecture BLOCK0_regular of BLOCK0 is begin POUT <= not(A or B); GOUT <= not(A and B); end BLOCK0_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK1 is port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK1; architecture BLOCK1_regular of BLOCK1 is begin POUT <= not(PIN1 or PIN2); GOUT <= not(GIN2 and (PIN2 or GIN1)); end BLOCK1_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK2 is port ( PIN1,PIN2,GIN1,GIN2,PHI:in std_logic; POUT,GOUT:out std_logic ); end BLOCK2; architecture BLOCK2_regular of BLOCK2 is begin POUT <= not(PIN1 and PIN2); GOUT <= not(GIN2 or (PIN2 and GIN1)); end BLOCK2_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK1A is port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end BLOCK1A; architecture BLOCK1A_regular of BLOCK1A is begin GOUT <= not(GIN2 and (PIN2 or GIN1)); end BLOCK1A_regular; library ieee; use ieee.std_logic_1164.all; entity BLOCK2A is port ( PIN2,GIN1,GIN2,PHI:in std_logic; GOUT:out std_logic ); end BLOCK2A; architecture BLOCK2A_regular of BLOCK2A is begin GOUT <= not(GIN2 or (PIN2 and GIN1)); end BLOCK2A_regular; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_64 is port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 63); GOUT: out std_logic_vector(0 to 64) ); end PRESTAGE_64; architecture PRESTAGE of PRESTAGE_64 is begin -- PRESTAGE U1:for I in 0 to 63 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: Level 0 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_64 is port ( PIN: in std_logic_vector(0 to 63); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 62); GOUT: out std_logic_vector(0 to 64) ); end DBLC_0_64; architecture DBLC_0 of DBLC_0_64 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 64 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_64 is port ( PIN: in std_logic_vector(0 to 62); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 60); GOUT: out std_logic_vector(0 to 64) ); end DBLC_1_64; architecture DBLC_1 of DBLC_1_64 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 64 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_64 is port ( PIN: in std_logic_vector(0 to 60); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 56); GOUT: out std_logic_vector(0 to 64) ); end DBLC_2_64; architecture DBLC_2 of DBLC_2_64 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 64 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_64 is port ( PIN: in std_logic_vector(0 to 56); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 48); GOUT: out std_logic_vector(0 to 64) ); end DBLC_3_64; architecture DBLC_3 of DBLC_3_64 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 64 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_64 is port ( PIN: in std_logic_vector(0 to 48); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 32); GOUT: out std_logic_vector(0 to 64) ); end DBLC_4_64; architecture DBLC_4 of DBLC_4_64 is begin -- Architecture DBLC_4 U1: for I in 0 to 15 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 64 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; -- The DBLC-tree: Level 5 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_5_64 is port ( PIN: in std_logic_vector(0 to 32); GIN: in std_logic_vector(0 to 64); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 64) ); end DBLC_5_64; architecture DBLC_5 of DBLC_5_64 is begin -- Architecture DBLC_5 U1: for I in 0 to 31 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 32 to 63 generate U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 64 to 64 generate U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I)); end generate U3; end DBLC_5; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_64 is port ( A: in std_logic_vector(0 to 63); B: in std_logic_vector(0 to 63); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 64); SUM: out std_logic_vector(0 to 63); COUT: out std_logic ); end XORSTAGE_64; architecture XORSTAGE of XORSTAGE_64 is begin -- XORSTAGE U2:for I in 0 to 63 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U1: BLOCK1A port map(PBIT,CARRY(0),CARRY(64),PHI,COUT); end XORSTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_64 is port ( PIN:in std_logic_vector(0 to 63); GIN:in std_logic_vector(0 to 64); PHI:in std_logic; GOUT:out std_logic_vector(0 to 64); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_64; architecture DBLCTREE of DBLCTREE_64 is signal INTPROP_0: std_logic_vector(0 to 62); signal INTGEN_0: std_logic_vector(0 to 64); signal INTPROP_1: std_logic_vector(0 to 60); signal INTGEN_1: std_logic_vector(0 to 64); signal INTPROP_2: std_logic_vector(0 to 56); signal INTGEN_2: std_logic_vector(0 to 64); signal INTPROP_3: std_logic_vector(0 to 48); signal INTGEN_3: std_logic_vector(0 to 64); signal INTPROP_4: std_logic_vector(0 to 32); signal INTGEN_4: std_logic_vector(0 to 64); begin -- Architecture DBLCTREE U_0: DBLC_0_64 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_64 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_64 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_64 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_64 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4); U_5: DBLC_5_64 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_64_64 is port ( OPA:in std_logic_vector(0 to 63); OPB:in std_logic_vector(0 to 63); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 63); COUT:out std_logic ); end DBLCADDER_64_64; architecture DBLCADDER of DBLCADDER_64_64 is signal INTPROP: std_logic_vector(0 to 63); signal INTGEN: std_logic_vector(0 to 64); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 64); begin -- Architecture DBLCADDER U1: PRESTAGE_64 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_64 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_64 port map(OPA(0 to 63),OPB(0 to 63),PBIT(0),PHI,CARRY(0 to 64),SUM,COUT); end DBLCADDER; ------------------------------------------------------------ -- END: Architectures used with the DBLC adder ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity XXOR2 is port ( A,B,GIN,PHI:in std_logic; SUM:out std_logic ); end XXOR2; architecture XXOR_true of XXOR2 is begin SUM <= (A xor B) xor GIN; end XXOR_true; -- -- Modgen adder created Fri Aug 16 14:47:23 2002 -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_32 is port ( PIN: in std_logic_vector(0 to 31); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 30); GOUT: out std_logic_vector(0 to 32) ); end DBLC_0_32; architecture DBLC_0 of DBLC_0_32 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 32 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_32 is port ( PIN: in std_logic_vector(0 to 30); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 28); GOUT: out std_logic_vector(0 to 32) ); end DBLC_1_32; architecture DBLC_1 of DBLC_1_32 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 32 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_32 is port ( PIN: in std_logic_vector(0 to 28); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 24); GOUT: out std_logic_vector(0 to 32) ); end DBLC_2_32; architecture DBLC_2 of DBLC_2_32 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 32 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_32 is port ( PIN: in std_logic_vector(0 to 24); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 16); GOUT: out std_logic_vector(0 to 32) ); end DBLC_3_32; architecture DBLC_3 of DBLC_3_32 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 32 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_32 is port ( PIN: in std_logic_vector(0 to 16); GIN: in std_logic_vector(0 to 32); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 32) ); end DBLC_4_32; architecture DBLC_4 of DBLC_4_32 is begin -- Architecture DBLC_4 GOUT(0 to 15) <= GIN(0 to 15); U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 32 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_32 is port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 32); SUM: out std_logic_vector(0 to 31); COUT: out std_logic ); end XORSTAGE_32; architecture XORSTAGE of XORSTAGE_32 is begin -- XORSTAGE U2:for I in 0 to 15 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U3:for I in 16 to 31 generate U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U3; U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(32),PHI,COUT); end XORSTAGE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_32 is port ( A: in std_logic_vector(0 to 31); B: in std_logic_vector(0 to 31); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 31); GOUT: out std_logic_vector(0 to 32) ); end PRESTAGE_32; architecture PRESTAGE of PRESTAGE_32 is begin -- PRESTAGE U1:for I in 0 to 31 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_32 is port ( PIN:in std_logic_vector(0 to 31); GIN:in std_logic_vector(0 to 32); PHI:in std_logic; GOUT:out std_logic_vector(0 to 32); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_32; architecture DBLCTREE of DBLCTREE_32 is signal INTPROP_0: std_logic_vector(0 to 30); signal INTGEN_0: std_logic_vector(0 to 32); signal INTPROP_1: std_logic_vector(0 to 28); signal INTGEN_1: std_logic_vector(0 to 32); signal INTPROP_2: std_logic_vector(0 to 24); signal INTGEN_2: std_logic_vector(0 to 32); signal INTPROP_3: std_logic_vector(0 to 16); signal INTGEN_3: std_logic_vector(0 to 32); begin -- Architecture DBLCTREE U_0: DBLC_0_32 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_32 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_32 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_32 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_32 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_32_32 is port ( OPA:in std_logic_vector(0 to 31); OPB:in std_logic_vector(0 to 31); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 31); COUT:out std_logic ); end DBLCADDER_32_32; architecture DBLCADDER of DBLCADDER_32_32 is signal INTPROP: std_logic_vector(0 to 31); signal INTGEN: std_logic_vector(0 to 32); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 32); begin -- Architecture DBLCADDER U1: PRESTAGE_32 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_32 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_32 port map(OPA(0 to 31),OPB(0 to 31),PBIT(0),PHI,CARRY(0 to 32),SUM,COUT); end DBLCADDER; ------------------------------------------------------------ -- END: Architectures used with the DBLC adder ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity PRESTAGE_128 is port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); CIN: in std_logic; PHI: in std_logic; POUT: out std_logic_vector(0 to 127); GOUT: out std_logic_vector(0 to 128) ); end PRESTAGE_128; architecture PRESTAGE of PRESTAGE_128 is begin -- PRESTAGE U1:for I in 0 to 127 generate U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1)); end generate U1; U2: INVBLOCK port map(CIN,PHI,GOUT(0)); end PRESTAGE; -- The DBLC-tree: Level 0 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_0_128 is port ( PIN: in std_logic_vector(0 to 127); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 126); GOUT: out std_logic_vector(0 to 128) ); end DBLC_0_128; architecture DBLC_0 of DBLC_0_128 is begin -- Architecture DBLC_0 U1: for I in 0 to 0 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 1 to 1 generate U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 2 to 128 generate U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I)); end generate U3; end DBLC_0; -- The DBLC-tree: Level 1 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_1_128 is port ( PIN: in std_logic_vector(0 to 126); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 124); GOUT: out std_logic_vector(0 to 128) ); end DBLC_1_128; architecture DBLC_1 of DBLC_1_128 is begin -- Architecture DBLC_1 U1: for I in 0 to 1 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 2 to 3 generate U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 4 to 128 generate U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I)); end generate U3; end DBLC_1; -- The DBLC-tree: Level 2 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_2_128 is port ( PIN: in std_logic_vector(0 to 124); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 120); GOUT: out std_logic_vector(0 to 128) ); end DBLC_2_128; architecture DBLC_2 of DBLC_2_128 is begin -- Architecture DBLC_2 U1: for I in 0 to 3 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 4 to 7 generate U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 8 to 128 generate U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I)); end generate U3; end DBLC_2; -- The DBLC-tree: Level 3 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_3_128 is port ( PIN: in std_logic_vector(0 to 120); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 112); GOUT: out std_logic_vector(0 to 128) ); end DBLC_3_128; architecture DBLC_3 of DBLC_3_128 is begin -- Architecture DBLC_3 U1: for I in 0 to 7 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 8 to 15 generate U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 16 to 128 generate U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I)); end generate U3; end DBLC_3; -- The DBLC-tree: Level 4 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_4_128 is port ( PIN: in std_logic_vector(0 to 112); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 96); GOUT: out std_logic_vector(0 to 128) ); end DBLC_4_128; architecture DBLC_4 of DBLC_4_128 is begin -- Architecture DBLC_4 U1: for I in 0 to 15 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 16 to 31 generate U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 32 to 128 generate U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I)); end generate U3; end DBLC_4; -- The DBLC-tree: Level 5 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_5_128 is port ( PIN: in std_logic_vector(0 to 96); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 64); GOUT: out std_logic_vector(0 to 128) ); end DBLC_5_128; architecture DBLC_5 of DBLC_5_128 is begin -- Architecture DBLC_5 U1: for I in 0 to 31 generate U11: INVBLOCK port map(GIN(I),PHI,GOUT(I)); end generate U1; U2: for I in 32 to 63 generate U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 64 to 128 generate U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I)); end generate U3; end DBLC_5; -- The DBLC-tree: Level 6 library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLC_6_128 is port ( PIN: in std_logic_vector(0 to 64); GIN: in std_logic_vector(0 to 128); PHI: in std_logic; POUT: out std_logic_vector(0 to 0); GOUT: out std_logic_vector(0 to 128) ); end DBLC_6_128; architecture DBLC_6 of DBLC_6_128 is begin -- Architecture DBLC_6 GOUT(0 to 63) <= GIN(0 to 63); U2: for I in 64 to 127 generate U21: BLOCK1A port map(PIN(I-64),GIN(I-64),GIN(I),PHI,GOUT(I)); end generate U2; U3: for I in 128 to 128 generate U31: BLOCK1 port map(PIN(I-128),PIN(I-64),GIN(I-64),GIN(I),PHI,POUT(I-128),GOUT(I)); end generate U3; end DBLC_6; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity XORSTAGE_128 is port ( A: in std_logic_vector(0 to 127); B: in std_logic_vector(0 to 127); PBIT, PHI: in std_logic; CARRY: in std_logic_vector(0 to 128); SUM: out std_logic_vector(0 to 127); COUT: out std_logic ); end XORSTAGE_128; architecture XORSTAGE of XORSTAGE_128 is begin -- XORSTAGE U2:for I in 0 to 63 generate U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U2; U3:for I in 64 to 127 generate U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I)); end generate U3; U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(128),PHI,COUT); end XORSTAGE; -- The DBLC-tree: All levels encapsulated library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCTREE_128 is port ( PIN:in std_logic_vector(0 to 127); GIN:in std_logic_vector(0 to 128); PHI:in std_logic; GOUT:out std_logic_vector(0 to 128); POUT:out std_logic_vector(0 to 0) ); end DBLCTREE_128; architecture DBLCTREE of DBLCTREE_128 is signal INTPROP_0: std_logic_vector(0 to 126); signal INTGEN_0: std_logic_vector(0 to 128); signal INTPROP_1: std_logic_vector(0 to 124); signal INTGEN_1: std_logic_vector(0 to 128); signal INTPROP_2: std_logic_vector(0 to 120); signal INTGEN_2: std_logic_vector(0 to 128); signal INTPROP_3: std_logic_vector(0 to 112); signal INTGEN_3: std_logic_vector(0 to 128); signal INTPROP_4: std_logic_vector(0 to 96); signal INTGEN_4: std_logic_vector(0 to 128); signal INTPROP_5: std_logic_vector(0 to 64); signal INTGEN_5: std_logic_vector(0 to 128); begin -- Architecture DBLCTREE U_0: DBLC_0_128 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0); U_1: DBLC_1_128 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1); U_2: DBLC_2_128 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2); U_3: DBLC_3_128 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3); U_4: DBLC_4_128 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4); U_5: DBLC_5_128 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>INTPROP_5,GOUT=>INTGEN_5); U_6: DBLC_6_128 port map(PIN=>INTPROP_5,GIN=>INTGEN_5,PHI=>PHI,POUT=>POUT,GOUT=>GOUT); end DBLCTREE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity DBLCADDER_128_128 is port ( OPA:in std_logic_vector(0 to 127); OPB:in std_logic_vector(0 to 127); CIN:in std_logic; PHI:in std_logic; SUM:out std_logic_vector(0 to 127); COUT:out std_logic ); end DBLCADDER_128_128; architecture DBLCADDER of DBLCADDER_128_128 is signal INTPROP: std_logic_vector(0 to 127); signal INTGEN: std_logic_vector(0 to 128); signal PBIT:std_logic_vector(0 to 0); signal CARRY: std_logic_vector(0 to 128); begin -- Architecture DBLCADDER U1: PRESTAGE_128 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN); U2: DBLCTREE_128 port map(INTPROP,INTGEN,PHI,CARRY,PBIT); U3: XORSTAGE_128 port map(OPA(0 to 127),OPB(0 to 127),PBIT(0),PHI,CARRY(0 to 128),SUM,COUT); end DBLCADDER; -- -- Modified Booth algorithm architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_18_18 is port ( OPA: in std_logic_vector(0 to 17); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 188) ); end BOOTHCODER_18_18; ------------------------------------------------------------ -- END: Entities used within the Modified Booth Recoding ------------------------------------------------------------ architecture BOOTHCODER of BOOTHCODER_18_18 is -- Components used in the architecture -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 17); signal INT_MULTIPLIER: std_logic_vector(0 to 35); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); PPH_0:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); SUMMAND(100) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_17:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_18:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_19:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_20:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_21:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_22:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_23:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_24:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_25:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_26:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_27:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_28:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_29:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_30:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_31:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_32:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(101) ); PPM_33:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(109) ); SUMMAND(110) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(118) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_34:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_35:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_36:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_37:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_38:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_39:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_40:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_41:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_42:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_43:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_44:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_45:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_46:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_47:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(102) ); PPM_48:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(111) ); PPM_49:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(119) ); PPM_50:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(126) ); SUMMAND(127) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(134) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_51:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_52:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_53:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_54:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_55:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_56:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_57:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_58:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_59:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_60:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_61:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_62:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(103) ); PPM_63:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(112) ); PPM_64:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(120) ); PPM_65:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(128) ); PPM_66:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(135) ); PPM_67:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(141) ); SUMMAND(142) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(148) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_68:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_69:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_70:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_71:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_72:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_73:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_74:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_75:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_76:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_77:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(104) ); PPM_78:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(113) ); PPM_79:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(121) ); PPM_80:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(129) ); PPM_81:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(136) ); PPM_82:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(143) ); PPM_83:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(149) ); PPM_84:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(154) ); SUMMAND(155) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_85:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_86:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_87:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_88:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_89:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_90:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_91:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_92:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(105) ); PPM_93:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(114) ); PPM_94:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(122) ); PPM_95:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(130) ); PPM_96:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(137) ); PPM_97:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(144) ); PPM_98:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(150) ); PPM_99:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(156) ); PPM_100:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(161) ); PPM_101:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(165) ); SUMMAND(166) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(170) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_102:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_103:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_104:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_105:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_106:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_107:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(106) ); PPM_108:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(115) ); PPM_109:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(123) ); PPM_110:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(131) ); PPM_111:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(138) ); PPM_112:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(145) ); PPM_113:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(151) ); PPM_114:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(157) ); PPM_115:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(162) ); PPM_116:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(167) ); PPM_117:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(171) ); PPM_118:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(174) ); SUMMAND(175) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(178) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_119:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_120:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_121:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_122:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(107) ); PPM_123:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(116) ); PPM_124:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(124) ); PPM_125:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(132) ); PPM_126:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(139) ); PPM_127:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(146) ); PPM_128:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(152) ); PPM_129:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(158) ); PPM_130:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(163) ); PPM_131:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(168) ); PPM_132:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(172) ); PPM_133:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(176) ); PPM_134:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(179) ); PPM_135:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(181) ); SUMMAND(182) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(184) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_136:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_137:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(108) ); PPM_138:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(117) ); PPM_139:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(125) ); PPM_140:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(133) ); PPM_141:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(140) ); PPM_142:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(147) ); PPM_143:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(153) ); PPM_144:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(159) ); PPM_145:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(164) ); PPM_146:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(169) ); PPM_147:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(173) ); PPM_148:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(177) ); PPM_149:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(180) ); PPM_150:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(183) ); PPM_151:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(185) ); PPM_152:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(186) ); SUMMAND(187) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(188) ); -- Begin partial product 9 end BOOTHCODER; ------------------------------------------------------------ -- END: Architectures used with the Modified Booth recoding ------------------------------------------------------------ -- -- Wallace tree architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_18_18 is port ( SUMMAND: in std_logic_vector(0 to 188); CARRY: out std_logic_vector(0 to 33); SUM: out std_logic_vector(0 to 34) ); end WALLACE_18_18; ------------------------------------------------------------ -- END: Entities within the Wallace-tree ------------------------------------------------------------ architecture WALLACE of WALLACE_18_18 is -- Components used in the netlist -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 114); signal INT_SUM: std_logic_vector(0 to 158); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin NO stage INT_SUM(76) <= SUMMAND(108); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(77), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_CARRY(49), DATA_C => INT_CARRY(50), SAVE => INT_SUM(78), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(51); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(77), DATA_B => INT_SUM(78), DATA_C => INT_SUM(79), SAVE => INT_SUM(80), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin NO stage INT_SUM(81) <= INT_CARRY(52); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(82) <= INT_CARRY(53); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_SUM(82), SAVE => INT_SUM(83), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin NO stage INT_SUM(84) <= INT_CARRY(54); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_64:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(83), DATA_B => INT_SUM(84), DATA_C => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End FA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_65:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(109), DATA_B => SUMMAND(110), DATA_C => SUMMAND(111), SAVE => INT_SUM(85), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(112), DATA_B => SUMMAND(113), DATA_C => SUMMAND(114), SAVE => INT_SUM(86), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117), SAVE => INT_SUM(87), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58), SAVE => INT_SUM(88), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(59), DATA_C => INT_CARRY(60), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_CARRY(61), SAVE => INT_SUM(91), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(91), DATA_B => INT_CARRY(62), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End HA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_72:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), DATA_C => SUMMAND(120), SAVE => INT_SUM(92), CARRY => INT_CARRY(70) ); ---- End FA stage ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(121), DATA_B => SUMMAND(122), DATA_C => SUMMAND(123), SAVE => INT_SUM(93), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(94) <= SUMMAND(124); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(95) <= SUMMAND(125); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_SUM(94), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin NO stage INT_SUM(97) <= INT_SUM(95); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(63), SAVE => INT_SUM(98), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(64), DATA_B => INT_CARRY(65), DATA_C => INT_CARRY(66), SAVE => INT_SUM(99), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(67), SAVE => INT_SUM(100), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin NO stage INT_SUM(101) <= INT_CARRY(68); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(69), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_79:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(102), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(103), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => INT_CARRY(70), SAVE => INT_SUM(104), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin NO stage INT_SUM(105) <= INT_CARRY(71); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_82:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_SUM(104), SAVE => INT_SUM(106), CARRY => INT_CARRY(79) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(105), DATA_B => INT_CARRY(72), SAVE => INT_SUM(107), CARRY => INT_CARRY(80) ); ---- End HA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(73), SAVE => INT_SUM(108), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin NO stage INT_SUM(109) <= INT_CARRY(74); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(75), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(134), DATA_B => SUMMAND(135), DATA_C => SUMMAND(136), SAVE => INT_SUM(110), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(137), DATA_B => SUMMAND(138), DATA_C => SUMMAND(139), SAVE => INT_SUM(111), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(112) <= SUMMAND(140); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_SUM(112), SAVE => INT_SUM(113), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), DATA_C => INT_CARRY(78), SAVE => INT_SUM(114), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_CARRY(79), SAVE => INT_SUM(115), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin NO stage INT_SUM(116) <= INT_CARRY(80); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(81), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_91:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143), SAVE => INT_SUM(117), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin FA stage FA_92:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146), SAVE => INT_SUM(118), CARRY => INT_CARRY(88) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= SUMMAND(147); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_SUM(119), SAVE => INT_SUM(120), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83), SAVE => INT_SUM(121), CARRY => INT_CARRY(90) ); ---- End HA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(84), SAVE => INT_SUM(122), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= INT_CARRY(85); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(86), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), DATA_C => SUMMAND(150), SAVE => INT_SUM(124), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(151), DATA_B => SUMMAND(152), DATA_C => SUMMAND(153), SAVE => INT_SUM(125), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(87), SAVE => INT_SUM(126), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin NO stage INT_SUM(127) <= INT_CARRY(88); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_99:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(89), SAVE => INT_SUM(128), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin NO stage INT_SUM(129) <= INT_CARRY(90); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(91), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_101:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(154), DATA_B => SUMMAND(155), DATA_C => SUMMAND(156), SAVE => INT_SUM(130), CARRY => INT_CARRY(96) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(157), DATA_B => SUMMAND(158), DATA_C => SUMMAND(159), SAVE => INT_SUM(131), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), DATA_C => INT_CARRY(92), SAVE => INT_SUM(132), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin NO stage INT_SUM(133) <= INT_CARRY(93); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(94), SAVE => INT_SUM(134), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(134), DATA_B => INT_CARRY(95), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End HA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_105:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(160), DATA_B => SUMMAND(161), DATA_C => SUMMAND(162), SAVE => INT_SUM(135), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(163), DATA_B => SUMMAND(164), SAVE => INT_SUM(136), CARRY => INT_CARRY(101) ); ---- End HA stage ---- Begin FA stage FA_106:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_CARRY(96), SAVE => INT_SUM(137), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin NO stage INT_SUM(138) <= INT_CARRY(97); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_CARRY(98), SAVE => INT_SUM(139), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(139), DATA_B => INT_CARRY(99), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_108:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(140), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), SAVE => INT_SUM(141), CARRY => INT_CARRY(105) ); ---- End HA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(100), SAVE => INT_SUM(142), CARRY => INT_CARRY(106) ); ---- End FA stage ---- Begin NO stage INT_SUM(143) <= INT_CARRY(101); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(102), SAVE => INT_SUM(144), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(144), DATA_B => INT_CARRY(103), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End HA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_111:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172), SAVE => INT_SUM(145), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(173), DATA_B => INT_CARRY(104), DATA_C => INT_CARRY(105), SAVE => INT_SUM(146), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin FA stage FA_113:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(106), SAVE => INT_SUM(147), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(147), DATA_B => INT_CARRY(107), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_114:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(148), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin NO stage INT_SUM(149) <= SUMMAND(177); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(108), SAVE => INT_SUM(150), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin NO stage INT_SUM(151) <= INT_CARRY(109); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(110), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_117:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(178), DATA_B => SUMMAND(179), DATA_C => SUMMAND(180), SAVE => INT_SUM(152), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin NO stage INT_SUM(153) <= INT_SUM(152); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(154) <= INT_CARRY(111); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_CARRY(112), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_119:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(181), DATA_B => SUMMAND(182), DATA_C => SUMMAND(183), SAVE => INT_SUM(155), CARRY => INT_CARRY(114) ); ---- End FA stage ---- Begin NO stage INT_SUM(156) <= INT_CARRY(113); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(155), DATA_B => INT_SUM(156), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End HA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin NO stage INT_SUM(157) <= SUMMAND(184); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(158) <= SUMMAND(185); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_120:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(114), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin HA stage HA_26:HALF_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End HA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin NO stage SUM(34) <= SUMMAND(188); -- At Level 5 ---- End NO stage -- End WT-branch 35 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_18_18 is generic (mulpipe : integer := 0); port ( MULTIPLICAND: in std_logic_vector(0 to 17); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_ulogic; holdn: in std_ulogic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_18_18; architecture MULTIPLIER of MULTIPLIER_18_18 is signal PPBIT:std_logic_vector(0 to 188); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_CARRYR: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal INT_SUMR: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_18_18 port map ( OPA(0 to 17) => MULTIPLICAND(0 to 17), OPB(0 to 17) => MULTIPLIER(0 to 17), SUMMAND(0 to 188) => PPBIT(0 to 188) ); W:WALLACE_18_18 port map ( SUMMAND(0 to 188) => PPBIT(0 to 188), CARRY(0 to 33) => INT_CARRY(1 to 34), SUM(0 to 34) => INT_SUM(0 to 34) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(35) <= LOGIC_ZERO; INT_CARRY(36) <= LOGIC_ZERO; INT_CARRY(37) <= LOGIC_ZERO; INT_CARRY(38) <= LOGIC_ZERO; INT_CARRY(39) <= LOGIC_ZERO; INT_CARRY(40) <= LOGIC_ZERO; INT_CARRY(41) <= LOGIC_ZERO; INT_CARRY(42) <= LOGIC_ZERO; INT_CARRY(43) <= LOGIC_ZERO; INT_CARRY(44) <= LOGIC_ZERO; INT_CARRY(45) <= LOGIC_ZERO; INT_CARRY(46) <= LOGIC_ZERO; INT_CARRY(47) <= LOGIC_ZERO; INT_CARRY(48) <= LOGIC_ZERO; INT_CARRY(49) <= LOGIC_ZERO; INT_CARRY(50) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(35) <= LOGIC_ZERO; INT_SUM(36) <= LOGIC_ZERO; INT_SUM(37) <= LOGIC_ZERO; INT_SUM(38) <= LOGIC_ZERO; INT_SUM(39) <= LOGIC_ZERO; INT_SUM(40) <= LOGIC_ZERO; INT_SUM(41) <= LOGIC_ZERO; INT_SUM(42) <= LOGIC_ZERO; INT_SUM(43) <= LOGIC_ZERO; INT_SUM(44) <= LOGIC_ZERO; INT_SUM(45) <= LOGIC_ZERO; INT_SUM(46) <= LOGIC_ZERO; INT_SUM(47) <= LOGIC_ZERO; INT_SUM(48) <= LOGIC_ZERO; INT_SUM(49) <= LOGIC_ZERO; INT_SUM(50) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; INT_SUMR(35 to 63) <= INT_SUM(35 to 63); INT_CARRYR(35 to 63) <= INT_CARRY(35 to 63); INT_CARRYR(0) <= INT_CARRY(0); reg : if MULPIPE /= 0 generate process (PHI) begin if rising_edge(PHI ) then if (holdn = '1') then INT_SUMR(0 to 34) <= INT_SUM(0 to 34); INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34); end if; end if; end process; end generate; noreg : if MULPIPE = 0 generate INT_SUMR(0 to 34) <= INT_SUM(0 to 34); INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34); end generate; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUMR(0 to 63), OPB(0 to 63) => INT_CARRYR(0 to 63), CIN => LOGIC_ZERO, PHI => PHI , SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_10 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 9); SUMMAND: out std_logic_vector(0 to 184) ); end BOOTHCODER_34_10; architecture BOOTHCODER of BOOTHCODER_34_10 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 19); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(40) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(45) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(50) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(55) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(60) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(65) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(70) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(75) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(85) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(95) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(100) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(105) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(110) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(115) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(120) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(125) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(130) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(135) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(140) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(145) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(150) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(155) ); SUMMAND(156) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(41) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(46) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(51) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(56) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(61) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(66) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(71) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(76) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(86) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(96) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(101) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(106) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(111) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(116) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(121) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(126) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(131) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(136) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(141) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(146) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(151) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(157) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(161) ); SUMMAND(162) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(166) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(42) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(47) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(52) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(57) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(62) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(67) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(72) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(77) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(87) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(97) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(102) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(107) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(112) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(117) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(122) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(127) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(132) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(137) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(142) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(147) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(152) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(158) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(163) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(167) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(170) ); SUMMAND(171) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(174) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(43) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(48) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(53) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(58) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(63) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(68) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(73) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(78) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(88) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(98) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(103) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(108) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(113) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(118) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(123) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(128) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(133) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(138) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(143) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(148) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(153) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(159) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(164) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(168) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(172) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(175) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(177) ); SUMMAND(178) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(180) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(44) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(49) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(54) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(59) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(64) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(69) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(74) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(79) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(89) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(99) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(104) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(109) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(114) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(119) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(124) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(129) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(134) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(139) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(144) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(149) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(154) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(165) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(169) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(173) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(176) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(179) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(181) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(182) ); SUMMAND(183) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(184) ); -- Begin partial product 5 end BOOTHCODER; ------------------------------------------------------------ -- END: Architectures used with the Modified Booth recoding ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the Wallace-tree ------------------------------------------------------------ -- -- Wallace tree architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_10 is port ( SUMMAND: in std_logic_vector(0 to 184); CARRY: out std_logic_vector(0 to 41); SUM: out std_logic_vector(0 to 42) ); end WALLACE_34_10; architecture WALLACE of WALLACE_34_10 is signal INT_CARRY: std_logic_vector(0 to 95); signal INT_SUM: std_logic_vector(0 to 133); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End HA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_CARRY(9), SAVE => INT_SUM(18), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin NO stage INT_SUM(19) <= INT_CARRY(10); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(18), DATA_B => INT_SUM(19), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_16:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(40), DATA_B => SUMMAND(41), DATA_C => SUMMAND(42), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End FA stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(43), DATA_B => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End HA stage ---- Begin FA stage FA_17:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(20), DATA_B => INT_SUM(21), DATA_C => INT_CARRY(12), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin NO stage INT_SUM(23) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(22), DATA_B => INT_SUM(23), DATA_C => INT_CARRY(14), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End FA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_19:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(24), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End HA stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(24), DATA_B => INT_SUM(25), DATA_C => INT_CARRY(15), SAVE => INT_SUM(26), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin NO stage INT_SUM(27) <= INT_CARRY(16); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_21:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(26), DATA_B => INT_SUM(27), DATA_C => INT_CARRY(17), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End FA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(50), DATA_B => SUMMAND(51), DATA_C => SUMMAND(52), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(53), DATA_B => SUMMAND(54), SAVE => INT_SUM(29), CARRY => INT_CARRY(22) ); ---- End HA stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(28), DATA_B => INT_SUM(29), DATA_C => INT_CARRY(18), SAVE => INT_SUM(30), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin NO stage INT_SUM(31) <= INT_CARRY(19); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(30), DATA_B => INT_SUM(31), DATA_C => INT_CARRY(20), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_25:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(55), DATA_B => SUMMAND(56), DATA_C => SUMMAND(57), SAVE => INT_SUM(32), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(58), DATA_B => SUMMAND(59), SAVE => INT_SUM(33), CARRY => INT_CARRY(25) ); ---- End HA stage ---- Begin FA stage FA_26:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(32), DATA_B => INT_SUM(33), DATA_C => INT_CARRY(21), SAVE => INT_SUM(34), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(35) <= INT_CARRY(22); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_CARRY(23), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_28:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(60), DATA_B => SUMMAND(61), DATA_C => SUMMAND(62), SAVE => INT_SUM(36), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), SAVE => INT_SUM(37), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(36), DATA_B => INT_SUM(37), DATA_C => INT_CARRY(24), SAVE => INT_SUM(38), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(39) <= INT_CARRY(25); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(38), DATA_B => INT_SUM(39), DATA_C => INT_CARRY(26), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(65), DATA_B => SUMMAND(66), DATA_C => SUMMAND(67), SAVE => INT_SUM(40), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(68), DATA_B => SUMMAND(69), SAVE => INT_SUM(41), CARRY => INT_CARRY(31) ); ---- End HA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(40), DATA_B => INT_SUM(41), DATA_C => INT_CARRY(27), SAVE => INT_SUM(42), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin NO stage INT_SUM(43) <= INT_CARRY(28); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(42), DATA_B => INT_SUM(43), DATA_C => INT_CARRY(29), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_34:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(70), DATA_B => SUMMAND(71), DATA_C => SUMMAND(72), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(73), DATA_B => SUMMAND(74), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(30), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(31); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(32), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End FA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End HA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_CARRY(33), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End FA stage ---- Begin NO stage INT_SUM(51) <= INT_CARRY(34); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(50), DATA_B => INT_SUM(51), DATA_C => INT_CARRY(35), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End FA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_40:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(52), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), SAVE => INT_SUM(53), CARRY => INT_CARRY(40) ); ---- End HA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(52), DATA_B => INT_SUM(53), DATA_C => INT_CARRY(36), SAVE => INT_SUM(54), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(55) <= INT_CARRY(37); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(54), DATA_B => INT_SUM(55), DATA_C => INT_CARRY(38), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End FA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(85), DATA_B => SUMMAND(86), DATA_C => SUMMAND(87), SAVE => INT_SUM(56), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(88), DATA_B => SUMMAND(89), SAVE => INT_SUM(57), CARRY => INT_CARRY(43) ); ---- End HA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(56), DATA_B => INT_SUM(57), DATA_C => INT_CARRY(39), SAVE => INT_SUM(58), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(59) <= INT_CARRY(40); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(58), DATA_B => INT_SUM(59), DATA_C => INT_CARRY(41), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_46:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(60), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), SAVE => INT_SUM(61), CARRY => INT_CARRY(46) ); ---- End HA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(60), DATA_B => INT_SUM(61), DATA_C => INT_CARRY(42), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin NO stage INT_SUM(63) <= INT_CARRY(43); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(44), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_49:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(95), DATA_B => SUMMAND(96), DATA_C => SUMMAND(97), SAVE => INT_SUM(64), CARRY => INT_CARRY(48) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(98), DATA_B => SUMMAND(99), SAVE => INT_SUM(65), CARRY => INT_CARRY(49) ); ---- End HA stage ---- Begin FA stage FA_50:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_CARRY(45), SAVE => INT_SUM(66), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin NO stage INT_SUM(67) <= INT_CARRY(46); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(66), DATA_B => INT_SUM(67), DATA_C => INT_CARRY(47), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(100), DATA_B => SUMMAND(101), DATA_C => SUMMAND(102), SAVE => INT_SUM(68), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(103), DATA_B => SUMMAND(104), SAVE => INT_SUM(69), CARRY => INT_CARRY(52) ); ---- End HA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(68), DATA_B => INT_SUM(69), DATA_C => INT_CARRY(48), SAVE => INT_SUM(70), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin NO stage INT_SUM(71) <= INT_CARRY(49); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(70), DATA_B => INT_SUM(71), DATA_C => INT_CARRY(50), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_55:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(72), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), SAVE => INT_SUM(73), CARRY => INT_CARRY(55) ); ---- End HA stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(72), DATA_B => INT_SUM(73), DATA_C => INT_CARRY(51), SAVE => INT_SUM(74), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin NO stage INT_SUM(75) <= INT_CARRY(52); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_57:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(74), DATA_B => INT_SUM(75), DATA_C => INT_CARRY(53), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112), SAVE => INT_SUM(76), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), SAVE => INT_SUM(77), CARRY => INT_CARRY(58) ); ---- End HA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(54), SAVE => INT_SUM(78), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(55); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(56), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End FA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_61:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117), SAVE => INT_SUM(80), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), SAVE => INT_SUM(81), CARRY => INT_CARRY(61) ); ---- End HA stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_CARRY(57), SAVE => INT_SUM(82), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin NO stage INT_SUM(83) <= INT_CARRY(58); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(59), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End FA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_64:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(84), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), SAVE => INT_SUM(85), CARRY => INT_CARRY(64) ); ---- End HA stage ---- Begin FA stage FA_65:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(60), SAVE => INT_SUM(86), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin NO stage INT_SUM(87) <= INT_CARRY(61); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(62), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End FA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_67:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(125), DATA_B => SUMMAND(126), DATA_C => SUMMAND(127), SAVE => INT_SUM(88), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(128), DATA_B => SUMMAND(129), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End HA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(88), DATA_B => INT_SUM(89), DATA_C => INT_CARRY(63), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(91) <= INT_CARRY(64); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(90), DATA_B => INT_SUM(91), DATA_C => INT_CARRY(65), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End FA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_70:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(130), DATA_B => SUMMAND(131), DATA_C => SUMMAND(132), SAVE => INT_SUM(92), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(133), DATA_B => SUMMAND(134), SAVE => INT_SUM(93), CARRY => INT_CARRY(70) ); ---- End HA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66), SAVE => INT_SUM(94), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(67); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), SAVE => INT_SUM(97), CARRY => INT_CARRY(73) ); ---- End HA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(69), SAVE => INT_SUM(98), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin NO stage INT_SUM(99) <= INT_CARRY(70); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(71), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_76:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(140), DATA_B => SUMMAND(141), DATA_C => SUMMAND(142), SAVE => INT_SUM(100), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), SAVE => INT_SUM(101), CARRY => INT_CARRY(76) ); ---- End HA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(72), SAVE => INT_SUM(102), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin NO stage INT_SUM(103) <= INT_CARRY(73); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(74), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End FA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_79:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(145), DATA_B => SUMMAND(146), DATA_C => SUMMAND(147), SAVE => INT_SUM(104), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), SAVE => INT_SUM(105), CARRY => INT_CARRY(79) ); ---- End HA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(104), DATA_B => INT_SUM(105), DATA_C => INT_CARRY(75), SAVE => INT_SUM(106), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin NO stage INT_SUM(107) <= INT_CARRY(76); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(77), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_82:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152), SAVE => INT_SUM(108), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), SAVE => INT_SUM(109), CARRY => INT_CARRY(82) ); ---- End HA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(78), SAVE => INT_SUM(110), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(111) <= INT_CARRY(79); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(80), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End FA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(155), DATA_B => SUMMAND(156), DATA_C => SUMMAND(157), SAVE => INT_SUM(112), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(158), DATA_B => SUMMAND(159), DATA_C => SUMMAND(160), SAVE => INT_SUM(113), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_CARRY(81), SAVE => INT_SUM(114), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin NO stage INT_SUM(115) <= INT_CARRY(82); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(114), DATA_B => INT_SUM(115), DATA_C => INT_CARRY(83), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_89:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(161), DATA_B => SUMMAND(162), DATA_C => SUMMAND(163), SAVE => INT_SUM(116), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(164), DATA_B => SUMMAND(165), SAVE => INT_SUM(117), CARRY => INT_CARRY(88) ); ---- End HA stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(84), SAVE => INT_SUM(118), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= INT_CARRY(85); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_91:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(86), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End FA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(166), DATA_B => SUMMAND(167), DATA_C => SUMMAND(168), SAVE => INT_SUM(120), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin NO stage INT_SUM(121) <= SUMMAND(169); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(87), SAVE => INT_SUM(122), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= INT_CARRY(88); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(89), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_95:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172), SAVE => INT_SUM(124), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin NO stage INT_SUM(125) <= SUMMAND(173); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(90), SAVE => INT_SUM(126), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(126), DATA_B => INT_CARRY(91), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End HA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_97:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(127), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin NO stage INT_SUM(128) <= INT_SUM(127); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(129) <= INT_CARRY(92); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(93), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_99:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(130), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin NO stage INT_SUM(131) <= INT_CARRY(94); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End HA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin NO stage INT_SUM(132) <= SUMMAND(180); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(133) <= SUMMAND(181); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(95), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin HA stage HA_35:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End HA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin NO stage SUM(42) <= SUMMAND(184); -- At Level 3 ---- End NO stage -- End WT-branch 43 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_10 is port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 9); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_34_10; ------------------------------------------------------------ -- End: Multiplier Entitiy architecture MULTIPLIER of MULTIPLIER_34_10 is signal PPBIT:std_logic_vector(0 to 184); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_10 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 9) => MULTIPLIER(0 to 9), SUMMAND(0 to 184) => PPBIT(0 to 184) ); W:WALLACE_34_10 port map ( SUMMAND(0 to 184) => PPBIT(0 to 184), CARRY(0 to 41) => INT_CARRY(1 to 42), SUM(0 to 42) => INT_SUM(0 to 42) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(43) <= LOGIC_ZERO; INT_CARRY(44) <= LOGIC_ZERO; INT_CARRY(45) <= LOGIC_ZERO; INT_CARRY(46) <= LOGIC_ZERO; INT_CARRY(47) <= LOGIC_ZERO; INT_CARRY(48) <= LOGIC_ZERO; INT_CARRY(49) <= LOGIC_ZERO; INT_CARRY(50) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(43) <= LOGIC_ZERO; INT_SUM(44) <= LOGIC_ZERO; INT_SUM(45) <= LOGIC_ZERO; INT_SUM(46) <= LOGIC_ZERO; INT_SUM(47) <= LOGIC_ZERO; INT_SUM(48) <= LOGIC_ZERO; INT_SUM(49) <= LOGIC_ZERO; INT_SUM(50) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUM(0 to 63), OPB(0 to 63) => INT_CARRY(0 to 63), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_9 is port(X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(8 downto 0); P: out std_logic_vector(41 downto 0)); end MUL_33_9; library ieee; use ieee.std_logic_1164.all; architecture A of MUL_33_9 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 9); signal Q: std_logic_vector(0 to 63); signal CLK: std_logic; begin U1: MULTIPLIER_34_10 port map(A,B,CLK,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(8); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); end A; ------------------------------------------------------------ -- START: Entities within the Wallace-tree ------------------------------------------------------------ -- -- Modified Booth algorithm architecture -- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_18 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 17); SUMMAND: out std_logic_vector(0 to 332) ); end BOOTHCODER_34_18; architecture BOOTHCODER of BOOTHCODER_34_18 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 35); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(108) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(117) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(126) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(135) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(144) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(153) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(162) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(171) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(180) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(189) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(198) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(207) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(216) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(225) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(234) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(243) ); SUMMAND(244) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(100) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(109) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(118) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(127) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(136) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(145) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(154) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(163) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(172) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(181) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(190) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(199) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(208) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(217) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(226) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(235) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(245) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(253) ); SUMMAND(254) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(262) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(101) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(110) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(119) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(128) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(137) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(146) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(155) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(164) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(173) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(182) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(191) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(200) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(209) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(218) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(227) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(236) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(246) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(255) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(263) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(270) ); SUMMAND(271) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(278) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(102) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(111) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(120) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(129) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(138) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(147) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(156) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(165) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(174) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(183) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(192) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(201) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(210) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(219) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(228) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(237) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(247) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(256) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(264) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(272) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(279) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(285) ); SUMMAND(286) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(292) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(103) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(112) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(121) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(130) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(139) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(148) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(157) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(166) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(175) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(184) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(193) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(202) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(211) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(220) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(229) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(238) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(248) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(257) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(265) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(273) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(280) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(287) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(293) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(298) ); SUMMAND(299) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(304) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_165:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_166:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_167:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_168:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_169:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_170:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_171:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_172:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(104) ); PPM_173:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(113) ); PPM_174:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(122) ); PPM_175:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(131) ); PPM_176:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(140) ); PPM_177:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(149) ); PPM_178:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(158) ); PPM_179:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(167) ); PPM_180:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(176) ); PPM_181:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(185) ); PPM_182:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(194) ); PPM_183:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(203) ); PPM_184:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(212) ); PPM_185:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(221) ); PPM_186:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(230) ); PPM_187:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(239) ); PPM_188:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(249) ); PPM_189:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(258) ); PPM_190:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(266) ); PPM_191:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(274) ); PPM_192:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(281) ); PPM_193:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(288) ); PPM_194:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(294) ); PPM_195:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(300) ); PPM_196:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(305) ); PPM_197:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(309) ); SUMMAND(310) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(314) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_198:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_199:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_200:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_201:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_202:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_203:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(105) ); PPM_204:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(114) ); PPM_205:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(123) ); PPM_206:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(132) ); PPM_207:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(141) ); PPM_208:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(150) ); PPM_209:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(159) ); PPM_210:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(168) ); PPM_211:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(177) ); PPM_212:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(186) ); PPM_213:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(195) ); PPM_214:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(204) ); PPM_215:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(213) ); PPM_216:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(222) ); PPM_217:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(231) ); PPM_218:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(240) ); PPM_219:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(250) ); PPM_220:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(259) ); PPM_221:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(267) ); PPM_222:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(275) ); PPM_223:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(282) ); PPM_224:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(289) ); PPM_225:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(295) ); PPM_226:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(301) ); PPM_227:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(306) ); PPM_228:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(311) ); PPM_229:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(315) ); PPM_230:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(318) ); SUMMAND(319) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(322) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_231:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_232:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_233:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_234:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(106) ); PPM_235:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(115) ); PPM_236:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(124) ); PPM_237:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(133) ); PPM_238:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(142) ); PPM_239:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(151) ); PPM_240:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(160) ); PPM_241:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(169) ); PPM_242:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(178) ); PPM_243:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(187) ); PPM_244:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(196) ); PPM_245:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(205) ); PPM_246:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(214) ); PPM_247:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(223) ); PPM_248:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(232) ); PPM_249:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(241) ); PPM_250:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(251) ); PPM_251:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(260) ); PPM_252:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(268) ); PPM_253:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(276) ); PPM_254:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(283) ); PPM_255:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(290) ); PPM_256:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(296) ); PPM_257:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(302) ); PPM_258:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(307) ); PPM_259:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(312) ); PPM_260:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(316) ); PPM_261:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(320) ); PPM_262:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(323) ); PPM_263:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(325) ); SUMMAND(326) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(328) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_264:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_265:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(107) ); PPM_266:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(116) ); PPM_267:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(125) ); PPM_268:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(134) ); PPM_269:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(143) ); PPM_270:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(152) ); PPM_271:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(161) ); PPM_272:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(170) ); PPM_273:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(179) ); PPM_274:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(188) ); PPM_275:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(197) ); PPM_276:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(206) ); PPM_277:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(215) ); PPM_278:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(224) ); PPM_279:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(233) ); PPM_280:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(242) ); PPM_281:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(252) ); PPM_282:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(261) ); PPM_283:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(269) ); PPM_284:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(277) ); PPM_285:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(284) ); PPM_286:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(291) ); PPM_287:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(297) ); PPM_288:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(303) ); PPM_289:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(308) ); PPM_290:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(313) ); PPM_291:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(317) ); PPM_292:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(321) ); PPM_293:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(324) ); PPM_294:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(327) ); PPM_295:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(329) ); PPM_296:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(330) ); SUMMAND(331) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(332) ); -- Begin partial product 9 end BOOTHCODER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_18 is port ( SUMMAND: in std_logic_vector(0 to 332); CARRY: out std_logic_vector(0 to 49); SUM: out std_logic_vector(0 to 50) ); end WALLACE_34_18; architecture WALLACE of WALLACE_34_18 is -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 226); signal INT_SUM: std_logic_vector(0 to 286); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(76), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(49), DATA_B => INT_CARRY(50), DATA_C => INT_CARRY(51), SAVE => INT_SUM(77), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(52), SAVE => INT_SUM(78), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin NO stage INT_SUM(79) <= INT_CARRY(53); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(54), SAVE => INT_SUM(80), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(80), DATA_B => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End HA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_64:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), DATA_C => SUMMAND(110), SAVE => INT_SUM(81), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin FA stage FA_65:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(111), DATA_B => SUMMAND(112), DATA_C => SUMMAND(113), SAVE => INT_SUM(82), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(114), DATA_B => SUMMAND(115), DATA_C => SUMMAND(116), SAVE => INT_SUM(83), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(81), DATA_B => INT_SUM(82), DATA_C => INT_SUM(83), SAVE => INT_SUM(84), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58), SAVE => INT_SUM(85), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(59), SAVE => INT_SUM(86), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(87) <= INT_CARRY(60); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(61), SAVE => INT_SUM(88), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(62), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End HA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_71:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(117), DATA_B => SUMMAND(118), DATA_C => SUMMAND(119), SAVE => INT_SUM(89), CARRY => INT_CARRY(70) ); ---- End FA stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(90), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125), SAVE => INT_SUM(91), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91), SAVE => INT_SUM(92), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(63), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65), SAVE => INT_SUM(93), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66), SAVE => INT_SUM(94), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(67); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68), SAVE => INT_SUM(96), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(96), DATA_B => INT_CARRY(69), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End HA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_78:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(97), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin FA stage FA_79:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(98), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134), SAVE => INT_SUM(99), CARRY => INT_CARRY(79) ); ---- End FA stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(97), DATA_B => INT_SUM(98), DATA_C => INT_SUM(99), SAVE => INT_SUM(100), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin FA stage FA_82:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(70), DATA_B => INT_CARRY(71), DATA_C => INT_CARRY(72), SAVE => INT_SUM(101), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(73), SAVE => INT_SUM(102), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin NO stage INT_SUM(103) <= INT_CARRY(74); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(75), SAVE => INT_SUM(104), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(104), DATA_B => INT_CARRY(76), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End HA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_85:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(105), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140), SAVE => INT_SUM(106), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143), SAVE => INT_SUM(107), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_SUM(107), SAVE => INT_SUM(108), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(77), DATA_B => INT_CARRY(78), DATA_C => INT_CARRY(79), SAVE => INT_SUM(109), CARRY => INT_CARRY(88) ); ---- End FA stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(80), SAVE => INT_SUM(110), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(111) <= INT_CARRY(81); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_91:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(82), SAVE => INT_SUM(112), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(112), DATA_B => INT_CARRY(83), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End HA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146), SAVE => INT_SUM(113), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(147), DATA_B => SUMMAND(148), DATA_C => SUMMAND(149), SAVE => INT_SUM(114), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152), SAVE => INT_SUM(115), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_SUM(115), SAVE => INT_SUM(116), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86), SAVE => INT_SUM(117), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(87), SAVE => INT_SUM(118), CARRY => INT_CARRY(96) ); ---- End FA stage ---- Begin NO stage INT_SUM(119) <= INT_CARRY(88); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(89), SAVE => INT_SUM(120), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(120), DATA_B => INT_CARRY(90), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End HA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_99:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), DATA_C => SUMMAND(155), SAVE => INT_SUM(121), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158), SAVE => INT_SUM(122), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin FA stage FA_101:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161), SAVE => INT_SUM(123), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(121), DATA_B => INT_SUM(122), DATA_C => INT_SUM(123), SAVE => INT_SUM(124), CARRY => INT_CARRY(101) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(91), DATA_B => INT_CARRY(92), DATA_C => INT_CARRY(93), SAVE => INT_SUM(125), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(94), SAVE => INT_SUM(126), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin NO stage INT_SUM(127) <= INT_CARRY(95); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_105:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(96), SAVE => INT_SUM(128), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(128), DATA_B => INT_CARRY(97), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End HA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_106:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164), SAVE => INT_SUM(129), CARRY => INT_CARRY(105) ); ---- End FA stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(130), CARRY => INT_CARRY(106) ); ---- End FA stage ---- Begin FA stage FA_108:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170), SAVE => INT_SUM(131), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_SUM(131), SAVE => INT_SUM(132), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(98), DATA_B => INT_CARRY(99), DATA_C => INT_CARRY(100), SAVE => INT_SUM(133), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin FA stage FA_111:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(101), SAVE => INT_SUM(134), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin NO stage INT_SUM(135) <= INT_CARRY(102); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(134), DATA_B => INT_SUM(135), DATA_C => INT_CARRY(103), SAVE => INT_SUM(136), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(136), DATA_B => INT_CARRY(104), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End HA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_113:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173), SAVE => INT_SUM(137), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin FA stage FA_114:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(138), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(139), CARRY => INT_CARRY(114) ); ---- End FA stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_SUM(139), SAVE => INT_SUM(140), CARRY => INT_CARRY(115) ); ---- End FA stage ---- Begin FA stage FA_117:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(105), DATA_B => INT_CARRY(106), DATA_C => INT_CARRY(107), SAVE => INT_SUM(141), CARRY => INT_CARRY(116) ); ---- End FA stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(108), SAVE => INT_SUM(142), CARRY => INT_CARRY(117) ); ---- End FA stage ---- Begin NO stage INT_SUM(143) <= INT_CARRY(109); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_119:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(110), SAVE => INT_SUM(144), CARRY => INT_CARRY(118) ); ---- End FA stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(144), DATA_B => INT_CARRY(111), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_120:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), DATA_C => SUMMAND(182), SAVE => INT_SUM(145), CARRY => INT_CARRY(119) ); ---- End FA stage ---- Begin FA stage FA_121:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(183), DATA_B => SUMMAND(184), DATA_C => SUMMAND(185), SAVE => INT_SUM(146), CARRY => INT_CARRY(120) ); ---- End FA stage ---- Begin FA stage FA_122:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), DATA_C => SUMMAND(188), SAVE => INT_SUM(147), CARRY => INT_CARRY(121) ); ---- End FA stage ---- Begin FA stage FA_123:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_SUM(147), SAVE => INT_SUM(148), CARRY => INT_CARRY(122) ); ---- End FA stage ---- Begin FA stage FA_124:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(112), DATA_B => INT_CARRY(113), DATA_C => INT_CARRY(114), SAVE => INT_SUM(149), CARRY => INT_CARRY(123) ); ---- End FA stage ---- Begin FA stage FA_125:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(115), SAVE => INT_SUM(150), CARRY => INT_CARRY(124) ); ---- End FA stage ---- Begin NO stage INT_SUM(151) <= INT_CARRY(116); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_126:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(117), SAVE => INT_SUM(152), CARRY => INT_CARRY(125) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(152), DATA_B => INT_CARRY(118), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End HA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_127:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(189), DATA_B => SUMMAND(190), DATA_C => SUMMAND(191), SAVE => INT_SUM(153), CARRY => INT_CARRY(126) ); ---- End FA stage ---- Begin FA stage FA_128:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(192), DATA_B => SUMMAND(193), DATA_C => SUMMAND(194), SAVE => INT_SUM(154), CARRY => INT_CARRY(127) ); ---- End FA stage ---- Begin FA stage FA_129:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197), SAVE => INT_SUM(155), CARRY => INT_CARRY(128) ); ---- End FA stage ---- Begin FA stage FA_130:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_SUM(155), SAVE => INT_SUM(156), CARRY => INT_CARRY(129) ); ---- End FA stage ---- Begin FA stage FA_131:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(119), DATA_B => INT_CARRY(120), DATA_C => INT_CARRY(121), SAVE => INT_SUM(157), CARRY => INT_CARRY(130) ); ---- End FA stage ---- Begin FA stage FA_132:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(156), DATA_B => INT_SUM(157), DATA_C => INT_CARRY(122), SAVE => INT_SUM(158), CARRY => INT_CARRY(131) ); ---- End FA stage ---- Begin NO stage INT_SUM(159) <= INT_CARRY(123); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_133:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(158), DATA_B => INT_SUM(159), DATA_C => INT_CARRY(124), SAVE => INT_SUM(160), CARRY => INT_CARRY(132) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(160), DATA_B => INT_CARRY(125), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_134:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200), SAVE => INT_SUM(161), CARRY => INT_CARRY(133) ); ---- End FA stage ---- Begin FA stage FA_135:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203), SAVE => INT_SUM(162), CARRY => INT_CARRY(134) ); ---- End FA stage ---- Begin FA stage FA_136:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206), SAVE => INT_SUM(163), CARRY => INT_CARRY(135) ); ---- End FA stage ---- Begin FA stage FA_137:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(161), DATA_B => INT_SUM(162), DATA_C => INT_SUM(163), SAVE => INT_SUM(164), CARRY => INT_CARRY(136) ); ---- End FA stage ---- Begin FA stage FA_138:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(126), DATA_B => INT_CARRY(127), DATA_C => INT_CARRY(128), SAVE => INT_SUM(165), CARRY => INT_CARRY(137) ); ---- End FA stage ---- Begin FA stage FA_139:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(164), DATA_B => INT_SUM(165), DATA_C => INT_CARRY(129), SAVE => INT_SUM(166), CARRY => INT_CARRY(138) ); ---- End FA stage ---- Begin NO stage INT_SUM(167) <= INT_CARRY(130); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_140:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(131), SAVE => INT_SUM(168), CARRY => INT_CARRY(139) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(168), DATA_B => INT_CARRY(132), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End HA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_141:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209), SAVE => INT_SUM(169), CARRY => INT_CARRY(140) ); ---- End FA stage ---- Begin FA stage FA_142:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212), SAVE => INT_SUM(170), CARRY => INT_CARRY(141) ); ---- End FA stage ---- Begin FA stage FA_143:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215), SAVE => INT_SUM(171), CARRY => INT_CARRY(142) ); ---- End FA stage ---- Begin FA stage FA_144:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(169), DATA_B => INT_SUM(170), DATA_C => INT_SUM(171), SAVE => INT_SUM(172), CARRY => INT_CARRY(143) ); ---- End FA stage ---- Begin FA stage FA_145:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135), SAVE => INT_SUM(173), CARRY => INT_CARRY(144) ); ---- End FA stage ---- Begin FA stage FA_146:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(172), DATA_B => INT_SUM(173), DATA_C => INT_CARRY(136), SAVE => INT_SUM(174), CARRY => INT_CARRY(145) ); ---- End FA stage ---- Begin NO stage INT_SUM(175) <= INT_CARRY(137); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_147:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(174), DATA_B => INT_SUM(175), DATA_C => INT_CARRY(138), SAVE => INT_SUM(176), CARRY => INT_CARRY(146) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(176), DATA_B => INT_CARRY(139), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End HA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_148:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218), SAVE => INT_SUM(177), CARRY => INT_CARRY(147) ); ---- End FA stage ---- Begin FA stage FA_149:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221), SAVE => INT_SUM(178), CARRY => INT_CARRY(148) ); ---- End FA stage ---- Begin FA stage FA_150:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), DATA_C => SUMMAND(224), SAVE => INT_SUM(179), CARRY => INT_CARRY(149) ); ---- End FA stage ---- Begin FA stage FA_151:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(177), DATA_B => INT_SUM(178), DATA_C => INT_SUM(179), SAVE => INT_SUM(180), CARRY => INT_CARRY(150) ); ---- End FA stage ---- Begin FA stage FA_152:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(140), DATA_B => INT_CARRY(141), DATA_C => INT_CARRY(142), SAVE => INT_SUM(181), CARRY => INT_CARRY(151) ); ---- End FA stage ---- Begin FA stage FA_153:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), DATA_C => INT_CARRY(143), SAVE => INT_SUM(182), CARRY => INT_CARRY(152) ); ---- End FA stage ---- Begin NO stage INT_SUM(183) <= INT_CARRY(144); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_154:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_CARRY(145), SAVE => INT_SUM(184), CARRY => INT_CARRY(153) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(184), DATA_B => INT_CARRY(146), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End HA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_155:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(225), DATA_B => SUMMAND(226), DATA_C => SUMMAND(227), SAVE => INT_SUM(185), CARRY => INT_CARRY(154) ); ---- End FA stage ---- Begin FA stage FA_156:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(228), DATA_B => SUMMAND(229), DATA_C => SUMMAND(230), SAVE => INT_SUM(186), CARRY => INT_CARRY(155) ); ---- End FA stage ---- Begin FA stage FA_157:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(231), DATA_B => SUMMAND(232), DATA_C => SUMMAND(233), SAVE => INT_SUM(187), CARRY => INT_CARRY(156) ); ---- End FA stage ---- Begin FA stage FA_158:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_SUM(187), SAVE => INT_SUM(188), CARRY => INT_CARRY(157) ); ---- End FA stage ---- Begin FA stage FA_159:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(147), DATA_B => INT_CARRY(148), DATA_C => INT_CARRY(149), SAVE => INT_SUM(189), CARRY => INT_CARRY(158) ); ---- End FA stage ---- Begin FA stage FA_160:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(188), DATA_B => INT_SUM(189), DATA_C => INT_CARRY(150), SAVE => INT_SUM(190), CARRY => INT_CARRY(159) ); ---- End FA stage ---- Begin NO stage INT_SUM(191) <= INT_CARRY(151); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_161:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(190), DATA_B => INT_SUM(191), DATA_C => INT_CARRY(152), SAVE => INT_SUM(192), CARRY => INT_CARRY(160) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(192), DATA_B => INT_CARRY(153), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End HA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_162:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(234), DATA_B => SUMMAND(235), DATA_C => SUMMAND(236), SAVE => INT_SUM(193), CARRY => INT_CARRY(161) ); ---- End FA stage ---- Begin FA stage FA_163:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(237), DATA_B => SUMMAND(238), DATA_C => SUMMAND(239), SAVE => INT_SUM(194), CARRY => INT_CARRY(162) ); ---- End FA stage ---- Begin FA stage FA_164:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242), SAVE => INT_SUM(195), CARRY => INT_CARRY(163) ); ---- End FA stage ---- Begin FA stage FA_165:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(193), DATA_B => INT_SUM(194), DATA_C => INT_SUM(195), SAVE => INT_SUM(196), CARRY => INT_CARRY(164) ); ---- End FA stage ---- Begin FA stage FA_166:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(154), DATA_B => INT_CARRY(155), DATA_C => INT_CARRY(156), SAVE => INT_SUM(197), CARRY => INT_CARRY(165) ); ---- End FA stage ---- Begin FA stage FA_167:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(196), DATA_B => INT_SUM(197), DATA_C => INT_CARRY(157), SAVE => INT_SUM(198), CARRY => INT_CARRY(166) ); ---- End FA stage ---- Begin NO stage INT_SUM(199) <= INT_CARRY(158); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_168:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(198), DATA_B => INT_SUM(199), DATA_C => INT_CARRY(159), SAVE => INT_SUM(200), CARRY => INT_CARRY(167) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(200), DATA_B => INT_CARRY(160), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End HA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_169:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245), SAVE => INT_SUM(201), CARRY => INT_CARRY(168) ); ---- End FA stage ---- Begin FA stage FA_170:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248), SAVE => INT_SUM(202), CARRY => INT_CARRY(169) ); ---- End FA stage ---- Begin FA stage FA_171:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251), SAVE => INT_SUM(203), CARRY => INT_CARRY(170) ); ---- End FA stage ---- Begin NO stage INT_SUM(204) <= SUMMAND(252); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_172:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(201), DATA_B => INT_SUM(202), DATA_C => INT_SUM(203), SAVE => INT_SUM(205), CARRY => INT_CARRY(171) ); ---- End FA stage ---- Begin FA stage FA_173:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(204), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162), SAVE => INT_SUM(206), CARRY => INT_CARRY(172) ); ---- End FA stage ---- Begin NO stage INT_SUM(207) <= INT_CARRY(163); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_174:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207), SAVE => INT_SUM(208), CARRY => INT_CARRY(173) ); ---- End FA stage ---- Begin NO stage INT_SUM(209) <= INT_CARRY(164); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(210) <= INT_CARRY(165); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_175:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_SUM(210), SAVE => INT_SUM(211), CARRY => INT_CARRY(174) ); ---- End FA stage ---- Begin NO stage INT_SUM(212) <= INT_CARRY(166); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_176:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(211), DATA_B => INT_SUM(212), DATA_C => INT_CARRY(167), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_177:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(253), DATA_B => SUMMAND(254), DATA_C => SUMMAND(255), SAVE => INT_SUM(213), CARRY => INT_CARRY(175) ); ---- End FA stage ---- Begin FA stage FA_178:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(256), DATA_B => SUMMAND(257), DATA_C => SUMMAND(258), SAVE => INT_SUM(214), CARRY => INT_CARRY(176) ); ---- End FA stage ---- Begin FA stage FA_179:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(259), DATA_B => SUMMAND(260), DATA_C => SUMMAND(261), SAVE => INT_SUM(215), CARRY => INT_CARRY(177) ); ---- End FA stage ---- Begin FA stage FA_180:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(168), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170), SAVE => INT_SUM(216), CARRY => INT_CARRY(178) ); ---- End FA stage ---- Begin FA stage FA_181:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(213), DATA_B => INT_SUM(214), DATA_C => INT_SUM(215), SAVE => INT_SUM(217), CARRY => INT_CARRY(179) ); ---- End FA stage ---- Begin FA stage FA_182:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(216), DATA_B => INT_CARRY(171), DATA_C => INT_CARRY(172), SAVE => INT_SUM(218), CARRY => INT_CARRY(180) ); ---- End FA stage ---- Begin FA stage FA_183:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_CARRY(173), SAVE => INT_SUM(219), CARRY => INT_CARRY(181) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(219), DATA_B => INT_CARRY(174), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End HA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_184:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(262), DATA_B => SUMMAND(263), DATA_C => SUMMAND(264), SAVE => INT_SUM(220), CARRY => INT_CARRY(182) ); ---- End FA stage ---- Begin FA stage FA_185:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(265), DATA_B => SUMMAND(266), DATA_C => SUMMAND(267), SAVE => INT_SUM(221), CARRY => INT_CARRY(183) ); ---- End FA stage ---- Begin NO stage INT_SUM(222) <= SUMMAND(268); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(223) <= SUMMAND(269); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_186:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_SUM(222), SAVE => INT_SUM(224), CARRY => INT_CARRY(184) ); ---- End FA stage ---- Begin NO stage INT_SUM(225) <= INT_SUM(223); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_187:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(224), DATA_B => INT_SUM(225), DATA_C => INT_CARRY(175), SAVE => INT_SUM(226), CARRY => INT_CARRY(185) ); ---- End FA stage ---- Begin FA stage FA_188:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(176), DATA_B => INT_CARRY(177), DATA_C => INT_CARRY(178), SAVE => INT_SUM(227), CARRY => INT_CARRY(186) ); ---- End FA stage ---- Begin FA stage FA_189:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_CARRY(179), SAVE => INT_SUM(228), CARRY => INT_CARRY(187) ); ---- End FA stage ---- Begin NO stage INT_SUM(229) <= INT_CARRY(180); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_190:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(228), DATA_B => INT_SUM(229), DATA_C => INT_CARRY(181), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_191:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(270), DATA_B => SUMMAND(271), DATA_C => SUMMAND(272), SAVE => INT_SUM(230), CARRY => INT_CARRY(188) ); ---- End FA stage ---- Begin FA stage FA_192:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(273), DATA_B => SUMMAND(274), DATA_C => SUMMAND(275), SAVE => INT_SUM(231), CARRY => INT_CARRY(189) ); ---- End FA stage ---- Begin FA stage FA_193:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(276), DATA_B => SUMMAND(277), DATA_C => INT_CARRY(182), SAVE => INT_SUM(232), CARRY => INT_CARRY(190) ); ---- End FA stage ---- Begin NO stage INT_SUM(233) <= INT_CARRY(183); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_194:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(230), DATA_B => INT_SUM(231), DATA_C => INT_SUM(232), SAVE => INT_SUM(234), CARRY => INT_CARRY(191) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(233), DATA_B => INT_CARRY(184), SAVE => INT_SUM(235), CARRY => INT_CARRY(192) ); ---- End HA stage ---- Begin FA stage FA_195:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(234), DATA_B => INT_SUM(235), DATA_C => INT_CARRY(185), SAVE => INT_SUM(236), CARRY => INT_CARRY(193) ); ---- End FA stage ---- Begin NO stage INT_SUM(237) <= INT_CARRY(186); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_196:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_CARRY(187), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End FA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_197:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280), SAVE => INT_SUM(238), CARRY => INT_CARRY(194) ); ---- End FA stage ---- Begin FA stage FA_198:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283), SAVE => INT_SUM(239), CARRY => INT_CARRY(195) ); ---- End FA stage ---- Begin NO stage INT_SUM(240) <= SUMMAND(284); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_199:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(238), DATA_B => INT_SUM(239), DATA_C => INT_SUM(240), SAVE => INT_SUM(241), CARRY => INT_CARRY(196) ); ---- End FA stage ---- Begin FA stage FA_200:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190), SAVE => INT_SUM(242), CARRY => INT_CARRY(197) ); ---- End FA stage ---- Begin FA stage FA_201:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(241), DATA_B => INT_SUM(242), DATA_C => INT_CARRY(191), SAVE => INT_SUM(243), CARRY => INT_CARRY(198) ); ---- End FA stage ---- Begin NO stage INT_SUM(244) <= INT_CARRY(192); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_202:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(243), DATA_B => INT_SUM(244), DATA_C => INT_CARRY(193), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_203:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(285), DATA_B => SUMMAND(286), DATA_C => SUMMAND(287), SAVE => INT_SUM(245), CARRY => INT_CARRY(199) ); ---- End FA stage ---- Begin FA stage FA_204:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290), SAVE => INT_SUM(246), CARRY => INT_CARRY(200) ); ---- End FA stage ---- Begin NO stage INT_SUM(247) <= SUMMAND(291); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_205:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(245), DATA_B => INT_SUM(246), DATA_C => INT_SUM(247), SAVE => INT_SUM(248), CARRY => INT_CARRY(201) ); ---- End FA stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(194), DATA_B => INT_CARRY(195), SAVE => INT_SUM(249), CARRY => INT_CARRY(202) ); ---- End HA stage ---- Begin FA stage FA_206:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(248), DATA_B => INT_SUM(249), DATA_C => INT_CARRY(196), SAVE => INT_SUM(250), CARRY => INT_CARRY(203) ); ---- End FA stage ---- Begin NO stage INT_SUM(251) <= INT_CARRY(197); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_207:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(250), DATA_B => INT_SUM(251), DATA_C => INT_CARRY(198), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End FA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin FA stage FA_208:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(292), DATA_B => SUMMAND(293), DATA_C => SUMMAND(294), SAVE => INT_SUM(252), CARRY => INT_CARRY(204) ); ---- End FA stage ---- Begin FA stage FA_209:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(295), DATA_B => SUMMAND(296), DATA_C => SUMMAND(297), SAVE => INT_SUM(253), CARRY => INT_CARRY(205) ); ---- End FA stage ---- Begin FA stage FA_210:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(252), DATA_B => INT_SUM(253), DATA_C => INT_CARRY(199), SAVE => INT_SUM(254), CARRY => INT_CARRY(206) ); ---- End FA stage ---- Begin NO stage INT_SUM(255) <= INT_CARRY(200); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_211:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_CARRY(201), SAVE => INT_SUM(256), CARRY => INT_CARRY(207) ); ---- End FA stage ---- Begin NO stage INT_SUM(257) <= INT_CARRY(202); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_212:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(256), DATA_B => INT_SUM(257), DATA_C => INT_CARRY(203), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin FA stage FA_213:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(298), DATA_B => SUMMAND(299), DATA_C => SUMMAND(300), SAVE => INT_SUM(258), CARRY => INT_CARRY(208) ); ---- End FA stage ---- Begin FA stage FA_214:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(301), DATA_B => SUMMAND(302), DATA_C => SUMMAND(303), SAVE => INT_SUM(259), CARRY => INT_CARRY(209) ); ---- End FA stage ---- Begin FA stage FA_215:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(258), DATA_B => INT_SUM(259), DATA_C => INT_CARRY(204), SAVE => INT_SUM(260), CARRY => INT_CARRY(210) ); ---- End FA stage ---- Begin NO stage INT_SUM(261) <= INT_CARRY(205); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_216:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(206), SAVE => INT_SUM(262), CARRY => INT_CARRY(211) ); ---- End FA stage ---- Begin HA stage HA_35:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(262), DATA_B => INT_CARRY(207), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End HA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin FA stage FA_217:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(304), DATA_B => SUMMAND(305), DATA_C => SUMMAND(306), SAVE => INT_SUM(263), CARRY => INT_CARRY(212) ); ---- End FA stage ---- Begin HA stage HA_36:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(307), DATA_B => SUMMAND(308), SAVE => INT_SUM(264), CARRY => INT_CARRY(213) ); ---- End HA stage ---- Begin FA stage FA_218:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(263), DATA_B => INT_SUM(264), DATA_C => INT_CARRY(208), SAVE => INT_SUM(265), CARRY => INT_CARRY(214) ); ---- End FA stage ---- Begin NO stage INT_SUM(266) <= INT_CARRY(209); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_219:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(210), SAVE => INT_SUM(267), CARRY => INT_CARRY(215) ); ---- End FA stage ---- Begin HA stage HA_37:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(267), DATA_B => INT_CARRY(211), SAVE => SUM(42), CARRY => CARRY(42) ); ---- End HA stage -- End WT-branch 43 -- Begin WT-branch 44 ---- Begin FA stage FA_220:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311), SAVE => INT_SUM(268), CARRY => INT_CARRY(216) ); ---- End FA stage ---- Begin HA stage HA_38:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), SAVE => INT_SUM(269), CARRY => INT_CARRY(217) ); ---- End HA stage ---- Begin FA stage FA_221:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(268), DATA_B => INT_SUM(269), DATA_C => INT_CARRY(212), SAVE => INT_SUM(270), CARRY => INT_CARRY(218) ); ---- End FA stage ---- Begin NO stage INT_SUM(271) <= INT_CARRY(213); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_222:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(270), DATA_B => INT_SUM(271), DATA_C => INT_CARRY(214), SAVE => INT_SUM(272), CARRY => INT_CARRY(219) ); ---- End FA stage ---- Begin HA stage HA_39:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(272), DATA_B => INT_CARRY(215), SAVE => SUM(43), CARRY => CARRY(43) ); ---- End HA stage -- End WT-branch 44 -- Begin WT-branch 45 ---- Begin FA stage FA_223:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(314), DATA_B => SUMMAND(315), DATA_C => SUMMAND(316), SAVE => INT_SUM(273), CARRY => INT_CARRY(220) ); ---- End FA stage ---- Begin FA stage FA_224:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(317), DATA_B => INT_CARRY(216), DATA_C => INT_CARRY(217), SAVE => INT_SUM(274), CARRY => INT_CARRY(221) ); ---- End FA stage ---- Begin FA stage FA_225:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(273), DATA_B => INT_SUM(274), DATA_C => INT_CARRY(218), SAVE => INT_SUM(275), CARRY => INT_CARRY(222) ); ---- End FA stage ---- Begin HA stage HA_40:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(275), DATA_B => INT_CARRY(219), SAVE => SUM(44), CARRY => CARRY(44) ); ---- End HA stage -- End WT-branch 45 -- Begin WT-branch 46 ---- Begin FA stage FA_226:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320), SAVE => INT_SUM(276), CARRY => INT_CARRY(223) ); ---- End FA stage ---- Begin NO stage INT_SUM(277) <= SUMMAND(321); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_227:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(276), DATA_B => INT_SUM(277), DATA_C => INT_CARRY(220), SAVE => INT_SUM(278), CARRY => INT_CARRY(224) ); ---- End FA stage ---- Begin NO stage INT_SUM(279) <= INT_CARRY(221); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_228:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(278), DATA_B => INT_SUM(279), DATA_C => INT_CARRY(222), SAVE => SUM(45), CARRY => CARRY(45) ); ---- End FA stage -- End WT-branch 46 -- Begin WT-branch 47 ---- Begin FA stage FA_229:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(322), DATA_B => SUMMAND(323), DATA_C => SUMMAND(324), SAVE => INT_SUM(280), CARRY => INT_CARRY(225) ); ---- End FA stage ---- Begin NO stage INT_SUM(281) <= INT_SUM(280); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(282) <= INT_CARRY(223); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_230:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(281), DATA_B => INT_SUM(282), DATA_C => INT_CARRY(224), SAVE => SUM(46), CARRY => CARRY(46) ); ---- End FA stage -- End WT-branch 47 -- Begin WT-branch 48 ---- Begin FA stage FA_231:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(325), DATA_B => SUMMAND(326), DATA_C => SUMMAND(327), SAVE => INT_SUM(283), CARRY => INT_CARRY(226) ); ---- End FA stage ---- Begin NO stage INT_SUM(284) <= INT_CARRY(225); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_41:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(283), DATA_B => INT_SUM(284), SAVE => SUM(47), CARRY => CARRY(47) ); ---- End HA stage -- End WT-branch 48 -- Begin WT-branch 49 ---- Begin NO stage INT_SUM(285) <= SUMMAND(328); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(286) <= SUMMAND(329); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_232:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(285), DATA_B => INT_SUM(286), DATA_C => INT_CARRY(226), SAVE => SUM(48), CARRY => CARRY(48) ); ---- End FA stage -- End WT-branch 49 -- Begin WT-branch 50 ---- Begin HA stage HA_42:HALF_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(330), DATA_B => SUMMAND(331), SAVE => SUM(49), CARRY => CARRY(49) ); ---- End HA stage -- End WT-branch 50 -- Begin WT-branch 51 ---- Begin NO stage SUM(50) <= SUMMAND(332); -- At Level 5 ---- End NO stage -- End WT-branch 51 end WALLACE; ------------------------------------------------------------ -- END: Architectures used with the Wallace-tree ------------------------------------------------------------ ------------------------------------------------------------ -- START: Architectures used with the multiplier ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_18 is port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 17); PHI: in std_logic; RESULT: out std_logic_vector(0 to 63) ); end MULTIPLIER_34_18; ------------------------------------------------------------ -- End: Multiplier Entitiy architecture MULTIPLIER of MULTIPLIER_34_18 is signal PPBIT:std_logic_vector(0 to 332); signal INT_CARRY: std_logic_vector(0 to 64); signal INT_SUM: std_logic_vector(0 to 63); signal LOGIC_ZERO: std_logic; begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_18 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 17) => MULTIPLIER(0 to 17), SUMMAND(0 to 332) => PPBIT(0 to 332) ); W:WALLACE_34_18 port map ( SUMMAND(0 to 332) => PPBIT(0 to 332), CARRY(0 to 49) => INT_CARRY(1 to 50), SUM(0 to 50) => INT_SUM(0 to 50) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(51) <= LOGIC_ZERO; INT_CARRY(52) <= LOGIC_ZERO; INT_CARRY(53) <= LOGIC_ZERO; INT_CARRY(54) <= LOGIC_ZERO; INT_CARRY(55) <= LOGIC_ZERO; INT_CARRY(56) <= LOGIC_ZERO; INT_CARRY(57) <= LOGIC_ZERO; INT_CARRY(58) <= LOGIC_ZERO; INT_CARRY(59) <= LOGIC_ZERO; INT_CARRY(60) <= LOGIC_ZERO; INT_CARRY(61) <= LOGIC_ZERO; INT_CARRY(62) <= LOGIC_ZERO; INT_CARRY(63) <= LOGIC_ZERO; INT_SUM(51) <= LOGIC_ZERO; INT_SUM(52) <= LOGIC_ZERO; INT_SUM(53) <= LOGIC_ZERO; INT_SUM(54) <= LOGIC_ZERO; INT_SUM(55) <= LOGIC_ZERO; INT_SUM(56) <= LOGIC_ZERO; INT_SUM(57) <= LOGIC_ZERO; INT_SUM(58) <= LOGIC_ZERO; INT_SUM(59) <= LOGIC_ZERO; INT_SUM(60) <= LOGIC_ZERO; INT_SUM(61) <= LOGIC_ZERO; INT_SUM(62) <= LOGIC_ZERO; INT_SUM(63) <= LOGIC_ZERO; D:DBLCADDER_64_64 port map ( OPA(0 to 63) => INT_SUM(0 to 63), OPB(0 to 63) => INT_CARRY(0 to 63), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 63) => RESULT(0 to 63) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ -- -- Modgen multiplier created Fri Aug 16 16:29:15 2002 -- ------------------------------------------------------------ -- START: Multiplier Entitiy ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -- START: Top entity ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_17 is port(X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(16 downto 0); P: out std_logic_vector(49 downto 0)); end MUL_33_17; library ieee; use ieee.std_logic_1164.all; architecture A of MUL_33_17 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 17); signal Q: std_logic_vector(0 to 63); signal CLK: std_logic; begin U1: MULTIPLIER_34_18 port map(A,B,CLK,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(16); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); P(42) <= Q(42); P(43) <= Q(43); P(44) <= Q(44); P(45) <= Q(45); P(46) <= Q(46); P(47) <= Q(47); P(48) <= Q(48); P(49) <= Q(49); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity BOOTHCODER_34_34 is port ( OPA: in std_logic_vector(0 to 33); OPB: in std_logic_vector(0 to 33); SUMMAND: out std_logic_vector(0 to 628) ); end BOOTHCODER_34_34; architecture BOOTHCODER of BOOTHCODER_34_34 is -- Internal signal in Booth structure signal INV_MULTIPLICAND: std_logic_vector(0 to 33); signal INT_MULTIPLIER: std_logic_vector(0 to 67); signal LOGIC_ONE, LOGIC_ZERO: std_logic; begin LOGIC_ONE <= '1'; LOGIC_ZERO <= '0'; -- Begin decoder block 1 DEC_0:DECODER -- Decoder of multiplier operand port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3) ); -- End decoder block 1 -- Begin partial product 1 INV_MULTIPLICAND(0) <= NOT OPA(0); PPL_0:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(0) ); RGATE_0:R_GATE port map ( INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1), PPBIT => SUMMAND(1) ); INV_MULTIPLICAND(1) <= NOT OPA(1); PPM_0:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(2) ); INV_MULTIPLICAND(2) <= NOT OPA(2); PPM_1:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(3) ); INV_MULTIPLICAND(3) <= NOT OPA(3); PPM_2:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(6) ); INV_MULTIPLICAND(4) <= NOT OPA(4); PPM_3:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(8) ); INV_MULTIPLICAND(5) <= NOT OPA(5); PPM_4:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(12) ); INV_MULTIPLICAND(6) <= NOT OPA(6); PPM_5:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(15) ); INV_MULTIPLICAND(7) <= NOT OPA(7); PPM_6:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(20) ); INV_MULTIPLICAND(8) <= NOT OPA(8); PPM_7:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(24) ); INV_MULTIPLICAND(9) <= NOT OPA(9); PPM_8:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(30) ); INV_MULTIPLICAND(10) <= NOT OPA(10); PPM_9:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(35) ); INV_MULTIPLICAND(11) <= NOT OPA(11); PPM_10:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(42) ); INV_MULTIPLICAND(12) <= NOT OPA(12); PPM_11:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(48) ); INV_MULTIPLICAND(13) <= NOT OPA(13); PPM_12:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(56) ); INV_MULTIPLICAND(14) <= NOT OPA(14); PPM_13:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(63) ); INV_MULTIPLICAND(15) <= NOT OPA(15); PPM_14:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(72) ); INV_MULTIPLICAND(16) <= NOT OPA(16); PPM_15:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(80) ); INV_MULTIPLICAND(17) <= NOT OPA(17); PPM_16:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(90) ); INV_MULTIPLICAND(18) <= NOT OPA(18); PPM_17:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(99) ); INV_MULTIPLICAND(19) <= NOT OPA(19); PPM_18:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(110) ); INV_MULTIPLICAND(20) <= NOT OPA(20); PPM_19:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(120) ); INV_MULTIPLICAND(21) <= NOT OPA(21); PPM_20:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(132) ); INV_MULTIPLICAND(22) <= NOT OPA(22); PPM_21:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(143) ); INV_MULTIPLICAND(23) <= NOT OPA(23); PPM_22:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(156) ); INV_MULTIPLICAND(24) <= NOT OPA(24); PPM_23:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(168) ); INV_MULTIPLICAND(25) <= NOT OPA(25); PPM_24:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(182) ); INV_MULTIPLICAND(26) <= NOT OPA(26); PPM_25:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(195) ); INV_MULTIPLICAND(27) <= NOT OPA(27); PPM_26:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(210) ); INV_MULTIPLICAND(28) <= NOT OPA(28); PPM_27:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(224) ); INV_MULTIPLICAND(29) <= NOT OPA(29); PPM_28:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(240) ); INV_MULTIPLICAND(30) <= NOT OPA(30); PPM_29:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(255) ); INV_MULTIPLICAND(31) <= NOT OPA(31); PPM_30:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(272) ); INV_MULTIPLICAND(32) <= NOT OPA(32); PPM_31:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(288) ); INV_MULTIPLICAND(33) <= NOT OPA(33); PPM_32:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(306) ); PPH_0:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3), PPBIT => SUMMAND(323) ); SUMMAND(324) <= '1'; -- Begin partial product 1 -- Begin decoder block 2 DEC_1:DECODER -- Decoder of multiplier operand port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7) ); -- End decoder block 2 -- Begin partial product 2 PPL_1:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(4) ); RGATE_1:R_GATE port map ( INA => OPB(1),INB => OPB(2),INC => OPB(3), PPBIT => SUMMAND(5) ); PPM_33:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(7) ); PPM_34:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(9) ); PPM_35:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(13) ); PPM_36:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(16) ); PPM_37:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(21) ); PPM_38:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(25) ); PPM_39:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(31) ); PPM_40:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(36) ); PPM_41:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(43) ); PPM_42:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(49) ); PPM_43:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(57) ); PPM_44:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(64) ); PPM_45:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(73) ); PPM_46:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(81) ); PPM_47:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(91) ); PPM_48:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(100) ); PPM_49:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(111) ); PPM_50:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(121) ); PPM_51:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(133) ); PPM_52:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(144) ); PPM_53:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(157) ); PPM_54:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(169) ); PPM_55:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(183) ); PPM_56:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(196) ); PPM_57:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(211) ); PPM_58:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(225) ); PPM_59:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(241) ); PPM_60:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(256) ); PPM_61:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(273) ); PPM_62:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(289) ); PPM_63:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(307) ); PPM_64:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(325) ); PPM_65:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(341) ); SUMMAND(342) <= LOGIC_ONE; PPH_1:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7), PPBIT => SUMMAND(358) ); -- Begin partial product 2 -- Begin decoder block 3 DEC_2:DECODER -- Decoder of multiplier operand port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11) ); -- End decoder block 3 -- Begin partial product 3 PPL_2:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(10) ); RGATE_2:R_GATE port map ( INA => OPB(3),INB => OPB(4),INC => OPB(5), PPBIT => SUMMAND(11) ); PPM_66:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(14) ); PPM_67:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(17) ); PPM_68:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(22) ); PPM_69:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(26) ); PPM_70:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(32) ); PPM_71:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(37) ); PPM_72:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(44) ); PPM_73:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(50) ); PPM_74:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(58) ); PPM_75:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(65) ); PPM_76:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(74) ); PPM_77:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(82) ); PPM_78:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(92) ); PPM_79:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(101) ); PPM_80:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(112) ); PPM_81:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(122) ); PPM_82:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(134) ); PPM_83:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(145) ); PPM_84:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(158) ); PPM_85:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(170) ); PPM_86:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(184) ); PPM_87:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(197) ); PPM_88:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(212) ); PPM_89:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(226) ); PPM_90:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(242) ); PPM_91:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(257) ); PPM_92:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(274) ); PPM_93:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(290) ); PPM_94:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(308) ); PPM_95:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(326) ); PPM_96:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(343) ); PPM_97:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(359) ); PPM_98:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(374) ); SUMMAND(375) <= LOGIC_ONE; PPH_2:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11), PPBIT => SUMMAND(390) ); -- Begin partial product 3 -- Begin decoder block 4 DEC_3:DECODER -- Decoder of multiplier operand port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15) ); -- End decoder block 4 -- Begin partial product 4 PPL_3:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(18) ); RGATE_3:R_GATE port map ( INA => OPB(5),INB => OPB(6),INC => OPB(7), PPBIT => SUMMAND(19) ); PPM_99:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(23) ); PPM_100:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(27) ); PPM_101:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(33) ); PPM_102:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(38) ); PPM_103:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(45) ); PPM_104:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(51) ); PPM_105:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(59) ); PPM_106:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(66) ); PPM_107:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(75) ); PPM_108:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(83) ); PPM_109:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(93) ); PPM_110:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(102) ); PPM_111:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(113) ); PPM_112:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(123) ); PPM_113:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(135) ); PPM_114:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(146) ); PPM_115:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(159) ); PPM_116:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(171) ); PPM_117:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(185) ); PPM_118:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(198) ); PPM_119:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(213) ); PPM_120:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(227) ); PPM_121:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(243) ); PPM_122:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(258) ); PPM_123:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(275) ); PPM_124:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(291) ); PPM_125:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(309) ); PPM_126:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(327) ); PPM_127:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(344) ); PPM_128:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(360) ); PPM_129:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(376) ); PPM_130:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(391) ); PPM_131:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(405) ); SUMMAND(406) <= LOGIC_ONE; PPH_3:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15), PPBIT => SUMMAND(420) ); -- Begin partial product 4 -- Begin decoder block 5 DEC_4:DECODER -- Decoder of multiplier operand port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19) ); -- End decoder block 5 -- Begin partial product 5 PPL_4:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(28) ); RGATE_4:R_GATE port map ( INA => OPB(7),INB => OPB(8),INC => OPB(9), PPBIT => SUMMAND(29) ); PPM_132:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(34) ); PPM_133:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(39) ); PPM_134:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(46) ); PPM_135:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(52) ); PPM_136:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(60) ); PPM_137:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(67) ); PPM_138:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(76) ); PPM_139:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(84) ); PPM_140:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(94) ); PPM_141:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(103) ); PPM_142:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(114) ); PPM_143:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(124) ); PPM_144:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(136) ); PPM_145:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(147) ); PPM_146:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(160) ); PPM_147:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(172) ); PPM_148:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(186) ); PPM_149:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(199) ); PPM_150:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(214) ); PPM_151:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(228) ); PPM_152:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(244) ); PPM_153:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(259) ); PPM_154:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(276) ); PPM_155:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(292) ); PPM_156:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(310) ); PPM_157:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(328) ); PPM_158:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(345) ); PPM_159:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(361) ); PPM_160:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(377) ); PPM_161:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(392) ); PPM_162:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(407) ); PPM_163:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(421) ); PPM_164:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(434) ); SUMMAND(435) <= LOGIC_ONE; PPH_4:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19), PPBIT => SUMMAND(448) ); -- Begin partial product 5 -- Begin decoder block 6 DEC_5:DECODER -- Decoder of multiplier operand port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23) ); -- End decoder block 6 -- Begin partial product 6 PPL_5:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(40) ); RGATE_5:R_GATE port map ( INA => OPB(9),INB => OPB(10),INC => OPB(11), PPBIT => SUMMAND(41) ); PPM_165:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(47) ); PPM_166:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(53) ); PPM_167:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(61) ); PPM_168:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(68) ); PPM_169:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(77) ); PPM_170:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(85) ); PPM_171:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(95) ); PPM_172:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(104) ); PPM_173:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(115) ); PPM_174:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(125) ); PPM_175:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(137) ); PPM_176:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(148) ); PPM_177:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(161) ); PPM_178:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(173) ); PPM_179:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(187) ); PPM_180:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(200) ); PPM_181:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(215) ); PPM_182:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(229) ); PPM_183:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(245) ); PPM_184:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(260) ); PPM_185:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(277) ); PPM_186:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(293) ); PPM_187:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(311) ); PPM_188:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(329) ); PPM_189:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(346) ); PPM_190:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(362) ); PPM_191:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(378) ); PPM_192:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(393) ); PPM_193:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(408) ); PPM_194:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(422) ); PPM_195:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(436) ); PPM_196:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(449) ); PPM_197:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(461) ); SUMMAND(462) <= LOGIC_ONE; PPH_5:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23), PPBIT => SUMMAND(474) ); -- Begin partial product 6 -- Begin decoder block 7 DEC_6:DECODER -- Decoder of multiplier operand port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27) ); -- End decoder block 7 -- Begin partial product 7 PPL_6:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(54) ); RGATE_6:R_GATE port map ( INA => OPB(11),INB => OPB(12),INC => OPB(13), PPBIT => SUMMAND(55) ); PPM_198:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(62) ); PPM_199:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(69) ); PPM_200:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(78) ); PPM_201:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(86) ); PPM_202:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(96) ); PPM_203:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(105) ); PPM_204:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(116) ); PPM_205:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(126) ); PPM_206:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(138) ); PPM_207:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(149) ); PPM_208:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(162) ); PPM_209:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(174) ); PPM_210:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(188) ); PPM_211:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(201) ); PPM_212:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(216) ); PPM_213:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(230) ); PPM_214:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(246) ); PPM_215:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(261) ); PPM_216:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(278) ); PPM_217:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(294) ); PPM_218:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(312) ); PPM_219:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(330) ); PPM_220:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(347) ); PPM_221:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(363) ); PPM_222:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(379) ); PPM_223:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(394) ); PPM_224:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(409) ); PPM_225:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(423) ); PPM_226:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(437) ); PPM_227:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(450) ); PPM_228:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(463) ); PPM_229:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(475) ); PPM_230:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(486) ); SUMMAND(487) <= LOGIC_ONE; PPH_6:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27), PPBIT => SUMMAND(498) ); -- Begin partial product 7 -- Begin decoder block 8 DEC_7:DECODER -- Decoder of multiplier operand port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31) ); -- End decoder block 8 -- Begin partial product 8 PPL_7:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(70) ); RGATE_7:R_GATE port map ( INA => OPB(13),INB => OPB(14),INC => OPB(15), PPBIT => SUMMAND(71) ); PPM_231:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(79) ); PPM_232:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(87) ); PPM_233:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(97) ); PPM_234:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(106) ); PPM_235:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(117) ); PPM_236:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(127) ); PPM_237:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(139) ); PPM_238:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(150) ); PPM_239:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(163) ); PPM_240:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(175) ); PPM_241:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(189) ); PPM_242:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(202) ); PPM_243:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(217) ); PPM_244:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(231) ); PPM_245:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(247) ); PPM_246:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(262) ); PPM_247:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(279) ); PPM_248:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(295) ); PPM_249:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(313) ); PPM_250:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(331) ); PPM_251:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(348) ); PPM_252:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(364) ); PPM_253:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(380) ); PPM_254:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(395) ); PPM_255:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(410) ); PPM_256:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(424) ); PPM_257:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(438) ); PPM_258:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(451) ); PPM_259:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(464) ); PPM_260:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(476) ); PPM_261:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(488) ); PPM_262:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(499) ); PPM_263:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(509) ); SUMMAND(510) <= LOGIC_ONE; PPH_7:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31), PPBIT => SUMMAND(520) ); -- Begin partial product 8 -- Begin decoder block 9 DEC_8:DECODER -- Decoder of multiplier operand port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35) ); -- End decoder block 9 -- Begin partial product 9 PPL_8:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(88) ); RGATE_8:R_GATE port map ( INA => OPB(15),INB => OPB(16),INC => OPB(17), PPBIT => SUMMAND(89) ); PPM_264:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(98) ); PPM_265:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(107) ); PPM_266:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(118) ); PPM_267:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(128) ); PPM_268:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(140) ); PPM_269:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(151) ); PPM_270:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(164) ); PPM_271:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(176) ); PPM_272:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(190) ); PPM_273:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(203) ); PPM_274:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(218) ); PPM_275:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(232) ); PPM_276:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(248) ); PPM_277:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(263) ); PPM_278:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(280) ); PPM_279:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(296) ); PPM_280:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(314) ); PPM_281:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(332) ); PPM_282:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(349) ); PPM_283:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(365) ); PPM_284:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(381) ); PPM_285:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(396) ); PPM_286:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(411) ); PPM_287:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(425) ); PPM_288:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(439) ); PPM_289:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(452) ); PPM_290:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(465) ); PPM_291:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(477) ); PPM_292:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(489) ); PPM_293:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(500) ); PPM_294:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(511) ); PPM_295:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(521) ); PPM_296:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(530) ); SUMMAND(531) <= LOGIC_ONE; PPH_8:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35), PPBIT => SUMMAND(540) ); -- Begin partial product 9 -- Begin decoder block 10 DEC_9:DECODER -- Decoder of multiplier operand port map ( INA => OPB(17),INB => OPB(18),INC => OPB(19), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39) ); -- End decoder block 10 -- Begin partial product 10 PPL_9:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(108) ); RGATE_9:R_GATE port map ( INA => OPB(17),INB => OPB(18),INC => OPB(19), PPBIT => SUMMAND(109) ); PPM_297:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(119) ); PPM_298:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(129) ); PPM_299:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(141) ); PPM_300:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(152) ); PPM_301:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(165) ); PPM_302:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(177) ); PPM_303:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(191) ); PPM_304:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(204) ); PPM_305:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(219) ); PPM_306:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(233) ); PPM_307:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(249) ); PPM_308:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(264) ); PPM_309:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(281) ); PPM_310:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(297) ); PPM_311:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(315) ); PPM_312:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(333) ); PPM_313:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(350) ); PPM_314:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(366) ); PPM_315:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(382) ); PPM_316:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(397) ); PPM_317:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(412) ); PPM_318:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(426) ); PPM_319:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(440) ); PPM_320:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(453) ); PPM_321:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(466) ); PPM_322:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(478) ); PPM_323:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(490) ); PPM_324:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(501) ); PPM_325:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(512) ); PPM_326:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(522) ); PPM_327:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(532) ); PPM_328:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(541) ); PPM_329:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(549) ); SUMMAND(550) <= LOGIC_ONE; PPH_9:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39), PPBIT => SUMMAND(558) ); -- Begin partial product 10 -- Begin decoder block 11 DEC_10:DECODER -- Decoder of multiplier operand port map ( INA => OPB(19),INB => OPB(20),INC => OPB(21), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43) ); -- End decoder block 11 -- Begin partial product 11 PPL_10:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(130) ); RGATE_10:R_GATE port map ( INA => OPB(19),INB => OPB(20),INC => OPB(21), PPBIT => SUMMAND(131) ); PPM_330:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(142) ); PPM_331:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(153) ); PPM_332:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(166) ); PPM_333:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(178) ); PPM_334:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(192) ); PPM_335:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(205) ); PPM_336:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(220) ); PPM_337:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(234) ); PPM_338:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(250) ); PPM_339:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(265) ); PPM_340:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(282) ); PPM_341:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(298) ); PPM_342:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(316) ); PPM_343:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(334) ); PPM_344:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(351) ); PPM_345:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(367) ); PPM_346:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(383) ); PPM_347:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(398) ); PPM_348:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(413) ); PPM_349:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(427) ); PPM_350:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(441) ); PPM_351:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(454) ); PPM_352:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(467) ); PPM_353:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(479) ); PPM_354:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(491) ); PPM_355:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(502) ); PPM_356:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(513) ); PPM_357:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(523) ); PPM_358:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(533) ); PPM_359:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(542) ); PPM_360:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(551) ); PPM_361:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(559) ); PPM_362:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(566) ); SUMMAND(567) <= LOGIC_ONE; PPH_10:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43), PPBIT => SUMMAND(574) ); -- Begin partial product 11 -- Begin decoder block 12 DEC_11:DECODER -- Decoder of multiplier operand port map ( INA => OPB(21),INB => OPB(22),INC => OPB(23), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47) ); -- End decoder block 12 -- Begin partial product 12 PPL_11:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(154) ); RGATE_11:R_GATE port map ( INA => OPB(21),INB => OPB(22),INC => OPB(23), PPBIT => SUMMAND(155) ); PPM_363:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(167) ); PPM_364:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(179) ); PPM_365:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(193) ); PPM_366:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(206) ); PPM_367:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(221) ); PPM_368:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(235) ); PPM_369:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(251) ); PPM_370:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(266) ); PPM_371:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(283) ); PPM_372:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(299) ); PPM_373:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(317) ); PPM_374:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(335) ); PPM_375:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(352) ); PPM_376:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(368) ); PPM_377:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(384) ); PPM_378:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(399) ); PPM_379:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(414) ); PPM_380:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(428) ); PPM_381:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(442) ); PPM_382:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(455) ); PPM_383:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(468) ); PPM_384:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(480) ); PPM_385:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(492) ); PPM_386:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(503) ); PPM_387:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(514) ); PPM_388:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(524) ); PPM_389:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(534) ); PPM_390:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(543) ); PPM_391:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(552) ); PPM_392:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(560) ); PPM_393:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(568) ); PPM_394:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(575) ); PPM_395:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(581) ); SUMMAND(582) <= LOGIC_ONE; PPH_11:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47), PPBIT => SUMMAND(588) ); -- Begin partial product 12 -- Begin decoder block 13 DEC_12:DECODER -- Decoder of multiplier operand port map ( INA => OPB(23),INB => OPB(24),INC => OPB(25), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51) ); -- End decoder block 13 -- Begin partial product 13 PPL_12:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(180) ); RGATE_12:R_GATE port map ( INA => OPB(23),INB => OPB(24),INC => OPB(25), PPBIT => SUMMAND(181) ); PPM_396:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(194) ); PPM_397:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(207) ); PPM_398:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(222) ); PPM_399:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(236) ); PPM_400:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(252) ); PPM_401:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(267) ); PPM_402:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(284) ); PPM_403:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(300) ); PPM_404:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(318) ); PPM_405:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(336) ); PPM_406:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(353) ); PPM_407:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(369) ); PPM_408:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(385) ); PPM_409:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(400) ); PPM_410:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(415) ); PPM_411:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(429) ); PPM_412:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(443) ); PPM_413:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(456) ); PPM_414:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(469) ); PPM_415:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(481) ); PPM_416:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(493) ); PPM_417:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(504) ); PPM_418:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(515) ); PPM_419:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(525) ); PPM_420:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(535) ); PPM_421:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(544) ); PPM_422:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(553) ); PPM_423:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(561) ); PPM_424:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(569) ); PPM_425:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(576) ); PPM_426:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(583) ); PPM_427:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(589) ); PPM_428:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(594) ); SUMMAND(595) <= LOGIC_ONE; PPH_12:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51), PPBIT => SUMMAND(600) ); -- Begin partial product 13 -- Begin decoder block 14 DEC_13:DECODER -- Decoder of multiplier operand port map ( INA => OPB(25),INB => OPB(26),INC => OPB(27), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55) ); -- End decoder block 14 -- Begin partial product 14 PPL_13:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(208) ); RGATE_13:R_GATE port map ( INA => OPB(25),INB => OPB(26),INC => OPB(27), PPBIT => SUMMAND(209) ); PPM_429:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(223) ); PPM_430:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(237) ); PPM_431:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(253) ); PPM_432:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(268) ); PPM_433:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(285) ); PPM_434:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(301) ); PPM_435:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(319) ); PPM_436:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(337) ); PPM_437:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(354) ); PPM_438:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(370) ); PPM_439:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(386) ); PPM_440:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(401) ); PPM_441:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(416) ); PPM_442:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(430) ); PPM_443:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(444) ); PPM_444:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(457) ); PPM_445:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(470) ); PPM_446:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(482) ); PPM_447:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(494) ); PPM_448:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(505) ); PPM_449:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(516) ); PPM_450:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(526) ); PPM_451:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(536) ); PPM_452:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(545) ); PPM_453:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(554) ); PPM_454:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(562) ); PPM_455:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(570) ); PPM_456:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(577) ); PPM_457:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(584) ); PPM_458:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(590) ); PPM_459:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(596) ); PPM_460:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(601) ); PPM_461:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(605) ); SUMMAND(606) <= LOGIC_ONE; PPH_13:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55), PPBIT => SUMMAND(610) ); -- Begin partial product 14 -- Begin decoder block 15 DEC_14:DECODER -- Decoder of multiplier operand port map ( INA => OPB(27),INB => OPB(28),INC => OPB(29), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59) ); -- End decoder block 15 -- Begin partial product 15 PPL_14:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(238) ); RGATE_14:R_GATE port map ( INA => OPB(27),INB => OPB(28),INC => OPB(29), PPBIT => SUMMAND(239) ); PPM_462:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(254) ); PPM_463:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(269) ); PPM_464:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(286) ); PPM_465:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(302) ); PPM_466:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(320) ); PPM_467:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(338) ); PPM_468:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(355) ); PPM_469:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(371) ); PPM_470:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(387) ); PPM_471:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(402) ); PPM_472:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(417) ); PPM_473:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(431) ); PPM_474:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(445) ); PPM_475:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(458) ); PPM_476:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(471) ); PPM_477:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(483) ); PPM_478:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(495) ); PPM_479:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(506) ); PPM_480:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(517) ); PPM_481:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(527) ); PPM_482:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(537) ); PPM_483:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(546) ); PPM_484:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(555) ); PPM_485:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(563) ); PPM_486:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(571) ); PPM_487:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(578) ); PPM_488:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(585) ); PPM_489:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(591) ); PPM_490:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(597) ); PPM_491:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(602) ); PPM_492:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(607) ); PPM_493:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(611) ); PPM_494:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(614) ); SUMMAND(615) <= LOGIC_ONE; PPH_14:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59), PPBIT => SUMMAND(618) ); -- Begin partial product 15 -- Begin decoder block 16 DEC_15:DECODER -- Decoder of multiplier operand port map ( INA => OPB(29),INB => OPB(30),INC => OPB(31), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63) ); -- End decoder block 16 -- Begin partial product 16 PPL_15:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(270) ); RGATE_15:R_GATE port map ( INA => OPB(29),INB => OPB(30),INC => OPB(31), PPBIT => SUMMAND(271) ); PPM_495:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(287) ); PPM_496:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(303) ); PPM_497:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(321) ); PPM_498:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(339) ); PPM_499:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(356) ); PPM_500:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(372) ); PPM_501:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(388) ); PPM_502:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(403) ); PPM_503:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(418) ); PPM_504:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(432) ); PPM_505:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(446) ); PPM_506:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(459) ); PPM_507:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(472) ); PPM_508:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(484) ); PPM_509:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(496) ); PPM_510:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(507) ); PPM_511:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(518) ); PPM_512:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(528) ); PPM_513:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(538) ); PPM_514:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(547) ); PPM_515:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(556) ); PPM_516:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(564) ); PPM_517:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(572) ); PPM_518:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(579) ); PPM_519:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(586) ); PPM_520:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(592) ); PPM_521:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(598) ); PPM_522:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(603) ); PPM_523:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(608) ); PPM_524:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(612) ); PPM_525:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(616) ); PPM_526:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(619) ); PPM_527:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(621) ); SUMMAND(622) <= LOGIC_ONE; PPH_15:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63), PPBIT => SUMMAND(624) ); -- Begin partial product 16 -- Begin decoder block 17 DEC_16:DECODER -- Decoder of multiplier operand port map ( INA => OPB(31),INB => OPB(32),INC => OPB(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67) ); -- End decoder block 17 -- Begin partial product 17 PPL_16:PP_LOW port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(304) ); RGATE_16:R_GATE port map ( INA => OPB(31),INB => OPB(32),INC => OPB(33), PPBIT => SUMMAND(305) ); PPM_528:PP_MIDDLE port map ( INA => OPA(0),INB => INV_MULTIPLICAND(0), INC => OPA(1),IND => INV_MULTIPLICAND(1), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(322) ); PPM_529:PP_MIDDLE port map ( INA => OPA(1),INB => INV_MULTIPLICAND(1), INC => OPA(2),IND => INV_MULTIPLICAND(2), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(340) ); PPM_530:PP_MIDDLE port map ( INA => OPA(2),INB => INV_MULTIPLICAND(2), INC => OPA(3),IND => INV_MULTIPLICAND(3), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(357) ); PPM_531:PP_MIDDLE port map ( INA => OPA(3),INB => INV_MULTIPLICAND(3), INC => OPA(4),IND => INV_MULTIPLICAND(4), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(373) ); PPM_532:PP_MIDDLE port map ( INA => OPA(4),INB => INV_MULTIPLICAND(4), INC => OPA(5),IND => INV_MULTIPLICAND(5), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(389) ); PPM_533:PP_MIDDLE port map ( INA => OPA(5),INB => INV_MULTIPLICAND(5), INC => OPA(6),IND => INV_MULTIPLICAND(6), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(404) ); PPM_534:PP_MIDDLE port map ( INA => OPA(6),INB => INV_MULTIPLICAND(6), INC => OPA(7),IND => INV_MULTIPLICAND(7), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(419) ); PPM_535:PP_MIDDLE port map ( INA => OPA(7),INB => INV_MULTIPLICAND(7), INC => OPA(8),IND => INV_MULTIPLICAND(8), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(433) ); PPM_536:PP_MIDDLE port map ( INA => OPA(8),INB => INV_MULTIPLICAND(8), INC => OPA(9),IND => INV_MULTIPLICAND(9), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(447) ); PPM_537:PP_MIDDLE port map ( INA => OPA(9),INB => INV_MULTIPLICAND(9), INC => OPA(10),IND => INV_MULTIPLICAND(10), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(460) ); PPM_538:PP_MIDDLE port map ( INA => OPA(10),INB => INV_MULTIPLICAND(10), INC => OPA(11),IND => INV_MULTIPLICAND(11), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(473) ); PPM_539:PP_MIDDLE port map ( INA => OPA(11),INB => INV_MULTIPLICAND(11), INC => OPA(12),IND => INV_MULTIPLICAND(12), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(485) ); PPM_540:PP_MIDDLE port map ( INA => OPA(12),INB => INV_MULTIPLICAND(12), INC => OPA(13),IND => INV_MULTIPLICAND(13), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(497) ); PPM_541:PP_MIDDLE port map ( INA => OPA(13),INB => INV_MULTIPLICAND(13), INC => OPA(14),IND => INV_MULTIPLICAND(14), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(508) ); PPM_542:PP_MIDDLE port map ( INA => OPA(14),INB => INV_MULTIPLICAND(14), INC => OPA(15),IND => INV_MULTIPLICAND(15), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(519) ); PPM_543:PP_MIDDLE port map ( INA => OPA(15),INB => INV_MULTIPLICAND(15), INC => OPA(16),IND => INV_MULTIPLICAND(16), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(529) ); PPM_544:PP_MIDDLE port map ( INA => OPA(16),INB => INV_MULTIPLICAND(16), INC => OPA(17),IND => INV_MULTIPLICAND(17), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(539) ); PPM_545:PP_MIDDLE port map ( INA => OPA(17),INB => INV_MULTIPLICAND(17), INC => OPA(18),IND => INV_MULTIPLICAND(18), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(548) ); PPM_546:PP_MIDDLE port map ( INA => OPA(18),INB => INV_MULTIPLICAND(18), INC => OPA(19),IND => INV_MULTIPLICAND(19), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(557) ); PPM_547:PP_MIDDLE port map ( INA => OPA(19),INB => INV_MULTIPLICAND(19), INC => OPA(20),IND => INV_MULTIPLICAND(20), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(565) ); PPM_548:PP_MIDDLE port map ( INA => OPA(20),INB => INV_MULTIPLICAND(20), INC => OPA(21),IND => INV_MULTIPLICAND(21), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(573) ); PPM_549:PP_MIDDLE port map ( INA => OPA(21),INB => INV_MULTIPLICAND(21), INC => OPA(22),IND => INV_MULTIPLICAND(22), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(580) ); PPM_550:PP_MIDDLE port map ( INA => OPA(22),INB => INV_MULTIPLICAND(22), INC => OPA(23),IND => INV_MULTIPLICAND(23), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(587) ); PPM_551:PP_MIDDLE port map ( INA => OPA(23),INB => INV_MULTIPLICAND(23), INC => OPA(24),IND => INV_MULTIPLICAND(24), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(593) ); PPM_552:PP_MIDDLE port map ( INA => OPA(24),INB => INV_MULTIPLICAND(24), INC => OPA(25),IND => INV_MULTIPLICAND(25), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(599) ); PPM_553:PP_MIDDLE port map ( INA => OPA(25),INB => INV_MULTIPLICAND(25), INC => OPA(26),IND => INV_MULTIPLICAND(26), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(604) ); PPM_554:PP_MIDDLE port map ( INA => OPA(26),INB => INV_MULTIPLICAND(26), INC => OPA(27),IND => INV_MULTIPLICAND(27), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(609) ); PPM_555:PP_MIDDLE port map ( INA => OPA(27),INB => INV_MULTIPLICAND(27), INC => OPA(28),IND => INV_MULTIPLICAND(28), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(613) ); PPM_556:PP_MIDDLE port map ( INA => OPA(28),INB => INV_MULTIPLICAND(28), INC => OPA(29),IND => INV_MULTIPLICAND(29), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(617) ); PPM_557:PP_MIDDLE port map ( INA => OPA(29),INB => INV_MULTIPLICAND(29), INC => OPA(30),IND => INV_MULTIPLICAND(30), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(620) ); PPM_558:PP_MIDDLE port map ( INA => OPA(30),INB => INV_MULTIPLICAND(30), INC => OPA(31),IND => INV_MULTIPLICAND(31), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(623) ); PPM_559:PP_MIDDLE port map ( INA => OPA(31),INB => INV_MULTIPLICAND(31), INC => OPA(32),IND => INV_MULTIPLICAND(32), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(625) ); PPM_560:PP_MIDDLE port map ( INA => OPA(32),INB => INV_MULTIPLICAND(32), INC => OPA(33),IND => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(626) ); SUMMAND(627) <= LOGIC_ONE; PPH_16:PP_HIGH port map ( INA => OPA(33),INB => INV_MULTIPLICAND(33), TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67), PPBIT => SUMMAND(628) ); -- Begin partial product 17 end BOOTHCODER; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity WALLACE_34_34 is port ( SUMMAND: in std_logic_vector(0 to 628); CARRY: out std_logic_vector(0 to 65); SUM: out std_logic_vector(0 to 66) ); end WALLACE_34_34; architecture WALLACE of WALLACE_34_34 is -- Signals used inside the wallace trees signal INT_CARRY: std_logic_vector(0 to 486); signal INT_SUM: std_logic_vector(0 to 620); begin -- netlist -- Begin WT-branch 1 ---- Begin HA stage HA_0:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(0), DATA_B => SUMMAND(1), SAVE => SUM(0), CARRY => CARRY(0) ); ---- End HA stage -- End WT-branch 1 -- Begin WT-branch 2 ---- Begin NO stage SUM(1) <= SUMMAND(2); -- At Level 1 CARRY(1) <= '0'; ---- End NO stage -- End WT-branch 2 -- Begin WT-branch 3 ---- Begin FA stage FA_0:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5), SAVE => SUM(2), CARRY => CARRY(2) ); ---- End FA stage -- End WT-branch 3 -- Begin WT-branch 4 ---- Begin HA stage HA_1:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(6), DATA_B => SUMMAND(7), SAVE => SUM(3), CARRY => CARRY(3) ); ---- End HA stage -- End WT-branch 4 -- Begin WT-branch 5 ---- Begin FA stage FA_1:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10), SAVE => INT_SUM(0), CARRY => INT_CARRY(0) ); ---- End FA stage ---- Begin NO stage INT_SUM(1) <= SUMMAND(11); -- At Level 1 ---- End NO stage ---- Begin HA stage HA_2:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(0), DATA_B => INT_SUM(1), SAVE => SUM(4), CARRY => CARRY(4) ); ---- End HA stage -- End WT-branch 5 -- Begin WT-branch 6 ---- Begin FA stage FA_2:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14), SAVE => INT_SUM(2), CARRY => INT_CARRY(1) ); ---- End FA stage ---- Begin HA stage HA_3:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0), SAVE => SUM(5), CARRY => CARRY(5) ); ---- End HA stage -- End WT-branch 6 -- Begin WT-branch 7 ---- Begin FA stage FA_3:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17), SAVE => INT_SUM(3), CARRY => INT_CARRY(2) ); ---- End FA stage ---- Begin HA stage HA_4:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(18), DATA_B => SUMMAND(19), SAVE => INT_SUM(4), CARRY => INT_CARRY(3) ); ---- End HA stage ---- Begin FA stage FA_4:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1), SAVE => SUM(6), CARRY => CARRY(6) ); ---- End FA stage -- End WT-branch 7 -- Begin WT-branch 8 ---- Begin FA stage FA_5:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22), SAVE => INT_SUM(5), CARRY => INT_CARRY(4) ); ---- End FA stage ---- Begin NO stage INT_SUM(6) <= SUMMAND(23); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_6:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2), SAVE => INT_SUM(7), CARRY => INT_CARRY(5) ); ---- End FA stage ---- Begin NO stage INT_SUM(8) <= INT_CARRY(3); -- At Level 2 ---- End NO stage ---- Begin HA stage HA_5:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(7), DATA_B => INT_SUM(8), SAVE => SUM(7), CARRY => CARRY(7) ); ---- End HA stage -- End WT-branch 8 -- Begin WT-branch 9 ---- Begin FA stage FA_7:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26), SAVE => INT_SUM(9), CARRY => INT_CARRY(6) ); ---- End FA stage ---- Begin FA stage FA_8:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29), SAVE => INT_SUM(10), CARRY => INT_CARRY(7) ); ---- End FA stage ---- Begin FA stage FA_9:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4), SAVE => INT_SUM(11), CARRY => INT_CARRY(8) ); ---- End FA stage ---- Begin HA stage HA_6:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5), SAVE => SUM(8), CARRY => CARRY(8) ); ---- End HA stage -- End WT-branch 9 -- Begin WT-branch 10 ---- Begin FA stage FA_10:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32), SAVE => INT_SUM(12), CARRY => INT_CARRY(9) ); ---- End FA stage ---- Begin HA stage HA_7:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(33), DATA_B => SUMMAND(34), SAVE => INT_SUM(13), CARRY => INT_CARRY(10) ); ---- End HA stage ---- Begin FA stage FA_11:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6), SAVE => INT_SUM(14), CARRY => INT_CARRY(11) ); ---- End FA stage ---- Begin NO stage INT_SUM(15) <= INT_CARRY(7); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_12:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8), SAVE => SUM(9), CARRY => CARRY(9) ); ---- End FA stage -- End WT-branch 10 -- Begin WT-branch 11 ---- Begin FA stage FA_13:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37), SAVE => INT_SUM(16), CARRY => INT_CARRY(12) ); ---- End FA stage ---- Begin FA stage FA_14:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40), SAVE => INT_SUM(17), CARRY => INT_CARRY(13) ); ---- End FA stage ---- Begin NO stage INT_SUM(18) <= SUMMAND(41); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_15:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18), SAVE => INT_SUM(19), CARRY => INT_CARRY(14) ); ---- End FA stage ---- Begin HA stage HA_8:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10), SAVE => INT_SUM(20), CARRY => INT_CARRY(15) ); ---- End HA stage ---- Begin FA stage FA_16:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11), SAVE => SUM(10), CARRY => CARRY(10) ); ---- End FA stage -- End WT-branch 11 -- Begin WT-branch 12 ---- Begin FA stage FA_17:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44), SAVE => INT_SUM(21), CARRY => INT_CARRY(16) ); ---- End FA stage ---- Begin FA stage FA_18:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47), SAVE => INT_SUM(22), CARRY => INT_CARRY(17) ); ---- End FA stage ---- Begin FA stage FA_19:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12), SAVE => INT_SUM(23), CARRY => INT_CARRY(18) ); ---- End FA stage ---- Begin NO stage INT_SUM(24) <= INT_CARRY(13); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_20:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14), SAVE => INT_SUM(25), CARRY => INT_CARRY(19) ); ---- End FA stage ---- Begin NO stage INT_SUM(26) <= INT_CARRY(15); -- At Level 3 ---- End NO stage ---- Begin HA stage HA_9:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(25), DATA_B => INT_SUM(26), SAVE => SUM(11), CARRY => CARRY(11) ); ---- End HA stage -- End WT-branch 12 -- Begin WT-branch 13 ---- Begin FA stage FA_21:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50), SAVE => INT_SUM(27), CARRY => INT_CARRY(20) ); ---- End FA stage ---- Begin FA stage FA_22:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53), SAVE => INT_SUM(28), CARRY => INT_CARRY(21) ); ---- End FA stage ---- Begin NO stage INT_SUM(29) <= SUMMAND(54); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(30) <= SUMMAND(55); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_23:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29), SAVE => INT_SUM(31), CARRY => INT_CARRY(22) ); ---- End FA stage ---- Begin FA stage FA_24:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17), SAVE => INT_SUM(32), CARRY => INT_CARRY(23) ); ---- End FA stage ---- Begin FA stage FA_25:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18), SAVE => INT_SUM(33), CARRY => INT_CARRY(24) ); ---- End FA stage ---- Begin HA stage HA_10:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19), SAVE => SUM(12), CARRY => CARRY(12) ); ---- End HA stage -- End WT-branch 13 -- Begin WT-branch 14 ---- Begin FA stage FA_26:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58), SAVE => INT_SUM(34), CARRY => INT_CARRY(25) ); ---- End FA stage ---- Begin FA stage FA_27:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61), SAVE => INT_SUM(35), CARRY => INT_CARRY(26) ); ---- End FA stage ---- Begin NO stage INT_SUM(36) <= SUMMAND(62); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_28:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36), SAVE => INT_SUM(37), CARRY => INT_CARRY(27) ); ---- End FA stage ---- Begin HA stage HA_11:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21), SAVE => INT_SUM(38), CARRY => INT_CARRY(28) ); ---- End HA stage ---- Begin FA stage FA_29:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22), SAVE => INT_SUM(39), CARRY => INT_CARRY(29) ); ---- End FA stage ---- Begin NO stage INT_SUM(40) <= INT_CARRY(23); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_30:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24), SAVE => SUM(13), CARRY => CARRY(13) ); ---- End FA stage -- End WT-branch 14 -- Begin WT-branch 15 ---- Begin FA stage FA_31:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65), SAVE => INT_SUM(41), CARRY => INT_CARRY(30) ); ---- End FA stage ---- Begin FA stage FA_32:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68), SAVE => INT_SUM(42), CARRY => INT_CARRY(31) ); ---- End FA stage ---- Begin FA stage FA_33:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71), SAVE => INT_SUM(43), CARRY => INT_CARRY(32) ); ---- End FA stage ---- Begin FA stage FA_34:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43), SAVE => INT_SUM(44), CARRY => INT_CARRY(33) ); ---- End FA stage ---- Begin HA stage HA_12:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26), SAVE => INT_SUM(45), CARRY => INT_CARRY(34) ); ---- End HA stage ---- Begin FA stage FA_35:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27), SAVE => INT_SUM(46), CARRY => INT_CARRY(35) ); ---- End FA stage ---- Begin NO stage INT_SUM(47) <= INT_CARRY(28); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_36:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29), SAVE => SUM(14), CARRY => CARRY(14) ); ---- End FA stage -- End WT-branch 15 -- Begin WT-branch 16 ---- Begin FA stage FA_37:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74), SAVE => INT_SUM(48), CARRY => INT_CARRY(36) ); ---- End FA stage ---- Begin FA stage FA_38:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77), SAVE => INT_SUM(49), CARRY => INT_CARRY(37) ); ---- End FA stage ---- Begin HA stage HA_13:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(78), DATA_B => SUMMAND(79), SAVE => INT_SUM(50), CARRY => INT_CARRY(38) ); ---- End HA stage ---- Begin FA stage FA_39:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50), SAVE => INT_SUM(51), CARRY => INT_CARRY(39) ); ---- End FA stage ---- Begin FA stage FA_40:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32), SAVE => INT_SUM(52), CARRY => INT_CARRY(40) ); ---- End FA stage ---- Begin FA stage FA_41:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33), SAVE => INT_SUM(53), CARRY => INT_CARRY(41) ); ---- End FA stage ---- Begin NO stage INT_SUM(54) <= INT_CARRY(34); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_42:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35), SAVE => SUM(15), CARRY => CARRY(15) ); ---- End FA stage -- End WT-branch 16 -- Begin WT-branch 17 ---- Begin FA stage FA_43:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82), SAVE => INT_SUM(55), CARRY => INT_CARRY(42) ); ---- End FA stage ---- Begin FA stage FA_44:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85), SAVE => INT_SUM(56), CARRY => INT_CARRY(43) ); ---- End FA stage ---- Begin FA stage FA_45:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88), SAVE => INT_SUM(57), CARRY => INT_CARRY(44) ); ---- End FA stage ---- Begin NO stage INT_SUM(58) <= SUMMAND(89); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_46:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57), SAVE => INT_SUM(59), CARRY => INT_CARRY(45) ); ---- End FA stage ---- Begin FA stage FA_47:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37), SAVE => INT_SUM(60), CARRY => INT_CARRY(46) ); ---- End FA stage ---- Begin NO stage INT_SUM(61) <= INT_CARRY(38); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_48:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61), SAVE => INT_SUM(62), CARRY => INT_CARRY(47) ); ---- End FA stage ---- Begin HA stage HA_14:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40), SAVE => INT_SUM(63), CARRY => INT_CARRY(48) ); ---- End HA stage ---- Begin FA stage FA_49:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41), SAVE => SUM(16), CARRY => CARRY(16) ); ---- End FA stage -- End WT-branch 17 -- Begin WT-branch 18 ---- Begin FA stage FA_50:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92), SAVE => INT_SUM(64), CARRY => INT_CARRY(49) ); ---- End FA stage ---- Begin FA stage FA_51:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95), SAVE => INT_SUM(65), CARRY => INT_CARRY(50) ); ---- End FA stage ---- Begin FA stage FA_52:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98), SAVE => INT_SUM(66), CARRY => INT_CARRY(51) ); ---- End FA stage ---- Begin FA stage FA_53:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66), SAVE => INT_SUM(67), CARRY => INT_CARRY(52) ); ---- End FA stage ---- Begin FA stage FA_54:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44), SAVE => INT_SUM(68), CARRY => INT_CARRY(53) ); ---- End FA stage ---- Begin FA stage FA_55:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45), SAVE => INT_SUM(69), CARRY => INT_CARRY(54) ); ---- End FA stage ---- Begin NO stage INT_SUM(70) <= INT_CARRY(46); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_56:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47), SAVE => INT_SUM(71), CARRY => INT_CARRY(55) ); ---- End FA stage ---- Begin NO stage INT_SUM(72) <= INT_CARRY(48); -- At Level 4 ---- End NO stage ---- Begin HA stage HA_15:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(71), DATA_B => INT_SUM(72), SAVE => SUM(17), CARRY => CARRY(17) ); ---- End HA stage -- End WT-branch 18 -- Begin WT-branch 19 ---- Begin FA stage FA_57:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101), SAVE => INT_SUM(73), CARRY => INT_CARRY(56) ); ---- End FA stage ---- Begin FA stage FA_58:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104), SAVE => INT_SUM(74), CARRY => INT_CARRY(57) ); ---- End FA stage ---- Begin FA stage FA_59:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107), SAVE => INT_SUM(75), CARRY => INT_CARRY(58) ); ---- End FA stage ---- Begin NO stage INT_SUM(76) <= SUMMAND(108); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(77) <= SUMMAND(109); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_60:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75), SAVE => INT_SUM(78), CARRY => INT_CARRY(59) ); ---- End FA stage ---- Begin FA stage FA_61:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(49), SAVE => INT_SUM(79), CARRY => INT_CARRY(60) ); ---- End FA stage ---- Begin NO stage INT_SUM(80) <= INT_CARRY(50); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(81) <= INT_CARRY(51); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_62:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_SUM(80), SAVE => INT_SUM(82), CARRY => INT_CARRY(61) ); ---- End FA stage ---- Begin FA stage FA_63:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(81), DATA_B => INT_CARRY(52), DATA_C => INT_CARRY(53), SAVE => INT_SUM(83), CARRY => INT_CARRY(62) ); ---- End FA stage ---- Begin FA stage FA_64:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(54), SAVE => INT_SUM(84), CARRY => INT_CARRY(63) ); ---- End FA stage ---- Begin HA stage HA_16:HALF_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(84), DATA_B => INT_CARRY(55), SAVE => SUM(18), CARRY => CARRY(18) ); ---- End HA stage -- End WT-branch 19 -- Begin WT-branch 20 ---- Begin FA stage FA_65:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112), SAVE => INT_SUM(85), CARRY => INT_CARRY(64) ); ---- End FA stage ---- Begin FA stage FA_66:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), DATA_C => SUMMAND(115), SAVE => INT_SUM(86), CARRY => INT_CARRY(65) ); ---- End FA stage ---- Begin FA stage FA_67:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(116), DATA_B => SUMMAND(117), DATA_C => SUMMAND(118), SAVE => INT_SUM(87), CARRY => INT_CARRY(66) ); ---- End FA stage ---- Begin NO stage INT_SUM(88) <= SUMMAND(119); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_68:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87), SAVE => INT_SUM(89), CARRY => INT_CARRY(67) ); ---- End FA stage ---- Begin FA stage FA_69:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(88), DATA_B => INT_CARRY(56), DATA_C => INT_CARRY(57), SAVE => INT_SUM(90), CARRY => INT_CARRY(68) ); ---- End FA stage ---- Begin NO stage INT_SUM(91) <= INT_CARRY(58); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_70:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91), SAVE => INT_SUM(92), CARRY => INT_CARRY(69) ); ---- End FA stage ---- Begin HA stage HA_17:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(59), DATA_B => INT_CARRY(60), SAVE => INT_SUM(93), CARRY => INT_CARRY(70) ); ---- End HA stage ---- Begin FA stage FA_71:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(61), SAVE => INT_SUM(94), CARRY => INT_CARRY(71) ); ---- End FA stage ---- Begin NO stage INT_SUM(95) <= INT_CARRY(62); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_72:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(63), SAVE => SUM(19), CARRY => CARRY(19) ); ---- End FA stage -- End WT-branch 20 -- Begin WT-branch 21 ---- Begin FA stage FA_73:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122), SAVE => INT_SUM(96), CARRY => INT_CARRY(72) ); ---- End FA stage ---- Begin FA stage FA_74:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125), SAVE => INT_SUM(97), CARRY => INT_CARRY(73) ); ---- End FA stage ---- Begin FA stage FA_75:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128), SAVE => INT_SUM(98), CARRY => INT_CARRY(74) ); ---- End FA stage ---- Begin FA stage FA_76:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131), SAVE => INT_SUM(99), CARRY => INT_CARRY(75) ); ---- End FA stage ---- Begin FA stage FA_77:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_SUM(98), SAVE => INT_SUM(100), CARRY => INT_CARRY(76) ); ---- End FA stage ---- Begin FA stage FA_78:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(99), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65), SAVE => INT_SUM(101), CARRY => INT_CARRY(77) ); ---- End FA stage ---- Begin NO stage INT_SUM(102) <= INT_CARRY(66); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_79:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_SUM(102), SAVE => INT_SUM(103), CARRY => INT_CARRY(78) ); ---- End FA stage ---- Begin HA stage HA_18:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(67), DATA_B => INT_CARRY(68), SAVE => INT_SUM(104), CARRY => INT_CARRY(79) ); ---- End HA stage ---- Begin FA stage FA_80:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(103), DATA_B => INT_SUM(104), DATA_C => INT_CARRY(69), SAVE => INT_SUM(105), CARRY => INT_CARRY(80) ); ---- End FA stage ---- Begin NO stage INT_SUM(106) <= INT_CARRY(70); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_81:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_CARRY(71), SAVE => SUM(20), CARRY => CARRY(20) ); ---- End FA stage -- End WT-branch 21 -- Begin WT-branch 22 ---- Begin FA stage FA_82:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134), SAVE => INT_SUM(107), CARRY => INT_CARRY(81) ); ---- End FA stage ---- Begin FA stage FA_83:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137), SAVE => INT_SUM(108), CARRY => INT_CARRY(82) ); ---- End FA stage ---- Begin FA stage FA_84:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140), SAVE => INT_SUM(109), CARRY => INT_CARRY(83) ); ---- End FA stage ---- Begin NO stage INT_SUM(110) <= SUMMAND(141); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(111) <= SUMMAND(142); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_85:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(107), DATA_B => INT_SUM(108), DATA_C => INT_SUM(109), SAVE => INT_SUM(112), CARRY => INT_CARRY(84) ); ---- End FA stage ---- Begin FA stage FA_86:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(72), SAVE => INT_SUM(113), CARRY => INT_CARRY(85) ); ---- End FA stage ---- Begin FA stage FA_87:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(73), DATA_B => INT_CARRY(74), DATA_C => INT_CARRY(75), SAVE => INT_SUM(114), CARRY => INT_CARRY(86) ); ---- End FA stage ---- Begin FA stage FA_88:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_SUM(114), SAVE => INT_SUM(115), CARRY => INT_CARRY(87) ); ---- End FA stage ---- Begin HA stage HA_19:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), SAVE => INT_SUM(116), CARRY => INT_CARRY(88) ); ---- End HA stage ---- Begin FA stage FA_89:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(78), SAVE => INT_SUM(117), CARRY => INT_CARRY(89) ); ---- End FA stage ---- Begin NO stage INT_SUM(118) <= INT_CARRY(79); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_90:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_CARRY(80), SAVE => SUM(21), CARRY => CARRY(21) ); ---- End FA stage -- End WT-branch 22 -- Begin WT-branch 23 ---- Begin FA stage FA_91:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), DATA_C => SUMMAND(145), SAVE => INT_SUM(119), CARRY => INT_CARRY(90) ); ---- End FA stage ---- Begin FA stage FA_92:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(146), DATA_B => SUMMAND(147), DATA_C => SUMMAND(148), SAVE => INT_SUM(120), CARRY => INT_CARRY(91) ); ---- End FA stage ---- Begin FA stage FA_93:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(149), DATA_B => SUMMAND(150), DATA_C => SUMMAND(151), SAVE => INT_SUM(121), CARRY => INT_CARRY(92) ); ---- End FA stage ---- Begin FA stage FA_94:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(152), DATA_B => SUMMAND(153), DATA_C => SUMMAND(154), SAVE => INT_SUM(122), CARRY => INT_CARRY(93) ); ---- End FA stage ---- Begin NO stage INT_SUM(123) <= SUMMAND(155); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_95:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(119), DATA_B => INT_SUM(120), DATA_C => INT_SUM(121), SAVE => INT_SUM(124), CARRY => INT_CARRY(94) ); ---- End FA stage ---- Begin FA stage FA_96:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(81), SAVE => INT_SUM(125), CARRY => INT_CARRY(95) ); ---- End FA stage ---- Begin HA stage HA_20:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83), SAVE => INT_SUM(126), CARRY => INT_CARRY(96) ); ---- End HA stage ---- Begin FA stage FA_97:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_SUM(126), SAVE => INT_SUM(127), CARRY => INT_CARRY(97) ); ---- End FA stage ---- Begin FA stage FA_98:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86), SAVE => INT_SUM(128), CARRY => INT_CARRY(98) ); ---- End FA stage ---- Begin FA stage FA_99:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(127), DATA_B => INT_SUM(128), DATA_C => INT_CARRY(87), SAVE => INT_SUM(129), CARRY => INT_CARRY(99) ); ---- End FA stage ---- Begin NO stage INT_SUM(130) <= INT_CARRY(88); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_100:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_CARRY(89), SAVE => SUM(22), CARRY => CARRY(22) ); ---- End FA stage -- End WT-branch 23 -- Begin WT-branch 24 ---- Begin FA stage FA_101:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158), SAVE => INT_SUM(131), CARRY => INT_CARRY(100) ); ---- End FA stage ---- Begin FA stage FA_102:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161), SAVE => INT_SUM(132), CARRY => INT_CARRY(101) ); ---- End FA stage ---- Begin FA stage FA_103:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164), SAVE => INT_SUM(133), CARRY => INT_CARRY(102) ); ---- End FA stage ---- Begin FA stage FA_104:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167), SAVE => INT_SUM(134), CARRY => INT_CARRY(103) ); ---- End FA stage ---- Begin FA stage FA_105:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(131), DATA_B => INT_SUM(132), DATA_C => INT_SUM(133), SAVE => INT_SUM(135), CARRY => INT_CARRY(104) ); ---- End FA stage ---- Begin FA stage FA_106:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(134), DATA_B => INT_CARRY(90), DATA_C => INT_CARRY(91), SAVE => INT_SUM(136), CARRY => INT_CARRY(105) ); ---- End FA stage ---- Begin HA stage HA_21:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(92), DATA_B => INT_CARRY(93), SAVE => INT_SUM(137), CARRY => INT_CARRY(106) ); ---- End HA stage ---- Begin FA stage FA_107:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_SUM(137), SAVE => INT_SUM(138), CARRY => INT_CARRY(107) ); ---- End FA stage ---- Begin FA stage FA_108:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(94), DATA_B => INT_CARRY(95), DATA_C => INT_CARRY(96), SAVE => INT_SUM(139), CARRY => INT_CARRY(108) ); ---- End FA stage ---- Begin FA stage FA_109:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(138), DATA_B => INT_SUM(139), DATA_C => INT_CARRY(97), SAVE => INT_SUM(140), CARRY => INT_CARRY(109) ); ---- End FA stage ---- Begin NO stage INT_SUM(141) <= INT_CARRY(98); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_110:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(99), SAVE => SUM(23), CARRY => CARRY(23) ); ---- End FA stage -- End WT-branch 24 -- Begin WT-branch 25 ---- Begin FA stage FA_111:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170), SAVE => INT_SUM(142), CARRY => INT_CARRY(110) ); ---- End FA stage ---- Begin FA stage FA_112:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173), SAVE => INT_SUM(143), CARRY => INT_CARRY(111) ); ---- End FA stage ---- Begin FA stage FA_113:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176), SAVE => INT_SUM(144), CARRY => INT_CARRY(112) ); ---- End FA stage ---- Begin FA stage FA_114:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179), SAVE => INT_SUM(145), CARRY => INT_CARRY(113) ); ---- End FA stage ---- Begin HA stage HA_22:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), SAVE => INT_SUM(146), CARRY => INT_CARRY(114) ); ---- End HA stage ---- Begin FA stage FA_115:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_SUM(144), SAVE => INT_SUM(147), CARRY => INT_CARRY(115) ); ---- End FA stage ---- Begin FA stage FA_116:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(100), SAVE => INT_SUM(148), CARRY => INT_CARRY(116) ); ---- End FA stage ---- Begin FA stage FA_117:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(101), DATA_B => INT_CARRY(102), DATA_C => INT_CARRY(103), SAVE => INT_SUM(149), CARRY => INT_CARRY(117) ); ---- End FA stage ---- Begin FA stage FA_118:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(147), DATA_B => INT_SUM(148), DATA_C => INT_SUM(149), SAVE => INT_SUM(150), CARRY => INT_CARRY(118) ); ---- End FA stage ---- Begin FA stage FA_119:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(104), DATA_B => INT_CARRY(105), DATA_C => INT_CARRY(106), SAVE => INT_SUM(151), CARRY => INT_CARRY(119) ); ---- End FA stage ---- Begin FA stage FA_120:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(107), SAVE => INT_SUM(152), CARRY => INT_CARRY(120) ); ---- End FA stage ---- Begin NO stage INT_SUM(153) <= INT_CARRY(108); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_121:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(152), DATA_B => INT_SUM(153), DATA_C => INT_CARRY(109), SAVE => SUM(24), CARRY => CARRY(24) ); ---- End FA stage -- End WT-branch 25 -- Begin WT-branch 26 ---- Begin FA stage FA_122:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), DATA_C => SUMMAND(184), SAVE => INT_SUM(154), CARRY => INT_CARRY(121) ); ---- End FA stage ---- Begin FA stage FA_123:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(185), DATA_B => SUMMAND(186), DATA_C => SUMMAND(187), SAVE => INT_SUM(155), CARRY => INT_CARRY(122) ); ---- End FA stage ---- Begin FA stage FA_124:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(188), DATA_B => SUMMAND(189), DATA_C => SUMMAND(190), SAVE => INT_SUM(156), CARRY => INT_CARRY(123) ); ---- End FA stage ---- Begin FA stage FA_125:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(191), DATA_B => SUMMAND(192), DATA_C => SUMMAND(193), SAVE => INT_SUM(157), CARRY => INT_CARRY(124) ); ---- End FA stage ---- Begin NO stage INT_SUM(158) <= SUMMAND(194); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_126:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(154), DATA_B => INT_SUM(155), DATA_C => INT_SUM(156), SAVE => INT_SUM(159), CARRY => INT_CARRY(125) ); ---- End FA stage ---- Begin FA stage FA_127:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(110), SAVE => INT_SUM(160), CARRY => INT_CARRY(126) ); ---- End FA stage ---- Begin FA stage FA_128:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(111), DATA_B => INT_CARRY(112), DATA_C => INT_CARRY(113), SAVE => INT_SUM(161), CARRY => INT_CARRY(127) ); ---- End FA stage ---- Begin NO stage INT_SUM(162) <= INT_CARRY(114); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_129:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(159), DATA_B => INT_SUM(160), DATA_C => INT_SUM(161), SAVE => INT_SUM(163), CARRY => INT_CARRY(128) ); ---- End FA stage ---- Begin FA stage FA_130:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(162), DATA_B => INT_CARRY(115), DATA_C => INT_CARRY(116), SAVE => INT_SUM(164), CARRY => INT_CARRY(129) ); ---- End FA stage ---- Begin NO stage INT_SUM(165) <= INT_CARRY(117); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_131:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(163), DATA_B => INT_SUM(164), DATA_C => INT_SUM(165), SAVE => INT_SUM(166), CARRY => INT_CARRY(130) ); ---- End FA stage ---- Begin HA stage HA_23:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(118), DATA_B => INT_CARRY(119), SAVE => INT_SUM(167), CARRY => INT_CARRY(131) ); ---- End HA stage ---- Begin FA stage FA_132:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(120), SAVE => SUM(25), CARRY => CARRY(25) ); ---- End FA stage -- End WT-branch 26 -- Begin WT-branch 27 ---- Begin FA stage FA_133:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197), SAVE => INT_SUM(168), CARRY => INT_CARRY(132) ); ---- End FA stage ---- Begin FA stage FA_134:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200), SAVE => INT_SUM(169), CARRY => INT_CARRY(133) ); ---- End FA stage ---- Begin FA stage FA_135:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203), SAVE => INT_SUM(170), CARRY => INT_CARRY(134) ); ---- End FA stage ---- Begin FA stage FA_136:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206), SAVE => INT_SUM(171), CARRY => INT_CARRY(135) ); ---- End FA stage ---- Begin FA stage FA_137:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209), SAVE => INT_SUM(172), CARRY => INT_CARRY(136) ); ---- End FA stage ---- Begin FA stage FA_138:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(168), DATA_B => INT_SUM(169), DATA_C => INT_SUM(170), SAVE => INT_SUM(173), CARRY => INT_CARRY(137) ); ---- End FA stage ---- Begin FA stage FA_139:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(171), DATA_B => INT_SUM(172), DATA_C => INT_CARRY(121), SAVE => INT_SUM(174), CARRY => INT_CARRY(138) ); ---- End FA stage ---- Begin FA stage FA_140:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(122), DATA_B => INT_CARRY(123), DATA_C => INT_CARRY(124), SAVE => INT_SUM(175), CARRY => INT_CARRY(139) ); ---- End FA stage ---- Begin FA stage FA_141:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(173), DATA_B => INT_SUM(174), DATA_C => INT_SUM(175), SAVE => INT_SUM(176), CARRY => INT_CARRY(140) ); ---- End FA stage ---- Begin FA stage FA_142:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(125), DATA_B => INT_CARRY(126), DATA_C => INT_CARRY(127), SAVE => INT_SUM(177), CARRY => INT_CARRY(141) ); ---- End FA stage ---- Begin FA stage FA_143:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(176), DATA_B => INT_SUM(177), DATA_C => INT_CARRY(128), SAVE => INT_SUM(178), CARRY => INT_CARRY(142) ); ---- End FA stage ---- Begin NO stage INT_SUM(179) <= INT_CARRY(129); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_144:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(178), DATA_B => INT_SUM(179), DATA_C => INT_CARRY(130), SAVE => INT_SUM(180), CARRY => INT_CARRY(143) ); ---- End FA stage ---- Begin NO stage INT_SUM(181) <= INT_CARRY(131); -- At Level 5 ---- End NO stage ---- Begin HA stage HA_24:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), SAVE => SUM(26), CARRY => CARRY(26) ); ---- End HA stage -- End WT-branch 27 -- Begin WT-branch 28 ---- Begin FA stage FA_145:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212), SAVE => INT_SUM(182), CARRY => INT_CARRY(144) ); ---- End FA stage ---- Begin FA stage FA_146:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215), SAVE => INT_SUM(183), CARRY => INT_CARRY(145) ); ---- End FA stage ---- Begin FA stage FA_147:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218), SAVE => INT_SUM(184), CARRY => INT_CARRY(146) ); ---- End FA stage ---- Begin FA stage FA_148:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221), SAVE => INT_SUM(185), CARRY => INT_CARRY(147) ); ---- End FA stage ---- Begin HA stage HA_25:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), SAVE => INT_SUM(186), CARRY => INT_CARRY(148) ); ---- End HA stage ---- Begin FA stage FA_149:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_SUM(184), SAVE => INT_SUM(187), CARRY => INT_CARRY(149) ); ---- End FA stage ---- Begin FA stage FA_150:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_CARRY(132), SAVE => INT_SUM(188), CARRY => INT_CARRY(150) ); ---- End FA stage ---- Begin FA stage FA_151:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135), SAVE => INT_SUM(189), CARRY => INT_CARRY(151) ); ---- End FA stage ---- Begin NO stage INT_SUM(190) <= INT_CARRY(136); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_152:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(187), DATA_B => INT_SUM(188), DATA_C => INT_SUM(189), SAVE => INT_SUM(191), CARRY => INT_CARRY(152) ); ---- End FA stage ---- Begin FA stage FA_153:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(190), DATA_B => INT_CARRY(137), DATA_C => INT_CARRY(138), SAVE => INT_SUM(192), CARRY => INT_CARRY(153) ); ---- End FA stage ---- Begin NO stage INT_SUM(193) <= INT_CARRY(139); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_154:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(191), DATA_B => INT_SUM(192), DATA_C => INT_SUM(193), SAVE => INT_SUM(194), CARRY => INT_CARRY(154) ); ---- End FA stage ---- Begin NO stage INT_SUM(195) <= INT_CARRY(140); -- At Level 4 ---- End NO stage ---- Begin NO stage INT_SUM(196) <= INT_CARRY(141); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_155:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(194), DATA_B => INT_SUM(195), DATA_C => INT_SUM(196), SAVE => INT_SUM(197), CARRY => INT_CARRY(155) ); ---- End FA stage ---- Begin NO stage INT_SUM(198) <= INT_CARRY(142); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_156:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(197), DATA_B => INT_SUM(198), DATA_C => INT_CARRY(143), SAVE => SUM(27), CARRY => CARRY(27) ); ---- End FA stage -- End WT-branch 28 -- Begin WT-branch 29 ---- Begin FA stage FA_157:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(224), DATA_B => SUMMAND(225), DATA_C => SUMMAND(226), SAVE => INT_SUM(199), CARRY => INT_CARRY(156) ); ---- End FA stage ---- Begin FA stage FA_158:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(227), DATA_B => SUMMAND(228), DATA_C => SUMMAND(229), SAVE => INT_SUM(200), CARRY => INT_CARRY(157) ); ---- End FA stage ---- Begin FA stage FA_159:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(230), DATA_B => SUMMAND(231), DATA_C => SUMMAND(232), SAVE => INT_SUM(201), CARRY => INT_CARRY(158) ); ---- End FA stage ---- Begin FA stage FA_160:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(233), DATA_B => SUMMAND(234), DATA_C => SUMMAND(235), SAVE => INT_SUM(202), CARRY => INT_CARRY(159) ); ---- End FA stage ---- Begin FA stage FA_161:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(236), DATA_B => SUMMAND(237), DATA_C => SUMMAND(238), SAVE => INT_SUM(203), CARRY => INT_CARRY(160) ); ---- End FA stage ---- Begin NO stage INT_SUM(204) <= SUMMAND(239); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_162:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(199), DATA_B => INT_SUM(200), DATA_C => INT_SUM(201), SAVE => INT_SUM(205), CARRY => INT_CARRY(161) ); ---- End FA stage ---- Begin FA stage FA_163:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(202), DATA_B => INT_SUM(203), DATA_C => INT_SUM(204), SAVE => INT_SUM(206), CARRY => INT_CARRY(162) ); ---- End FA stage ---- Begin FA stage FA_164:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(144), DATA_B => INT_CARRY(145), DATA_C => INT_CARRY(146), SAVE => INT_SUM(207), CARRY => INT_CARRY(163) ); ---- End FA stage ---- Begin NO stage INT_SUM(208) <= INT_CARRY(147); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(209) <= INT_CARRY(148); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_165:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207), SAVE => INT_SUM(210), CARRY => INT_CARRY(164) ); ---- End FA stage ---- Begin FA stage FA_166:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_CARRY(149), SAVE => INT_SUM(211), CARRY => INT_CARRY(165) ); ---- End FA stage ---- Begin NO stage INT_SUM(212) <= INT_CARRY(150); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(213) <= INT_CARRY(151); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_167:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(210), DATA_B => INT_SUM(211), DATA_C => INT_SUM(212), SAVE => INT_SUM(214), CARRY => INT_CARRY(166) ); ---- End FA stage ---- Begin FA stage FA_168:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(213), DATA_B => INT_CARRY(152), DATA_C => INT_CARRY(153), SAVE => INT_SUM(215), CARRY => INT_CARRY(167) ); ---- End FA stage ---- Begin FA stage FA_169:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(214), DATA_B => INT_SUM(215), DATA_C => INT_CARRY(154), SAVE => INT_SUM(216), CARRY => INT_CARRY(168) ); ---- End FA stage ---- Begin HA stage HA_26:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(216), DATA_B => INT_CARRY(155), SAVE => SUM(28), CARRY => CARRY(28) ); ---- End HA stage -- End WT-branch 29 -- Begin WT-branch 30 ---- Begin FA stage FA_170:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242), SAVE => INT_SUM(217), CARRY => INT_CARRY(169) ); ---- End FA stage ---- Begin FA stage FA_171:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245), SAVE => INT_SUM(218), CARRY => INT_CARRY(170) ); ---- End FA stage ---- Begin FA stage FA_172:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248), SAVE => INT_SUM(219), CARRY => INT_CARRY(171) ); ---- End FA stage ---- Begin FA stage FA_173:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251), SAVE => INT_SUM(220), CARRY => INT_CARRY(172) ); ---- End FA stage ---- Begin FA stage FA_174:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(252), DATA_B => SUMMAND(253), DATA_C => SUMMAND(254), SAVE => INT_SUM(221), CARRY => INT_CARRY(173) ); ---- End FA stage ---- Begin FA stage FA_175:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_SUM(219), SAVE => INT_SUM(222), CARRY => INT_CARRY(174) ); ---- End FA stage ---- Begin FA stage FA_176:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_CARRY(156), SAVE => INT_SUM(223), CARRY => INT_CARRY(175) ); ---- End FA stage ---- Begin FA stage FA_177:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(157), DATA_B => INT_CARRY(158), DATA_C => INT_CARRY(159), SAVE => INT_SUM(224), CARRY => INT_CARRY(176) ); ---- End FA stage ---- Begin NO stage INT_SUM(225) <= INT_CARRY(160); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_178:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(222), DATA_B => INT_SUM(223), DATA_C => INT_SUM(224), SAVE => INT_SUM(226), CARRY => INT_CARRY(177) ); ---- End FA stage ---- Begin FA stage FA_179:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(225), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162), SAVE => INT_SUM(227), CARRY => INT_CARRY(178) ); ---- End FA stage ---- Begin NO stage INT_SUM(228) <= INT_CARRY(163); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_180:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_SUM(228), SAVE => INT_SUM(229), CARRY => INT_CARRY(179) ); ---- End FA stage ---- Begin HA stage HA_27:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(164), DATA_B => INT_CARRY(165), SAVE => INT_SUM(230), CARRY => INT_CARRY(180) ); ---- End HA stage ---- Begin FA stage FA_181:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(229), DATA_B => INT_SUM(230), DATA_C => INT_CARRY(166), SAVE => INT_SUM(231), CARRY => INT_CARRY(181) ); ---- End FA stage ---- Begin NO stage INT_SUM(232) <= INT_CARRY(167); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_182:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(231), DATA_B => INT_SUM(232), DATA_C => INT_CARRY(168), SAVE => SUM(29), CARRY => CARRY(29) ); ---- End FA stage -- End WT-branch 30 -- Begin WT-branch 31 ---- Begin FA stage FA_183:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(255), DATA_B => SUMMAND(256), DATA_C => SUMMAND(257), SAVE => INT_SUM(233), CARRY => INT_CARRY(182) ); ---- End FA stage ---- Begin FA stage FA_184:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(258), DATA_B => SUMMAND(259), DATA_C => SUMMAND(260), SAVE => INT_SUM(234), CARRY => INT_CARRY(183) ); ---- End FA stage ---- Begin FA stage FA_185:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(261), DATA_B => SUMMAND(262), DATA_C => SUMMAND(263), SAVE => INT_SUM(235), CARRY => INT_CARRY(184) ); ---- End FA stage ---- Begin FA stage FA_186:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(264), DATA_B => SUMMAND(265), DATA_C => SUMMAND(266), SAVE => INT_SUM(236), CARRY => INT_CARRY(185) ); ---- End FA stage ---- Begin FA stage FA_187:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(267), DATA_B => SUMMAND(268), DATA_C => SUMMAND(269), SAVE => INT_SUM(237), CARRY => INT_CARRY(186) ); ---- End FA stage ---- Begin NO stage INT_SUM(238) <= SUMMAND(270); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(239) <= SUMMAND(271); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_188:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(233), DATA_B => INT_SUM(234), DATA_C => INT_SUM(235), SAVE => INT_SUM(240), CARRY => INT_CARRY(187) ); ---- End FA stage ---- Begin FA stage FA_189:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_SUM(238), SAVE => INT_SUM(241), CARRY => INT_CARRY(188) ); ---- End FA stage ---- Begin FA stage FA_190:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(239), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170), SAVE => INT_SUM(242), CARRY => INT_CARRY(189) ); ---- End FA stage ---- Begin FA stage FA_191:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(171), DATA_B => INT_CARRY(172), DATA_C => INT_CARRY(173), SAVE => INT_SUM(243), CARRY => INT_CARRY(190) ); ---- End FA stage ---- Begin FA stage FA_192:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(240), DATA_B => INT_SUM(241), DATA_C => INT_SUM(242), SAVE => INT_SUM(244), CARRY => INT_CARRY(191) ); ---- End FA stage ---- Begin FA stage FA_193:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(243), DATA_B => INT_CARRY(174), DATA_C => INT_CARRY(175), SAVE => INT_SUM(245), CARRY => INT_CARRY(192) ); ---- End FA stage ---- Begin NO stage INT_SUM(246) <= INT_CARRY(176); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_194:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(244), DATA_B => INT_SUM(245), DATA_C => INT_SUM(246), SAVE => INT_SUM(247), CARRY => INT_CARRY(193) ); ---- End FA stage ---- Begin HA stage HA_28:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(177), DATA_B => INT_CARRY(178), SAVE => INT_SUM(248), CARRY => INT_CARRY(194) ); ---- End HA stage ---- Begin FA stage FA_195:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(247), DATA_B => INT_SUM(248), DATA_C => INT_CARRY(179), SAVE => INT_SUM(249), CARRY => INT_CARRY(195) ); ---- End FA stage ---- Begin NO stage INT_SUM(250) <= INT_CARRY(180); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_196:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(249), DATA_B => INT_SUM(250), DATA_C => INT_CARRY(181), SAVE => SUM(30), CARRY => CARRY(30) ); ---- End FA stage -- End WT-branch 31 -- Begin WT-branch 32 ---- Begin FA stage FA_197:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(272), DATA_B => SUMMAND(273), DATA_C => SUMMAND(274), SAVE => INT_SUM(251), CARRY => INT_CARRY(196) ); ---- End FA stage ---- Begin FA stage FA_198:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(275), DATA_B => SUMMAND(276), DATA_C => SUMMAND(277), SAVE => INT_SUM(252), CARRY => INT_CARRY(197) ); ---- End FA stage ---- Begin FA stage FA_199:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280), SAVE => INT_SUM(253), CARRY => INT_CARRY(198) ); ---- End FA stage ---- Begin FA stage FA_200:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283), SAVE => INT_SUM(254), CARRY => INT_CARRY(199) ); ---- End FA stage ---- Begin FA stage FA_201:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(284), DATA_B => SUMMAND(285), DATA_C => SUMMAND(286), SAVE => INT_SUM(255), CARRY => INT_CARRY(200) ); ---- End FA stage ---- Begin NO stage INT_SUM(256) <= SUMMAND(287); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_202:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(251), DATA_B => INT_SUM(252), DATA_C => INT_SUM(253), SAVE => INT_SUM(257), CARRY => INT_CARRY(201) ); ---- End FA stage ---- Begin FA stage FA_203:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_SUM(256), SAVE => INT_SUM(258), CARRY => INT_CARRY(202) ); ---- End FA stage ---- Begin FA stage FA_204:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(182), DATA_B => INT_CARRY(183), DATA_C => INT_CARRY(184), SAVE => INT_SUM(259), CARRY => INT_CARRY(203) ); ---- End FA stage ---- Begin NO stage INT_SUM(260) <= INT_CARRY(185); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(261) <= INT_CARRY(186); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_205:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(257), DATA_B => INT_SUM(258), DATA_C => INT_SUM(259), SAVE => INT_SUM(262), CARRY => INT_CARRY(204) ); ---- End FA stage ---- Begin FA stage FA_206:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(187), SAVE => INT_SUM(263), CARRY => INT_CARRY(205) ); ---- End FA stage ---- Begin FA stage FA_207:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190), SAVE => INT_SUM(264), CARRY => INT_CARRY(206) ); ---- End FA stage ---- Begin FA stage FA_208:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(262), DATA_B => INT_SUM(263), DATA_C => INT_SUM(264), SAVE => INT_SUM(265), CARRY => INT_CARRY(207) ); ---- End FA stage ---- Begin HA stage HA_29:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(191), DATA_B => INT_CARRY(192), SAVE => INT_SUM(266), CARRY => INT_CARRY(208) ); ---- End HA stage ---- Begin FA stage FA_209:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(193), SAVE => INT_SUM(267), CARRY => INT_CARRY(209) ); ---- End FA stage ---- Begin NO stage INT_SUM(268) <= INT_CARRY(194); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_210:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(267), DATA_B => INT_SUM(268), DATA_C => INT_CARRY(195), SAVE => SUM(31), CARRY => CARRY(31) ); ---- End FA stage -- End WT-branch 32 -- Begin WT-branch 33 ---- Begin FA stage FA_211:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290), SAVE => INT_SUM(269), CARRY => INT_CARRY(210) ); ---- End FA stage ---- Begin FA stage FA_212:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(291), DATA_B => SUMMAND(292), DATA_C => SUMMAND(293), SAVE => INT_SUM(270), CARRY => INT_CARRY(211) ); ---- End FA stage ---- Begin FA stage FA_213:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(294), DATA_B => SUMMAND(295), DATA_C => SUMMAND(296), SAVE => INT_SUM(271), CARRY => INT_CARRY(212) ); ---- End FA stage ---- Begin FA stage FA_214:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(297), DATA_B => SUMMAND(298), DATA_C => SUMMAND(299), SAVE => INT_SUM(272), CARRY => INT_CARRY(213) ); ---- End FA stage ---- Begin FA stage FA_215:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(300), DATA_B => SUMMAND(301), DATA_C => SUMMAND(302), SAVE => INT_SUM(273), CARRY => INT_CARRY(214) ); ---- End FA stage ---- Begin FA stage FA_216:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(303), DATA_B => SUMMAND(304), DATA_C => SUMMAND(305), SAVE => INT_SUM(274), CARRY => INT_CARRY(215) ); ---- End FA stage ---- Begin FA stage FA_217:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(269), DATA_B => INT_SUM(270), DATA_C => INT_SUM(271), SAVE => INT_SUM(275), CARRY => INT_CARRY(216) ); ---- End FA stage ---- Begin FA stage FA_218:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(272), DATA_B => INT_SUM(273), DATA_C => INT_SUM(274), SAVE => INT_SUM(276), CARRY => INT_CARRY(217) ); ---- End FA stage ---- Begin FA stage FA_219:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(196), DATA_B => INT_CARRY(197), DATA_C => INT_CARRY(198), SAVE => INT_SUM(277), CARRY => INT_CARRY(218) ); ---- End FA stage ---- Begin HA stage HA_30:HALF_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(199), DATA_B => INT_CARRY(200), SAVE => INT_SUM(278), CARRY => INT_CARRY(219) ); ---- End HA stage ---- Begin FA stage FA_220:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(275), DATA_B => INT_SUM(276), DATA_C => INT_SUM(277), SAVE => INT_SUM(279), CARRY => INT_CARRY(220) ); ---- End FA stage ---- Begin FA stage FA_221:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(278), DATA_B => INT_CARRY(201), DATA_C => INT_CARRY(202), SAVE => INT_SUM(280), CARRY => INT_CARRY(221) ); ---- End FA stage ---- Begin NO stage INT_SUM(281) <= INT_CARRY(203); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_222:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(279), DATA_B => INT_SUM(280), DATA_C => INT_SUM(281), SAVE => INT_SUM(282), CARRY => INT_CARRY(222) ); ---- End FA stage ---- Begin FA stage FA_223:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(204), DATA_B => INT_CARRY(205), DATA_C => INT_CARRY(206), SAVE => INT_SUM(283), CARRY => INT_CARRY(223) ); ---- End FA stage ---- Begin FA stage FA_224:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(282), DATA_B => INT_SUM(283), DATA_C => INT_CARRY(207), SAVE => INT_SUM(284), CARRY => INT_CARRY(224) ); ---- End FA stage ---- Begin NO stage INT_SUM(285) <= INT_CARRY(208); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_225:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(284), DATA_B => INT_SUM(285), DATA_C => INT_CARRY(209), SAVE => SUM(32), CARRY => CARRY(32) ); ---- End FA stage -- End WT-branch 33 -- Begin WT-branch 34 ---- Begin FA stage FA_226:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(306), DATA_B => SUMMAND(307), DATA_C => SUMMAND(308), SAVE => INT_SUM(286), CARRY => INT_CARRY(225) ); ---- End FA stage ---- Begin FA stage FA_227:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311), SAVE => INT_SUM(287), CARRY => INT_CARRY(226) ); ---- End FA stage ---- Begin FA stage FA_228:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), DATA_C => SUMMAND(314), SAVE => INT_SUM(288), CARRY => INT_CARRY(227) ); ---- End FA stage ---- Begin FA stage FA_229:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(315), DATA_B => SUMMAND(316), DATA_C => SUMMAND(317), SAVE => INT_SUM(289), CARRY => INT_CARRY(228) ); ---- End FA stage ---- Begin FA stage FA_230:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320), SAVE => INT_SUM(290), CARRY => INT_CARRY(229) ); ---- End FA stage ---- Begin NO stage INT_SUM(291) <= SUMMAND(321); -- At Level 1 ---- End NO stage ---- Begin NO stage INT_SUM(292) <= SUMMAND(322); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_231:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(286), DATA_B => INT_SUM(287), DATA_C => INT_SUM(288), SAVE => INT_SUM(293), CARRY => INT_CARRY(230) ); ---- End FA stage ---- Begin FA stage FA_232:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(289), DATA_B => INT_SUM(290), DATA_C => INT_SUM(291), SAVE => INT_SUM(294), CARRY => INT_CARRY(231) ); ---- End FA stage ---- Begin FA stage FA_233:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(292), DATA_B => INT_CARRY(210), DATA_C => INT_CARRY(211), SAVE => INT_SUM(295), CARRY => INT_CARRY(232) ); ---- End FA stage ---- Begin FA stage FA_234:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(212), DATA_B => INT_CARRY(213), DATA_C => INT_CARRY(214), SAVE => INT_SUM(296), CARRY => INT_CARRY(233) ); ---- End FA stage ---- Begin NO stage INT_SUM(297) <= INT_CARRY(215); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_235:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(293), DATA_B => INT_SUM(294), DATA_C => INT_SUM(295), SAVE => INT_SUM(298), CARRY => INT_CARRY(234) ); ---- End FA stage ---- Begin FA stage FA_236:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(296), DATA_B => INT_SUM(297), DATA_C => INT_CARRY(216), SAVE => INT_SUM(299), CARRY => INT_CARRY(235) ); ---- End FA stage ---- Begin FA stage FA_237:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(217), DATA_B => INT_CARRY(218), DATA_C => INT_CARRY(219), SAVE => INT_SUM(300), CARRY => INT_CARRY(236) ); ---- End FA stage ---- Begin FA stage FA_238:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(298), DATA_B => INT_SUM(299), DATA_C => INT_SUM(300), SAVE => INT_SUM(301), CARRY => INT_CARRY(237) ); ---- End FA stage ---- Begin HA stage HA_31:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(220), DATA_B => INT_CARRY(221), SAVE => INT_SUM(302), CARRY => INT_CARRY(238) ); ---- End HA stage ---- Begin FA stage FA_239:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(301), DATA_B => INT_SUM(302), DATA_C => INT_CARRY(222), SAVE => INT_SUM(303), CARRY => INT_CARRY(239) ); ---- End FA stage ---- Begin NO stage INT_SUM(304) <= INT_CARRY(223); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_240:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(303), DATA_B => INT_SUM(304), DATA_C => INT_CARRY(224), SAVE => SUM(33), CARRY => CARRY(33) ); ---- End FA stage -- End WT-branch 34 -- Begin WT-branch 35 ---- Begin FA stage FA_241:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(323), DATA_B => SUMMAND(324), DATA_C => SUMMAND(325), SAVE => INT_SUM(305), CARRY => INT_CARRY(240) ); ---- End FA stage ---- Begin FA stage FA_242:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(326), DATA_B => SUMMAND(327), DATA_C => SUMMAND(328), SAVE => INT_SUM(306), CARRY => INT_CARRY(241) ); ---- End FA stage ---- Begin FA stage FA_243:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(329), DATA_B => SUMMAND(330), DATA_C => SUMMAND(331), SAVE => INT_SUM(307), CARRY => INT_CARRY(242) ); ---- End FA stage ---- Begin FA stage FA_244:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(332), DATA_B => SUMMAND(333), DATA_C => SUMMAND(334), SAVE => INT_SUM(308), CARRY => INT_CARRY(243) ); ---- End FA stage ---- Begin FA stage FA_245:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(335), DATA_B => SUMMAND(336), DATA_C => SUMMAND(337), SAVE => INT_SUM(309), CARRY => INT_CARRY(244) ); ---- End FA stage ---- Begin FA stage FA_246:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(338), DATA_B => SUMMAND(339), DATA_C => SUMMAND(340), SAVE => INT_SUM(310), CARRY => INT_CARRY(245) ); ---- End FA stage ---- Begin FA stage FA_247:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(305), DATA_B => INT_SUM(306), DATA_C => INT_SUM(307), SAVE => INT_SUM(311), CARRY => INT_CARRY(246) ); ---- End FA stage ---- Begin FA stage FA_248:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(308), DATA_B => INT_SUM(309), DATA_C => INT_SUM(310), SAVE => INT_SUM(312), CARRY => INT_CARRY(247) ); ---- End FA stage ---- Begin FA stage FA_249:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(225), DATA_B => INT_CARRY(226), DATA_C => INT_CARRY(227), SAVE => INT_SUM(313), CARRY => INT_CARRY(248) ); ---- End FA stage ---- Begin NO stage INT_SUM(314) <= INT_CARRY(228); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(315) <= INT_CARRY(229); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_250:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(311), DATA_B => INT_SUM(312), DATA_C => INT_SUM(313), SAVE => INT_SUM(316), CARRY => INT_CARRY(249) ); ---- End FA stage ---- Begin FA stage FA_251:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(314), DATA_B => INT_SUM(315), DATA_C => INT_CARRY(230), SAVE => INT_SUM(317), CARRY => INT_CARRY(250) ); ---- End FA stage ---- Begin FA stage FA_252:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(231), DATA_B => INT_CARRY(232), DATA_C => INT_CARRY(233), SAVE => INT_SUM(318), CARRY => INT_CARRY(251) ); ---- End FA stage ---- Begin FA stage FA_253:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(316), DATA_B => INT_SUM(317), DATA_C => INT_SUM(318), SAVE => INT_SUM(319), CARRY => INT_CARRY(252) ); ---- End FA stage ---- Begin FA stage FA_254:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(234), DATA_B => INT_CARRY(235), DATA_C => INT_CARRY(236), SAVE => INT_SUM(320), CARRY => INT_CARRY(253) ); ---- End FA stage ---- Begin FA stage FA_255:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(319), DATA_B => INT_SUM(320), DATA_C => INT_CARRY(237), SAVE => INT_SUM(321), CARRY => INT_CARRY(254) ); ---- End FA stage ---- Begin NO stage INT_SUM(322) <= INT_CARRY(238); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_256:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(321), DATA_B => INT_SUM(322), DATA_C => INT_CARRY(239), SAVE => SUM(34), CARRY => CARRY(34) ); ---- End FA stage -- End WT-branch 35 -- Begin WT-branch 36 ---- Begin FA stage FA_257:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(341), DATA_B => SUMMAND(342), DATA_C => SUMMAND(343), SAVE => INT_SUM(323), CARRY => INT_CARRY(255) ); ---- End FA stage ---- Begin FA stage FA_258:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(344), DATA_B => SUMMAND(345), DATA_C => SUMMAND(346), SAVE => INT_SUM(324), CARRY => INT_CARRY(256) ); ---- End FA stage ---- Begin FA stage FA_259:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(347), DATA_B => SUMMAND(348), DATA_C => SUMMAND(349), SAVE => INT_SUM(325), CARRY => INT_CARRY(257) ); ---- End FA stage ---- Begin FA stage FA_260:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(350), DATA_B => SUMMAND(351), DATA_C => SUMMAND(352), SAVE => INT_SUM(326), CARRY => INT_CARRY(258) ); ---- End FA stage ---- Begin FA stage FA_261:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(353), DATA_B => SUMMAND(354), DATA_C => SUMMAND(355), SAVE => INT_SUM(327), CARRY => INT_CARRY(259) ); ---- End FA stage ---- Begin HA stage HA_32:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(356), DATA_B => SUMMAND(357), SAVE => INT_SUM(328), CARRY => INT_CARRY(260) ); ---- End HA stage ---- Begin FA stage FA_262:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(323), DATA_B => INT_SUM(324), DATA_C => INT_SUM(325), SAVE => INT_SUM(329), CARRY => INT_CARRY(261) ); ---- End FA stage ---- Begin FA stage FA_263:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(326), DATA_B => INT_SUM(327), DATA_C => INT_SUM(328), SAVE => INT_SUM(330), CARRY => INT_CARRY(262) ); ---- End FA stage ---- Begin FA stage FA_264:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(240), DATA_B => INT_CARRY(241), DATA_C => INT_CARRY(242), SAVE => INT_SUM(331), CARRY => INT_CARRY(263) ); ---- End FA stage ---- Begin FA stage FA_265:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(243), DATA_B => INT_CARRY(244), DATA_C => INT_CARRY(245), SAVE => INT_SUM(332), CARRY => INT_CARRY(264) ); ---- End FA stage ---- Begin FA stage FA_266:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(329), DATA_B => INT_SUM(330), DATA_C => INT_SUM(331), SAVE => INT_SUM(333), CARRY => INT_CARRY(265) ); ---- End FA stage ---- Begin FA stage FA_267:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(332), DATA_B => INT_CARRY(246), DATA_C => INT_CARRY(247), SAVE => INT_SUM(334), CARRY => INT_CARRY(266) ); ---- End FA stage ---- Begin NO stage INT_SUM(335) <= INT_CARRY(248); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_268:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(333), DATA_B => INT_SUM(334), DATA_C => INT_SUM(335), SAVE => INT_SUM(336), CARRY => INT_CARRY(267) ); ---- End FA stage ---- Begin FA stage FA_269:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(249), DATA_B => INT_CARRY(250), DATA_C => INT_CARRY(251), SAVE => INT_SUM(337), CARRY => INT_CARRY(268) ); ---- End FA stage ---- Begin FA stage FA_270:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(336), DATA_B => INT_SUM(337), DATA_C => INT_CARRY(252), SAVE => INT_SUM(338), CARRY => INT_CARRY(269) ); ---- End FA stage ---- Begin NO stage INT_SUM(339) <= INT_CARRY(253); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_271:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(338), DATA_B => INT_SUM(339), DATA_C => INT_CARRY(254), SAVE => SUM(35), CARRY => CARRY(35) ); ---- End FA stage -- End WT-branch 36 -- Begin WT-branch 37 ---- Begin FA stage FA_272:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(358), DATA_B => SUMMAND(359), DATA_C => SUMMAND(360), SAVE => INT_SUM(340), CARRY => INT_CARRY(270) ); ---- End FA stage ---- Begin FA stage FA_273:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(361), DATA_B => SUMMAND(362), DATA_C => SUMMAND(363), SAVE => INT_SUM(341), CARRY => INT_CARRY(271) ); ---- End FA stage ---- Begin FA stage FA_274:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(364), DATA_B => SUMMAND(365), DATA_C => SUMMAND(366), SAVE => INT_SUM(342), CARRY => INT_CARRY(272) ); ---- End FA stage ---- Begin FA stage FA_275:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(367), DATA_B => SUMMAND(368), DATA_C => SUMMAND(369), SAVE => INT_SUM(343), CARRY => INT_CARRY(273) ); ---- End FA stage ---- Begin FA stage FA_276:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(370), DATA_B => SUMMAND(371), DATA_C => SUMMAND(372), SAVE => INT_SUM(344), CARRY => INT_CARRY(274) ); ---- End FA stage ---- Begin NO stage INT_SUM(345) <= SUMMAND(373); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_277:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(340), DATA_B => INT_SUM(341), DATA_C => INT_SUM(342), SAVE => INT_SUM(346), CARRY => INT_CARRY(275) ); ---- End FA stage ---- Begin FA stage FA_278:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(343), DATA_B => INT_SUM(344), DATA_C => INT_SUM(345), SAVE => INT_SUM(347), CARRY => INT_CARRY(276) ); ---- End FA stage ---- Begin FA stage FA_279:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(255), DATA_B => INT_CARRY(256), DATA_C => INT_CARRY(257), SAVE => INT_SUM(348), CARRY => INT_CARRY(277) ); ---- End FA stage ---- Begin FA stage FA_280:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(258), DATA_B => INT_CARRY(259), DATA_C => INT_CARRY(260), SAVE => INT_SUM(349), CARRY => INT_CARRY(278) ); ---- End FA stage ---- Begin FA stage FA_281:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(346), DATA_B => INT_SUM(347), DATA_C => INT_SUM(348), SAVE => INT_SUM(350), CARRY => INT_CARRY(279) ); ---- End FA stage ---- Begin FA stage FA_282:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(349), DATA_B => INT_CARRY(261), DATA_C => INT_CARRY(262), SAVE => INT_SUM(351), CARRY => INT_CARRY(280) ); ---- End FA stage ---- Begin NO stage INT_SUM(352) <= INT_CARRY(263); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(353) <= INT_CARRY(264); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_283:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(350), DATA_B => INT_SUM(351), DATA_C => INT_SUM(352), SAVE => INT_SUM(354), CARRY => INT_CARRY(281) ); ---- End FA stage ---- Begin FA stage FA_284:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(353), DATA_B => INT_CARRY(265), DATA_C => INT_CARRY(266), SAVE => INT_SUM(355), CARRY => INT_CARRY(282) ); ---- End FA stage ---- Begin FA stage FA_285:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(354), DATA_B => INT_SUM(355), DATA_C => INT_CARRY(267), SAVE => INT_SUM(356), CARRY => INT_CARRY(283) ); ---- End FA stage ---- Begin NO stage INT_SUM(357) <= INT_CARRY(268); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_286:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(356), DATA_B => INT_SUM(357), DATA_C => INT_CARRY(269), SAVE => SUM(36), CARRY => CARRY(36) ); ---- End FA stage -- End WT-branch 37 -- Begin WT-branch 38 ---- Begin FA stage FA_287:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(374), DATA_B => SUMMAND(375), DATA_C => SUMMAND(376), SAVE => INT_SUM(358), CARRY => INT_CARRY(284) ); ---- End FA stage ---- Begin FA stage FA_288:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(377), DATA_B => SUMMAND(378), DATA_C => SUMMAND(379), SAVE => INT_SUM(359), CARRY => INT_CARRY(285) ); ---- End FA stage ---- Begin FA stage FA_289:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(380), DATA_B => SUMMAND(381), DATA_C => SUMMAND(382), SAVE => INT_SUM(360), CARRY => INT_CARRY(286) ); ---- End FA stage ---- Begin FA stage FA_290:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(383), DATA_B => SUMMAND(384), DATA_C => SUMMAND(385), SAVE => INT_SUM(361), CARRY => INT_CARRY(287) ); ---- End FA stage ---- Begin FA stage FA_291:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(386), DATA_B => SUMMAND(387), DATA_C => SUMMAND(388), SAVE => INT_SUM(362), CARRY => INT_CARRY(288) ); ---- End FA stage ---- Begin NO stage INT_SUM(363) <= SUMMAND(389); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_292:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(358), DATA_B => INT_SUM(359), DATA_C => INT_SUM(360), SAVE => INT_SUM(364), CARRY => INT_CARRY(289) ); ---- End FA stage ---- Begin FA stage FA_293:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(361), DATA_B => INT_SUM(362), DATA_C => INT_SUM(363), SAVE => INT_SUM(365), CARRY => INT_CARRY(290) ); ---- End FA stage ---- Begin FA stage FA_294:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(270), DATA_B => INT_CARRY(271), DATA_C => INT_CARRY(272), SAVE => INT_SUM(366), CARRY => INT_CARRY(291) ); ---- End FA stage ---- Begin NO stage INT_SUM(367) <= INT_CARRY(273); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(368) <= INT_CARRY(274); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_295:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(364), DATA_B => INT_SUM(365), DATA_C => INT_SUM(366), SAVE => INT_SUM(369), CARRY => INT_CARRY(292) ); ---- End FA stage ---- Begin FA stage FA_296:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(367), DATA_B => INT_SUM(368), DATA_C => INT_CARRY(275), SAVE => INT_SUM(370), CARRY => INT_CARRY(293) ); ---- End FA stage ---- Begin FA stage FA_297:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(276), DATA_B => INT_CARRY(277), DATA_C => INT_CARRY(278), SAVE => INT_SUM(371), CARRY => INT_CARRY(294) ); ---- End FA stage ---- Begin FA stage FA_298:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(369), DATA_B => INT_SUM(370), DATA_C => INT_SUM(371), SAVE => INT_SUM(372), CARRY => INT_CARRY(295) ); ---- End FA stage ---- Begin HA stage HA_33:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(279), DATA_B => INT_CARRY(280), SAVE => INT_SUM(373), CARRY => INT_CARRY(296) ); ---- End HA stage ---- Begin FA stage FA_299:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(372), DATA_B => INT_SUM(373), DATA_C => INT_CARRY(281), SAVE => INT_SUM(374), CARRY => INT_CARRY(297) ); ---- End FA stage ---- Begin NO stage INT_SUM(375) <= INT_CARRY(282); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_300:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(374), DATA_B => INT_SUM(375), DATA_C => INT_CARRY(283), SAVE => SUM(37), CARRY => CARRY(37) ); ---- End FA stage -- End WT-branch 38 -- Begin WT-branch 39 ---- Begin FA stage FA_301:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(390), DATA_B => SUMMAND(391), DATA_C => SUMMAND(392), SAVE => INT_SUM(376), CARRY => INT_CARRY(298) ); ---- End FA stage ---- Begin FA stage FA_302:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(393), DATA_B => SUMMAND(394), DATA_C => SUMMAND(395), SAVE => INT_SUM(377), CARRY => INT_CARRY(299) ); ---- End FA stage ---- Begin FA stage FA_303:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(396), DATA_B => SUMMAND(397), DATA_C => SUMMAND(398), SAVE => INT_SUM(378), CARRY => INT_CARRY(300) ); ---- End FA stage ---- Begin FA stage FA_304:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(399), DATA_B => SUMMAND(400), DATA_C => SUMMAND(401), SAVE => INT_SUM(379), CARRY => INT_CARRY(301) ); ---- End FA stage ---- Begin FA stage FA_305:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(402), DATA_B => SUMMAND(403), DATA_C => SUMMAND(404), SAVE => INT_SUM(380), CARRY => INT_CARRY(302) ); ---- End FA stage ---- Begin FA stage FA_306:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(376), DATA_B => INT_SUM(377), DATA_C => INT_SUM(378), SAVE => INT_SUM(381), CARRY => INT_CARRY(303) ); ---- End FA stage ---- Begin FA stage FA_307:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(379), DATA_B => INT_SUM(380), DATA_C => INT_CARRY(284), SAVE => INT_SUM(382), CARRY => INT_CARRY(304) ); ---- End FA stage ---- Begin FA stage FA_308:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(285), DATA_B => INT_CARRY(286), DATA_C => INT_CARRY(287), SAVE => INT_SUM(383), CARRY => INT_CARRY(305) ); ---- End FA stage ---- Begin NO stage INT_SUM(384) <= INT_CARRY(288); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_309:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(381), DATA_B => INT_SUM(382), DATA_C => INT_SUM(383), SAVE => INT_SUM(385), CARRY => INT_CARRY(306) ); ---- End FA stage ---- Begin FA stage FA_310:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(384), DATA_B => INT_CARRY(289), DATA_C => INT_CARRY(290), SAVE => INT_SUM(386), CARRY => INT_CARRY(307) ); ---- End FA stage ---- Begin NO stage INT_SUM(387) <= INT_CARRY(291); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_311:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(385), DATA_B => INT_SUM(386), DATA_C => INT_SUM(387), SAVE => INT_SUM(388), CARRY => INT_CARRY(308) ); ---- End FA stage ---- Begin FA stage FA_312:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(292), DATA_B => INT_CARRY(293), DATA_C => INT_CARRY(294), SAVE => INT_SUM(389), CARRY => INT_CARRY(309) ); ---- End FA stage ---- Begin FA stage FA_313:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(388), DATA_B => INT_SUM(389), DATA_C => INT_CARRY(295), SAVE => INT_SUM(390), CARRY => INT_CARRY(310) ); ---- End FA stage ---- Begin NO stage INT_SUM(391) <= INT_CARRY(296); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_314:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(390), DATA_B => INT_SUM(391), DATA_C => INT_CARRY(297), SAVE => SUM(38), CARRY => CARRY(38) ); ---- End FA stage -- End WT-branch 39 -- Begin WT-branch 40 ---- Begin FA stage FA_315:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(405), DATA_B => SUMMAND(406), DATA_C => SUMMAND(407), SAVE => INT_SUM(392), CARRY => INT_CARRY(311) ); ---- End FA stage ---- Begin FA stage FA_316:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(408), DATA_B => SUMMAND(409), DATA_C => SUMMAND(410), SAVE => INT_SUM(393), CARRY => INT_CARRY(312) ); ---- End FA stage ---- Begin FA stage FA_317:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(411), DATA_B => SUMMAND(412), DATA_C => SUMMAND(413), SAVE => INT_SUM(394), CARRY => INT_CARRY(313) ); ---- End FA stage ---- Begin FA stage FA_318:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(414), DATA_B => SUMMAND(415), DATA_C => SUMMAND(416), SAVE => INT_SUM(395), CARRY => INT_CARRY(314) ); ---- End FA stage ---- Begin FA stage FA_319:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(417), DATA_B => SUMMAND(418), DATA_C => SUMMAND(419), SAVE => INT_SUM(396), CARRY => INT_CARRY(315) ); ---- End FA stage ---- Begin FA stage FA_320:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(392), DATA_B => INT_SUM(393), DATA_C => INT_SUM(394), SAVE => INT_SUM(397), CARRY => INT_CARRY(316) ); ---- End FA stage ---- Begin FA stage FA_321:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(395), DATA_B => INT_SUM(396), DATA_C => INT_CARRY(298), SAVE => INT_SUM(398), CARRY => INT_CARRY(317) ); ---- End FA stage ---- Begin FA stage FA_322:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(299), DATA_B => INT_CARRY(300), DATA_C => INT_CARRY(301), SAVE => INT_SUM(399), CARRY => INT_CARRY(318) ); ---- End FA stage ---- Begin NO stage INT_SUM(400) <= INT_CARRY(302); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_323:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(397), DATA_B => INT_SUM(398), DATA_C => INT_SUM(399), SAVE => INT_SUM(401), CARRY => INT_CARRY(319) ); ---- End FA stage ---- Begin FA stage FA_324:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(400), DATA_B => INT_CARRY(303), DATA_C => INT_CARRY(304), SAVE => INT_SUM(402), CARRY => INT_CARRY(320) ); ---- End FA stage ---- Begin NO stage INT_SUM(403) <= INT_CARRY(305); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_325:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(401), DATA_B => INT_SUM(402), DATA_C => INT_SUM(403), SAVE => INT_SUM(404), CARRY => INT_CARRY(321) ); ---- End FA stage ---- Begin HA stage HA_34:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(306), DATA_B => INT_CARRY(307), SAVE => INT_SUM(405), CARRY => INT_CARRY(322) ); ---- End HA stage ---- Begin FA stage FA_326:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(404), DATA_B => INT_SUM(405), DATA_C => INT_CARRY(308), SAVE => INT_SUM(406), CARRY => INT_CARRY(323) ); ---- End FA stage ---- Begin NO stage INT_SUM(407) <= INT_CARRY(309); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_327:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(406), DATA_B => INT_SUM(407), DATA_C => INT_CARRY(310), SAVE => SUM(39), CARRY => CARRY(39) ); ---- End FA stage -- End WT-branch 40 -- Begin WT-branch 41 ---- Begin FA stage FA_328:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(420), DATA_B => SUMMAND(421), DATA_C => SUMMAND(422), SAVE => INT_SUM(408), CARRY => INT_CARRY(324) ); ---- End FA stage ---- Begin FA stage FA_329:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(423), DATA_B => SUMMAND(424), DATA_C => SUMMAND(425), SAVE => INT_SUM(409), CARRY => INT_CARRY(325) ); ---- End FA stage ---- Begin FA stage FA_330:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(426), DATA_B => SUMMAND(427), DATA_C => SUMMAND(428), SAVE => INT_SUM(410), CARRY => INT_CARRY(326) ); ---- End FA stage ---- Begin FA stage FA_331:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(429), DATA_B => SUMMAND(430), DATA_C => SUMMAND(431), SAVE => INT_SUM(411), CARRY => INT_CARRY(327) ); ---- End FA stage ---- Begin HA stage HA_35:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(432), DATA_B => SUMMAND(433), SAVE => INT_SUM(412), CARRY => INT_CARRY(328) ); ---- End HA stage ---- Begin FA stage FA_332:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(408), DATA_B => INT_SUM(409), DATA_C => INT_SUM(410), SAVE => INT_SUM(413), CARRY => INT_CARRY(329) ); ---- End FA stage ---- Begin FA stage FA_333:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(411), DATA_B => INT_SUM(412), DATA_C => INT_CARRY(311), SAVE => INT_SUM(414), CARRY => INT_CARRY(330) ); ---- End FA stage ---- Begin FA stage FA_334:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(312), DATA_B => INT_CARRY(313), DATA_C => INT_CARRY(314), SAVE => INT_SUM(415), CARRY => INT_CARRY(331) ); ---- End FA stage ---- Begin NO stage INT_SUM(416) <= INT_CARRY(315); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_335:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(413), DATA_B => INT_SUM(414), DATA_C => INT_SUM(415), SAVE => INT_SUM(417), CARRY => INT_CARRY(332) ); ---- End FA stage ---- Begin FA stage FA_336:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(416), DATA_B => INT_CARRY(316), DATA_C => INT_CARRY(317), SAVE => INT_SUM(418), CARRY => INT_CARRY(333) ); ---- End FA stage ---- Begin NO stage INT_SUM(419) <= INT_CARRY(318); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_337:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(417), DATA_B => INT_SUM(418), DATA_C => INT_SUM(419), SAVE => INT_SUM(420), CARRY => INT_CARRY(334) ); ---- End FA stage ---- Begin HA stage HA_36:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(319), DATA_B => INT_CARRY(320), SAVE => INT_SUM(421), CARRY => INT_CARRY(335) ); ---- End HA stage ---- Begin FA stage FA_338:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(420), DATA_B => INT_SUM(421), DATA_C => INT_CARRY(321), SAVE => INT_SUM(422), CARRY => INT_CARRY(336) ); ---- End FA stage ---- Begin NO stage INT_SUM(423) <= INT_CARRY(322); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_339:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(422), DATA_B => INT_SUM(423), DATA_C => INT_CARRY(323), SAVE => SUM(40), CARRY => CARRY(40) ); ---- End FA stage -- End WT-branch 41 -- Begin WT-branch 42 ---- Begin FA stage FA_340:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(434), DATA_B => SUMMAND(435), DATA_C => SUMMAND(436), SAVE => INT_SUM(424), CARRY => INT_CARRY(337) ); ---- End FA stage ---- Begin FA stage FA_341:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(437), DATA_B => SUMMAND(438), DATA_C => SUMMAND(439), SAVE => INT_SUM(425), CARRY => INT_CARRY(338) ); ---- End FA stage ---- Begin FA stage FA_342:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(440), DATA_B => SUMMAND(441), DATA_C => SUMMAND(442), SAVE => INT_SUM(426), CARRY => INT_CARRY(339) ); ---- End FA stage ---- Begin FA stage FA_343:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(443), DATA_B => SUMMAND(444), DATA_C => SUMMAND(445), SAVE => INT_SUM(427), CARRY => INT_CARRY(340) ); ---- End FA stage ---- Begin HA stage HA_37:HALF_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(446), DATA_B => SUMMAND(447), SAVE => INT_SUM(428), CARRY => INT_CARRY(341) ); ---- End HA stage ---- Begin FA stage FA_344:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(424), DATA_B => INT_SUM(425), DATA_C => INT_SUM(426), SAVE => INT_SUM(429), CARRY => INT_CARRY(342) ); ---- End FA stage ---- Begin FA stage FA_345:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(427), DATA_B => INT_SUM(428), DATA_C => INT_CARRY(324), SAVE => INT_SUM(430), CARRY => INT_CARRY(343) ); ---- End FA stage ---- Begin FA stage FA_346:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(325), DATA_B => INT_CARRY(326), DATA_C => INT_CARRY(327), SAVE => INT_SUM(431), CARRY => INT_CARRY(344) ); ---- End FA stage ---- Begin NO stage INT_SUM(432) <= INT_CARRY(328); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_347:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(429), DATA_B => INT_SUM(430), DATA_C => INT_SUM(431), SAVE => INT_SUM(433), CARRY => INT_CARRY(345) ); ---- End FA stage ---- Begin FA stage FA_348:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(432), DATA_B => INT_CARRY(329), DATA_C => INT_CARRY(330), SAVE => INT_SUM(434), CARRY => INT_CARRY(346) ); ---- End FA stage ---- Begin NO stage INT_SUM(435) <= INT_CARRY(331); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_349:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(433), DATA_B => INT_SUM(434), DATA_C => INT_SUM(435), SAVE => INT_SUM(436), CARRY => INT_CARRY(347) ); ---- End FA stage ---- Begin HA stage HA_38:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(332), DATA_B => INT_CARRY(333), SAVE => INT_SUM(437), CARRY => INT_CARRY(348) ); ---- End HA stage ---- Begin FA stage FA_350:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(436), DATA_B => INT_SUM(437), DATA_C => INT_CARRY(334), SAVE => INT_SUM(438), CARRY => INT_CARRY(349) ); ---- End FA stage ---- Begin NO stage INT_SUM(439) <= INT_CARRY(335); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_351:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(438), DATA_B => INT_SUM(439), DATA_C => INT_CARRY(336), SAVE => SUM(41), CARRY => CARRY(41) ); ---- End FA stage -- End WT-branch 42 -- Begin WT-branch 43 ---- Begin FA stage FA_352:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(448), DATA_B => SUMMAND(449), DATA_C => SUMMAND(450), SAVE => INT_SUM(440), CARRY => INT_CARRY(350) ); ---- End FA stage ---- Begin FA stage FA_353:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(451), DATA_B => SUMMAND(452), DATA_C => SUMMAND(453), SAVE => INT_SUM(441), CARRY => INT_CARRY(351) ); ---- End FA stage ---- Begin FA stage FA_354:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(454), DATA_B => SUMMAND(455), DATA_C => SUMMAND(456), SAVE => INT_SUM(442), CARRY => INT_CARRY(352) ); ---- End FA stage ---- Begin FA stage FA_355:FULL_ADDER -- At Level 1 port map ( DATA_A => SUMMAND(457), DATA_B => SUMMAND(458), DATA_C => SUMMAND(459), SAVE => INT_SUM(443), CARRY => INT_CARRY(353) ); ---- End FA stage ---- Begin NO stage INT_SUM(444) <= SUMMAND(460); -- At Level 1 ---- End NO stage ---- Begin FA stage FA_356:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(440), DATA_B => INT_SUM(441), DATA_C => INT_SUM(442), SAVE => INT_SUM(445), CARRY => INT_CARRY(354) ); ---- End FA stage ---- Begin FA stage FA_357:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_SUM(443), DATA_B => INT_SUM(444), DATA_C => INT_CARRY(337), SAVE => INT_SUM(446), CARRY => INT_CARRY(355) ); ---- End FA stage ---- Begin FA stage FA_358:FULL_ADDER -- At Level 2 port map ( DATA_A => INT_CARRY(338), DATA_B => INT_CARRY(339), DATA_C => INT_CARRY(340), SAVE => INT_SUM(447), CARRY => INT_CARRY(356) ); ---- End FA stage ---- Begin NO stage INT_SUM(448) <= INT_CARRY(341); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_359:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(445), DATA_B => INT_SUM(446), DATA_C => INT_SUM(447), SAVE => INT_SUM(449), CARRY => INT_CARRY(357) ); ---- End FA stage ---- Begin FA stage FA_360:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(448), DATA_B => INT_CARRY(342), DATA_C => INT_CARRY(343), SAVE => INT_SUM(450), CARRY => INT_CARRY(358) ); ---- End FA stage ---- Begin NO stage INT_SUM(451) <= INT_CARRY(344); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_361:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(449), DATA_B => INT_SUM(450), DATA_C => INT_SUM(451), SAVE => INT_SUM(452), CARRY => INT_CARRY(359) ); ---- End FA stage ---- Begin HA stage HA_39:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(345), DATA_B => INT_CARRY(346), SAVE => INT_SUM(453), CARRY => INT_CARRY(360) ); ---- End HA stage ---- Begin FA stage FA_362:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(452), DATA_B => INT_SUM(453), DATA_C => INT_CARRY(347), SAVE => INT_SUM(454), CARRY => INT_CARRY(361) ); ---- End FA stage ---- Begin NO stage INT_SUM(455) <= INT_CARRY(348); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_363:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(454), DATA_B => INT_SUM(455), DATA_C => INT_CARRY(349), SAVE => SUM(42), CARRY => CARRY(42) ); ---- End FA stage -- End WT-branch 43 -- Begin WT-branch 44 ---- Begin FA stage FA_364:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(461), DATA_B => SUMMAND(462), DATA_C => SUMMAND(463), SAVE => INT_SUM(456), CARRY => INT_CARRY(362) ); ---- End FA stage ---- Begin FA stage FA_365:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(464), DATA_B => SUMMAND(465), DATA_C => SUMMAND(466), SAVE => INT_SUM(457), CARRY => INT_CARRY(363) ); ---- End FA stage ---- Begin FA stage FA_366:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(467), DATA_B => SUMMAND(468), DATA_C => SUMMAND(469), SAVE => INT_SUM(458), CARRY => INT_CARRY(364) ); ---- End FA stage ---- Begin FA stage FA_367:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(470), DATA_B => SUMMAND(471), DATA_C => SUMMAND(472), SAVE => INT_SUM(459), CARRY => INT_CARRY(365) ); ---- End FA stage ---- Begin FA stage FA_368:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(473), DATA_B => INT_CARRY(350), DATA_C => INT_CARRY(351), SAVE => INT_SUM(460), CARRY => INT_CARRY(366) ); ---- End FA stage ---- Begin NO stage INT_SUM(461) <= INT_CARRY(352); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(462) <= INT_CARRY(353); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_369:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(456), DATA_B => INT_SUM(457), DATA_C => INT_SUM(458), SAVE => INT_SUM(463), CARRY => INT_CARRY(367) ); ---- End FA stage ---- Begin FA stage FA_370:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(459), DATA_B => INT_SUM(460), DATA_C => INT_SUM(461), SAVE => INT_SUM(464), CARRY => INT_CARRY(368) ); ---- End FA stage ---- Begin FA stage FA_371:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(462), DATA_B => INT_CARRY(354), DATA_C => INT_CARRY(355), SAVE => INT_SUM(465), CARRY => INT_CARRY(369) ); ---- End FA stage ---- Begin NO stage INT_SUM(466) <= INT_CARRY(356); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_372:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(463), DATA_B => INT_SUM(464), DATA_C => INT_SUM(465), SAVE => INT_SUM(467), CARRY => INT_CARRY(370) ); ---- End FA stage ---- Begin FA stage FA_373:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(466), DATA_B => INT_CARRY(357), DATA_C => INT_CARRY(358), SAVE => INT_SUM(468), CARRY => INT_CARRY(371) ); ---- End FA stage ---- Begin FA stage FA_374:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(467), DATA_B => INT_SUM(468), DATA_C => INT_CARRY(359), SAVE => INT_SUM(469), CARRY => INT_CARRY(372) ); ---- End FA stage ---- Begin NO stage INT_SUM(470) <= INT_CARRY(360); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_375:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(469), DATA_B => INT_SUM(470), DATA_C => INT_CARRY(361), SAVE => SUM(43), CARRY => CARRY(43) ); ---- End FA stage -- End WT-branch 44 -- Begin WT-branch 45 ---- Begin FA stage FA_376:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(474), DATA_B => SUMMAND(475), DATA_C => SUMMAND(476), SAVE => INT_SUM(471), CARRY => INT_CARRY(373) ); ---- End FA stage ---- Begin FA stage FA_377:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(477), DATA_B => SUMMAND(478), DATA_C => SUMMAND(479), SAVE => INT_SUM(472), CARRY => INT_CARRY(374) ); ---- End FA stage ---- Begin FA stage FA_378:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(480), DATA_B => SUMMAND(481), DATA_C => SUMMAND(482), SAVE => INT_SUM(473), CARRY => INT_CARRY(375) ); ---- End FA stage ---- Begin FA stage FA_379:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(483), DATA_B => SUMMAND(484), DATA_C => SUMMAND(485), SAVE => INT_SUM(474), CARRY => INT_CARRY(376) ); ---- End FA stage ---- Begin FA stage FA_380:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(471), DATA_B => INT_SUM(472), DATA_C => INT_SUM(473), SAVE => INT_SUM(475), CARRY => INT_CARRY(377) ); ---- End FA stage ---- Begin FA stage FA_381:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(474), DATA_B => INT_CARRY(362), DATA_C => INT_CARRY(363), SAVE => INT_SUM(476), CARRY => INT_CARRY(378) ); ---- End FA stage ---- Begin FA stage FA_382:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(364), DATA_B => INT_CARRY(365), DATA_C => INT_CARRY(366), SAVE => INT_SUM(477), CARRY => INT_CARRY(379) ); ---- End FA stage ---- Begin FA stage FA_383:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(475), DATA_B => INT_SUM(476), DATA_C => INT_SUM(477), SAVE => INT_SUM(478), CARRY => INT_CARRY(380) ); ---- End FA stage ---- Begin FA stage FA_384:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(367), DATA_B => INT_CARRY(368), DATA_C => INT_CARRY(369), SAVE => INT_SUM(479), CARRY => INT_CARRY(381) ); ---- End FA stage ---- Begin FA stage FA_385:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(478), DATA_B => INT_SUM(479), DATA_C => INT_CARRY(370), SAVE => INT_SUM(480), CARRY => INT_CARRY(382) ); ---- End FA stage ---- Begin NO stage INT_SUM(481) <= INT_CARRY(371); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_386:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(480), DATA_B => INT_SUM(481), DATA_C => INT_CARRY(372), SAVE => SUM(44), CARRY => CARRY(44) ); ---- End FA stage -- End WT-branch 45 -- Begin WT-branch 46 ---- Begin FA stage FA_387:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(486), DATA_B => SUMMAND(487), DATA_C => SUMMAND(488), SAVE => INT_SUM(482), CARRY => INT_CARRY(383) ); ---- End FA stage ---- Begin FA stage FA_388:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(489), DATA_B => SUMMAND(490), DATA_C => SUMMAND(491), SAVE => INT_SUM(483), CARRY => INT_CARRY(384) ); ---- End FA stage ---- Begin FA stage FA_389:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(492), DATA_B => SUMMAND(493), DATA_C => SUMMAND(494), SAVE => INT_SUM(484), CARRY => INT_CARRY(385) ); ---- End FA stage ---- Begin FA stage FA_390:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(495), DATA_B => SUMMAND(496), DATA_C => SUMMAND(497), SAVE => INT_SUM(485), CARRY => INT_CARRY(386) ); ---- End FA stage ---- Begin FA stage FA_391:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(482), DATA_B => INT_SUM(483), DATA_C => INT_SUM(484), SAVE => INT_SUM(486), CARRY => INT_CARRY(387) ); ---- End FA stage ---- Begin FA stage FA_392:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(485), DATA_B => INT_CARRY(373), DATA_C => INT_CARRY(374), SAVE => INT_SUM(487), CARRY => INT_CARRY(388) ); ---- End FA stage ---- Begin HA stage HA_40:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(375), DATA_B => INT_CARRY(376), SAVE => INT_SUM(488), CARRY => INT_CARRY(389) ); ---- End HA stage ---- Begin FA stage FA_393:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(486), DATA_B => INT_SUM(487), DATA_C => INT_SUM(488), SAVE => INT_SUM(489), CARRY => INT_CARRY(390) ); ---- End FA stage ---- Begin FA stage FA_394:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(377), DATA_B => INT_CARRY(378), DATA_C => INT_CARRY(379), SAVE => INT_SUM(490), CARRY => INT_CARRY(391) ); ---- End FA stage ---- Begin FA stage FA_395:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(489), DATA_B => INT_SUM(490), DATA_C => INT_CARRY(380), SAVE => INT_SUM(491), CARRY => INT_CARRY(392) ); ---- End FA stage ---- Begin NO stage INT_SUM(492) <= INT_CARRY(381); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_396:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(491), DATA_B => INT_SUM(492), DATA_C => INT_CARRY(382), SAVE => SUM(45), CARRY => CARRY(45) ); ---- End FA stage -- End WT-branch 46 -- Begin WT-branch 47 ---- Begin FA stage FA_397:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(498), DATA_B => SUMMAND(499), DATA_C => SUMMAND(500), SAVE => INT_SUM(493), CARRY => INT_CARRY(393) ); ---- End FA stage ---- Begin FA stage FA_398:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(501), DATA_B => SUMMAND(502), DATA_C => SUMMAND(503), SAVE => INT_SUM(494), CARRY => INT_CARRY(394) ); ---- End FA stage ---- Begin FA stage FA_399:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(504), DATA_B => SUMMAND(505), DATA_C => SUMMAND(506), SAVE => INT_SUM(495), CARRY => INT_CARRY(395) ); ---- End FA stage ---- Begin NO stage INT_SUM(496) <= SUMMAND(507); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(497) <= SUMMAND(508); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_400:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(493), DATA_B => INT_SUM(494), DATA_C => INT_SUM(495), SAVE => INT_SUM(498), CARRY => INT_CARRY(396) ); ---- End FA stage ---- Begin FA stage FA_401:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(496), DATA_B => INT_SUM(497), DATA_C => INT_CARRY(383), SAVE => INT_SUM(499), CARRY => INT_CARRY(397) ); ---- End FA stage ---- Begin FA stage FA_402:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(384), DATA_B => INT_CARRY(385), DATA_C => INT_CARRY(386), SAVE => INT_SUM(500), CARRY => INT_CARRY(398) ); ---- End FA stage ---- Begin FA stage FA_403:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(498), DATA_B => INT_SUM(499), DATA_C => INT_SUM(500), SAVE => INT_SUM(501), CARRY => INT_CARRY(399) ); ---- End FA stage ---- Begin FA stage FA_404:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(387), DATA_B => INT_CARRY(388), DATA_C => INT_CARRY(389), SAVE => INT_SUM(502), CARRY => INT_CARRY(400) ); ---- End FA stage ---- Begin FA stage FA_405:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(501), DATA_B => INT_SUM(502), DATA_C => INT_CARRY(390), SAVE => INT_SUM(503), CARRY => INT_CARRY(401) ); ---- End FA stage ---- Begin NO stage INT_SUM(504) <= INT_CARRY(391); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_406:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(503), DATA_B => INT_SUM(504), DATA_C => INT_CARRY(392), SAVE => SUM(46), CARRY => CARRY(46) ); ---- End FA stage -- End WT-branch 47 -- Begin WT-branch 48 ---- Begin FA stage FA_407:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(509), DATA_B => SUMMAND(510), DATA_C => SUMMAND(511), SAVE => INT_SUM(505), CARRY => INT_CARRY(402) ); ---- End FA stage ---- Begin FA stage FA_408:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(512), DATA_B => SUMMAND(513), DATA_C => SUMMAND(514), SAVE => INT_SUM(506), CARRY => INT_CARRY(403) ); ---- End FA stage ---- Begin FA stage FA_409:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(515), DATA_B => SUMMAND(516), DATA_C => SUMMAND(517), SAVE => INT_SUM(507), CARRY => INT_CARRY(404) ); ---- End FA stage ---- Begin HA stage HA_41:HALF_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(518), DATA_B => SUMMAND(519), SAVE => INT_SUM(508), CARRY => INT_CARRY(405) ); ---- End HA stage ---- Begin FA stage FA_410:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(505), DATA_B => INT_SUM(506), DATA_C => INT_SUM(507), SAVE => INT_SUM(509), CARRY => INT_CARRY(406) ); ---- End FA stage ---- Begin FA stage FA_411:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(508), DATA_B => INT_CARRY(393), DATA_C => INT_CARRY(394), SAVE => INT_SUM(510), CARRY => INT_CARRY(407) ); ---- End FA stage ---- Begin NO stage INT_SUM(511) <= INT_CARRY(395); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_412:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(509), DATA_B => INT_SUM(510), DATA_C => INT_SUM(511), SAVE => INT_SUM(512), CARRY => INT_CARRY(408) ); ---- End FA stage ---- Begin FA stage FA_413:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(396), DATA_B => INT_CARRY(397), DATA_C => INT_CARRY(398), SAVE => INT_SUM(513), CARRY => INT_CARRY(409) ); ---- End FA stage ---- Begin FA stage FA_414:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(512), DATA_B => INT_SUM(513), DATA_C => INT_CARRY(399), SAVE => INT_SUM(514), CARRY => INT_CARRY(410) ); ---- End FA stage ---- Begin NO stage INT_SUM(515) <= INT_CARRY(400); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_415:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(514), DATA_B => INT_SUM(515), DATA_C => INT_CARRY(401), SAVE => SUM(47), CARRY => CARRY(47) ); ---- End FA stage -- End WT-branch 48 -- Begin WT-branch 49 ---- Begin FA stage FA_416:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(520), DATA_B => SUMMAND(521), DATA_C => SUMMAND(522), SAVE => INT_SUM(516), CARRY => INT_CARRY(411) ); ---- End FA stage ---- Begin FA stage FA_417:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(523), DATA_B => SUMMAND(524), DATA_C => SUMMAND(525), SAVE => INT_SUM(517), CARRY => INT_CARRY(412) ); ---- End FA stage ---- Begin FA stage FA_418:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(526), DATA_B => SUMMAND(527), DATA_C => SUMMAND(528), SAVE => INT_SUM(518), CARRY => INT_CARRY(413) ); ---- End FA stage ---- Begin NO stage INT_SUM(519) <= SUMMAND(529); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_419:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(516), DATA_B => INT_SUM(517), DATA_C => INT_SUM(518), SAVE => INT_SUM(520), CARRY => INT_CARRY(414) ); ---- End FA stage ---- Begin FA stage FA_420:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(519), DATA_B => INT_CARRY(402), DATA_C => INT_CARRY(403), SAVE => INT_SUM(521), CARRY => INT_CARRY(415) ); ---- End FA stage ---- Begin NO stage INT_SUM(522) <= INT_CARRY(404); -- At Level 3 ---- End NO stage ---- Begin NO stage INT_SUM(523) <= INT_CARRY(405); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_421:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(520), DATA_B => INT_SUM(521), DATA_C => INT_SUM(522), SAVE => INT_SUM(524), CARRY => INT_CARRY(416) ); ---- End FA stage ---- Begin FA stage FA_422:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(523), DATA_B => INT_CARRY(406), DATA_C => INT_CARRY(407), SAVE => INT_SUM(525), CARRY => INT_CARRY(417) ); ---- End FA stage ---- Begin FA stage FA_423:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(524), DATA_B => INT_SUM(525), DATA_C => INT_CARRY(408), SAVE => INT_SUM(526), CARRY => INT_CARRY(418) ); ---- End FA stage ---- Begin NO stage INT_SUM(527) <= INT_CARRY(409); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_424:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(526), DATA_B => INT_SUM(527), DATA_C => INT_CARRY(410), SAVE => SUM(48), CARRY => CARRY(48) ); ---- End FA stage -- End WT-branch 49 -- Begin WT-branch 50 ---- Begin FA stage FA_425:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(530), DATA_B => SUMMAND(531), DATA_C => SUMMAND(532), SAVE => INT_SUM(528), CARRY => INT_CARRY(419) ); ---- End FA stage ---- Begin FA stage FA_426:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(533), DATA_B => SUMMAND(534), DATA_C => SUMMAND(535), SAVE => INT_SUM(529), CARRY => INT_CARRY(420) ); ---- End FA stage ---- Begin FA stage FA_427:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(536), DATA_B => SUMMAND(537), DATA_C => SUMMAND(538), SAVE => INT_SUM(530), CARRY => INT_CARRY(421) ); ---- End FA stage ---- Begin NO stage INT_SUM(531) <= SUMMAND(539); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_428:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(528), DATA_B => INT_SUM(529), DATA_C => INT_SUM(530), SAVE => INT_SUM(532), CARRY => INT_CARRY(422) ); ---- End FA stage ---- Begin FA stage FA_429:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(531), DATA_B => INT_CARRY(411), DATA_C => INT_CARRY(412), SAVE => INT_SUM(533), CARRY => INT_CARRY(423) ); ---- End FA stage ---- Begin NO stage INT_SUM(534) <= INT_CARRY(413); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_430:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(532), DATA_B => INT_SUM(533), DATA_C => INT_SUM(534), SAVE => INT_SUM(535), CARRY => INT_CARRY(424) ); ---- End FA stage ---- Begin HA stage HA_42:HALF_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(414), DATA_B => INT_CARRY(415), SAVE => INT_SUM(536), CARRY => INT_CARRY(425) ); ---- End HA stage ---- Begin FA stage FA_431:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(535), DATA_B => INT_SUM(536), DATA_C => INT_CARRY(416), SAVE => INT_SUM(537), CARRY => INT_CARRY(426) ); ---- End FA stage ---- Begin NO stage INT_SUM(538) <= INT_CARRY(417); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_432:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(537), DATA_B => INT_SUM(538), DATA_C => INT_CARRY(418), SAVE => SUM(49), CARRY => CARRY(49) ); ---- End FA stage -- End WT-branch 50 -- Begin WT-branch 51 ---- Begin FA stage FA_433:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(540), DATA_B => SUMMAND(541), DATA_C => SUMMAND(542), SAVE => INT_SUM(539), CARRY => INT_CARRY(427) ); ---- End FA stage ---- Begin FA stage FA_434:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(543), DATA_B => SUMMAND(544), DATA_C => SUMMAND(545), SAVE => INT_SUM(540), CARRY => INT_CARRY(428) ); ---- End FA stage ---- Begin FA stage FA_435:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(546), DATA_B => SUMMAND(547), DATA_C => SUMMAND(548), SAVE => INT_SUM(541), CARRY => INT_CARRY(429) ); ---- End FA stage ---- Begin FA stage FA_436:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(539), DATA_B => INT_SUM(540), DATA_C => INT_SUM(541), SAVE => INT_SUM(542), CARRY => INT_CARRY(430) ); ---- End FA stage ---- Begin FA stage FA_437:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(419), DATA_B => INT_CARRY(420), DATA_C => INT_CARRY(421), SAVE => INT_SUM(543), CARRY => INT_CARRY(431) ); ---- End FA stage ---- Begin FA stage FA_438:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(542), DATA_B => INT_SUM(543), DATA_C => INT_CARRY(422), SAVE => INT_SUM(544), CARRY => INT_CARRY(432) ); ---- End FA stage ---- Begin NO stage INT_SUM(545) <= INT_CARRY(423); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_439:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(544), DATA_B => INT_SUM(545), DATA_C => INT_CARRY(424), SAVE => INT_SUM(546), CARRY => INT_CARRY(433) ); ---- End FA stage ---- Begin NO stage INT_SUM(547) <= INT_CARRY(425); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_440:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(546), DATA_B => INT_SUM(547), DATA_C => INT_CARRY(426), SAVE => SUM(50), CARRY => CARRY(50) ); ---- End FA stage -- End WT-branch 51 -- Begin WT-branch 52 ---- Begin FA stage FA_441:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(549), DATA_B => SUMMAND(550), DATA_C => SUMMAND(551), SAVE => INT_SUM(548), CARRY => INT_CARRY(434) ); ---- End FA stage ---- Begin FA stage FA_442:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(552), DATA_B => SUMMAND(553), DATA_C => SUMMAND(554), SAVE => INT_SUM(549), CARRY => INT_CARRY(435) ); ---- End FA stage ---- Begin FA stage FA_443:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(555), DATA_B => SUMMAND(556), DATA_C => SUMMAND(557), SAVE => INT_SUM(550), CARRY => INT_CARRY(436) ); ---- End FA stage ---- Begin FA stage FA_444:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(548), DATA_B => INT_SUM(549), DATA_C => INT_SUM(550), SAVE => INT_SUM(551), CARRY => INT_CARRY(437) ); ---- End FA stage ---- Begin FA stage FA_445:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(427), DATA_B => INT_CARRY(428), DATA_C => INT_CARRY(429), SAVE => INT_SUM(552), CARRY => INT_CARRY(438) ); ---- End FA stage ---- Begin FA stage FA_446:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(551), DATA_B => INT_SUM(552), DATA_C => INT_CARRY(430), SAVE => INT_SUM(553), CARRY => INT_CARRY(439) ); ---- End FA stage ---- Begin NO stage INT_SUM(554) <= INT_CARRY(431); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_447:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(553), DATA_B => INT_SUM(554), DATA_C => INT_CARRY(432), SAVE => INT_SUM(555), CARRY => INT_CARRY(440) ); ---- End FA stage ---- Begin HA stage HA_43:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(555), DATA_B => INT_CARRY(433), SAVE => SUM(51), CARRY => CARRY(51) ); ---- End HA stage -- End WT-branch 52 -- Begin WT-branch 53 ---- Begin FA stage FA_448:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(558), DATA_B => SUMMAND(559), DATA_C => SUMMAND(560), SAVE => INT_SUM(556), CARRY => INT_CARRY(441) ); ---- End FA stage ---- Begin FA stage FA_449:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(561), DATA_B => SUMMAND(562), DATA_C => SUMMAND(563), SAVE => INT_SUM(557), CARRY => INT_CARRY(442) ); ---- End FA stage ---- Begin FA stage FA_450:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(564), DATA_B => SUMMAND(565), DATA_C => INT_CARRY(434), SAVE => INT_SUM(558), CARRY => INT_CARRY(443) ); ---- End FA stage ---- Begin HA stage HA_44:HALF_ADDER -- At Level 3 port map ( DATA_A => INT_CARRY(435), DATA_B => INT_CARRY(436), SAVE => INT_SUM(559), CARRY => INT_CARRY(444) ); ---- End HA stage ---- Begin FA stage FA_451:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(556), DATA_B => INT_SUM(557), DATA_C => INT_SUM(558), SAVE => INT_SUM(560), CARRY => INT_CARRY(445) ); ---- End FA stage ---- Begin FA stage FA_452:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(559), DATA_B => INT_CARRY(437), DATA_C => INT_CARRY(438), SAVE => INT_SUM(561), CARRY => INT_CARRY(446) ); ---- End FA stage ---- Begin FA stage FA_453:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(560), DATA_B => INT_SUM(561), DATA_C => INT_CARRY(439), SAVE => INT_SUM(562), CARRY => INT_CARRY(447) ); ---- End FA stage ---- Begin HA stage HA_45:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(562), DATA_B => INT_CARRY(440), SAVE => SUM(52), CARRY => CARRY(52) ); ---- End HA stage -- End WT-branch 53 -- Begin WT-branch 54 ---- Begin FA stage FA_454:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(566), DATA_B => SUMMAND(567), DATA_C => SUMMAND(568), SAVE => INT_SUM(563), CARRY => INT_CARRY(448) ); ---- End FA stage ---- Begin FA stage FA_455:FULL_ADDER -- At Level 2 port map ( DATA_A => SUMMAND(569), DATA_B => SUMMAND(570), DATA_C => SUMMAND(571), SAVE => INT_SUM(564), CARRY => INT_CARRY(449) ); ---- End FA stage ---- Begin NO stage INT_SUM(565) <= SUMMAND(572); -- At Level 2 ---- End NO stage ---- Begin NO stage INT_SUM(566) <= SUMMAND(573); -- At Level 2 ---- End NO stage ---- Begin FA stage FA_456:FULL_ADDER -- At Level 3 port map ( DATA_A => INT_SUM(563), DATA_B => INT_SUM(564), DATA_C => INT_SUM(565), SAVE => INT_SUM(567), CARRY => INT_CARRY(450) ); ---- End FA stage ---- Begin NO stage INT_SUM(568) <= INT_SUM(566); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_457:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(567), DATA_B => INT_SUM(568), DATA_C => INT_CARRY(441), SAVE => INT_SUM(569), CARRY => INT_CARRY(451) ); ---- End FA stage ---- Begin FA stage FA_458:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(442), DATA_B => INT_CARRY(443), DATA_C => INT_CARRY(444), SAVE => INT_SUM(570), CARRY => INT_CARRY(452) ); ---- End FA stage ---- Begin FA stage FA_459:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(569), DATA_B => INT_SUM(570), DATA_C => INT_CARRY(445), SAVE => INT_SUM(571), CARRY => INT_CARRY(453) ); ---- End FA stage ---- Begin NO stage INT_SUM(572) <= INT_CARRY(446); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_460:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(571), DATA_B => INT_SUM(572), DATA_C => INT_CARRY(447), SAVE => SUM(53), CARRY => CARRY(53) ); ---- End FA stage -- End WT-branch 54 -- Begin WT-branch 55 ---- Begin FA stage FA_461:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(574), DATA_B => SUMMAND(575), DATA_C => SUMMAND(576), SAVE => INT_SUM(573), CARRY => INT_CARRY(454) ); ---- End FA stage ---- Begin FA stage FA_462:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(577), DATA_B => SUMMAND(578), DATA_C => SUMMAND(579), SAVE => INT_SUM(574), CARRY => INT_CARRY(455) ); ---- End FA stage ---- Begin FA stage FA_463:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(580), DATA_B => INT_CARRY(448), DATA_C => INT_CARRY(449), SAVE => INT_SUM(575), CARRY => INT_CARRY(456) ); ---- End FA stage ---- Begin FA stage FA_464:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(573), DATA_B => INT_SUM(574), DATA_C => INT_SUM(575), SAVE => INT_SUM(576), CARRY => INT_CARRY(457) ); ---- End FA stage ---- Begin NO stage INT_SUM(577) <= INT_CARRY(450); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_465:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(576), DATA_B => INT_SUM(577), DATA_C => INT_CARRY(451), SAVE => INT_SUM(578), CARRY => INT_CARRY(458) ); ---- End FA stage ---- Begin NO stage INT_SUM(579) <= INT_CARRY(452); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_466:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(578), DATA_B => INT_SUM(579), DATA_C => INT_CARRY(453), SAVE => SUM(54), CARRY => CARRY(54) ); ---- End FA stage -- End WT-branch 55 -- Begin WT-branch 56 ---- Begin FA stage FA_467:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(581), DATA_B => SUMMAND(582), DATA_C => SUMMAND(583), SAVE => INT_SUM(580), CARRY => INT_CARRY(459) ); ---- End FA stage ---- Begin FA stage FA_468:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(584), DATA_B => SUMMAND(585), DATA_C => SUMMAND(586), SAVE => INT_SUM(581), CARRY => INT_CARRY(460) ); ---- End FA stage ---- Begin NO stage INT_SUM(582) <= SUMMAND(587); -- At Level 3 ---- End NO stage ---- Begin FA stage FA_469:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(580), DATA_B => INT_SUM(581), DATA_C => INT_SUM(582), SAVE => INT_SUM(583), CARRY => INT_CARRY(461) ); ---- End FA stage ---- Begin FA stage FA_470:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_CARRY(454), DATA_B => INT_CARRY(455), DATA_C => INT_CARRY(456), SAVE => INT_SUM(584), CARRY => INT_CARRY(462) ); ---- End FA stage ---- Begin FA stage FA_471:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(583), DATA_B => INT_SUM(584), DATA_C => INT_CARRY(457), SAVE => INT_SUM(585), CARRY => INT_CARRY(463) ); ---- End FA stage ---- Begin HA stage HA_46:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(585), DATA_B => INT_CARRY(458), SAVE => SUM(55), CARRY => CARRY(55) ); ---- End HA stage -- End WT-branch 56 -- Begin WT-branch 57 ---- Begin FA stage FA_472:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(588), DATA_B => SUMMAND(589), DATA_C => SUMMAND(590), SAVE => INT_SUM(586), CARRY => INT_CARRY(464) ); ---- End FA stage ---- Begin FA stage FA_473:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(591), DATA_B => SUMMAND(592), DATA_C => SUMMAND(593), SAVE => INT_SUM(587), CARRY => INT_CARRY(465) ); ---- End FA stage ---- Begin FA stage FA_474:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(586), DATA_B => INT_SUM(587), DATA_C => INT_CARRY(459), SAVE => INT_SUM(588), CARRY => INT_CARRY(466) ); ---- End FA stage ---- Begin NO stage INT_SUM(589) <= INT_CARRY(460); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_475:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(588), DATA_B => INT_SUM(589), DATA_C => INT_CARRY(461), SAVE => INT_SUM(590), CARRY => INT_CARRY(467) ); ---- End FA stage ---- Begin NO stage INT_SUM(591) <= INT_CARRY(462); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_476:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(590), DATA_B => INT_SUM(591), DATA_C => INT_CARRY(463), SAVE => SUM(56), CARRY => CARRY(56) ); ---- End FA stage -- End WT-branch 57 -- Begin WT-branch 58 ---- Begin FA stage FA_477:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(594), DATA_B => SUMMAND(595), DATA_C => SUMMAND(596), SAVE => INT_SUM(592), CARRY => INT_CARRY(468) ); ---- End FA stage ---- Begin FA stage FA_478:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(597), DATA_B => SUMMAND(598), DATA_C => SUMMAND(599), SAVE => INT_SUM(593), CARRY => INT_CARRY(469) ); ---- End FA stage ---- Begin FA stage FA_479:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(592), DATA_B => INT_SUM(593), DATA_C => INT_CARRY(464), SAVE => INT_SUM(594), CARRY => INT_CARRY(470) ); ---- End FA stage ---- Begin NO stage INT_SUM(595) <= INT_CARRY(465); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_480:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(594), DATA_B => INT_SUM(595), DATA_C => INT_CARRY(466), SAVE => INT_SUM(596), CARRY => INT_CARRY(471) ); ---- End FA stage ---- Begin HA stage HA_47:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(596), DATA_B => INT_CARRY(467), SAVE => SUM(57), CARRY => CARRY(57) ); ---- End HA stage -- End WT-branch 58 -- Begin WT-branch 59 ---- Begin FA stage FA_481:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(600), DATA_B => SUMMAND(601), DATA_C => SUMMAND(602), SAVE => INT_SUM(597), CARRY => INT_CARRY(472) ); ---- End FA stage ---- Begin HA stage HA_48:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(603), DATA_B => SUMMAND(604), SAVE => INT_SUM(598), CARRY => INT_CARRY(473) ); ---- End HA stage ---- Begin FA stage FA_482:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(597), DATA_B => INT_SUM(598), DATA_C => INT_CARRY(468), SAVE => INT_SUM(599), CARRY => INT_CARRY(474) ); ---- End FA stage ---- Begin NO stage INT_SUM(600) <= INT_CARRY(469); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_483:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(599), DATA_B => INT_SUM(600), DATA_C => INT_CARRY(470), SAVE => INT_SUM(601), CARRY => INT_CARRY(475) ); ---- End FA stage ---- Begin HA stage HA_49:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(601), DATA_B => INT_CARRY(471), SAVE => SUM(58), CARRY => CARRY(58) ); ---- End HA stage -- End WT-branch 59 -- Begin WT-branch 60 ---- Begin FA stage FA_484:FULL_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(605), DATA_B => SUMMAND(606), DATA_C => SUMMAND(607), SAVE => INT_SUM(602), CARRY => INT_CARRY(476) ); ---- End FA stage ---- Begin HA stage HA_50:HALF_ADDER -- At Level 3 port map ( DATA_A => SUMMAND(608), DATA_B => SUMMAND(609), SAVE => INT_SUM(603), CARRY => INT_CARRY(477) ); ---- End HA stage ---- Begin FA stage FA_485:FULL_ADDER -- At Level 4 port map ( DATA_A => INT_SUM(602), DATA_B => INT_SUM(603), DATA_C => INT_CARRY(472), SAVE => INT_SUM(604), CARRY => INT_CARRY(478) ); ---- End FA stage ---- Begin NO stage INT_SUM(605) <= INT_CARRY(473); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_486:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(604), DATA_B => INT_SUM(605), DATA_C => INT_CARRY(474), SAVE => INT_SUM(606), CARRY => INT_CARRY(479) ); ---- End FA stage ---- Begin HA stage HA_51:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(606), DATA_B => INT_CARRY(475), SAVE => SUM(59), CARRY => CARRY(59) ); ---- End HA stage -- End WT-branch 60 -- Begin WT-branch 61 ---- Begin FA stage FA_487:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(610), DATA_B => SUMMAND(611), DATA_C => SUMMAND(612), SAVE => INT_SUM(607), CARRY => INT_CARRY(480) ); ---- End FA stage ---- Begin FA stage FA_488:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(613), DATA_B => INT_CARRY(476), DATA_C => INT_CARRY(477), SAVE => INT_SUM(608), CARRY => INT_CARRY(481) ); ---- End FA stage ---- Begin FA stage FA_489:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(607), DATA_B => INT_SUM(608), DATA_C => INT_CARRY(478), SAVE => INT_SUM(609), CARRY => INT_CARRY(482) ); ---- End FA stage ---- Begin HA stage HA_52:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(609), DATA_B => INT_CARRY(479), SAVE => SUM(60), CARRY => CARRY(60) ); ---- End HA stage -- End WT-branch 61 -- Begin WT-branch 62 ---- Begin FA stage FA_490:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(614), DATA_B => SUMMAND(615), DATA_C => SUMMAND(616), SAVE => INT_SUM(610), CARRY => INT_CARRY(483) ); ---- End FA stage ---- Begin NO stage INT_SUM(611) <= SUMMAND(617); -- At Level 4 ---- End NO stage ---- Begin FA stage FA_491:FULL_ADDER -- At Level 5 port map ( DATA_A => INT_SUM(610), DATA_B => INT_SUM(611), DATA_C => INT_CARRY(480), SAVE => INT_SUM(612), CARRY => INT_CARRY(484) ); ---- End FA stage ---- Begin NO stage INT_SUM(613) <= INT_CARRY(481); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_492:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(612), DATA_B => INT_SUM(613), DATA_C => INT_CARRY(482), SAVE => SUM(61), CARRY => CARRY(61) ); ---- End FA stage -- End WT-branch 62 -- Begin WT-branch 63 ---- Begin FA stage FA_493:FULL_ADDER -- At Level 4 port map ( DATA_A => SUMMAND(618), DATA_B => SUMMAND(619), DATA_C => SUMMAND(620), SAVE => INT_SUM(614), CARRY => INT_CARRY(485) ); ---- End FA stage ---- Begin NO stage INT_SUM(615) <= INT_SUM(614); -- At Level 5 ---- End NO stage ---- Begin NO stage INT_SUM(616) <= INT_CARRY(483); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_494:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(615), DATA_B => INT_SUM(616), DATA_C => INT_CARRY(484), SAVE => SUM(62), CARRY => CARRY(62) ); ---- End FA stage -- End WT-branch 63 -- Begin WT-branch 64 ---- Begin FA stage FA_495:FULL_ADDER -- At Level 5 port map ( DATA_A => SUMMAND(621), DATA_B => SUMMAND(622), DATA_C => SUMMAND(623), SAVE => INT_SUM(617), CARRY => INT_CARRY(486) ); ---- End FA stage ---- Begin NO stage INT_SUM(618) <= INT_CARRY(485); -- At Level 5 ---- End NO stage ---- Begin HA stage HA_53:HALF_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(617), DATA_B => INT_SUM(618), SAVE => SUM(63), CARRY => CARRY(63) ); ---- End HA stage -- End WT-branch 64 -- Begin WT-branch 65 ---- Begin NO stage INT_SUM(619) <= SUMMAND(624); -- At Level 5 ---- End NO stage ---- Begin NO stage INT_SUM(620) <= SUMMAND(625); -- At Level 5 ---- End NO stage ---- Begin FA stage FA_496:FULL_ADDER -- At Level 6 port map ( DATA_A => INT_SUM(619), DATA_B => INT_SUM(620), DATA_C => INT_CARRY(486), SAVE => SUM(64), CARRY => CARRY(64) ); ---- End FA stage -- End WT-branch 65 -- Begin WT-branch 66 ---- Begin HA stage HA_54:HALF_ADDER -- At Level 6 port map ( DATA_A => SUMMAND(626), DATA_B => SUMMAND(627), SAVE => SUM(65), CARRY => CARRY(65) ); ---- End HA stage -- End WT-branch 66 -- Begin WT-branch 67 ---- Begin NO stage SUM(66) <= SUMMAND(628); -- At Level 6 ---- End NO stage -- End WT-branch 67 end WALLACE; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MULTIPLIER_34_34 is generic (mulpipe : integer := 0); port ( MULTIPLICAND: in std_logic_vector(0 to 33); MULTIPLIER: in std_logic_vector(0 to 33); PHI: in std_logic; holdn: in std_logic; RESULT: out std_logic_vector(0 to 127) ); end MULTIPLIER_34_34; architecture MULTIPLIER of MULTIPLIER_34_34 is signal PPBIT:std_logic_vector(0 to 628); signal INT_CARRY: std_logic_vector(0 to 128); signal INT_SUM: std_logic_vector(0 to 127); signal LOGIC_ZERO: std_logic; signal INT_CARRYR: std_logic_vector(0 to 128); signal INT_SUMR: std_logic_vector(0 to 127); begin -- Architecture LOGIC_ZERO <= '0'; B:BOOTHCODER_34_34 port map ( OPA(0 to 33) => MULTIPLICAND(0 to 33), OPB(0 to 33) => MULTIPLIER(0 to 33), SUMMAND(0 to 628) => PPBIT(0 to 628) ); W:WALLACE_34_34 port map ( SUMMAND(0 to 628) => PPBIT(0 to 628), CARRY(0 to 65) => INT_CARRY(1 to 66), SUM(0 to 66) => INT_SUM(0 to 66) ); INT_CARRY(0) <= LOGIC_ZERO; INT_CARRY(67) <= LOGIC_ZERO; INT_CARRY(68) <= LOGIC_ZERO; INT_CARRY(69) <= LOGIC_ZERO; INT_CARRY(70) <= LOGIC_ZERO; INT_CARRY(71) <= LOGIC_ZERO; INT_CARRY(72) <= LOGIC_ZERO; INT_CARRY(73) <= LOGIC_ZERO; INT_CARRY(74) <= LOGIC_ZERO; INT_CARRY(75) <= LOGIC_ZERO; INT_CARRY(76) <= LOGIC_ZERO; INT_CARRY(77) <= LOGIC_ZERO; INT_CARRY(78) <= LOGIC_ZERO; INT_CARRY(79) <= LOGIC_ZERO; INT_CARRY(80) <= LOGIC_ZERO; INT_CARRY(81) <= LOGIC_ZERO; INT_CARRY(82) <= LOGIC_ZERO; INT_CARRY(83) <= LOGIC_ZERO; INT_CARRY(84) <= LOGIC_ZERO; INT_CARRY(85) <= LOGIC_ZERO; INT_CARRY(86) <= LOGIC_ZERO; INT_CARRY(87) <= LOGIC_ZERO; INT_CARRY(88) <= LOGIC_ZERO; INT_CARRY(89) <= LOGIC_ZERO; INT_CARRY(90) <= LOGIC_ZERO; INT_CARRY(91) <= LOGIC_ZERO; INT_CARRY(92) <= LOGIC_ZERO; INT_CARRY(93) <= LOGIC_ZERO; INT_CARRY(94) <= LOGIC_ZERO; INT_CARRY(95) <= LOGIC_ZERO; INT_CARRY(96) <= LOGIC_ZERO; INT_CARRY(97) <= LOGIC_ZERO; INT_CARRY(98) <= LOGIC_ZERO; INT_CARRY(99) <= LOGIC_ZERO; INT_CARRY(100) <= LOGIC_ZERO; INT_CARRY(101) <= LOGIC_ZERO; INT_CARRY(102) <= LOGIC_ZERO; INT_CARRY(103) <= LOGIC_ZERO; INT_CARRY(104) <= LOGIC_ZERO; INT_CARRY(105) <= LOGIC_ZERO; INT_CARRY(106) <= LOGIC_ZERO; INT_CARRY(107) <= LOGIC_ZERO; INT_CARRY(108) <= LOGIC_ZERO; INT_CARRY(109) <= LOGIC_ZERO; INT_CARRY(110) <= LOGIC_ZERO; INT_CARRY(111) <= LOGIC_ZERO; INT_CARRY(112) <= LOGIC_ZERO; INT_CARRY(113) <= LOGIC_ZERO; INT_CARRY(114) <= LOGIC_ZERO; INT_CARRY(115) <= LOGIC_ZERO; INT_CARRY(116) <= LOGIC_ZERO; INT_CARRY(117) <= LOGIC_ZERO; INT_CARRY(118) <= LOGIC_ZERO; INT_CARRY(119) <= LOGIC_ZERO; INT_CARRY(120) <= LOGIC_ZERO; INT_CARRY(121) <= LOGIC_ZERO; INT_CARRY(122) <= LOGIC_ZERO; INT_CARRY(123) <= LOGIC_ZERO; INT_CARRY(124) <= LOGIC_ZERO; INT_CARRY(125) <= LOGIC_ZERO; INT_CARRY(126) <= LOGIC_ZERO; INT_CARRY(127) <= LOGIC_ZERO; INT_SUM(67) <= LOGIC_ZERO; INT_SUM(68) <= LOGIC_ZERO; INT_SUM(69) <= LOGIC_ZERO; INT_SUM(70) <= LOGIC_ZERO; INT_SUM(71) <= LOGIC_ZERO; INT_SUM(72) <= LOGIC_ZERO; INT_SUM(73) <= LOGIC_ZERO; INT_SUM(74) <= LOGIC_ZERO; INT_SUM(75) <= LOGIC_ZERO; INT_SUM(76) <= LOGIC_ZERO; INT_SUM(77) <= LOGIC_ZERO; INT_SUM(78) <= LOGIC_ZERO; INT_SUM(79) <= LOGIC_ZERO; INT_SUM(80) <= LOGIC_ZERO; INT_SUM(81) <= LOGIC_ZERO; INT_SUM(82) <= LOGIC_ZERO; INT_SUM(83) <= LOGIC_ZERO; INT_SUM(84) <= LOGIC_ZERO; INT_SUM(85) <= LOGIC_ZERO; INT_SUM(86) <= LOGIC_ZERO; INT_SUM(87) <= LOGIC_ZERO; INT_SUM(88) <= LOGIC_ZERO; INT_SUM(89) <= LOGIC_ZERO; INT_SUM(90) <= LOGIC_ZERO; INT_SUM(91) <= LOGIC_ZERO; INT_SUM(92) <= LOGIC_ZERO; INT_SUM(93) <= LOGIC_ZERO; INT_SUM(94) <= LOGIC_ZERO; INT_SUM(95) <= LOGIC_ZERO; INT_SUM(96) <= LOGIC_ZERO; INT_SUM(97) <= LOGIC_ZERO; INT_SUM(98) <= LOGIC_ZERO; INT_SUM(99) <= LOGIC_ZERO; INT_SUM(100) <= LOGIC_ZERO; INT_SUM(101) <= LOGIC_ZERO; INT_SUM(102) <= LOGIC_ZERO; INT_SUM(103) <= LOGIC_ZERO; INT_SUM(104) <= LOGIC_ZERO; INT_SUM(105) <= LOGIC_ZERO; INT_SUM(106) <= LOGIC_ZERO; INT_SUM(107) <= LOGIC_ZERO; INT_SUM(108) <= LOGIC_ZERO; INT_SUM(109) <= LOGIC_ZERO; INT_SUM(110) <= LOGIC_ZERO; INT_SUM(111) <= LOGIC_ZERO; INT_SUM(112) <= LOGIC_ZERO; INT_SUM(113) <= LOGIC_ZERO; INT_SUM(114) <= LOGIC_ZERO; INT_SUM(115) <= LOGIC_ZERO; INT_SUM(116) <= LOGIC_ZERO; INT_SUM(117) <= LOGIC_ZERO; INT_SUM(118) <= LOGIC_ZERO; INT_SUM(119) <= LOGIC_ZERO; INT_SUM(120) <= LOGIC_ZERO; INT_SUM(121) <= LOGIC_ZERO; INT_SUM(122) <= LOGIC_ZERO; INT_SUM(123) <= LOGIC_ZERO; INT_SUM(124) <= LOGIC_ZERO; INT_SUM(125) <= LOGIC_ZERO; INT_SUM(126) <= LOGIC_ZERO; INT_SUM(127) <= LOGIC_ZERO; INT_SUMR(67 to 127) <= INT_SUM(67 to 127); INT_CARRYR(67 to 127) <= INT_CARRY(67 to 127); INT_CARRYR(0) <= INT_CARRY(0); reg : if MULPIPE /= 0 generate process (PHI) begin if rising_edge(PHI ) then if (holdn = '1') then INT_SUMR(0 to 66) <= INT_SUM(0 to 66); INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66); end if; end if; end process; end generate; noreg : if MULPIPE = 0 generate INT_SUMR(0 to 66) <= INT_SUM(0 to 66); INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66); end generate; D:DBLCADDER_128_128 port map ( OPA(0 to 127) => INT_SUMR(0 to 127), OPB(0 to 127) => INT_CARRYR(0 to 127), CIN => LOGIC_ZERO, PHI => PHI, SUM(0 to 127) => RESULT(0 to 127) ); end MULTIPLIER; ------------------------------------------------------------ -- END: Architectures used with the multiplier ------------------------------------------------------------ -- -- Modgen multiplier created Fri Aug 16 16:35:11 2002 -- ------------------------------------------------------------ -- START: Multiplier Entitiy ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -- START: Top entity ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_33_33 is generic (mulpipe : integer := 0); port(clk : in std_ulogic; holdn: in std_ulogic; X: in std_logic_vector(32 downto 0); Y: in std_logic_vector(32 downto 0); P: out std_logic_vector(65 downto 0)); end MUL_33_33; architecture A of MUL_33_33 is signal A: std_logic_vector(0 to 33); signal B: std_logic_vector(0 to 33); signal Q: std_logic_vector(0 to 127); begin U1: MULTIPLIER_34_34 generic map (mulpipe) port map(A,B,CLK, holdn ,Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(17); A(18) <= X(18); A(19) <= X(19); A(20) <= X(20); A(21) <= X(21); A(22) <= X(22); A(23) <= X(23); A(24) <= X(24); A(25) <= X(25); A(26) <= X(26); A(27) <= X(27); A(28) <= X(28); A(29) <= X(29); A(30) <= X(30); A(31) <= X(31); A(32) <= X(32); A(33) <= X(32); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(17); B(18) <= Y(18); B(19) <= Y(19); B(20) <= Y(20); B(21) <= Y(21); B(22) <= Y(22); B(23) <= Y(23); B(24) <= Y(24); B(25) <= Y(25); B(26) <= Y(26); B(27) <= Y(27); B(28) <= Y(28); B(29) <= Y(29); B(30) <= Y(30); B(31) <= Y(31); B(32) <= Y(32); B(33) <= Y(32); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); P(34) <= Q(34); P(35) <= Q(35); P(36) <= Q(36); P(37) <= Q(37); P(38) <= Q(38); P(39) <= Q(39); P(40) <= Q(40); P(41) <= Q(41); P(42) <= Q(42); P(43) <= Q(43); P(44) <= Q(44); P(45) <= Q(45); P(46) <= Q(46); P(47) <= Q(47); P(48) <= Q(48); P(49) <= Q(49); P(50) <= Q(50); P(51) <= Q(51); P(52) <= Q(52); P(53) <= Q(53); P(54) <= Q(54); P(55) <= Q(55); P(56) <= Q(56); P(57) <= Q(57); P(58) <= Q(58); P(59) <= Q(59); P(60) <= Q(60); P(61) <= Q(61); P(62) <= Q(62); P(63) <= Q(63); P(64) <= Q(64); P(65) <= Q(65); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity ADD32 is port(X: in std_logic_vector(31 downto 0); Y: in std_logic_vector(31 downto 0); CI: in std_logic; S: out std_logic_vector(31 downto 0); CO: out std_logic); end ADD32; architecture A of ADD32 is signal A,B,Q: std_logic_vector(0 to 31); signal CLK: std_logic; begin U1: DBLCADDER_32_32 port map(A,B,CI,CLK,Q,CO); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); B(0) <= Y(0); A(1) <= X(1); B(1) <= Y(1); A(2) <= X(2); B(2) <= Y(2); A(3) <= X(3); B(3) <= Y(3); A(4) <= X(4); B(4) <= Y(4); A(5) <= X(5); B(5) <= Y(5); A(6) <= X(6); B(6) <= Y(6); A(7) <= X(7); B(7) <= Y(7); A(8) <= X(8); B(8) <= Y(8); A(9) <= X(9); B(9) <= Y(9); A(10) <= X(10); B(10) <= Y(10); A(11) <= X(11); B(11) <= Y(11); A(12) <= X(12); B(12) <= Y(12); A(13) <= X(13); B(13) <= Y(13); A(14) <= X(14); B(14) <= Y(14); A(15) <= X(15); B(15) <= Y(15); A(16) <= X(16); B(16) <= Y(16); A(17) <= X(17); B(17) <= Y(17); A(18) <= X(18); B(18) <= Y(18); A(19) <= X(19); B(19) <= Y(19); A(20) <= X(20); B(20) <= Y(20); A(21) <= X(21); B(21) <= Y(21); A(22) <= X(22); B(22) <= Y(22); A(23) <= X(23); B(23) <= Y(23); A(24) <= X(24); B(24) <= Y(24); A(25) <= X(25); B(25) <= Y(25); A(26) <= X(26); B(26) <= Y(26); A(27) <= X(27); B(27) <= Y(27); A(28) <= X(28); B(28) <= Y(28); A(29) <= X(29); B(29) <= Y(29); A(30) <= X(30); B(30) <= Y(30); A(31) <= X(31); B(31) <= Y(31); S(0) <= Q(0); S(1) <= Q(1); S(2) <= Q(2); S(3) <= Q(3); S(4) <= Q(4); S(5) <= Q(5); S(6) <= Q(6); S(7) <= Q(7); S(8) <= Q(8); S(9) <= Q(9); S(10) <= Q(10); S(11) <= Q(11); S(12) <= Q(12); S(13) <= Q(13); S(14) <= Q(14); S(15) <= Q(15); S(16) <= Q(16); S(17) <= Q(17); S(18) <= Q(18); S(19) <= Q(19); S(20) <= Q(20); S(21) <= Q(21); S(22) <= Q(22); S(23) <= Q(23); S(24) <= Q(24); S(25) <= Q(25); S(26) <= Q(26); S(27) <= Q(27); S(28) <= Q(28); S(29) <= Q(29); S(30) <= Q(30); S(31) <= Q(31); end A; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.blocks.all; entity MUL_17_17 is generic (mulpipe : integer := 0); port(clk : in std_ulogic; holdn: in std_ulogic; X: in std_logic_vector(16 downto 0); Y: in std_logic_vector(16 downto 0); P: out std_logic_vector(33 downto 0)); end MUL_17_17; architecture A of MUL_17_17 is signal A: std_logic_vector(0 to 17); signal B: std_logic_vector(0 to 17); signal Q: std_logic_vector(0 to 63); begin U1: MULTIPLIER_18_18 generic map (mulpipe) port map(A,B,CLK, holdn, Q); -- std_logic_vector reversals to incorporate decreasing vectors A(0) <= X(0); A(1) <= X(1); A(2) <= X(2); A(3) <= X(3); A(4) <= X(4); A(5) <= X(5); A(6) <= X(6); A(7) <= X(7); A(8) <= X(8); A(9) <= X(9); A(10) <= X(10); A(11) <= X(11); A(12) <= X(12); A(13) <= X(13); A(14) <= X(14); A(15) <= X(15); A(16) <= X(16); A(17) <= X(16); B(0) <= Y(0); B(1) <= Y(1); B(2) <= Y(2); B(3) <= Y(3); B(4) <= Y(4); B(5) <= Y(5); B(6) <= Y(6); B(7) <= Y(7); B(8) <= Y(8); B(9) <= Y(9); B(10) <= Y(10); B(11) <= Y(11); B(12) <= Y(12); B(13) <= Y(13); B(14) <= Y(14); B(15) <= Y(15); B(16) <= Y(16); B(17) <= Y(16); P(0) <= Q(0); P(1) <= Q(1); P(2) <= Q(2); P(3) <= Q(3); P(4) <= Q(4); P(5) <= Q(5); P(6) <= Q(6); P(7) <= Q(7); P(8) <= Q(8); P(9) <= Q(9); P(10) <= Q(10); P(11) <= Q(11); P(12) <= Q(12); P(13) <= Q(13); P(14) <= Q(14); P(15) <= Q(15); P(16) <= Q(16); P(17) <= Q(17); P(18) <= Q(18); P(19) <= Q(19); P(20) <= Q(20); P(21) <= Q(21); P(22) <= Q(22); P(23) <= Q(23); P(24) <= Q(24); P(25) <= Q(25); P(26) <= Q(26); P(27) <= Q(27); P(28) <= Q(28); P(29) <= Q(29); P(30) <= Q(30); P(31) <= Q(31); P(32) <= Q(32); P(33) <= Q(33); end A;
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2014 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file cc_cmplr_v3_0_e58a4eb9f6488d2d.vhd when simulating -- the core, cc_cmplr_v3_0_e58a4eb9f6488d2d. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY cc_cmplr_v3_0_e58a4eb9f6488d2d IS PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0); s_axis_data_tvalid : IN STD_LOGIC; s_axis_data_tready : OUT STD_LOGIC; s_axis_data_tlast : IN STD_LOGIC; m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tlast : OUT STD_LOGIC; event_tlast_unexpected : OUT STD_LOGIC; event_tlast_missing : OUT STD_LOGIC ); END cc_cmplr_v3_0_e58a4eb9f6488d2d; ARCHITECTURE cc_cmplr_v3_0_e58a4eb9f6488d2d_a OF cc_cmplr_v3_0_e58a4eb9f6488d2d IS -- synthesis translate_off COMPONENT wrapped_cc_cmplr_v3_0_e58a4eb9f6488d2d PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0); s_axis_data_tvalid : IN STD_LOGIC; s_axis_data_tready : OUT STD_LOGIC; s_axis_data_tlast : IN STD_LOGIC; m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tlast : OUT STD_LOGIC; event_tlast_unexpected : OUT STD_LOGIC; event_tlast_missing : OUT STD_LOGIC ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_cc_cmplr_v3_0_e58a4eb9f6488d2d USE ENTITY XilinxCoreLib.cic_compiler_v3_0(behavioral) GENERIC MAP ( c_c1 => 61, c_c2 => 61, c_c3 => 61, c_c4 => 0, c_c5 => 0, c_c6 => 0, c_clk_freq => 2240, c_component_name => "cc_cmplr_v3_0_e58a4eb9f6488d2d", c_diff_delay => 2, c_family => "artix7", c_filter_type => 1, c_has_aclken => 1, c_has_aresetn => 0, c_has_dout_tready => 0, c_has_rounding => 0, c_i1 => 61, c_i2 => 61, c_i3 => 61, c_i4 => 0, c_i5 => 0, c_i6 => 0, c_input_width => 24, c_m_axis_data_tdata_width => 64, c_m_axis_data_tuser_width => 16, c_max_rate => 2500, c_min_rate => 2500, c_num_channels => 4, c_num_stages => 3, c_output_width => 61, c_rate => 2500, c_rate_type => 0, c_s_axis_config_tdata_width => 1, c_s_axis_data_tdata_width => 24, c_sample_freq => 1, c_use_dsp => 1, c_use_streaming_interface => 1, c_xdevicefamily => "artix7" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_cc_cmplr_v3_0_e58a4eb9f6488d2d PORT MAP ( aclk => aclk, aclken => aclken, s_axis_data_tdata => s_axis_data_tdata, s_axis_data_tvalid => s_axis_data_tvalid, s_axis_data_tready => s_axis_data_tready, s_axis_data_tlast => s_axis_data_tlast, m_axis_data_tdata => m_axis_data_tdata, m_axis_data_tuser => m_axis_data_tuser, m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tlast => m_axis_data_tlast, event_tlast_unexpected => event_tlast_unexpected, event_tlast_missing => event_tlast_missing ); -- synthesis translate_on END cc_cmplr_v3_0_e58a4eb9f6488d2d_a;
entity default1 is end entity; architecture test of default1 is signal s : positive; begin process is type mat2x2 is array (1 to 2, 1 to 2) of natural; type int_array10 is array (1 to 10) of positive; type int_array5 is array (5 to 7) of positive; variable x : integer; variable v : bit_vector(1 to 3); variable m : mat2x2; variable p : int_array10; variable q : int_array5; begin assert s = 1; assert x = integer'left; assert v = ('0', '0', '0'); assert m = ((0, 0), (0, 0)); assert p = (1 to 10 => 1); assert q = (5 to 7 => 1); assert p'left = 1; assert p'right = 10; assert q'left = 5; assert q'right = 7; assert q'length = 3; s <= 4; -- FIXME wait; end process; end architecture;
entity default1 is end entity; architecture test of default1 is signal s : positive; begin process is type mat2x2 is array (1 to 2, 1 to 2) of natural; type int_array10 is array (1 to 10) of positive; type int_array5 is array (5 to 7) of positive; variable x : integer; variable v : bit_vector(1 to 3); variable m : mat2x2; variable p : int_array10; variable q : int_array5; begin assert s = 1; assert x = integer'left; assert v = ('0', '0', '0'); assert m = ((0, 0), (0, 0)); assert p = (1 to 10 => 1); assert q = (5 to 7 => 1); assert p'left = 1; assert p'right = 10; assert q'left = 5; assert q'right = 7; assert q'length = 3; s <= 4; -- FIXME wait; end process; end architecture;
entity default1 is end entity; architecture test of default1 is signal s : positive; begin process is type mat2x2 is array (1 to 2, 1 to 2) of natural; type int_array10 is array (1 to 10) of positive; type int_array5 is array (5 to 7) of positive; variable x : integer; variable v : bit_vector(1 to 3); variable m : mat2x2; variable p : int_array10; variable q : int_array5; begin assert s = 1; assert x = integer'left; assert v = ('0', '0', '0'); assert m = ((0, 0), (0, 0)); assert p = (1 to 10 => 1); assert q = (5 to 7 => 1); assert p'left = 1; assert p'right = 10; assert q'left = 5; assert q'right = 7; assert q'length = 3; s <= 4; -- FIXME wait; end process; end architecture;
entity default1 is end entity; architecture test of default1 is signal s : positive; begin process is type mat2x2 is array (1 to 2, 1 to 2) of natural; type int_array10 is array (1 to 10) of positive; type int_array5 is array (5 to 7) of positive; variable x : integer; variable v : bit_vector(1 to 3); variable m : mat2x2; variable p : int_array10; variable q : int_array5; begin assert s = 1; assert x = integer'left; assert v = ('0', '0', '0'); assert m = ((0, 0), (0, 0)); assert p = (1 to 10 => 1); assert q = (5 to 7 => 1); assert p'left = 1; assert p'right = 10; assert q'left = 5; assert q'right = 7; assert q'length = 3; s <= 4; -- FIXME wait; end process; end architecture;
entity default1 is end entity; architecture test of default1 is signal s : positive; begin process is type mat2x2 is array (1 to 2, 1 to 2) of natural; type int_array10 is array (1 to 10) of positive; type int_array5 is array (5 to 7) of positive; variable x : integer; variable v : bit_vector(1 to 3); variable m : mat2x2; variable p : int_array10; variable q : int_array5; begin assert s = 1; assert x = integer'left; assert v = ('0', '0', '0'); assert m = ((0, 0), (0, 0)); assert p = (1 to 10 => 1); assert q = (5 to 7 => 1); assert p'left = 1; assert p'right = 10; assert q'left = 5; assert q'right = 7; assert q'length = 3; s <= 4; -- FIXME wait; end process; end architecture;
---------------------------------------------------------------------------------- -- Company: -- Engineer: StrayWarrior -- -- Create Date: 23:36:20 11/21/2015 -- Design Name: -- Module Name: PC_REG - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity PC_REG is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; stall : in STD_LOGIC; PC_in : in STD_LOGIC_VECTOR (15 downto 0); PC_out : out STD_LOGIC_VECTOR (15 downto 0) ); end PC_REG; architecture Behavioral of PC_REG is begin process (reset, clk) begin if (reset = '0') then PC_out <= (others => '0'); elsif (clk'event and clk = '1' and stall = '0') then PC_out <= PC_in; end if; end process; end Behavioral;
-- -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- Package that contains the program object code in VHDL constant format. use work.obj_code_pkg.all; entity ZYBO_TOP is port( -- Clock from Ethernet PHY. @note1. clk_125MHz_i : in std_logic; -- Pushbuttons. buttons_i : in std_logic_vector(3 downto 0); -- Switches. switches_i : in std_logic_vector(3 downto 0); -- LEDs. leds_o : out std_logic_vector(3 downto 0); -- PMOD E (Std) connector -- PMOD UART (Digilent). pmod_e_2_txd_o : out std_logic; pmod_e_3_rxd_i : in std_logic ); end entity ZYBO_TOP; architecture rtl of ZYBO_TOP is signal clk : std_logic; signal reset : std_logic; signal extint : std_logic_vector(3 downto 0); signal iop1 : std_logic_vector(7 downto 0); signal iop2 : std_logic_vector(7 downto 0); begin clk <= clk_125MHz_i; reset <= buttons_i(3); -- Light8080 MCU and glue logic ---------------------------------------------- mcu: entity work.mcu80 generic map ( OBJ_CODE => work.obj_code_pkg.object_code, UART_HARDWIRED => false, -- UART baud rate NOT run-time programmable. UART_IRQ_LINE => 3, -- UART uses IRQ3 line of irq controller. BAUD_RATE => 115200, -- UART baud rate. CLOCK_FREQ => 125E6 -- Clock frequency in Hz. ) port map ( clk => clk, reset => reset, p1_i => iop1, p2_o => iop2, extint_i => extint, txd_o => pmod_e_2_txd_o, rxd_i => pmod_e_3_rxd_i ); extint <= iop2(7 downto 4); iop1(3 downto 0) <= switches_i; iop1(7 downto 4) <= buttons_i; -- Smoke test logic (to be removed when up and running) ---------------------- process(clk) begin if clk'event and clk='1' then if reset = '1' then leds_o <= "1010"; else leds_o <= iop2(3 downto 0); end if; end if; end process; end; -- @note1: Clock active if PHYRSTB is high. PHYRSTB pin unused, pulled high.
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:user:vga_color_test:1.0 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY system_vga_color_test_0_0 IS PORT ( clk_25 : IN STD_LOGIC; xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ); END system_vga_color_test_0_0; ARCHITECTURE system_vga_color_test_0_0_arch OF system_vga_color_test_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT vga_color_test IS GENERIC ( H_SIZE : INTEGER; V_SIZE : INTEGER ); PORT ( clk_25 : IN STD_LOGIC; xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ); END COMPONENT vga_color_test; BEGIN U0 : vga_color_test GENERIC MAP ( H_SIZE => 640, V_SIZE => 480 ) PORT MAP ( clk_25 => clk_25, xaddr => xaddr, yaddr => yaddr, rgb => rgb ); END system_vga_color_test_0_0_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:user:vga_color_test:1.0 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY system_vga_color_test_0_0 IS PORT ( clk_25 : IN STD_LOGIC; xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ); END system_vga_color_test_0_0; ARCHITECTURE system_vga_color_test_0_0_arch OF system_vga_color_test_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT vga_color_test IS GENERIC ( H_SIZE : INTEGER; V_SIZE : INTEGER ); PORT ( clk_25 : IN STD_LOGIC; xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ); END COMPONENT vga_color_test; BEGIN U0 : vga_color_test GENERIC MAP ( H_SIZE => 640, V_SIZE => 480 ) PORT MAP ( clk_25 => clk_25, xaddr => xaddr, yaddr => yaddr, rgb => rgb ); END system_vga_color_test_0_0_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:user:vga_color_test:1.0 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY system_vga_color_test_0_0 IS PORT ( clk_25 : IN STD_LOGIC; xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ); END system_vga_color_test_0_0; ARCHITECTURE system_vga_color_test_0_0_arch OF system_vga_color_test_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT vga_color_test IS GENERIC ( H_SIZE : INTEGER; V_SIZE : INTEGER ); PORT ( clk_25 : IN STD_LOGIC; xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ); END COMPONENT vga_color_test; BEGIN U0 : vga_color_test GENERIC MAP ( H_SIZE => 640, V_SIZE => 480 ) PORT MAP ( clk_25 => clk_25, xaddr => xaddr, yaddr => yaddr, rgb => rgb ); END system_vga_color_test_0_0_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:user:vga_color_test:1.0 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY system_vga_color_test_0_0 IS PORT ( clk_25 : IN STD_LOGIC; xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ); END system_vga_color_test_0_0; ARCHITECTURE system_vga_color_test_0_0_arch OF system_vga_color_test_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT vga_color_test IS GENERIC ( H_SIZE : INTEGER; V_SIZE : INTEGER ); PORT ( clk_25 : IN STD_LOGIC; xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ); END COMPONENT vga_color_test; BEGIN U0 : vga_color_test GENERIC MAP ( H_SIZE => 640, V_SIZE => 480 ) PORT MAP ( clk_25 => clk_25, xaddr => xaddr, yaddr => yaddr, rgb => rgb ); END system_vga_color_test_0_0_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:user:vga_color_test:1.0 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY system_vga_color_test_0_0 IS PORT ( clk_25 : IN STD_LOGIC; xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ); END system_vga_color_test_0_0; ARCHITECTURE system_vga_color_test_0_0_arch OF system_vga_color_test_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT vga_color_test IS GENERIC ( H_SIZE : INTEGER; V_SIZE : INTEGER ); PORT ( clk_25 : IN STD_LOGIC; xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ); END COMPONENT vga_color_test; BEGIN U0 : vga_color_test GENERIC MAP ( H_SIZE => 640, V_SIZE => 480 ) PORT MAP ( clk_25 => clk_25, xaddr => xaddr, yaddr => yaddr, rgb => rgb ); END system_vga_color_test_0_0_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:user:vga_color_test:1.0 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY system_vga_color_test_0_0 IS PORT ( clk_25 : IN STD_LOGIC; xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ); END system_vga_color_test_0_0; ARCHITECTURE system_vga_color_test_0_0_arch OF system_vga_color_test_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT vga_color_test IS GENERIC ( H_SIZE : INTEGER; V_SIZE : INTEGER ); PORT ( clk_25 : IN STD_LOGIC; xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ); END COMPONENT vga_color_test; BEGIN U0 : vga_color_test GENERIC MAP ( H_SIZE => 640, V_SIZE => 480 ) PORT MAP ( clk_25 => clk_25, xaddr => xaddr, yaddr => yaddr, rgb => rgb ); END system_vga_color_test_0_0_arch;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library work; use work.rv_components.all; use work.utils.all; use work.constants_pkg.all; entity oimm_register is generic ( ADDRESS_WIDTH : positive; DATA_WIDTH : positive; LOG2_BURSTLENGTH : positive := 2; REQUEST_REGISTER : request_register_type; RETURN_REGISTER : boolean ); port ( clk : in std_logic; reset : in std_logic; register_idle : out std_logic; --ORCA-internal memory-mapped slave slave_oimm_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); slave_oimm_burstlength : in std_logic_vector(LOG2_BURSTLENGTH downto 0) := (0 => '1', others => '0'); slave_oimm_burstlength_minus1 : in std_logic_vector(LOG2_BURSTLENGTH-1 downto 0) := (others => '0'); slave_oimm_byteenable : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); slave_oimm_requestvalid : in std_logic; slave_oimm_readnotwrite : in std_logic; slave_oimm_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0); slave_oimm_writelast : in std_logic := '1'; slave_oimm_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0); slave_oimm_readdatavalid : out std_logic; slave_oimm_waitrequest : out std_logic; --ORCA-internal memory-mapped master master_oimm_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); master_oimm_burstlength : out std_logic_vector(LOG2_BURSTLENGTH downto 0); master_oimm_burstlength_minus1 : out std_logic_vector(LOG2_BURSTLENGTH-1 downto 0); master_oimm_byteenable : out std_logic_vector((DATA_WIDTH/8)-1 downto 0); master_oimm_requestvalid : out std_logic; master_oimm_readnotwrite : out std_logic; master_oimm_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0); master_oimm_writelast : out std_logic; master_oimm_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0); master_oimm_readdatavalid : in std_logic; master_oimm_waitrequest : in std_logic ); end entity oimm_register; architecture rtl of oimm_register is signal slave_oimm_waitrequest_signal : std_logic; signal master_oimm_requestvalid_signal : std_logic; begin slave_oimm_waitrequest <= slave_oimm_waitrequest_signal; master_oimm_requestvalid <= master_oimm_requestvalid_signal; ----------------------------------------------------------------------------- -- Optional Memory Request Register ----------------------------------------------------------------------------- --Passthrough, lowest fmax but no extra resources or added latency. no_request_register_gen : if REQUEST_REGISTER = OFF generate master_oimm_address <= slave_oimm_address; master_oimm_burstlength <= slave_oimm_burstlength; master_oimm_burstlength_minus1 <= slave_oimm_burstlength_minus1; master_oimm_byteenable <= slave_oimm_byteenable; master_oimm_requestvalid_signal <= slave_oimm_requestvalid; master_oimm_readnotwrite <= slave_oimm_readnotwrite; master_oimm_writedata <= slave_oimm_writedata; master_oimm_writelast <= slave_oimm_writelast; slave_oimm_waitrequest_signal <= master_oimm_waitrequest; register_idle <= '1'; --idle is state-only end generate no_request_register_gen; --Light register; breaks waitrequest/stall combinational path but does not break --address/etc. path. Does not add latency if slave is not asserting --waitrequest, but will reduce throughput if the slave does. light_request_register_gen : if REQUEST_REGISTER = LIGHT generate signal slave_oimm_address_held : std_logic_vector(ADDRESS_WIDTH-1 downto 0); signal slave_oimm_burstlength_held : std_logic_vector(LOG2_BURSTLENGTH downto 0); signal slave_oimm_burstlength_minus1_held : std_logic_vector(LOG2_BURSTLENGTH-1 downto 0); signal slave_oimm_byteenable_held : std_logic_vector((DATA_WIDTH/8)-1 downto 0); signal slave_oimm_requestvalid_held : std_logic; signal slave_oimm_readnotwrite_held : std_logic; signal slave_oimm_writedata_held : std_logic_vector(DATA_WIDTH-1 downto 0); signal slave_oimm_writelast_held : std_logic; begin master_oimm_address <= slave_oimm_address_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_address; master_oimm_burstlength <= slave_oimm_burstlength_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_burstlength; master_oimm_burstlength_minus1 <= slave_oimm_burstlength_minus1_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_burstlength_minus1; master_oimm_byteenable <= slave_oimm_byteenable_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_byteenable; master_oimm_requestvalid_signal <= slave_oimm_requestvalid_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_requestvalid; master_oimm_readnotwrite <= slave_oimm_readnotwrite_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_readnotwrite; master_oimm_writedata <= slave_oimm_writedata_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_writedata; master_oimm_writelast <= slave_oimm_writelast_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_writelast; process(clk) begin if rising_edge(clk) then --When coming out of reset, need to put waitrequest down if slave_oimm_requestvalid_held = '0' then slave_oimm_waitrequest_signal <= '0'; end if; if master_oimm_waitrequest = '0' then slave_oimm_waitrequest_signal <= '0'; end if; if slave_oimm_waitrequest_signal = '0' then slave_oimm_address_held <= slave_oimm_address; slave_oimm_burstlength_held <= slave_oimm_burstlength; slave_oimm_burstlength_minus1_held <= slave_oimm_burstlength_minus1; slave_oimm_byteenable_held <= slave_oimm_byteenable; slave_oimm_requestvalid_held <= slave_oimm_requestvalid; slave_oimm_readnotwrite_held <= slave_oimm_readnotwrite; slave_oimm_writedata_held <= slave_oimm_writedata; slave_oimm_writelast_held <= slave_oimm_writelast; slave_oimm_waitrequest_signal <= master_oimm_waitrequest and slave_oimm_requestvalid; end if; if reset = '1' then slave_oimm_requestvalid_held <= '0'; slave_oimm_waitrequest_signal <= '1'; end if; end if; end process; register_idle <= not slave_oimm_waitrequest_signal; --idle is state-only end generate light_request_register_gen; --Full register; breaks waitrequest/stall combinational path and address/etc. --path. Always adds one cycle of latency but does not reduce throughput. full_request_register_gen : if REQUEST_REGISTER = FULL generate signal registered_oimm_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0); signal registered_oimm_burstlength : std_logic_vector(LOG2_BURSTLENGTH downto 0); signal registered_oimm_burstlength_minus1 : std_logic_vector(LOG2_BURSTLENGTH-1 downto 0); signal registered_oimm_byteenable : std_logic_vector((DATA_WIDTH/8)-1 downto 0); signal registered_oimm_requestvalid : std_logic; signal registered_oimm_readnotwrite : std_logic; signal registered_oimm_writedata : std_logic_vector(DATA_WIDTH-1 downto 0); signal registered_oimm_writelast : std_logic; begin process(clk) begin if rising_edge(clk) then --When coming out of reset, need to put waitrequest down if registered_oimm_requestvalid = '0' then slave_oimm_waitrequest_signal <= '0'; end if; if master_oimm_waitrequest = '0' then master_oimm_requestvalid_signal <= '0'; if registered_oimm_requestvalid = '1' then master_oimm_address <= registered_oimm_address; master_oimm_burstlength <= registered_oimm_burstlength; master_oimm_burstlength_minus1 <= registered_oimm_burstlength_minus1; master_oimm_byteenable <= registered_oimm_byteenable; master_oimm_readnotwrite <= registered_oimm_readnotwrite; master_oimm_requestvalid_signal <= registered_oimm_requestvalid; master_oimm_writedata <= registered_oimm_writedata; master_oimm_writelast <= registered_oimm_writelast; registered_oimm_requestvalid <= '0'; slave_oimm_waitrequest_signal <= '0'; else master_oimm_address <= slave_oimm_address; master_oimm_burstlength <= slave_oimm_burstlength; master_oimm_burstlength_minus1 <= slave_oimm_burstlength_minus1; master_oimm_byteenable <= slave_oimm_byteenable; master_oimm_readnotwrite <= slave_oimm_readnotwrite; master_oimm_requestvalid_signal <= slave_oimm_requestvalid and (not slave_oimm_waitrequest_signal); master_oimm_writedata <= slave_oimm_writedata; master_oimm_writelast <= slave_oimm_writelast; end if; else if slave_oimm_waitrequest_signal = '0' then if master_oimm_requestvalid_signal = '1' then registered_oimm_address <= slave_oimm_address; registered_oimm_burstlength <= slave_oimm_burstlength; registered_oimm_burstlength_minus1 <= slave_oimm_burstlength_minus1; registered_oimm_byteenable <= slave_oimm_byteenable; registered_oimm_requestvalid <= slave_oimm_requestvalid; registered_oimm_readnotwrite <= slave_oimm_readnotwrite; registered_oimm_writedata <= slave_oimm_writedata; registered_oimm_writelast <= slave_oimm_writelast; slave_oimm_waitrequest_signal <= slave_oimm_requestvalid; else master_oimm_address <= slave_oimm_address; master_oimm_burstlength <= slave_oimm_burstlength; master_oimm_burstlength_minus1 <= slave_oimm_burstlength_minus1; master_oimm_byteenable <= slave_oimm_byteenable; master_oimm_readnotwrite <= slave_oimm_readnotwrite; master_oimm_requestvalid_signal <= slave_oimm_requestvalid; master_oimm_writedata <= slave_oimm_writedata; master_oimm_writelast <= slave_oimm_writelast; end if; end if; end if; if reset = '1' then master_oimm_requestvalid_signal <= '0'; registered_oimm_requestvalid <= '0'; slave_oimm_waitrequest_signal <= '1'; end if; end if; end process; register_idle <= not master_oimm_requestvalid_signal; --idle is state-only end generate full_request_register_gen; ----------------------------------------------------------------------------- -- Optional Data Memory Return Register ----------------------------------------------------------------------------- no_return_register_gen : if not RETURN_REGISTER generate slave_oimm_readdata <= master_oimm_readdata; slave_oimm_readdatavalid <= master_oimm_readdatavalid; end generate no_return_register_gen; return_register_gen : if RETURN_REGISTER generate process(clk) begin if rising_edge(clk) then slave_oimm_readdata <= master_oimm_readdata; slave_oimm_readdatavalid <= master_oimm_readdatavalid; end if; end process; end generate return_register_gen; end architecture rtl;
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity nfa_forward_buckets_if_ap_fifo_uw is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 4; DEPTH : integer := 16); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0)); end entity; architecture rtl of nfa_forward_buckets_if_ap_fifo_uw is type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal mStorage : memtype; signal mInPtr, mNextInPtr, mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0); signal internal_empty_n, internal_full_n : STD_LOGIC; signal internal_use_word : STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0); begin mNextInPtr <= mInPtr + 1; if_dout <= mStorage(CONV_INTEGER(mOutPtr)); if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; use_word <= internal_use_word; process (clk, reset) begin if reset = '1' then mInPtr <= (others => '0'); mOutPtr <= (others => '0'); internal_use_word <= (others => '0'); else if clk'event and clk = '1' then if if_read = '1' and internal_empty_n = '1' then mOutPtr <= mOutPtr + 1; end if; if if_write = '1' and internal_full_n = '1' then mStorage(CONV_INTEGER(mInPtr)) <= if_din; mInPtr <= mNextInPtr; end if; if (if_read = '1' and if_write = '0') then internal_use_word <= internal_use_word - '1'; elsif (if_read = '0' and if_write = '1') then internal_use_word <= internal_use_word + '1'; end if; end if; end if; end process; process (mInPtr, mOutPtr, mNextInPtr) begin if mInPtr = mOutPtr then internal_empty_n <= '0'; else internal_empty_n <= '1'; end if; if mNextInPtr = mOutPtr then internal_full_n <= '0'; else internal_full_n <= '1'; end if; end process; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity nfa_forward_buckets_if_plb_master_if is generic ( C_PLB_AWIDTH : integer := 32; C_PLB_DWIDTH : integer := 64; PLB_ADDR_SHIFT : integer := 3 ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete PLB_Clk : in std_logic; PLB_Rst : in std_logic; M_abort : out std_logic; M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1); M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1); M_busLock : out std_logic; M_lockErr : out std_logic; M_MSize : out std_logic_vector(0 to 1); M_priority : out std_logic_vector(0 to 1); M_rdBurst : out std_logic; M_request : out std_logic; M_RNW : out std_logic; M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_wrBurst : out std_logic; M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1); PLB_MBusy : in std_logic; PLB_MWrBTerm : in std_logic; PLB_MWrDAck : in std_logic; PLB_MAddrAck : in std_logic; PLB_MRdBTerm : in std_logic; PLB_MRdDAck : in std_logic; PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1)); PLB_MRdWdAddr : in std_logic_vector(0 to 3); PLB_MRearbitrate : in std_logic; PLB_MSSize : in std_logic_vector(0 to 1); -- signals from user logic BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data BUS_address : in std_logic_vector(31 downto 0); -- physical address BUS_size : in std_logic_vector(31 downto 0); -- burst size of word BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8-1 downto 0); -- Bus write data byte enable BUS_req_full_n : out std_logic; -- req Fifo full BUS_req_push : in std_logic; -- req Fifo push (new request in) BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type BUS_rsp_empty_n: out std_logic; -- return data FIFO empty BUS_rsp_pop : in std_logic -- return data FIFO pop ); attribute SIGIS : string; attribute SIGIS of PLB_Clk : signal is "Clk"; attribute SIGIS of PLB_Rst : signal is "Rst"; end entity; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of nfa_forward_buckets_if_plb_master_if is component nfa_forward_buckets_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 4; DEPTH : integer := 16); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end component; component nfa_forward_buckets_if_ap_fifo_uw is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 4; DEPTH : integer := 16); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0)); end component; constant PLB_DW : integer := C_PLB_DWIDTH; constant PLB_BYTE_COUNT : integer := PLB_DW/8; constant REQ_FIFO_WIDTH : integer := 1 + PLB_BYTE_COUNT + 32 + 32; --nRW + BE + 32 bits phy addr + size constant FIFO_ADDR_WIDTH : integer := 5; constant FIFO_DEPTH : integer := 32; -- request FIFO signal req_fifo_empty_n : STD_LOGIC; signal req_fifo_pop : STD_LOGIC; signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0); signal req_fifo_full_n : STD_LOGIC; signal req_fifo_push : STD_LOGIC; signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0); -- burst write counter (only push burst data in and ignore all burst write request except the first one) signal req_burst_write: STD_LOGIC; -- whether last request is a burst write signal req_burst_write_counter: STD_LOGIC_VECTOR(31 downto 0); -- write data FIFO (for bus write data) signal wd_fifo_empty_n : STD_LOGIC; signal wd_fifo_pop : STD_LOGIC; signal wd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal wd_fifo_dout_mirror : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal wd_fifo_full_n : STD_LOGIC; signal wd_fifo_push : STD_LOGIC; signal wd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal wd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0); -- read data FIFO (for bus read returned data) signal rd_fifo_empty_n : STD_LOGIC; signal rd_fifo_pop : STD_LOGIC; signal rd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal rd_fifo_full_n : STD_LOGIC; signal rd_fifo_push : STD_LOGIC; signal rd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal rd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0); signal req_address : std_logic_vector(0 to C_PLB_AWIDTH -1);-- bus request word address signal req_fifo_dout_req_size : std_logic_vector(31 downto 0); -- req_size -1 signal req_size : std_logic_vector(0 to 27); -- burst size of 16 word block signal request, req_nRW: std_logic; signal req_BE : std_logic_vector(PLB_BYTE_COUNT-1 downto 0); signal pending_rd_req_burst_mode: std_logic; signal pending_rd_req_burst_size: std_logic_vector(3 downto 0); signal pending_wr_req_burst_mode: std_logic; signal pending_wr_req_burst_size: std_logic_vector(3 downto 0); signal pending_read, pending_write: std_logic; signal burst_mode, burst_last : std_logic; signal burst_size : std_logic_vector(3 downto 0); -- maximum burst 16 words --signals for write data mirror signal conv_mode_comb : std_logic_vector(1 downto 0); -- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64 signal conv_counter_comb: std_logic_vector(1 downto 0); signal wr_data_phase : std_logic; signal dataConv_last: std_logic; signal dp_dataConv_last: std_logic; signal dp_dataConv_word_addr: std_logic_vector(1 downto 0); signal dp_dataConv_wd_conv_mode : std_logic_vector(1 downto 0); -- 00:NO conv, 01:128/32, 10:64/32, 11:128/64 signal dp_dataConv_wd_burst_counter: std_logic_vector(1 downto 0); signal dp_dataConv_wd_BE: std_logic_vector(PLB_BYTE_COUNT-1 downto 0); signal dp_PLB_MSSize : std_logic_vector(1 downto 0); --signals for read data mirror signal PLB_MRdDAck_reg : std_logic; signal dp_dataConv_rd_conv_mode : std_logic_vector(1 downto 0);-- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64 signal dp_dataConv_rd_burst_counter, dp_dataConv_rd_burst_counter_reg: std_logic_vector(1 downto 0); signal PLB_MRdDBus_reverse : std_logic_vector(PLB_DW-1 downto 0); -- signals with dp_ prefix stand for data phase signals -- signals with req_ prefix stand for request phase signals begin -- interface to user logic BUS_RdData <= rd_fifo_dout; BUS_req_full_n <= req_fifo_full_n and wd_fifo_full_n; BUS_rsp_nRW <= '0'; BUS_rsp_empty_n <= rd_fifo_empty_n; -- interface to PLB M_abort <= '0'; M_busLock <= '0'; M_lockErr <= '0'; M_MSize <= "01"; -- 00:32b dev, 01:64b, 10:128b, 11:256b M_size <= "0000" when (burst_mode = '0' or burst_size = "0000") else "1011"; -- single rw or 64 bits burst M_type <= "000"; -- memory trans M_priority <= "00"; M_RNW <= not req_nRW; M_rdBurst <= '1' when pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /="00") else '0'; process (PLB_MSSize) begin M_wrBurst <= '0'; if (pending_wr_req_burst_mode = '1' and (pending_wr_req_burst_size /= "0000" or dp_dataConv_wd_burst_counter /="00")) then M_wrBurst <= '1'; elsif (request = '1' and req_nRW = '1' and pending_write = '0' and burst_mode = '1' and burst_size /="0000" and wd_fifo_use_word > burst_size) then M_wrBurst <= '1'; end if; end process; -- write data mirror section process (PLB_MSSize) begin if (C_PLB_DWIDTH = 64 and PLB_MSSize = "00") then conv_mode_comb <= "10"; -- conv 64:32 conv_counter_comb <= "01"; elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "01") then conv_mode_comb <= "11"; -- conv 128:64 conv_counter_comb <= "01"; elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "00") then conv_mode_comb <= "01"; -- conv 128:32 conv_counter_comb <= "11"; else conv_mode_comb <= "00"; -- do not need conv conv_counter_comb <= "00"; end if; end process; process (burst_mode, burst_size, conv_mode_comb, req_address, req_BE) begin dataConv_last <= '0'; if (burst_mode = '0' or burst_size = "0000") then if (conv_mode_comb = "00") then -- no conv dataConv_last <= '1'; elsif (conv_mode_comb = "10") then -- 64:32 conv if (req_address(29)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then dataConv_last <= '1'; end if; elsif (conv_mode_comb = "11") then -- 128:64 conv if (req_address(28)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then dataConv_last <= '1'; end if; elsif (conv_mode_comb = "01") then -- 128:32 conv if (req_address(28 to 29) = "00" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT*3/4)) then dataConv_last <= '1'; elsif (req_address(28 to 29) = "01" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then dataConv_last <= '1'; elsif (req_address(28 to 29) = "10" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT*3/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/4)) then dataConv_last <= '1'; elsif (req_address(28 to 29) = "11") then dataConv_last <= '1'; end if; end if; end if; end process; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then dp_dataConv_word_addr <= (others => '0'); dp_dataConv_wd_conv_mode <= (others =>'0'); dp_dataConv_wd_burst_counter <= (others => '0'); dp_dataConv_wd_BE <= (others => '0'); dp_dataConv_last <= '0'; wr_data_phase <= '0'; elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '1') then dp_dataConv_wd_BE <= req_BE; dp_dataConv_last <= dataConv_last; end if; if (PLB_MAddrAck = '1' and req_nRW = '1' and (PLB_MWrDAck = '0' or (burst_mode = '1' and burst_size /= "0000"))) then wr_data_phase <= '1'; end if; if (PLB_MWrDAck = '1' and wr_data_phase = '1') then if ((pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or (pending_wr_req_burst_mode = '0')) then wr_data_phase <= '0'; end if; end if; if (PLB_MAddrAck = '1' and req_nRW = '1' and dp_dataConv_wd_conv_mode = "00") then if (PLB_MWrDAck = '0') then -- only AddrAck asserted dp_dataConv_wd_conv_mode <= conv_mode_comb; dp_dataConv_word_addr <= req_address(28 to 29); dp_dataConv_wd_burst_counter <= conv_counter_comb; else -- Xilinx PLB v4.6 support assert addrAck & wrDAck at the same cycle if (dataConv_last = '0') then dp_dataConv_wd_conv_mode <= conv_mode_comb; end if; if (PLB_MSSize = "00") then -- 32 bits slave dp_dataConv_word_addr <= req_address(28 to 29) +1; elsif (PLB_MSSize = "01") then -- 64 bits slave dp_dataConv_word_addr <= req_address(28 to 29) +2; end if; if (conv_mode_comb /= "00") then -- need conv dp_dataConv_wd_burst_counter <= conv_counter_comb -1; end if; end if; end if; if (wr_data_phase = '1' and PLB_MWrDAck = '1' and ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or (pending_wr_req_burst_mode = '0' and dp_dataConv_last = '1'))) then dp_dataConv_wd_conv_mode <= "00"; end if; if (PLB_MWrDAck = '1' and wr_data_phase = '1') then if (dp_PLB_MSSize = "01") then -- 64 bits slave dp_dataConv_word_addr <= dp_dataConv_word_addr +2; else dp_dataConv_word_addr <= dp_dataConv_word_addr +1; end if; if ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size /= "0000") or dp_dataConv_wd_burst_counter /= "00") then if (dp_dataConv_wd_burst_counter = "00") then if (dp_dataConv_wd_conv_mode = "01") then -- 128/32 dp_dataConv_wd_burst_counter <= "11"; elsif (dp_dataConv_wd_conv_mode(1) = '1') then -- 64/32 or 128/64 dp_dataConv_wd_burst_counter <= "01"; end if; else dp_dataConv_wd_burst_counter <= dp_dataConv_wd_burst_counter -1; end if; end if; end if; end if; end process; process(PLB_MWrDAck, wr_data_phase, dp_dataConv_wd_burst_counter, burst_mode, conv_counter_comb, conv_mode_comb, req_BE) begin wd_fifo_pop <= '0'; if (PLB_MWrDAck = '1') then if (wr_data_phase = '1') then if ((pending_wr_req_burst_mode = '1' and dp_dataConv_wd_burst_counter = "00") or (dp_dataConv_wd_conv_mode /= "00" and dp_dataConv_last = '1') or dp_dataConv_wd_conv_mode = "00" )then wd_fifo_pop <= '1'; end if; else -- got addrAck and wrDAck at the same cycle if (burst_mode = '1' and burst_size /= "0000" and conv_counter_comb = "00") then wd_fifo_pop <= '1'; elsif ((burst_mode = '0' or burst_size = "0000") and dataConv_last = '1') then wd_fifo_pop <= '1'; end if; end if; end if; end process; process(wd_fifo_dout, wr_data_phase, req_address, dp_dataConv_wd_conv_mode, dp_dataConv_word_addr) begin wd_fifo_dout_mirror <= wd_fifo_dout; if (wr_data_phase = '0') then -- we do not know slave bus width, perform default convert if (C_PLB_DWIDTH = 32) then wd_fifo_dout_mirror <= wd_fifo_dout; elsif (C_PLB_DWIDTH = 64) then if (req_address(29) = '0') then wd_fifo_dout_mirror <= wd_fifo_dout; else wd_fifo_dout_mirror(PLB_DW/2-1 downto 0) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2); wd_fifo_dout_mirror(PLB_DW-1 downto PLB_DW/2) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2); end if; elsif (C_PLB_DWIDTH = 128) then case req_address(28 to 29) is when "00" => wd_fifo_dout_mirror <= wd_fifo_dout; when "01" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4); when "10" => wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); when "11" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); wd_fifo_dout_mirror(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); when others => null; end case; end if; else -- in data phase wd_fifo_dout_mirror <= wd_fifo_dout; if ((dp_dataConv_wd_conv_mode = "10" and dp_dataConv_word_addr(0) = '1') or (dp_dataConv_wd_conv_mode = "11" and dp_dataConv_word_addr(1) = '1')) then -- conv 64:32 or 128:64 wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); elsif (dp_dataConv_wd_conv_mode = "01") then -- conv 128:32 case dp_dataConv_word_addr is when "00" => wd_fifo_dout_mirror <= wd_fifo_dout; when "01" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4); when "10" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2); when "11" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); when others => null; end case; end if; end if; end process; process(wd_fifo_dout_mirror) variable i: integer; begin for i in 0 to C_PLB_DWIDTH-1 loop M_wrDBus(i) <= wd_fifo_dout_mirror(i); end loop; end process; process (request, req_nRW, pending_read, burst_mode, rd_fifo_full_n, rd_fifo_use_word, pending_write, wd_fifo_empty_n, wd_fifo_use_word, burst_size) begin M_request <= '0'; if (request = '1') then if (req_nRW = '0' and pending_read = '0') then -- read request if ((burst_mode = '0' or burst_size = "0000") and rd_fifo_full_n = '1') then M_request <= '1'; elsif (rd_fifo_use_word(4) = '0') then -- 16 words slots available M_request <= '1'; end if; elsif (req_nRW = '1' and pending_write = '0') then -- write request if ((burst_mode = '0' or burst_size = "0000") and wd_fifo_empty_n = '1') then M_request <= '1'; elsif (wd_fifo_use_word > burst_size) then M_request <= '1'; end if; end if; end if; end process; M_ABus(0 to C_PLB_AWIDTH - 1) <= req_address; process(req_nRW, burst_mode, burst_size, req_BE) variable i:integer; begin M_BE <= (others => '0'); if (burst_mode = '1') then if (burst_size = "0000") then M_BE <= (others => '1'); -- first single,then burst 16 else M_BE(0 to 3) <= burst_size; -- fixed length burst end if; elsif (req_nRW = '0') then M_BE <= (others => '1'); else for i in 0 to PLB_BYTE_COUNT-1 loop M_BE(i) <= req_BE(i); end loop; end if; end process; -- user req FIFO, for both read request and write request U_req_nfa_forward_buckets_if_fifo: component nfa_forward_buckets_if_ap_fifo generic map( DATA_WIDTH => REQ_FIFO_WIDTH, ADDR_WIDTH => FIFO_ADDR_WIDTH, DEPTH => FIFO_DEPTH) port map( clk => PLB_Clk, reset => PLB_Rst, if_empty_n => req_fifo_empty_n, if_read => req_fifo_pop, if_dout => req_fifo_dout, if_full_n => req_fifo_full_n, if_write => req_fifo_push, if_din => req_fifo_din ); req_fifo_push <= BUS_req_push and not req_burst_write; req_fifo_din <= BUS_req_nRW & BUS_req_BE & BUS_address & BUS_size; req_fifo_dout_req_size <= req_fifo_dout(31 downto 0) -1; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then req_burst_write <= '0'; req_burst_write_counter <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (req_fifo_push = '1' and BUS_req_nRW = '1' and BUS_size(31 downto 1) /= "0000000000000000000000000000000") then req_burst_write <= '1'; req_burst_write_counter <= BUS_size - 1; end if; if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write = '1') then req_burst_write_counter <= req_burst_write_counter -1; end if; if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write_counter = X"00000001") then-- last burst write data req_burst_write <= '0'; end if; end if; end process; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then request <= '0'; req_size <= (others => '0'); req_nRW <= '0'; req_address(0 to C_PLB_AWIDTH - 1) <= (others => '0'); burst_mode <= '0'; burst_size <= (others => '0'); req_fifo_pop <= '0'; elsif (PLB_Clk'event and PLB_Clk = '1') then req_fifo_pop <= '0'; if ((request = '0' and req_fifo_empty_n = '1') or PLB_MAddrAck = '1') then if (PLB_MAddrAck = '1' and (burst_mode = '0' or burst_size ="0000") and dataConv_last = '0') then request <= '1'; if (conv_mode_comb(1) = '1') then -- 2:1 conv req_BE(PLB_BYTE_COUNT/2-1 downto 0) <= (others => '0'); else -- 128:32 if (req_address(28 to 29) = "00") then req_BE(PLB_BYTE_COUNT/4-1 downto 0) <= (others => '0'); elsif (req_address(28 to 29) = "01") then req_BE(PLB_BYTE_COUNT/2-1 downto PLB_BYTE_COUNT/4) <= (others => '0'); elsif (req_address(28 to 29) = "10") then req_BE(PLB_BYTE_COUNT*3/4-1 downto PLB_BYTE_COUNT/2) <= (others => '0'); end if; end if; if (PLB_MSSize = "00") then -- 32 bits slave req_address <= req_address + 4; elsif (PLB_MSSize = "01") then -- 64 slave req_address <= req_address + 8; end if;-- 128 bits slave does not need conversion cycle elsif (PLB_MAddrAck = '1' and burst_mode = '1' and burst_last = '0') then request <= '1'; -- req next burst section, this will be pending until previous burst finished req_size(0 to 27) <= req_size(0 to 27) - 1; req_address(0 to C_PLB_AWIDTH - PLB_ADDR_SHIFT - 1) <= req_address(0 to C_PLB_AWIDTH -PLB_ADDR_SHIFT -1) + burst_size +1; req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0'); -- low bits of addr must be reset for possible data_conv modifications of 10 lines above burst_mode <= '1'; burst_size <= "1111"; -- burst 16 words else if (req_fifo_empty_n = '1') then req_fifo_pop <= '1'; end if; request <= req_fifo_empty_n; -- fetch next user_req, may be a vaild req or a null req req_size(0 to 27) <= req_fifo_dout_req_size(31 downto 4); --remaining burst transfer except current one req_nRW <= req_fifo_dout(REQ_FIFO_WIDTH-1); req_BE <= req_fifo_dout(REQ_FIFO_WIDTH-2 downto 64); req_address <= req_fifo_dout(63 downto 32); if (req_fifo_dout(REQ_FIFO_WIDTH-1) = '0') then -- read request req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0'); end if; -- long burst request will be split to 1stReq: 1-16 words, all next req: 16 words if (req_fifo_dout_req_size /= X"00000000") then -- more than 1 word, burst burst_mode <= req_fifo_empty_n; -- fetched req may be null req -- req of burst 17 will be single + burst 16, please check burst_size also else burst_mode <= '0'; end if; burst_size(3 downto 0) <= req_fifo_dout_req_size(3 downto 0);-- 0:single, 1-15: burst 2-16words end if; end if; end if; end process; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then pending_read <= '0'; pending_write <= '0'; dp_PLB_MSSize <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MRdDAck = '1' and ((pending_rd_req_burst_mode = '1' and pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00") or (pending_rd_req_burst_mode = '0'))) then pending_read <= '0'; elsif (PLB_MAddrAck = '1' and req_nRW='0') then pending_read <= '1'; end if; if (PLB_MWrDAck = '1' and wr_data_phase = '1' and ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or pending_wr_req_burst_mode = '0')) then pending_write <= '0'; elsif (PLB_MAddrAck = '1' and req_nRW='1' and (PLB_MWrDAck = '0' or burst_size /= "0000")) then pending_write <= '1'; end if; if (PLB_MAddrAck = '1') then dp_PLB_MSSize <= PLB_MSSize; end if; end if; end process; process(req_size) begin if (req_size(0 to 27) = "000000000000000000000000000") then burst_last <= '1'; -- one request is ok else burst_last <= '0'; end if; end process; -- user write data FIFO, for data of bus write request U_wd_nfa_forward_buckets_if_fifo: component nfa_forward_buckets_if_ap_fifo_uw generic map( DATA_WIDTH => PLB_DW, ADDR_WIDTH => FIFO_ADDR_WIDTH, DEPTH => FIFO_DEPTH) port map( clk => PLB_Clk, reset => PLB_Rst, if_empty_n => wd_fifo_empty_n, if_read => wd_fifo_pop, if_dout => wd_fifo_dout, if_full_n => wd_fifo_full_n, if_write => wd_fifo_push, if_din => wd_fifo_din, use_word => wd_fifo_use_word ); wd_fifo_push <= BUS_req_push and BUS_req_nRW; wd_fifo_din <= BUS_WrData; -- returned bus read data fifo U_rd_nfa_forward_buckets_if_fifo: component nfa_forward_buckets_if_ap_fifo_uw generic map( DATA_WIDTH => PLB_DW, ADDR_WIDTH => FIFO_ADDR_WIDTH, DEPTH => FIFO_DEPTH) port map( clk => PLB_Clk, reset => PLB_Rst, if_empty_n => rd_fifo_empty_n, if_read => rd_fifo_pop, if_dout => rd_fifo_dout, if_full_n => rd_fifo_full_n, if_write => rd_fifo_push, if_din => rd_fifo_din, use_word => rd_fifo_use_word ); process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then dp_dataConv_rd_conv_mode <= (others =>'0'); dp_dataConv_rd_burst_counter <= (others => '0'); dp_dataConv_rd_burst_counter_reg <= (others => '0'); PLB_MRdDAck_reg <= '0'; elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '0' and dp_dataConv_rd_conv_mode = "00") then dp_dataConv_rd_conv_mode <= conv_mode_comb; dp_dataConv_rd_burst_counter <= conv_counter_comb; end if; if (PLB_MRdDAck = '1' and ((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00")) or (pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter = "00")))then dp_dataConv_rd_conv_mode <= "00"; end if; if (PLB_MRdDAck = '1' and ((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /= "00")) or (pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter /= "00")))then if (dp_dataConv_rd_burst_counter = "00") then if (dp_dataConv_rd_conv_mode = "01") then -- 128/32 dp_dataConv_rd_burst_counter <= "11"; elsif (dp_dataConv_rd_conv_mode(1) = '1') then -- 64/32 or 128/64 dp_dataConv_rd_burst_counter <= "01"; end if; else dp_dataConv_rd_burst_counter <= dp_dataConv_rd_burst_counter -1; end if; end if; dp_dataConv_rd_burst_counter_reg <= dp_dataConv_rd_burst_counter; PLB_MRdDAck_reg <= PLB_MRdDAck; end if; end process; rd_fifo_push <= '1' when PLB_MRdDAck_reg = '1' and dp_dataConv_rd_burst_counter_reg = "00" else '0'; process(PLB_MRdDBus) variable i: integer; begin -- change to little endian for i in 0 to C_PLB_DWIDTH-1 loop PLB_MRdDBus_reverse(i) <= PLB_MRdDBus(i); end loop; end process; process(PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then rd_fifo_din <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MRdDAck = '1') then case dp_dataConv_rd_conv_mode is when "00" => rd_fifo_din <= PLB_MRdDBus_reverse; when "10" | "11" => if (dp_dataConv_rd_burst_counter = "00") then rd_fifo_din(PLB_DW-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0); else rd_fifo_din(PLB_DW/2-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0); end if; when "01" => case dp_dataConv_rd_burst_counter is when "00" => rd_fifo_din(PLB_DW-1 downto PLB_DW*3/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when "01" => rd_fifo_din(PLB_DW*3/4-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when "10" => rd_fifo_din(PLB_DW/2-1 downto PLB_DW/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when "11" => rd_fifo_din(PLB_DW/4-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when others => null; end case; when others => null; end case; end if; end if; end process; rd_fifo_pop <= BUS_rsp_pop; pending_read_req_p: process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then pending_rd_req_burst_mode <= '0'; pending_rd_req_burst_size <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '0') then if (burst_mode = '1' and burst_size /= "0000") then pending_rd_req_burst_mode <= burst_mode; end if; pending_rd_req_burst_size <= burst_size; elsif (PLB_MRdDAck = '1' and pending_rd_req_burst_mode = '1') then if (dp_dataConv_rd_burst_counter = "00") then pending_rd_req_burst_size <= pending_rd_req_burst_size - 1; if (pending_rd_req_burst_size = "0000") then pending_rd_req_burst_mode <= '0'; end if; end if; end if; end if; end process; pending_write_req_p: process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then pending_wr_req_burst_mode <= '0'; pending_wr_req_burst_size <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '1') then if (burst_mode = '1' and burst_size /= "0000") then pending_wr_req_burst_mode <= '1'; end if; pending_wr_req_burst_size <= burst_size; if (PLB_MWrDAck = '1') then if (conv_counter_comb = "00") then pending_wr_req_burst_size <= burst_size -1; else pending_wr_req_burst_size <= burst_size; end if; end if; elsif (PLB_MWrDAck = '1' and pending_wr_req_burst_mode = '1') then if (dp_dataConv_wd_burst_counter = "00") then pending_wr_req_burst_size <= pending_wr_req_burst_size - 1; if (pending_wr_req_burst_size = "0000") then pending_wr_req_burst_mode <= '0'; end if; end if; end if; end if; end process; end IMP;
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity nfa_forward_buckets_if_ap_fifo_uw is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 4; DEPTH : integer := 16); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0)); end entity; architecture rtl of nfa_forward_buckets_if_ap_fifo_uw is type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal mStorage : memtype; signal mInPtr, mNextInPtr, mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0); signal internal_empty_n, internal_full_n : STD_LOGIC; signal internal_use_word : STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0); begin mNextInPtr <= mInPtr + 1; if_dout <= mStorage(CONV_INTEGER(mOutPtr)); if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; use_word <= internal_use_word; process (clk, reset) begin if reset = '1' then mInPtr <= (others => '0'); mOutPtr <= (others => '0'); internal_use_word <= (others => '0'); else if clk'event and clk = '1' then if if_read = '1' and internal_empty_n = '1' then mOutPtr <= mOutPtr + 1; end if; if if_write = '1' and internal_full_n = '1' then mStorage(CONV_INTEGER(mInPtr)) <= if_din; mInPtr <= mNextInPtr; end if; if (if_read = '1' and if_write = '0') then internal_use_word <= internal_use_word - '1'; elsif (if_read = '0' and if_write = '1') then internal_use_word <= internal_use_word + '1'; end if; end if; end if; end process; process (mInPtr, mOutPtr, mNextInPtr) begin if mInPtr = mOutPtr then internal_empty_n <= '0'; else internal_empty_n <= '1'; end if; if mNextInPtr = mOutPtr then internal_full_n <= '0'; else internal_full_n <= '1'; end if; end process; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity nfa_forward_buckets_if_plb_master_if is generic ( C_PLB_AWIDTH : integer := 32; C_PLB_DWIDTH : integer := 64; PLB_ADDR_SHIFT : integer := 3 ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete PLB_Clk : in std_logic; PLB_Rst : in std_logic; M_abort : out std_logic; M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1); M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1); M_busLock : out std_logic; M_lockErr : out std_logic; M_MSize : out std_logic_vector(0 to 1); M_priority : out std_logic_vector(0 to 1); M_rdBurst : out std_logic; M_request : out std_logic; M_RNW : out std_logic; M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_wrBurst : out std_logic; M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1); PLB_MBusy : in std_logic; PLB_MWrBTerm : in std_logic; PLB_MWrDAck : in std_logic; PLB_MAddrAck : in std_logic; PLB_MRdBTerm : in std_logic; PLB_MRdDAck : in std_logic; PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1)); PLB_MRdWdAddr : in std_logic_vector(0 to 3); PLB_MRearbitrate : in std_logic; PLB_MSSize : in std_logic_vector(0 to 1); -- signals from user logic BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data BUS_address : in std_logic_vector(31 downto 0); -- physical address BUS_size : in std_logic_vector(31 downto 0); -- burst size of word BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8-1 downto 0); -- Bus write data byte enable BUS_req_full_n : out std_logic; -- req Fifo full BUS_req_push : in std_logic; -- req Fifo push (new request in) BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type BUS_rsp_empty_n: out std_logic; -- return data FIFO empty BUS_rsp_pop : in std_logic -- return data FIFO pop ); attribute SIGIS : string; attribute SIGIS of PLB_Clk : signal is "Clk"; attribute SIGIS of PLB_Rst : signal is "Rst"; end entity; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of nfa_forward_buckets_if_plb_master_if is component nfa_forward_buckets_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 4; DEPTH : integer := 16); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end component; component nfa_forward_buckets_if_ap_fifo_uw is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 4; DEPTH : integer := 16); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0)); end component; constant PLB_DW : integer := C_PLB_DWIDTH; constant PLB_BYTE_COUNT : integer := PLB_DW/8; constant REQ_FIFO_WIDTH : integer := 1 + PLB_BYTE_COUNT + 32 + 32; --nRW + BE + 32 bits phy addr + size constant FIFO_ADDR_WIDTH : integer := 5; constant FIFO_DEPTH : integer := 32; -- request FIFO signal req_fifo_empty_n : STD_LOGIC; signal req_fifo_pop : STD_LOGIC; signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0); signal req_fifo_full_n : STD_LOGIC; signal req_fifo_push : STD_LOGIC; signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0); -- burst write counter (only push burst data in and ignore all burst write request except the first one) signal req_burst_write: STD_LOGIC; -- whether last request is a burst write signal req_burst_write_counter: STD_LOGIC_VECTOR(31 downto 0); -- write data FIFO (for bus write data) signal wd_fifo_empty_n : STD_LOGIC; signal wd_fifo_pop : STD_LOGIC; signal wd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal wd_fifo_dout_mirror : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal wd_fifo_full_n : STD_LOGIC; signal wd_fifo_push : STD_LOGIC; signal wd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal wd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0); -- read data FIFO (for bus read returned data) signal rd_fifo_empty_n : STD_LOGIC; signal rd_fifo_pop : STD_LOGIC; signal rd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal rd_fifo_full_n : STD_LOGIC; signal rd_fifo_push : STD_LOGIC; signal rd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal rd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0); signal req_address : std_logic_vector(0 to C_PLB_AWIDTH -1);-- bus request word address signal req_fifo_dout_req_size : std_logic_vector(31 downto 0); -- req_size -1 signal req_size : std_logic_vector(0 to 27); -- burst size of 16 word block signal request, req_nRW: std_logic; signal req_BE : std_logic_vector(PLB_BYTE_COUNT-1 downto 0); signal pending_rd_req_burst_mode: std_logic; signal pending_rd_req_burst_size: std_logic_vector(3 downto 0); signal pending_wr_req_burst_mode: std_logic; signal pending_wr_req_burst_size: std_logic_vector(3 downto 0); signal pending_read, pending_write: std_logic; signal burst_mode, burst_last : std_logic; signal burst_size : std_logic_vector(3 downto 0); -- maximum burst 16 words --signals for write data mirror signal conv_mode_comb : std_logic_vector(1 downto 0); -- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64 signal conv_counter_comb: std_logic_vector(1 downto 0); signal wr_data_phase : std_logic; signal dataConv_last: std_logic; signal dp_dataConv_last: std_logic; signal dp_dataConv_word_addr: std_logic_vector(1 downto 0); signal dp_dataConv_wd_conv_mode : std_logic_vector(1 downto 0); -- 00:NO conv, 01:128/32, 10:64/32, 11:128/64 signal dp_dataConv_wd_burst_counter: std_logic_vector(1 downto 0); signal dp_dataConv_wd_BE: std_logic_vector(PLB_BYTE_COUNT-1 downto 0); signal dp_PLB_MSSize : std_logic_vector(1 downto 0); --signals for read data mirror signal PLB_MRdDAck_reg : std_logic; signal dp_dataConv_rd_conv_mode : std_logic_vector(1 downto 0);-- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64 signal dp_dataConv_rd_burst_counter, dp_dataConv_rd_burst_counter_reg: std_logic_vector(1 downto 0); signal PLB_MRdDBus_reverse : std_logic_vector(PLB_DW-1 downto 0); -- signals with dp_ prefix stand for data phase signals -- signals with req_ prefix stand for request phase signals begin -- interface to user logic BUS_RdData <= rd_fifo_dout; BUS_req_full_n <= req_fifo_full_n and wd_fifo_full_n; BUS_rsp_nRW <= '0'; BUS_rsp_empty_n <= rd_fifo_empty_n; -- interface to PLB M_abort <= '0'; M_busLock <= '0'; M_lockErr <= '0'; M_MSize <= "01"; -- 00:32b dev, 01:64b, 10:128b, 11:256b M_size <= "0000" when (burst_mode = '0' or burst_size = "0000") else "1011"; -- single rw or 64 bits burst M_type <= "000"; -- memory trans M_priority <= "00"; M_RNW <= not req_nRW; M_rdBurst <= '1' when pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /="00") else '0'; process (PLB_MSSize) begin M_wrBurst <= '0'; if (pending_wr_req_burst_mode = '1' and (pending_wr_req_burst_size /= "0000" or dp_dataConv_wd_burst_counter /="00")) then M_wrBurst <= '1'; elsif (request = '1' and req_nRW = '1' and pending_write = '0' and burst_mode = '1' and burst_size /="0000" and wd_fifo_use_word > burst_size) then M_wrBurst <= '1'; end if; end process; -- write data mirror section process (PLB_MSSize) begin if (C_PLB_DWIDTH = 64 and PLB_MSSize = "00") then conv_mode_comb <= "10"; -- conv 64:32 conv_counter_comb <= "01"; elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "01") then conv_mode_comb <= "11"; -- conv 128:64 conv_counter_comb <= "01"; elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "00") then conv_mode_comb <= "01"; -- conv 128:32 conv_counter_comb <= "11"; else conv_mode_comb <= "00"; -- do not need conv conv_counter_comb <= "00"; end if; end process; process (burst_mode, burst_size, conv_mode_comb, req_address, req_BE) begin dataConv_last <= '0'; if (burst_mode = '0' or burst_size = "0000") then if (conv_mode_comb = "00") then -- no conv dataConv_last <= '1'; elsif (conv_mode_comb = "10") then -- 64:32 conv if (req_address(29)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then dataConv_last <= '1'; end if; elsif (conv_mode_comb = "11") then -- 128:64 conv if (req_address(28)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then dataConv_last <= '1'; end if; elsif (conv_mode_comb = "01") then -- 128:32 conv if (req_address(28 to 29) = "00" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT*3/4)) then dataConv_last <= '1'; elsif (req_address(28 to 29) = "01" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then dataConv_last <= '1'; elsif (req_address(28 to 29) = "10" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT*3/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/4)) then dataConv_last <= '1'; elsif (req_address(28 to 29) = "11") then dataConv_last <= '1'; end if; end if; end if; end process; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then dp_dataConv_word_addr <= (others => '0'); dp_dataConv_wd_conv_mode <= (others =>'0'); dp_dataConv_wd_burst_counter <= (others => '0'); dp_dataConv_wd_BE <= (others => '0'); dp_dataConv_last <= '0'; wr_data_phase <= '0'; elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '1') then dp_dataConv_wd_BE <= req_BE; dp_dataConv_last <= dataConv_last; end if; if (PLB_MAddrAck = '1' and req_nRW = '1' and (PLB_MWrDAck = '0' or (burst_mode = '1' and burst_size /= "0000"))) then wr_data_phase <= '1'; end if; if (PLB_MWrDAck = '1' and wr_data_phase = '1') then if ((pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or (pending_wr_req_burst_mode = '0')) then wr_data_phase <= '0'; end if; end if; if (PLB_MAddrAck = '1' and req_nRW = '1' and dp_dataConv_wd_conv_mode = "00") then if (PLB_MWrDAck = '0') then -- only AddrAck asserted dp_dataConv_wd_conv_mode <= conv_mode_comb; dp_dataConv_word_addr <= req_address(28 to 29); dp_dataConv_wd_burst_counter <= conv_counter_comb; else -- Xilinx PLB v4.6 support assert addrAck & wrDAck at the same cycle if (dataConv_last = '0') then dp_dataConv_wd_conv_mode <= conv_mode_comb; end if; if (PLB_MSSize = "00") then -- 32 bits slave dp_dataConv_word_addr <= req_address(28 to 29) +1; elsif (PLB_MSSize = "01") then -- 64 bits slave dp_dataConv_word_addr <= req_address(28 to 29) +2; end if; if (conv_mode_comb /= "00") then -- need conv dp_dataConv_wd_burst_counter <= conv_counter_comb -1; end if; end if; end if; if (wr_data_phase = '1' and PLB_MWrDAck = '1' and ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or (pending_wr_req_burst_mode = '0' and dp_dataConv_last = '1'))) then dp_dataConv_wd_conv_mode <= "00"; end if; if (PLB_MWrDAck = '1' and wr_data_phase = '1') then if (dp_PLB_MSSize = "01") then -- 64 bits slave dp_dataConv_word_addr <= dp_dataConv_word_addr +2; else dp_dataConv_word_addr <= dp_dataConv_word_addr +1; end if; if ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size /= "0000") or dp_dataConv_wd_burst_counter /= "00") then if (dp_dataConv_wd_burst_counter = "00") then if (dp_dataConv_wd_conv_mode = "01") then -- 128/32 dp_dataConv_wd_burst_counter <= "11"; elsif (dp_dataConv_wd_conv_mode(1) = '1') then -- 64/32 or 128/64 dp_dataConv_wd_burst_counter <= "01"; end if; else dp_dataConv_wd_burst_counter <= dp_dataConv_wd_burst_counter -1; end if; end if; end if; end if; end process; process(PLB_MWrDAck, wr_data_phase, dp_dataConv_wd_burst_counter, burst_mode, conv_counter_comb, conv_mode_comb, req_BE) begin wd_fifo_pop <= '0'; if (PLB_MWrDAck = '1') then if (wr_data_phase = '1') then if ((pending_wr_req_burst_mode = '1' and dp_dataConv_wd_burst_counter = "00") or (dp_dataConv_wd_conv_mode /= "00" and dp_dataConv_last = '1') or dp_dataConv_wd_conv_mode = "00" )then wd_fifo_pop <= '1'; end if; else -- got addrAck and wrDAck at the same cycle if (burst_mode = '1' and burst_size /= "0000" and conv_counter_comb = "00") then wd_fifo_pop <= '1'; elsif ((burst_mode = '0' or burst_size = "0000") and dataConv_last = '1') then wd_fifo_pop <= '1'; end if; end if; end if; end process; process(wd_fifo_dout, wr_data_phase, req_address, dp_dataConv_wd_conv_mode, dp_dataConv_word_addr) begin wd_fifo_dout_mirror <= wd_fifo_dout; if (wr_data_phase = '0') then -- we do not know slave bus width, perform default convert if (C_PLB_DWIDTH = 32) then wd_fifo_dout_mirror <= wd_fifo_dout; elsif (C_PLB_DWIDTH = 64) then if (req_address(29) = '0') then wd_fifo_dout_mirror <= wd_fifo_dout; else wd_fifo_dout_mirror(PLB_DW/2-1 downto 0) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2); wd_fifo_dout_mirror(PLB_DW-1 downto PLB_DW/2) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2); end if; elsif (C_PLB_DWIDTH = 128) then case req_address(28 to 29) is when "00" => wd_fifo_dout_mirror <= wd_fifo_dout; when "01" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4); when "10" => wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); when "11" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); wd_fifo_dout_mirror(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); when others => null; end case; end if; else -- in data phase wd_fifo_dout_mirror <= wd_fifo_dout; if ((dp_dataConv_wd_conv_mode = "10" and dp_dataConv_word_addr(0) = '1') or (dp_dataConv_wd_conv_mode = "11" and dp_dataConv_word_addr(1) = '1')) then -- conv 64:32 or 128:64 wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); elsif (dp_dataConv_wd_conv_mode = "01") then -- conv 128:32 case dp_dataConv_word_addr is when "00" => wd_fifo_dout_mirror <= wd_fifo_dout; when "01" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4); when "10" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2); when "11" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); when others => null; end case; end if; end if; end process; process(wd_fifo_dout_mirror) variable i: integer; begin for i in 0 to C_PLB_DWIDTH-1 loop M_wrDBus(i) <= wd_fifo_dout_mirror(i); end loop; end process; process (request, req_nRW, pending_read, burst_mode, rd_fifo_full_n, rd_fifo_use_word, pending_write, wd_fifo_empty_n, wd_fifo_use_word, burst_size) begin M_request <= '0'; if (request = '1') then if (req_nRW = '0' and pending_read = '0') then -- read request if ((burst_mode = '0' or burst_size = "0000") and rd_fifo_full_n = '1') then M_request <= '1'; elsif (rd_fifo_use_word(4) = '0') then -- 16 words slots available M_request <= '1'; end if; elsif (req_nRW = '1' and pending_write = '0') then -- write request if ((burst_mode = '0' or burst_size = "0000") and wd_fifo_empty_n = '1') then M_request <= '1'; elsif (wd_fifo_use_word > burst_size) then M_request <= '1'; end if; end if; end if; end process; M_ABus(0 to C_PLB_AWIDTH - 1) <= req_address; process(req_nRW, burst_mode, burst_size, req_BE) variable i:integer; begin M_BE <= (others => '0'); if (burst_mode = '1') then if (burst_size = "0000") then M_BE <= (others => '1'); -- first single,then burst 16 else M_BE(0 to 3) <= burst_size; -- fixed length burst end if; elsif (req_nRW = '0') then M_BE <= (others => '1'); else for i in 0 to PLB_BYTE_COUNT-1 loop M_BE(i) <= req_BE(i); end loop; end if; end process; -- user req FIFO, for both read request and write request U_req_nfa_forward_buckets_if_fifo: component nfa_forward_buckets_if_ap_fifo generic map( DATA_WIDTH => REQ_FIFO_WIDTH, ADDR_WIDTH => FIFO_ADDR_WIDTH, DEPTH => FIFO_DEPTH) port map( clk => PLB_Clk, reset => PLB_Rst, if_empty_n => req_fifo_empty_n, if_read => req_fifo_pop, if_dout => req_fifo_dout, if_full_n => req_fifo_full_n, if_write => req_fifo_push, if_din => req_fifo_din ); req_fifo_push <= BUS_req_push and not req_burst_write; req_fifo_din <= BUS_req_nRW & BUS_req_BE & BUS_address & BUS_size; req_fifo_dout_req_size <= req_fifo_dout(31 downto 0) -1; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then req_burst_write <= '0'; req_burst_write_counter <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (req_fifo_push = '1' and BUS_req_nRW = '1' and BUS_size(31 downto 1) /= "0000000000000000000000000000000") then req_burst_write <= '1'; req_burst_write_counter <= BUS_size - 1; end if; if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write = '1') then req_burst_write_counter <= req_burst_write_counter -1; end if; if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write_counter = X"00000001") then-- last burst write data req_burst_write <= '0'; end if; end if; end process; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then request <= '0'; req_size <= (others => '0'); req_nRW <= '0'; req_address(0 to C_PLB_AWIDTH - 1) <= (others => '0'); burst_mode <= '0'; burst_size <= (others => '0'); req_fifo_pop <= '0'; elsif (PLB_Clk'event and PLB_Clk = '1') then req_fifo_pop <= '0'; if ((request = '0' and req_fifo_empty_n = '1') or PLB_MAddrAck = '1') then if (PLB_MAddrAck = '1' and (burst_mode = '0' or burst_size ="0000") and dataConv_last = '0') then request <= '1'; if (conv_mode_comb(1) = '1') then -- 2:1 conv req_BE(PLB_BYTE_COUNT/2-1 downto 0) <= (others => '0'); else -- 128:32 if (req_address(28 to 29) = "00") then req_BE(PLB_BYTE_COUNT/4-1 downto 0) <= (others => '0'); elsif (req_address(28 to 29) = "01") then req_BE(PLB_BYTE_COUNT/2-1 downto PLB_BYTE_COUNT/4) <= (others => '0'); elsif (req_address(28 to 29) = "10") then req_BE(PLB_BYTE_COUNT*3/4-1 downto PLB_BYTE_COUNT/2) <= (others => '0'); end if; end if; if (PLB_MSSize = "00") then -- 32 bits slave req_address <= req_address + 4; elsif (PLB_MSSize = "01") then -- 64 slave req_address <= req_address + 8; end if;-- 128 bits slave does not need conversion cycle elsif (PLB_MAddrAck = '1' and burst_mode = '1' and burst_last = '0') then request <= '1'; -- req next burst section, this will be pending until previous burst finished req_size(0 to 27) <= req_size(0 to 27) - 1; req_address(0 to C_PLB_AWIDTH - PLB_ADDR_SHIFT - 1) <= req_address(0 to C_PLB_AWIDTH -PLB_ADDR_SHIFT -1) + burst_size +1; req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0'); -- low bits of addr must be reset for possible data_conv modifications of 10 lines above burst_mode <= '1'; burst_size <= "1111"; -- burst 16 words else if (req_fifo_empty_n = '1') then req_fifo_pop <= '1'; end if; request <= req_fifo_empty_n; -- fetch next user_req, may be a vaild req or a null req req_size(0 to 27) <= req_fifo_dout_req_size(31 downto 4); --remaining burst transfer except current one req_nRW <= req_fifo_dout(REQ_FIFO_WIDTH-1); req_BE <= req_fifo_dout(REQ_FIFO_WIDTH-2 downto 64); req_address <= req_fifo_dout(63 downto 32); if (req_fifo_dout(REQ_FIFO_WIDTH-1) = '0') then -- read request req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0'); end if; -- long burst request will be split to 1stReq: 1-16 words, all next req: 16 words if (req_fifo_dout_req_size /= X"00000000") then -- more than 1 word, burst burst_mode <= req_fifo_empty_n; -- fetched req may be null req -- req of burst 17 will be single + burst 16, please check burst_size also else burst_mode <= '0'; end if; burst_size(3 downto 0) <= req_fifo_dout_req_size(3 downto 0);-- 0:single, 1-15: burst 2-16words end if; end if; end if; end process; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then pending_read <= '0'; pending_write <= '0'; dp_PLB_MSSize <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MRdDAck = '1' and ((pending_rd_req_burst_mode = '1' and pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00") or (pending_rd_req_burst_mode = '0'))) then pending_read <= '0'; elsif (PLB_MAddrAck = '1' and req_nRW='0') then pending_read <= '1'; end if; if (PLB_MWrDAck = '1' and wr_data_phase = '1' and ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or pending_wr_req_burst_mode = '0')) then pending_write <= '0'; elsif (PLB_MAddrAck = '1' and req_nRW='1' and (PLB_MWrDAck = '0' or burst_size /= "0000")) then pending_write <= '1'; end if; if (PLB_MAddrAck = '1') then dp_PLB_MSSize <= PLB_MSSize; end if; end if; end process; process(req_size) begin if (req_size(0 to 27) = "000000000000000000000000000") then burst_last <= '1'; -- one request is ok else burst_last <= '0'; end if; end process; -- user write data FIFO, for data of bus write request U_wd_nfa_forward_buckets_if_fifo: component nfa_forward_buckets_if_ap_fifo_uw generic map( DATA_WIDTH => PLB_DW, ADDR_WIDTH => FIFO_ADDR_WIDTH, DEPTH => FIFO_DEPTH) port map( clk => PLB_Clk, reset => PLB_Rst, if_empty_n => wd_fifo_empty_n, if_read => wd_fifo_pop, if_dout => wd_fifo_dout, if_full_n => wd_fifo_full_n, if_write => wd_fifo_push, if_din => wd_fifo_din, use_word => wd_fifo_use_word ); wd_fifo_push <= BUS_req_push and BUS_req_nRW; wd_fifo_din <= BUS_WrData; -- returned bus read data fifo U_rd_nfa_forward_buckets_if_fifo: component nfa_forward_buckets_if_ap_fifo_uw generic map( DATA_WIDTH => PLB_DW, ADDR_WIDTH => FIFO_ADDR_WIDTH, DEPTH => FIFO_DEPTH) port map( clk => PLB_Clk, reset => PLB_Rst, if_empty_n => rd_fifo_empty_n, if_read => rd_fifo_pop, if_dout => rd_fifo_dout, if_full_n => rd_fifo_full_n, if_write => rd_fifo_push, if_din => rd_fifo_din, use_word => rd_fifo_use_word ); process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then dp_dataConv_rd_conv_mode <= (others =>'0'); dp_dataConv_rd_burst_counter <= (others => '0'); dp_dataConv_rd_burst_counter_reg <= (others => '0'); PLB_MRdDAck_reg <= '0'; elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '0' and dp_dataConv_rd_conv_mode = "00") then dp_dataConv_rd_conv_mode <= conv_mode_comb; dp_dataConv_rd_burst_counter <= conv_counter_comb; end if; if (PLB_MRdDAck = '1' and ((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00")) or (pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter = "00")))then dp_dataConv_rd_conv_mode <= "00"; end if; if (PLB_MRdDAck = '1' and ((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /= "00")) or (pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter /= "00")))then if (dp_dataConv_rd_burst_counter = "00") then if (dp_dataConv_rd_conv_mode = "01") then -- 128/32 dp_dataConv_rd_burst_counter <= "11"; elsif (dp_dataConv_rd_conv_mode(1) = '1') then -- 64/32 or 128/64 dp_dataConv_rd_burst_counter <= "01"; end if; else dp_dataConv_rd_burst_counter <= dp_dataConv_rd_burst_counter -1; end if; end if; dp_dataConv_rd_burst_counter_reg <= dp_dataConv_rd_burst_counter; PLB_MRdDAck_reg <= PLB_MRdDAck; end if; end process; rd_fifo_push <= '1' when PLB_MRdDAck_reg = '1' and dp_dataConv_rd_burst_counter_reg = "00" else '0'; process(PLB_MRdDBus) variable i: integer; begin -- change to little endian for i in 0 to C_PLB_DWIDTH-1 loop PLB_MRdDBus_reverse(i) <= PLB_MRdDBus(i); end loop; end process; process(PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then rd_fifo_din <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MRdDAck = '1') then case dp_dataConv_rd_conv_mode is when "00" => rd_fifo_din <= PLB_MRdDBus_reverse; when "10" | "11" => if (dp_dataConv_rd_burst_counter = "00") then rd_fifo_din(PLB_DW-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0); else rd_fifo_din(PLB_DW/2-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0); end if; when "01" => case dp_dataConv_rd_burst_counter is when "00" => rd_fifo_din(PLB_DW-1 downto PLB_DW*3/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when "01" => rd_fifo_din(PLB_DW*3/4-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when "10" => rd_fifo_din(PLB_DW/2-1 downto PLB_DW/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when "11" => rd_fifo_din(PLB_DW/4-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when others => null; end case; when others => null; end case; end if; end if; end process; rd_fifo_pop <= BUS_rsp_pop; pending_read_req_p: process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then pending_rd_req_burst_mode <= '0'; pending_rd_req_burst_size <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '0') then if (burst_mode = '1' and burst_size /= "0000") then pending_rd_req_burst_mode <= burst_mode; end if; pending_rd_req_burst_size <= burst_size; elsif (PLB_MRdDAck = '1' and pending_rd_req_burst_mode = '1') then if (dp_dataConv_rd_burst_counter = "00") then pending_rd_req_burst_size <= pending_rd_req_burst_size - 1; if (pending_rd_req_burst_size = "0000") then pending_rd_req_burst_mode <= '0'; end if; end if; end if; end if; end process; pending_write_req_p: process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then pending_wr_req_burst_mode <= '0'; pending_wr_req_burst_size <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '1') then if (burst_mode = '1' and burst_size /= "0000") then pending_wr_req_burst_mode <= '1'; end if; pending_wr_req_burst_size <= burst_size; if (PLB_MWrDAck = '1') then if (conv_counter_comb = "00") then pending_wr_req_burst_size <= burst_size -1; else pending_wr_req_burst_size <= burst_size; end if; end if; elsif (PLB_MWrDAck = '1' and pending_wr_req_burst_mode = '1') then if (dp_dataConv_wd_burst_counter = "00") then pending_wr_req_burst_size <= pending_wr_req_burst_size - 1; if (pending_wr_req_burst_size = "0000") then pending_wr_req_burst_mode <= '0'; end if; end if; end if; end if; end process; end IMP;
------------------------------------------------------------------------------- -- Title : TIE-50206, Exercise 12 -- Project : ------------------------------------------------------------------------------- -- File : i2c_config.vhd -- Author : Jonas Nikula, Tuomas Huuki -- Company : TUT -- Created : 20.1.2016 -- Platform : -- Standard : VHDL'93 ------------------------------------------------------------------------------- -- Description: I2C bus controller, for Wolfson Audio Codec configuration ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 20.01.2016 1.0 nikulaj Created -- 03.02.2016 1.1 huukitu Moved data to pkg. -- 02.03.2016 1.2 nikulaj Assign finished_out sequentially ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; -- define the entity entity i2c_config is generic( ref_clk_freq_g : integer := 50000000; -- reference clk i2c_freq_g : integer := 20000; -- wanted i2c frequency n_params_g : integer := 10 -- amount of 3 byte transmissions ); port( clk : in std_logic; rst_n : in std_logic; -- active low rst sdat_inout : inout std_logic; -- i2c dataline sclk_out : out std_logic; -- i2c clk param_status_out : out std_logic_vector(n_params_g - 1 downto 0); -- status "display" finished_out : out std_logic -- 1 when done sending ); end i2c_config; architecture rtl of i2c_config is -- type definitions type state_type is (start_condition, stop_condition, acknowledge, data_transfer); type temp_transmission_arr is array (2 downto 0) of std_logic_vector(7 downto 0); -- constants -- max value for clk prescaler constant prescaler_max_c : integer := (ref_clk_freq_g / i2c_freq_g) / 2; -- data to be sent constant codec_address_c : std_logic_vector(7 downto 0) := "00110100"; type transmission_data_arr is array (n_params_g - 1 downto 0) of std_logic_vector(15 downto 0); -- Actual transmission data array. constant transmission_data_c : transmission_data_arr := ( "0001001000000001", "0001000000000010", "0000111000000001", "0000110000000000", "0000101000000110", "0000100011111000", "0000011001111011", "0000010001111011", "0000001000011010", "0000000000011010" ); -- registers signal finished_r : std_logic; signal sclk_r : std_logic; signal sclk_prescaler_r : unsigned(integer(ceil(log2(real(prescaler_max_c)))) downto 0); signal present_state_r : state_type; signal bit_counter_r : unsigned(2 downto 0); signal byte_counter_r : unsigned(1 downto 0); signal status_counter_r : unsigned(3 downto 0); signal param_status_r : std_logic_vector(n_params_g - 1 downto 0); signal temp_transmission_r : temp_transmission_arr; begin finished_out <= finished_r; param_status_out <= param_status_r; -- Only output clk when NOT finished with param_status_r(n_params_g - 1) select sclk_out <= sclk_r when '0', 'Z' when others; -- i2c clk generation process -- Increments counter, until it hits max value. At that point the clk -- changes value generate_sclk : process(clk, rst_n) begin if(rst_n = '0') then sclk_r <= '0'; sclk_prescaler_r <= (others => '0'); elsif(clk'event and clk = '1') then if(sclk_prescaler_r = prescaler_max_c) then sclk_prescaler_r <= (others => '0'); sclk_r <= not sclk_r; else sclk_prescaler_r <= sclk_prescaler_r + 1; end if; end if; end process generate_sclk; -- i2c data output process generate_sdat : process(clk, rst_n) begin if(rst_n = '0') then -- reset all values that need it sdat_inout <= 'Z'; present_state_r <= start_condition; bit_counter_r <= to_unsigned(7, bit_counter_r'length); byte_counter_r <= to_unsigned(0, byte_counter_r'length); status_counter_r <= to_unsigned(0, status_counter_r'length); param_status_r <= (others => '0'); temp_transmission_r(0) <= (others => '0'); temp_transmission_r(1) <= (others => '0'); temp_transmission_r(2) <= (others => '0'); finished_r <= '0'; elsif(clk'event and clk = '1') then if(param_status_r(n_params_g - 1) = '1') then sdat_inout <= 'Z'; -- When finished, take config logic finished_r <= '1'; -- out of the circuit -- and set finished signal to 1 elsif(present_state_r = acknowledge and sclk_prescaler_r = 0) then sdat_inout <= 'Z'; -- set to high-Z, so that ack can be received elsif(sclk_prescaler_r = prescaler_max_c / 2) then case present_state_r is when start_condition => -- when sdat is high, a transition to low triggers a -- start condition -- also prepare for data transfer if(sdat_inout = '1' and sclk_r = '1') then sdat_inout <= '0'; present_state_r <= data_transfer; bit_counter_r <= to_unsigned(7, bit_counter_r'length); byte_counter_r <= to_unsigned(0, byte_counter_r'length); temp_transmission_r(0) <= codec_address_c; temp_transmission_r(1) <= transmission_data_c(to_integer(status_counter_r))(15 downto 8); temp_transmission_r(2) <= transmission_data_c(to_integer(status_counter_r))(7 downto 0); elsif(sclk_r = '0') then -- set sdat high so it can be pulled low sdat_inout <= '1'; end if; when stop_condition => if(sdat_inout = '0' and sclk_r = '1') then -- when sdat is low, a transition to high -- triggers a stop condition sdat_inout <= '1'; -- 3 byte transfer is done, increment status status_counter_r <= status_counter_r + 1; param_status_r(to_integer(status_counter_r)) <= '1'; -- after stop cond, go to start present_state_r <= start_condition; elsif(sclk_r = '0') then sdat_inout <= '0'; end if; when acknowledge => bit_counter_r <= to_unsigned(7, bit_counter_r'length); -- listening for ack (or nack) if(sclk_r = '1') then if(sdat_inout = '1') then -- on nack, go to start present_state_r <= start_condition; elsif(sdat_inout = '0') then -- on ack, got to stop if all 3 bytes sent if(byte_counter_r = 2) then present_state_r <= stop_condition; -- otherwise to next byte else present_state_r <= data_transfer; byte_counter_r <= byte_counter_r + 1; end if; end if; end if; when data_transfer => -- when clk is low, change state, so that line is -- stable for high if(sclk_r = '0') then sdat_inout <= temp_transmission_r(to_integer(byte_counter_r))(to_integer(bit_counter_r)); else -- When bit is being sent, check if whole byte is -- sent. If so, go to ack, otherwise -- increment bit counter. if(bit_counter_r = 0) then present_state_r <= acknowledge; else bit_counter_r <= bit_counter_r - 1; end if; end if; end case; end if; end if; end process generate_sdat; end rtl;
---------------------------------------------------------------------------- -- This file is a part of the LEON VHDL model -- Copyright (C) 1999 European Space Agency (ESA) -- -- This library is free software; you can redistribute it and/or -- modify it under the terms of the GNU Lesser General Public -- License as published by the Free Software Foundation; either -- version 2 of the License, or (at your option) any later version. -- -- See the file COPYING.LGPL for the full details of the license. ----------------------------------------------------------------------------- -- Entity: ahbarb -- File: ahbarb.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: AMBA AHB arbiter and decoder ------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.target.all; use work.config.all; use work.iface.all; use work.amba.all; entity ahbarb is generic ( masters : integer := 2; -- number of masters defmast : integer := 1 -- default master ); port ( rst : in std_logic; clk : in clk_type; msti : out ahb_mst_in_vector(0 to masters-1); msto : in ahb_mst_out_vector(0 to masters-1); slvi : out ahb_slv_in_vector(0 to AHB_SLV_MAX-1); slvo : in ahb_slv_out_vector(0 to AHB_SLV_MAX-1) ); end; architecture rtl of ahbarb is constant MIMAX : integer := log2x(masters) - 1; constant SIMAX : integer := log2(AHB_SLV_MAX+1) - 1; type reg_type is record hmaster : std_logic_vector(MIMAX downto 0); hmasterd : std_logic_vector(MIMAX downto 0); hslave : std_logic_vector(SIMAX downto 0); hready : std_logic; -- needed for two-cycle error response hmasterlock : std_logic; hmasterlock2 : std_logic; htrans : std_logic_vector(1 downto 0); -- transfer type hcache : std_logic; -- cacheable access end record; constant ahbmin : integer := AHB_SLV_ADDR_MSB-1; type nmstarr is array ( 1 to 5) of integer range 0 to masters-1; type nvalarr is array ( 1 to 5) of boolean; signal r, rin : reg_type; signal rsplit, rsplitin : std_logic_vector(masters-1 downto 0); begin comb : process(rst, msto, slvo, r, rsplit) variable rv : reg_type; variable rhmaster, rhmasterd : integer range 0 to masters -1; variable rhslave : integer range 0 to AHB_SLV_MAX; variable nhmaster, hmaster : integer range 0 to masters -1; variable haddr : std_logic_vector(31 downto 0); -- address bus variable hrdata : std_logic_vector(31 downto 0); -- read data bus variable htrans : std_logic_vector(1 downto 0); -- transfer type variable hresp : std_logic_vector(1 downto 0); -- respons type variable hwrite : std_logic; -- read/write variable hsize : std_logic_vector(2 downto 0); -- transfer size variable hprot : std_logic_vector(2 downto 0); -- protection info variable hburst : std_logic_vector(2 downto 0); -- burst type variable hwdata : std_logic_vector(31 downto 0); -- write data variable hgrant : std_logic_vector(0 to masters-1); -- bus grant variable hsel : std_logic_vector(0 to AHB_SLV_MAX); -- slave select variable hready : std_logic; -- ready variable hmastlock : std_logic; variable nslave : natural range 0 to AHB_SLV_MAX; variable ahbaddr : std_logic_vector(ahbmin downto 0); variable vsplit : std_logic_vector(masters-1 downto 0); variable nmst : nmstarr; variable nvalid : nvalarr; variable hcache : std_logic; variable htmp : std_logic_vector(3 downto 0); begin rv := r; rv.hready := '0'; -- bus multiplexers -- pragma translate_off if not is_x(r.hmaster) then -- pragma translate_on rhmaster := conv_integer(unsigned(r.hmaster)); -- pragma translate_off end if; if not is_x(r.hmasterd) then -- pragma translate_on rhmasterd := conv_integer(unsigned(r.hmasterd)); -- pragma translate_off end if; if not is_x(r.hslave) then -- pragma translate_on rhslave := conv_integer(unsigned(r.hslave)); -- pragma translate_off end if; -- pragma translate_on haddr := msto(rhmaster).haddr; htrans := msto(rhmaster).htrans; hwrite := msto(rhmaster).hwrite; hsize := msto(rhmaster).hsize; hburst := msto(rhmaster).hburst; hmastlock := msto(rhmaster).hlock; hwdata := msto(rhmasterd).hwdata; if rhslave /= AHB_SLV_MAX then hready := slvo(rhslave).hready; hrdata := slvo(rhslave).hrdata; hresp := slvo(rhslave).hresp ; else -- default slave hrdata := (others => '-'); if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then hresp := HRESP_OKAY; hready := '1'; else -- return two-cycle error in case of unimplemented slave access hresp := HRESP_ERROR; hready := r.hready; rv.hready := not r.hready; end if; end if; -- find next master -- re-arbitrate on non-sequential accesses or when BUSY is seen -- with the following priority: -- 1. busreq and (htrans /= idle) and (htrans /= busy) and (split = 0) -- 2. busreq and (htrans /= idle) and (split = 0) -- 3. busreq and (split = 0) -- 4. default master nvalid(1 to 4) := (others => false); nvalid(5) := true; nmst(1 to 4) := (others => 0); nmst(5) := defmast; nhmaster := rhmaster; if ((msto(rhmaster).htrans = HTRANS_IDLE) or (msto(rhmaster).htrans = HTRANS_BUSY) or (msto(rhmaster).hburst = HBURST_SINGLE)) and ((r.hmasterlock or r.hmasterlock2) = '0') then for i in 0 to (masters -1) loop if ((rsplit(i) = '0') or not AHB_SPLIT) then if (msto(i).hbusreq = '1') then if (msto(i).htrans /= HTRANS_IDLE) then if (msto(i).htrans /= HTRANS_BUSY) then nmst(1) := i; nvalid(1) := true; end if; nmst(2) := i; nvalid(2) := true; end if; nmst(3) := i; nvalid(3) := true; end if; if not ((nmst(4) = defmast) and nvalid(4)) then nmst(4) := i; nvalid(4) := true; end if; end if; end loop; for i in 1 to 5 loop if nvalid(i) then nhmaster := nmst(i); exit; end if; end loop; end if; hgrant := (others => '0'); hgrant(nhmaster) := '1'; -- select slave nslave := AHB_SLV_MAX; ahbaddr := haddr(31 downto (31 - ahbmin)); for i in AHB_SLVTABLE'range loop --' if AHB_SLVTABLE(i).enable and (ahbaddr >= AHB_SLVTABLE(i).firstaddr(ahbmin downto 0)) and (ahbaddr <= AHB_SLVTABLE(i).lastaddr(ahbmin downto 0)) then nslave := AHB_SLVTABLE(i).index; end if; end loop; if htrans = HTRANS_IDLE then nslave := AHB_SLV_MAX; end if; hsel := (others => '0'); hsel(nslave) := '1'; -- latch active master and slave if hready = '1' then rv.hmaster := std_logic_vector(conv_unsigned(nhmaster, MIMAX + 1)); rv.hmasterd := r.hmaster; rv.hslave := std_logic_vector(conv_unsigned(nslave, SIMAX + 1)); rv.htrans := htrans; rv.hmasterlock := msto(nhmaster).hlock; rv.hmasterlock2 := r.hmasterlock; end if; -- split support vsplit := (others => '0'); if AHB_SPLIT then vsplit := rsplit; if hresp = HRESP_SPLIT then vsplit(rhmasterd) := '1'; end if; for i in AHB_SLVTABLE'range loop --' if AHB_SLVTABLE(i).split then vsplit := vsplit and not slvo(AHB_SLVTABLE(i).index).hsplit(masters-1 downto 0); end if; end loop; end if; -- decode cacheability hcache := '0'; for i in AHB_CACHETABLE'range loop --' if (haddr(31 downto 32-AHB_CACHE_ADDR_MSB) >= AHB_CACHETABLE(i).firstaddr) and (haddr(31 downto 32-AHB_CACHE_ADDR_MSB) <= AHB_CACHETABLE(i).lastaddr) then hcache := '1'; end if; end loop; if hready = '1' then rv.hcache := hcache; end if; -- reset operation if (rst = '0') then rv.hmaster := (others => '0'); rv.hmasterlock := '0'; rv.hslave := std_logic_vector(conv_unsigned(AHB_SLV_MAX, SIMAX+1)); hsel := (others => '0'); rv.htrans := HTRANS_IDLE; hready := '1'; vsplit := (others => '0'); rv.hcache := '0'; end if; -- drive master inputs for i in 0 to (masters -1) loop msti(i).hgrant <= hgrant(i); msti(i).hready <= hready; msti(i).hrdata <= hrdata; msti(i).hresp <= hresp; msti(i).hcache <= r.hcache; end loop; -- drive slave inputs for i in 0 to (AHB_SLV_MAX -1) loop slvi(i).haddr <= haddr; slvi(i).htrans <= htrans; slvi(i).hwrite <= hwrite; slvi(i).hsize <= hsize; slvi(i).hburst <= hburst; slvi(i).hready <= hready; slvi(i).hwdata <= hwdata; slvi(i).hsel <= hsel(i); htmp := "0000"; htmp(MIMAX downto 0) := r.hmaster; slvi(i).hmaster <= htmp; slvi(i).hmastlock <= hmastlock; end loop; -- assign register inputs rin <= rv; rsplitin <= vsplit; end process; reg0 : process(clk) begin if rising_edge(clk) then r <= rin; end if; end process; splitreg : if AHB_SPLIT generate reg1 : process(clk) begin if rising_edge(clk) then rsplit <= rsplitin; end if; end process; end generate; end;
------------------------------------------------------------------------------- -- Low-frequency clock generator for Virtex 4/5 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- pragma translate_off library grlib; use grlib.stdlib.all; library unisim; use unisim.BUFG; use unisim.DCM; -- pragma translate_on library techmap; use techmap.gencomp.all; entity lfclkgen is generic ( dv_div : real; fx_mul : integer; fx_div : integer); port ( resetin : in std_logic; clkin : in std_logic; clk : out std_logic; resetout: out std_logic); end; architecture struct of lfclkgen is -- attribute CLKIN_PERIOD : string; -- attribute CLKIN_PERIOD of brm_dcm_fx: label is "20"; component DCM generic ( CLKDV_DIVIDE : real := 2.0; CLKFX_DIVIDE : integer := 1; CLKFX_MULTIPLY : integer := 4; CLKIN_DIVIDE_BY_2 : boolean := false; CLKIN_PERIOD : real := 10.0; CLKOUT_PHASE_SHIFT : string := "NONE"; CLK_FEEDBACK : string := "1X"; DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; DFS_FREQUENCY_MODE : string := "LOW"; DLL_FREQUENCY_MODE : string := "LOW"; DSS_MODE : string := "NONE"; DUTY_CYCLE_CORRECTION : boolean := true; FACTORY_JF : bit_vector := X"C080"; PHASE_SHIFT : integer := 0; STARTUP_WAIT : boolean := false ); port ( CLKFB : in std_logic; CLKIN : in std_logic; DSSEN : in std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; RST : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKDV : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; LOCKED : out std_logic; PSDONE : out std_logic; STATUS : out std_logic_vector (7 downto 0)); end component; component BUFG port ( O : out std_logic; I : in std_logic); end component; signal gnd, clk0, clk1, clk_fb0, clk_fb1, clk_dv, clk_div, clk_fx,clk_fxo, rst0, lock0 : std_logic; signal rst1 : std_logic_vector(3 downto 0); begin process(clk_fxo, resetin) begin if resetin = '0' then rst1 <= "1111"; elsif rising_edge(clk_fxo) then rst1 <= rst1(2 downto 0) & not lock0; end if; end process; gnd <= '0'; rst0 <= not resetin; bufg0 : BUFG port map (I => clk_dv, O => clk); bufg1 : BUFG port map (I => clk0, O => clk_fb0); bufg2 : BUFG port map (I => clk1, O => clk_fb1); bufg3 : BUFG port map (I => clk_fx, O => clk_fxo); brm_dcm_fx: DCM generic map (CLKFX_MULTIPLY => fx_mul, CLKFX_DIVIDE => fx_div) port map ( CLKIN => clkin, CLKFB => clk_fb0, DSSEN => gnd, PSCLK => gnd, PSEN => gnd, PSINCDEC => gnd, RST => rst0, CLK0 => clk0, LOCKED => lock0, CLKFX => clk_fx); brm_dcm_dv: DCM generic map (CLKDV_DIVIDE => dv_div) port map ( CLKIN => clk_fxo, CLKFB => clk_fb1, DSSEN => gnd, PSCLK => gnd, PSEN => gnd, PSINCDEC => gnd, RST => rst1(2), CLK0 => clk1, LOCKED => resetout, CLKDV => clk_dv); end;
-- This file is part of the Omega CPU Core -- Copyright 2015 - 2016 Joseph Shetaye -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as -- published by the Free Software Foundation, either version 3 of the -- License, or (at your option) any later version. -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. library IEEE; use IEEE.std_logic_1164.all; use work.Constants.all; use IEEE.Numeric_std.all; entity ALU is port ( RegisterB : in Word; RegisterC : in Word; Instruction : in Word; RegisterA : out Word; RegisterD : out Word; Carry : out std_logic; OutputReady : out std_logic; Status : out std_logic_vector(1 downto 0)); end ALU; architecture Behavioral of ALU is constant OperatorOr : std_logic_vector(1 downto 0) := "00"; constant OperatorAnd : std_logic_vector(1 downto 0) := "01"; constant OperatorXor : std_logic_vector(1 downto 0) := "10"; constant OperatorAdd : std_logic_vector(1 downto 0) := "00"; constant OperatorSub : std_logic_vector(1 downto 0) := "01"; constant OperatorMultiply : std_logic_vector(1 downto 0) := "10"; constant OperatorDivide : std_logic_vector(1 downto 0) := "11"; constant OperatorShiftRight : std_logic := '0'; constant OperatorShiftLeft : std_logic := '1'; constant OpSigned : std_logic := '0'; constant OpUnsigned : std_logic := '1'; constant OperatorEqual : std_logic := '0'; constant OperatorLessThan : std_logic := '1'; constant NormalAOnly : std_logic_vector(1 downto 0) := "00"; constant DivideOverflow : std_logic_vector(1 downto 0) := "01"; constant NormalAAndD : std_logic_vector(1 downto 0) := "10"; constant GenericError : std_logic_vector(1 downto 0) := "11"; signal Opcode_S : Opcode; signal Operator_S : Operator; signal RegisterReferenceA : RegisterReference; signal RegisterReferenceB : RegisterReference; signal RegisterReferenceC : RegisterReference; signal RegisterReferenceD : RegisterReference; signal ImmediateValue_S : ImmediateValue; signal RegisterA_S : std_logic_vector(32 downto 0); signal RegisterD_S : std_logic_vector(32 downto 0); signal Carry_S : std_logic; begin -- Behavioral Opcode_S <= GetOpcode(Instruction); Operator_S <= GetOperator(Instruction); RegisterReferenceA <= GetRegisterReferenceA(Instruction); RegisterReferenceB <= GetRegisterReferenceB(Instruction); RegisterReferenceC <= GetRegisterReferenceC(Instruction); RegisterReferenceD <= GetRegisterReferenceD(Instruction); ImmediateValue_S <= GetImmediateValue(Instruction); RegisterA <= RegisterA_S(31 downto 0); RegisterD <= RegisterD_S(31 downto 0); Carry <= Carry_S; Math: process (Opcode_S, Operator_S, RegisterReferenceA, RegisterReferenceB, RegisterReferenceC, RegisterReferenceD, ImmediateValue_S, RegisterB, RegisterC) variable Product : std_logic_vector(63 downto 0); variable SignExtendedImmediate : std_logic_vector(31 downto 0); variable Result : std_logic_vector(32 downto 0); begin -- process Math case Opcode_S is when OpcodeLogical => case Operator_S(2 downto 1) is when OperatorOr => -- Or case Operator_S(0) is when RegisterMode => RegisterD_S <= (others => '0'); RegisterA_S <= "0" & (RegisterB or RegisterC); Carry_S <= '0'; OutputReady <= '1'; Status <= NormalAOnly; when ImmediateMode => RegisterD_S <= (others => '0'); RegisterA_S <= "0" & (RegisterB or ("0000000000000000" & ImmediateValue_S)); OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when others => Carry_S <= '0'; OutputReady <= '1'; Status <= GenericError; end case; when OperatorAnd => -- And case Operator_S(0) is when RegisterMode => RegisterD_S <= (others => '0'); RegisterA_S <= "0" & (RegisterB and RegisterC); OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when ImmediateMode => RegisterD_S <= (others => '0'); RegisterA_S <= "0" & (RegisterB and ("0000000000000000" & ImmediateValue_S)); OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when others => Carry_S <= '0'; OutputReady <= '1'; Status <= GenericError; end case; when OperatorXor => --Xor case Operator_S(0) is when RegisterMode => RegisterD_S <= (others => '0'); RegisterA_S <= "0" & (RegisterB xor RegisterC); OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when ImmediateMode => RegisterD_S <= (others => '0'); RegisterA_S <= "0" & (RegisterB xor ("0000000000000000" & ImmediateValue_S)); OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when others => Carry_S <= '0'; OutputReady <= '1'; Status <= GenericError; end case; when others => OutputReady <= '1'; Status <= GenericError; end case; when OpcodeArithmetic => case Operator_S(2 downto 1) is when OperatorAdd => -- Add case Operator_S(0) is when RegisterMode => RegisterD_S <= (others => '0'); Result := std_logic_vector(("0" & unsigned(RegisterB)) + ("0" & unsigned(RegisterC))); RegisterA_S <= Result; OutputReady <= '1'; Carry_S <= Result(32); Status <= NormalAOnly; when ImmediateMode => SignExtendedImmediate:= std_logic_vector(resize(signed(ImmediateValue_S), 32)); RegisterD_S <= (others => '0'); Result := std_logic_vector(("0" & unsigned(RegisterB)) + ("0" & unsigned(SignExtendedImmediate))); OutputReady <= '1'; RegisterA_S <= Result; Carry_S <= Result(32); Status <= NormalAOnly; when others => Carry_S <= '0'; OutputReady <= '1'; Status <= GenericError; end case; when OperatorSub => -- Sub case Operator_S(0) is when RegisterMode => RegisterD_S <= (others => '0'); Result := std_logic_vector(("0" & unsigned(RegisterB)) - ("0" & unsigned(RegisterC))); OutputReady <= '1'; RegisterA_S <= Result; Carry_S <= Result(32); Status <= NormalAOnly; when ImmediateMode => SignExtendedImmediate:= std_logic_vector(resize(signed(ImmediateValue_S), 32));--std_logic_vector(not(resize(signed(ImmediateValue_S), 32)) + 1); RegisterD_S <= (others => '0'); Result := std_logic_vector(("0" & unsigned(RegisterB)) - ("0" & unsigned(SignExtendedImmediate))); RegisterA_S <= Result; OutputReady <= '1'; Carry_S <= Result(32); Status <= NormalAOnly; when others => Carry_S <= '0'; OutputReady <= '1'; Status <= GenericError; end case; when OperatorMultiply => -- Multiply case Operator_S(0) is when RegisterMode => Product:= std_logic_vector(unsigned(RegisterB) * unsigned(RegisterC)); RegisterD_S <= (others => '0'); RegisterA_S <= Product(32 downto 0); OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when ImmediateMode => SignExtendedImmediate:= std_logic_vector(resize(signed(ImmediateValue_S), 32)); Product:= std_logic_vector(unsigned(RegisterB) * unsigned(SignExtendedImmediate)); RegisterD_S <= "0" & Product(63 downto 32); RegisterA_S <= Product(32 downto 0); OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when others => Carry_S <= '0'; OutputReady <= '1'; Status <= GenericError; end case; -- when OperatorDivide => -- Divide And Remainder -- case Operator_S(0) is -- when RegisterMode => -- -- OutputReady <= '1'; -- if signed(RegisterC) = 0 then -- OutputReady <= '1'; -- Carry_S <= '0'; -- Status <= DivideOverflow; -- RegisterA_S <= (others => '0'); -- RegisterD_S <= (others => '0'); -- else -- Carry_S <= '0'; -- RegisterA_S <= "0" & std_logic_vector(signed(RegisterB) / signed(RegisterC)); -- RegisterD_S <= "0" & std_logic_vector(signed(RegisterB) rem signed(RegisterC)); -- OutputReady <= '1'; -- Status <= NormalAAndD; -- end if; -- when ImmediateMode => -- SignExtendedImmediate := std_logic_vector(resize(signed(ImmediateValue_S), 32)); -- OutputReady <= '1'; -- if signed(SignExtendedImmediate) = 0 then -- OutputReady <= '1'; -- Carry_S <= '0'; -- Status <= DivideOverflow; -- RegisterA_S <= (others => '0'); -- RegisterD_S <= (others => '0'); -- else -- Carry_S <= '0'; -- RegisterA_S <= "0" & std_logic_vector(signed(RegisterB) / signed(SignExtendedImmediate)); -- RegisterD_S <= "0" & std_logic_vector(signed(RegisterB) rem signed(SignExtendedImmediate)); -- OutputReady <= '1'; -- Status <= NormalAAndD; -- end if; -- when others => -- Carry_S <= '0'; -- OutputReady <= '1'; -- Status <= GenericError; -- end case; when others => Carry_S <= '0'; OutputReady <= '1'; Status <= GenericError; end case; when OpcodeShift => case Operator_S(2) is when OperatorShiftRight => case Operator_S(1) is when OpUnsigned => case Operator_S(0) is when RegisterMode => RegisterD_S <= (others => '0'); RegisterA_S <= std_logic_vector(shift_right("0" & unsigned(RegisterB),to_integer("0" & unsigned(RegisterC)))); OutputReady <= '1'; Status <= NormalAOnly; when ImmediateMode => RegisterD_S <= (others => '0'); RegisterA_S <= std_logic_vector(shift_right("0" & unsigned(RegisterB),to_integer(unsigned(ImmediateValue_S)))); OutputReady <= '1'; Status <= NormalAOnly; when others => Carry_S <= '0'; OutputReady <= '1'; Status <= GenericError; end case; when OpSigned => case Operator_S(0) is when RegisterMode => RegisterD_S <= (others => '0'); RegisterA_S <= std_logic_vector(shift_right("0" & signed(RegisterB),to_integer("0" & unsigned(RegisterC)))); OutputReady <= '1'; Status <= NormalAOnly; when ImmediateMode => RegisterD_S <= (others => '0'); RegisterA_S <= std_logic_vector(shift_right("0" & signed(RegisterB),to_integer(unsigned(ImmediateValue_S)))); OutputReady <= '1'; Status <= NormalAOnly; Carry_S <= '0'; when others => Carry_S <= '0'; OutputReady <= '1'; Status <= GenericError; end case; when others => OutputReady <= '1'; Carry_S <= '0'; Status <= GenericError; end case; when OperatorShiftLeft => case Operator_S(1) is when OpUnsigned => case Operator_S(0) is when RegisterMode => RegisterD_S <= (others => '0'); RegisterA_S <= std_logic_vector(shift_left("0" & unsigned(RegisterB),to_integer("0" & unsigned(RegisterC)))); OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when ImmediateMode => RegisterD_S <= (others => '0'); RegisterA_S <= std_logic_vector(shift_left("0" & unsigned(RegisterB),to_integer(unsigned(ImmediateValue_S)))); OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when others => Carry_S <= '0'; OutputReady <= '1'; Status <= GenericError; end case; when OpSigned => case Operator_S(0) is when RegisterMode => RegisterD_S <= (others => '0'); RegisterA_S <= std_logic_vector(shift_left("0" & signed(RegisterB),to_integer("0" & unsigned(RegisterC)))); OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when ImmediateMode => RegisterD_S <= (others => '0'); RegisterA_S <= std_logic_vector(shift_left("0" & signed(RegisterB),to_integer(unsigned(ImmediateValue_S)))); OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when others => OutputReady <= '1'; Carry_S <= '0'; Status <= GenericError; end case; when others => OutputReady <= '1'; Carry_S <= '0'; Status <= GenericError; end case; when others => OutputReady <= '1'; Carry_S <= '0'; Status <= GenericError; end case; when OpcodeRelational => case Operator_S(2) is when OperatorLessThan => case Operator_S(1) is when OpUnsigned => case Operator_S(0) is when RegisterMode => if ("0" & unsigned(RegisterB)) < ("0" & unsigned(RegisterC)) then RegisterD_S <= (others => '0'); RegisterA_S <= (0 => '1', others => '0'); else RegisterD_S <= (others => '0'); RegisterA_S <= (0 => '0', others => '0'); end if; OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when ImmediateMode => if ("0" & unsigned(RegisterB)) < unsigned(ImmediateValue_S) then RegisterD_S <= (others => '0'); RegisterA_S <= (0 => '1', others => '0'); else RegisterD_S <= (others => '0'); RegisterA_S <= (0 => '0', others => '0'); OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; end if; when others => OutputReady <= '1'; Carry_S <= '0'; Status <= GenericError; end case; when OpSigned => case Operator_S(0) is when RegisterMode => if signed(RegisterB) < signed(RegisterC) then RegisterD_S <= (others => '0'); RegisterA_S <= (0 => '1', others => '0'); else RegisterD_S <= (others => '0'); RegisterA_S <= (0 => '0', others => '0'); end if; OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when ImmediateMode => if signed(RegisterB) < signed(ImmediateValue_S) then RegisterD_S <= (others => '0'); RegisterA_S <= (0 => '1', others => '0'); else RegisterD_S <= (others => '0'); RegisterA_S <= (0 => '0', others => '0'); end if; OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when others => OutputReady <= '1'; Carry_S <= '0'; Status <= GenericError; end case; when others => OutputReady <= '1'; Carry_S <= '0'; Status <= GenericError; end case; when OperatorEqual => case Operator_S(0) is when RegisterMode => if RegisterB = RegisterC then RegisterD_S <= (others => '0'); RegisterA_S <= (0 => '1', others => '0'); else RegisterD_S <= (others => '0'); RegisterA_S <= (0 => '0', others => '0'); end if; Carry_S <= '0'; OutputReady <= '1'; Status <= NormalAOnly; when ImmediateMode => case Operator_S(1) is when OpUnsigned => if ("0" & unsigned(RegisterB)) = unsigned(ImmediateValue_S) then RegisterD_S <= (others => '0'); RegisterA_S <= (0 => '1', others => '0'); else RegisterD_S <= (others => '0'); RegisterA_S <= (0 => '0', others => '0'); end if; Carry_S <= '0'; OutputReady <= '1'; Status <= NormalAOnly; when OpSigned => if ("0" & signed(RegisterB)) = signed(ImmediateValue_S) then RegisterD_S <= (others => '0'); RegisterA_S <= (0 => '1', others => '0'); else RegisterD_S <= (others => '0'); RegisterA_S <= (0 => '0', others => '0'); end if; OutputReady <= '1'; Carry_S <= '0'; Status <= NormalAOnly; when others => OutputReady <= '1'; Carry_S <= '0'; Status <= GenericError; end case; when others => OutputReady <= '1'; Carry_S <= '0'; Status <= GenericError; end case; when others => OutputReady <= '1'; Carry_S <= '0'; Status <= GenericError; end case; when others => OutputReady <= '1'; Carry_S <= '0'; Status <= GenericError; end case; end process Math; end Behavioral;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core - core top file for implementation -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: cmdfifo_exdes.vhd -- -- Description: -- This is the FIFO core wrapper with BUFG instances for clock connections. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- entity cmdfifo_exdes is PORT ( WR_CLK : IN std_logic; RD_CLK : IN std_logic; VALID : OUT std_logic; ALMOST_FULL : OUT std_logic; ALMOST_EMPTY : OUT std_logic; RST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(8-1 DOWNTO 0); DOUT : OUT std_logic_vector(16-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end cmdfifo_exdes; architecture xilinx of cmdfifo_exdes is signal wr_clk_i : std_logic; signal rd_clk_i : std_logic; component cmdfifo is PORT ( WR_CLK : IN std_logic; RD_CLK : IN std_logic; VALID : OUT std_logic; ALMOST_FULL : OUT std_logic; ALMOST_EMPTY : OUT std_logic; RST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(8-1 DOWNTO 0); DOUT : OUT std_logic_vector(16-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end component; begin wr_clk_buf: bufg PORT map( i => WR_CLK, o => wr_clk_i ); rd_clk_buf: bufg PORT map( i => RD_CLK, o => rd_clk_i ); exdes_inst : cmdfifo PORT MAP ( WR_CLK => wr_clk_i, RD_CLK => rd_clk_i, VALID => valid, ALMOST_FULL => almost_full, ALMOST_EMPTY => almost_empty, RST => rst, WR_EN => wr_en, RD_EN => rd_en, DIN => din, DOUT => dout, FULL => full, EMPTY => empty); end xilinx;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core - core top file for implementation -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: cmdfifo_exdes.vhd -- -- Description: -- This is the FIFO core wrapper with BUFG instances for clock connections. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- entity cmdfifo_exdes is PORT ( WR_CLK : IN std_logic; RD_CLK : IN std_logic; VALID : OUT std_logic; ALMOST_FULL : OUT std_logic; ALMOST_EMPTY : OUT std_logic; RST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(8-1 DOWNTO 0); DOUT : OUT std_logic_vector(16-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end cmdfifo_exdes; architecture xilinx of cmdfifo_exdes is signal wr_clk_i : std_logic; signal rd_clk_i : std_logic; component cmdfifo is PORT ( WR_CLK : IN std_logic; RD_CLK : IN std_logic; VALID : OUT std_logic; ALMOST_FULL : OUT std_logic; ALMOST_EMPTY : OUT std_logic; RST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(8-1 DOWNTO 0); DOUT : OUT std_logic_vector(16-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end component; begin wr_clk_buf: bufg PORT map( i => WR_CLK, o => wr_clk_i ); rd_clk_buf: bufg PORT map( i => RD_CLK, o => rd_clk_i ); exdes_inst : cmdfifo PORT MAP ( WR_CLK => wr_clk_i, RD_CLK => rd_clk_i, VALID => valid, ALMOST_FULL => almost_full, ALMOST_EMPTY => almost_empty, RST => rst, WR_EN => wr_en, RD_EN => rd_en, DIN => din, DOUT => dout, FULL => full, EMPTY => empty); end xilinx;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core - core top file for implementation -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: cmdfifo_exdes.vhd -- -- Description: -- This is the FIFO core wrapper with BUFG instances for clock connections. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- entity cmdfifo_exdes is PORT ( WR_CLK : IN std_logic; RD_CLK : IN std_logic; VALID : OUT std_logic; ALMOST_FULL : OUT std_logic; ALMOST_EMPTY : OUT std_logic; RST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(8-1 DOWNTO 0); DOUT : OUT std_logic_vector(16-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end cmdfifo_exdes; architecture xilinx of cmdfifo_exdes is signal wr_clk_i : std_logic; signal rd_clk_i : std_logic; component cmdfifo is PORT ( WR_CLK : IN std_logic; RD_CLK : IN std_logic; VALID : OUT std_logic; ALMOST_FULL : OUT std_logic; ALMOST_EMPTY : OUT std_logic; RST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(8-1 DOWNTO 0); DOUT : OUT std_logic_vector(16-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end component; begin wr_clk_buf: bufg PORT map( i => WR_CLK, o => wr_clk_i ); rd_clk_buf: bufg PORT map( i => RD_CLK, o => rd_clk_i ); exdes_inst : cmdfifo PORT MAP ( WR_CLK => wr_clk_i, RD_CLK => rd_clk_i, VALID => valid, ALMOST_FULL => almost_full, ALMOST_EMPTY => almost_empty, RST => rst, WR_EN => wr_en, RD_EN => rd_en, DIN => din, DOUT => dout, FULL => full, EMPTY => empty); end xilinx;
-- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers -- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com> -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. use std.textio.all; library ieee; use ieee.math_real.all; -- for uniform --use ieee.numeric_std.all; -- for TO_UNSIGNED use ieee.std_logic_1164.all; entity arbiter is port ( req : in bit; gnt : out bit := '1'; -- bus_transfer_cycles_counter_out : out integer := 0; arb_latency_cycles_counter_out : out integer := 0; pciclk : in bit ); end arbiter; -- Architecture begin architecture V1 of arbiter is --------------- Random number generator configuration --------------- constant arbiter_seed1_value : positive := 14; constant arbiter_seed2_value : positive := 49; --------------- Bus arbitration latency configuration --------------- constant min_arbitration_latency : positive := 1; constant max_arbitration_latency : positive := 100; --------------- Burst size configuration --------------- constant dma_burst_size_in_cycles : integer := 32; -- DMA busrt size = 256 bytes (PCI-X bus) --constant dma_burst_size_in_cycles : integer := 64; -- DMA busrt size = 512 bytes (PCI-X bus) --constant dma_burst_size_in_cycles : integer := 128; -- DMA busrt size = 1024 bytes (PCI-X bus) --constant dma_burst_size_in_cycles : integer := 256; -- DMA busrt size = 2048 bytes (PCI-X bus) --constant dma_burst_size_in_cycles : integer := 512; -- DMA busrt size = 4096 bytes (PCI-X bus) -- ****** In the future, constant pcilck_period should be removed a function based on the pciclk signal should be implemented --constant pciclk_period : time := 0.03030303 us; -- PCI 33 --constant pciclk_period : time := 0.015151515 us; -- PCI-X 66 constant pciclk_period : time := 0.007518797 us; -- PCI-X 133 --constant pciclk_period : time := 0.003759398 us; -- PCI-X 266 --constant pciclk_period : time := 0.001876173 us; -- PCI-X 533 --------------- Variables Declarations --------------- shared variable random_cycles_count : integer := 0; shared variable bus_transfer_cycles_counter : integer := dma_burst_size_in_cycles; shared variable total_latency_cycles : integer := 0; shared variable total_bus_transfer_cycles : integer := 0; shared variable latency_cycles_count : integer := 0; shared variable gnt_value : bit := '1'; shared variable max_arbitration_latency_in_cycles : integer; -- Variables needed for arbiter FSM type pci_bus_state is (idle, waiting_arbitration_latency, bus_granted); shared variable state : pci_bus_state := idle; shared variable next_state : pci_bus_state := idle; -- Variables needed for printing out simulation statistics shared variable transmission_cycles_count : natural := 0; shared variable non_transmission_cycles_count : natural := 0; -- Architecture Begin begin -- Arbiter FSM pci_arbiter_fsm: process begin wait until pciclk'event and pciclk = '1'; case state is when idle => gnt_value := '1'; bus_transfer_cycles_counter := 0; latency_cycles_count := 0; if req = '1' then gnt_value := '1'; next_state := idle; elsif req = '0' then --latency_cycles_count := generate_random_latency_in_cycles; latency_cycles_count := random_cycles_count; total_latency_cycles := total_latency_cycles + latency_cycles_count; bus_transfer_cycles_counter := dma_burst_size_in_cycles; --total_bus_transfer_cycles = total_bus_transfer_cycles + bus_transfer_cycles_counter; assert false report "pci_arbiter_fsm: waiting_arbitration_latency" severity note; next_state := waiting_arbitration_latency; end if; when waiting_arbitration_latency => if req = '1' then next_state := idle; elsif req = '0' and latency_cycles_count = 0 then gnt_value := '0'; assert false report "pci_arbiter_fsm: bus_granted" severity note; next_state := bus_granted; elsif req = '0' and latency_cycles_count > 0 then latency_cycles_count := latency_cycles_count - 1; next_state := waiting_arbitration_latency; end if; when bus_granted => if req = '0' and gnt_value = '1' and bus_transfer_cycles_counter > 0 and gnt_value = '0' then assert false report "pci_arbiter_fsm: bus_granted" severity note; next_state := bus_granted; elsif req = '0' and gnt_value = '1' and bus_transfer_cycles_counter = 0 then next_state := idle; elsif (req = '0' and bus_transfer_cycles_counter = 0) or req = '1' then next_state := idle; end if; end case; state := next_state; end process pci_arbiter_fsm; -- FSM of Latecy Cycles Generator random_number_generator_fsm: process type generator_state is (idle, generating_random_number, waiting); variable state : generator_state := idle; variable next_state : generator_state := idle; variable random_number : integer := 1; variable seed1 : positive := arbiter_seed1_value; variable seed2 : positive := arbiter_seed2_value; variable rand: real; file random_arbitration_cycles_file : text open write_mode is "random_arbitration_cycles.out"; variable output_line : line; begin case state is when idle => wait until req'event and req = '0'; assert false report "generating random arbitration latency" severity note; next_state := generating_random_number; when generating_random_number => uniform(seed1, seed2, rand); -- Since rand values are in the interval 0..1, the values are multiplicated by 1000 and rounded. -- This way, an integer random value in the interval 1..1000 is obtained random_number := integer(round(rand*1000.0)); --random_number := integer(round(rand * max_arbitration_latency)); if random_number >= min_arbitration_latency and random_number <= max_arbitration_latency then random_cycles_count := random_number; write(output_line, random_cycles_count); writeline(random_arbitration_cycles_file, output_line); next_state := waiting; else next_state := generating_random_number; end if; when waiting => wait until req'event and req = '0'; next_state := generating_random_number; end case; state := next_state; end process random_number_generator_fsm; arb_cycles_counter_out_driver: process begin wait until pciclk'event and pciclk = '0'; -- bus_transfer_cycles_counter_out <= bus_transfer_cycles_counter; arb_latency_cycles_counter_out <= latency_cycles_count; end process arb_cycles_counter_out_driver; output_signals_driver: process begin wait until pciclk'event and pciclk = '1'; gnt <= gnt_value; end process output_signals_driver; end V1;
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Sun Apr 09 07:04:02 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode synth_stub -- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_processing_system7_0_0_1/system_processing_system7_0_0_stub.vhdl -- Design : system_processing_system7_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity system_processing_system7_0_0 is Port ( TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); end system_processing_system7_0_0; architecture stub of system_processing_system7_0_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2016.4"; begin end;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: outpad -- File: outpad.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: output pad with technology wrapper ------------------------------------------------------------------------------ library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; use techmap.allpads.all; entity outpad is generic (tech : integer := 0; level : integer := 0; slew : integer := 0; voltage : integer := x33v; strength : integer := 12); port (pad : out std_ulogic; i : in std_ulogic); end; architecture rtl of outpad is signal padx, gnd, vcc : std_ulogic; begin gnd <= '0'; vcc <= '1'; gen0 : if has_pads(tech) = 0 generate pad <= i after 2 ns when slew = 0 else i; end generate; xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) generate x0 : virtex_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate x0 : axcel_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; atc : if (tech = atc18s) generate x0 : atc18_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; atcrh : if (tech = atc18rha) generate x0 : atc18rha_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; um : if (tech = umc) generate x0 : umc_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; rhu : if (tech = rhumc) generate x0 : rhumc_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; ihp : if (tech = ihp25) generate x0 : ihp25_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; ihprh : if (tech = ihp25rh) generate x0 : ihp25rh_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; rh18t : if (tech = rhlib18t) generate x0 : rh_lib18t_iopad generic map (strength) port map (padx, i, gnd, open); pad <= padx; end generate; ut025 : if (tech = ut25) generate x0 : ut025crh_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; pere : if (tech = peregrine) generate x0 : peregrine_toutpad generic map (level, slew, voltage, strength) port map(pad, i, vcc); end generate; nex : if (tech = easic90) generate x0 : nextreme_toutpad generic map (level, slew, voltage, strength) port map(pad, i, vcc); end generate; end; library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; entity outpadv is generic (tech : integer := 0; level : integer := 0; slew : integer := 0; voltage : integer := 0; strength : integer := 12; width : integer := 1); port ( pad : out std_logic_vector(width-1 downto 0); i : in std_logic_vector(width-1 downto 0)); end; architecture rtl of outpadv is begin v : for j in width-1 downto 0 generate x0 : outpad generic map (tech, level, slew, voltage, strength) port map (pad(j), i(j)); end generate; end;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: outpad -- File: outpad.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: output pad with technology wrapper ------------------------------------------------------------------------------ library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; use techmap.allpads.all; entity outpad is generic (tech : integer := 0; level : integer := 0; slew : integer := 0; voltage : integer := x33v; strength : integer := 12); port (pad : out std_ulogic; i : in std_ulogic); end; architecture rtl of outpad is signal padx, gnd, vcc : std_ulogic; begin gnd <= '0'; vcc <= '1'; gen0 : if has_pads(tech) = 0 generate pad <= i after 2 ns when slew = 0 else i; end generate; xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) generate x0 : virtex_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate x0 : axcel_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; atc : if (tech = atc18s) generate x0 : atc18_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; atcrh : if (tech = atc18rha) generate x0 : atc18rha_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; um : if (tech = umc) generate x0 : umc_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; rhu : if (tech = rhumc) generate x0 : rhumc_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; ihp : if (tech = ihp25) generate x0 : ihp25_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; ihprh : if (tech = ihp25rh) generate x0 : ihp25rh_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; rh18t : if (tech = rhlib18t) generate x0 : rh_lib18t_iopad generic map (strength) port map (padx, i, gnd, open); pad <= padx; end generate; ut025 : if (tech = ut25) generate x0 : ut025crh_outpad generic map (level, slew, voltage, strength) port map (pad, i); end generate; pere : if (tech = peregrine) generate x0 : peregrine_toutpad generic map (level, slew, voltage, strength) port map(pad, i, vcc); end generate; nex : if (tech = easic90) generate x0 : nextreme_toutpad generic map (level, slew, voltage, strength) port map(pad, i, vcc); end generate; end; library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; entity outpadv is generic (tech : integer := 0; level : integer := 0; slew : integer := 0; voltage : integer := 0; strength : integer := 12; width : integer := 1); port ( pad : out std_logic_vector(width-1 downto 0); i : in std_logic_vector(width-1 downto 0)); end; architecture rtl of outpadv is begin v : for j in width-1 downto 0 generate x0 : outpad generic map (tech, level, slew, voltage, strength) port map (pad(j), i(j)); end generate; end;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity clock_divider_top is Port ( CLK_PB4 : in STD_LOGIC; LED1 : out STD_LOGIC; LED2 : out STD_LOGIC); end clock_divider_top; architecture Behavioral of clock_divider_top is signal CLK_DIV : std_logic_vector (4 downto 0); -- 5 bits begin -- clock divider process (CLK_PB4) begin if (CLK_PB4'Event and CLK_PB4 = '1') then CLK_DIV <= CLK_DIV + '1'; end if; end process; LED1 <= CLK_PB4; -- connect LED 1 to clock source LED2 <= CLK_DIV(4); -- connect LED 2 to divided clock end Behavioral;
-- -*- vhdl -*- ------------------------------------------------------------------------------- -- Copyright (c) 2012, The CARPE Project, All rights reserved. -- -- See the AUTHORS file for individual contributors. -- -- -- -- Copyright and related rights are licensed under the Solderpad -- -- Hardware License, Version 0.51 (the "License"); you may not use this -- -- file except in compliance with the License. You may obtain a copy of -- -- the License at http://solderpad.org/licenses/SHL-0.51. -- -- -- -- Unless required by applicable law or agreed to in writing, software, -- -- hardware and materials distributed under this License is distributed -- -- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -- -- either express or implied. See the License for the specific language -- -- governing permissions and limitations under the License. -- ------------------------------------------------------------------------------- library ieee; use ieee.numeric_std.all; library util; use util.numeric_pkg.all; use util.logic_pkg.all; -- right shift unsigned result zero sel in_left in_right -- 0 00 1 1234 1 00 XXXX XXXX -- 0 01 1 234R 0 01 1234 RRRR -- 0 10 1 34RR 0 10 1234 RRRR -- 0 11 1 4RRR 0 11 1234 RRRR -- 1 00 1 1234 1 00 XXXX XXXX -- 1 01 1 L123 0 11 LLLL 1234 -- 1 10 1 LL12 0 10 LLLL 1234 -- 1 11 1 LLL1 0 01 LLLL 1234 -- 0 00 0 1234 1 00 XXXX XXXX -- 0 01 0 234R 0 01 1234 RRRR -- 0 10 0 LL12 0 10 LLLL 1234 -- 0 11 0 L123 0 11 LLLL 1234 -- 1 00 0 1234 1 00 XXXX XXXX -- 1 01 0 L123 0 11 LLLL 1234 -- 1 10 0 34RR 0 10 1234 RRRR -- 1 11 0 234R 0 01 1234 RRRR -- right shift unsigned result zero sel in_left in_right -- 0 000 1 12345678 1 XXX 12345678 RRRRRRRR -- 0 001 1 2345678R 0 001 12345678 RRRRRRRR -- 0 010 1 345678RR 0 010 12345678 RRRRRRRR -- 0 011 1 45678RRR 0 011 12345678 RRRRRRRR -- 0 100 1 5678RRRR 0 100 12345678 RRRRRRRR -- 0 101 1 678RRRRR 0 101 12345678 RRRRRRRR -- 0 110 1 78RRRRRR 0 110 12345678 RRRRRRRR -- 0 111 1 8RRRRRRR 0 111 12345678 RRRRRRRR -- 1 000 1 12345678 1 XXX LLLLLLLL 12345678 -- 1 001 1 L1234567 0 111 LLLLLLLL 12345678 -- 1 010 1 LL123456 0 110 LLLLLLLL 12345678 -- 1 011 1 LLL12345 0 101 LLLLLLLL 12345678 -- 1 100 1 LLLL1234 0 100 LLLLLLLL 12345678 -- 1 101 1 LLLLL123 0 011 LLLLLLLL 12345678 -- 1 110 1 LLLLLL12 0 010 LLLLLLLL 12345678 -- 1 111 1 LLLLLLL1 0 001 LLLLLLLL 12345678 -- 0 000 0 12345678 1 000 12345678 RRRRRRRR -- 0 001 0 2345678R 0 001 12345678 RRRRRRRR -- 0 010 0 345678RR 0 010 12345678 RRRRRRRR -- 0 011 0 45678RRR 0 011 12345678 RRRRRRRR -- 0 100 0 LLLL1234 0 100 LLLLLLLL 12345678 -- 0 101 0 LLL12345 0 101 LLLLLLLL 12345678 -- 0 110 0 LL123456 0 110 LLLLLLLL 12345678 -- 0 111 0 L1234567 0 111 LLLLLLLL 12345678 -- 1 000 0 12345678 1 000 LLLLLLLL 12345678 -- 1 001 0 L1234567 0 111 LLLLLLLL 12345678 -- 1 010 0 LL123456 0 110 LLLLLLLL 12345678 -- 1 011 0 LLL12345 0 101 LLLLLLLL 12345678 -- 1 100 0 5678RRRR 0 100 12345678 RRRRRRRR -- 1 101 0 45678RRR 0 011 12345678 RRRRRRRR -- 1 110 0 345678RR 0 010 12345678 RRRRRRRR -- 1 111 0 2345678R 0 001 12345678 RRRRRRRR architecture rtl of shifter_inferred is constant barrel_size : natural := integer_minimum(shift_bits, log2ceil(src_bits)); type barrel_type is array(0 to barrel_size) of std_ulogic_vector(2*src_bits-1 downto 0); type comb_type is record shift_is_neg : std_ulogic; right_shift : std_ulogic; right_shift_fill : std_ulogic; abs_shift : std_ulogic_vector(shift_bits downto 0); barrel_sel : std_ulogic_vector(barrel_size-1 downto 0); barrel : barrel_type; shift_is_zero : std_ulogic; end record; signal c : comb_type; begin c.shift_is_neg <= not shift_unsgnd and shift(shift_bits-1); c.right_shift <= (right xor c.shift_is_neg); c.right_shift_fill <= not unsgnd and src(src_bits-1); c.abs_shift <= logic_if(right, std_ulogic_vector(-signed(shift)), shift); c.barrel_sel <= c.abs_shift(barrel_size-1 downto 0); -- barrel shifter with c.right_shift select c.barrel(0) <= (src & logic_if(rot, src, (src_bits-1 downto 0 => '0')) ) when '0', (logic_if(rot, src, (src_bits-1 downto 0 => c.right_shift_fill)) & src ) when '1', (others => 'X') when others; barrel_loop : for n in 0 to barrel_size-1 generate with c.barrel_sel(n) select c.barrel(n+1) <= c.barrel(n) when '0', c.barrel(n)(2*src_bits-2**n-1 downto 0) & (2**n-1 downto 0 => 'X') when '1', (others => 'X') when others; end generate; c.shift_is_zero <= all_zeros(shift); result_1 : if shift_bits > log2(src_bits) generate blk : block signal shift_diff : std_ulogic_vector(shift_bits downto 0); signal shift_overflow : std_ulogic; signal result_sel : std_ulogic_vector(1 downto 0); begin shift_diff <= std_ulogic_vector(to_unsigned(src_bits-1, shift_bits+1) - unsigned('0' & c.abs_shift)); shift_overflow <= shift_diff(shift_bits-1); result_sel <= (0 => c.shift_is_zero, 1 => shift_overflow ); with result_sel select result <= c.barrel(barrel_size)(2*src_bits-1 downto src_bits) when "00", src when "01", (others => c.right_shift and c.right_shift_fill) when "10", (others => 'X') when others; end block; end generate; result_2 : if shift_bits <= log2(src_bits) generate with c.shift_is_zero select result <= c.barrel(barrel_size)(2*src_bits-1 downto src_bits) when '0', src when '1', (others => 'X') when others; end generate; end;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: sdmctrl -- File: sdmctrl.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: SDRAM memory controller to fit with LEON2 memory controller. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; library gaisler; use gaisler.memctrl.all; entity sdmctrl is generic ( pindex : integer := 0; invclk : integer := 0; fast : integer := 0; wprot : integer := 0; sdbits : integer := 32; pageburst : integer := 0; mobile : integer := 0 ); port ( rst : in std_ulogic; clk : in std_ulogic; sdi : in sdram_in_type; sdo : out sdram_out_type; apbi : in apb_slv_in_type; wpo : in wprot_out_type; sdmo : out sdram_mctrl_out_type ); end; architecture rtl of sdmctrl is constant WPROTEN : boolean := (wprot /= 0); constant SDINVCLK : boolean := (invclk /= 0); constant BUS64 : boolean := (sdbits = 64); constant PM_PD : std_logic_vector(2 downto 0) := "001"; constant PM_SR : std_logic_vector(2 downto 0) := "010"; constant PM_DPD : std_logic_vector(2 downto 0) := "101"; type mcycletype is (midle, active, leadout); type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8, wr1, wr2, wr3, wr4, wr5, sidle, sref, pd, dpd); type icycletype is (iidle, pre, ref, lmode, emode, finish); -- sdram configuration register type sdram_cfg_type is record command : std_logic_vector(2 downto 0); csize : std_logic_vector(1 downto 0); bsize : std_logic_vector(2 downto 0); casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles trfc : std_logic_vector(2 downto 0); trp : std_ulogic; -- precharge to activate: 2/3 clock cycles refresh : std_logic_vector(14 downto 0); renable : std_ulogic; pageburst : std_ulogic; mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update) tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update) pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update) pmode : std_logic_vector(2 downto 0); -- Power-Saving mode txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing cke : std_ulogic; -- Clock enable end record; -- local registers type reg_type is record hready : std_ulogic; hsel : std_ulogic; bdrive : std_ulogic; burst : std_ulogic; busy : std_ulogic; bdelay : std_ulogic; wprothit : std_ulogic; startsd : std_ulogic; aload : std_ulogic; mstate : mcycletype; sdstate : sdcycletype; cmstate : mcycletype; istate : icycletype; icnt : std_logic_vector(2 downto 0); cfg : sdram_cfg_type; trfc : std_logic_vector(3 downto 0); refresh : std_logic_vector(14 downto 0); sdcsn : std_logic_vector(1 downto 0); sdwen : std_ulogic; rasn : std_ulogic; casn : std_ulogic; dqm : std_logic_vector(7 downto 0); bsel : std_ulogic; haddr : std_logic_vector(31 downto 10); -- only needed to keep address lines from switch too much address : std_logic_vector(16 downto 2); -- memory address idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref end record; signal r, ri : reg_type; begin ctrl : process(rst, apbi, sdi, wpo, r) variable v : reg_type; -- local variables for registers variable startsd : std_ulogic; variable dataout : std_logic_vector(31 downto 0); -- data from memory variable haddr : std_logic_vector(31 downto 0); variable regsd : std_logic_vector(31 downto 0); -- data from registers variable dqm : std_logic_vector(7 downto 0); variable raddr : std_logic_vector(12 downto 0); variable adec : std_ulogic; variable busy : std_ulogic; variable aload : std_ulogic; variable rams : std_logic_vector(1 downto 0); variable hresp : std_logic_vector(1 downto 0); variable ba : std_logic_vector(1 downto 0); variable lline : std_logic_vector(2 downto 0); variable rline : std_logic_vector(2 downto 0); variable lineburst : boolean; variable arefresh : std_logic; begin -- Variable default settings to avoid latches v := r; startsd := '0'; v.busy := '0'; hresp := HRESP_OKAY; lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel; rline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel; arefresh := '0'; if sdi.hready = '1' then v.hsel := sdi.hsel; end if; if (sdi.hready and sdi.hsel ) = '1' then if sdi.htrans(1) = '1' then v.hready := '0'; end if; end if; if fast = 1 then haddr := sdi.rhaddr; else haddr := sdi.haddr; end if; if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then lineburst := true; else lineburst := false; end if; -- main state case sdi.hsize is when "00" => case sdi.rhaddr(1 downto 0) is when "00" => dqm := "11110111"; when "01" => dqm := "11111011"; when "10" => dqm := "11111101"; when others => dqm := "11111110"; end case; when "01" => if sdi.rhaddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if; when others => dqm := "11110000"; end case; if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if; -- main FSM case r.mstate is when midle => if (v.hsel and sdi.nhtrans(1)) = '1' then if (r.sdstate = sidle) and (r.cfg.command = "000") and (r.cmstate = midle) and (sdi.idle = '1') then if fast = 1 then v.startsd := '1'; else startsd := '1'; end if; v.mstate := active; elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd)) and (r.cfg.command = "000") and (r.cmstate = midle) --and (v.hio = '0') then v.startsd := '1'; if r.sdstate = dpd then -- Error response when on Deep Power-Down mode hresp := HRESP_ERROR; else v.mstate := active; end if; end if; end if; when others => null; end case; startsd := r.startsd or startsd; -- generate row and column address size case r.cfg.csize is when "00" => raddr := haddr(22 downto 10); when "01" => raddr := haddr(23 downto 11); when "10" => raddr := haddr(24 downto 12); when others => if r.cfg.bsize = "111" then raddr := haddr(26 downto 14); else raddr := haddr(25 downto 13); end if; end case; -- generate bank address ba := genmux(r.cfg.bsize, haddr(28 downto 21)) & genmux(r.cfg.bsize, haddr(27 downto 20)); -- generate chip select if BUS64 then adec := genmux(r.cfg.bsize, haddr(30 downto 23)); v.bsel := genmux(r.cfg.bsize, sdi.rhaddr(29 downto 22)); else adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0'; end if; if (sdi.srdis = '0') and (r.cfg.bsize = "111") then adec := not adec; end if; rams := adec & not adec; if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if; if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if; -- sdram access FSM case r.sdstate is when sidle => v.bdelay := '0'; if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then v.address(16 downto 2) := ba & raddr; v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1; v.startsd := '0'; elsif (r.idlecnt = "0000") and (r.cfg.command = "000") and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then case r.cfg.pmode is when PM_SR => v.cfg.cke := '0'; v.sdstate := sref; v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS) when PM_PD => v.cfg.cke := '0'; v.sdstate := pd; when PM_DPD => v.cfg.cke := '0'; v.sdstate := dpd; v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1'; when others => end case; end if; when act1 => v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; v.haddr := sdi.rhaddr(31 downto 10); if r.cfg.casdel = '1' then v.sdstate := act2; else v.sdstate := act3; v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1); end if; if WPROTEN then v.wprothit := wpo.wprothit; if wpo.wprothit = '1' then hresp := HRESP_ERROR; end if; end if; when act2 => v.sdstate := act3; v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1); if WPROTEN and (r.wprothit = '1') then hresp := HRESP_ERROR; v.hready := '0'; end if; when act3 => v.casn := '0'; v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2); v.dqm := dqm; v.burst := r.hready; if sdi.hwrite = '1' then v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '1'; if sdi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if; if WPROTEN and (r.wprothit = '1') then hresp := HRESP_ERROR; v.hready := '1'; v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '0'; v.casn := '1'; end if; else v.sdstate := rd1; end if; when wr1 => v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2); if (((r.burst and r.hready) = '1') and (sdi.rhtrans = "11")) and not (WPROTEN and (r.wprothit = '1')) then v.hready := sdi.htrans(0) and sdi.htrans(1) and r.hready; if ((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh v.hready := '0'; end if; else v.sdstate := wr2; v.bdrive := '0'; v.casn := '1'; v.sdwen := '1'; v.dqm := (others => '1'); end if; when wr2 => if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.hsel = '1') then if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3; elsif (r.trfc(2 downto 1) = "00") then if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if; v.sdstate := wr3; end if; when wr3 => if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.sdwen = '1') and (r.hsel = '1') then if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3; elsif (r.cfg.trp = '1') then v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; else v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; if r.trfc = "0000" then v.sdstate := sidle; end if; end if; when wr4 => v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; if (r.cfg.trp = '1') then v.sdstate := wr5; else if r.trfc = "0000" then v.sdstate := sidle; end if; end if; when wr5 => if r.trfc = "0000" then v.sdstate := sidle; v.idlecnt := (others => '1'); end if; when rd1 => v.casn := '1'; v.sdstate := rd7; if lineburst and (sdi.htrans = "11") then if sdi.rhaddr(4 downto 2) = "111" then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; when rd7 => v.casn := '1'; if r.cfg.casdel = '1' then v.sdstate := rd2; if lineburst and (sdi.htrans = "11") then if sdi.rhaddr(4 downto 2) = "110" then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; else v.sdstate := rd3; if sdi.htrans /= "11" then if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if; elsif lineburst then if sdi.rhaddr(4 downto 2) = "110" then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; end if; when rd2 => v.casn := '1'; v.sdstate := rd3; if sdi.htrans /= "11" then -- v.rasn := '0'; v.sdwen := '0'; if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if; elsif lineburst then if sdi.rhaddr(4 downto 2) = "101" then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; if v.sdwen = '0' then v.dqm := (others => '1'); end if; when rd3 => v.sdstate := rd4; v.hready := '1'; v.casn := '1'; if r.sdwen = '0' then v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); elsif lineburst and (sdi.htrans = "11") and (r.casn = '1') then if sdi.rhaddr(4 downto 2) = ("10" & not r.cfg.casdel) then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; when rd4 => v.hready := '1'; v.casn := '1'; if (sdi.htrans /= "11") or (r.sdcsn = "11") or ((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh then v.hready := '0'; v.dqm := (others => '1'); if (r.sdcsn /= "11") then v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5; else if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if; end if; elsif lineburst then if (sdi.rhaddr(4 downto 2) = lline) and (r.casn = '1') then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; when rd5 => if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if; v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1'); v.casn := '1'; when rd6 => v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1'); v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; when sref => if (startsd = '1') -- and (r.hio = '0')) or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then if r.trfc = "0000" then -- Minimum duration (= tRAS) v.cfg.cke := '1'; v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1'; end if; if r.cfg.cke = '1' then if (r.idlecnt = "0000") then -- tXSR ns with NOP v.sdstate := sidle; v.idlecnt := (others => '1'); v.sref_tmpcom := r.cfg.command; v.cfg.command := "100"; end if; else v.idlecnt := r.cfg.txsr; end if; end if; when pd => if (startsd = '1') -- and (r.hio = '0')) or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then v.cfg.cke := '1'; v.sdstate := sidle; v.idlecnt := (others => '1'); end if; when dpd => v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1'; v.cfg.renable := '0'; if (startsd = '1') then -- and r.hio = '0') then v.hready := '1'; -- ack all accesses with Error response v.startsd := '0'; hresp := HRESP_ERROR; elsif r.cfg.pmode /= PM_DPD then v.cfg.cke := '1'; if r.cfg.cke = '1' then v.sdstate := sidle; v.idlecnt := (others => '1'); v.cfg.renable := '1'; end if; end if; when others => v.sdstate := sidle; v.idlecnt := (others => '1'); end case; -- sdram commands case r.cmstate is when midle => if r.sdstate = sidle then case r.cfg.command is when "010" => -- precharge if (sdi.idle = '1') then v.busy := '1'; v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0'; v.address(12) := '1'; v.cmstate := active; end if; when "100" => -- auto-refresh v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0'; v.cmstate := active; when "110" => if (sdi.idle = '1') then v.busy := '1'; v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0'; v.sdwen := '0'; v.cmstate := active; if lineburst then v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011"; else v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111"; end if; end if; when "111" => -- Load Ext-Mode Reg if (sdi.idle = '1') then v.busy := '1'; v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0'; v.sdwen := '0'; v.cmstate := active; v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0); end if; when others => null; end case; end if; when active => v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1'; v.sdwen := '1'; --v.cfg.command := "000"; v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000"; v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; when leadout => if r.trfc = "0000" then v.cmstate := midle; end if; end case; -- sdram init case r.istate is when iidle => v.cfg.cke := '1'; if (sdi.idle and sdi.enable) = '1' and r.cfg.cke = '1' then v.cfg.command := "010"; v.istate := pre; end if; when pre => if r.cfg.command = "000" then v.cfg.command := "100"; v.istate := ref; v.icnt := "111"; end if; when ref => if r.cfg.command = "000" then v.cfg.command := "100"; v.icnt := r.icnt - 1; if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if; end if; when lmode => if r.cfg.command = "000" then if r.cfg.mobileen = "11" then v.cfg.command := "111"; v.istate := emode; else v.istate := finish; end if; end if; when emode => if r.cfg.command = "000" then v.istate := finish; end if; when others => if sdi.enable = '0' and r.sdstate /= dpd then v.istate := iidle; end if; end case; if (sdi.hready and sdi.hsel ) = '1' then if sdi.htrans(1) = '0' then v.hready := '1'; end if; end if; -- second part of main fsm case r.mstate is when active => if v.hready = '1' then v.mstate := midle; end if; when others => null; end case; -- sdram refresh counter if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then v.refresh := r.refresh - 1; if (v.refresh(14) and not r.refresh(14)) = '1' then v.refresh := r.cfg.refresh; v.cfg.command := "100"; arefresh := '1'; end if; end if; -- APB register access if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then case apbi.paddr(3 downto 2) is when "01" => if pageburst = 2 then v.cfg.pageburst := apbi.pwdata(17); end if; if sdi.enable = '1' then v.cfg.command(2 downto 1) := apbi.pwdata(20 downto 19); end if; v.cfg.csize := apbi.pwdata(22 downto 21); v.cfg.bsize := apbi.pwdata(25 downto 23); v.cfg.casdel := apbi.pwdata(26); v.cfg.trfc := apbi.pwdata(29 downto 27); v.cfg.trp := apbi.pwdata(30); v.cfg.renable := apbi.pwdata(31); when "10" => v.cfg.refresh := apbi.pwdata(26 downto 12); v.refresh := (others => '0'); when "11" => if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := apbi.pwdata(31); end if; if r.cfg.pmode = "000" then v.cfg.cke := apbi.pwdata(30); end if; if r.cfg.mobileen(1) = '1' then if sdi.enable = '1' then v.cfg.command(0) := apbi.pwdata(29); end if; v.cfg.txsr := apbi.pwdata(23 downto 20); v.cfg.pmode := apbi.pwdata(18 downto 16); v.cfg.ds(3 downto 2) := apbi.pwdata( 6 downto 5); v.cfg.tcsr(3 downto 2) := apbi.pwdata( 4 downto 3); v.cfg.pasr(5 downto 3) := apbi.pwdata( 2 downto 0); end if; when others => end case; end if; -- Disable CS and DPD when Mobile SDR is Disabled if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if; -- Update EMR when ds, tcsr or pasr change if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2); end if; if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2); end if; if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3); end if; end if; regsd := (others => '0'); case apbi.paddr(3 downto 2) is when "01" => regsd(31 downto 19) := r.cfg.renable & r.cfg.trp & r.cfg.trfc & r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command(2 downto 1); if not lineburst then regsd(17) := '1'; end if; regsd(16) := r.cfg.mobileen(1); when "11" => regsd(31) := r.cfg.mobileen(0); regsd(30) := r.cfg.cke; regsd(30) := r.cfg.command(0); regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0); when others => regsd(26 downto 12) := r.cfg.refresh; end case; sdmo.prdata <= regsd; -- synchronise with sram/prom controller if fast = 0 then if (r.sdstate < wr4) or (v.hsel = '1') then v.busy := '1';end if; else if (r.sdstate < wr4) or (r.startsd = '1') then v.busy := '1';end if; end if; v.busy := v.busy or r.bdelay; busy := v.busy or r.busy; v.aload := r.busy and not v.busy; aload := v.aload; -- generate memory address sdmo.address <= v.address; -- reset if rst = '0' then v.sdstate := sidle; v.mstate := midle; v.istate := iidle; v.cmstate := midle; v.hsel := '0'; v.cfg.command := "000"; v.cfg.csize := "10"; v.cfg.bsize := "000"; v.cfg.casdel := '1'; v.cfg.trfc := "111"; v.cfg.renable := '0'; v.cfg.trp := '1'; v.dqm := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1'; v.hready := '1'; v.startsd := '0'; if (pageburst = 2) then v.cfg.pageburst := '0'; end if; if mobile >= 2 then v.cfg.mobileen := "11"; elsif mobile = 1 then v.cfg.mobileen := "10"; else v.cfg.mobileen := "00"; end if; v.cfg.txsr := (others => '1'); v.cfg.pmode := (others => '0'); v.cfg.ds := (others => '0'); v.cfg.tcsr := (others => '0'); v.cfg.pasr := (others => '0'); if mobile >= 2 then v.cfg.cke := '0'; else v.cfg.cke := '1'; end if; v.sref_tmpcom := "000"; v.idlecnt := (others => '1'); end if; ri <= v; sdmo.bdrive <= v.bdrive; --sdo.sdcke <= (others => '1'); sdo.sdcke <= (others => r.cfg.cke); sdo.sdcsn <= r.sdcsn; sdo.sdwen <= r.sdwen; sdo.dqm <= r.dqm; sdo.rasn <= r.rasn; sdo.casn <= r.casn; sdmo.busy <= busy; sdmo.aload <= aload; sdmo.hready <= r.hready; sdmo.vhready <= v.hready; sdmo.hresp <= hresp; sdmo.hsel <= r.hsel; sdmo.bsel <= r.bsel; end process; regs : process(clk,rst) begin if rising_edge(clk) then r <= ri; if rst = '0' then r.icnt <= (others => '0'); end if; end if; if rst = '0' then r.bdrive <= '0'; r.sdcsn <= (others => '1'); end if; end process; end;
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 -- IP Revision: 5 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_3_5; USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5; ENTITY title1 IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END title1; ARCHITECTURE title1_arch OF title1 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF title1_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_3_5 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_USE_URAM : INTEGER; C_EN_RDADDRA_CHG : INTEGER; C_EN_RDADDRB_CHG : INTEGER; C_EN_DEEPSLEEP_PIN : INTEGER; C_EN_SHUTDOWN_PIN : INTEGER; C_EN_SAFETY_CKT : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); sleep : IN STD_LOGIC; deepsleep : IN STD_LOGIC; shutdown : IN STD_LOGIC; rsta_busy : OUT STD_LOGIC; rstb_busy : OUT STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_3_5; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF title1_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF title1_arch : ARCHITECTURE IS "title1,blk_mem_gen_v8_3_5,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF title1_arch: ARCHITECTURE IS "title1,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=title1.mif,C" & "_INIT_FILE=title1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=13104,C_READ_DEPTH_A=13104,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=" & "13104,C_READ_DEPTH_B=13104,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WAR" & "N_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=2,C_EST_POWER_SUMMARY=Estimated Power for IP _ 6.153268 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; BEGIN U0 : blk_mem_gen_v8_3_5 GENERIC MAP ( C_FAMILY => "artix7", C_XDEVICEFAMILY => "artix7", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 0, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 1, C_INIT_FILE_NAME => "title1.mif", C_INIT_FILE => "title1.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 0, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 12, C_READ_WIDTH_A => 12, C_WRITE_DEPTH_A => 13104, C_READ_DEPTH_A => 13104, C_ADDRA_WIDTH => 14, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 12, C_READ_WIDTH_B => 12, C_WRITE_DEPTH_B => 13104, C_READ_DEPTH_B => 13104, C_ADDRB_WIDTH => 14, C_HAS_MEM_OUTPUT_REGS_A => 1, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_USE_URAM => 0, C_EN_RDADDRA_CHG => 0, C_EN_RDADDRB_CHG => 0, C_EN_DEEPSLEEP_PIN => 0, C_EN_SHUTDOWN_PIN => 0, C_EN_SAFETY_CKT => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "4", C_COUNT_18K_BRAM => "2", C_EST_POWER_SUMMARY => "Estimated Power for IP : 6.153268 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => '0', regcea => '0', wea => wea, addra => addra, dina => dina, douta => douta, clkb => '0', rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)), dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)), injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', deepsleep => '0', shutdown => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END title1_arch;
-- Automatically generated VHDL-93 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.MATH_REAL.ALL; use std.textio.all; use work.all; use work.packetprocessordf_types.all; entity packetprocessordf_cnt is port(s : in packetprocessordf_types.counterstate; x : in std_logic_vector(28 downto 0); result : out packetprocessordf_types.counterstate); end; architecture structural of packetprocessordf_cnt is signal case_alt : packetprocessordf_types.counterstate; signal case_alt_0 : packetprocessordf_types.counterstate; signal case_alt_1 : packetprocessordf_types.counterstate; signal app_arg : unsigned(10 downto 0); signal app_arg_0 : unsigned(10 downto 0); signal app_arg_1 : unsigned(3 downto 0); signal app_arg_2 : unsigned(15 downto 0); signal app_arg_3 : std_logic_vector(8 downto 0); signal app_arg_4 : boolean; signal app_arg_5 : packetprocessordf_types.array_of_tup3(0 to 3); signal app_arg_6 : unsigned(1 downto 0); signal app_arg_7 : boolean; signal case_alt_2 : packetprocessordf_types.counterstate; signal case_alt_3 : packetprocessordf_types.counterstate; signal case_alt_4 : unsigned(10 downto 0); signal case_alt_5 : unsigned(10 downto 0); signal case_alt_6 : unsigned(3 downto 0); signal case_alt_7 : unsigned(15 downto 0); signal case_alt_8 : std_logic_vector(8 downto 0); signal case_alt_9 : boolean; signal result_0 : packetprocessordf_types.array_of_tup3(0 to 3); signal app_arg_8 : unsigned(1 downto 0); signal ds : unsigned(10 downto 0); signal ds1 : unsigned(10 downto 0); signal ds2 : unsigned(3 downto 0); signal ds3 : unsigned(15 downto 0); signal ds4 : std_logic_vector(8 downto 0); signal ds5 : boolean; signal ds8 : boolean; signal app_arg_9 : boolean; signal ds6 : packetprocessordf_types.array_of_tup3(0 to 3); signal ds7 : unsigned(1 downto 0); signal case_alt_10 : unsigned(10 downto 0); signal case_alt_11 : unsigned(10 downto 0); signal case_alt_12 : unsigned(3 downto 0); signal case_alt_13 : unsigned(15 downto 0); signal case_alt_14 : unsigned(15 downto 0); signal case_scrut : boolean; signal case_alt_15 : std_logic_vector(8 downto 0); signal case_alt_16 : boolean; signal app_arg_10 : signed(63 downto 0); signal app_arg_11 : packetprocessordf_types.tup3; signal app_arg_12 : std_logic_vector(10 downto 0); signal app_arg_13 : std_logic_vector(3 downto 0); signal app_arg_14 : std_logic_vector(15 downto 0); signal app_arg_15 : std_logic_vector(15 downto 0); signal result_1 : boolean; signal case_scrut_0 : packetprocessordf_types.tup3; signal wild3 : signed(63 downto 0); signal d : unsigned(7 downto 0); signal pos : unsigned(10 downto 0); signal mask : unsigned(7 downto 0); signal val : unsigned(7 downto 0); signal app_arg_16 : std_logic_vector(15 downto 0); signal app_arg_17 : std_logic_vector(7 downto 0); signal app_arg_18 : std_logic_vector(15 downto 0); signal case_scrut_1 : boolean; signal case_alt_17 : boolean; signal cnt_jout : boolean; signal wild3_app_arg : signed(63 downto 0); signal app_arg_19 : unsigned(15 downto 0); signal case_scrut_2 : boolean; signal a : unsigned(10 downto 0); signal app_arg_20 : unsigned(7 downto 0); signal p : unsigned(7 downto 0); signal m : unsigned(7 downto 0); begin case_alt <= (counterstate_sel0 => app_arg ,counterstate_sel1 => app_arg_0 ,counterstate_sel2 => app_arg_1 ,counterstate_sel3 => app_arg_2 ,counterstate_sel4 => app_arg_3 ,counterstate_sel5 => app_arg_4 ,counterstate_sel6 => app_arg_5 ,counterstate_sel7 => app_arg_6 ,counterstate_sel8 => app_arg_7); case_alt_0 <= case_alt_2; case_alt_1 <= case_alt_3; app_arg <= case_alt_4; app_arg_0 <= case_alt_5; app_arg_1 <= case_alt_6; app_arg_2 <= case_alt_7; app_arg_3 <= case_alt_8; app_arg_4 <= app_arg_9; app_arg_5 <= ds6; app_arg_6 <= ds7; app_arg_7 <= case_alt_9; case_alt_2 <= (counterstate_sel0 => ds ,counterstate_sel1 => ds1 ,counterstate_sel2 => ds2 ,counterstate_sel3 => ds3 ,counterstate_sel4 => ds4 ,counterstate_sel5 => ds5 ,counterstate_sel6 => result_0 ,counterstate_sel7 => app_arg_8 ,counterstate_sel8 => ds8); case_alt_3 <= (counterstate_sel0 => ds ,counterstate_sel1 => ds1 ,counterstate_sel2 => ds2 ,counterstate_sel3 => ds3 ,counterstate_sel4 => ds4 ,counterstate_sel5 => app_arg_9 ,counterstate_sel6 => ds6 ,counterstate_sel7 => ds7 ,counterstate_sel8 => ds8); case_alt_4 <= ds + to_unsigned(1,11); with (ds) select case_alt_5 <= case_alt_11 when "00000000100", case_alt_10 when others; with (ds) select case_alt_6 <= case_alt_12 when "00000000000", ds2 when others; with (ds) select case_alt_7 <= case_alt_13 when "00000000010", case_alt_14 when "00000000011", ds3 when others; case_alt_8 <= case_alt_15 when case_scrut else std_logic_vector'("0" & "00000000"); case_alt_9 <= true when ds8 else case_alt_16; -- replace begin replacevec : block signal vec_index : integer range 0 to 4-1; begin vec_index <= to_integer(app_arg_10) -- pragma translate_off mod 4 -- pragma translate_on ; process(vec_index,ds6,app_arg_11) variable ivec : packetprocessordf_types.array_of_tup3(0 to 3); begin ivec := ds6; ivec(vec_index) := app_arg_11; result_0 <= ivec; end process; end block; -- replace end app_arg_8 <= ds7 + to_unsigned(1,2); ds <= s.counterstate_sel0; ds1 <= s.counterstate_sel1; ds2 <= s.counterstate_sel2; ds3 <= s.counterstate_sel3; ds4 <= s.counterstate_sel4; ds5 <= s.counterstate_sel5; ds8 <= s.counterstate_sel8; app_arg_9 <= ds1 = to_unsigned(0,11); ds6 <= s.counterstate_sel6; ds7 <= s.counterstate_sel7; case_alt_10 <= ds1 - to_unsigned(1,11); case_alt_11 <= unsigned(app_arg_12); case_alt_12 <= unsigned(app_arg_13); case_alt_13 <= unsigned(app_arg_14); case_alt_14 <= unsigned(app_arg_15); case_scrut <= ds1 /= to_unsigned(0,11); case_alt_15 <= std_logic_vector'("1" & std_logic_vector(d)); case_alt_16 <= result_1; app_arg_10 <= wild3; app_arg_11 <= (tup3_sel0 => pos ,tup3_sel1 => mask ,tup3_sel2 => val); -- slice begin app_arg_12 <= app_arg_16(10 downto 0); -- slice end -- slice begin app_arg_13 <= app_arg_17(3 downto 0); -- slice end -- setSlice begin setslice : process(app_arg_18,app_arg_17) variable ivec_0 : std_logic_vector(15 downto 0); begin ivec_0 := app_arg_18; ivec_0(15 downto 8) := app_arg_17; app_arg_14 <= ivec_0; end process; -- setSlice end -- setSlice begin setslice_0 : process(app_arg_18,app_arg_17) variable ivec_1 : std_logic_vector(15 downto 0); begin ivec_1 := app_arg_18; ivec_1(7 downto 0) := app_arg_17; app_arg_15 <= ivec_1; end process; -- setSlice end result_1 <= cnt_jout when case_scrut_1 else case_alt_17; -- index begin indexvec : block signal vec_index_0 : integer range 0 to 4-1; begin vec_index_0 <= to_integer(to_signed(0,64)) -- pragma translate_off mod 4 -- pragma translate_on ; case_scrut_0 <= ds6(vec_index_0); end block; -- index end wild3 <= wild3_app_arg; d <= unsigned(x(26 downto 19)); pos <= unsigned(x(26 downto 16)); mask <= unsigned(x(15 downto 8)); val <= unsigned(x(7 downto 0)); app_arg_16 <= std_logic_vector(app_arg_19); app_arg_17 <= std_logic_vector(d); app_arg_18 <= std_logic_vector(ds3); case_scrut_1 <= ds /= a; case_alt_17 <= true when case_scrut_2 else cnt_jout; packetprocessordf_cnt_j_cnt_jout : entity packetprocessordf_cnt_j port map (result => cnt_jout ,pts => ds6 ,pts_0 => ds ,pts_1 => d); wild3_app_arg <= signed(std_logic_vector(resize(ds7,64))); app_arg_19 <= ds3 - to_unsigned(5,16); case_scrut_2 <= app_arg_20 = p; a <= case_scrut_0.tup3_sel0; app_arg_20 <= d and m; p <= case_scrut_0.tup3_sel2; m <= case_scrut_0.tup3_sel1; with (x(28 downto 27)) select result <= case_alt when "00", case_alt_0 when "01", (counterstate_sel0 => to_unsigned(0,11) ,counterstate_sel1 => to_unsigned(2047,11) ,counterstate_sel2 => to_unsigned(0,4) ,counterstate_sel3 => to_unsigned(0,16) ,counterstate_sel4 => std_logic_vector'("0" & "00000000") ,counterstate_sel5 => false ,counterstate_sel6 => packetprocessordf_types.array_of_tup3'((tup3_sel0 => to_unsigned(2047,11) ,tup3_sel1 => to_unsigned(0,8) ,tup3_sel2 => to_unsigned(0,8)) ,(tup3_sel0 => to_unsigned(2047,11) ,tup3_sel1 => to_unsigned(0,8) ,tup3_sel2 => to_unsigned(0,8)) ,(tup3_sel0 => to_unsigned(2047,11) ,tup3_sel1 => to_unsigned(0,8) ,tup3_sel2 => to_unsigned(0,8)) ,(tup3_sel0 => to_unsigned(2047,11) ,tup3_sel1 => to_unsigned(0,8) ,tup3_sel2 => to_unsigned(0,8))) ,counterstate_sel7 => to_unsigned(0,2) ,counterstate_sel8 => false) when "10", case_alt_1 when others; end;
-- Automatically generated VHDL-93 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.MATH_REAL.ALL; use std.textio.all; use work.all; use work.packetprocessordf_types.all; entity packetprocessordf_cnt is port(s : in packetprocessordf_types.counterstate; x : in std_logic_vector(28 downto 0); result : out packetprocessordf_types.counterstate); end; architecture structural of packetprocessordf_cnt is signal case_alt : packetprocessordf_types.counterstate; signal case_alt_0 : packetprocessordf_types.counterstate; signal case_alt_1 : packetprocessordf_types.counterstate; signal app_arg : unsigned(10 downto 0); signal app_arg_0 : unsigned(10 downto 0); signal app_arg_1 : unsigned(3 downto 0); signal app_arg_2 : unsigned(15 downto 0); signal app_arg_3 : std_logic_vector(8 downto 0); signal app_arg_4 : boolean; signal app_arg_5 : packetprocessordf_types.array_of_tup3(0 to 3); signal app_arg_6 : unsigned(1 downto 0); signal app_arg_7 : boolean; signal case_alt_2 : packetprocessordf_types.counterstate; signal case_alt_3 : packetprocessordf_types.counterstate; signal case_alt_4 : unsigned(10 downto 0); signal case_alt_5 : unsigned(10 downto 0); signal case_alt_6 : unsigned(3 downto 0); signal case_alt_7 : unsigned(15 downto 0); signal case_alt_8 : std_logic_vector(8 downto 0); signal case_alt_9 : boolean; signal result_0 : packetprocessordf_types.array_of_tup3(0 to 3); signal app_arg_8 : unsigned(1 downto 0); signal ds : unsigned(10 downto 0); signal ds1 : unsigned(10 downto 0); signal ds2 : unsigned(3 downto 0); signal ds3 : unsigned(15 downto 0); signal ds4 : std_logic_vector(8 downto 0); signal ds5 : boolean; signal ds8 : boolean; signal app_arg_9 : boolean; signal ds6 : packetprocessordf_types.array_of_tup3(0 to 3); signal ds7 : unsigned(1 downto 0); signal case_alt_10 : unsigned(10 downto 0); signal case_alt_11 : unsigned(10 downto 0); signal case_alt_12 : unsigned(3 downto 0); signal case_alt_13 : unsigned(15 downto 0); signal case_alt_14 : unsigned(15 downto 0); signal case_scrut : boolean; signal case_alt_15 : std_logic_vector(8 downto 0); signal case_alt_16 : boolean; signal app_arg_10 : signed(63 downto 0); signal app_arg_11 : packetprocessordf_types.tup3; signal app_arg_12 : std_logic_vector(10 downto 0); signal app_arg_13 : std_logic_vector(3 downto 0); signal app_arg_14 : std_logic_vector(15 downto 0); signal app_arg_15 : std_logic_vector(15 downto 0); signal result_1 : boolean; signal case_scrut_0 : packetprocessordf_types.tup3; signal wild3 : signed(63 downto 0); signal d : unsigned(7 downto 0); signal pos : unsigned(10 downto 0); signal mask : unsigned(7 downto 0); signal val : unsigned(7 downto 0); signal app_arg_16 : std_logic_vector(15 downto 0); signal app_arg_17 : std_logic_vector(7 downto 0); signal app_arg_18 : std_logic_vector(15 downto 0); signal case_scrut_1 : boolean; signal case_alt_17 : boolean; signal cnt_jout : boolean; signal wild3_app_arg : signed(63 downto 0); signal app_arg_19 : unsigned(15 downto 0); signal case_scrut_2 : boolean; signal a : unsigned(10 downto 0); signal app_arg_20 : unsigned(7 downto 0); signal p : unsigned(7 downto 0); signal m : unsigned(7 downto 0); begin case_alt <= (counterstate_sel0 => app_arg ,counterstate_sel1 => app_arg_0 ,counterstate_sel2 => app_arg_1 ,counterstate_sel3 => app_arg_2 ,counterstate_sel4 => app_arg_3 ,counterstate_sel5 => app_arg_4 ,counterstate_sel6 => app_arg_5 ,counterstate_sel7 => app_arg_6 ,counterstate_sel8 => app_arg_7); case_alt_0 <= case_alt_2; case_alt_1 <= case_alt_3; app_arg <= case_alt_4; app_arg_0 <= case_alt_5; app_arg_1 <= case_alt_6; app_arg_2 <= case_alt_7; app_arg_3 <= case_alt_8; app_arg_4 <= app_arg_9; app_arg_5 <= ds6; app_arg_6 <= ds7; app_arg_7 <= case_alt_9; case_alt_2 <= (counterstate_sel0 => ds ,counterstate_sel1 => ds1 ,counterstate_sel2 => ds2 ,counterstate_sel3 => ds3 ,counterstate_sel4 => ds4 ,counterstate_sel5 => ds5 ,counterstate_sel6 => result_0 ,counterstate_sel7 => app_arg_8 ,counterstate_sel8 => ds8); case_alt_3 <= (counterstate_sel0 => ds ,counterstate_sel1 => ds1 ,counterstate_sel2 => ds2 ,counterstate_sel3 => ds3 ,counterstate_sel4 => ds4 ,counterstate_sel5 => app_arg_9 ,counterstate_sel6 => ds6 ,counterstate_sel7 => ds7 ,counterstate_sel8 => ds8); case_alt_4 <= ds + to_unsigned(1,11); with (ds) select case_alt_5 <= case_alt_11 when "00000000100", case_alt_10 when others; with (ds) select case_alt_6 <= case_alt_12 when "00000000000", ds2 when others; with (ds) select case_alt_7 <= case_alt_13 when "00000000010", case_alt_14 when "00000000011", ds3 when others; case_alt_8 <= case_alt_15 when case_scrut else std_logic_vector'("0" & "00000000"); case_alt_9 <= true when ds8 else case_alt_16; -- replace begin replacevec : block signal vec_index : integer range 0 to 4-1; begin vec_index <= to_integer(app_arg_10) -- pragma translate_off mod 4 -- pragma translate_on ; process(vec_index,ds6,app_arg_11) variable ivec : packetprocessordf_types.array_of_tup3(0 to 3); begin ivec := ds6; ivec(vec_index) := app_arg_11; result_0 <= ivec; end process; end block; -- replace end app_arg_8 <= ds7 + to_unsigned(1,2); ds <= s.counterstate_sel0; ds1 <= s.counterstate_sel1; ds2 <= s.counterstate_sel2; ds3 <= s.counterstate_sel3; ds4 <= s.counterstate_sel4; ds5 <= s.counterstate_sel5; ds8 <= s.counterstate_sel8; app_arg_9 <= ds1 = to_unsigned(0,11); ds6 <= s.counterstate_sel6; ds7 <= s.counterstate_sel7; case_alt_10 <= ds1 - to_unsigned(1,11); case_alt_11 <= unsigned(app_arg_12); case_alt_12 <= unsigned(app_arg_13); case_alt_13 <= unsigned(app_arg_14); case_alt_14 <= unsigned(app_arg_15); case_scrut <= ds1 /= to_unsigned(0,11); case_alt_15 <= std_logic_vector'("1" & std_logic_vector(d)); case_alt_16 <= result_1; app_arg_10 <= wild3; app_arg_11 <= (tup3_sel0 => pos ,tup3_sel1 => mask ,tup3_sel2 => val); -- slice begin app_arg_12 <= app_arg_16(10 downto 0); -- slice end -- slice begin app_arg_13 <= app_arg_17(3 downto 0); -- slice end -- setSlice begin setslice : process(app_arg_18,app_arg_17) variable ivec_0 : std_logic_vector(15 downto 0); begin ivec_0 := app_arg_18; ivec_0(15 downto 8) := app_arg_17; app_arg_14 <= ivec_0; end process; -- setSlice end -- setSlice begin setslice_0 : process(app_arg_18,app_arg_17) variable ivec_1 : std_logic_vector(15 downto 0); begin ivec_1 := app_arg_18; ivec_1(7 downto 0) := app_arg_17; app_arg_15 <= ivec_1; end process; -- setSlice end result_1 <= cnt_jout when case_scrut_1 else case_alt_17; -- index begin indexvec : block signal vec_index_0 : integer range 0 to 4-1; begin vec_index_0 <= to_integer(to_signed(0,64)) -- pragma translate_off mod 4 -- pragma translate_on ; case_scrut_0 <= ds6(vec_index_0); end block; -- index end wild3 <= wild3_app_arg; d <= unsigned(x(26 downto 19)); pos <= unsigned(x(26 downto 16)); mask <= unsigned(x(15 downto 8)); val <= unsigned(x(7 downto 0)); app_arg_16 <= std_logic_vector(app_arg_19); app_arg_17 <= std_logic_vector(d); app_arg_18 <= std_logic_vector(ds3); case_scrut_1 <= ds /= a; case_alt_17 <= true when case_scrut_2 else cnt_jout; packetprocessordf_cnt_j_cnt_jout : entity packetprocessordf_cnt_j port map (result => cnt_jout ,pts => ds6 ,pts_0 => ds ,pts_1 => d); wild3_app_arg <= signed(std_logic_vector(resize(ds7,64))); app_arg_19 <= ds3 - to_unsigned(5,16); case_scrut_2 <= app_arg_20 = p; a <= case_scrut_0.tup3_sel0; app_arg_20 <= d and m; p <= case_scrut_0.tup3_sel2; m <= case_scrut_0.tup3_sel1; with (x(28 downto 27)) select result <= case_alt when "00", case_alt_0 when "01", (counterstate_sel0 => to_unsigned(0,11) ,counterstate_sel1 => to_unsigned(2047,11) ,counterstate_sel2 => to_unsigned(0,4) ,counterstate_sel3 => to_unsigned(0,16) ,counterstate_sel4 => std_logic_vector'("0" & "00000000") ,counterstate_sel5 => false ,counterstate_sel6 => packetprocessordf_types.array_of_tup3'((tup3_sel0 => to_unsigned(2047,11) ,tup3_sel1 => to_unsigned(0,8) ,tup3_sel2 => to_unsigned(0,8)) ,(tup3_sel0 => to_unsigned(2047,11) ,tup3_sel1 => to_unsigned(0,8) ,tup3_sel2 => to_unsigned(0,8)) ,(tup3_sel0 => to_unsigned(2047,11) ,tup3_sel1 => to_unsigned(0,8) ,tup3_sel2 => to_unsigned(0,8)) ,(tup3_sel0 => to_unsigned(2047,11) ,tup3_sel1 => to_unsigned(0,8) ,tup3_sel2 => to_unsigned(0,8))) ,counterstate_sel7 => to_unsigned(0,2) ,counterstate_sel8 => false) when "10", case_alt_1 when others; end;
---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- -- Copyright 2017 International Business Machines -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions AND -- limitations under the License. -- ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- True dual port, single clocked register LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_misc.all; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; ENTITY mmio_register_2w2r IS GENERIC ( WIDTH : integer := 16; SIZE : integer := 512; ADDR_WIDTH : integer := 9 ); PORT ( clk : IN std_logic; we_a : IN std_logic; addr_a : IN std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0); din_a : IN std_logic_vector(WIDTH-1 DOWNTO 0); dout_a : OUT std_logic_vector(WIDTH-1 DOWNTO 0); we_b : IN std_logic; addr_b : IN std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0); din_b : IN std_logic_vector(WIDTH-1 DOWNTO 0); dout_b : OUT std_logic_vector(WIDTH-1 DOWNTO 0) ); END mmio_register_2w2r; ARCHITECTURE mmio_register_2w2r OF mmio_register_2w2r IS TYPE ram_t IS ARRAY (SIZE-1 DOWNTO 0) OF std_logic_vector(WIDTH-1 DOWNTO 0); SHARED VARIABLE ram_v : ram_t; BEGIN mmio_register_2w2r_b: PROCESS (clk) BEGIN -- PROCESS mmio_register IF (rising_edge(clk)) THEN IF (we_b = '1') THEN ram_v(to_integer(unsigned(addr_b))) := din_b; END IF; dout_b <= ram_v(to_integer(unsigned(addr_b))); END IF; END PROCESS mmio_register_2w2r_b; mmio_register_2w2r_a: PROCESS (clk) BEGIN -- PROCESS mmio_register IF (rising_edge(clk)) THEN IF (we_a = '1') THEN ram_v(to_integer(unsigned(addr_a))) := din_a; END IF; dout_a <= ram_v(to_integer(unsigned(addr_a))); END IF; END PROCESS mmio_register_2w2r_a; END ARCHITECTURE; -- Single write / dual read port, single clocked register LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_misc.all; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; ENTITY mmio_register_1w2r IS GENERIC ( WIDTH : integer := 16; SIZE : integer := 512; ADDR_WIDTH : integer := 9 ); PORT ( clk : IN std_logic; we_a : IN std_logic; addr_a : IN std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0); din_a : IN std_logic_vector(WIDTH-1 DOWNTO 0); dout_a : OUT std_logic_vector(WIDTH-1 DOWNTO 0); addr_b : IN std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0); dout_b : OUT std_logic_vector(WIDTH-1 DOWNTO 0) ); END mmio_register_1w2r; ARCHITECTURE mmio_register_1w2r OF mmio_register_1w2r IS TYPE mem_t IS ARRAY (SIZE DOWNTO 0) OF std_logic_vector(WIDTH-1 DOWNTO 0); SIGNAL mem : mem_t; BEGIN mmio_register_1w2r: PROCESS (clk) BEGIN -- PROCESS mmio_register IF (rising_edge(clk)) THEN IF (we_a = '1') THEN mem(to_integer(unsigned(addr_a))) <= din_a; END IF; dout_a <= mem(to_integer(unsigned(addr_a))); dout_b <= mem(to_integer(unsigned(addr_b))); END IF; END PROCESS mmio_register_1w2r; END ARCHITECTURE; -- Single port register LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_misc.all; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; ENTITY mmio_register_1w1r IS GENERIC ( WIDTH : integer := 16; SIZE : integer := 512; ADDR_WIDTH : integer := 9 ); PORT ( clk : IN std_logic; we : IN std_logic; addr : IN std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0); din : IN std_logic_vector(WIDTH-1 DOWNTO 0); dout : OUT std_logic_vector(WIDTH-1 DOWNTO 0) ); END mmio_register_1w1r; ARCHITECTURE mmio_register_1w1r OF mmio_register_1w1r IS TYPE mem_t IS ARRAY (SIZE DOWNTO 0) OF std_logic_vector(WIDTH-1 DOWNTO 0); SIGNAL mem : mem_t; BEGIN mmio_register_1w1r: PROCESS (clk) BEGIN -- PROCESS mmio_register IF (rising_edge(clk)) THEN IF (we = '1') THEN mem(to_integer(unsigned(addr))) <= din; END IF; dout <= mem(to_integer(unsigned(addr))); END IF; END PROCESS mmio_register_1w1r; END ARCHITECTURE;
ENTITY test1 IS PORT ( i : IN integer); END ENTITY test1; ENTITY test IS PORT ( o : OUT integer); END ENTITY test; ARCHITECTURE rtl OF test IS BEGIN test1_1 : ENTITY work.test1 PORT MAP ( i => o); END ARCHITECTURE rtl;
ENTITY test1 IS PORT ( i : IN integer); END ENTITY test1; ENTITY test IS PORT ( o : OUT integer); END ENTITY test; ARCHITECTURE rtl OF test IS BEGIN test1_1 : ENTITY work.test1 PORT MAP ( i => o); END ARCHITECTURE rtl;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 02/07/2017 02:26:58 PM -- Design Name: -- Module Name: blur - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library work; use work.filter_lib.all; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity sobel_filter is port ( vid_i : in rgb_interface_t; vid_o : out rgb_interface_t; x_position : in std_logic_vector(15 downto 0); threshold : in std_logic_vector(7 downto 0); sensitivity : in std_logic_vector(3 downto 0); invert : in std_logic; split_line : in std_logic_vector(15 downto 0); rotoscope : in std_logic; PIXEL_CLK : in std_logic ); end sobel_filter; architecture Behavioral of sobel_filter is -- We need to convert the image to grayscale before processing it. signal pixel_in : pixel_t; -- Size of the filter constant FILTER_WIDTH : natural := 3; constant FILTER_HEIGHT : natural := 3; -- Output of the linebuffer / Input to the filters signal window : pixel2d_t(FILTER_WIDTH - 1 downto 0, FILTER_HEIGHT - 1 downto 0); -- Kernels for our filters constant sobel_x_kernel : kernel_matrix_t(FILTER_WIDTH - 1 downto 0, FILTER_HEIGHT - 1 downto 0) := ( (-1, 0, 1), (-2, 0, 2), (-1, 0, 1) ); constant sobel_y_kernel : kernel_matrix_t(FILTER_WIDTH - 1 downto 0, FILTER_HEIGHT - 1 downto 0) := ( (-1,-2,-1), ( 0, 0, 0), ( 1, 2, 1) ); -- Results of the two filter kernels signal sobel_x, sobel_y : signed(21 downto 0) := (others => '0'); -- Post-filter computations and results (thresholding, truncation, saturation, inversion, etc.) signal sobel_mag, sobel_shift : signed(21 downto 0); signal sobel_trunc, sobel_sat, sobel_inv : std_logic_vector(7 downto 0); signal roto_rgb, roto_combined, rgb_buf, rgb_buf_reg : std_logic_vector(23 downto 0); -- Buffered output signal vid_buf, vid_buf_reg, vid_out : rgb_interface_t; begin -- Convert input to grayscale pixel_in <= std_logic_vector( resize(unsigned( vid_i.RGB(23 downto 16) ), 10) + resize(unsigned( vid_i.RGB(15 downto 8) ), 10) + resize(unsigned( vid_i.RGB( 7 downto 0) ), 10) ); -- Parameterizable pixel buffer pixel_buf: entity work.pixel_buffer(Behavioral) generic map ( WIDTH => FILTER_WIDTH, HEIGHT => FILTER_HEIGHT, LINE_LENGTH => 2048 ) port map ( -- Clock CLK => PIXEL_CLK, -- Inputs data_in => pixel_in, vde_in => vid_i.vde, hs_in => vid_i.hs, vs_in => vid_i.vs, -- Outputs data_out => window, vde_out => vid_buf.vde, hs_out => vid_buf.hs, vs_out => vid_buf.vs ); vid_buf.rgb <= vid_i.rgb; -- Filter kernels sobel_x_filter : entity work.filter_kernel(Combinational) generic map ( WIDTH => FILTER_WIDTH, HEIGHT => FILTER_HEIGHT, kernel => sobel_x_kernel ) port map ( data_in => window, data_out => sobel_x ); sobel_y_filter : entity work.filter_kernel(Combinational) generic map ( WIDTH => FILTER_WIDTH, HEIGHT => FILTER_HEIGHT, kernel => sobel_y_kernel ) port map ( data_in => window, data_out => sobel_y ); -- Process the outputs of the filters -- Approximate magnitude sobel_mag <= abs(sobel_x) + abs(sobel_y); -- Move the radix point sobel_shift <= sobel_mag srl to_integer(unsigned(sensitivity)); -- Truncate sobel_trunc <= std_logic_vector(sobel_shift(7 downto 0)); -- Threshold and Saturate sobel_sat <= (others=>'0') when unsigned(sobel_shift) < unsigned(threshold) else (others=>'1') when unsigned(sobel_shift) > 255 else sobel_trunc; -- Invert sobel_inv <= sobel_sat when invert = '0' else not(sobel_sat); -- Rotoscoping Logic -- Give the color a nice "palettized" look roto_rgb <= vid_i.RGB(23 downto 20) & vid_i.RGB(23 downto 20) -- R & vid_i.RGB(15 downto 12) & vid_i.RGB(15 downto 12) -- G & vid_i.RGB(7 downto 4) & vid_i.RGB(7 downto 4); -- B roto_combined <= (sobel_inv & sobel_inv & sobel_inv) when unsigned(sobel_shift) > 255 else roto_rgb; -- Select Rotoscope rgb_buf <= roto_combined when (rotoscope = '1') else (sobel_inv & sobel_inv & sobel_inv); -- Buffer stage process(PIXEL_CLK) begin if (rising_edge(PIXEL_CLK)) then -- Buffer stage rgb_buf_reg <= rgb_buf; vid_buf_reg <= vid_buf; -- Do splitscreen and buffer the output if (unsigned(x_position) < unsigned(split_line)) then vid_out.rgb <= rgb_buf_reg; else vid_out.rgb <= vid_buf_reg.rgb; end if; vid_out.vde <= vid_buf_reg.vde; vid_out.hs <= vid_buf_reg.hs; vid_out.vs <= vid_buf_reg.vs; end if; end process; -- Output vid_o <= vid_out; end Behavioral;
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY increment IS GENERIC ( length : integer ); PORT ( input : IN std_logic_vector(length-1 downto 0); output : OUT std_logic_vector(length-1 downto 0); overflow : OUT std_logic ); END increment; ARCHITECTURE behavior OF increment IS COMPONENT halfAdder PORT ( in1 : IN std_logic; in2 : IN std_logic; res : OUT std_logic; carry : OUT std_logic ); END COMPONENT; SIGNAL carry : std_logic_vector(length downto 0); BEGIN carry(0) <= '1'; gen: FOR X IN 0 TO length-1 GENERATE addx : halfAdder PORT MAP (input(X), carry(X), output(X), carry(X+1)); END GENERATE gen; overflow <= carry(length); END behavior;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity tb_dac is end tb_dac; architecture tb of tb_dac is signal clk, reset : std_logic := '0'; signal dac_in : signed(11 downto 0) := (others => '0'); signal dac_out_1 : std_logic; signal dac_out_2 : std_logic; signal vc_1 : real := 0.0; signal vc_2 : real := 0.0; signal diff : real := 0.0; constant R : real := 2200.0; constant C : real := 0.000000022; begin clk <= not clk after 10 ns; -- 50 MHz reset <= '1', '0' after 100 ns; dac1: entity work.sigma_delta_dac generic map (12, 0) port map ( clock => clk, reset => reset, dac_in => dac_in, dac_out => dac_out_1 ); dac2: entity work.sigma_delta_dac generic map (12, 1) port map ( clock => clk, reset => reset, dac_in => dac_in, dac_out => dac_out_2 ); test:process begin dac_in <= X"800"; wait for 1000 us; dac_in <= X"A00"; wait for 1000 us; dac_in <= X"C00"; wait for 1000 us; dac_in <= X"E00"; wait for 1000 us; dac_in <= X"000"; wait for 1000 us; dac_in <= X"200"; wait for 1000 us; dac_in <= X"400"; wait for 1000 us; dac_in <= X"600"; wait for 1000 us; dac_in <= X"7FF"; wait for 1000 us; -- dac_in <= X"002"; -- wait for 2000 us; -- dac_in <= X"7FF"; -- wait for 500 us; -- dac_in <= X"800"; -- wait for 500 us; for i in 0 to 15 loop dac_in <= to_signed(i * 16#111#, 12); wait for 10 us; -- 10 kHz end loop; for i in 0 to 15 loop dac_in <= to_signed(i * 16#111#, 12); wait for 20 us; -- 10 kHz end loop; -- now generate a 2 kHz wave (sample rate = 500 kHz, 250 clocks / sample, 100 samples per sine wave) for i in 0 to 400 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 5 us; end loop; -- now generate a 5 kHz wave (sample rate = 500 kHz, 100 clocks / sample, 100 samples per sine wave) for i in 0 to 1000 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 2 us; end loop; -- now generate a 10 kHz wave (sample rate = 500 kHz, 50 clocks / sample, 100 samples per sine wave) for i in 0 to 2000 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 1 us; end loop; dac_in <= X"7FF"; wait; end process; filter: process(clk) variable v_dac : real; variable i_r : real; variable q_c : real; begin if rising_edge(clk) then if dac_out_1='0' then v_dac := -1.2; else v_dac := 1.2; end if; i_r := (v_dac - vc_1) / R; q_c := i_r * 20.0e-9; -- 20 ns; vc_1 <= vc_1 + (q_c / C); ------- if dac_out_2='0' then v_dac := -1.0; else v_dac := 1.0; end if; i_r := (v_dac - vc_2) / R; q_c := i_r * 20.0e-9; vc_2 <= vc_2 + (q_c / C); end if; end process; diff <= vc_2 - vc_1; end tb;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity tb_dac is end tb_dac; architecture tb of tb_dac is signal clk, reset : std_logic := '0'; signal dac_in : signed(11 downto 0) := (others => '0'); signal dac_out_1 : std_logic; signal dac_out_2 : std_logic; signal vc_1 : real := 0.0; signal vc_2 : real := 0.0; signal diff : real := 0.0; constant R : real := 2200.0; constant C : real := 0.000000022; begin clk <= not clk after 10 ns; -- 50 MHz reset <= '1', '0' after 100 ns; dac1: entity work.sigma_delta_dac generic map (12, 0) port map ( clock => clk, reset => reset, dac_in => dac_in, dac_out => dac_out_1 ); dac2: entity work.sigma_delta_dac generic map (12, 1) port map ( clock => clk, reset => reset, dac_in => dac_in, dac_out => dac_out_2 ); test:process begin dac_in <= X"800"; wait for 1000 us; dac_in <= X"A00"; wait for 1000 us; dac_in <= X"C00"; wait for 1000 us; dac_in <= X"E00"; wait for 1000 us; dac_in <= X"000"; wait for 1000 us; dac_in <= X"200"; wait for 1000 us; dac_in <= X"400"; wait for 1000 us; dac_in <= X"600"; wait for 1000 us; dac_in <= X"7FF"; wait for 1000 us; -- dac_in <= X"002"; -- wait for 2000 us; -- dac_in <= X"7FF"; -- wait for 500 us; -- dac_in <= X"800"; -- wait for 500 us; for i in 0 to 15 loop dac_in <= to_signed(i * 16#111#, 12); wait for 10 us; -- 10 kHz end loop; for i in 0 to 15 loop dac_in <= to_signed(i * 16#111#, 12); wait for 20 us; -- 10 kHz end loop; -- now generate a 2 kHz wave (sample rate = 500 kHz, 250 clocks / sample, 100 samples per sine wave) for i in 0 to 400 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 5 us; end loop; -- now generate a 5 kHz wave (sample rate = 500 kHz, 100 clocks / sample, 100 samples per sine wave) for i in 0 to 1000 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 2 us; end loop; -- now generate a 10 kHz wave (sample rate = 500 kHz, 50 clocks / sample, 100 samples per sine wave) for i in 0 to 2000 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 1 us; end loop; dac_in <= X"7FF"; wait; end process; filter: process(clk) variable v_dac : real; variable i_r : real; variable q_c : real; begin if rising_edge(clk) then if dac_out_1='0' then v_dac := -1.2; else v_dac := 1.2; end if; i_r := (v_dac - vc_1) / R; q_c := i_r * 20.0e-9; -- 20 ns; vc_1 <= vc_1 + (q_c / C); ------- if dac_out_2='0' then v_dac := -1.0; else v_dac := 1.0; end if; i_r := (v_dac - vc_2) / R; q_c := i_r * 20.0e-9; vc_2 <= vc_2 + (q_c / C); end if; end process; diff <= vc_2 - vc_1; end tb;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity tb_dac is end tb_dac; architecture tb of tb_dac is signal clk, reset : std_logic := '0'; signal dac_in : signed(11 downto 0) := (others => '0'); signal dac_out_1 : std_logic; signal dac_out_2 : std_logic; signal vc_1 : real := 0.0; signal vc_2 : real := 0.0; signal diff : real := 0.0; constant R : real := 2200.0; constant C : real := 0.000000022; begin clk <= not clk after 10 ns; -- 50 MHz reset <= '1', '0' after 100 ns; dac1: entity work.sigma_delta_dac generic map (12, 0) port map ( clock => clk, reset => reset, dac_in => dac_in, dac_out => dac_out_1 ); dac2: entity work.sigma_delta_dac generic map (12, 1) port map ( clock => clk, reset => reset, dac_in => dac_in, dac_out => dac_out_2 ); test:process begin dac_in <= X"800"; wait for 1000 us; dac_in <= X"A00"; wait for 1000 us; dac_in <= X"C00"; wait for 1000 us; dac_in <= X"E00"; wait for 1000 us; dac_in <= X"000"; wait for 1000 us; dac_in <= X"200"; wait for 1000 us; dac_in <= X"400"; wait for 1000 us; dac_in <= X"600"; wait for 1000 us; dac_in <= X"7FF"; wait for 1000 us; -- dac_in <= X"002"; -- wait for 2000 us; -- dac_in <= X"7FF"; -- wait for 500 us; -- dac_in <= X"800"; -- wait for 500 us; for i in 0 to 15 loop dac_in <= to_signed(i * 16#111#, 12); wait for 10 us; -- 10 kHz end loop; for i in 0 to 15 loop dac_in <= to_signed(i * 16#111#, 12); wait for 20 us; -- 10 kHz end loop; -- now generate a 2 kHz wave (sample rate = 500 kHz, 250 clocks / sample, 100 samples per sine wave) for i in 0 to 400 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 5 us; end loop; -- now generate a 5 kHz wave (sample rate = 500 kHz, 100 clocks / sample, 100 samples per sine wave) for i in 0 to 1000 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 2 us; end loop; -- now generate a 10 kHz wave (sample rate = 500 kHz, 50 clocks / sample, 100 samples per sine wave) for i in 0 to 2000 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 1 us; end loop; dac_in <= X"7FF"; wait; end process; filter: process(clk) variable v_dac : real; variable i_r : real; variable q_c : real; begin if rising_edge(clk) then if dac_out_1='0' then v_dac := -1.2; else v_dac := 1.2; end if; i_r := (v_dac - vc_1) / R; q_c := i_r * 20.0e-9; -- 20 ns; vc_1 <= vc_1 + (q_c / C); ------- if dac_out_2='0' then v_dac := -1.0; else v_dac := 1.0; end if; i_r := (v_dac - vc_2) / R; q_c := i_r * 20.0e-9; vc_2 <= vc_2 + (q_c / C); end if; end process; diff <= vc_2 - vc_1; end tb;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity tb_dac is end tb_dac; architecture tb of tb_dac is signal clk, reset : std_logic := '0'; signal dac_in : signed(11 downto 0) := (others => '0'); signal dac_out_1 : std_logic; signal dac_out_2 : std_logic; signal vc_1 : real := 0.0; signal vc_2 : real := 0.0; signal diff : real := 0.0; constant R : real := 2200.0; constant C : real := 0.000000022; begin clk <= not clk after 10 ns; -- 50 MHz reset <= '1', '0' after 100 ns; dac1: entity work.sigma_delta_dac generic map (12, 0) port map ( clock => clk, reset => reset, dac_in => dac_in, dac_out => dac_out_1 ); dac2: entity work.sigma_delta_dac generic map (12, 1) port map ( clock => clk, reset => reset, dac_in => dac_in, dac_out => dac_out_2 ); test:process begin dac_in <= X"800"; wait for 1000 us; dac_in <= X"A00"; wait for 1000 us; dac_in <= X"C00"; wait for 1000 us; dac_in <= X"E00"; wait for 1000 us; dac_in <= X"000"; wait for 1000 us; dac_in <= X"200"; wait for 1000 us; dac_in <= X"400"; wait for 1000 us; dac_in <= X"600"; wait for 1000 us; dac_in <= X"7FF"; wait for 1000 us; -- dac_in <= X"002"; -- wait for 2000 us; -- dac_in <= X"7FF"; -- wait for 500 us; -- dac_in <= X"800"; -- wait for 500 us; for i in 0 to 15 loop dac_in <= to_signed(i * 16#111#, 12); wait for 10 us; -- 10 kHz end loop; for i in 0 to 15 loop dac_in <= to_signed(i * 16#111#, 12); wait for 20 us; -- 10 kHz end loop; -- now generate a 2 kHz wave (sample rate = 500 kHz, 250 clocks / sample, 100 samples per sine wave) for i in 0 to 400 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 5 us; end loop; -- now generate a 5 kHz wave (sample rate = 500 kHz, 100 clocks / sample, 100 samples per sine wave) for i in 0 to 1000 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 2 us; end loop; -- now generate a 10 kHz wave (sample rate = 500 kHz, 50 clocks / sample, 100 samples per sine wave) for i in 0 to 2000 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 1 us; end loop; dac_in <= X"7FF"; wait; end process; filter: process(clk) variable v_dac : real; variable i_r : real; variable q_c : real; begin if rising_edge(clk) then if dac_out_1='0' then v_dac := -1.2; else v_dac := 1.2; end if; i_r := (v_dac - vc_1) / R; q_c := i_r * 20.0e-9; -- 20 ns; vc_1 <= vc_1 + (q_c / C); ------- if dac_out_2='0' then v_dac := -1.0; else v_dac := 1.0; end if; i_r := (v_dac - vc_2) / R; q_c := i_r * 20.0e-9; vc_2 <= vc_2 + (q_c / C); end if; end process; diff <= vc_2 - vc_1; end tb;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity tb_dac is end tb_dac; architecture tb of tb_dac is signal clk, reset : std_logic := '0'; signal dac_in : signed(11 downto 0) := (others => '0'); signal dac_out_1 : std_logic; signal dac_out_2 : std_logic; signal vc_1 : real := 0.0; signal vc_2 : real := 0.0; signal diff : real := 0.0; constant R : real := 2200.0; constant C : real := 0.000000022; begin clk <= not clk after 10 ns; -- 50 MHz reset <= '1', '0' after 100 ns; dac1: entity work.sigma_delta_dac generic map (12, 0) port map ( clock => clk, reset => reset, dac_in => dac_in, dac_out => dac_out_1 ); dac2: entity work.sigma_delta_dac generic map (12, 1) port map ( clock => clk, reset => reset, dac_in => dac_in, dac_out => dac_out_2 ); test:process begin dac_in <= X"800"; wait for 1000 us; dac_in <= X"A00"; wait for 1000 us; dac_in <= X"C00"; wait for 1000 us; dac_in <= X"E00"; wait for 1000 us; dac_in <= X"000"; wait for 1000 us; dac_in <= X"200"; wait for 1000 us; dac_in <= X"400"; wait for 1000 us; dac_in <= X"600"; wait for 1000 us; dac_in <= X"7FF"; wait for 1000 us; -- dac_in <= X"002"; -- wait for 2000 us; -- dac_in <= X"7FF"; -- wait for 500 us; -- dac_in <= X"800"; -- wait for 500 us; for i in 0 to 15 loop dac_in <= to_signed(i * 16#111#, 12); wait for 10 us; -- 10 kHz end loop; for i in 0 to 15 loop dac_in <= to_signed(i * 16#111#, 12); wait for 20 us; -- 10 kHz end loop; -- now generate a 2 kHz wave (sample rate = 500 kHz, 250 clocks / sample, 100 samples per sine wave) for i in 0 to 400 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 5 us; end loop; -- now generate a 5 kHz wave (sample rate = 500 kHz, 100 clocks / sample, 100 samples per sine wave) for i in 0 to 1000 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 2 us; end loop; -- now generate a 10 kHz wave (sample rate = 500 kHz, 50 clocks / sample, 100 samples per sine wave) for i in 0 to 2000 loop dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12); wait for 1 us; end loop; dac_in <= X"7FF"; wait; end process; filter: process(clk) variable v_dac : real; variable i_r : real; variable q_c : real; begin if rising_edge(clk) then if dac_out_1='0' then v_dac := -1.2; else v_dac := 1.2; end if; i_r := (v_dac - vc_1) / R; q_c := i_r * 20.0e-9; -- 20 ns; vc_1 <= vc_1 + (q_c / C); ------- if dac_out_2='0' then v_dac := -1.0; else v_dac := 1.0; end if; i_r := (v_dac - vc_2) / R; q_c := i_r * 20.0e-9; vc_2 <= vc_2 + (q_c / C); end if; end process; diff <= vc_2 - vc_1; end tb;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21:36:59 04/04/2014 -- Design Name: -- Module Name: phase_acc - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity phase_acc is generic( sine_length_bits: integer := 10 ); port( x_out: out std_logic_vector(sine_length_bits - 1 downto 0); freq_mult: in std_logic_vector(9 downto 0); phase_in: in std_logic_vector(7 downto 0); clk: in std_logic ); end phase_acc; architecture Behavioral of phase_acc is signal big_ol_counter: unsigned(20 downto 0) := (others => '0'); begin process(clk) begin if(rising_edge(clk)) then big_ol_counter <= big_ol_counter + unsigned(freq_mult); end if; end process; x_out <= std_logic_vector(big_ol_counter(20 downto 11) + unsigned(phase_in & "00")); end Behavioral;
library verilog; use verilog.vl_types.all; entity F2DSS_GPIO is port( PRESETN : in vl_logic; PCLK : in vl_logic; PSEL : in vl_logic; PENABLE : in vl_logic; PWRITE : in vl_logic; PADDR : in vl_logic_vector(7 downto 0); PWDATA : in vl_logic_vector(31 downto 0); PRDATA : out vl_logic_vector(31 downto 0); INT : out vl_logic_vector(31 downto 0); GPIO_IN : in vl_logic_vector(31 downto 0); GPIO_OUT : out vl_logic_vector(31 downto 0); GPIO_OE : out vl_logic_vector(31 downto 0) ); end F2DSS_GPIO;
library verilog; use verilog.vl_types.all; entity F2DSS_GPIO is port( PRESETN : in vl_logic; PCLK : in vl_logic; PSEL : in vl_logic; PENABLE : in vl_logic; PWRITE : in vl_logic; PADDR : in vl_logic_vector(7 downto 0); PWDATA : in vl_logic_vector(31 downto 0); PRDATA : out vl_logic_vector(31 downto 0); INT : out vl_logic_vector(31 downto 0); GPIO_IN : in vl_logic_vector(31 downto 0); GPIO_OUT : out vl_logic_vector(31 downto 0); GPIO_OE : out vl_logic_vector(31 downto 0) ); end F2DSS_GPIO;
library verilog; use verilog.vl_types.all; entity F2DSS_GPIO is port( PRESETN : in vl_logic; PCLK : in vl_logic; PSEL : in vl_logic; PENABLE : in vl_logic; PWRITE : in vl_logic; PADDR : in vl_logic_vector(7 downto 0); PWDATA : in vl_logic_vector(31 downto 0); PRDATA : out vl_logic_vector(31 downto 0); INT : out vl_logic_vector(31 downto 0); GPIO_IN : in vl_logic_vector(31 downto 0); GPIO_OUT : out vl_logic_vector(31 downto 0); GPIO_OE : out vl_logic_vector(31 downto 0) ); end F2DSS_GPIO;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.utils.all; use work.constants_pkg.all; entity sys_call is generic ( REGISTER_SIZE : positive range 32 to 32; POWER_OPTIMIZED : boolean; INTERRUPT_VECTOR : std_logic_vector(31 downto 0); ENABLE_EXCEPTIONS : boolean; ENABLE_EXT_INTERRUPTS : boolean; NUM_EXT_INTERRUPTS : positive range 1 to 32; VCP_ENABLE : vcp_type; MULTIPLY_ENABLE : boolean; AUX_MEMORY_REGIONS : natural range 0 to 4; AMR0_ADDR_BASE : std_logic_vector(31 downto 0); AMR0_ADDR_LAST : std_logic_vector(31 downto 0); AMR0_READ_ONLY : boolean; UC_MEMORY_REGIONS : natural range 0 to 4; UMR0_ADDR_BASE : std_logic_vector(31 downto 0); UMR0_ADDR_LAST : std_logic_vector(31 downto 0); UMR0_READ_ONLY : boolean; HAS_ICACHE : boolean; HAS_DCACHE : boolean ); port ( clk : in std_logic; reset : in std_logic; global_interrupts : in std_logic_vector(NUM_EXT_INTERRUPTS-1 downto 0); core_idle : in std_logic; memory_idle : in std_logic; program_counter : in unsigned(REGISTER_SIZE-1 downto 0); to_syscall_valid : in std_logic; from_syscall_illegal : out std_logic; current_pc : in unsigned(REGISTER_SIZE-1 downto 0); instruction : in std_logic_vector(31 downto 0); rs1_data : in std_logic_vector(REGISTER_SIZE-1 downto 0); rs2_data : in std_logic_vector(REGISTER_SIZE-1 downto 0); from_syscall_ready : out std_logic; from_branch_misaligned : in std_logic; illegal_instruction : in std_logic; from_lsu_addr_misalign : in std_logic; from_lsu_address : in std_logic_vector(REGISTER_SIZE-1 downto 0); from_syscall_valid : out std_logic; from_syscall_data : out std_logic_vector(REGISTER_SIZE-1 downto 0); to_pc_correction_data : out unsigned(REGISTER_SIZE-1 downto 0); to_pc_correction_valid : out std_logic; from_pc_correction_ready : in std_logic; from_icache_control_ready : in std_logic; to_icache_control_valid : buffer std_logic; to_icache_control_command : out cache_control_command; from_dcache_control_ready : in std_logic; to_dcache_control_valid : buffer std_logic; to_dcache_control_command : out cache_control_command; to_cache_control_base : out std_logic_vector(REGISTER_SIZE-1 downto 0); to_cache_control_last : out std_logic_vector(REGISTER_SIZE-1 downto 0); amr_base_addrs : out std_logic_vector((imax(AUX_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0); amr_last_addrs : out std_logic_vector((imax(AUX_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0); umr_base_addrs : out std_logic_vector((imax(UC_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0); umr_last_addrs : out std_logic_vector((imax(UC_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0); pause_ifetch : out std_logic; timer_value : in std_logic_vector(63 downto 0); timer_interrupt : in std_logic; vcp_writeback_en : in std_logic; vcp_writeback_data : in std_logic_vector(REGISTER_SIZE-1 downto 0) ); end entity sys_call; architecture rtl of sys_call is signal fence_select : std_logic; signal fencei_select : std_logic; signal cache_select : std_logic; signal csr_select : std_logic; signal ebreak_select : std_logic; signal ecall_select : std_logic; signal mret_select : std_logic; -- CSR signals. These are initialized to zero so that if any bits are never -- assigned, they act like constants. signal mstatus : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0'); signal mscratch : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0'); signal mepc : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0'); signal mcause : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0'); signal mtval : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0'); signal mtime : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0'); signal mtimeh : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0'); signal meimask : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0'); signal meimask_full : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0'); signal meipend : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0'); signal mcache : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0'); signal misa : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0'); signal mtvec : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0'); alias csr_number : std_logic_vector(CSR_ADDRESS'length-1 downto 0) is instruction(CSR_ADDRESS'range); alias opcode : std_logic_vector(INSTR_OPCODE'length-1 downto 0) is instruction(INSTR_OPCODE'range); alias func3 : std_logic_vector(INSTR_FUNC3'length-1 downto 0) is instruction(INSTR_FUNC3'range); alias func7 : std_logic_vector(INSTR_FUNC7'length-1 downto 0) is instruction(INSTR_FUNC7'range); alias imm : std_logic_vector(CSR_ZIMM'length-1 downto 0) is instruction(CSR_ZIMM'range); alias rs1_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is instruction(REGISTER_RS1'range); alias rd_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is instruction(REGISTER_RD'range); alias mcause_exc_code : std_logic_vector is mcause(CSR_MCAUSE_CODE'range); alias bit_sel : std_logic_vector(REGISTER_SIZE-1 downto 0) is rs1_data; signal csr_readdata : std_logic_vector(REGISTER_SIZE-1 downto 0); signal csr_writedata : std_logic_vector(REGISTER_SIZE-1 downto 0); signal last_csr_writedata : std_logic_vector(REGISTER_SIZE-1 downto 0); signal was_mret : std_logic; signal was_illegal : std_logic; signal fence_pc_correction_valid : std_logic; signal next_fence_pc : unsigned(REGISTER_SIZE-1 downto 0); signal fence_pending : std_logic; signal interrupt_pending : std_logic; signal interrupt_pc_correction_valid : std_logic; --Uncached/Auxiliary memory region CSR signals. Will be assigned 0's if unused. type csr_vector is array (natural range <>) of std_logic_vector(REGISTER_SIZE-1 downto 0); signal mamr_base : csr_vector(3 downto 0); signal mamr_last : csr_vector(3 downto 0); signal mumr_base : csr_vector(3 downto 0); signal mumr_last : csr_vector(3 downto 0); signal amr_base_select : std_logic_vector(3 downto 0); signal amr_last_select : std_logic_vector(3 downto 0); signal umr_base_select : std_logic_vector(3 downto 0); signal umr_last_select : std_logic_vector(3 downto 0); signal amr_base_write : std_logic_vector(3 downto 0); signal amr_last_write : std_logic_vector(3 downto 0); signal umr_base_write : std_logic_vector(3 downto 0); signal umr_last_write : std_logic_vector(3 downto 0); begin --Decode instruction to select submodule. All paths must decode to exactly --one submodule. --ASSUMES only SYSTEM_OP | MISC_MEM_OP for opcode. process (opcode, func3, func7) is begin fence_select <= '0'; fencei_select <= '0'; cache_select <= '0'; csr_select <= '0'; ebreak_select <= '0'; ecall_select <= '0'; mret_select <= '0'; from_syscall_illegal <= '0'; if opcode(6) = SYSTEM_OP(6) then if ENABLE_EXCEPTIONS then case func3 is when PRIV_FUNC3 => if rs1_select /= REGISTER_ZERO or rd_select /= REGISTER_ZERO then from_syscall_illegal <= '1'; else case csr_number is when SYSTEM_ECALL => ecall_select <= '1'; when SYSTEM_EBREAK => ebreak_select <= '1'; when SYSTEM_MRET => mret_select <= '1'; when others => from_syscall_illegal <= '1'; end case; end if; when "100" => from_syscall_illegal <= '1'; when others => csr_select <= '1'; end case; else csr_select <= '1'; end if; else case func3 is when FENCE_FUNC3 => fence_select <= '1'; when REGION_FUNC3 => case func7 is when FENCE_I_FUNC7 | FENCE_RI_FUNC7 => fencei_select <= '1'; when FENCE_RD_FUNC7 => fence_select <= '1'; when CACHE_WRITEBACK_FUNC7 | CACHE_FLUSH_FUNC7 | CACHE_DISCARD_FUNC7 => if HAS_DCACHE then cache_select <= '1'; else fence_select <= '1'; end if; when others => if ENABLE_EXCEPTIONS then from_syscall_illegal <= '1'; else fence_select <= '1'; end if; end case; when others => if ENABLE_EXCEPTIONS then from_syscall_illegal <= '1'; else fence_select <= '1'; end if; end case; end if; end process; mtime <= std_logic_vector(timer_value(REGISTER_SIZE-1 downto 0)); mtimeh <= std_logic_vector(timer_value(timer_value'left downto timer_value'left-REGISTER_SIZE+1)); misa(misa'left downto misa'left-1) <= "01"; misa(23) <= '0' when VCP_ENABLE = DISABLED else '1'; misa(8) <= '1'; --I misa(12) <= '1' when MULTIPLY_ENABLE else '0'; with csr_number select csr_readdata <= misa when CSR_MISA, mscratch when CSR_MSCRATCH, mstatus when CSR_MSTATUS, mepc when CSR_MEPC, mcause when CSR_MCAUSE, mtval when CSR_MTVAL, meimask when CSR_MEIMASK, meipend when CSR_MEIPEND, mtime when CSR_MTIME, mtimeh when CSR_MTIMEH, mtime when CSR_UTIME, mtimeh when CSR_UTIMEH, mcache when CSR_MCACHE, mtvec when CSR_MTVEC, mamr_base(0) when CSR_MAMR0_BASE, mamr_base(1) when CSR_MAMR1_BASE, mamr_base(2) when CSR_MAMR2_BASE, mamr_base(3) when CSR_MAMR3_BASE, mamr_last(0) when CSR_MAMR0_LAST, mamr_last(1) when CSR_MAMR1_LAST, mamr_last(2) when CSR_MAMR2_LAST, mamr_last(3) when CSR_MAMR3_LAST, mumr_base(0) when CSR_MUMR0_BASE, mumr_base(1) when CSR_MUMR1_BASE, mumr_base(2) when CSR_MUMR2_BASE, mumr_base(3) when CSR_MUMR3_BASE, mumr_last(0) when CSR_MUMR0_LAST, mumr_last(1) when CSR_MUMR1_LAST, mumr_last(2) when CSR_MUMR2_LAST, mumr_last(3) when CSR_MUMR3_LAST, (others => '0') when others; with func3 select csr_writedata <= csr_readdata(31 downto 5) & (csr_readdata(CSR_ZIMM'length-1 downto 0) and (not imm)) when CSRRCI_FUNC3, csr_readdata(31 downto 5) & (csr_readdata(CSR_ZIMM'length-1 downto 0) or imm) when CSRRSI_FUNC3, std_logic_vector(resize(unsigned(imm), csr_writedata'length)) when CSRRWI_FUNC3, csr_readdata and (not rs1_data) when CSRRC_FUNC3, csr_readdata or rs1_data when CSRRS_FUNC3, rs1_data when others; --CSRRW_FUNC3, --Currently all syscall instructions execute without backpressure from_syscall_ready <= '1'; exceptions_gen : if ENABLE_EXCEPTIONS generate process(clk) begin if rising_edge(clk) then --Hold pc_correction causing signals until they have been processed if from_pc_correction_ready = '1' then was_mret <= '0'; was_illegal <= '0'; end if; if(illegal_instruction = '1' or from_lsu_addr_misalign = '1' or from_branch_misaligned = '1' or (to_syscall_valid = '1' and (ebreak_select = '1' or ecall_select = '1'))) then --Handle Illegal Instructions mstatus(CSR_MSTATUS_MIE) <= '0'; mstatus(CSR_MSTATUS_MPIE) <= mstatus(CSR_MSTATUS_MIE); mcause(mcause'left) <= '0'; if from_branch_misaligned = '1' then mcause(CSR_MCAUSE_CODE'range) <= CSR_MCAUSE_FETCH_MISALIGN; --according to the tests its legal to put zero in this register mtval <= std_logic_vector(to_unsigned(0, mtval'length)); elsif illegal_instruction = '1' then mcause(CSR_MCAUSE_CODE'range) <= CSR_MCAUSE_ILLEGAL; mtval <= instruction(mtval'range); elsif from_lsu_addr_misalign = '1' then mtval <= from_lsu_address; mcause(CSR_MCAUSE_CODE'range) <= CSR_MCAUSE_LOAD_MISALIGN; if instruction(5) = '1' then mcause(CSR_MCAUSE_CODE'range) <= CSR_MCAUSE_STORE_MISALIGN; end if; else if ebreak_select = '1' then mcause(CSR_MCAUSE_CODE'range) <= CSR_MCAUSE_EBREAK; else mcause(CSR_MCAUSE_CODE'range) <= CSR_MCAUSE_MECALL; end if; end if; mepc <= std_logic_vector(current_pc); was_illegal <= '1'; end if; if to_syscall_valid = '1' then if csr_select = '1' then --CSR Read/Write case csr_number is when CSR_MTVEC => -- Only direct exceptions are available; zero lower two bits mtvec(REGISTER_SIZE-1 downto 2) <= csr_writedata(REGISTER_SIZE-1 downto 2); when CSR_MSTATUS => -- Only 2 bits are writeable. mstatus(CSR_MSTATUS_MIE) <= csr_writedata(CSR_MSTATUS_MIE); mstatus(CSR_MSTATUS_MPIE) <= csr_writedata(CSR_MSTATUS_MPIE); when CSR_MEPC => mepc <= csr_writedata; when CSR_MCAUSE => --MCAUSE is WLRL so only legal values need to be supported mcause(mcause'left) <= csr_writedata(mcause'left); mcause(CSR_MCAUSE_CODE'range) <= csr_writedata(CSR_MCAUSE_CODE'range); when CSR_MTVAL => mtval <= csr_writedata; when CSR_MEIMASK => meimask_full <= csr_writedata; when CSR_MSCRATCH => mscratch <= csr_writedata; when others => null; end case; end if; if mret_select = '1' then --MRET mstatus(CSR_MSTATUS_MIE) <= mstatus(CSR_MSTATUS_MPIE); mstatus(CSR_MSTATUS_MPIE) <= '0'; was_mret <= '1'; end if; end if; if from_pc_correction_ready = '1' then interrupt_pc_correction_valid <= '0'; end if; if interrupt_pending = '1' and core_idle = '1' then interrupt_pc_correction_valid <= '1'; -- Latch in mepc the cycle before interrupt_pc_correction_valid goes high. -- When interrupt_pc_correction_valid goes high, the next_pc of the instruction fetch will -- be corrected to the interrupt reset vector. mepc <= std_logic_vector(program_counter); mstatus(CSR_MSTATUS_MIE) <= '0'; mstatus(CSR_MSTATUS_MPIE) <= '1'; mcause(mcause'left) <= '1'; mcause_exc_code <= CSR_MCAUSE_MEXT; if timer_interrupt = '1' then mcause_exc_code <= CSR_MCAUSE_MTIMER; end if; end if; if reset = '1' then was_mret <= '0'; was_illegal <= '0'; interrupt_pc_correction_valid <= '0'; mtvec(REGISTER_SIZE-1 downto 2) <= INTERRUPT_VECTOR(REGISTER_SIZE-1 downto 2); mstatus(CSR_MSTATUS_MIE) <= '0'; mstatus(CSR_MSTATUS_MPIE) <= '0'; mepc <= (others => '0'); mcause(mcause'left) <= '0'; mcause_exc_code <= (others => '0'); meimask_full <= (others => '0'); end if; mepc(1 downto 0) <= "00"; end if; end process; mtvec(1 downto 0) <= (others => '0'); mstatus(REGISTER_SIZE-1 downto CSR_MSTATUS_MPIE+1) <= (others => '0'); mstatus(CSR_MSTATUS_MPIE-1 downto CSR_MSTATUS_MIE+1) <= (others => '0'); mstatus(CSR_MSTATUS_MIE-1 downto 0) <= (others => '0'); mcause(mcause'left-1 downto CSR_MCAUSE_CODE'left+1) <= (others => '0'); end generate exceptions_gen; no_exceptions_gen : if not ENABLE_EXCEPTIONS generate mtvec <= (others => '0'); was_mret <= '0'; was_illegal <= '0'; interrupt_pc_correction_valid <= '0'; mstatus <= (others => '0'); mepc <= (others => '0'); mcause <= (others => '0'); end generate no_exceptions_gen; memory_region_registers_gen : for gregister in 3 downto 0 generate amr_gen : if (AUX_MEMORY_REGIONS > gregister) and ((UC_MEMORY_REGIONS /= 0) or HAS_ICACHE or HAS_DCACHE) generate read_only_amr_gen : if gregister = 0 and AMR0_READ_ONLY generate amr_base_select(gregister) <= '0'; amr_last_select(gregister) <= '0'; mamr_base(gregister) <= AMR0_ADDR_BASE; mamr_last(gregister) <= AMR0_ADDR_LAST; end generate read_only_amr_gen; writeable_amr_gen : if gregister /= 0 or (not AMR0_READ_ONLY) generate amr_base_select(gregister) <= '1' when (csr_number(csr_number'left downto 3) = CSR_MAMR0_BASE(CSR_MAMR0_BASE'left downto 3) and unsigned(csr_number(2 downto 0)) = to_unsigned(gregister, 3)) else '0'; amr_last_select(gregister) <= '1' when (csr_number(csr_number'left downto 3) = CSR_MAMR0_LAST(CSR_MAMR0_LAST'left downto 3) and unsigned(csr_number(2 downto 0)) = to_unsigned(gregister, 3)) else '0'; process(clk) begin if rising_edge(clk) then --Don't write the new AMR until the pipeline and memory interface are --flushed if from_pc_correction_ready = '1' then if (memory_idle = '1' and (from_icache_control_ready = '1' or to_icache_control_valid = '0') and (from_dcache_control_ready = '1' or to_dcache_control_valid = '0')) then if amr_base_write(gregister) = '1' then mamr_base(gregister) <= last_csr_writedata; end if; if amr_last_write(gregister) = '1' then mamr_last(gregister) <= last_csr_writedata; end if; end if; end if; if reset = '1' then if gregister = 0 then mamr_base(gregister) <= AMR0_ADDR_BASE; mamr_last(gregister) <= AMR0_ADDR_LAST; else mamr_base(gregister) <= (others => '1'); mamr_last(gregister) <= (others => '0'); end if; end if; end if; end process; end generate writeable_amr_gen; end generate amr_gen; no_amr_gen : if ((AUX_MEMORY_REGIONS <= gregister) or ((UC_MEMORY_REGIONS = 0) and (not HAS_ICACHE) and (not HAS_DCACHE))) generate amr_base_select(gregister) <= '0'; amr_last_select(gregister) <= '0'; mamr_base(gregister) <= (others => '0'); mamr_last(gregister) <= (others => '0'); end generate no_amr_gen; umr_gen : if (UC_MEMORY_REGIONS > gregister) and ((AUX_MEMORY_REGIONS /= 0) or HAS_ICACHE or HAS_DCACHE) generate read_only_umr_gen : if gregister = 0 and UMR0_READ_ONLY generate umr_base_select(gregister) <= '0'; umr_last_select(gregister) <= '0'; mumr_base(gregister) <= UMR0_ADDR_BASE; mumr_last(gregister) <= UMR0_ADDR_LAST; end generate read_only_umr_gen; writeable_umr_gen : if gregister /= 0 or (not UMR0_READ_ONLY) generate umr_base_select(gregister) <= '1' when (csr_number(csr_number'left downto 3) = CSR_MUMR0_BASE(CSR_MUMR0_BASE'left downto 3) and unsigned(csr_number(2 downto 0)) = to_unsigned(gregister, 3)) else '0'; umr_last_select(gregister) <= '1' when (csr_number(csr_number'left downto 3) = CSR_MUMR0_LAST(CSR_MUMR0_LAST'left downto 3) and unsigned(csr_number(2 downto 0)) = to_unsigned(gregister, 3)) else '0'; process(clk) begin if rising_edge(clk) then --Don't write the new UMR until the pipeline and memory interface are --flushed if from_pc_correction_ready = '1' then if (memory_idle = '1' and (from_icache_control_ready = '1' or to_icache_control_valid = '0') and (from_dcache_control_ready = '1' or to_dcache_control_valid = '0')) then if umr_base_write(gregister) = '1' then mumr_base(gregister) <= last_csr_writedata; end if; if umr_last_write(gregister) = '1' then mumr_last(gregister) <= last_csr_writedata; end if; end if; end if; if reset = '1' then if gregister = 0 then mumr_base(gregister) <= UMR0_ADDR_BASE; mumr_last(gregister) <= UMR0_ADDR_LAST; else mumr_base(gregister) <= (others => '1'); mumr_last(gregister) <= (others => '0'); end if; end if; end if; end process; end generate writeable_umr_gen; end generate umr_gen; no_umr_gen : if ((UC_MEMORY_REGIONS <= gregister) or ((AUX_MEMORY_REGIONS = 0) and (not HAS_ICACHE) and (not HAS_DCACHE))) generate umr_base_select(gregister) <= '0'; umr_last_select(gregister) <= '0'; mumr_base(gregister) <= (others => '0'); mumr_last(gregister) <= (others => '0'); end generate no_umr_gen; end generate memory_region_registers_gen; amr_gen : for gregister in imax(AUX_MEMORY_REGIONS, 1)-1 downto 0 generate amr_base_addrs(((gregister+1)*REGISTER_SIZE)-1 downto gregister*REGISTER_SIZE) <= mamr_base(gregister); amr_last_addrs(((gregister+1)*REGISTER_SIZE)-1 downto gregister*REGISTER_SIZE) <= mamr_last(gregister); end generate amr_gen; umr_gen : for gregister in imax(UC_MEMORY_REGIONS, 1)-1 downto 0 generate umr_base_addrs(((gregister+1)*REGISTER_SIZE)-1 downto gregister*REGISTER_SIZE) <= mumr_base(gregister); umr_last_addrs(((gregister+1)*REGISTER_SIZE)-1 downto gregister*REGISTER_SIZE) <= mumr_last(gregister); end generate umr_gen; has_icache_gen : if HAS_ICACHE generate mcache(CSR_MCACHE_IEXISTS) <= '1'; end generate has_icache_gen; no_icache_gen : if not HAS_ICACHE generate mcache(CSR_MCACHE_IEXISTS) <= '0'; end generate no_icache_gen; has_dcache_gen : if HAS_DCACHE generate mcache(CSR_MCACHE_DEXISTS) <= '1'; end generate has_dcache_gen; no_dcache_gen : if not HAS_DCACHE generate mcache(CSR_MCACHE_DEXISTS) <= '0'; end generate no_dcache_gen; mcache(REGISTER_SIZE-1 downto CSR_MCACHE_DEXISTS+1) <= (others => '0'); process(clk) begin if rising_edge(clk) then from_syscall_valid <= '0'; --Hold pc_correction causing signals until they have been processed if from_pc_correction_ready = '1' then fence_pc_correction_valid <= '0'; --On FENCE.I hold the PC correction until all pending writebacks have --occurred and the ICache is flushed (from_icache_control_ready is --hardwired to '1' when no ICache is present). if (memory_idle = '1' and (from_icache_control_ready = '1' or to_icache_control_valid = '0') and (from_dcache_control_ready = '1' or to_dcache_control_valid = '0')) then fence_pending <= '0'; amr_base_write <= (others => '0'); amr_last_write <= (others => '0'); umr_base_write <= (others => '0'); umr_last_write <= (others => '0'); end if; end if; if from_icache_control_ready = '1' then to_icache_control_valid <= '0'; end if; if from_dcache_control_ready = '1' then to_dcache_control_valid <= '0'; end if; if illegal_instruction = '0' and to_syscall_valid = '1' then if csr_select = '1' then --CSR Read/Write from_syscall_valid <= '1'; from_syscall_data <= csr_readdata; last_csr_writedata <= csr_writedata; --Changing cacheability flushes the pipeline and clears the --memory interface before resuming. if or_slv(amr_base_select or amr_last_select or umr_base_select or umr_last_select) = '1' then fence_pc_correction_valid <= '1'; fence_pending <= '1'; end if; amr_base_write <= amr_base_select; amr_last_write <= amr_last_select; umr_base_write <= umr_base_select; umr_last_write <= umr_last_select; end if; next_fence_pc <= unsigned(current_pc) + to_unsigned(4, next_fence_pc'length); to_icache_control_command <= INVALIDATE; to_dcache_control_command <= WRITEBACK; to_cache_control_base <= rs1_data; to_cache_control_last <= rs2_data; if fencei_select = '1' then --FENCE.I/FENCE.RI fence_pc_correction_valid <= '1'; fence_pending <= '1'; to_icache_control_valid <= '1'; to_dcache_control_valid <= '1'; if func7(1) = '0' then --FENCE.I does not take base/last parameters; applies to all of cache to_cache_control_base <= (others => '0'); to_cache_control_last <= (others => '1'); end if; --Unclear from the REGION draft spec if FENCE.RI should return a --value or not, since it can't partially complete. Omitting for now --as it doesn't seem useful. end if; if cache_select = '1' then --CACHE control instructions --A FENCE is implied by all cache control instructions. fence_pc_correction_valid <= '1'; fence_pending <= '1'; --Cache control instructions must return a value > rs2 on completion, --corresponding to the start of memory not affected. Since if all --memory is affected it's valid to return 0, just return 0 for all --these instructions. from_syscall_valid <= '1'; from_syscall_data <= (others => '0'); to_dcache_control_valid <= '1'; case func7(1 downto 0) is when "00" => --CACHE_WRITEBACK_FUNC7(1 downto 0) to_dcache_control_command <= WRITEBACK; when "01" => --CACHE_FLUSH_FUNC7(1 downto 0) to_dcache_control_command <= FLUSH; when others => --CACHE_DISCARD_FUNC7(1 downto 0) + don't care --Currently INVALIDATE invalidates the entire cache which is not --safe. Until region support is added just flush the cache which --is always safe. to_dcache_control_command <= FLUSH; end case; end if; if fence_select = '1' then --FENCE --All interfaces are strictly ordered and when switching between --interfaces (via AMR/UMR writes) a FENCE is performed, so FENCEs --don't need to do anything. --Unclear from the REGION draft spec if FENCE.RI should return a --value or not, since it can't partially complete. Omitting for now --as it doesn't seem useful. null; end if; end if; if VCP_ENABLE /= DISABLED and vcp_writeback_en = '1' then -- To avoid having a 5 to one mux in execute, we add -- the writebacks from the vcp here. Since the writebacks -- are from vbx_get, which are sort of control/status -- registers it could be construed that this is an -- appropriate place for this logic from_syscall_data <= vcp_writeback_data; from_syscall_valid <= '1'; end if; if reset = '1' then from_syscall_valid <= '0'; fence_pc_correction_valid <= '0'; fence_pending <= '0'; to_icache_control_valid <= '0'; to_dcache_control_valid <= '0'; amr_base_write <= (others => '0'); amr_last_write <= (others => '0'); umr_base_write <= (others => '0'); umr_last_write <= (others => '0'); end if; end if; end process; -------------------------------------------------------------------------------- -- Handle Global Interrupts -- -- If interrupt is pending and enabled, slip the pipeline. This is done by -- sending the interrupt_pending signal to the instruction_fetch. -- -- Once the pipeline is empty, then correct the PC. -------------------------------------------------------------------------------- interrupts_gen : if ENABLE_EXT_INTERRUPTS generate process(clk) begin if rising_edge(clk) then meipend(NUM_EXT_INTERRUPTS-1 downto 0) <= global_interrupts; end if; end process; meimask(NUM_EXT_INTERRUPTS-1 downto 0) <= meimask_full(NUM_EXT_INTERRUPTS-1 downto 0); not_all_interrupts_gen : if NUM_EXT_INTERRUPTS < REGISTER_SIZE generate meipend(REGISTER_SIZE-1 downto NUM_EXT_INTERRUPTS) <= (others => '0'); meimask(REGISTER_SIZE-1 downto NUM_EXT_INTERRUPTS) <= (others => '0'); end generate not_all_interrupts_gen; end generate interrupts_gen; no_interrupts_gen : if not ENABLE_EXT_INTERRUPTS generate meipend <= (others => '0'); meimask <= (others => '0'); end generate no_interrupts_gen; interrupt_pending <= mstatus(CSR_MSTATUS_MIE) when unsigned(meimask and meipend) /= 0 or timer_interrupt = '1' else '0'; pause_ifetch <= fence_pending or interrupt_pending; -- There are several reasons that sys_calls might send a pc correction -- global interrupt -- illegal instruction -- mret instruction -- fence.i (flush pipeline, and start over) to_pc_correction_valid <= fence_pc_correction_valid or was_mret or was_illegal or interrupt_pc_correction_valid; to_pc_correction_data <= next_fence_pc when fence_pc_correction_valid = '1' else unsigned(mtvec) when (was_illegal = '1' or interrupt_pc_correction_valid = '1') else unsigned(mepc) when was_mret = '1' else (others => '-'); end architecture rtl;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc705.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:08 1996 -- -- **************************** -- -- **************************** -- -- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:43 1996 -- -- **************************** -- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:46 1996 -- -- **************************** -- ENTITY c03s04b01x00p23n01i00705ent IS END c03s04b01x00p23n01i00705ent; ARCHITECTURE c03s04b01x00p23n01i00705arch OF c03s04b01x00p23n01i00705ent IS BEGIN TESTING: PROCESS -- Declare the type and the file. subtype BIT_VECTOR5 is BIT_VECTOR( 1 to 5 ); type FT is file of BIT_VECTOR5; -- Declare the actual file to read. file FILEV : FT open read_mode is "iofile.57"; -- Declare a variable into which we will read. constant CON : BIT_VECTOR5 := B"10101"; variable VAR : BIT_VECTOR5; variable k : integer := 0; BEGIN -- Read in the file. for I in 1 to 100 loop if (ENDFILE( FILEV ) /= FALSE) then k := 1; end if; assert( (ENDFILE( FILEV ) = FALSE) ) report "Hit the end of file too soon."; READ( FILEV,VAR ); if (VAR /= CON) then k := 1; end if; end loop; -- Verify that we are at the end. if (ENDFILE( FILEV ) /= TRUE) then k := 1; end if; assert( ENDFILE( FILEV ) = TRUE ) report "Have not reached end of file yet." severity ERROR; assert NOT( k = 0 ) report "***PASSED TEST: c03s04b01x00p23n01i00705" severity NOTE; assert( k = 0 ) report "***FAILED TEST: c03s04b01x00p23n01i00705 - The variables don't equal the constants." severity ERROR; wait; END PROCESS TESTING; END c03s04b01x00p23n01i00705arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc705.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:08 1996 -- -- **************************** -- -- **************************** -- -- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:43 1996 -- -- **************************** -- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:46 1996 -- -- **************************** -- ENTITY c03s04b01x00p23n01i00705ent IS END c03s04b01x00p23n01i00705ent; ARCHITECTURE c03s04b01x00p23n01i00705arch OF c03s04b01x00p23n01i00705ent IS BEGIN TESTING: PROCESS -- Declare the type and the file. subtype BIT_VECTOR5 is BIT_VECTOR( 1 to 5 ); type FT is file of BIT_VECTOR5; -- Declare the actual file to read. file FILEV : FT open read_mode is "iofile.57"; -- Declare a variable into which we will read. constant CON : BIT_VECTOR5 := B"10101"; variable VAR : BIT_VECTOR5; variable k : integer := 0; BEGIN -- Read in the file. for I in 1 to 100 loop if (ENDFILE( FILEV ) /= FALSE) then k := 1; end if; assert( (ENDFILE( FILEV ) = FALSE) ) report "Hit the end of file too soon."; READ( FILEV,VAR ); if (VAR /= CON) then k := 1; end if; end loop; -- Verify that we are at the end. if (ENDFILE( FILEV ) /= TRUE) then k := 1; end if; assert( ENDFILE( FILEV ) = TRUE ) report "Have not reached end of file yet." severity ERROR; assert NOT( k = 0 ) report "***PASSED TEST: c03s04b01x00p23n01i00705" severity NOTE; assert( k = 0 ) report "***FAILED TEST: c03s04b01x00p23n01i00705 - The variables don't equal the constants." severity ERROR; wait; END PROCESS TESTING; END c03s04b01x00p23n01i00705arch;