content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19104)
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19104)
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
entity slot_bus_master_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_slot_req;
resp : in t_slot_resp );
end slot_bus_master_bfm;
architecture bfm of slot_bus_master_bfm is
shared variable this : p_slot_bus_master_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, exec);
signal state : t_state := idle;
signal delay : integer := 0;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_slot_bus_master_bfm(g_name, this);
bound <= true;
wait;
end process;
process(clock)
begin
if rising_edge(clock) then
req.bus_write <= '0';
req.io_read <= '0';
req.io_write <= '0';
this.irq_pending := (resp.irq = '1');
case state is
when idle =>
req <= c_slot_req_init;
if bound then
delay <= 3;
if this.command /= e_slot_none then
req.io_address <= this.address;
req.bus_address <= this.address;
req.data <= this.data;
end if;
case this.command is
when e_slot_io_read =>
state <= exec;
when e_slot_io_write =>
state <= exec;
when e_slot_bus_read =>
state <= exec;
when e_slot_bus_write =>
req.bus_write <= '1';
state <= exec;
when others =>
null;
end case;
end if;
when exec =>
if delay=0 then
case this.command is
when e_slot_io_read =>
req.io_read <= '1';
when e_slot_io_write =>
req.io_write <= '1';
when others =>
null;
end case;
if resp.reg_output='1' then
this.data := resp.data;
else
this.data := (others => 'X');
end if;
this.command := e_slot_none;
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
end if;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
entity slot_bus_master_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_slot_req;
resp : in t_slot_resp );
end slot_bus_master_bfm;
architecture bfm of slot_bus_master_bfm is
shared variable this : p_slot_bus_master_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, exec);
signal state : t_state := idle;
signal delay : integer := 0;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_slot_bus_master_bfm(g_name, this);
bound <= true;
wait;
end process;
process(clock)
begin
if rising_edge(clock) then
req.bus_write <= '0';
req.io_read <= '0';
req.io_write <= '0';
this.irq_pending := (resp.irq = '1');
case state is
when idle =>
req <= c_slot_req_init;
if bound then
delay <= 3;
if this.command /= e_slot_none then
req.io_address <= this.address;
req.bus_address <= this.address;
req.data <= this.data;
end if;
case this.command is
when e_slot_io_read =>
state <= exec;
when e_slot_io_write =>
state <= exec;
when e_slot_bus_read =>
state <= exec;
when e_slot_bus_write =>
req.bus_write <= '1';
state <= exec;
when others =>
null;
end case;
end if;
when exec =>
if delay=0 then
case this.command is
when e_slot_io_read =>
req.io_read <= '1';
when e_slot_io_write =>
req.io_write <= '1';
when others =>
null;
end case;
if resp.reg_output='1' then
this.data := resp.data;
else
this.data := (others => 'X');
end if;
this.command := e_slot_none;
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
end if;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
entity slot_bus_master_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_slot_req;
resp : in t_slot_resp );
end slot_bus_master_bfm;
architecture bfm of slot_bus_master_bfm is
shared variable this : p_slot_bus_master_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, exec);
signal state : t_state := idle;
signal delay : integer := 0;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_slot_bus_master_bfm(g_name, this);
bound <= true;
wait;
end process;
process(clock)
begin
if rising_edge(clock) then
req.bus_write <= '0';
req.io_read <= '0';
req.io_write <= '0';
this.irq_pending := (resp.irq = '1');
case state is
when idle =>
req <= c_slot_req_init;
if bound then
delay <= 3;
if this.command /= e_slot_none then
req.io_address <= this.address;
req.bus_address <= this.address;
req.data <= this.data;
end if;
case this.command is
when e_slot_io_read =>
state <= exec;
when e_slot_io_write =>
state <= exec;
when e_slot_bus_read =>
state <= exec;
when e_slot_bus_write =>
req.bus_write <= '1';
state <= exec;
when others =>
null;
end case;
end if;
when exec =>
if delay=0 then
case this.command is
when e_slot_io_read =>
req.io_read <= '1';
when e_slot_io_write =>
req.io_write <= '1';
when others =>
null;
end case;
if resp.reg_output='1' then
this.data := resp.data;
else
this.data := (others => 'X');
end if;
this.command := e_slot_none;
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
end if;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
entity slot_bus_master_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_slot_req;
resp : in t_slot_resp );
end slot_bus_master_bfm;
architecture bfm of slot_bus_master_bfm is
shared variable this : p_slot_bus_master_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, exec);
signal state : t_state := idle;
signal delay : integer := 0;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_slot_bus_master_bfm(g_name, this);
bound <= true;
wait;
end process;
process(clock)
begin
if rising_edge(clock) then
req.bus_write <= '0';
req.io_read <= '0';
req.io_write <= '0';
this.irq_pending := (resp.irq = '1');
case state is
when idle =>
req <= c_slot_req_init;
if bound then
delay <= 3;
if this.command /= e_slot_none then
req.io_address <= this.address;
req.bus_address <= this.address;
req.data <= this.data;
end if;
case this.command is
when e_slot_io_read =>
state <= exec;
when e_slot_io_write =>
state <= exec;
when e_slot_bus_read =>
state <= exec;
when e_slot_bus_write =>
req.bus_write <= '1';
state <= exec;
when others =>
null;
end case;
end if;
when exec =>
if delay=0 then
case this.command is
when e_slot_io_read =>
req.io_read <= '1';
when e_slot_io_write =>
req.io_write <= '1';
when others =>
null;
end case;
if resp.reg_output='1' then
this.data := resp.data;
else
this.data := (others => 'X');
end if;
this.command := e_slot_none;
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
end if;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
entity slot_bus_master_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_slot_req;
resp : in t_slot_resp );
end slot_bus_master_bfm;
architecture bfm of slot_bus_master_bfm is
shared variable this : p_slot_bus_master_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, exec);
signal state : t_state := idle;
signal delay : integer := 0;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_slot_bus_master_bfm(g_name, this);
bound <= true;
wait;
end process;
process(clock)
begin
if rising_edge(clock) then
req.bus_write <= '0';
req.io_read <= '0';
req.io_write <= '0';
this.irq_pending := (resp.irq = '1');
case state is
when idle =>
req <= c_slot_req_init;
if bound then
delay <= 3;
if this.command /= e_slot_none then
req.io_address <= this.address;
req.bus_address <= this.address;
req.data <= this.data;
end if;
case this.command is
when e_slot_io_read =>
state <= exec;
when e_slot_io_write =>
state <= exec;
when e_slot_bus_read =>
state <= exec;
when e_slot_bus_write =>
req.bus_write <= '1';
state <= exec;
when others =>
null;
end case;
end if;
when exec =>
if delay=0 then
case this.command is
when e_slot_io_read =>
req.io_read <= '1';
when e_slot_io_write =>
req.io_write <= '1';
when others =>
null;
end case;
if resp.reg_output='1' then
this.data := resp.data;
else
this.data := (others => 'X');
end if;
this.command := e_slot_none;
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
end if;
end process;
end bfm;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : floppy_stream.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--library work;
--use work.floppy_emu_pkg.all;
entity floppy_stream is
port (
clock : in std_logic;
clock_en : in std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
reset : in std_logic;
-- data from memory
drv_rdata : in std_logic_vector(7 downto 0);
do_read : out std_logic;
do_write : out std_logic;
do_advance : out std_logic;
-- info about the head
track : out std_logic_vector(6 downto 0);
track_is_0 : out std_logic;
do_head_bang : out std_logic;
do_track_out : out std_logic;
do_track_in : out std_logic;
-- control i/o
floppy_inserted : in std_logic;
motor_on : in std_logic;
sync : out std_logic;
mode : in std_logic;
write_prot_n : in std_logic;
step : in std_logic_vector(1 downto 0);
byte_ready : out std_logic;
soe : in std_logic;
rate_ctrl : in std_logic_vector(1 downto 0); -- dont have any effect anymore
bit_time : in unsigned(8 downto 0); -- in steps of 10 ns
-- data to drive CPU
read_data : out std_logic_vector(7 downto 0) );
end floppy_stream;
architecture gideon of floppy_stream is
signal bit_square : std_logic;
signal bit_tick : std_logic;
signal bit_timer : unsigned(7 downto 0);
signal bit_carry : std_logic;
signal mem_bit_cnt : unsigned(2 downto 0);
signal rd_bit_cnt : unsigned(2 downto 0) := "000";
signal mem_shift : std_logic_vector(7 downto 0);
signal rd_shift : std_logic_vector(9 downto 0) := (others => '0');
signal sync_i : std_logic;
signal byte_rdy_i : std_logic;
alias mem_rd_bit : std_logic is mem_shift(7);
--signal track_c : unsigned(6 downto 2);
signal track_i : unsigned(6 downto 0);
signal up, down : std_logic;
signal step_d : std_logic_vector(1 downto 0);
signal step_dd0 : std_logic;
signal mode_d : std_logic;
signal write_delay : integer range 0 to 3;
signal random_data : std_logic_vector(15 downto 0);
begin
p_clock_div: process(clock)
begin
if rising_edge(clock) then
bit_tick <= '0';
if bit_timer = 0 then
bit_tick <= motor_on;
bit_carry <= not bit_carry and bit_time(0); -- toggle if bit 0 is set
if bit_carry='1' then
bit_timer <= bit_time(8 downto 1);
else
bit_timer <= bit_time(8 downto 1) - 1;
end if;
else
bit_timer <= bit_timer - 1;
end if;
bit_square <= '0';
if bit_timer < ('0' & bit_time(8 downto 2)) then
bit_square <= '1';
end if;
if reset='1' then
bit_timer <= to_unsigned(10, bit_timer'length);
bit_carry <= '0';
end if;
-- if clock_en='1' then
-- if bit_div="1111" then
-- bit_div <= "00" & unsigned(rate_ctrl);
-- bit_tick <= motor_on;
-- else
-- bit_div <= bit_div + 1;
-- end if;
-- end if;
-- if reset='1' then
-- bit_div <= "0000";
-- end if;
end if;
end process;
-- stream from memory
p_stream: process(clock)
variable new_bit : std_logic;
begin
if rising_edge(clock) then
do_read <= '0';
if bit_tick='1' then
new_bit := random_data(15) xor random_data(13) xor random_data(12) xor random_data(10);
mem_bit_cnt <= mem_bit_cnt + 1;
if mem_bit_cnt="000" then
random_data <= random_data(14 downto 0) & new_bit;
if drv_rdata = X"00" then
mem_shift <= random_data(15 downto 8) and random_data(7 downto 0);
else
mem_shift <= drv_rdata;
end if;
-- issue command to fifo
do_read <= mode; --'1'; does not pulse when in write mode
else
mem_shift <= mem_shift(6 downto 0) & '1';
end if;
end if;
if reset='1' then
mem_shift <= (others => '1');
mem_bit_cnt <= "000";
random_data <= X"ABCD";
end if;
end if;
end process;
-- parallelize stream and generate sync
-- and handle writes
p_reading: process(clock)
variable s : std_logic;
begin
if rising_edge(clock) then
if rd_shift = "1111111111" and mode='1' then
s := '0';
else
s := '1';
end if;
sync_i <= s;
do_advance <= '0';
mode_d <= mode;
if mode_d='1' and mode='0' then -- going to write
write_delay <= 2;
do_advance <= '0';
end if;
do_write <= '0';
if rd_bit_cnt = "111" and mode='0' and bit_tick='1' then
if write_delay = 0 then
do_write <= floppy_inserted; --'1';
else
do_advance <= '1';
write_delay <= write_delay - 1;
end if;
end if;
if bit_tick='1' then
rd_shift <= rd_shift(8 downto 0) & mem_rd_bit;
rd_bit_cnt <= rd_bit_cnt + 1;
end if;
if s = '0' then
rd_bit_cnt <= "000";
end if;
if (rd_bit_cnt="111") and (soe = '1') and (bit_square='1') then
byte_rdy_i <= '0';
else
byte_rdy_i <= '1';
end if;
end if;
end process;
p_move: process(clock)
variable st : std_logic_vector(3 downto 0);
begin
if rising_edge(clock) then
do_track_in <= '0';
do_track_out <= '0';
do_head_bang <= '0';
if motor_on='1' then
st := std_logic_vector(track_i(1 downto 0)) & step;
down <= '0';
up <= '0';
case st is
when "0001" | "0110" | "1011" | "1100" => -- up
do_track_in <= '1';
if track_i /= 83 then
track_i <= track_i + 1;
end if;
when "0011" | "0100" | "1001" | "1110" => -- down
do_track_out <= '1';
if track_i /= 0 then
track_i <= track_i - 1;
end if;
when others =>
null;
end case;
end if;
if reset='1' then
track_i <= "0100000";
end if;
end if;
end process;
-- track_i <= track_c & unsigned(step_d);
-- outputs
sync <= sync_i;
read_data <= rd_shift(7 downto 0);
byte_ready <= byte_rdy_i;
track <= std_logic_vector(track_i);
track_is_0 <= '1' when track_i = "0000000" else '0';
end gideon;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : floppy_stream.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--library work;
--use work.floppy_emu_pkg.all;
entity floppy_stream is
port (
clock : in std_logic;
clock_en : in std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
reset : in std_logic;
-- data from memory
drv_rdata : in std_logic_vector(7 downto 0);
do_read : out std_logic;
do_write : out std_logic;
do_advance : out std_logic;
-- info about the head
track : out std_logic_vector(6 downto 0);
track_is_0 : out std_logic;
do_head_bang : out std_logic;
do_track_out : out std_logic;
do_track_in : out std_logic;
-- control i/o
floppy_inserted : in std_logic;
motor_on : in std_logic;
sync : out std_logic;
mode : in std_logic;
write_prot_n : in std_logic;
step : in std_logic_vector(1 downto 0);
byte_ready : out std_logic;
soe : in std_logic;
rate_ctrl : in std_logic_vector(1 downto 0); -- dont have any effect anymore
bit_time : in unsigned(8 downto 0); -- in steps of 10 ns
-- data to drive CPU
read_data : out std_logic_vector(7 downto 0) );
end floppy_stream;
architecture gideon of floppy_stream is
signal bit_square : std_logic;
signal bit_tick : std_logic;
signal bit_timer : unsigned(7 downto 0);
signal bit_carry : std_logic;
signal mem_bit_cnt : unsigned(2 downto 0);
signal rd_bit_cnt : unsigned(2 downto 0) := "000";
signal mem_shift : std_logic_vector(7 downto 0);
signal rd_shift : std_logic_vector(9 downto 0) := (others => '0');
signal sync_i : std_logic;
signal byte_rdy_i : std_logic;
alias mem_rd_bit : std_logic is mem_shift(7);
--signal track_c : unsigned(6 downto 2);
signal track_i : unsigned(6 downto 0);
signal up, down : std_logic;
signal step_d : std_logic_vector(1 downto 0);
signal step_dd0 : std_logic;
signal mode_d : std_logic;
signal write_delay : integer range 0 to 3;
signal random_data : std_logic_vector(15 downto 0);
begin
p_clock_div: process(clock)
begin
if rising_edge(clock) then
bit_tick <= '0';
if bit_timer = 0 then
bit_tick <= motor_on;
bit_carry <= not bit_carry and bit_time(0); -- toggle if bit 0 is set
if bit_carry='1' then
bit_timer <= bit_time(8 downto 1);
else
bit_timer <= bit_time(8 downto 1) - 1;
end if;
else
bit_timer <= bit_timer - 1;
end if;
bit_square <= '0';
if bit_timer < ('0' & bit_time(8 downto 2)) then
bit_square <= '1';
end if;
if reset='1' then
bit_timer <= to_unsigned(10, bit_timer'length);
bit_carry <= '0';
end if;
-- if clock_en='1' then
-- if bit_div="1111" then
-- bit_div <= "00" & unsigned(rate_ctrl);
-- bit_tick <= motor_on;
-- else
-- bit_div <= bit_div + 1;
-- end if;
-- end if;
-- if reset='1' then
-- bit_div <= "0000";
-- end if;
end if;
end process;
-- stream from memory
p_stream: process(clock)
variable new_bit : std_logic;
begin
if rising_edge(clock) then
do_read <= '0';
if bit_tick='1' then
new_bit := random_data(15) xor random_data(13) xor random_data(12) xor random_data(10);
mem_bit_cnt <= mem_bit_cnt + 1;
if mem_bit_cnt="000" then
random_data <= random_data(14 downto 0) & new_bit;
if drv_rdata = X"00" then
mem_shift <= random_data(15 downto 8) and random_data(7 downto 0);
else
mem_shift <= drv_rdata;
end if;
-- issue command to fifo
do_read <= mode; --'1'; does not pulse when in write mode
else
mem_shift <= mem_shift(6 downto 0) & '1';
end if;
end if;
if reset='1' then
mem_shift <= (others => '1');
mem_bit_cnt <= "000";
random_data <= X"ABCD";
end if;
end if;
end process;
-- parallelize stream and generate sync
-- and handle writes
p_reading: process(clock)
variable s : std_logic;
begin
if rising_edge(clock) then
if rd_shift = "1111111111" and mode='1' then
s := '0';
else
s := '1';
end if;
sync_i <= s;
do_advance <= '0';
mode_d <= mode;
if mode_d='1' and mode='0' then -- going to write
write_delay <= 2;
do_advance <= '0';
end if;
do_write <= '0';
if rd_bit_cnt = "111" and mode='0' and bit_tick='1' then
if write_delay = 0 then
do_write <= floppy_inserted; --'1';
else
do_advance <= '1';
write_delay <= write_delay - 1;
end if;
end if;
if bit_tick='1' then
rd_shift <= rd_shift(8 downto 0) & mem_rd_bit;
rd_bit_cnt <= rd_bit_cnt + 1;
end if;
if s = '0' then
rd_bit_cnt <= "000";
end if;
if (rd_bit_cnt="111") and (soe = '1') and (bit_square='1') then
byte_rdy_i <= '0';
else
byte_rdy_i <= '1';
end if;
end if;
end process;
p_move: process(clock)
variable st : std_logic_vector(3 downto 0);
begin
if rising_edge(clock) then
do_track_in <= '0';
do_track_out <= '0';
do_head_bang <= '0';
if motor_on='1' then
st := std_logic_vector(track_i(1 downto 0)) & step;
down <= '0';
up <= '0';
case st is
when "0001" | "0110" | "1011" | "1100" => -- up
do_track_in <= '1';
if track_i /= 83 then
track_i <= track_i + 1;
end if;
when "0011" | "0100" | "1001" | "1110" => -- down
do_track_out <= '1';
if track_i /= 0 then
track_i <= track_i - 1;
end if;
when others =>
null;
end case;
end if;
if reset='1' then
track_i <= "0100000";
end if;
end if;
end process;
-- track_i <= track_c & unsigned(step_d);
-- outputs
sync <= sync_i;
read_data <= rd_shift(7 downto 0);
byte_ready <= byte_rdy_i;
track <= std_logic_vector(track_i);
track_is_0 <= '1' when track_i = "0000000" else '0';
end gideon;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : floppy_stream.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--library work;
--use work.floppy_emu_pkg.all;
entity floppy_stream is
port (
clock : in std_logic;
clock_en : in std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
reset : in std_logic;
-- data from memory
drv_rdata : in std_logic_vector(7 downto 0);
do_read : out std_logic;
do_write : out std_logic;
do_advance : out std_logic;
-- info about the head
track : out std_logic_vector(6 downto 0);
track_is_0 : out std_logic;
do_head_bang : out std_logic;
do_track_out : out std_logic;
do_track_in : out std_logic;
-- control i/o
floppy_inserted : in std_logic;
motor_on : in std_logic;
sync : out std_logic;
mode : in std_logic;
write_prot_n : in std_logic;
step : in std_logic_vector(1 downto 0);
byte_ready : out std_logic;
soe : in std_logic;
rate_ctrl : in std_logic_vector(1 downto 0); -- dont have any effect anymore
bit_time : in unsigned(8 downto 0); -- in steps of 10 ns
-- data to drive CPU
read_data : out std_logic_vector(7 downto 0) );
end floppy_stream;
architecture gideon of floppy_stream is
signal bit_square : std_logic;
signal bit_tick : std_logic;
signal bit_timer : unsigned(7 downto 0);
signal bit_carry : std_logic;
signal mem_bit_cnt : unsigned(2 downto 0);
signal rd_bit_cnt : unsigned(2 downto 0) := "000";
signal mem_shift : std_logic_vector(7 downto 0);
signal rd_shift : std_logic_vector(9 downto 0) := (others => '0');
signal sync_i : std_logic;
signal byte_rdy_i : std_logic;
alias mem_rd_bit : std_logic is mem_shift(7);
--signal track_c : unsigned(6 downto 2);
signal track_i : unsigned(6 downto 0);
signal up, down : std_logic;
signal step_d : std_logic_vector(1 downto 0);
signal step_dd0 : std_logic;
signal mode_d : std_logic;
signal write_delay : integer range 0 to 3;
signal random_data : std_logic_vector(15 downto 0);
begin
p_clock_div: process(clock)
begin
if rising_edge(clock) then
bit_tick <= '0';
if bit_timer = 0 then
bit_tick <= motor_on;
bit_carry <= not bit_carry and bit_time(0); -- toggle if bit 0 is set
if bit_carry='1' then
bit_timer <= bit_time(8 downto 1);
else
bit_timer <= bit_time(8 downto 1) - 1;
end if;
else
bit_timer <= bit_timer - 1;
end if;
bit_square <= '0';
if bit_timer < ('0' & bit_time(8 downto 2)) then
bit_square <= '1';
end if;
if reset='1' then
bit_timer <= to_unsigned(10, bit_timer'length);
bit_carry <= '0';
end if;
-- if clock_en='1' then
-- if bit_div="1111" then
-- bit_div <= "00" & unsigned(rate_ctrl);
-- bit_tick <= motor_on;
-- else
-- bit_div <= bit_div + 1;
-- end if;
-- end if;
-- if reset='1' then
-- bit_div <= "0000";
-- end if;
end if;
end process;
-- stream from memory
p_stream: process(clock)
variable new_bit : std_logic;
begin
if rising_edge(clock) then
do_read <= '0';
if bit_tick='1' then
new_bit := random_data(15) xor random_data(13) xor random_data(12) xor random_data(10);
mem_bit_cnt <= mem_bit_cnt + 1;
if mem_bit_cnt="000" then
random_data <= random_data(14 downto 0) & new_bit;
if drv_rdata = X"00" then
mem_shift <= random_data(15 downto 8) and random_data(7 downto 0);
else
mem_shift <= drv_rdata;
end if;
-- issue command to fifo
do_read <= mode; --'1'; does not pulse when in write mode
else
mem_shift <= mem_shift(6 downto 0) & '1';
end if;
end if;
if reset='1' then
mem_shift <= (others => '1');
mem_bit_cnt <= "000";
random_data <= X"ABCD";
end if;
end if;
end process;
-- parallelize stream and generate sync
-- and handle writes
p_reading: process(clock)
variable s : std_logic;
begin
if rising_edge(clock) then
if rd_shift = "1111111111" and mode='1' then
s := '0';
else
s := '1';
end if;
sync_i <= s;
do_advance <= '0';
mode_d <= mode;
if mode_d='1' and mode='0' then -- going to write
write_delay <= 2;
do_advance <= '0';
end if;
do_write <= '0';
if rd_bit_cnt = "111" and mode='0' and bit_tick='1' then
if write_delay = 0 then
do_write <= floppy_inserted; --'1';
else
do_advance <= '1';
write_delay <= write_delay - 1;
end if;
end if;
if bit_tick='1' then
rd_shift <= rd_shift(8 downto 0) & mem_rd_bit;
rd_bit_cnt <= rd_bit_cnt + 1;
end if;
if s = '0' then
rd_bit_cnt <= "000";
end if;
if (rd_bit_cnt="111") and (soe = '1') and (bit_square='1') then
byte_rdy_i <= '0';
else
byte_rdy_i <= '1';
end if;
end if;
end process;
p_move: process(clock)
variable st : std_logic_vector(3 downto 0);
begin
if rising_edge(clock) then
do_track_in <= '0';
do_track_out <= '0';
do_head_bang <= '0';
if motor_on='1' then
st := std_logic_vector(track_i(1 downto 0)) & step;
down <= '0';
up <= '0';
case st is
when "0001" | "0110" | "1011" | "1100" => -- up
do_track_in <= '1';
if track_i /= 83 then
track_i <= track_i + 1;
end if;
when "0011" | "0100" | "1001" | "1110" => -- down
do_track_out <= '1';
if track_i /= 0 then
track_i <= track_i - 1;
end if;
when others =>
null;
end case;
end if;
if reset='1' then
track_i <= "0100000";
end if;
end if;
end process;
-- track_i <= track_c & unsigned(step_d);
-- outputs
sync <= sync_i;
read_data <= rd_shift(7 downto 0);
byte_ready <= byte_rdy_i;
track <= std_logic_vector(track_i);
track_is_0 <= '1' when track_i = "0000000" else '0';
end gideon;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : floppy_stream.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--library work;
--use work.floppy_emu_pkg.all;
entity floppy_stream is
port (
clock : in std_logic;
clock_en : in std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
reset : in std_logic;
-- data from memory
drv_rdata : in std_logic_vector(7 downto 0);
do_read : out std_logic;
do_write : out std_logic;
do_advance : out std_logic;
-- info about the head
track : out std_logic_vector(6 downto 0);
track_is_0 : out std_logic;
do_head_bang : out std_logic;
do_track_out : out std_logic;
do_track_in : out std_logic;
-- control i/o
floppy_inserted : in std_logic;
motor_on : in std_logic;
sync : out std_logic;
mode : in std_logic;
write_prot_n : in std_logic;
step : in std_logic_vector(1 downto 0);
byte_ready : out std_logic;
soe : in std_logic;
rate_ctrl : in std_logic_vector(1 downto 0); -- dont have any effect anymore
bit_time : in unsigned(8 downto 0); -- in steps of 10 ns
-- data to drive CPU
read_data : out std_logic_vector(7 downto 0) );
end floppy_stream;
architecture gideon of floppy_stream is
signal bit_square : std_logic;
signal bit_tick : std_logic;
signal bit_timer : unsigned(7 downto 0);
signal bit_carry : std_logic;
signal mem_bit_cnt : unsigned(2 downto 0);
signal rd_bit_cnt : unsigned(2 downto 0) := "000";
signal mem_shift : std_logic_vector(7 downto 0);
signal rd_shift : std_logic_vector(9 downto 0) := (others => '0');
signal sync_i : std_logic;
signal byte_rdy_i : std_logic;
alias mem_rd_bit : std_logic is mem_shift(7);
--signal track_c : unsigned(6 downto 2);
signal track_i : unsigned(6 downto 0);
signal up, down : std_logic;
signal step_d : std_logic_vector(1 downto 0);
signal step_dd0 : std_logic;
signal mode_d : std_logic;
signal write_delay : integer range 0 to 3;
signal random_data : std_logic_vector(15 downto 0);
begin
p_clock_div: process(clock)
begin
if rising_edge(clock) then
bit_tick <= '0';
if bit_timer = 0 then
bit_tick <= motor_on;
bit_carry <= not bit_carry and bit_time(0); -- toggle if bit 0 is set
if bit_carry='1' then
bit_timer <= bit_time(8 downto 1);
else
bit_timer <= bit_time(8 downto 1) - 1;
end if;
else
bit_timer <= bit_timer - 1;
end if;
bit_square <= '0';
if bit_timer < ('0' & bit_time(8 downto 2)) then
bit_square <= '1';
end if;
if reset='1' then
bit_timer <= to_unsigned(10, bit_timer'length);
bit_carry <= '0';
end if;
-- if clock_en='1' then
-- if bit_div="1111" then
-- bit_div <= "00" & unsigned(rate_ctrl);
-- bit_tick <= motor_on;
-- else
-- bit_div <= bit_div + 1;
-- end if;
-- end if;
-- if reset='1' then
-- bit_div <= "0000";
-- end if;
end if;
end process;
-- stream from memory
p_stream: process(clock)
variable new_bit : std_logic;
begin
if rising_edge(clock) then
do_read <= '0';
if bit_tick='1' then
new_bit := random_data(15) xor random_data(13) xor random_data(12) xor random_data(10);
mem_bit_cnt <= mem_bit_cnt + 1;
if mem_bit_cnt="000" then
random_data <= random_data(14 downto 0) & new_bit;
if drv_rdata = X"00" then
mem_shift <= random_data(15 downto 8) and random_data(7 downto 0);
else
mem_shift <= drv_rdata;
end if;
-- issue command to fifo
do_read <= mode; --'1'; does not pulse when in write mode
else
mem_shift <= mem_shift(6 downto 0) & '1';
end if;
end if;
if reset='1' then
mem_shift <= (others => '1');
mem_bit_cnt <= "000";
random_data <= X"ABCD";
end if;
end if;
end process;
-- parallelize stream and generate sync
-- and handle writes
p_reading: process(clock)
variable s : std_logic;
begin
if rising_edge(clock) then
if rd_shift = "1111111111" and mode='1' then
s := '0';
else
s := '1';
end if;
sync_i <= s;
do_advance <= '0';
mode_d <= mode;
if mode_d='1' and mode='0' then -- going to write
write_delay <= 2;
do_advance <= '0';
end if;
do_write <= '0';
if rd_bit_cnt = "111" and mode='0' and bit_tick='1' then
if write_delay = 0 then
do_write <= floppy_inserted; --'1';
else
do_advance <= '1';
write_delay <= write_delay - 1;
end if;
end if;
if bit_tick='1' then
rd_shift <= rd_shift(8 downto 0) & mem_rd_bit;
rd_bit_cnt <= rd_bit_cnt + 1;
end if;
if s = '0' then
rd_bit_cnt <= "000";
end if;
if (rd_bit_cnt="111") and (soe = '1') and (bit_square='1') then
byte_rdy_i <= '0';
else
byte_rdy_i <= '1';
end if;
end if;
end process;
p_move: process(clock)
variable st : std_logic_vector(3 downto 0);
begin
if rising_edge(clock) then
do_track_in <= '0';
do_track_out <= '0';
do_head_bang <= '0';
if motor_on='1' then
st := std_logic_vector(track_i(1 downto 0)) & step;
down <= '0';
up <= '0';
case st is
when "0001" | "0110" | "1011" | "1100" => -- up
do_track_in <= '1';
if track_i /= 83 then
track_i <= track_i + 1;
end if;
when "0011" | "0100" | "1001" | "1110" => -- down
do_track_out <= '1';
if track_i /= 0 then
track_i <= track_i - 1;
end if;
when others =>
null;
end case;
end if;
if reset='1' then
track_i <= "0100000";
end if;
end if;
end process;
-- track_i <= track_c & unsigned(step_d);
-- outputs
sync <= sync_i;
read_data <= rd_shift(7 downto 0);
byte_ready <= byte_rdy_i;
track <= std_logic_vector(track_i);
track_is_0 <= '1' when track_i = "0000000" else '0';
end gideon;
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_to_uint - Structural
-- Description: Converts an IEEE-754 floating point number back to a uint
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ieee754_fp_to_uint is
generic(
WIDTH : integer := 10
);
port(
x : in std_logic_vector(31 downto 0);
y : out std_logic_vector(WIDTH - 1 downto 0)
);
end ieee754_fp_to_uint;
architecture Structural of ieee754_fp_to_uint is
signal exponent : std_logic_vector(7 downto 0);
signal mantissa : std_logic_vector(23 downto 0);
begin
exponent <= x(30 downto 23);
mantissa(23) <= '1';
mantissa(22 downto 0) <= x(22 downto 0);
process(exponent, mantissa)
variable exp : integer := 0;
variable shifted_mantissa : unsigned(23 downto 0);
begin
exp := to_integer(unsigned(exponent)) - 127;
-- bit shift back to base zero
shifted_mantissa := unsigned(mantissa) srl (23 - exp);
y <= std_logic_vector(shifted_mantissa(WIDTH - 1 downto 0));
end process;
end Structural;
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_to_uint - Structural
-- Description: Converts an IEEE-754 floating point number back to a uint
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ieee754_fp_to_uint is
generic(
WIDTH : integer := 10
);
port(
x : in std_logic_vector(31 downto 0);
y : out std_logic_vector(WIDTH - 1 downto 0)
);
end ieee754_fp_to_uint;
architecture Structural of ieee754_fp_to_uint is
signal exponent : std_logic_vector(7 downto 0);
signal mantissa : std_logic_vector(23 downto 0);
begin
exponent <= x(30 downto 23);
mantissa(23) <= '1';
mantissa(22 downto 0) <= x(22 downto 0);
process(exponent, mantissa)
variable exp : integer := 0;
variable shifted_mantissa : unsigned(23 downto 0);
begin
exp := to_integer(unsigned(exponent)) - 127;
-- bit shift back to base zero
shifted_mantissa := unsigned(mantissa) srl (23 - exp);
y <= std_logic_vector(shifted_mantissa(WIDTH - 1 downto 0));
end process;
end Structural;
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_to_uint - Structural
-- Description: Converts an IEEE-754 floating point number back to a uint
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ieee754_fp_to_uint is
generic(
WIDTH : integer := 10
);
port(
x : in std_logic_vector(31 downto 0);
y : out std_logic_vector(WIDTH - 1 downto 0)
);
end ieee754_fp_to_uint;
architecture Structural of ieee754_fp_to_uint is
signal exponent : std_logic_vector(7 downto 0);
signal mantissa : std_logic_vector(23 downto 0);
begin
exponent <= x(30 downto 23);
mantissa(23) <= '1';
mantissa(22 downto 0) <= x(22 downto 0);
process(exponent, mantissa)
variable exp : integer := 0;
variable shifted_mantissa : unsigned(23 downto 0);
begin
exp := to_integer(unsigned(exponent)) - 127;
-- bit shift back to base zero
shifted_mantissa := unsigned(mantissa) srl (23 - exp);
y <= std_logic_vector(shifted_mantissa(WIDTH - 1 downto 0));
end process;
end Structural;
|
--
-- UART Baudrate generator
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART baudrate generator
entity uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end uart_baudgen;
architecture rtl of uart_baudgen is
-- Signals
signal iCounter : unsigned(15 downto 0);
begin
-- Baudrate counter
BG_COUNT: process (CLK, RST)
begin
if (RST = '1') then
iCounter <= (others => '0');
BAUDTICK <= '0';
elsif (CLK'event and CLK = '1') then
if (CLEAR = '1') then
iCounter <= (others => '0');
elsif (CE = '1') then
iCounter <= iCounter + 1;
end if;
BAUDTICK <= '0';
if (iCounter = unsigned(DIVIDER)) then
iCounter <= (others => '0');
BAUDTICK <= '1';
end if;
end if;
end process;
end rtl;
|
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library altera;
use altera.altera_syn_attributes.all;
library lpm;
use lpm.all;
entity blink_top is
port
(
-- {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!
A : out std_logic;
B : out std_logic;
btn0 : in std_logic;
btn1 : in std_logic;
btn2 : in std_logic;
btn3 : in std_logic;
C : out std_logic;
clk : in std_logic;
CT1 : out std_logic;
CT2 : out std_logic;
CT3 : out std_logic;
CT4 : out std_logic;
D : out std_logic;
DP : out std_logic;
E : out std_logic;
F : out std_logic;
G : out std_logic;
hcsr04trig : out std_logic;
hcsr04echo : in std_logic
-- {ALTERA_IO_END} DO NOT REMOVE THIS LINE!
);
-- {ALTERA_ATTRIBUTE_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_ATTRIBUTE_END} DO NOT REMOVE THIS LINE!
end blink_top;
architecture ppl_type of blink_top is
signal cnt : std_logic_vector(22 downto 0);
signal stopwatch_cur : std_logic_vector(15 downto 0);
signal stopwatch_lap0: std_logic_vector(15 downto 0);
signal stopwatch_lap1: std_logic_vector(15 downto 0);
signal stopwatch_lap2: std_logic_vector(15 downto 0);
signal current_time: std_logic_vector(15 downto 0);
signal time_idx: std_logic_vector(1 downto 0);
signal lap_idx: std_logic_vector(1 downto 0);
signal soft_reset: std_logic;
signal paused : std_logic;
signal btn0_clean: std_logic;
signal btn1_clean: std_logic;
signal btn2_clean: std_logic;
signal btn3_clean: std_logic;
signal btn3_clean_prev: std_logic;
signal clk10hz: std_logic;
signal clk97khz: std_logic;
signal btn0_prev : std_logic;
signal btn1_prev : std_logic;
signal btn2_prev : std_logic;
signal btn3_prev : std_logic;
signal led7wires : std_logic_vector(7 downto 0);
signal segid : std_logic_vector(3 downto 0);
signal hcsr04trig_val: std_logic;
signal hcsr04echo_clean: std_logic;
signal hcsr04echo_prev: std_logic;
signal cnt12bit: std_logic_vector(11 downto 0);
signal distance : std_logic_vector(11 downto 0);
signal distance_last : std_logic_vector(15 downto 0);
-- {ALTERA_COMPONENTS_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_COMPONENTS_END} DO NOT REMOVE THIS LINE!
begin
-- {ALTERA_INSTANTIATION_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_INSTANTIATION_END} DO NOT REMOVE THIS LINE!
globalcnt_inst : entity lpm.globalcnt PORT MAP (
clock => clk,
cout => clk10hz,
q => cnt
);
clk97khz <= cnt(8);
process(clk97khz) is begin
if (rising_edge(clk97khz)) then
cnt12bit <= cnt12bit + '1';
if (cnt12bit = "000000000000") then
hcsr04trig_val <= '1';
else
hcsr04trig_val <= '0';
end if;
if (hcsr04echo_prev = hcsr04echo) then
hcsr04echo_clean <= hcsr04echo_prev;
end if;
hcsr04echo_prev <= hcsr04echo;
if (hcsr04echo_clean = '1') then
distance <= distance + '1';
else
if (not (distance = "000000000000")) then
distance_last(11 downto 0) <= distance;
end if;
distance <= "000000000000";
end if;
end if;
end process;
distance_last(15 downto 12) <= "1111";
hcsr04trig <= hcsr04trig_val;
stopwatch_inst : entity work.stopwatch PORT MAP (
clk10hz => clk10hz,
paused => paused,
clr => btn1_clean or soft_reset,
d => stopwatch_cur
);
process(clk) is
begin
if ( rising_edge(btn0_clean) ) then
paused <= not paused;
end if;
if ( rising_edge(btn2_clean) ) then
time_idx <= time_idx + "1";
end if;
if ( rising_edge(btn3_clean) ) then
if ( not (stopwatch_cur = 0)) then
if (lap_idx = "00") then
stopwatch_lap0 <= stopwatch_cur;
lap_idx <= "01";
elsif (lap_idx = "01") then
stopwatch_lap1 <= stopwatch_cur;
lap_idx <= "10";
elsif (lap_idx = "10") then
stopwatch_lap2 <= stopwatch_cur;
lap_idx <= "00";
end if;
end if;
end if;
soft_reset <= btn3_clean_prev and btn3_clean;
btn3_clean_prev <= btn3_clean;
end process;
process (cnt(16)) begin
if (rising_edge(cnt(16))) then
btn0_clean <= (not btn0_prev) and (not btn0);
btn0_prev <= btn0;
btn1_clean <= (not btn1_prev) and (not btn1);
btn1_prev <= btn1;
btn2_clean <= (not btn2_prev) and (not btn2);
btn2_prev <= btn2;
btn3_clean <= (not btn3_prev) and (not btn3);
btn3_prev <= btn3;
end if;
end process;
with time_idx select current_time <=
stopwatch_cur when "00",
stopwatch_lap0 when "01",
stopwatch_lap1 when "10",
distance_last when others;
seg7multi_inst : entity work.seg7multi port map (
curnum => cnt(17 downto 16),
data => current_time,
segid => segid,
seg => led7wires
);
CT1 <= segid(0);
CT2 <= segid(1);
CT3 <= segid(2);
CT4 <= segid(3);
A <= led7wires(0);
B <= led7wires(1);
C <= led7wires(2);
D <= led7wires(3);
E <= led7wires(4);
F <= led7wires(5);
G <= led7wires(6);
DP<= led7wires(7);
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity cpu_engine is
PORT( -- WISHBONE interface
CLK_I : in std_logic;
DAT_I : in std_logic_vector( 7 downto 0);
DAT_O : out std_logic_vector( 7 downto 0);
RST_I : in std_logic;
ACK_I : in std_logic;
ADR_O : out std_logic_vector(15 downto 0);
CYC_O : out std_logic;
STB_O : out std_logic;
TGA_O : out std_logic_vector( 0 downto 0); -- '1' if I/O
WE_O : out std_logic;
INT : in std_logic;
HALT : out std_logic;
-- debug signals
--
Q_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector( 7 downto 0);
Q_CAT : out op_category;
Q_IMM : out std_logic_vector(15 downto 0);
Q_CYC : out cycle;
-- select signals
Q_SX : out std_logic_vector(1 downto 0);
Q_SY : out std_logic_vector(3 downto 0);
Q_OP : out std_logic_vector(4 downto 0);
Q_SA : out std_logic_vector(4 downto 0);
Q_SMQ : out std_logic;
-- write enable/select signal
Q_WE_RR : out std_logic;
Q_WE_LL : out std_logic;
Q_WE_SP : out SP_OP;
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
end cpu_engine;
architecture Behavioral of cpu_engine is
-- Unfortunately, the on-chip memory needs a clock to read data.
-- Therefore we cannot make it wishbone compliant without a speed penalty.
-- We avoid this problem by making the on-chip memory part of the CPU.
-- However, as a consequence, you cannot DMA to the on-chip memory.
--
-- The on-chip memory is 8K, so that you can run a test SoC without external
-- memory. For bigger applications, you should use external ROM and RAM and
-- remove the internal memory entirely (setting EXTERN accordingly).
--
COMPONENT memory
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CE : IN std_logic;
PC : IN std_logic_vector(15 downto 0);
ADR : IN std_logic_vector(15 downto 0);
WR : IN std_logic;
WDAT : IN std_logic_vector(7 downto 0);
OPC : OUT std_logic_vector(7 downto 0);
RDAT : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT opcode_fetch
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
PC_OP : IN std_logic_vector(2 downto 0);
JDATA : IN std_logic_vector(15 downto 0);
RR : IN std_logic_vector(15 downto 0);
RDATA : IN std_logic_vector(7 downto 0);
PC : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT opcode_decoder
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
OPCODE : in std_logic_vector(7 downto 0);
OP_CYC : in cycle;
INT : in std_logic;
RRZ : in std_logic;
OP_CAT : out op_category;
-- select signals
D_SX : out std_logic_vector(1 downto 0); -- ALU select X
D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
D_OP : out std_logic_vector(4 downto 0); -- ALU operation
D_SA : out std_logic_vector(4 downto 0); -- select address
D_SMQ : out std_logic;
-- write enable/select signal
D_WE_RR : out std_logic;
D_WE_LL : out std_logic;
D_WE_SP : out SP_OP;
D_RD_O : out std_logic;
D_WE_O : out std_logic;
D_LOCK : out std_logic;
-- input/output
D_IO : out std_logic;
PC_OP : out std_logic_vector(2 downto 0);
LAST_M : out std_logic;
HLT : out std_logic
);
END COMPONENT;
COMPONENT data_core
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
-- select signals
SX : in std_logic_vector( 1 downto 0);
SY : in std_logic_vector( 3 downto 0);
OP : in std_logic_vector( 4 downto 0); -- alu op
PC : in std_logic_vector(15 downto 0); -- PC
QU : in std_logic_vector( 3 downto 0); -- quick operand
SA : in std_logic_vector(4 downto 0); -- select address
SMQ : in std_logic; -- select MQ (H/L)
-- write enable/select signal
WE_RR : in std_logic;
WE_LL : in std_logic;
WE_SP : in SP_OP;
IMM : in std_logic_vector(15 downto 0); -- immediate data
RDAT : in std_logic_vector( 7 downto 0); -- data from memory/IO
ADR : out std_logic_vector(15 downto 0); -- memory/IO address
MQ : out std_logic_vector( 7 downto 0); -- data to memory/IO
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
END COMPONENT;
-- global signals
signal CE : std_logic;
signal T2 : std_logic;
-- memory signals
signal WDAT : std_logic_vector(7 downto 0);
signal RDAT : std_logic_vector(7 downto 0);
signal M_PC : std_logic_vector(15 downto 0);
signal M_OPC : std_logic_vector(7 downto 0);
-- decoder signals
--
signal D_CAT : op_category;
signal D_OPC : std_logic_vector(7 downto 0);
signal D_CYC : cycle;
signal D_PC : std_logic_vector(15 downto 0); -- debug signal
signal D_PC_OP : std_logic_vector( 2 downto 0);
signal D_LAST_M : std_logic;
signal D_IO : std_logic;
-- select signals
signal D_SX : std_logic_vector(1 downto 0);
signal D_SY : std_logic_vector(3 downto 0);
signal D_OP : std_logic_vector(4 downto 0);
signal D_SA : std_logic_vector(4 downto 0);
signal D_SMQ : std_logic;
-- write enable/select signals
signal D_WE_RR : std_logic;
signal D_WE_LL : std_logic;
signal D_WE_SP : SP_OP;
signal D_RD_O : std_logic;
signal D_WE_O : std_logic;
signal D_LOCK : std_logic; -- first cycle
signal LM_WE : std_logic;
-- core signals
--
signal C_IMM : std_logic_vector(15 downto 0);
signal ADR : std_logic_vector(15 downto 0);
signal C_CYC : cycle; -- debug signal
signal C_PC : std_logic_vector(15 downto 0); -- debug signal
signal C_OPC : std_logic_vector( 7 downto 0); -- debug signal
signal C_RR : std_logic_vector(15 downto 0);
signal RRZ : std_logic;
signal OC_JD : std_logic_vector(15 downto 0);
signal C_MQ : std_logic_vector(7 downto 0);
-- select signals
signal C_SX : std_logic_vector(1 downto 0);
signal C_SY : std_logic_vector(3 downto 0);
signal C_OP : std_logic_vector(4 downto 0);
signal C_SA : std_logic_vector(4 downto 0);
signal C_SMQ : std_logic;
signal C_WE_RR : std_logic;
signal C_WE_LL : std_logic;
signal C_WE_SP : SP_OP;
signal XM_OPC : std_logic_vector(7 downto 0);
signal LM_OPC : std_logic_vector(7 downto 0);
signal LM_RDAT : std_logic_vector(7 downto 0);
signal XM_RDAT : std_logic_vector(7 downto 0);
signal C_IO : std_logic;
signal C_RD_O : std_logic;
signal C_WE_O : std_logic;
-- signals to remember, whether the previous read cycle
-- addressed internal memory or external memory
--
signal OPCS : std_logic; -- '1' if opcode from external memory
signal RDATS : std_logic; -- '1' if data from external memory
signal EXTERN : std_logic; -- '1' if opcode or data from external memory
begin
memo: memory
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CE => CE,
-- read in T1
PC => M_PC,
OPC => LM_OPC,
-- read or written in T2
ADR => ADR,
WR => LM_WE,
WDAT => WDAT,
RDAT => LM_RDAT
);
ocf: opcode_fetch
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
PC_OP => D_PC_OP,
JDATA => OC_JD,
RR => C_RR,
RDATA => RDAT,
PC => M_PC
);
opdec: opcode_decoder
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
OPCODE => D_OPC,
OP_CYC => D_CYC,
INT => INT,
RRZ => RRZ,
OP_CAT => D_CAT,
-- select signals
D_SX => D_SX,
D_SY => D_SY,
D_OP => D_OP,
D_SA => D_SA,
D_SMQ => D_SMQ,
-- write enable/select signal
D_WE_RR => D_WE_RR,
D_WE_LL => D_WE_LL,
D_WE_SP => D_WE_SP,
D_RD_O => D_RD_O,
D_WE_O => D_WE_O,
D_LOCK => D_LOCK,
D_IO => D_IO,
PC_OP => D_PC_OP,
LAST_M => D_LAST_M,
HLT => HALT
);
dcore: data_core
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
-- select signals
SX => C_SX,
SY => C_SY,
OP => C_OP,
PC => C_PC,
QU => C_OPC(3 downto 0),
SA => C_SA,
SMQ => C_SMQ,
-- write enable/select signal
WE_RR => C_WE_RR,
WE_LL => C_WE_LL,
WE_SP => C_WE_SP,
IMM => C_IMM,
RDAT => RDAT,
ADR => ADR,
MQ => WDAT,
Q_RR => C_RR,
Q_LL => Q_LL,
Q_SP => Q_SP
);
CE <= ACK_I or not EXTERN;
TGA_O(0) <= T2 and C_IO;
WE_O <= T2 and C_WE_O;
STB_O <= EXTERN;
CYC_O <= EXTERN;
Q_RR <= C_RR;
RRZ <= '1' when (C_RR = X"0000") else '0';
OC_JD <= M_OPC & C_IMM(7 downto 0);
Q_PC <= C_PC;
Q_OPC <= C_OPC;
Q_CYC <= C_CYC;
Q_IMM <= C_IMM;
-- select signals
Q_SX <= C_SX;
Q_SY <= C_SY;
Q_OP <= C_OP;
Q_SA <= C_SA;
Q_SMQ <= C_SMQ;
-- write enable/select signal (debug)
Q_WE_RR <= C_WE_RR;
Q_WE_LL <= C_WE_LL;
Q_WE_SP <= C_WE_SP;
DAT_O <= WDAT;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then T2 <= '0';
else T2 <= not T2;
end if;
end if;
end process;
process(T2, M_PC, ADR, C_IO)
begin
if (T2 = '0') then -- opcode fetch
EXTERN <= M_PC(15) or M_PC(14) or M_PC(13); -- 8Kx8 internal memory
-- A EXTERN <= M_PC(15) or M_PC(14) or M_PC(13) or -- 512x8 internal memory
-- A M_PC(12) or M_PC(11) or M_PC(10) or M_PC(9)
-- B EXTERN <= '1'; -- no internal memory
else -- data or I/O
EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 8Kx8 internal memory
-- A EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 512x8 internal memory
-- A ADR(12) or ADR(11) or ADR(10) or ADR(9) or
-- B EXTERN <= ('1' or -- no internal memory
C_IO) and (C_RD_O or C_WE_O);
end if;
end process;
-- remember whether access is to internal or to external (incl I/O) memory.
-- clock read data to XM_OPCODE in T1 or to XM_RDAT in T2
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '0') then
OPCS <= EXTERN;
XM_OPC <= DAT_I;
else
RDATS <= EXTERN;
XM_RDAT <= DAT_I;
end if;
end if;
end process;
M_OPC <= LM_OPC when (OPCS = '0') else XM_OPC;
ADR_O <= M_PC when (T2 = '0') else ADR;
RDAT <= LM_RDAT when (RDATS = '0') else XM_RDAT;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then
D_PC <= X"0000";
D_OPC <= X"01";
D_CYC <= M1;
C_PC <= X"0000";
C_OPC <= X"01";
C_CYC <= M1;
C_IMM <= X"FFFF";
C_SX <= "00";
C_SY <= "0000";
C_OP <= "00000";
C_SA <= "00000";
C_SMQ <= '0';
C_WE_RR <= '0';
C_WE_LL <= '0';
C_WE_SP <= SP_NOP;
C_IO <= '0';
C_RD_O <= '0';
C_WE_O <= '0';
LM_WE <= '0';
elsif (CE = '1' and T2 = '1') then
C_CYC <= D_CYC;
Q_CAT <= D_CAT;
C_PC <= D_PC;
C_OPC <= D_OPC;
C_SX <= D_SX;
C_SY <= D_SY;
C_OP <= D_OP;
C_SA <= D_SA;
C_SMQ <= D_SMQ;
C_WE_RR <= D_WE_RR;
C_WE_LL <= D_WE_LL;
C_WE_SP <= D_WE_SP;
C_IO <= D_IO;
C_RD_O <= D_RD_O;
C_WE_O <= D_WE_O;
LM_WE <= D_WE_O and not D_IO;
if (D_LAST_M = '1') then -- D goes to M1
-- signals valid for entire opcode...
D_OPC <= M_OPC;
D_PC <= M_PC;
D_CYC <= M1;
else
case D_CYC is
when M1 => D_CYC <= M2; -- C goes to M1
C_IMM <= X"00" & M_OPC;
when M2 => D_CYC <= M3;
C_IMM(15 downto 8) <= M_OPC;
when M3 => D_CYC <= M4;
when M4 => D_CYC <= M5;
when M5 => D_CYC <= M1;
end case;
end if;
end if;
end if;
end process;
end Behavioral;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_cmd_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
MASTER_TRANSMIT_AND_RECEIVE, MASTER_TRANSMIT_AND_CHECK, MASTER_TRANSMIT_ONLY, MASTER_RECEIVE_ONLY, MASTER_CHECK_ONLY,
SLAVE_TRANSMIT_AND_RECEIVE, SLAVE_TRANSMIT_AND_CHECK, SLAVE_TRANSMIT_ONLY, SLAVE_RECEIVE_ONLY, SLAVE_CHECK_ONLY);
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32;
--===============================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--===============================================================================================
type t_vvc_cmd_record is record
-- VVC dedicated fields
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
data_exp : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
-- Common VVC fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory)
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
data => (others => '0'),
data_exp => (others => '0'),
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => failure,
delay => 0 ns,
quietness => NON_QUIET
);
--===============================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--===============================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>, natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
--=================================================================================================
--=================================================================================================
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity DRAM_4M_by_4 is
port ( a : in std_logic_vector(0 to 10);
d : inout std_logic_vector(0 to 3);
cs, we, ras, cas : in std_logic );
end entity DRAM_4M_by_4;
architecture chip_function of DRAM_4M_by_4 is
begin
d <= (others => 'Z');
end architecture chip_function;
-- code from book
library chip_lib; use chip_lib.all;
configuration down_to_chips of memory_board is
for chip_level
for bank_array
for nibble_array
for a_DRAM : DRAM
use entity DRAM_4M_by_4(chip_function);
end for;
end for;
end for;
-- . . . -- configurations of other component instances
end for;
end configuration down_to_chips;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity DRAM_4M_by_4 is
port ( a : in std_logic_vector(0 to 10);
d : inout std_logic_vector(0 to 3);
cs, we, ras, cas : in std_logic );
end entity DRAM_4M_by_4;
architecture chip_function of DRAM_4M_by_4 is
begin
d <= (others => 'Z');
end architecture chip_function;
-- code from book
library chip_lib; use chip_lib.all;
configuration down_to_chips of memory_board is
for chip_level
for bank_array
for nibble_array
for a_DRAM : DRAM
use entity DRAM_4M_by_4(chip_function);
end for;
end for;
end for;
-- . . . -- configurations of other component instances
end for;
end configuration down_to_chips;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity DRAM_4M_by_4 is
port ( a : in std_logic_vector(0 to 10);
d : inout std_logic_vector(0 to 3);
cs, we, ras, cas : in std_logic );
end entity DRAM_4M_by_4;
architecture chip_function of DRAM_4M_by_4 is
begin
d <= (others => 'Z');
end architecture chip_function;
-- code from book
library chip_lib; use chip_lib.all;
configuration down_to_chips of memory_board is
for chip_level
for bank_array
for nibble_array
for a_DRAM : DRAM
use entity DRAM_4M_by_4(chip_function);
end for;
end for;
end for;
-- . . . -- configurations of other component instances
end for;
end configuration down_to_chips;
-- end code from book
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "spi_test_top"
-- Project :
-------------------------------------------------------------------------------
-- File : spi_test_top_tb.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-10-24
-- Last update: 2014-10-27
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-10-24 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity spi_test_top_tb is
end entity spi_test_top_tb;
-------------------------------------------------------------------------------
architecture test of spi_test_top_tb is
constant input_freq : real := 2.0e08;
constant clock_period : time := 1.0 sec /(input_freq);
constant c_width : positive := 16;
-- component ports
signal sys_clk_p_i : std_logic;
signal sys_clk_n_i : std_logic;
signal on_sw_i : std_logic;
signal rst_i : std_logic;
signal spi_sck : std_logic;
signal spi_mosi : std_logic;
signal spi_miso : std_logic;
signal spi_ssel : std_logic;
signal nok_o : std_logic_vector(c_width-1 downto 0);
signal ok_o : std_logic_vector(c_width-1 downto 0);
component spi_test_top is
port (
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
on_sw_i : in std_logic;
rst_i : in std_logic;
spi_sck_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
spi_ssel_o : out std_logic;
spi_sck_i : in std_logic;
spi_mosi_i : in std_logic;
spi_miso_o : out std_logic;
spi_ssel_i : in std_logic;
nok_o : out std_logic_vector(c_width-1 downto 0);
ok_o : out std_logic_vector(c_width-1 downto 0));
end component spi_test_top;
begin -- architecture test
clk_gen : process
begin
sys_clk_n_i <= '0';
sys_clk_p_i <= '1';
wait for clock_period/2.0;
sys_clk_n_i <= '1';
sys_clk_p_i <= '0';
wait for clock_period/2.0;
end process;
on_sw_i <= '1';
rst_i <= '0';
-- component instantiation
uut : spi_test_top
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
spi_sck_o => spi_sck,
spi_mosi_o => spi_mosi,
spi_miso_i => spi_miso,
spi_ssel_o => spi_ssel,
spi_sck_i => spi_sck,
spi_mosi_i => spi_mosi,
spi_miso_o => spi_miso,
spi_ssel_i => spi_ssel,
nok_o => nok_o,
ok_o => ok_o,
on_sw_i => on_sw_i,
rst_i => rst_i);
end architecture test;
|
entity bounds2 is
end entity;
architecture test of bounds2 is
begin
asssignment_delays: block
signal b1,b2,b3,b4,b5,b6,b7 : boolean;
begin
b1 <= true; -- OK
b2 <= true after 10 ns; -- OK
b3 <= true after 0 ns; -- OK
b4 <= true after -1 ns; -- Error
process
begin
b5 <= true; -- OK
b5 <= true after 0 ns; -- OK
b5 <= true after 1 fs; -- OK
b5 <= true after -1 fs; -- Error
wait;
end process;
b6 <= true after -10 ns when now = 5 ns else false;
b7 <= true when now = 1 ns else false after -10 ns;
end block;
rejection_limits: block
signal b1,b2,b3 : boolean;
begin
b1 <= reject 10 ns inertial true after 10 ns; -- OK
b2 <= reject -10 ns inertial true; -- Error
b3 <= reject 10 ns inertial true after 5 ns; -- Error
end block;
process
begin
wait for -10 ns; -- Error
wait;
end process;
default_values: block
type r is range 0 to 1;
constant ok1 : integer range 0 to 1 := 1; -- OK
constant ok2 : character range 'a' to 'z' := 'b'; -- OK
constant ok3 : real range 0.0 to 1.0 := 0.0; -- OK
constant ok4 : time range 10 ns to 20 ns := 10 ns; -- OK
constant ok5 : r := 0; -- OK
signal s : integer range 0 to 9 := 20; -- Error
constant c1 : character range 'a' to 'z' := 'Z'; -- Error
shared variable v : real range 0.0 to 5.0 := 10.0; -- Error
constant t : time range 10 ns to 10 us := 0 fs; -- Error
constant c2 : r := 10; -- Error
subtype subint is integer range 1 to 10;
procedure test(a : subint := 30) is
begin
end procedure;
function test(a : character range 'a' to 'b' := 'c') return integer is
begin
return 1;
end function;
component comp is
generic (
g2 : integer range 10 downto 0 := 20
);
port (
p2 : in integer range 0 to 1 := 2
);
end component;
begin
process is
variable v2 : real range 0.0 to 5.0 := 5.1; -- Error
begin
end process;
end block;
ascending_time: block
signal s : integer;
signal del : time;
begin
process
begin
s <= 0 after 10 ns, 1 after 11 ns; -- OK
s <= 0, 1 after 1 ns; -- OK
s <= 10 after del; -- OK
s <= 10 after del, 20 after del + 1 ns; -- OK
s <= 0, 1; -- Error
s <= 0 after 1 ns, 1; -- Error
s <= 0 after 2 ns, 1 after 1 ns; -- Error
s <= 0 after 1 ns, 1 after del, 2; -- Error
s <= 1 after del, 2; -- Error
wait;
end process;
end block;
textio1: block is
function unit_string (unit : time) return string is
begin
if unit = fs then -- OK
return " fs";
elsif unit = ps then
return " ps";
elsif unit = ns then
return " ns";
else
report "invalid unit " & time'image(unit);
end if;
end function;
begin
end block;
end architecture;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY hex2seg_tb IS
END hex2seg_tb;
ARCHITECTURE behavior OF hex2seg_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT hex2seg
PORT(
clk : IN std_logic;
en : in std_logic;
hex : IN std_logic_vector(3 downto 0);
seg : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal en: std_logic := '0';
signal hex : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal seg : std_logic_vector(6 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: hex2seg PORT MAP (
clk => clk,
en => en,
hex => hex,
seg => seg
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
--Test if nothing happens if enabled is on '0'
en <= '0';
hex <= "0001";
wait for clk_period*10;
-- Test decoding of hex numbers 0-F
en <= '1';
hex <= "0000";
wait for clk_period*10;
hex <= "0001";
wait for clk_period*10;
hex <= "0010";
wait for clk_period*10;
hex <= "0011";
wait for clk_period*10;
hex <= "0100";
wait for clk_period*10;
hex <= "0101";
wait for clk_period*10;
hex <= "0110";
wait for clk_period*10;
hex <= "0111";
wait for clk_period*10;
hex <= "1000";
wait for clk_period*10;
hex <= "1001";
wait for clk_period*10;
hex <= "1010";
wait for clk_period*10;
hex <= "1011";
wait for clk_period*10;
hex <= "1100";
wait for clk_period*10;
hex <= "1101";
wait for clk_period*10;
hex <= "1110";
wait for clk_period*10;
hex <= "1111";
wait;
end process;
END;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4720)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4720)
`protect data_block
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`protect begin_protected
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|
`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4720)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4720)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4720)
`protect data_block
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`protect end_protected
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_10a is
end entity inline_10a;
architecture test of inline_10a is
constant R : real := 10_000.0;
constant R1 : real := 10_000.0;
constant R2 : real := 10_000.0;
-- code from book
nature electrical_bus is
record
strobe: electrical;
databus : electrical_vector(0 to 7);
end record;
-- end code from book
begin
block_1 : block is
-- code from book
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
-- end code from book
begin
-- code from book
bus_v == bus_i * R;
-- end code from book
end block block_1;
block_2 : block is
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
begin
-- code from book
bus_v.strobe == bus_i.strobe * R;
bus_v.databus(0) == bus_i.databus(0) * R;
bus_v.databus(1) == bus_i.databus(1) * R;
-- ...
-- not in book
bus_v.databus(2) == bus_i.databus(2) * R;
bus_v.databus(3) == bus_i.databus(3) * R;
bus_v.databus(4) == bus_i.databus(4) * R;
bus_v.databus(5) == bus_i.databus(5) * R;
bus_v.databus(6) == bus_i.databus(6) * R;
-- end not in book
bus_v.databus(7) == bus_i.databus(7) * R;
-- end code from book
end block block_2;
block_3 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v == i * R;
-- end code from book
end block block_3;
block_4 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v / R == i;
-- end code from book
end block block_4;
block_5 : block is
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
begin
-- code from book
bus_v.strobe == bus_i.strobe * R;
bus_v.databus(0) == bus_i.databus(0) * R;
-- end code from book
bus_v.databus(1) == bus_i.databus(1) * R;
bus_v.databus(2) == bus_i.databus(2) * R;
bus_v.databus(3) == bus_i.databus(3) * R;
bus_v.databus(4) == bus_i.databus(4) * R;
bus_v.databus(5) == bus_i.databus(5) * R;
bus_v.databus(6) == bus_i.databus(6) * R;
bus_v.databus(7) == bus_i.databus(7) * R;
end block block_5;
block_6 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2; -- illegal
-- end code from book
end block block_6;
block_7 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2 tolerance "current_tolerance";
-- end code from book
end block block_7;
block_8 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2 tolerance i2'tolerance;
-- end code from book
end block block_8;
block_9 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v == i * R tolerance i'tolerance;
-- end code from book
end block block_9;
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_10a is
end entity inline_10a;
architecture test of inline_10a is
constant R : real := 10_000.0;
constant R1 : real := 10_000.0;
constant R2 : real := 10_000.0;
-- code from book
nature electrical_bus is
record
strobe: electrical;
databus : electrical_vector(0 to 7);
end record;
-- end code from book
begin
block_1 : block is
-- code from book
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
-- end code from book
begin
-- code from book
bus_v == bus_i * R;
-- end code from book
end block block_1;
block_2 : block is
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
begin
-- code from book
bus_v.strobe == bus_i.strobe * R;
bus_v.databus(0) == bus_i.databus(0) * R;
bus_v.databus(1) == bus_i.databus(1) * R;
-- ...
-- not in book
bus_v.databus(2) == bus_i.databus(2) * R;
bus_v.databus(3) == bus_i.databus(3) * R;
bus_v.databus(4) == bus_i.databus(4) * R;
bus_v.databus(5) == bus_i.databus(5) * R;
bus_v.databus(6) == bus_i.databus(6) * R;
-- end not in book
bus_v.databus(7) == bus_i.databus(7) * R;
-- end code from book
end block block_2;
block_3 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v == i * R;
-- end code from book
end block block_3;
block_4 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v / R == i;
-- end code from book
end block block_4;
block_5 : block is
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
begin
-- code from book
bus_v.strobe == bus_i.strobe * R;
bus_v.databus(0) == bus_i.databus(0) * R;
-- end code from book
bus_v.databus(1) == bus_i.databus(1) * R;
bus_v.databus(2) == bus_i.databus(2) * R;
bus_v.databus(3) == bus_i.databus(3) * R;
bus_v.databus(4) == bus_i.databus(4) * R;
bus_v.databus(5) == bus_i.databus(5) * R;
bus_v.databus(6) == bus_i.databus(6) * R;
bus_v.databus(7) == bus_i.databus(7) * R;
end block block_5;
block_6 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2; -- illegal
-- end code from book
end block block_6;
block_7 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2 tolerance "current_tolerance";
-- end code from book
end block block_7;
block_8 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2 tolerance i2'tolerance;
-- end code from book
end block block_8;
block_9 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v == i * R tolerance i'tolerance;
-- end code from book
end block block_9;
begin
end architecture test;
|
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
end STD_LOGIC_TEXTIO; |
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
end STD_LOGIC_TEXTIO; |
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
end STD_LOGIC_TEXTIO; |
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
end STD_LOGIC_TEXTIO; |
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
end STD_LOGIC_TEXTIO; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc4.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p04n01i00004ent IS
END c04s01b00x00p04n01i00004ent;
ARCHITECTURE c04s01b00x00p04n01i00004arch OF c04s01b00x00p04n01i00004ent IS
-- a constrained array declaration
type my_word is array (one => 0 to 31) of bit; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s01b00x00p04n01i00004 - Syntax error in type declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p04n01i00004arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc4.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p04n01i00004ent IS
END c04s01b00x00p04n01i00004ent;
ARCHITECTURE c04s01b00x00p04n01i00004arch OF c04s01b00x00p04n01i00004ent IS
-- a constrained array declaration
type my_word is array (one => 0 to 31) of bit; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s01b00x00p04n01i00004 - Syntax error in type declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p04n01i00004arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc4.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p04n01i00004ent IS
END c04s01b00x00p04n01i00004ent;
ARCHITECTURE c04s01b00x00p04n01i00004arch OF c04s01b00x00p04n01i00004ent IS
-- a constrained array declaration
type my_word is array (one => 0 to 31) of bit; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s01b00x00p04n01i00004 - Syntax error in type declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p04n01i00004arch;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ac
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ac-rtl-a.vhd,v 1.1 2006/04/10 15:42:05 wig Exp $
-- $Date: 2006/04/10 15:42:05 $
-- $Log: ent_ac-rtl-a.vhd,v $
-- Revision 1.1 2006/04/10 15:42:05 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ac
--
architecture rtl of ent_ac is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fx2_usb is
Port (
clk_i : in std_logic;
rst_i : in std_logic;
fx2_wr_full_i : in std_logic;
fx2_rd_empty_i : in std_logic;
fx2_data_io : inout std_logic_vector(7 downto 0);
fx2_clk_i : in std_logic;
fx2_slcs_o : out std_logic;
fx2_slrd_o : out std_logic;
fx2_sloe_o : out std_logic;
fx2_slwr_o : out std_logic;
fx2_pktend_o : out std_logic;
fx2_fifo_addr_o : out std_logic_vector(1 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
wr_full : out std_logic;
rd_empty : out std_logic;
pktend_i : in std_logic;
sync : out std_logic
);
end fx2_usb;
architecture Behavioral of fx2_usb is
component tiny_fifo
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;
signal tx_dout : std_logic_vector(7 downto 0);
signal tx_empty, rx_full, rx_empty : std_logic;
signal tx_rd_en, rx_wr_en : std_logic;
type mode is (IDLE, RD, DELAY, PKTEND);
signal state : mode;
signal tx_fifo_selected : std_logic;
signal pktend_r1 : std_logic;
signal pktend_r2 : std_logic;
signal pktend_r3 : std_logic;
signal pktend_pending : std_logic;
signal pktend_delay : integer;
signal fx2_rx_empty_r1 : std_logic;
signal fx2_rx_empty_r2 : std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
sync <= '0';
else
sync <= '0';
fx2_rx_empty_r1 <= fx2_rd_empty_i;
fx2_rx_empty_r2 <= fx2_rx_empty_r1;
if fx2_rx_empty_r2 = '0' and rx_empty = '1' then
sync <= '1';
end if;
end if;
end if;
end process;
fx2_slcs_o <= '0';
fx2_sloe_o <= '0' when tx_fifo_selected = '0' else '1';
fx2_data_io <= tx_dout when tx_fifo_selected = '1' else (others => 'Z');
fx2_fifo_addr_o <= "10" when tx_fifo_selected = '1' else "00";
process(fx2_clk_i)
begin
if rising_edge(fx2_clk_i) then
fx2_slwr_o <= not tx_rd_en;
fx2_slrd_o <= '1';
fx2_pktend_o <= '1';
pktend_r1 <= pktend_i;
pktend_r2 <= pktend_r1;
pktend_r3 <= pktend_r2;
if pktend_r3 = '0' and pktend_r2 = '1' then
pktend_pending <= '1';
end if;
rx_wr_en <= '0';
tx_rd_en <= '0';
if rst_i = '1' then
tx_fifo_selected <= '0';
state <= IDLE;
pktend_pending <= '0';
else
-- always go back to idle state
state <= IDLE;
case state is
when IDLE =>
-- pktend?
if fx2_wr_full_i = '1' and tx_empty = '1' and pktend_pending = '1' then
pktend_pending <= '0';
pktend_delay <= 4;
tx_fifo_selected <= '1';
state <= PKTEND;
-- send
elsif fx2_wr_full_i = '1' and tx_empty = '0' and tx_fifo_selected = '1' then
tx_rd_en <= '1';
state <= DELAY;
-- receive
elsif fx2_rd_empty_i = '1' and rx_full = '0' and tx_fifo_selected = '0' then
rx_wr_en <= '1';
state <= RD;
-- switch to sending
elsif fx2_wr_full_i = '1' and tx_empty = '0' then
tx_fifo_selected <= '1';
state <= DELAY;
-- switch to receiving
elsif fx2_rd_empty_i = '1' and rx_full = '0' then
tx_fifo_selected <= '0';
state <= DELAY;
end if;
when RD =>
fx2_slrd_o <= '0';
when DELAY => null;
when PKTEND =>
state <= PKTEND;
pktend_delay <= pktend_delay - 1;
if pktend_delay = 0 then
fx2_pktend_o <= '0';
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
rx_fifo : tiny_fifo
port map (
din => fx2_data_io,
rd_clk => clk_i,
rd_en => rd_en,
rst => rst_i,
wr_clk => fx2_clk_i,
wr_en => rx_wr_en,
dout => dout,
empty => rx_empty,
full => rx_full);
rd_empty <= rx_empty;
tx_fifo : tiny_fifo
port map (
din => din,
rd_clk => fx2_clk_i,
rd_en => tx_rd_en,
rst => rst_i,
wr_clk => clk_i,
wr_en => wr_en,
dout => tx_dout,
empty => tx_empty,
full => wr_full);
end Behavioral;
|
------------------------------------------------------------------------------
--
-- \file xps_osif.vhd
--
-- Wrapper to connect OSIF to PLBv46
--
-- Mostly generated using Xilinx tools.
--
-- \author Enno Luebbers <luebbers@reconos.de>
-- \date 11.08.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Original Xilinx header follows:
--
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: xps_osif.vhd
-- Version: 2.01.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed May 27 14:11:08 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_master_burst_v1_01_a;
use plbv46_master_burst_v1_01_a.plbv46_master_burst;
library osif_core_v2_01_a;
use osif_core_v2_01_a.all;
library xps_osif_v2_01_a;
use xps_osif_v2_01_a.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
-- C_MEM0_BASEADDR -- User memory space 0 base address
-- C_MEM0_HIGHADDR -- User memory space 0 high address
-- C_MEM1_BASEADDR -- User memory space 1 base address
-- C_MEM1_HIGHADDR -- User memory space 1 high address
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity xps_osif is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
C_BURST_AWIDTH : integer := 13; -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
C_FIFO_DWIDTH : integer := 32;
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_DCR_ILA : integer := 0;
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
-- C_BASEADDR : std_logic_vector := X"FFFFFFFF";
-- C_HIGHADDR : std_logic_vector := X"00000000";
-- C_SPLB_AWIDTH : integer := 32;
-- C_SPLB_DWIDTH : integer := 128;
-- C_SPLB_NUM_MASTERS : integer := 8;
-- C_SPLB_MID_WIDTH : integer := 3;
-- C_SPLB_NATIVE_DWIDTH : integer := 32;
-- C_SPLB_P2P : integer := 0;
-- C_SPLB_SUPPORT_BURSTS : integer := 0;
-- C_SPLB_SMALLEST_MASTER : integer := 32;
-- C_SPLB_CLK_PERIOD_PS : integer := 10000;
-- C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 64;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
-- C_MEM0_BASEADDR : std_logic_vector := X"FFFFFFFF";
-- C_MEM0_HIGHADDR : std_logic_vector := X"00000000";
-- C_MEM1_BASEADDR : std_logic_vector := X"FFFFFFFF";
-- C_MEM1_HIGHADDR : std_logic_vector := X"00000000"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
sys_clk : in std_logic;
sys_reset : in std_logic;
interrupt : out std_logic;
busy : out std_logic;
blocking : out std_logic;
-- task interface
task_clk : out std_logic;
task_reset : out std_logic;
osif_os2task_vec : out std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
osif_task2os_vec : in std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
-- burst mem interface
burstAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
burstWrData : out std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
burstRdData : in std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
burstWE : out std_logic;
burstBE : out std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
-- FIFO access signals
o_fifo_clk : out std_logic;
o_fifo_reset : out std_logic;
-- left (read) FIFO
o_fifo_read_en : out std_logic;
i_fifo_read_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_read_ready : in std_logic;
-- right (write) FIFO
o_fifo_write_en : out std_logic;
o_fifo_write_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_write_ready : in std_logic;
-- bus macro control
bmEnable : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DCR Bus protocol ports
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic;
i_dcrICON : in std_logic_vector(35 downto 0); -- chipscope
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
-- sys_clk : in std_logic;
-- sys_reset : in std_logic;
-- SPLB_Clk : in std_logic;
-- SPLB_Rst : in std_logic;
-- PLB_ABus : in std_logic_vector(0 to 31);
-- PLB_UABus : in std_logic_vector(0 to 31);
-- PLB_PAValid : in std_logic;
-- PLB_SAValid : in std_logic;
-- PLB_rdPrim : in std_logic;
-- PLB_wrPrim : in std_logic;
-- PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
-- PLB_abort : in std_logic;
-- PLB_busLock : in std_logic;
-- PLB_RNW : in std_logic;
-- PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
-- PLB_MSize : in std_logic_vector(0 to 1);
-- PLB_size : in std_logic_vector(0 to 3);
-- PLB_type : in std_logic_vector(0 to 2);
-- PLB_lockErr : in std_logic;
-- PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
-- PLB_wrBurst : in std_logic;
-- PLB_rdBurst : in std_logic;
-- PLB_wrPendReq : in std_logic;
-- PLB_rdPendReq : in std_logic;
-- PLB_wrPendPri : in std_logic_vector(0 to 1);
-- PLB_rdPendPri : in std_logic_vector(0 to 1);
-- PLB_reqPri : in std_logic_vector(0 to 1);
-- PLB_TAttribute : in std_logic_vector(0 to 15);
-- Sl_addrAck : out std_logic;
-- Sl_SSize : out std_logic_vector(0 to 1);
-- Sl_wait : out std_logic;
-- Sl_rearbitrate : out std_logic;
-- Sl_wrDAck : out std_logic;
-- Sl_wrComp : out std_logic;
-- Sl_wrBTerm : out std_logic;
-- Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
-- Sl_rdWdAddr : out std_logic_vector(0 to 3);
-- Sl_rdDAck : out std_logic;
-- Sl_rdComp : out std_logic;
-- Sl_rdBTerm : out std_logic;
-- Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
-- attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of MPLB_Clk : signal is "CLK";
-- attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of MPLB_Rst : signal is "RST";
end entity xps_osif;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of xps_osif is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
--constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
--constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
--constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
--USER_LOGIC needs this parameter
--constant BURST_BASEADDR : std_logic_vector := C_BASEADDR or X"00004000";
--constant BURST_HIGHADDR : std_logic_vector := C_BASEADDR or X"00007FFF";
--constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
--(
--ZERO_ADDR_PAD & USER_MST_BASEADDR, -- user logic master space base address
--ZERO_ADDR_PAD & USER_MST_HIGHADDR, -- user logic master space high address
--ZERO_ADDR_PAD & BURST_BASEADDR, -- user logic memory space 0 base address
--ZERO_ADDR_PAD & BURST_HIGHADDR -- user logic memory space 0 high address
--ZERO_ADDR_PAD & C_MEM1_BASEADDR, -- user logic memory space 1 base address
--ZERO_ADDR_PAD & C_MEM1_HIGHADDR -- user logic memory space 1 high address
-- );
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
-- constant USER_MST_NUM_REG : integer := 1;
-- constant USER_NUM_REG : integer := USER_MST_NUM_REG;
-- constant USER_NUM_MEM : integer := 1;
-- constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
-- (
--0 => pad_power2(USER_MST_NUM_REG), -- number of ce for user logic master space
-- 0 => 1
--1 => 1, -- number of ce for user logic memory space 0 (always 1 chip enable)
--2 => 1 -- number of ce for user logic memory space 1 (always 1 chip enable)
-- );
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
--constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
--constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master data bus (32, 64, or 128)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_MPLB_DWIDTH;
constant IPIF_MST_DWIDTH : integer := C_MPLB_DWIDTH;
------------------------------------------
-- Inhibit the automatic inculsion of the Conversion Cycle and Burst Length Expansion logic
-- 0 = allow automatic inclusion of the CC and BLE logic
-- 1 = inhibit automatic inclusion of the CC and BLE logic
------------------------------------------
constant IPIF_INHIBIT_CC_BLE_INCLUSION : integer := 0;
------------------------------------------
-- Width of the slave address bus (32 only)
------------------------------------------
--constant USER_SLV_AWIDTH : integer := C_SPLB_AWIDTH;
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_MPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
--constant USER_MST_CS_INDEX : integer := 0;
--constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
--constant USER_MEM0_CS_INDEX : integer := 1;
--constant USER_MEM0_CS_INDEX : integer := 0;
--constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX;
--constant USER_CE_INDEX : integer := USER_MST_CE_INDEX;
--constant USER_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_CS_INDEX);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
-- signal ipif_Bus2IP_Clk : std_logic;
-- signal ipif_Bus2IP_Reset : std_logic;
-- signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_MST_DWIDTH-1);
-- signal ipif_IP2Bus_WrAck : std_logic;
-- signal ipif_IP2Bus_RdAck : std_logic;
-- signal ipif_IP2Bus_AddrAck : std_logic;
-- signal ipif_IP2Bus_Error : std_logic;
-- signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
-- signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_MST_DWIDTH-1);
-- signal ipif_Bus2IP_RNW : std_logic;
-- signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
-- signal ipif_Bus2IP_Burst : std_logic;
-- signal ipif_Bus2IP_BurstLength : std_logic_vector(0 to log2(16*(C_SPLB_DWIDTH/8)));
-- signal ipif_Bus2IP_WrReq : std_logic;
-- signal ipif_Bus2IP_RdReq : std_logic;
-- signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
-- signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
-- signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_IP2Bus_MstRd_Req : std_logic;
signal ipif_IP2Bus_MstWr_Req : std_logic;
signal ipif_IP2Bus_Mst_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
signal ipif_IP2Bus_Mst_Length : std_logic_vector(0 to 11);
signal ipif_IP2Bus_Mst_BE : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_Mst_Type : std_logic;
signal ipif_IP2Bus_Mst_Lock : std_logic;
signal ipif_IP2Bus_Mst_Reset : std_logic;
signal ipif_Bus2IP_Mst_CmdAck : std_logic;
signal ipif_Bus2IP_Mst_Cmplt : std_logic;
signal ipif_Bus2IP_Mst_Error : std_logic;
signal ipif_Bus2IP_Mst_Rearbitrate : std_logic;
signal ipif_Bus2IP_Mst_Cmd_Timeout : std_logic;
signal ipif_Bus2IP_MstRd_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstRd_rem : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_Bus2IP_MstRd_sof_n : std_logic;
signal ipif_Bus2IP_MstRd_eof_n : std_logic;
signal ipif_Bus2IP_MstRd_src_rdy_n : std_logic;
signal ipif_Bus2IP_MstRd_src_dsc_n : std_logic;
signal ipif_IP2Bus_MstRd_dst_rdy_n : std_logic;
signal ipif_IP2Bus_MstRd_dst_dsc_n : std_logic;
signal ipif_IP2Bus_MstWr_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_IP2Bus_MstWr_rem : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_MstWr_sof_n : std_logic;
signal ipif_IP2Bus_MstWr_eof_n : std_logic;
signal ipif_IP2Bus_MstWr_src_rdy_n : std_logic;
signal ipif_IP2Bus_MstWr_src_dsc_n : std_logic;
signal ipif_Bus2IP_MstWr_dst_rdy_n : std_logic;
signal ipif_Bus2IP_MstWr_dst_dsc_n : std_logic;
-- signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
-- signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
-- signal user_Bus2IP_BurstLength : std_logic_vector(0 to 8) := (others => '0');
-- signal user_Bus2IP_Data : std_logic_vector(0 to USER_MST_DWIDTH-1);
-- signal user_Bus2IP_DataX : std_logic_vector(0 to USER_MST_DWIDTH-1);
-- signal user_IP2Bus_Data : std_logic_vector(0 to USER_MST_DWIDTH-1);
-- signal user_IP2Bus_DataX : std_logic_vector(0 to USER_MST_DWIDTH-1);
-- signal user_IP2Bus_RdAck : std_logic;
-- signal user_IP2Bus_WrAck : std_logic;
-- signal user_IP2Bus_Error : std_logic;
signal task_clk_internal : std_logic;
signal task_reset_internal : std_logic;
-- single word data input/output
signal mem2osif_singleData : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal osif2mem_singleData : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- addresses for master transfers
signal mem_localAddr : std_logic_vector(0 to USER_MST_AWIDTH-1);
signal mem_targetAddr : std_logic_vector(0 to USER_MST_AWIDTH-1);
-- single word transfer requests
signal mem_singleRdReq : std_logic;
signal mem_singleWrReq : std_logic;
-- burst transfer requests
signal mem_burstRdReq : std_logic;
signal mem_burstWrReq : std_logic;
signal mem_burstLen : std_logic_vector(0 to 11);
-- status outputs
signal mem_busy : std_logic;
signal mem_rdDone : std_logic;
signal mem_wrDone : std_logic;
---------
-- local FIFO control and data lines
---------
signal fifomgr_read_remove : std_logic;
signal fifomgr_read_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifomgr_read_wait : std_logic;
signal fifomgr_write_add : std_logic;
signal fifomgr_write_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifomgr_write_wait : std_logic;
-- bus macro control signal
signal bmEnable_i : std_logic;
-- incoming task signals (can be disabled via bmEnable_i)
signal osif_task2os_vec_i : std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
signal burstRdData_i : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
begin
---------
-- set task clock/reset
---------
task_clk <= task_clk_internal;
task_reset <= task_reset_internal;
-- propagate bus macro enable signal (COMPATIBILITY with older tool chains)
bmEnable <= bmEnable_i;
-- gate incoming task signals with bmEnable_i
gate_incoming : process(bmEnable_i, osif_task2os_vec, burstRdData)
begin
if bmEnable_i = '1' then
osif_task2os_vec_i <= osif_task2os_vec;
burstRdData_i <= burstRdData;
else
osif_task2os_vec_i <= (others => '0');
burstRdData_i <= (others => '0');
end if;
end process;
--------------------------------------
-- memory bus controller core
--
-- PLBv46
---------------------------------------
mem_plb46_i : entity xps_osif_v2_01_a.mem_plb46
generic map
(
-- Bus protocol parameters
C_AWIDTH => C_MPLB_AWIDTH,
C_DWIDTH => 32,
C_PLB_AWIDTH => C_MPLB_AWIDTH,
C_PLB_DWIDTH => C_MPLB_NATIVE_DWIDTH,
--C_NUM_CE => USER_MST_NUM_REG,
C_BURST_AWIDTH => C_BURST_AWIDTH
)
port map
(
clk => task_clk_internal,
reset => task_reset_internal,
-- data interface ---------------------------
-- burst mem interface
o_burstAddr => burstAddr,
o_burstData => burstWrData,
i_burstData => burstRdData_i,
o_burstWE => burstWE,
o_burstBE => burstBE,
-- single word data input/output
i_singleData => osif2mem_singleData,
o_singleData => mem2osif_singleData,
-- control interface ------------------------
-- addresses for master transfers
i_localAddr => mem_localAddr,
i_targetAddr => mem_targetAddr,
-- single word transfer requests
i_singleRdReq => mem_singleRdReq,
i_singleWrReq => mem_singleWrReq,
-- burst transfer requests
i_burstRdReq => mem_burstRdReq,
i_burstWrReq => mem_burstWrReq,
i_burstLen => mem_burstLen,
-- status outputs
o_busy => mem_busy,
o_rdDone => mem_rdDone,
o_wrDone => mem_wrDone,
-- PLBv46 bus interface -----------------------------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk => MPLB_Clk,
Bus2IP_Reset => MPLB_Rst,
Bus2IP_MstError => ipif_Bus2IP_Mst_Error,
Bus2IP_MstLastAck => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_MstRdAck => PLB_MRdDAck,
Bus2IP_MstWrAck => PLB_MWrDAck,
Bus2IP_MstRetry => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_MstTimeOut => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
IP2Bus_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_MstBE => ipif_IP2Bus_Mst_BE,
IP2Bus_MstBurst => ipif_IP2Bus_Mst_Type,
IP2Bus_MstBusReset => ipif_IP2Bus_Mst_Reset,
IP2Bus_MstBusLock => ipif_IP2Bus_Mst_Lock,
IP2Bus_MstNum => ipif_IP2Bus_Mst_Length,
IP2Bus_MstRdReq => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWrReq => ipif_IP2Bus_MstWr_Req,
-- Ports for Local Link
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_rem => ipif_Bus2IP_MstRd_rem,
Bus2IP_MstRd_sof_n => ipif_Bus2IP_MstRd_sof_n,
Bus2IP_MstRd_eof_n => ipif_Bus2IP_MstRd_eof_n,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
Bus2IP_MstRd_src_dsc_n => ipif_Bus2IP_MstRd_src_dsc_n,
IP2Bus_MstRd_dst_rdy_n => ipif_IP2Bus_MstRd_dst_rdy_n,
IP2Bus_MstRd_dst_dsc_n => ipif_IP2Bus_MstRd_dst_dsc_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
IP2Bus_MstWr_rem => ipif_IP2Bus_MstWr_rem,
IP2Bus_MstWr_sof_n => ipif_IP2Bus_MstWr_sof_n,
IP2Bus_MstWr_eof_n => ipif_IP2Bus_MstWr_eof_n,
IP2Bus_MstWr_src_rdy_n => ipif_IP2Bus_MstWr_src_rdy_n,
IP2Bus_MstWr_src_dsc_n => ipif_IP2Bus_MstWr_src_dsc_n,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n,
Bus2IP_MstWr_dst_dsc_n => ipif_Bus2IP_MstWr_dst_dsc_n
);
------------------------------------------
-- instantiate plbv46_master_burst
------------------------------------------
PLBV46_MASTER_BURST_I : entity plbv46_master_burst_v1_01_a.plbv46_master_burst
generic map
(
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_MPLB_SMALLEST_SLAVE => C_MPLB_SMALLEST_SLAVE,
C_INHIBIT_CC_BLE_INCLUSION => IPIF_INHIBIT_CC_BLE_INCLUSION,
C_FAMILY => C_FAMILY
)
port map
(
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_Length => ipif_IP2Bus_Mst_Length,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Type => ipif_IP2Bus_Mst_Type,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_rem => ipif_Bus2IP_MstRd_rem,
Bus2IP_MstRd_sof_n => ipif_Bus2IP_MstRd_sof_n,
Bus2IP_MstRd_eof_n => ipif_Bus2IP_MstRd_eof_n,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
Bus2IP_MstRd_src_dsc_n => ipif_Bus2IP_MstRd_src_dsc_n,
IP2Bus_MstRd_dst_rdy_n => ipif_IP2Bus_MstRd_dst_rdy_n,
IP2Bus_MstRd_dst_dsc_n => ipif_IP2Bus_MstRd_dst_dsc_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
IP2Bus_MstWr_rem => ipif_IP2Bus_MstWr_rem,
IP2Bus_MstWr_sof_n => ipif_IP2Bus_MstWr_sof_n,
IP2Bus_MstWr_eof_n => ipif_IP2Bus_MstWr_eof_n,
IP2Bus_MstWr_src_rdy_n => ipif_IP2Bus_MstWr_src_rdy_n,
IP2Bus_MstWr_src_dsc_n => ipif_IP2Bus_MstWr_src_dsc_n,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n,
Bus2IP_MstWr_dst_dsc_n => ipif_Bus2IP_MstWr_dst_dsc_n
);
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : entity osif_core_v2_01_a.osif_core
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
C_BURST_AWIDTH => C_BURST_AWIDTH,
C_FIFO_DWIDTH => C_FIFO_DWIDTH,
C_BURSTLEN_WIDTH => 12,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_AWIDTH => C_MPLB_AWIDTH,
C_DWIDTH => 32,
C_PLB_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_NUM_CE => 2, --isnt used in USER_LOGIC
C_DCR_BASEADDR => C_DCR_BASEADDR,
C_DCR_HIGHADDR => C_DCR_HIGHADDR,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_DCR_ILA => C_DCR_ILA
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
interrupt => interrupt,
busy => busy,
blocking => blocking,
-- task interface
task_clk => task_clk_internal,
task_reset => task_reset_internal,
osif_os2task_vec => osif_os2task_vec,
osif_task2os_vec => osif_task2os_vec_i,
-- FIFO manager access signals
o_fifomgr_read_remove => fifomgr_read_remove,
i_fifomgr_read_data => fifomgr_read_data,
i_fifomgr_read_wait => fifomgr_read_wait,
o_fifomgr_write_add => fifomgr_write_add,
o_fifomgr_write_data => fifomgr_write_data,
i_fifomgr_write_wait => fifomgr_write_wait,
-- memory access signals
o_mem_singleData => osif2mem_singleData,
i_mem_singleData => mem2osif_singleData,
o_mem_localAddr => mem_localAddr,
o_mem_targetAddr => mem_targetAddr,
o_mem_singleRdReq => mem_singleRdReq,
o_mem_singleWrReq => mem_singleWrReq,
o_mem_burstRdReq => mem_burstRdReq,
o_mem_burstWrReq => mem_burstWrReq,
o_mem_burstLen => mem_burstLen,
i_mem_busy => mem_busy,
i_mem_rdDone => mem_rdDone,
i_mem_wrDone => mem_wrDone,
-- bus macro control
o_bm_enable => bmEnable_i,
-- MAP USER PORTS ABOVE THIS LINE ------------------
sys_clk => MPLB_Clk,--sys_clk,
sys_reset => MPLB_Rst,--sys_reset,
-- DCR Bus protocol ports
o_dcrAck => o_dcrAck,
o_dcrDBus => o_dcrDBus,
i_dcrABus => i_dcrABus,
i_dcrDBus => i_dcrDBus,
i_dcrRead => i_dcrRead,
i_dcrWrite => i_dcrWrite,
i_dcrICON => i_dcrICON
);
-----------------------------------------------------------------------
-- fifo_mgr_inst: FIFO manager instantiation
--
-- The FIFO manager handles incoming push/pop requests to the two
-- hardware FIFOs attached to the OSIF. It arbitrates between
-- local hardware-thread-initiated requests and indirect bus accesses
-- by other hardware threads.
-----------------------------------------------------------------------
fifo_mgr_inst : entity xps_osif_v2_01_a.fifo_mgr
generic map (
C_FIFO_DWIDTH => C_FIFO_DWIDTH
)
port map (
clk => sys_clk,
reset => sys_reset, -- we don't want a thread reset command to flush
-- the FIFOs, therefore no thread_reset_i!
-- local FIFO access signals
i_local_read_remove => fifomgr_read_remove,
o_local_read_data => fifomgr_read_data,
o_local_read_wait => fifomgr_read_wait,
i_local_write_add => fifomgr_write_add,
i_local_write_data => fifomgr_write_data,
o_local_write_wait => fifomgr_write_wait,
-- "real" FIFO access signals
o_fifo_read_en => o_fifo_read_en,
i_fifo_read_data => i_fifo_read_data,
i_fifo_read_ready => i_fifo_read_ready,
o_fifo_write_en => o_fifo_write_en,
o_fifo_write_data => o_fifo_write_data,
i_fifo_write_ready => i_fifo_write_ready
);
--------
-- set FIFO clock/reset
--------
o_fifo_clk <= sys_clk;
o_fifo_reset <= sys_reset;
------------------------------------------
-- connect internal signals
------------------------------------------
-- IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data, user_IP2Bus_DataX ) is
-- begin
-- case ipif_Bus2IP_CS is
-- when "1" => ipif_IP2Bus_Data <= user_IP2Bus_Data & user_IP2Bus_DataX;
-- when "010" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
-- when "001" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
-- when others => ipif_IP2Bus_Data <= (others => '0');
-- end case;
-- end process IP2BUS_DATA_MUX_PROC;
-- user_Bus2IP_Data <= ipif_Bus2IP_Data(0 to USER_MST_DWIDTH-1);
-- user_Bus2IP_DataX <= iBus2IP_Data(USER_MST_DWIDTH to C_MPLB_DWIDTH-1);
-- ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
-- ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
-- ipif_IP2Bus_Error <= user_IP2Bus_Error;
-- user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
-- user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= hex_to_std_logic_vector("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"blk_mem_gen_v7_3.mif",
DEFAULT_DATA,
32,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
-----------------------------------------------------------------------------
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- LEON3 Zedboard Demonstration design
-- Copyright (C) 2012 Fredrik Ringhage, Aeroflex Gaisler
-- Modifed by Jiri Gaisler to provide working AXI interface, 2014-04-05
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.config.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false
);
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : inout std_logic;
processing_system7_0_PS_CLK : inout std_logic;
processing_system7_0_PS_PORB : inout std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : inout std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
component leon3_zedboard_stub
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_arready : out STD_LOGIC;
S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arvalid : in STD_LOGIC;
S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_awready : out STD_LOGIC;
S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awvalid : in STD_LOGIC;
S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_bready : in STD_LOGIC;
S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_bvalid : out STD_LOGIC;
S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_rlast : out STD_LOGIC;
S_AXI_GP0_rready : in STD_LOGIC;
S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_rvalid : out STD_LOGIC;
S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_wlast : in STD_LOGIC;
S_AXI_GP0_wready : out STD_LOGIC;
S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_wvalid : in STD_LOGIC
);
end component;
constant maxahbm : integer := (CFG_LEON3*CFG_NCPU)+CFG_AHB_JTAG;
constant maxahbs : integer := 8;
constant maxapbs : integer := 16;
signal vcc, gnd : std_logic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rsti, rst : std_ulogic;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
constant BOARD_FREQ : integer := 83333; -- CLK0 frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ;
signal stati : ahbstat_in_type;
constant CIDSZ : integer := 6;
constant CLENSZ : integer := 4;
signal S_AXI_GP0_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_arcache : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_arid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_arlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 );
signal S_AXI_GP0_arlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
signal S_AXI_GP0_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_arqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
signal S_AXI_GP0_awqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
signal S_AXI_GP0_arready : STD_LOGIC;
signal S_AXI_GP0_arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_arvalid : STD_LOGIC;
signal S_AXI_GP0_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_awburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_awcache : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_awid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_awlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 );
signal S_AXI_GP0_awlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
signal S_AXI_GP0_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_awready : STD_LOGIC;
signal S_AXI_GP0_awsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_awvalid : STD_LOGIC;
signal S_AXI_GP0_bid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_bready : STD_LOGIC;
signal S_AXI_GP0_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_bvalid : STD_LOGIC;
signal S_AXI_GP0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_rid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_rlast : STD_LOGIC;
signal S_AXI_GP0_rready : STD_LOGIC;
signal S_AXI_GP0_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_rvalid : STD_LOGIC;
signal S_AXI_GP0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_wlast : STD_LOGIC;
signal S_AXI_GP0_wready : STD_LOGIC;
signal S_AXI_GP0_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_wvalid : STD_LOGIC;
signal S_AXI_GP0_wid : STD_LOGIC_VECTOR ( 5 downto 0 ); --
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
reset_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech)
port map (button(0), rsti);
rstn <= rst and not rsti;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3_0 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
nocpu : if CFG_LEON3 = 0 generate dbgo(0) <= dbgo_none; end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(1), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= gpioi.val(0);
end generate;
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(0), dsuo.active);
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_LEON3*CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_LEON3*CFG_NCPU),
open, open, open, open, open, open, open, gnd);
end generate;
leon3_zedboard_stub_i : leon3_zedboard_stub
port map (
DDR_ck_p => processing_system7_0_DDR_Clk,
DDR_ck_n => processing_system7_0_DDR_Clk_n,
DDR_cke => processing_system7_0_DDR_CKE,
DDR_cs_n => processing_system7_0_DDR_CS_n,
DDR_ras_n => processing_system7_0_DDR_RAS_n,
DDR_cas_n => processing_system7_0_DDR_CAS_n,
DDR_we_n => processing_system7_0_DDR_WEB_pin,
DDR_ba => processing_system7_0_DDR_BankAddr,
DDR_addr => processing_system7_0_DDR_Addr,
DDR_odt => processing_system7_0_DDR_ODT,
DDR_reset_n => processing_system7_0_DDR_DRSTB,
DDR_dq => processing_system7_0_DDR_DQ,
DDR_dm => processing_system7_0_DDR_DM,
DDR_dqs_p => processing_system7_0_DDR_DQS,
DDR_dqs_n => processing_system7_0_DDR_DQS_n,
FCLK_CLK0 => clkm,
FCLK_RESET0_N => rst,
FIXED_IO_mio => processing_system7_0_MIO,
FIXED_IO_ps_srstb => processing_system7_0_PS_SRSTB,
FIXED_IO_ps_clk => processing_system7_0_PS_CLK,
FIXED_IO_ps_porb => processing_system7_0_PS_PORB,
FIXED_IO_ddr_vrn => processing_system7_0_DDR_VRN,
FIXED_IO_ddr_vrp => processing_system7_0_DDR_VRP,
S_AXI_GP0_araddr => S_AXI_GP0_araddr,
S_AXI_GP0_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0),
S_AXI_GP0_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0),
S_AXI_GP0_arid => S_AXI_GP0_arid,
S_AXI_GP0_arlen => S_AXI_GP0_arlen,
S_AXI_GP0_arlock => S_AXI_GP0_arlock,
S_AXI_GP0_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0),
S_AXI_GP0_arqos => S_AXI_GP0_arqos,
S_AXI_GP0_awqos => S_AXI_GP0_awqos,
S_AXI_GP0_arready => S_AXI_GP0_arready,
S_AXI_GP0_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0),
S_AXI_GP0_arvalid => S_AXI_GP0_arvalid,
S_AXI_GP0_awaddr => S_AXI_GP0_awaddr,
S_AXI_GP0_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0),
S_AXI_GP0_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0),
S_AXI_GP0_awid => S_AXI_GP0_awid,
S_AXI_GP0_awlen => S_AXI_GP0_awlen,
S_AXI_GP0_awlock => S_AXI_GP0_awlock,
S_AXI_GP0_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0),
S_AXI_GP0_awready => S_AXI_GP0_awready,
S_AXI_GP0_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0),
S_AXI_GP0_awvalid => S_AXI_GP0_awvalid,
S_AXI_GP0_bid => S_AXI_GP0_bid,
S_AXI_GP0_bready => S_AXI_GP0_bready,
S_AXI_GP0_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0),
S_AXI_GP0_bvalid => S_AXI_GP0_bvalid,
S_AXI_GP0_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0),
S_AXI_GP0_rid => S_AXI_GP0_rid,
S_AXI_GP0_rlast => S_AXI_GP0_rlast,
S_AXI_GP0_rready => S_AXI_GP0_rready,
S_AXI_GP0_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0),
S_AXI_GP0_rvalid => S_AXI_GP0_rvalid,
S_AXI_GP0_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0),
S_AXI_GP0_wid => S_AXI_GP0_wid,
S_AXI_GP0_wlast => S_AXI_GP0_wlast,
S_AXI_GP0_wready => S_AXI_GP0_wready,
S_AXI_GP0_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0),
S_AXI_GP0_wvalid => S_AXI_GP0_wvalid
);
ahb2axi0 : entity work.ahb2axi
generic map(
hindex => 3, haddr => 16#400#, hmask => 16#F00#,
pindex => 0, paddr => 0, cidsz => CIDSZ, clensz => CLENSZ)
port map(
rstn => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(3),
apbi => apbi,
apbo => apbo(0),
M_AXI_araddr => S_AXI_GP0_araddr,
M_AXI_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0),
M_AXI_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0),
M_AXI_arid => S_AXI_GP0_arid,
M_AXI_arlen => S_AXI_GP0_arlen,
M_AXI_arlock => S_AXI_GP0_arlock,
M_AXI_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0),
M_AXI_arqos => S_AXI_GP0_arqos,
M_AXI_arready => S_AXI_GP0_arready,
M_AXI_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0),
M_AXI_arvalid => S_AXI_GP0_arvalid,
M_AXI_awaddr => S_AXI_GP0_awaddr,
M_AXI_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0),
M_AXI_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0),
M_AXI_awid => S_AXI_GP0_awid,
M_AXI_awlen => S_AXI_GP0_awlen,
M_AXI_awlock => S_AXI_GP0_awlock,
M_AXI_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0),
M_AXI_awqos => S_AXI_GP0_awqos,
M_AXI_awready => S_AXI_GP0_awready,
M_AXI_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0),
M_AXI_awvalid => S_AXI_GP0_awvalid,
M_AXI_bid => S_AXI_GP0_bid,
M_AXI_bready => S_AXI_GP0_bready,
M_AXI_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0),
M_AXI_bvalid => S_AXI_GP0_bvalid,
M_AXI_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0),
M_AXI_rid => S_AXI_GP0_rid,
M_AXI_rlast => S_AXI_GP0_rlast,
M_AXI_rready => S_AXI_GP0_rready,
M_AXI_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0),
M_AXI_rvalid => S_AXI_GP0_rvalid,
M_AXI_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0),
M_AXI_wlast => S_AXI_GP0_wlast,
M_AXI_wready => S_AXI_GP0_wready,
M_AXI_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0),
M_AXI_wvalid => S_AXI_GP0_wvalid
);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqgen : if CFG_LEON3 = 1 generate
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
end generate;
irqctrl : if (CFG_IRQ3_ENABLE + CFG_LEON3) /= 2 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => 0)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
pio_pad_0 : inpad generic map (tech => padtech)
port map (switch(0), gpioi.din(0)) -- Do not let SW modify BREAK input
pio_pads : for i in 1 to 7 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 8 to 10 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (button(i-8+1), gpioi.din(i));
end generate;
pio_pads3 : for i in 11 to 14 generate
pio_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (led(i-11+4), gpioo.dout(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
hready_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech)
port map (led(2), ahbmi.hready);
rsti_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech)
port map (led(3), rsti);
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0_gen : if (testahb = true) generate
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
end generate;
-- pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (maxahbs+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx Zedboard Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:48:03 02/19/2017
-- Design Name:
-- Module Name: sumador_medio - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sumador_medio is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cout : out STD_LOGIC;
s : out STD_LOGIC);
end sumador_medio;
architecture Behavioral of sumador_medio is
begin
s <= a XOR b;
cout <= a AND b;
end Behavioral;
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
entity FIFO is
port (
I_INPUT : in integer;
O_OUTPUT : out integer
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
entity FIFO is
port (
I_INPUT : in integer;
O_OUTPUT : out integer
);
end entity FIFO;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 23:00:32 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_gpio_0_1_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_gpio_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair4";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_io_o(7 downto 0) <= \^gpio_io_o\(7 downto 0);
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(7),
Q => D(7),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(6),
Q => D(6),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(5),
Q => D(5),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(4),
Q => D(4),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(3),
Q => D(3),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[5].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(2),
Q => D(2),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[6].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(1),
Q => D(1),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(0),
Q => D(0),
R => bus2ip_rnw_i_reg
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7),
Q => \^gpio_io_o\(7),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6),
Q => \^gpio_io_o\(6),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5),
Q => \^gpio_io_o\(5),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4),
Q => \^gpio_io_o\(4),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3),
Q => \^gpio_io_o\(3),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2),
Q => \^gpio_io_o\(2),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1),
Q => \^gpio_io_o\(1),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0),
Q => \^gpio_io_o\(0),
R => SS(0)
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7),
Q => gpio_io_t(7),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6),
Q => gpio_io_t(6),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5),
Q => gpio_io_t(5),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4),
Q => gpio_io_t(4),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3),
Q => gpio_io_t(3),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2),
Q => gpio_io_t(2),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1),
Q => gpio_io_t(1),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0),
Q => gpio_io_t(0),
S => SS(0)
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => SS(0)
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => bus2ip_cs,
I1 => \^gpio_xferack_reg\,
I2 => \^gpio_xferack_i\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => SS(0)
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
rst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
start2_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => start2_reg,
I2 => s_axi_aresetn,
I3 => \^s_axi_arready\,
I4 => \^s_axi_wready\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => gpio_xferAck_Reg,
I3 => GPIO_xferAck_i,
O => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAABAAAA"
)
port map (
I0 => rst_reg,
I1 => Q(1),
I2 => bus2ip_rnw_i_reg,
I3 => Q(0),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => Q(2),
O => E(0)
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(7),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(15),
O => D(7)
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(6),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(14),
O => D(6)
);
\Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(5),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(13),
O => D(5)
);
\Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(12),
O => D(4)
);
\Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(11),
O => D(3)
);
\Not_Dual.gpio_Data_Out[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(10),
O => D(2)
);
\Not_Dual.gpio_Data_Out[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(9),
O => D(1)
);
\Not_Dual.gpio_Data_Out[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(8),
O => D(0)
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => rst_reg,
I1 => Q(0),
I2 => Q(1),
I3 => bus2ip_rnw_i_reg,
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => Q(2),
O => \Not_Dual.gpio_OE_reg[0]\(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => is_read,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => is_write_reg,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
SR : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.gpio_data_out_reg[0]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair1";
begin
\Not_Dual.gpio_Data_Out_reg[0]\ <= \^not_dual.gpio_data_out_reg[0]\;
SR <= \^sr\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
D(7 downto 0) => D(7 downto 0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\,
\Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0),
Q(2) => bus2ip_addr(0),
Q(1) => bus2ip_addr(5),
Q(0) => bus2ip_addr(6),
bus2ip_rnw_i_reg => \^not_dual.gpio_data_out_reg[0]\,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
rst_reg => \^sr\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0),
s_axi_wready => \^s_axi_wready\,
start2_reg => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(6),
R => \^sr\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(5),
R => \^sr\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(0),
R => \^sr\
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => state(0),
I1 => state(1),
I2 => s_axi_arvalid,
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.gpio_data_out_reg[0]\,
R => \^sr\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^sr\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => p_1_in
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_1_in,
Q => \^sr\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => \s_axi_rdata_i[7]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(0),
Q => s_axi_rdata(0),
R => \^sr\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(1),
Q => s_axi_rdata(1),
R => \^sr\
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(2),
Q => s_axi_rdata(2),
R => \^sr\
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(3),
Q => s_axi_rdata(3),
R => \^sr\
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(4),
Q => s_axi_rdata(4),
R => \^sr\
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(5),
Q => s_axi_rdata(5),
R => \^sr\
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(6),
Q => s_axi_rdata(6),
R => \^sr\
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(7),
Q => s_axi_rdata(7),
R => \^sr\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => state(0),
I2 => s_axi_arvalid,
I3 => state(1),
I4 => \^s_axi_wready\,
O => p_0_out(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => \state[1]_i_3_n_0\,
I2 => state(1),
I3 => state(0),
I4 => \^s_axi_arready\,
O => p_0_out(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => state(0),
R => \^sr\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(1),
Q => state(1),
R => \^sr\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
D(7 downto 0) => D(7 downto 0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\,
\Not_Dual.gpio_Data_Out_reg[0]\ => bus2ip_rnw,
\Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0),
Q(7 downto 0) => Q(7 downto 0),
SR => bus2ip_reset,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => s_axi_rdata(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "LOGICORE";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_6 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_7 : STD_LOGIC;
signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 7 );
signal GPIO_xferAck_i : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_core_1_n_19 : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 24 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 24 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7 downto 0) <= \^s_axi_rdata\(7 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
D(7) => DBus_Reg(0),
D(6) => DBus_Reg(1),
D(5) => DBus_Reg(2),
D(4) => DBus_Reg(3),
D(3) => DBus_Reg(4),
D(2) => DBus_Reg(5),
D(1) => DBus_Reg(6),
D(0) => DBus_Reg(7),
E(0) => AXI_LITE_IPIF_I_n_6,
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_17,
\Not_Dual.gpio_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_7,
Q(7) => ip2bus_data_i_D1(24),
Q(6) => ip2bus_data_i_D1(25),
Q(5) => ip2bus_data_i_D1(26),
Q(4) => ip2bus_data_i_D1(27),
Q(3) => ip2bus_data_i_D1(28),
Q(2) => ip2bus_data_i_D1(29),
Q(1) => ip2bus_data_i_D1(30),
Q(0) => ip2bus_data_i_D1(31),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => \^s_axi_rdata\(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(15 downto 8) => s_axi_wdata(31 downto 24),
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
gpio_core_1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
port map (
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
E(0) => AXI_LITE_IPIF_I_n_6,
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7) => DBus_Reg(0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6) => DBus_Reg(1),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5) => DBus_Reg(2),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4) => DBus_Reg(3),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3) => DBus_Reg(4),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2) => DBus_Reg(5),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1) => DBus_Reg(6),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0) => DBus_Reg(7),
SS(0) => bus2ip_reset,
bus2ip_cs => bus2ip_cs,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_17,
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => gpio_io_t(7 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_19,
rst_reg(0) => AXI_LITE_IPIF_I_n_7,
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(24),
Q => ip2bus_data_i_D1(24),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(25),
Q => ip2bus_data_i_D1(25),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(26),
Q => ip2bus_data_i_D1(26),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_19,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_gpio_0_1,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_gpio,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 1;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(7 downto 0) => B"00000000",
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => NLW_U0_gpio_io_t_UNCONNECTED(7 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Report & assert tests.
library ieee;
use ieee.std_logic_1164.all;
package vhdl_report_pkg is
-- as of the moment of writing vhdlpp does not support procedures
function test_asserts(a : integer) return integer;
end vhdl_report_pkg;
package body vhdl_report_pkg is
-- Test functions used to output package files
function test_asserts(a : integer) return integer is
begin
report "procedure 1"
severity ERROR;
assert false;
assert 1 = 0
report "procedure 2";
assert 1 = 2
severity NOTE;
assert false
report "procedure 3"
severity WARNING;
return 0;
end function;
end vhdl_report_pkg;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Report & assert tests.
library ieee;
use ieee.std_logic_1164.all;
package vhdl_report_pkg is
-- as of the moment of writing vhdlpp does not support procedures
function test_asserts(a : integer) return integer;
end vhdl_report_pkg;
package body vhdl_report_pkg is
-- Test functions used to output package files
function test_asserts(a : integer) return integer is
begin
report "procedure 1"
severity ERROR;
assert false;
assert 1 = 0
report "procedure 2";
assert 1 = 2
severity NOTE;
assert false
report "procedure 3"
severity WARNING;
return 0;
end function;
end vhdl_report_pkg;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Report & assert tests.
library ieee;
use ieee.std_logic_1164.all;
package vhdl_report_pkg is
-- as of the moment of writing vhdlpp does not support procedures
function test_asserts(a : integer) return integer;
end vhdl_report_pkg;
package body vhdl_report_pkg is
-- Test functions used to output package files
function test_asserts(a : integer) return integer is
begin
report "procedure 1"
severity ERROR;
assert false;
assert 1 = 0
report "procedure 2";
assert 1 = 2
severity NOTE;
assert false
report "procedure 3"
severity WARNING;
return 0;
end function;
end vhdl_report_pkg;
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_if_statement is
end entity alt_dspbuilder_if_statement;
architecture rtl of alt_dspbuilder_if_statement is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_if_statement is
end entity alt_dspbuilder_if_statement;
architecture rtl of alt_dspbuilder_if_statement is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_if_statement is
end entity alt_dspbuilder_if_statement;
architecture rtl of alt_dspbuilder_if_statement is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_if_statement is
end entity alt_dspbuilder_if_statement;
architecture rtl of alt_dspbuilder_if_statement is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_if_statement is
end entity alt_dspbuilder_if_statement;
architecture rtl of alt_dspbuilder_if_statement is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_if_statement is
end entity alt_dspbuilder_if_statement;
architecture rtl of alt_dspbuilder_if_statement is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_if_statement is
end entity alt_dspbuilder_if_statement;
architecture rtl of alt_dspbuilder_if_statement is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_if_statement is
end entity alt_dspbuilder_if_statement;
architecture rtl of alt_dspbuilder_if_statement is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_if_statement is
end entity alt_dspbuilder_if_statement;
architecture rtl of alt_dspbuilder_if_statement is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_if_statement is
end entity alt_dspbuilder_if_statement;
architecture rtl of alt_dspbuilder_if_statement is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2cslv
-- File: i2cslv.vhd
-- Author: Jan Andersson - Gaisler Research
-- jan@gaisler.com
--
-- Description: Simple I2C-slave with AMBA APB interface
--
-- Documentation of generics:
--
-- [hardaddr]
-- If this generic is set to 1 the core uses i2caddr as the hard coded address.
-- If hardaddr is set to 0 the core's address can be changed via the SLVADDR
-- register.
--
-- [tenbit]
-- Support for ten bit addresses.
--
-- [i2caddr]
-- The slave's (initial) i2c address.
--
-- [oepol]
-- Output enable polarity
--
-- [filter]
-- Length of filters used on SCL and SDA
--
-- The slave has four different modes operation. The mode is defined by the
-- value of the bits RMODE and TMODE.
-- RMODE TMODE I2CSLAVE Mode
-- 0 0 0
-- 0 1 1
-- 1 0 2
-- 1 1 3
--
-- RMODE 0:
-- The slave accepts one byte and NAKs all other transfers until software has
-- acknowledged the received byte.
-- RMODE 1:
-- The slave accepts one byte and keeps SCL low until software has acknowledged
-- the received byte
-- TMODE 0:
-- The slave transmits the same byte to all if the master requests more than
-- one byte in the transfer. The slave then NAKs all read requests unless the
-- Transmit Always Valid (TAV) bit in the control register is set.
-- TMODE 1:
-- The slave transmits one byte and then keeps SCL low until software has
-- acknowledged that the byte has been transmitted.
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity i2cslv is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0; -- interrupt index
-- I2C configuration
hardaddr : integer range 0 to 1 := 0; -- See description above
tenbit : integer range 0 to 1 := 0;
i2caddr : integer range 0 to 1023 := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2cslv;
architecture rtl of i2cslv is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Core version
constant I2CSLV_REV : integer := 0;
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2CSLV, 0, I2CSLV_REV, pirq),
1 => apb_iobar(paddr, pmask));
-- Register addresses
constant SLV_ADDR : std_logic_vector(7 downto 2) := "000000";
constant CTRL_ADDR : std_logic_vector(7 downto 2) := "000001";
constant STS_ADDR : std_logic_vector(7 downto 2) := "000010";
constant MSK_ADDR : std_logic_vector(7 downto 2) := "000011";
constant RD_ADDR : std_logic_vector(7 downto 2) := "000100";
constant TD_ADDR : std_logic_vector(7 downto 2) := "000101";
-- Core configuration
constant TENBIT_SUPPORT : integer := tenbit;
constant I2CADDRLEN : integer := 7 + tenbit*3;
constant HARDCADDR : integer := hardaddr;
constant I2CSLVADDR : std_logic_vector((I2CADDRLEN-1) downto 0) :=
conv_std_logic_vector(i2caddr, I2CADDRLEN);
-- Misc constants
constant I2C_READ : std_ulogic := '1'; -- R/Wn bit
constant I2C_WRITE : std_ulogic := '0';
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant I2C_LOW : std_ulogic := OEPOL_LEVEL; -- OE
constant I2C_HIZ : std_ulogic := not OEPOL_LEVEL;
constant I2C_ACK : std_ulogic := '0';
constant TENBIT_ADDR_START : std_logic_vector(4 downto 0) := "11110";
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type ctrl_reg_type is record -- Control register
rmode : std_ulogic; -- Receive mode
tmode : std_ulogic; -- Transmit mode
tv : std_ulogic; -- Transmit valid
tav : std_ulogic; -- Transmit always valid
en : std_ulogic; -- Enable
end record;
type sts_reg_type is record -- Status/Mask registers
rec : std_ulogic; -- Received byte
tra : std_ulogic; -- Transmitted byte
nak : std_ulogic; -- NAK'd address
end record;
type slvaddr_reg_type is record -- Slave address register
tba : std_ulogic; -- 10-bit address
slvaddr : std_logic_vector((I2CADDRLEN-1) downto 0);
end record;
type i2cslv_reg_bank is record -- APB registers
slvaddr : slvaddr_reg_type;
ctrl : ctrl_reg_type;
sts : sts_reg_type;
msk : sts_reg_type;
receive : std_logic_vector(7 downto 0);
transmit : std_logic_vector(7 downto 0);
end record;
type i2c_in_array is array (filter downto 0) of i2c_in_type;
type slv_state_type is (idle, checkaddr, check10bitaddr, sclhold,
movebyte, handshake);
type i2cslv_reg_type is record
slvstate : slv_state_type;
--
reg : i2cslv_reg_bank;
irq : std_ulogic;
-- Transfer phase
active : boolean;
addr : boolean;
transmit : boolean;
receive : boolean;
-- Shift register
sreg : std_logic_vector(7 downto 0);
cnt : std_logic_vector(2 downto 0);
-- Synchronizers for inputs SCL and SDA
scl : std_ulogic;
sda : std_ulogic;
i2ci : i2c_in_array;
-- Output enables
scloen : std_ulogic;
sdaoen : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Subprograms
-----------------------------------------------------------------------------
-- purpose: Compares the first byte of a received address with the slave's
-- address. The tba input determines if the slave is using a ten bit address.
function compaddr1stb (
ibyte : std_logic_vector(7 downto 0); -- I2C byte
sr : slvaddr_reg_type) -- slave address register
return boolean is
variable correct : std_logic_vector(7 downto 1);
begin -- compaddr1stb
if sr.tba = '1' then
correct(7 downto 3) := TENBIT_ADDR_START;
correct(2 downto 1):= sr.slvaddr((I2CADDRLEN-1) downto (I2CADDRLEN-2));
else
correct(7 downto 1) := sr.slvaddr(6 downto 0);
end if;
return ibyte(7 downto 1) = correct(7 downto 1);
end compaddr1stb;
-- purpose: Compares the 2nd byte of a ten bit address with the slave address
function compaddr2ndb (
ibyte : std_logic_vector(7 downto 0); -- I2C byte
slvaddr : std_logic_vector((I2CADDRLEN-1) downto 0)) -- slave address
return boolean is
begin -- compaddr2ndb
return ibyte((I2CADDRLEN-3) downto 0) = slvaddr((I2CADDRLEN-3) downto 0);
end compaddr2ndb;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Register interface
signal r, rin : i2cslv_reg_type;
begin
comb: process (r, rstn, apbi, i2ci)
variable v : i2cslv_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable apbaddr : std_logic_vector(5 downto 0);
variable apbout : std_logic_vector(31 downto 0);
variable sclfilt : std_logic_vector(filter-1 downto 0);
variable sdafilt : std_logic_vector(filter-1 downto 0);
variable tba : boolean;
begin -- process comb
v := r; v.irq := '0'; irq := (others=>'0'); irq(pirq) := r.irq;
apbaddr := apbi.paddr(7 downto 2); apbout := (others => '0');
v.i2ci(0) := i2ci; v.i2ci(filter downto 1) := r.i2ci(filter-1 downto 0);
tba := false;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when SLV_ADDR =>
apbout(31) := r.reg.slvaddr.tba;
apbout((I2CADDRLEN-1) downto 0) := r.reg.slvaddr.slvaddr;
when CTRL_ADDR =>
apbout(4 downto 0) := r.reg.ctrl.rmode & r.reg.ctrl.tmode &
r.reg.ctrl.tv & r.reg.ctrl.tav & r.reg.ctrl.en;
when STS_ADDR =>
apbout(2 downto 0) := r.reg.sts.rec & r.reg.sts.tra & r.reg.sts.nak;
when MSK_ADDR =>
apbout(2 downto 0) := r.reg.msk.rec & r.reg.msk.tra & r.reg.msk.nak;
when RD_ADDR =>
v.reg.sts.rec := '0';
apbout(7 downto 0) := r.reg.receive;
when TD_ADDR =>
apbout(7 downto 0) := r.reg.transmit;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when SLV_ADDR =>
if HARDCADDR = 0 then
if TENBIT_SUPPORT = 1 then
v.reg.slvaddr.tba := apbi.pwdata(31);
end if;
v.reg.slvaddr.slvaddr := apbi.pwdata((I2CADDRLEN-1) downto 0);
end if;
when CTRL_ADDR =>
v.reg.ctrl.rmode := apbi.pwdata(4);
v.reg.ctrl.tmode := apbi.pwdata(3);
v.reg.ctrl.tv := apbi.pwdata(2);
v.reg.ctrl.tav := apbi.pwdata(1);
v.reg.ctrl.en := apbi.pwdata(0);
when STS_ADDR =>
v.reg.sts.tra := r.reg.sts.tra and not apbi.pwdata(1);
v.reg.sts.nak := r.reg.sts.nak and not apbi.pwdata(0);
when MSK_ADDR =>
v.reg.msk.rec := apbi.pwdata(2);
v.reg.msk.tra := apbi.pwdata(1);
v.reg.msk.nak := apbi.pwdata(0);
when TD_ADDR =>
v.reg.transmit := apbi.pwdata(7 downto 0);
when others => null;
end case;
end if;
----------------------------------------------------------------------------
-- Bus filtering
----------------------------------------------------------------------------
for i in 0 to filter-1 loop
sclfilt(i) := r.i2ci(i+1).scl; sdafilt(i) := r.i2ci(i+1).sda;
end loop; -- i
if andv(sclfilt) = '1' then v.scl := '1'; end if;
if orv(sclfilt) = '0' then v.scl := '0'; end if;
if andv(sdafilt) = '1' then v.sda := '1'; end if;
if orv(sdafilt) = '0' then v.sda := '0'; end if;
---------------------------------------------------------------------------
-- I2C slave control FSM
---------------------------------------------------------------------------
case r.slvstate is
when idle =>
-- Release bus
if (r.scl and not v.scl) = '1' then
v.sdaoen := I2C_HIZ;
end if;
when checkaddr =>
tba := r.reg.slvaddr.tba = '1';
if compaddr1stb(r.sreg, r.reg.slvaddr) then
if r.sreg(0) = I2C_READ then
if (not tba or (tba and r.active)) then
if r.reg.ctrl.tv = '1' then
-- Transmit data
v.transmit := true;
v.slvstate := handshake;
else
-- No data to transmit, NAK
if (not v.reg.sts.nak and r.reg.msk.nak) = '1' then
v.irq := '1';
end if;
v.reg.sts.nak := '1';
v.slvstate := idle;
end if;
else
-- Ten bit address with R/Wn = 1 and slave not previously
-- addressed.
v.slvstate := idle;
end if;
else
v.receive := not tba;
v.slvstate := handshake;
end if;
else
-- Slave address did not match
v.active := false;
v.slvstate := idle;
end if;
v.sreg := r.reg.transmit;
when check10bitaddr =>
if compaddr2ndb(r.sreg, r.reg.slvaddr.slvaddr) then
-- Slave has been addressed with a matching 10 bit address
-- If we receive a repeated start condition, matching address
-- and R/Wn = 1 we will transmit data. Without start condition we
-- will receive data.
v.addr := true;
v.active := true;
v.receive := true;
v.slvstate := handshake;
else
v.slvstate := idle;
end if;
when sclhold =>
-- This state is used when the device has been addressed to see if SCL
-- should be kept low until the receive register is free or the
-- transmit register is filled. It is also used when a data byte has
-- been transmitted or received to SCL low until software acknowledges
-- the transfer.
if (r.scl and not v.scl) = '1' then
v.scloen := I2C_LOW;
v.sdaoen := I2C_HIZ;
end if;
if ((r.receive and (not r.reg.sts.rec or not r.reg.ctrl.rmode) = '1') or
(r.transmit and (r.reg.ctrl.tv or not r.reg.ctrl.tmode) = '1')) then
v.slvstate := movebyte;
v.scloen := I2C_HIZ;
-- Falling edge that should be detected in movebyte may have passed
if r.transmit and v.scl = '0' then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
end if;
end if;
v.sreg := r.reg.transmit;
when movebyte =>
if (r.scl and not v.scl) = '1' then
if r.transmit then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
else
v.sdaoen := I2C_HIZ;
end if;
end if;
if (not r.scl and v.scl) = '1' then
v.sreg := r.sreg(6 downto 0) & r.sda;
if r.cnt = "111" then
if r.addr then
v.slvstate := checkaddr;
elsif r.receive nor r.transmit then
v.slvstate := check10bitaddr;
else
v.slvstate := handshake;
end if;
v.cnt := (others => '0');
else
v.cnt := r.cnt + 1;
end if;
end if;
when handshake =>
-- Falling edge
if (r.scl and not v.scl) = '1' then
if r.addr then
v.sdaoen := I2C_LOW;
elsif r.receive then
-- Receive, send ACK/NAK
-- Acknowledge byte if core has room in receive register
-- This code assumes that the core's receive register is free if we are
-- in RMODE 1. This should always be the case unless software has
-- reconfigured the core during operation.
if r.reg.sts.rec = '0' then
v.sdaoen := I2C_LOW;
v.reg.receive := r.sreg;
if r.reg.msk.rec = '1' then
v.irq := '1';
end if;
v.reg.sts.rec := '1';
else
-- NAK the byte, the master must abort the transfer
v.sdaoen := I2C_HIZ;
v.slvstate := idle;
end if;
else
-- Transmit, release bus
v.sdaoen := I2C_HIZ;
-- Byte transmitted, unset TV unless TAV is set.
v.reg.ctrl.tv := r.reg.ctrl.tav;
-- Set status bit and check if interrupt should be generated
if (not v.reg.sts.tra and r.reg.msk.tra) = '1' then
v.irq := '1';
end if;
v.reg.sts.tra := '1';
end if;
if not r.addr and r.receive and v.sdaoen = I2C_HIZ then
if (not v.reg.sts.nak and r.reg.msk.nak) = '1' then
v.irq := '1';
end if;
v.reg.sts.nak := '1';
end if;
end if;
-- Risinge edge
if (not r.scl and v.scl) = '1' then
if r.addr then
v.slvstate := movebyte;
else
if r.receive then
-- RMODE 0: Be ready to accept one more byte which will be NAK'd if
-- software has not read the receive register
-- RMODE 1: Keep SCL low until software has acknowledged received byte
if r.reg.ctrl.rmode = '0' then
v.slvstate := movebyte;
else
v.slvstate := sclhold;
end if;
else
-- Transmit, check ACK/NAK from master
-- If the master NAKs the transmitted byte the transfer has ended and
-- we should wait for the master's next action. If the master ACKs the
-- byte the core will act depending on tmode:
-- TMODE 0:
-- If the master ACKs the byte we must continue to transmit and will
-- transmit the same byte on all requests.
-- TMODE 1:
-- IF the master ACKs the byte we will keep SCL low until software has
-- put new transmit data into the transmit register.
if r.sda = I2C_ACK then
if r.reg.ctrl.tmode = '0' then
v.slvstate := movebyte;
else
v.slvstate := sclhold;
end if;
else
v.slvstate := idle;
end if;
end if;
end if;
v.addr := false;
v.sreg := r.reg.transmit;
end if;
end case;
if r.reg.ctrl.en = '1' then
-- STOP condition
if (r.scl and v.scl and not r.sda and v.sda) = '1' then
v.active := false;
v.slvstate := idle;
end if;
-- START or repeated START condition
if (r.scl and v.scl and r.sda and not v.sda) = '1' then
v.slvstate := movebyte;
v.cnt := (others => '0');
v.addr := true;
v.transmit := false;
v.receive := false;
end if;
end if;
----------------------------------------------------------------------------
-- Reset and idle operation
----------------------------------------------------------------------------
if rstn = '0' then
v.slvstate := idle;
v.reg.slvaddr.slvaddr := I2CSLVADDR;
if TENBIT_SUPPORT = 1 then v.reg.slvaddr.tba := '1';
else v.reg.slvaddr.tba := '0'; end if;
v.reg.ctrl.en := '0';
v.reg.sts := ('0', '0', '0');
v.scl := '0';
v.active := false;
v.scloen := I2C_HIZ; v.sdaoen := I2C_HIZ;
end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Update registers
rin <= v;
-- Update outputs
apbo.prdata <= apbout;
apbo.pirq <= irq;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
i2co.scl <= '0';
i2co.scloen <= r.scloen;
i2co.sda <= '0';
i2co.sdaoen <= r.sdaoen;
i2co.enable <= r.reg.ctrl.en;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"i2cslv" & tost(pindex) & ": I2C slave rev " &
tost(I2CSLV_REV) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
|
package pkgb is
shared variable v : natural;
end pkgb;
|
-- TwoToFourDecoder implements a two to four bits decoder.
--
-- Copyright (C) 2014 Nicola Cimmino
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see http://www.gnu.org/licenses/.
--
--------------------------------------------------
-- Two to four decoder.
--
-- I 0-1 in Inputs
-- O 0-3 out Outputs
--------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
--------------------------------------------------
entity TwoToFourDecoder is
port(
I: in std_logic_vector(0 to 1);
O : out std_logic_vector(0 to 3)
);
end TwoToFourDecoder;
--------------------------------------------------
architecture Behaviour of TwoToFourDecoder is
begin
process (I)
begin
case I is
when "00"=> O <="0001";
when "01"=> O <="0010";
when "10"=> O <="0100";
when "11"=> O <="1000";
end case;
end process;
end Behaviour;
-------------------------------------------------- |
-- NEED RESULT: ARCH00384.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P11: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P12: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P13: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P14: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P15: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P16: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P17: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P17: Inertial transactions completed entirely passed
-- NEED RESULT: P16: Inertial transactions completed entirely passed
-- NEED RESULT: P15: Inertial transactions completed entirely passed
-- NEED RESULT: P14: Inertial transactions completed entirely passed
-- NEED RESULT: P13: Inertial transactions completed entirely passed
-- NEED RESULT: P12: Inertial transactions completed entirely passed
-- NEED RESULT: P11: Inertial transactions completed entirely passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00384
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00384(ARCH00384)
-- ENT00384_Test_Bench(ARCH00384_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00384 is
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
end ENT00384 ;
--
--
architecture ARCH00384 of ENT00384 is
subtype chk_time_type is Time ;
signal s_boolean_savt : chk_time_type := 0 ns ;
signal s_bit_savt : chk_time_type := 0 ns ;
signal s_severity_level_savt : chk_time_type := 0 ns ;
signal s_character_savt : chk_time_type := 0 ns ;
signal s_st_enum1_savt : chk_time_type := 0 ns ;
signal s_integer_savt : chk_time_type := 0 ns ;
signal s_st_int1_savt : chk_time_type := 0 ns ;
signal s_time_savt : chk_time_type := 0 ns ;
signal s_st_phys1_savt : chk_time_type := 0 ns ;
signal s_real_savt : chk_time_type := 0 ns ;
signal s_st_real1_savt : chk_time_type := 0 ns ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
signal s_st_arr1_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
signal s_st_arr3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_boolean_cnt : chk_cnt_type := 0 ;
signal s_bit_cnt : chk_cnt_type := 0 ;
signal s_severity_level_cnt : chk_cnt_type := 0 ;
signal s_character_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_cnt : chk_cnt_type := 0 ;
signal s_integer_cnt : chk_cnt_type := 0 ;
signal s_st_int1_cnt : chk_cnt_type := 0 ;
signal s_time_cnt : chk_cnt_type := 0 ;
signal s_st_phys1_cnt : chk_cnt_type := 0 ;
signal s_real_cnt : chk_cnt_type := 0 ;
signal s_st_real1_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
signal s_st_arr1_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal boolean_select : select_type := 1 ;
signal bit_select : select_type := 1 ;
signal severity_level_select : select_type := 1 ;
signal character_select : select_type := 1 ;
signal st_enum1_select : select_type := 1 ;
signal integer_select : select_type := 1 ;
signal st_int1_select : select_type := 1 ;
signal time_select : select_type := 1 ;
signal st_phys1_select : select_type := 1 ;
signal real_select : select_type := 1 ;
signal st_real1_select : select_type := 1 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
signal st_arr1_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
signal st_arr3_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_boolean_cnt is
when 0
=> null ;
-- s_boolean <=
-- c_boolean_2 after 10 ns,
-- c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
boolean_select <= transport 2 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
boolean_select <= transport 3 ;
-- s_boolean <=
-- c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 4 ;
-- s_boolean <=
-- c_boolean_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 5 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 6 ;
-- Last transaction above is marked
-- s_boolean <=
-- c_boolean_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_boolean_savt <= transport Std.Standard.Now ;
chk_boolean <= transport s_boolean_cnt
after (1 us - Std.Standard.Now) ;
s_boolean_cnt <= transport s_boolean_cnt + 1 ;
wait until (not s_boolean'Quiet) and
(s_boolean_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_boolean <=
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns
when boolean_select = 1 else
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when boolean_select = 2 else
--
c_boolean_1 after 5 ns
when boolean_select = 3 else
--
c_boolean_1 after 100 ns
when boolean_select = 4 else
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when boolean_select = 5 else
--
-- Last transaction above is marked
c_boolean_1 after 40 ns ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_bit_cnt is
when 0
=> null ;
-- s_bit <=
-- c_bit_2 after 10 ns,
-- c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
bit_select <= transport 2 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
bit_select <= transport 3 ;
-- s_bit <=
-- c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 4 ;
-- s_bit <=
-- c_bit_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 5 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 6 ;
-- Last transaction above is marked
-- s_bit <=
-- c_bit_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_bit_savt <= transport Std.Standard.Now ;
chk_bit <= transport s_bit_cnt
after (1 us - Std.Standard.Now) ;
s_bit_cnt <= transport s_bit_cnt + 1 ;
wait until (not s_bit'Quiet) and
(s_bit_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_bit <=
c_bit_2 after 10 ns,
c_bit_1 after 20 ns
when bit_select = 1 else
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when bit_select = 2 else
--
c_bit_1 after 5 ns
when bit_select = 3 else
--
c_bit_1 after 100 ns
when bit_select = 4 else
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when bit_select = 5 else
--
-- Last transaction above is marked
c_bit_1 after 40 ns ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_severity_level_cnt is
when 0
=> null ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns,
-- c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
severity_level_select <= transport 2 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
severity_level_select <= transport 3 ;
-- s_severity_level <=
-- c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 4 ;
-- s_severity_level <=
-- c_severity_level_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 5 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 6 ;
-- Last transaction above is marked
-- s_severity_level <=
-- c_severity_level_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_severity_level_savt <= transport Std.Standard.Now ;
chk_severity_level <= transport s_severity_level_cnt
after (1 us - Std.Standard.Now) ;
s_severity_level_cnt <= transport s_severity_level_cnt + 1 ;
wait until (not s_severity_level'Quiet) and
(s_severity_level_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_severity_level <=
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns
when severity_level_select = 1 else
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when severity_level_select = 2 else
--
c_severity_level_1 after 5 ns
when severity_level_select = 3 else
--
c_severity_level_1 after 100 ns
when severity_level_select = 4 else
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when severity_level_select = 5 else
--
-- Last transaction above is marked
c_severity_level_1 after 40 ns ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_character_cnt is
when 0
=> null ;
-- s_character <=
-- c_character_2 after 10 ns,
-- c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
character_select <= transport 2 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
character_select <= transport 3 ;
-- s_character <=
-- c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 4 ;
-- s_character <=
-- c_character_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 5 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 6 ;
-- Last transaction above is marked
-- s_character <=
-- c_character_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_character_savt <= transport Std.Standard.Now ;
chk_character <= transport s_character_cnt
after (1 us - Std.Standard.Now) ;
s_character_cnt <= transport s_character_cnt + 1 ;
wait until (not s_character'Quiet) and
(s_character_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
s_character <=
c_character_2 after 10 ns,
c_character_1 after 20 ns
when character_select = 1 else
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when character_select = 2 else
--
c_character_1 after 5 ns
when character_select = 3 else
--
c_character_1 after 100 ns
when character_select = 4 else
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when character_select = 5 else
--
-- Last transaction above is marked
c_character_1 after 40 ns ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_enum1_cnt is
when 0
=> null ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns,
-- c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_select <= transport 2 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
st_enum1_select <= transport 3 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 4 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 5 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1 <=
-- c_st_enum1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_savt <= transport Std.Standard.Now ;
chk_st_enum1 <= transport s_st_enum1_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ;
wait until (not s_st_enum1'Quiet) and
(s_st_enum1_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
s_st_enum1 <=
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns
when st_enum1_select = 1 else
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when st_enum1_select = 2 else
--
c_st_enum1_1 after 5 ns
when st_enum1_select = 3 else
--
c_st_enum1_1 after 100 ns
when st_enum1_select = 4 else
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when st_enum1_select = 5 else
--
-- Last transaction above is marked
c_st_enum1_1 after 40 ns ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_integer_cnt is
when 0
=> null ;
-- s_integer <=
-- c_integer_2 after 10 ns,
-- c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
integer_select <= transport 2 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
integer_select <= transport 3 ;
-- s_integer <=
-- c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 4 ;
-- s_integer <=
-- c_integer_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 5 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 6 ;
-- Last transaction above is marked
-- s_integer <=
-- c_integer_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_integer_savt <= transport Std.Standard.Now ;
chk_integer <= transport s_integer_cnt
after (1 us - Std.Standard.Now) ;
s_integer_cnt <= transport s_integer_cnt + 1 ;
wait until (not s_integer'Quiet) and
(s_integer_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
s_integer <=
c_integer_2 after 10 ns,
c_integer_1 after 20 ns
when integer_select = 1 else
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when integer_select = 2 else
--
c_integer_1 after 5 ns
when integer_select = 3 else
--
c_integer_1 after 100 ns
when integer_select = 4 else
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when integer_select = 5 else
--
-- Last transaction above is marked
c_integer_1 after 40 ns ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_int1_cnt is
when 0
=> null ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns,
-- c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_int1_select <= transport 2 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
st_int1_select <= transport 3 ;
-- s_st_int1 <=
-- c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 4 ;
-- s_st_int1 <=
-- c_st_int1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 5 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_int1 <=
-- c_st_int1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_int1_savt <= transport Std.Standard.Now ;
chk_st_int1 <= transport s_st_int1_cnt
after (1 us - Std.Standard.Now) ;
s_st_int1_cnt <= transport s_st_int1_cnt + 1 ;
wait until (not s_st_int1'Quiet) and
(s_st_int1_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
s_st_int1 <=
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns
when st_int1_select = 1 else
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when st_int1_select = 2 else
--
c_st_int1_1 after 5 ns
when st_int1_select = 3 else
--
c_st_int1_1 after 100 ns
when st_int1_select = 4 else
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when st_int1_select = 5 else
--
-- Last transaction above is marked
c_st_int1_1 after 40 ns ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_time_cnt is
when 0
=> null ;
-- s_time <=
-- c_time_2 after 10 ns,
-- c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
time_select <= transport 2 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
time_select <= transport 3 ;
-- s_time <=
-- c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 4 ;
-- s_time <=
-- c_time_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 5 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 6 ;
-- Last transaction above is marked
-- s_time <=
-- c_time_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_time_savt <= transport Std.Standard.Now ;
chk_time <= transport s_time_cnt
after (1 us - Std.Standard.Now) ;
s_time_cnt <= transport s_time_cnt + 1 ;
wait until (not s_time'Quiet) and
(s_time_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
s_time <=
c_time_2 after 10 ns,
c_time_1 after 20 ns
when time_select = 1 else
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when time_select = 2 else
--
c_time_1 after 5 ns
when time_select = 3 else
--
c_time_1 after 100 ns
when time_select = 4 else
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when time_select = 5 else
--
-- Last transaction above is marked
c_time_1 after 40 ns ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_phys1_cnt is
when 0
=> null ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns,
-- c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_phys1_select <= transport 2 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
st_phys1_select <= transport 3 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 4 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 5 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_phys1 <=
-- c_st_phys1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_phys1_savt <= transport Std.Standard.Now ;
chk_st_phys1 <= transport s_st_phys1_cnt
after (1 us - Std.Standard.Now) ;
s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ;
wait until (not s_st_phys1'Quiet) and
(s_st_phys1_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
s_st_phys1 <=
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns
when st_phys1_select = 1 else
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when st_phys1_select = 2 else
--
c_st_phys1_1 after 5 ns
when st_phys1_select = 3 else
--
c_st_phys1_1 after 100 ns
when st_phys1_select = 4 else
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when st_phys1_select = 5 else
--
-- Last transaction above is marked
c_st_phys1_1 after 40 ns ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_real_cnt is
when 0
=> null ;
-- s_real <=
-- c_real_2 after 10 ns,
-- c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
real_select <= transport 2 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
real_select <= transport 3 ;
-- s_real <=
-- c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 4 ;
-- s_real <=
-- c_real_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 5 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 6 ;
-- Last transaction above is marked
-- s_real <=
-- c_real_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_real_savt <= transport Std.Standard.Now ;
chk_real <= transport s_real_cnt
after (1 us - Std.Standard.Now) ;
s_real_cnt <= transport s_real_cnt + 1 ;
wait until (not s_real'Quiet) and
(s_real_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
s_real <=
c_real_2 after 10 ns,
c_real_1 after 20 ns
when real_select = 1 else
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when real_select = 2 else
--
c_real_1 after 5 ns
when real_select = 3 else
--
c_real_1 after 100 ns
when real_select = 4 else
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when real_select = 5 else
--
-- Last transaction above is marked
c_real_1 after 40 ns ;
--
CHG11 :
process
variable correct : boolean ;
begin
case s_st_real1_cnt is
when 0
=> null ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns,
-- c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P11" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real1_select <= transport 2 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
st_real1_select <= transport 3 ;
-- s_st_real1 <=
-- c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 4 ;
-- s_st_real1 <=
-- c_st_real1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 5 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real1 <=
-- c_st_real1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real1_savt <= transport Std.Standard.Now ;
chk_st_real1 <= transport s_st_real1_cnt
after (1 us - Std.Standard.Now) ;
s_st_real1_cnt <= transport s_st_real1_cnt + 1 ;
wait until (not s_st_real1'Quiet) and
(s_st_real1_savt /= Std.Standard.Now) ;
--
end process CHG11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions completed entirely",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
--
s_st_real1 <=
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns
when st_real1_select = 1 else
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when st_real1_select = 2 else
--
c_st_real1_1 after 5 ns
when st_real1_select = 3 else
--
c_st_real1_1 after 100 ns
when st_real1_select = 4 else
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when st_real1_select = 5 else
--
-- Last transaction above is marked
c_st_real1_1 after 40 ns ;
--
CHG12 :
process
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns,
-- c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P12" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 4 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 5 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1 <=
-- c_st_rec1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
wait until (not s_st_rec1'Quiet) and
(s_st_rec1_savt /= Std.Standard.Now) ;
--
end process CHG12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions completed entirely",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
--
s_st_rec1 <=
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns
when st_rec1_select = 1 else
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when st_rec1_select = 2 else
--
c_st_rec1_1 after 5 ns
when st_rec1_select = 3 else
--
c_st_rec1_1 after 100 ns
when st_rec1_select = 4 else
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when st_rec1_select = 5 else
--
-- Last transaction above is marked
c_st_rec1_1 after 40 ns ;
--
CHG13 :
process
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns,
-- c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P13" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 4 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 5 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec2 <=
-- c_st_rec2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
wait until (not s_st_rec2'Quiet) and
(s_st_rec2_savt /= Std.Standard.Now) ;
--
end process CHG13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions completed entirely",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
--
s_st_rec2 <=
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns
when st_rec2_select = 1 else
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when st_rec2_select = 2 else
--
c_st_rec2_1 after 5 ns
when st_rec2_select = 3 else
--
c_st_rec2_1 after 100 ns
when st_rec2_select = 4 else
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when st_rec2_select = 5 else
--
-- Last transaction above is marked
c_st_rec2_1 after 40 ns ;
--
CHG14 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns,
-- c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P14" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3 <=
-- c_st_rec3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
--
s_st_rec3 <=
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1 after 5 ns
when st_rec3_select = 3 else
--
c_st_rec3_1 after 100 ns
when st_rec3_select = 4 else
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when st_rec3_select = 5 else
--
-- Last transaction above is marked
c_st_rec3_1 after 40 ns ;
--
CHG15 :
process
variable correct : boolean ;
begin
case s_st_arr1_cnt is
when 0
=> null ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns,
-- c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P15" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_select <= transport 2 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
st_arr1_select <= transport 3 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 4 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 5 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr1 <=
-- c_st_arr1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr1_savt <= transport Std.Standard.Now ;
chk_st_arr1 <= transport s_st_arr1_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ;
wait until (not s_st_arr1'Quiet) and
(s_st_arr1_savt /= Std.Standard.Now) ;
--
end process CHG15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions completed entirely",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
--
s_st_arr1 <=
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns
when st_arr1_select = 1 else
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when st_arr1_select = 2 else
--
c_st_arr1_1 after 5 ns
when st_arr1_select = 3 else
--
c_st_arr1_1 after 100 ns
when st_arr1_select = 4 else
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when st_arr1_select = 5 else
--
-- Last transaction above is marked
c_st_arr1_1 after 40 ns ;
--
CHG16 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns,
-- c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P16" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2 <=
-- c_st_arr2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
--
s_st_arr2 <=
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns
when st_arr2_select = 1 else
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when st_arr2_select = 2 else
--
c_st_arr2_1 after 5 ns
when st_arr2_select = 3 else
--
c_st_arr2_1 after 100 ns
when st_arr2_select = 4 else
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when st_arr2_select = 5 else
--
-- Last transaction above is marked
c_st_arr2_1 after 40 ns ;
--
CHG17 :
process
variable correct : boolean ;
begin
case s_st_arr3_cnt is
when 0
=> null ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns,
-- c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P17" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_select <= transport 2 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
st_arr3_select <= transport 3 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 4 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 5 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr3 <=
-- c_st_arr3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr3_savt <= transport Std.Standard.Now ;
chk_st_arr3 <= transport s_st_arr3_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ;
wait until (not s_st_arr3'Quiet) and
(s_st_arr3_savt /= Std.Standard.Now) ;
--
end process CHG17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions completed entirely",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
s_st_arr3 <=
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns
when st_arr3_select = 1 else
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when st_arr3_select = 2 else
--
c_st_arr3_1 after 5 ns
when st_arr3_select = 3 else
--
c_st_arr3_1 after 100 ns
when st_arr3_select = 4 else
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when st_arr3_select = 5 else
--
-- Last transaction above is marked
c_st_arr3_1 after 40 ns ;
--
end ARCH00384 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00384_Test_Bench is
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00384_Test_Bench ;
--
--
architecture ARCH00384_Test_Bench of ENT00384_Test_Bench is
begin
L1:
block
component UUT
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00384 ( ARCH00384 ) ;
begin
CIS1 : UUT
port map (
s_boolean
, s_bit
, s_severity_level
, s_character
, s_st_enum1
, s_integer
, s_st_int1
, s_time
, s_st_phys1
, s_real
, s_st_real1
, s_st_rec1
, s_st_rec2
, s_st_rec3
, s_st_arr1
, s_st_arr2
, s_st_arr3
)
;
end block L1 ;
end ARCH00384_Test_Bench ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity g_ethtx is
generic(
HEAD_AWIDTH : natural := 5;
BUFF_AWIDTH : natural := 5;
FIFO_AWIDTH : natural := 2;
RD_CYCLE : natural := 1;
RD_DELAY : natural := 1;
RAM_AWIDTH : natural := 32
);
port (
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(7 downto 0);
txen : out std_logic;
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
-- ram_raddr : out std_logic_vector(23 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- ram_rdata : in std_logic_vector(7 downto 0);
ram_rdata : in std_logic_vector(31 downto 0);
-- local time --
localtime : in std_logic_vector(31 downto 0)
);
end entity;
architecture arch_ethtx of g_ethtx is
component g_ethtx_output
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 5;
RAM_AWIDTH : NATURAL := 32
);
port(
clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(7 downto 0);
txen : out std_logic;
tx_queue_empty : in std_logic;
tx_head_raddr : out std_logic_vector((HEAD_AWIDTH-1) downto 0);
tx_head_rdata : in std_logic_vector(7 downto 0);
tx_head_rd_block : out std_logic;
db_queue_empty : in std_logic;
db_head_raddr : out std_logic_vector((HEAD_AWIDTH-1) downto 0);
db_head_rdata : in std_logic_vector(7 downto 0);
db_head_rd_block : out std_logic;
buff_raddr : out std_logic_vector((BUFF_AWIDTH-1) downto 0);
buff_rdata : in std_logic_vector(31 downto 0);
dma_start : out std_logic;
-- dma_start_addr : out std_logic_vector(23 downto 0);
dma_start_addr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
dma_length : out std_logic_vector(15 downto 0);
dma_step : out std_logic_vector(7 downto 0);
-- local time --
localtime: in std_logic_vector(31 downto 0)
);
end component;
component Tx_queue
generic(
HEAD_AWIDTH : NATURAL := 5;
FIFO_AWIDTH : NATURAL := 2;
RAM_TYPE : STRING := "DIS_RAM");
port(
clk : in std_logic;
reset : in std_logic;
queue_empty : out std_logic;
head_raddr : in std_logic_vector((HEAD_AWIDTH-1) downto 0);
head_rdata : out std_logic_vector(7 downto 0);
head_rd_block : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0));
end component;
component disdram
generic(
depth : INTEGER;
Dwidth : INTEGER;
Awidth : INTEGER);
port(
A : in std_logic_vector((Awidth-1) downto 0);
CLK : in std_logic;
D : in std_logic_vector((Dwidth-1) downto 0);
WE : in std_logic;
DPRA : in std_logic_vector((Awidth-1) downto 0);
DPO : out std_logic_vector((Dwidth-1) downto 0);
QDPO : out std_logic_vector((Dwidth-1) downto 0));
end component;
component dma_ctrl
generic(
DWIDTH : NATURAL;
RD_CYCLE : NATURAL;
RD_DELAY : NATURAL;
RAM_AWIDTH : NATURAL
);
port(
clk : in std_logic;
reset : in std_logic;
ena : in std_logic;
start : in std_logic;
length : in std_logic_vector(15 downto 0);
start_waddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- start_raddr : in std_logic_vector(23 downto 0);
start_raddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
wstep : in std_logic_vector(7 downto 0);
rstep : in std_logic_vector(7 downto 0);
busy : out std_logic;
-- raddr : out std_logic_vector(23 downto 0);
raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
rdata : in std_logic_vector((DWIDTH-1) downto 0);
wren : out std_logic;
waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
wdata : out std_logic_vector((DWIDTH-1) downto 0));
end component;
signal tx_queue_empty : std_logic;
signal tx_head_raddr : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal tx_head_rdata : std_logic_vector(7 downto 0);
signal tx_head_rd_block : std_logic;
signal db_queue_empty : std_logic;
signal db_head_raddr : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal db_head_rdata : std_logic_vector(7 downto 0);
signal db_head_rd_block : std_logic;
signal buff_raddr : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_rdata : std_logic_vector(31 downto 0);
signal buff_wren : std_logic;
signal buff_waddr : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_wdata : std_logic_vector(31 downto 0);
signal dma_length_byte : std_logic_vector(15 downto 0);
signal dma_length_dword : std_logic_vector(15 downto 0);
-- signal dma_start_raddr : std_logic_vector(23 downto 0);
signal dma_start_raddr_word : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_start_raddr_dword : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_rstep : std_logic_vector(7 downto 0);
signal dma_start : std_logic;
signal dma_busy : std_logic;
-- signal dma_raddr : std_logic_vector(23 downto 0);
signal dma_raddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- signal dma_rdata : std_logic_vector(7 downto 0);
signal dma_rdata : std_logic_vector(31 downto 0);
signal dma_wdata_dword : std_logic_vector(31 downto 0);
signal dma_waddr_dword : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_wren_dword : std_logic;
signal flag : std_logic;
signal buff_waddr_reg : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal buff_wdata_reg : std_logic_vector(31 downto 0);
signal dma_wren_reg : std_logic;
-- signal dma_wren : std_logic;
-- signal dma_waddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- signal dma_wdata : std_logic_vector(7 downto 0);
signal dma_ena : std_logic;
signal buff_wr_diff : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
begin
u_output : g_ethtx_output
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
BUFF_AWIDTH => BUFF_AWIDTH,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
reset => reset,
txclk => txclk,
txd => txd,
txen => txen,
tx_queue_empty => tx_queue_empty,
tx_head_raddr => tx_head_raddr,
tx_head_rdata => tx_head_rdata,
tx_head_rd_block => tx_head_rd_block,
db_queue_empty => db_queue_empty,
db_head_raddr => db_head_raddr,
db_head_rdata => db_head_rdata,
db_head_rd_block => db_head_rd_block,
buff_raddr => buff_raddr,
buff_rdata => buff_rdata,
dma_start => dma_start,
dma_start_addr => dma_start_raddr_word,
dma_length => dma_length_byte,
dma_step => dma_rstep,
-- local time
localtime => localtime
);
u_db_queue : Tx_queue
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => 0,
RAM_TYPE => "DIS_RAM"
)
port map(
clk => clk,
reset => reset,
queue_empty => db_queue_empty,
head_raddr => db_head_raddr,
head_rdata => db_head_rdata,
head_rd_block => db_head_rd_block,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => db_ce,
zcpsm_port_id => db_port_id,
zcpsm_write_strobe => db_write_strobe,
zcpsm_out_port => db_out_port,
zcpsm_read_strobe => db_read_strobe,
zcpsm_in_port => db_in_port
);
u_tx_queue : Tx_queue
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => FIFO_AWIDTH,
RAM_TYPE => "DIS_RAM"
)
port map(
clk => clk,
reset => reset,
queue_empty => tx_queue_empty,
head_raddr => tx_head_raddr,
head_rdata => tx_head_rdata,
head_rd_block => tx_head_rd_block,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => eth_ce,
zcpsm_port_id => eth_port_id,
zcpsm_write_strobe => eth_write_strobe,
zcpsm_out_port => eth_out_port,
zcpsm_read_strobe => eth_read_strobe,
zcpsm_in_port => eth_in_port
);
u_tx_buffer : disdram
generic map(
DEPTH => 2 ** BUFF_AWIDTH,
AWIDTH => BUFF_AWIDTH,
DWIDTH => 32
)
port map(
A => buff_waddr(BUFF_AWIDTH - 1 downto 0),
CLK => clk,
D => buff_wdata,
WE => buff_wren,
DPRA => buff_raddr(BUFF_AWIDTH - 1 downto 0),
DPO => buff_rdata,
QDPO => open
);
u_dma : dma_ctrl
generic map(
DWIDTH => 32,
RD_CYCLE => RD_CYCLE,
RD_DELAY => RD_DELAY,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
reset => reset,
ena => dma_ena,
start => dma_start,
length => dma_length_dword,
start_waddr => (others => '0'),
start_raddr => dma_start_raddr_dword,
wstep => X"01",
rstep => dma_rstep,
busy => dma_busy,
raddr => dma_raddr,
rdata => dma_rdata,
wren => dma_wren_dword,
waddr => dma_waddr_dword,
wdata => dma_wdata_dword
);
----------
dma_length_dword <= "00" & dma_length_byte(15 downto 2);
dma_start_raddr_dword <= '0' & dma_start_raddr_word(RAM_AWIDTH-1 downto 1);
--- process(reset, clk)
---- begin
-- if reset = '1' then
--- wren_byte <= '0';
-- elsif rising_edge(clk) then
-- if dma_wren_byte = '1' then
-- wren_byte <= dma_wren_byte;
-- buff_waddr <= dma_waddr_byte(BUFF_AWIDTH - 1 downto 1)&'0';
-- buff_wdata <= dma_wdata_byte(7 downto 0);
-- elsif flag = '1' then
-- buff_waddr <= dma_waddr_byte(BUFF_AWIDTH - 1 downto 1)&'1';
-- buff_wdata <= dma_wdata_byte(15 downto 8);
-- end if;
-- end if;
-- end process;
process(reset, clk)
begin
if reset = '1' then
buff_waddr_reg <= (others => '0');
buff_wdata_reg <= (others => '0');
dma_wren_reg <= '0';
elsif rising_edge(clk) then
if dma_wren_dword = '1' then
buff_waddr_reg <= dma_waddr_dword;
buff_wdata_reg <= dma_wdata_dword;
end if;
dma_wren_reg <= dma_wren_dword;
end if;
end process;
-- buff_waddr <= buff_waddr_reg(BUFF_AWIDTH - 2 downto 0)&'0' when dma_wren_reg = '1' else
-- buff_waddr_reg(BUFF_AWIDTH - 2 downto 0)&'1' ;
--
-- buff_wdata <= buff_wdata_reg(7 downto 0) when dma_wren_reg = '1' else
-- buff_wdata_reg(15 downto 8);
buff_waddr <= buff_waddr_reg(BUFF_AWIDTH - 1 downto 0);
buff_wdata <= buff_wdata_reg;
process(reset, clk)
begin
if reset = '1' then
flag <= '0';
elsif rising_edge(clk) then
-- if wren_byte = '1' then
flag <= dma_wren_reg;
-- end if;
end if;
end process;
buff_wren <= flag or dma_wren_reg;
ram_raddr <= dma_raddr;
dma_rdata <= ram_rdata;
-- buff_wren <= dma_wren;
-- buff_waddr <= dma_waddr(BUFF_AWIDTH - 1 downto 0);
-- buff_wdata <= dma_wdata;
buff_wr_diff <= buff_waddr - buff_raddr;
p_dma_ena : process(clk, reset)
begin
if reset = '1' then
dma_ena <= '1';
elsif rising_edge(clk) then
if buff_wr_diff >= 2 ** BUFF_AWIDTH - RD_CYCLE - RD_DELAY - 4 then
dma_ena <= '0';
elsif buff_wr_diff <= RD_CYCLE + RD_DELAY + 2 then
dma_ena <= '1';
end if;
end if;
end process;
end arch_ethtx;
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
use work.mypack.all;
use work.myentities.all;
--#------- tute2 ------------------------------------
architecture rtl of tute2 is
type myArr16_u4 is array(0 to 15) of u4;
type LOC_FSM is (
LOC_FSM_state1,
LOC_FSM_state2,
LOC_FSM_idle);
signal nextData: u8; -- reg
signal fsm: MyEnum; -- reg
----- internal regs/wires/etc --------
signal dg_c_memctl: MEM_CTL;
signal dg_c_memres: MEM_RES;
signal dg_o_memres: MEM_RES;
signal dg_w_resXorAnd: u8;
signal dg_c_nextData: u8;
signal dg_c_fsm: MyEnum;
begin
main: process (all)
begin
dg_c_memres <= dg_o_memres; -- reg preload
dg_w_resXorAnd <= X"00"; -- wire pre-zero-init
dg_c_nextData <= nextData; -- reg preload
dg_c_memres.valid <= '0';
dg_c_memres.busy <= '0';
if (memctl.act = '1') then
if (memctl.write = '1') then
dg_c_nextData <= memctl.wdata;
else
dg_c_memres.rdata <= nextData;
dg_c_memres.valid <= '1';
dg_c_nextData <= nextData + X"01";
end if;
end if;
dg_w_resXorAnd <= DoXorAnd(memctl.wdata, nextData, '1');
end process;
----[ sync clock pump for clk ]------
process begin
wait until rising_edge(clk_clk);
dg_o_memres <= dg_c_memres;
nextData <= dg_c_nextData;
fsm <= dg_c_fsm;
if clk_reset_n = '0' then
nextData <= X"22";
fsm <= MyEnum_one;
end if;
end process;
------[ output registers/wires/latches ] --------------
memres <= dg_o_memres;
resXorAnd <= dg_w_resXorAnd;
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: constants_mem_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : constants_mem.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 1
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 1
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY constants_mem_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END constants_mem_prod;
ARCHITECTURE xilinx OF constants_mem_prod IS
COMPONENT constants_mem_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : constants_mem_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
-------------------------------------------------------------------------------
-- Title : Logic Analzyer Data Capture Controller Entity
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : la_ctrl_e.vhd
-- Created : 2016-02-22
-- Last update: 2016-04-10
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- SUMMARY: This entity module is the primary capture controller of the
-- Logic Analyzer. It responsible for matching the trigger mask to the sampled
-- data bus, and the passing the requested amount of data out.
--
-- FUNCTIONAL DESCRIPTION:
-- Upon startup/reset, the controll will wait until the downstream fifo is
-- ready by the asserted fifo_tready before proceeding. Once the fifo is ready,
-- the capture_rdy flag will be asserted. In this state, the controller is
-- continuously reading the parallel triggere mask, trigger value, number of
-- read counts and number of delay counts on the inputs. When the arm command
-- it asserted, these values will be locked in and the ARMED signal will be
-- asserted for the remained of the capture cycle. Once ARMED, the data input
-- (din) will be masked and compared against a the masked trigger values. If
-- there is a match, the controller will either delay for the specified number
-- of delay cycles (delay_cnt_4x) or start capturing data. Data will be captured
-- for the specified depth (ready_cnt_4x).
--
-- SAMPLE RATE CONTROL:
-- During the delay and capture cycles, valid capture cycles will occur when
-- sample_enable is asserted, otherwise the sampled data is not flaged as valid.
-- This allowed for a divided sample rate.
--
-- FIFO Interface:
-- Capured data is deliverd via the output fifo inteface, based upon the
-- AXI-Stream standard. Input sample data is continuously pulled from din
-- and placed on fifo_tdata. Fifo_tvalid indicates is that data should be
-- stored/transmitted as valid data. This allows for minimized logic around
-- the datapath through this module. fifo_tlast will be assered on the last
-- cycle of valid sampled data.
-- NOTE: fifo_tready is only monitored at the start of the capture process.
-- It is checked at the start to make sure that the fifo is ready before data
-- is attempted to be sampled. Traditionally with an AXI-Stream interface a
-- valid transaction occurs when tvalid and tready are both asserted for a
-- give clock cycle; however, since the input data can't be paused, the
-- capture controller must pass the data ever valid cycle of the triggered process.
-------------------------------------------------------I------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-22 1.0 ashton Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY capture_ctrl IS
GENERIC (
DATA_WIDTH : POSITIVE RANGE 1 TO 32 := 8);
PORT (
--top level interafaces
clk : IN STD_LOGIC; -- Clock
rst : IN STD_LOGIC := '0'; -- syncronous reset
din : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); -- input channels
--status indicators
armed : OUT STD_LOGIC; --latched indicator when armed.
triggered : OUT STD_LOGIC; --latched indicator when triggerd.
------message processing interfaces
--serially received reset command. one clock cycle required
rst_cmd : IN STD_LOGIC := '0';
--serially received arm command. one clock cycle required.
arm_cmd : IN STD_LOGIC;
--command to send out a predeterminged ID word
id_cmd : in STD_LOGIC;
--debug command
debug_cmd : in STD_LOGIC;
--sample enable trigger. for subsampling data.
sample_enable : IN STD_LOGIC := '1';
--send a reset pulse to the sample rate clock
sample_cnt_rst : OUT STD_LOGIC;
--number of sample_rate cycles to delay captureing data after trigger has occured.
delay_cnt_4x : IN STD_LOGIC_VECTOR(16-1 DOWNTO 0) := (OTHERS => '0');
--number of samples to read, times four. max==262,140 samples
read_cnt_4x : IN STD_LOGIC_VECTOR(16-1 DOWNTO 0) := (OTHERS => '1');
--parallel trigger bit mask for par_trig_val. latched in on arm_cmd
par_trig_msk : IN STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '0');
--parallel triger values, latched in on arm_cmd
par_trig_val : IN STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '1');
--ready_to_arm indicator
capture_rdy : OUT STD_LOGIC;
--fifo interface
fifo_tdata : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0); --captured
--data output
fifo_tvalid : OUT STD_LOGIC; -- indicating tdata has valid data
fifo_tlast : OUT STD_LOGIC; -- no planned usage
fifo_tready : IN STD_LOGIC := '1'; -- only used on initial setup
fifo_tfull : IN STD_LOGIC := '0'; --no intended use
fifo_tempty : IN STD_LOGIC := '1'; --needs to control capture_rdy
fifo_aresetn : OUT STD_LOGIC; --used to flush fifo in reset cmd.
--dummy placeholder
placeholder : IN STD_LOGIC := '0'
);
BEGIN
-----------------------------------------------------------------------------
-- Architecture Independent Port Assertions
-----------------------------------------------------------------------------
--confirm clk is connected
ASSERT IS_X(clk) = FALSE REPORT "clock is undefined" SEVERITY ERROR;
PROCESS (clk) IS
BEGIN -- PROCESS
IF rising_edge(clk) THEN -- rising clock edge
--cofirm arm_cmd is connected
ASSERT IS_X(arm_cmd) = FALSE REPORT "arm_cmd is undefined" SEVERITY ERROR;
END IF;
END PROCESS;
END ENTITY capture_ctrl;
--See capture_ctrl_a for architecture
|
-- Generated from Simulink block
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity pfb_fir_2048ch_core_ip is
port (
pol0_in0 : in std_logic_vector( 8-1 downto 0 );
pol1_in0 : in std_logic_vector( 8-1 downto 0 );
sync : in std_logic_vector( 32-1 downto 0 );
pol2_in0 : in std_logic_vector( 8-1 downto 0 );
pol2_in1 : in std_logic_vector( 8-1 downto 0 );
pol3_in0 : in std_logic_vector( 8-1 downto 0 );
pol3_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_in1 : in std_logic_vector( 8-1 downto 0 );
pol1_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_out0 : out std_logic_vector( 18-1 downto 0 );
pol1_out0 : out std_logic_vector( 18-1 downto 0 );
sync_out : out std_logic_vector( 1-1 downto 0 );
pol2_out0 : out std_logic_vector( 18-1 downto 0 );
pol3_out0 : out std_logic_vector( 18-1 downto 0 );
pol0_out1 : out std_logic_vector( 18-1 downto 0 );
pol1_out1 : out std_logic_vector( 18-1 downto 0 );
pol2_out1 : out std_logic_vector( 18-1 downto 0 );
pol3_out1 : out std_logic_vector( 18-1 downto 0 );
clk : in std_logic
);
end pfb_fir_2048ch_core_ip;
-- Generated from Simulink block
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity pfb_fir_2048ch_core_ip_struct is
port (
pol0_in0 : in std_logic_vector( 8-1 downto 0 );
pol1_in0 : in std_logic_vector( 8-1 downto 0 );
sync : in std_logic_vector( 32-1 downto 0 );
pol2_in0 : in std_logic_vector( 8-1 downto 0 );
pol2_in1 : in std_logic_vector( 8-1 downto 0 );
pol3_in0 : in std_logic_vector( 8-1 downto 0 );
pol3_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_in1 : in std_logic_vector( 8-1 downto 0 );
pol1_in1 : in std_logic_vector( 8-1 downto 0 );
clk_1 : in std_logic;
ce_1 : in std_logic;
pol0_out0 : out std_logic_vector( 18-1 downto 0 );
pol1_out0 : out std_logic_vector( 18-1 downto 0 );
sync_out : out std_logic_vector( 1-1 downto 0 );
pol2_out0 : out std_logic_vector( 18-1 downto 0 );
pol3_out0 : out std_logic_vector( 18-1 downto 0 );
pol0_out1 : out std_logic_vector( 18-1 downto 0 );
pol1_out1 : out std_logic_vector( 18-1 downto 0 );
pol2_out1 : out std_logic_vector( 18-1 downto 0 );
pol3_out1 : out std_logic_vector( 18-1 downto 0 )
);
end pfb_fir_2048ch_core_ip_struct;
architecture structural of pfb_fir_2048ch_core_ip_struct is
component pfb_fir_2048ch_core_ip
port (
pol0_in0 : in std_logic_vector( 8-1 downto 0 );
pol1_in0 : in std_logic_vector( 8-1 downto 0 );
sync : in std_logic_vector( 32-1 downto 0 );
pol2_in0 : in std_logic_vector( 8-1 downto 0 );
pol2_in1 : in std_logic_vector( 8-1 downto 0 );
pol3_in0 : in std_logic_vector( 8-1 downto 0 );
pol3_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_in1 : in std_logic_vector( 8-1 downto 0 );
pol1_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_out0 : out std_logic_vector( 18-1 downto 0 );
pol1_out0 : out std_logic_vector( 18-1 downto 0 );
sync_out : out std_logic_vector( 1-1 downto 0 );
pol2_out0 : out std_logic_vector( 18-1 downto 0 );
pol3_out0 : out std_logic_vector( 18-1 downto 0 );
pol0_out1 : out std_logic_vector( 18-1 downto 0 );
pol1_out1 : out std_logic_vector( 18-1 downto 0 );
pol2_out1 : out std_logic_vector( 18-1 downto 0 );
pol3_out1 : out std_logic_vector( 18-1 downto 0 );
clk : in std_logic
);
end component;
begin
pfb_fir_2048ch_core_ip_inst : pfb_fir_2048ch_core_ip
port map (
pol0_in0 => pol0_in0,
pol1_in0 => pol1_in0,
sync => sync,
pol2_in0 => pol2_in0,
pol2_in1 => pol2_in1,
pol3_in0 => pol3_in0,
pol3_in1 => pol3_in1,
pol0_in1 => pol0_in1,
pol1_in1 => pol1_in1,
clk => clk_1,
pol0_out0 => pol0_out0,
pol1_out0 => pol1_out0,
sync_out => sync_out,
pol2_out0 => pol2_out0,
pol3_out0 => pol3_out0,
pol0_out1 => pol0_out1,
pol1_out1 => pol1_out1,
pol2_out1 => pol2_out1,
pol3_out1 => pol3_out1
);
end structural;
|
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal clk : std_logic;
signal en : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.ent
port map (clk => clk, enable => en, i => din, o => dout);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
en <= '1';
pulse;
assert dout = '0' severity failure;
din <= '1';
en <= '1';
pulse;
assert dout = '1' severity failure;
din <= '0';
en <= '0';
pulse;
assert dout = '1' severity failure;
wait;
din <= '0';
en <= '1';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
library ieee;
package body fifo_pkg is
end package body;
-- Violation below
package body fifo_pkg is
-- Comments are not allowed
end package body;
library ieee;
package body fifo_pkg is
constant a : std_logic;
end package body;
|
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`protect version = 1
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`protect end_protected
|
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
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-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
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-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
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-- (individually and collectively, "Critical
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-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reset.vhd
-- Description: This entity encompasses the reset logic (soft and hard) for
-- distribution to the axi_vdma core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reset is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_AXI_PRMRY_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_AXI_SCNDRY_ACLK_FREQ_HZ : integer := 100000000
-- Secondary clock frequency in hertz
);
port (
-- Clock Sources
m_axi_sg_aclk : in std_logic ; --
axi_prmry_aclk : in std_logic ; --
--
-- Hard Reset --
axi_resetn : in std_logic ; --
--
-- Soft Reset --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
soft_reset_done : in std_logic ; --
--
--
all_idle : in std_logic ; --
stop : in std_logic ; --
halt : out std_logic := '0' ; --
halt_cmplt : in std_logic ; --
--
-- Secondary Reset --
scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
prmry_resetn : out std_logic := '0' ; --
-- AXI DataMover Primary Reset (Raw) --
dm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_scndry_resetn : out std_logic := '1' ; --
-- AXI Primary Stream Reset Outputs --
prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Alternat Stream Reset Outputs --
altrnt_reset_out_n : out std_logic := '1' --
);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of scndry_resetn : signal is "TRUE";
Attribute KEEP of prmry_resetn : signal is "TRUE";
Attribute KEEP of dm_scndry_resetn : signal is "TRUE";
Attribute KEEP of dm_prmry_resetn : signal is "TRUE";
Attribute KEEP of prmry_reset_out_n : signal is "TRUE";
Attribute KEEP of altrnt_reset_out_n : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_reset_out_n : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of altrnt_reset_out_n: signal is "no";
end axi_dma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Soft Reset Support
signal s_soft_reset_i : std_logic := '0';
signal s_soft_reset_i_d1 : std_logic := '0';
signal s_soft_reset_i_re : std_logic := '0';
signal assert_sftrst_d1 : std_logic := '0';
signal min_assert_sftrst : std_logic := '0';
signal min_assert_sftrst_d1_cdc_tig : std_logic := '0';
--ATTRIBUTE async_reg OF min_assert_sftrst_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF min_assert_sftrst : SIGNAL IS "true";
signal p_min_assert_sftrst : std_logic := '0';
signal sft_rst_dly1 : std_logic := '0';
signal sft_rst_dly2 : std_logic := '0';
signal sft_rst_dly3 : std_logic := '0';
signal sft_rst_dly4 : std_logic := '0';
signal sft_rst_dly5 : std_logic := '0';
signal sft_rst_dly6 : std_logic := '0';
signal sft_rst_dly7 : std_logic := '0';
signal sft_rst_dly8 : std_logic := '0';
signal sft_rst_dly9 : std_logic := '0';
signal sft_rst_dly10 : std_logic := '0';
signal sft_rst_dly11 : std_logic := '0';
signal sft_rst_dly12 : std_logic := '0';
signal sft_rst_dly13 : std_logic := '0';
signal sft_rst_dly14 : std_logic := '0';
signal sft_rst_dly15 : std_logic := '0';
signal sft_rst_dly16 : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
-- Soft Reset to Primary clock domain signals
signal p_soft_reset : std_logic := '0';
signal p_soft_reset_d1_cdc_tig : std_logic := '0';
signal p_soft_reset_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_soft_reset_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_soft_reset_d2 : SIGNAL IS "true";
signal p_soft_reset_d3 : std_logic := '0';
signal p_soft_reset_re : std_logic := '0';
-- Qualified soft reset in primary clock domain for
-- generating mimimum reset pulse for soft reset
signal p_soft_reset_i : std_logic := '0';
signal p_soft_reset_i_d1 : std_logic := '0';
signal p_soft_reset_i_re : std_logic := '0';
-- Graceful halt control
signal halt_cmplt_d1_cdc_tig : std_logic := '0';
signal s_halt_cmplt : std_logic := '0';
--ATTRIBUTE async_reg OF halt_cmplt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_halt_cmplt : SIGNAL IS "true";
signal p_halt_d1_cdc_tig : std_logic := '0';
signal p_halt : std_logic := '0';
--ATTRIBUTE async_reg OF p_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_halt : SIGNAL IS "true";
signal s_halt : std_logic := '0';
-- composite reset (hard and soft)
signal resetn_i : std_logic := '1';
signal scndry_resetn_i : std_logic := '1';
signal axi_resetn_d1_cdc_tig : std_logic := '1';
signal axi_resetn_d2 : std_logic := '1';
--ATTRIBUTE async_reg OF axi_resetn_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF axi_resetn_d2 : SIGNAL IS "true";
signal halt_i : std_logic := '0';
signal p_all_idle : std_logic := '1';
signal p_all_idle_d1_cdc_tig : std_logic := '1';
signal halt_cmplt_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Internal Hard Reset
-- Generate reset on hardware reset or soft reset
-------------------------------------------------------------------------------
resetn_i <= '0' when s_soft_reset_i = '1'
or min_assert_sftrst = '1'
or axi_resetn = '0'
else '1';
-------------------------------------------------------------------------------
-- Minimum Reset Logic for Soft Reset
-------------------------------------------------------------------------------
-- Register to generate rising edge on soft reset and falling edge
-- on reset assertion.
REG_SFTRST_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_soft_reset_i_d1 <= s_soft_reset_i;
assert_sftrst_d1 <= min_assert_sftrst;
-- Register soft reset from DMACR to create
-- rising edge pulse
soft_reset_d1 <= soft_reset;
end if;
end process REG_SFTRST_FOR_RE;
-- rising edge pulse on internal soft reset
s_soft_reset_i_re <= s_soft_reset_i and not s_soft_reset_i_d1;
-- CR605883
-- rising edge pulse on DMACR soft reset
REG_SOFT_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
soft_reset_re <= soft_reset and not soft_reset_d1;
end if;
end process REG_SOFT_RE;
-- falling edge detection on min soft rst to clear soft reset
-- bit in register module
soft_reset_clr <= (not min_assert_sftrst and assert_sftrst_d1)
or (not axi_resetn);
-------------------------------------------------------------------------------
-- Generate Reset for synchronous configuration
-------------------------------------------------------------------------------
GNE_SYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly7 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
-- On soft reset or error
-- mm2s dma controller will idle immediatly
-- sg fetch engine will complete current task and idle (desc's will flush)
-- sg update engine will update all completed descriptors then idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1' and halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(resetn_i = '0')then
halt_i <= '0';
elsif(soft_reset_re = '1' or stop = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- AXI Stream reset output
REG_STRM_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_STRM_RESET_OUT;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream reset output
REG_ALT_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
altrnt_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_ALT_RESET_OUT;
end generate GEN_ALT_RESET_OUT;
-- If in Simple mode or status control stream excluded
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Registered primary and secondary resets out
REG_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_resetn <= resetn_i;
scndry_resetn <= resetn_i;
end if;
end process REG_RESET_OUT;
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn <= resetn_i;
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn <= resetn_i;
end generate GNE_SYNC_RESET;
-------------------------------------------------------------------------------
-- Generate Reset for asynchronous configuration
-------------------------------------------------------------------------------
GEN_ASYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Primary clock is slower or equal to secondary therefore...
-- For Halt - can simply pass secondary clock version of soft reset
-- rising edge into p_halt assertion
-- For Min Rst Assertion - can simply use secondary logic version of min pulse genator
GEN_PRMRY_GRTR_EQL_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ >= C_AXI_SCNDRY_ACLK_FREQ_HZ generate
begin
-- CR605883 - Register to provide pure register output for synchronizer
REG_HALT_CONDITIONS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_halt <= soft_reset_re or stop;
end if;
end process REG_HALT_CONDITIONS;
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
HALT_PROCESS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --p_halt_d1_cdc_tig <= soft_reset_re or stop; -- CR605883
-- p_halt_d1_cdc_tig <= s_halt; -- CR605883
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
-- Adding 5 more flops to make up for 5 stages of Sync flops
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
end generate GEN_PRMRY_GRTR_EQL_SCNDRY;
-- Primary clock is running slower than secondary therefore need to use a primary clock
-- based rising edge version of soft_reset for primary halt assertion
GEN_PRMRY_LESS_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ < C_AXI_SCNDRY_ACLK_FREQ_HZ generate
signal soft_halt_int : std_logic := '0';
begin
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
soft_halt_int <= p_soft_reset_re or stop;
HALT_PROCESS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_halt_int,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_halt_d1_cdc_tig <= p_soft_reset_re or stop;
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
REG_IDLE2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_all_idle,
scndry_vect_out => open
);
-- REG_IDLE2PRMRY : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_all_idle_d1_cdc_tig <= all_idle;
-- p_all_idle <= p_all_idle_d1_cdc_tig;
-- end if;
-- end process REG_IDLE2PRMRY;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(p_all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 primary clocks.
MIN_RESET_ASSERTION : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
p_min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
p_min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-- register minimum reset pulse back to secondary domain
REG_MINRST2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_min_assert_sftrst,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => min_assert_sftrst,
scndry_vect_out => open
);
-- REG_MINRST2SCNDRY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- min_assert_sftrst_d1_cdc_tig <= p_min_assert_sftrst;
-- min_assert_sftrst <= min_assert_sftrst_d1_cdc_tig;
-- end if;
-- end process REG_MINRST2SCNDRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate reset on hardware reset or soft reset if system is idle
REG_P_SOFT_RESET : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_soft_reset = '1'
and p_all_idle = '1'
and halt_cmplt = '1')then
p_soft_reset_i <= '1';
else
p_soft_reset_i <= '0';
end if;
end if;
end process REG_P_SOFT_RESET;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Register qualified soft reset flag for generating rising edge
-- pulse for starting minimum reset pulse
REG_SOFT2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
p_soft_reset_i_d1 <= p_soft_reset_i;
end if;
end process REG_SOFT2PRMRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate rising edge pulse on qualified soft reset for min pulse
-- logic.
p_soft_reset_i_re <= p_soft_reset_i and not p_soft_reset_i_d1;
end generate GEN_PRMRY_LESS_SCNDRY;
-- Double register halt complete flag from primary to secondary
-- clock domain.
-- Note: halt complete stays asserted until halt clears therefore
-- only need to double register from fast to slow clock domain.
process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
halt_cmplt_reg <= halt_cmplt;
end if;
end process;
REG_HALT_CMPLT_IN : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => halt_cmplt_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_halt_cmplt,
scndry_vect_out => open
);
-- REG_HALT_CMPLT_IN : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
--
-- halt_cmplt_d1_cdc_tig <= halt_cmplt;
-- s_halt_cmplt <= halt_cmplt_d1_cdc_tig;
-- end if;
-- end process REG_HALT_CMPLT_IN;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1'
and s_halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Register soft reset flag into primary domain to correcly
-- halt data mover
REG_SOFT2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_reset,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_soft_reset_d2,
scndry_vect_out => open
);
REG_SOFT2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_soft_reset_d1_cdc_tig <= soft_reset;
-- p_soft_reset_d2 <= p_soft_reset_d1_cdc_tig;
p_soft_reset_d3 <= p_soft_reset_d2;
end if;
end process REG_SOFT2PRMRY1;
-- Generate rising edge pulse for use with p_halt creation
p_soft_reset_re <= p_soft_reset_d2 and not p_soft_reset_d3;
-- used to mask halt reset below
p_soft_reset <= p_soft_reset_d2;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(axi_resetn_d2 = '0')then
halt_i <= '0';
elsif(p_halt = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- CR605883 (CDC) Create pure register out for synchronizer
REG_CMB_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn_i <= resetn_i;
end if;
end process REG_CMB_RESET;
-- Sync to mm2s primary and register resets out
REG_RESET_OUT : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => scndry_resetn_i,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => axi_resetn_d2,
scndry_vect_out => open
);
-- REG_RESET_OUT : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --axi_resetn_d1_cdc_tig <= resetn_i; -- CR605883
-- axi_resetn_d1_cdc_tig <= scndry_resetn_i;
-- axi_resetn_d2 <= axi_resetn_d1_cdc_tig;
-- end if;
-- end process REG_RESET_OUT;
-- Register resets out to AXI DMA Logic
REG_SRESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn <= resetn_i;
end if;
end process REG_SRESET_OUT;
-- AXI Stream reset output
prmry_reset_out_n <= axi_resetn_d2;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream alternate reset output
altrnt_reset_out_n <= axi_resetn_d2;
end generate GEN_ALT_RESET_OUT;
-- If in Simple Mode or status control stream excluded.
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Register primary reset
prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Primary Reset
dm_prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Secondary Reset
dm_scndry_resetn <= resetn_i;
end generate GEN_ASYNC_RESET;
end implementation;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.03.2014 15:08:57
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port ( clk_raw : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (7 downto 0);
btn : in STD_LOGIC_VECTOR (4 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0);
VGA_DATA : out STD_LOGIC_VECTOR (11 downto 0);
VGA_HSYNC : out STD_LOGIC;
VGA_VSYNC : out STD_LOGIC
);
end top;
architecture Behavioral of top is
constant vga_width : integer := 1280;
constant vga_height : integer := 1024;
constant dds_mag : integer := 16;
constant delay_length : integer := 14;
constant xwidth : integer := log2(vga_width);
constant ywidth : integer := log2(vga_height);
constant str_chars: integer := 50;
signal dbtn : std_logic_vector(4 downto 0);
signal clk_100MHz: std_logic;
signal clk_250MHz: std_logic;
signal ch1_x: std_logic_vector(xwidth-1 downto 0);
signal ch1_y: std_logic_vector(ywidth-1 downto 0);
signal ch1_trigger: std_logic_vector(ywidth-1 downto 0);
signal ch1_update: std_logic;
signal ch2_x: std_logic_vector(xwidth-1 downto 0);
signal ch2_y: std_logic_vector(ywidth-1 downto 0);
signal ch2_trigger: std_logic_vector(ywidth-1 downto 0);
signal ch2_update: std_logic;
signal mag: std_logic_vector(ywidth-1 downto 0);
signal mostsig: std_logic_vector(5 downto 0);
signal offset: std_logic_vector(ywidth-1 downto 0);
signal trigger1_enable: std_logic;
signal str : String(1 to str_chars);
signal str_std : std_logic_vector(8*str_chars-1 downto 0);
signal vline: std_logic_vector(ywidth-1 downto 0);
signal vline_clear: std_logic;
signal vline_enb: std_logic;
signal vline_enb_buf: std_logic;
signal delay_index: integer range 0 to 13 ;
signal amplitude : std_logic_vector(1 downto 0);
signal phase : std_logic_vector(15 downto 0);
signal dds_out: std_logic_vector(31 downto 0);
alias sine_raw: std_logic_vector(15 downto 0) is dds_out(15 downto 0);
alias cosine_raw: std_logic_vector(15 downto 0) is dds_out(31 downto 16);
signal sine_out: std_logic_vector(dds_mag-1 downto 0);
signal cosine_out: std_logic_vector(dds_mag-1 downto 0);
signal signed_ch1 :std_logic_vector(dds_mag-1 downto 0);
signal signed_ch2 :std_logic_vector(ywidth-1 downto 0);
signal scaled_ch1 :std_logic_vector(dds_mag-1 downto 0);
signal scaled_ch2 :std_logic_vector(ywidth-1 downto 0);
signal sw_buffer : std_logic_vector(7 downto 0);
signal valid: std_logic;
signal nums_of_zeros: integer;
signal w: integer;
signal fe: integer;
signal fir_input: STD_LOGIC_VECTOR(15 DOWNTO 0);
signal fir_output: STD_LOGIC_VECTOR(39 DOWNTO 0);
signal fir_valid: std_logic;
signal fir_ready: std_logic;
signal fir_extracted: std_logic_vector(15 downto 0);
signal time_val: std_logic_vector(6 downto 0);
signal s_axis_active: std_logic;
-----------------------------------------------------------------------
-- DUT signals
----------------------------------------------------------------------
-- Config slave channel signals
signal s_axis_config_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_config_tready : std_logic := '1'; -- slave is ready
signal s_axis_config_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
-- Data slave channel signals
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
signal s_axis_data_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- data payload
signal s_axis_data_tlast : std_logic := '0'; -- indicates end of packet
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tready : std_logic := '1'; -- slave is ready
signal m_axis_data_tdata : std_logic_vector(63 downto 0) := (others => '0'); -- data payload
signal m_axis_data_tuser : std_logic_vector(15 downto 0) := (others => '0'); -- user-defined payload
signal m_axis_data_tlast : std_logic := '0'; -- indicates end of packet
-- Event signals
signal event_frame_started : std_logic := '0';
signal event_tlast_unexpected : std_logic := '0';
signal event_tlast_missing : std_logic := '0';
signal event_status_channel_halt : std_logic := '0';
signal event_data_in_channel_halt : std_logic := '0';
signal event_data_out_channel_halt : std_logic := '0';
alias fft_out_re : std_logic_vector(28 downto 0) is m_axis_data_tdata(28 downto 0);
alias fft_out_im : std_logic_vector(28 downto 0) is m_axis_data_tdata(60 downto 32);
alias fft_out_index:std_logic_vector(11 downto 0) is m_axis_data_tuser(11 downto 0);
signal fft_out_index_buf:std_logic_vector(11*delay_length-1 downto 0);
signal ch1_y_fft_in: std_logic_vector(15 downto 0);
signal sqr_re_i, sqr_im_i : std_logic_vector(28 downto 0);
signal sqr_re_o, sqr_im_o : std_logic_vector(57 downto 0);
signal sqr_summed: std_logic_vector(57 downto 0);
signal scale_sig: std_logic_vector(ywidth-1 downto 0);
signal top_6: std_logic_vector(5 downto 0);
signal mem_out_data,mem_out_data_buf : std_logic_vector(11 downto 0);
signal mem_out_address: std_logic_vector(11 downto 0);
signal white_noise: std_logic_vector(15 downto 0);
component clk_base is
port (
clk_raw : in STD_LOGIC;
clk_250MHz : out STD_LOGIC;
clk_100MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end component;
COMPONENT fir
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
);
END COMPONENT;
COMPONENT fft
PORT (
aclk : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_frame_started : OUT STD_LOGIC;
event_tlast_unexpected:OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_status_channel_halt : OUT STD_LOGIC;
event_data_in_channel_halt : OUT STD_LOGIC;
event_data_out_channel_halt : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT multi_fft PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(57 DOWNTO 0)
);
END COMPONENT;
COMPONENT blk_mem_gen_0
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
component trigger is
generic(
vga_width:integer := 1280;
vga_height:integer := 1024
);
Port ( clk_100MHz : in STD_LOGIC;
enable: in STD_LOGIC;
input: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
value: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
valid: out STD_LOGIC;
output: out STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0);
time_val: in STD_LOGIC_VECTOR(6 downto 0)
);
end component;
component cro is
generic(
vga_width:integer := 1280;
vga_height:integer := 1024
);
Port ( clk_100MHz : in STD_LOGIC;
ch1_x: in STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0);
ch1_y: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
ch1_update: in STD_LOGIC;
ch2_x: in STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0);
ch2_y: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
ch2_update: in STD_LOGIC;
vline: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
vline_enb: in std_logic;
str: in std_logic_vector(8*50-1 downto 0);
VGA_DATA : out STD_LOGIC_VECTOR (11 downto 0);
VGA_HSYNC : out STD_LOGIC;
VGA_VSYNC : out STD_LOGIC
);
end component;
COMPONENT dds
PORT (
aclk : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
type modstate is (set_amplitude,set_phase,set_ch1_trigger,set_bits,set_fe,set_delay);
signal state : modstate;
begin
clk_base1: clk_base port map(clk_raw, clk_250MHz, clk_100MHz, open);
cro1: cro generic map(vga_width,vga_height) port map(clk_100MHz,ch1_x,ch1_y,ch1_update,ch2_x,ch2_y,ch2_update,vline,vline_enb_buf,str_std,VGA_DATA,VGA_HSYNC,VGA_VSYNC);
trigger1: trigger generic map(vga_width,vga_height) port map(clk_100MHz,trigger1_enable,ch1_y,ch1_trigger,ch1_update,ch1_x,(others=>'0'));
--trigger2: trigger generic map(vga_width,vga_height) port map(clk_100MHz,ch2_y,ch2_trigger,ch2_update,ch2_x,(others=>'0'));
dbounce1: debounce port map(clk_100MHz, btn(0), dbtn(0));
dbounce2: debounce port map(clk_100MHz, btn(4), dbtn(4));
dbounce3: debounce port map(clk_100MHz, btn(1), dbtn(1));
dbounce4: debounce port map(clk_100MHz, btn(3), dbtn(3));
--dbounce5: debounce port map(clk_100MHz, btn(2), dbtn(2));
prn1: prn32 generic map(n=>16) port map(clk_100MHz,white_noise);
fir1: fir
PORT MAP (
aclk => clk_100MHz,
s_axis_data_tvalid => '1',
s_axis_data_tready => fir_ready,
s_axis_data_tdata => fir_input,
m_axis_data_tvalid => fir_valid,
m_axis_data_tdata => fir_output
);
bitshift_div1: bitshift_div generic map(size=>dds_mag) port map(amplitude,signed_ch1,scaled_ch1);
sig_gen: dds
PORT MAP (
aclk => clk_100MHz,
s_axis_phase_tvalid => '1',
s_axis_phase_tdata => phase,
m_axis_data_tvalid => valid,
m_axis_data_tdata => dds_out
);
re_sqr: multi_fft
PORT MAP (
CLK => clk_100MHz,
A => sqr_re_i,
B => sqr_re_i,
P => sqr_re_o
);
im_sqr: multi_fft
PORT MAP (
CLK => clk_100MHz,
A => sqr_im_i,
B => sqr_im_i,
P => sqr_im_o
);
fft1: fft
PORT MAP (
aclk => clk_100MHz,
s_axis_config_tdata => X"01", -- fwd_inv
s_axis_config_tvalid => '1',
s_axis_config_tready => s_axis_config_tready,
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => s_axis_data_tlast,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tlast => m_axis_data_tlast,
event_frame_started => event_frame_started,
event_tlast_unexpected => event_tlast_unexpected,
event_tlast_missing => event_tlast_missing,
event_status_channel_halt => event_status_channel_halt,
event_data_in_channel_halt => event_data_in_channel_halt,
event_data_out_channel_halt => event_data_out_channel_halt
);
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
end if;
end process;
process(clk_100MHz)
variable TMP : std_logic;
begin
if(clk_100MHz'event and clk_100MHz='1')then
TMP := '0';
for I in 57 downto 0 loop
if (TMP = '0' and sqr_summed(I) = '1') then
nums_of_zeros <= I;
TMP :='1';
mag <= std_logic_vector( to_unsigned( (nums_of_zeros)*20, ywidth));
case I IS
when 6 to 57 => mostsig <= sqr_summed(I downto I-5);
when 5 => mostsig <= "0"&sqr_summed(I downto I-4);
when 4 => mostsig <= "00"&sqr_summed(I downto I-3);
when 3 => mostsig <= "000"&sqr_summed(I downto I-2);
when 2 => mostsig <= "0000"&sqr_summed(I downto I-1);
when 1 => mostsig <= "00000"&sqr_summed(I downto I-0);
when 0 => mostsig <= (others=>'0');
end case;
end if;
end loop;
case mostsig is
when std_logic_vector(to_unsigned(0,6)) => scale_sig <= std_logic_vector(to_unsigned(0,ywidth)) ;
when std_logic_vector(to_unsigned(1,6)) => scale_sig <= std_logic_vector(to_unsigned(0,ywidth)) ;
when std_logic_vector(to_unsigned(2,6)) => scale_sig <= std_logic_vector(to_unsigned(1,ywidth)) ;
when std_logic_vector(to_unsigned(3,6)) => scale_sig <= std_logic_vector(to_unsigned(1,ywidth)) ;
when std_logic_vector(to_unsigned(4,6)) => scale_sig <= std_logic_vector(to_unsigned(1,ywidth)) ;
when std_logic_vector(to_unsigned(5,6)) => scale_sig <= std_logic_vector(to_unsigned(2,ywidth)) ;
when std_logic_vector(to_unsigned(6,6)) => scale_sig <= std_logic_vector(to_unsigned(2,ywidth)) ;
when std_logic_vector(to_unsigned(7,6)) => scale_sig <= std_logic_vector(to_unsigned(2,ywidth)) ;
when std_logic_vector(to_unsigned(8,6)) => scale_sig <= std_logic_vector(to_unsigned(3,ywidth)) ;
when std_logic_vector(to_unsigned(9,6)) => scale_sig <= std_logic_vector(to_unsigned(3,ywidth)) ;
when std_logic_vector(to_unsigned(10,6)) => scale_sig <= std_logic_vector(to_unsigned(3,ywidth)) ;
when std_logic_vector(to_unsigned(11,6)) => scale_sig <= std_logic_vector(to_unsigned(3,ywidth)) ;
when std_logic_vector(to_unsigned(12,6)) => scale_sig <= std_logic_vector(to_unsigned(4,ywidth)) ;
when std_logic_vector(to_unsigned(13,6)) => scale_sig <= std_logic_vector(to_unsigned(4,ywidth)) ;
when std_logic_vector(to_unsigned(14,6)) => scale_sig <= std_logic_vector(to_unsigned(4,ywidth)) ;
when std_logic_vector(to_unsigned(15,6)) => scale_sig <= std_logic_vector(to_unsigned(5,ywidth)) ;
when std_logic_vector(to_unsigned(16,6)) => scale_sig <= std_logic_vector(to_unsigned(5,ywidth)) ;
when std_logic_vector(to_unsigned(17,6)) => scale_sig <= std_logic_vector(to_unsigned(5,ywidth)) ;
when std_logic_vector(to_unsigned(18,6)) => scale_sig <= std_logic_vector(to_unsigned(6,ywidth)) ;
when std_logic_vector(to_unsigned(19,6)) => scale_sig <= std_logic_vector(to_unsigned(6,ywidth)) ;
when std_logic_vector(to_unsigned(20,6)) => scale_sig <= std_logic_vector(to_unsigned(6,ywidth)) ;
when std_logic_vector(to_unsigned(21,6)) => scale_sig <= std_logic_vector(to_unsigned(7,ywidth)) ;
when std_logic_vector(to_unsigned(22,6)) => scale_sig <= std_logic_vector(to_unsigned(7,ywidth)) ;
when std_logic_vector(to_unsigned(23,6)) => scale_sig <= std_logic_vector(to_unsigned(7,ywidth)) ;
when std_logic_vector(to_unsigned(24,6)) => scale_sig <= std_logic_vector(to_unsigned(8,ywidth)) ;
when std_logic_vector(to_unsigned(25,6)) => scale_sig <= std_logic_vector(to_unsigned(8,ywidth)) ;
when std_logic_vector(to_unsigned(26,6)) => scale_sig <= std_logic_vector(to_unsigned(8,ywidth)) ;
when std_logic_vector(to_unsigned(27,6)) => scale_sig <= std_logic_vector(to_unsigned(9,ywidth)) ;
when std_logic_vector(to_unsigned(28,6)) => scale_sig <= std_logic_vector(to_unsigned(9,ywidth)) ;
when std_logic_vector(to_unsigned(29,6)) => scale_sig <= std_logic_vector(to_unsigned(9,ywidth)) ;
when std_logic_vector(to_unsigned(30,6)) => scale_sig <= std_logic_vector(to_unsigned(10,ywidth)) ;
when std_logic_vector(to_unsigned(31,6)) => scale_sig <= std_logic_vector(to_unsigned(10,ywidth)) ;
when std_logic_vector(to_unsigned(32,6)) => scale_sig <= std_logic_vector(to_unsigned(10,ywidth)) ;
when std_logic_vector(to_unsigned(33,6)) => scale_sig <= std_logic_vector(to_unsigned(10,ywidth)) ;
when std_logic_vector(to_unsigned(34,6)) => scale_sig <= std_logic_vector(to_unsigned(11,ywidth)) ;
when std_logic_vector(to_unsigned(35,6)) => scale_sig <= std_logic_vector(to_unsigned(11,ywidth)) ;
when std_logic_vector(to_unsigned(36,6)) => scale_sig <= std_logic_vector(to_unsigned(11,ywidth)) ;
when std_logic_vector(to_unsigned(37,6)) => scale_sig <= std_logic_vector(to_unsigned(12,ywidth)) ;
when std_logic_vector(to_unsigned(38,6)) => scale_sig <= std_logic_vector(to_unsigned(12,ywidth)) ;
when std_logic_vector(to_unsigned(39,6)) => scale_sig <= std_logic_vector(to_unsigned(12,ywidth)) ;
when std_logic_vector(to_unsigned(40,6)) => scale_sig <= std_logic_vector(to_unsigned(13,ywidth)) ;
when std_logic_vector(to_unsigned(41,6)) => scale_sig <= std_logic_vector(to_unsigned(13,ywidth)) ;
when std_logic_vector(to_unsigned(42,6)) => scale_sig <= std_logic_vector(to_unsigned(13,ywidth)) ;
when std_logic_vector(to_unsigned(43,6)) => scale_sig <= std_logic_vector(to_unsigned(14,ywidth)) ;
when std_logic_vector(to_unsigned(44,6)) => scale_sig <= std_logic_vector(to_unsigned(14,ywidth)) ;
when std_logic_vector(to_unsigned(45,6)) => scale_sig <= std_logic_vector(to_unsigned(14,ywidth)) ;
when std_logic_vector(to_unsigned(46,6)) => scale_sig <= std_logic_vector(to_unsigned(15,ywidth)) ;
when std_logic_vector(to_unsigned(47,6)) => scale_sig <= std_logic_vector(to_unsigned(15,ywidth)) ;
when std_logic_vector(to_unsigned(48,6)) => scale_sig <= std_logic_vector(to_unsigned(15,ywidth)) ;
when std_logic_vector(to_unsigned(49,6)) => scale_sig <= std_logic_vector(to_unsigned(16,ywidth)) ;
when std_logic_vector(to_unsigned(50,6)) => scale_sig <= std_logic_vector(to_unsigned(16,ywidth)) ;
when std_logic_vector(to_unsigned(51,6)) => scale_sig <= std_logic_vector(to_unsigned(16,ywidth)) ;
when std_logic_vector(to_unsigned(52,6)) => scale_sig <= std_logic_vector(to_unsigned(17,ywidth)) ;
when std_logic_vector(to_unsigned(53,6)) => scale_sig <= std_logic_vector(to_unsigned(17,ywidth)) ;
when std_logic_vector(to_unsigned(54,6)) => scale_sig <= std_logic_vector(to_unsigned(17,ywidth)) ;
when std_logic_vector(to_unsigned(55,6)) => scale_sig <= std_logic_vector(to_unsigned(17,ywidth)) ;
when std_logic_vector(to_unsigned(56,6)) => scale_sig <= std_logic_vector(to_unsigned(18,ywidth)) ;
when std_logic_vector(to_unsigned(57,6)) => scale_sig <= std_logic_vector(to_unsigned(18,ywidth)) ;
when std_logic_vector(to_unsigned(58,6)) => scale_sig <= std_logic_vector(to_unsigned(18,ywidth)) ;
when std_logic_vector(to_unsigned(59,6)) => scale_sig <= std_logic_vector(to_unsigned(19,ywidth)) ;
when std_logic_vector(to_unsigned(60,6)) => scale_sig <= std_logic_vector(to_unsigned(19,ywidth)) ;
when std_logic_vector(to_unsigned(61,6)) => scale_sig <= std_logic_vector(to_unsigned(19,ywidth)) ;
when std_logic_vector(to_unsigned(62,6)) => scale_sig <= std_logic_vector(to_unsigned(20,ywidth)) ;
when std_logic_vector(to_unsigned(63,6)) => scale_sig <= std_logic_vector(to_unsigned(20,ywidth)) ;
end case;
end if;
end process;
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
fir_input <= white_noise;
fir_extracted <= fir_output(fe + 15 downto fe);
end if;
end process;
-- signal str : String(1 to 50) := "hold time violation";
-- signal str_std : std_logic_vector(8*50-1 downto 0);
GEN_str_buf: for I in 0 to 49 generate
str_std(I*8+7 downto I*8) <= char2std(str(I+1));
end generate;
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
--led <= str_test;
ch2_update <= '1';
--ch2_y <= vga_height/2;
ch2_y <= mag + scale_sig;--(sqr_summed((ywidth-1)+w downto w));
--ch2_x <= fft_out_index(10 downto 0);
ch1_y_fft_in <= scaled_ch1;
ch1_y <= scaled_ch1(scaled_ch1'length-1 downto (scaled_ch1'length-1)-(ch1_y'length)+1);
--ch2_y <= signed_ch2;
if(sw(0) = '0')then
signed_ch1 <= std_logic_vector(signed(sine_raw));
trigger1_enable <= '1';
else
trigger1_enable <= '0';
if(sw(1) = '0')then
signed_ch1 <= std_logic_vector(signed(white_noise));
else
signed_ch1 <= std_logic_vector(signed(fir_extracted));
end if;
end if;
--signed_ch2 <= std_logic_vector(resize(signed(cosine_raw),ywidth));
end if;
end process;
-- input
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
-- led(0) <= s_axis_active;
-- led(1) <= s_axis_data_tvalid;
-- led(2) <= m_axis_data_tvalid;
-- led(3) <= m_axis_data_tready;
-- led(4) <= s_axis_data_tready;
-- led(5) <= event_status_channel_halt;
-- led(6) <= event_data_in_channel_halt;
--led(7) <= event_data_out_channel_halt;
sqr_summed <= sqr_re_o + sqr_im_o;
if(s_axis_active = '1')then
s_axis_data_tlast <= '0';
end if;
if( s_axis_data_tready = '1' and s_axis_active = '0' and ch1_x = "000000000000")then
s_axis_data_tvalid <= '1';
s_axis_active <= '1';
s_axis_data_tdata(15 downto 0) <= ch1_y_fft_in;
end if;
if(s_axis_active = '1' and ch1_x /= "000000000000")then
s_axis_data_tdata(15 downto 0) <= ch1_y_fft_in;
elsif(s_axis_active = '1' and ch1_x > 4096)then
s_axis_data_tvalid <= '0';
s_axis_active <= '0';
elsif(s_axis_active = '1' and ch1_x = 4096)then
s_axis_data_tlast <= '1';
end if;
end if;
end process;-- output fft
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
ch2_x <= fft_out_index_buf(11*delay_length-1 downto 11*(delay_length-1)); -- pop
--ch2_y <= sqr_summed(57 downto 47);
if( m_axis_data_tvalid = '1' )then
sqr_re_i <= fft_out_re;
sqr_im_i <= fft_out_im;
if(fft_out_index < 4096/2)then
fft_out_index_buf <= fft_out_index_buf(11*(delay_length-1)-1 downto 0) & (fft_out_index(10 downto 0)); --push
else
fft_out_index_buf <= (others=>'1'); -- off screen
end if;
-- if(m_axis_data_tlast = '1')then
-- end if;
end if;
end if;
end process;
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
vline_enb_buf <= vline_enb;
end if;
end process;
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
--set values
case state is
when set_amplitude =>
str <= "set amplitude ";
vline_enb <= '0';
if(dbtn(0) = '1')then
amplitude <= amplitude + 1;
elsif(dbtn(4) = '1')then
amplitude <= amplitude - 1;
end if;
when set_phase =>
str <= "set phase ";
vline_enb <= '0';
if(dbtn(0) = '1')then
phase <= phase + 1;
elsif(dbtn(4) = '1')then
phase <= phase - 1;
end if;
when set_ch1_trigger =>
str <= "set ch1 trigger ";
vline_enb <= '1';
vline <= ch1_trigger;
if(dbtn(0) = '1')then
ch1_trigger <= ch1_trigger + 1;
elsif(dbtn(4) = '1')then
ch1_trigger <= ch1_trigger - 1;
end if;
when set_bits =>
str <= "set fft index ";
vline_enb <= '0';
if(dbtn(0) = '1')then
w <= w + 1;
elsif(dbtn(4) = '1')then
w <= w - 1;
end if;
when set_fe =>
str <= "set filter index ";
vline_enb <= '0';
if(dbtn(0) = '1')then
fe <= fe + 1;
elsif(dbtn(4) = '1')then
fe <= fe - 1;
end if;
when set_delay =>
str <= "set delay index ";
vline_enb <= '0';
if(dbtn(0) = '1')then
delay_index <= delay_index + 1;
elsif(dbtn(4) = '1')then
delay_index <= delay_index - 1;
end if;
end case;
end if;
end process;
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
--change mode
if(dbtn(1) = '1')then
case state is
when set_amplitude =>
state <= set_phase;
when set_phase =>
state <= set_ch1_trigger;
when set_ch1_trigger =>
state <= set_bits;
when set_bits =>
state <= set_fe;
when set_fe =>
state <= set_delay;
when set_delay =>
state <= set_amplitude;
end case;
elsif(dbtn(3) = '1')then
case state is
when set_amplitude =>
state <= set_delay;
when set_phase =>
state <= set_amplitude;
when set_ch1_trigger =>
state <= set_phase;
when set_bits =>
state <= set_ch1_trigger;
when set_fe =>
state <= set_bits;
when set_delay =>
state <= set_fe;
end case;
end if;
sw_buffer <= sw;
end if;
end process;
end Behavioral;
|
entity ee is end entity;
architecture aa of ee is
type int_ptr is access integer;
type bv_ptr is access bit_vector;
begin
process is
variable x, p : int_ptr;
variable v : integer;
variable a : bv_ptr;
variable q : bit_vector(1 to 3);
variable r : bit;
begin
x.all := 1;
v := x.all + 5;
p := new integer;
q := a.all(1 to 3);
r := a.all(3);
end process;
end architecture;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:router:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_router_20_0 IS
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END sys_router_20_0;
ARCHITECTURE sys_router_20_0_arch OF sys_router_20_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_router_20_0_arch: ARCHITECTURE IS "yes";
COMPONENT router_struct IS
GENERIC (
ADDR_X : INTEGER;
ADDR_Y : INTEGER;
N_INST : BOOLEAN;
S_INST : BOOLEAN;
E_INST : BOOLEAN;
W_INST : BOOLEAN
);
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END COMPONENT router_struct;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLOCK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLOCK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF L_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF L_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF W_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF W_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF W_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF W_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF W_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF W_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TREADY";
BEGIN
U0 : router_struct
GENERIC MAP (
ADDR_X => 2,
ADDR_Y => 1,
N_INST => true,
S_INST => true,
E_INST => false,
W_INST => true
)
PORT MAP (
CLOCK => CLOCK,
RESET => RESET,
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => L_RIN,
L_DOUT => L_DOUT,
L_VOUT => L_VOUT,
L_ROUT => L_ROUT,
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => N_RIN,
N_DOUT => N_DOUT,
N_VOUT => N_VOUT,
N_ROUT => N_ROUT,
S_DIN => S_DIN,
S_VIN => S_VIN,
S_RIN => S_RIN,
S_DOUT => S_DOUT,
S_VOUT => S_VOUT,
S_ROUT => S_ROUT,
E_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
E_VIN => '0',
E_ROUT => '0',
W_DIN => W_DIN,
W_VIN => W_VIN,
W_RIN => W_RIN,
W_DOUT => W_DOUT,
W_VOUT => W_VOUT,
W_ROUT => W_ROUT
);
END sys_router_20_0_arch;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
entity syncram_banked_1r1w_inferred is
generic (
addr_bits : natural := 1;
word_bits : natural := 1;
log2_banks : natural := 0;
write_first : boolean := true
);
port (
clk : in std_ulogic;
we : in std_ulogic;
wbanken : in std_ulogic_vector(2**log2_banks-1 downto 0);
waddr : in std_ulogic_vector(addr_bits-1 downto 0);
wdata : in std_ulogic_vector2(2**log2_banks-1 downto 0, word_bits-1 downto 0);
re : in std_ulogic;
rbanken : in std_ulogic_vector(2**log2_banks-1 downto 0);
raddr : in std_ulogic_vector(addr_bits-1 downto 0);
rdata : out std_ulogic_vector2(2**log2_banks-1 downto 0, word_bits-1 downto 0)
);
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04.03.2016 11:22:26
-- Design Name:
-- Module Name: rem_testbench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity add64_testbench is
end add64_testbench;
architecture Behavioural of add64_testbench is
signal sig_i00, sig_i01, sig_i02, sig_r00, sig_r01, sig_r02, sig_FP, sig_FPout,sig_MDAT : std_logic_vector(31 DOWNTO 0);
signal sig_reset, sig_CLK, sig_MWAIT : std_logic;
component ADD64CoreAndMemory is
PORT (
in0 : IN std_logic_vector(31 DOWNTO 0);
in1 : IN std_logic_vector(31 DOWNTO 0);
in2 : IN std_logic_vector(31 DOWNTO 0);
out0 : OUT std_logic_vector(31 DOWNTO 0);
out1 : OUT std_logic_vector(31 DOWNTO 0);
out2 : OUT std_logic_vector(31 DOWNTO 0);
frame_pointer : IN std_logic_vector(31 DOWNTO 0);
frame_pointer_out : OUT std_logic_vector(31 DOWNTO 0);
rst : IN std_logic;
clck : IN std_logic;
mem_wait : IN std_logic;
mem_push : IN std_logic_vector(31 DOWNTO 0)
);
end component;
begin
uut: ADD64CoreAndMemory
port map (
in0 => sig_i00,
in1 => sig_i01,
in2 => sig_i02,
out0 => sig_r00,
out1 => sig_r01,
out2 => sig_r02,
frame_pointer => sig_FP,
frame_pointer_out => sig_FPout,
rst => sig_reset,
clck => sig_CLK,
mem_wait => sig_MWAIT,
mem_push => sig_MDAT
);
clock: process
constant clock_period:time := 40ns;
begin
wait for 200ns;
for I in 0 to 10 loop
sig_CLK <= '0';
wait for clock_period/2;
sig_CLK <= '1';
wait for clock_period/2;
end loop;
wait;
end process clock;
test: process begin
sig_MWAIT <= '1';
sig_reset <= '1';
wait for 100ns;
sig_reset <= '0';
wait for 100ns;
sig_i00 <= "00000000000000000000000001010000";
sig_i01 <= "00000000000000000000000100000000";
sig_i02 <= "00000000000000000000001000000000";
sig_FP <= "00000000000000000000000000000010";
sig_MDAT <= "00000000000000000000001100000000";
wait;
end process test;
end Behavioural;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for vgca_top_tb
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:40:14 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca_top_tb-rtl-conf-c.vhd,v 1.2 2004/08/18 10:46:57 wig Exp $
-- $Date: 2004/08/18 10:46:57 $
-- $Log: vgca_top_tb-rtl-conf-c.vhd,v $
-- Revision 1.2 2004/08/18 10:46:57 wig
-- reworked some testcases
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration vgca_top_tb_rtl_conf / vgca_top_tb
--
configuration vgca_top_tb_rtl_conf of vgca_top_tb is
for rtl
-- Generated Configuration
for dut : vgca_top
use configuration work.vgca_top_struct_conf;
end for;
end for;
end vgca_top_tb_rtl_conf;
--
-- End of Generated Configuration vgca_top_tb_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;
entity Adder is
generic(
N : positive := 4
);
port(
A : in std_logic_vector(N-1 downto 0);
B : in std_logic_vector(N-1 downto 0);
Cin : in std_logic;
Sum : out std_logic_vector(N-1 downto 0);
Cout : out std_logic
);
end Adder;
architecture RTL of Adder is
signal cout_sum: std_logic_vector(Sum'length downto 0);
begin
-- This works fine:
-- cout_sum <= ("0" & A) + B + Cin;
-- Cout <= cout_sum(Sum'length);
-- Sum <= cout_sum(Sum'length-1 downto 0);
-- This crashes GHDL:
(Cout, Sum) <= ("0" & A) + B + Cin;
end RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DEL is port(
D : in std_logic;
E : in std_logic;
Q, nQ : out std_logic
);
end DEL;
architecture DEL of DEL is
component RSL is port(
S,R : in std_logic;
Q, nQ : out std_logic
);
end component;
component NOT1 is port(
a : in std_logic;
z : out std_logic
);
end component;
component AND2 is port(
a,b: in std_logic;
z: out std_logic
);
end component;
signal nD : std_logic;
signal DE : std_logic;
signal nDE : std_logic;
begin
M1: NOT1 port map (D, nD);
M2: AND2 port map (D, E, DE);
M3: AND2 port map (nD, E, nDE);
M4: RSL port map (DE, nDE, Q, nQ);
end DEL;
|
--
-- This file is part of top_test_fsm_implem
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_test_fsm_implem is
Port ( clk : in STD_LOGIC;
w1a : inout STD_LOGIC_VECTOR (15 downto 0));
end top_test_fsm_implem;
architecture Behavioral of top_test_fsm_implem is
signal reset : std_logic;
signal output : std_logic;
begin
-- inst_fsm_implem : entity work.fsm_implem(Test)
-- inst_fsm_implem : entity work.fsm_implem(Simple)
-- inst_fsm_implem : entity work.fsm_implem(Naive)
inst_fsm_implem : entity work.fsm_implem(Trial)
port map (
clk => clk,
rst => reset,
output => output
);
w1a(0) <= output;
reset <= '0';
generate_w1a : for I in 1 to 15 generate
w1a(I) <= '0';
end generate generate_w1a;
end Behavioral;
|
----------------------------------------------------------------------------------------------
--
-- Input file : sram_4en.vhd
-- Design name : sram_4en
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Single Port Synchronous Random Access Memory with 4 write enable
-- ports.
-- Architecture 'arch' : Default implementation
-- Architecture 'arch2' : Alternative implementation
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.std_Pkg.all;
entity sram_4en is generic
(
WIDTH : positive := 32;
SIZE : positive := 16
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic_vector(WIDTH/8 - 1 downto 0);
ena_i : in std_logic;
clk_i : in std_logic
);
end sram_4en;
-- Although this memory is very easy to use in conjunction with Modelsims mem load, it is not
-- supported by many devices (although it comes straight from the library. Many devices give
-- cryptic synthesization errors on this implementation, so it is not the default.
architecture arch2 of sram_4en is
type ram_type is array(2 ** SIZE - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
type sel_type is array(WIDTH/8 - 1 downto 0) of std_logic_vector(7 downto 0);
signal ram: ram_type;
signal di: sel_type;
begin
process(wre_i, dat_i, adr_i)
begin
for i in 0 to WIDTH/8 - 1 loop
if wre_i(i) = '1' then
di(i) <= dat_i((i+1)*8 - 1 downto i*8);
else
di(i) <= ram(my_conv_integer(adr_i))((i+1)*8 - 1 downto i*8);
end if;
end loop;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if ena_i = '1' then
ram(my_conv_integer(adr_i)) <= di(3) & di(2) & di(1) & di(0);
dat_o <= di(3) & di(2) & di(1) & di(0);
end if;
end if;
end process;
end arch2;
-- Less convenient but very general memory block with four separate write
-- enable signals. (4x8 bit)
architecture arch of sram_4en is
begin
mem: for i in 0 to WIDTH/8 - 1 generate
mem : sram generic map
(
WIDTH => 8,
SIZE => SIZE
)
port map
(
dat_o => dat_o((i+1)*8 - 1 downto i*8),
dat_i => dat_i((i+1)*8 - 1 downto i*8),
adr_i => adr_i,
wre_i => wre_i(i),
ena_i => ena_i,
clk_i => clk_i
);
end generate;
end arch;
|
----------------------------------------------------------------------------------------------
--
-- Input file : sram_4en.vhd
-- Design name : sram_4en
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Single Port Synchronous Random Access Memory with 4 write enable
-- ports.
-- Architecture 'arch' : Default implementation
-- Architecture 'arch2' : Alternative implementation
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.std_Pkg.all;
entity sram_4en is generic
(
WIDTH : positive := 32;
SIZE : positive := 16
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic_vector(WIDTH/8 - 1 downto 0);
ena_i : in std_logic;
clk_i : in std_logic
);
end sram_4en;
-- Although this memory is very easy to use in conjunction with Modelsims mem load, it is not
-- supported by many devices (although it comes straight from the library. Many devices give
-- cryptic synthesization errors on this implementation, so it is not the default.
architecture arch2 of sram_4en is
type ram_type is array(2 ** SIZE - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
type sel_type is array(WIDTH/8 - 1 downto 0) of std_logic_vector(7 downto 0);
signal ram: ram_type;
signal di: sel_type;
begin
process(wre_i, dat_i, adr_i)
begin
for i in 0 to WIDTH/8 - 1 loop
if wre_i(i) = '1' then
di(i) <= dat_i((i+1)*8 - 1 downto i*8);
else
di(i) <= ram(my_conv_integer(adr_i))((i+1)*8 - 1 downto i*8);
end if;
end loop;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if ena_i = '1' then
ram(my_conv_integer(adr_i)) <= di(3) & di(2) & di(1) & di(0);
dat_o <= di(3) & di(2) & di(1) & di(0);
end if;
end if;
end process;
end arch2;
-- Less convenient but very general memory block with four separate write
-- enable signals. (4x8 bit)
architecture arch of sram_4en is
begin
mem: for i in 0 to WIDTH/8 - 1 generate
mem : sram generic map
(
WIDTH => 8,
SIZE => SIZE
)
port map
(
dat_o => dat_o((i+1)*8 - 1 downto i*8),
dat_i => dat_i((i+1)*8 - 1 downto i*8),
adr_i => adr_i,
wre_i => wre_i(i),
ena_i => ena_i,
clk_i => clk_i
);
end generate;
end arch;
|
entity assert2 is
end entity;
architecture test of assert2 is
signal x : integer;
begin
process is
begin
x <= 5;
wait for 1 ns;
x <= 12;
wait for 1 ns;
wait;
end process;
assert x < 10 report "x >= 10" severity warning;
end architecture;
|
entity assert2 is
end entity;
architecture test of assert2 is
signal x : integer;
begin
process is
begin
x <= 5;
wait for 1 ns;
x <= 12;
wait for 1 ns;
wait;
end process;
assert x < 10 report "x >= 10" severity warning;
end architecture;
|
entity assert2 is
end entity;
architecture test of assert2 is
signal x : integer;
begin
process is
begin
x <= 5;
wait for 1 ns;
x <= 12;
wait for 1 ns;
wait;
end process;
assert x < 10 report "x >= 10" severity warning;
end architecture;
|
entity assert2 is
end entity;
architecture test of assert2 is
signal x : integer;
begin
process is
begin
x <= 5;
wait for 1 ns;
x <= 12;
wait for 1 ns;
wait;
end process;
assert x < 10 report "x >= 10" severity warning;
end architecture;
|
entity assert2 is
end entity;
architecture test of assert2 is
signal x : integer;
begin
process is
begin
x <= 5;
wait for 1 ns;
x <= 12;
wait for 1 ns;
wait;
end process;
assert x < 10 report "x >= 10" severity warning;
end architecture;
|
-- $Id: tb_nexys4d.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4d - sim
-- Description: Test bench for nexys4d (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_nexys4d_core
-- serport/tb/serport_master_tb
-- nexys4d_aif [UUT]
--
-- To test: generic, any nexys4d_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2016.2-2018.2; ghdl 0.33-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.0.1 use sfs_gsim_core
-- 2017-01-04 838 1.0 Initial version (derived from tb_nexys4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys4dlib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys4d is
end tb_nexys4d;
architecture sim of tb_nexys4d is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_nexys4d_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
UUT : nexys4d_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hls_saturation_enbkb_div_u is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
function max (left, right : INTEGER) return INTEGER is
begin
if left > right then return left;
else return right;
end if;
end max;
end entity;
architecture rtl of hls_saturation_enbkb_div_u is
constant cal_WIDTH : INTEGER := max(in0_WIDTH, in1_WIDTH);
type in0_vector is array(INTEGER range <>) of UNSIGNED(in0_WIDTH-1 downto 0);
type in1_vector is array(INTEGER range <>) of UNSIGNED(in1_WIDTH-1 downto 0);
type cal_vector is array(INTEGER range <>) of UNSIGNED(cal_WIDTH downto 0);
signal dividend_tmp : in0_vector(0 to in0_WIDTH);
signal divisor_tmp : in1_vector(0 to in0_WIDTH);
signal remd_tmp : in0_vector(0 to in0_WIDTH);
signal comb_tmp : in0_vector(0 to in0_WIDTH-1);
signal cal_tmp : cal_vector(0 to in0_WIDTH-1);
begin
quot <= STD_LOGIC_VECTOR(RESIZE(dividend_tmp(in0_WIDTH), out_WIDTH));
remd <= STD_LOGIC_VECTOR(RESIZE(remd_tmp(in0_WIDTH), out_WIDTH));
tran_tmp_proc : process (clk)
begin
if (clk'event and clk='1') then
if (ce = '1') then
dividend_tmp(0) <= UNSIGNED(dividend);
divisor_tmp(0) <= UNSIGNED(divisor);
remd_tmp(0) <= (others => '0');
end if;
end if;
end process tran_tmp_proc;
run_proc: for i in 0 to in0_WIDTH-1 generate
begin
comb_tmp(i) <= remd_tmp(i)(in0_WIDTH-2 downto 0) & dividend_tmp(i)(in0_WIDTH-1);
cal_tmp(i) <= ('0' & comb_tmp(i)) - ('0' & divisor_tmp(i));
process (clk)
begin
if (clk'event and clk='1') then
if (ce = '1') then
dividend_tmp(i+1) <= dividend_tmp(i)(in0_WIDTH-2 downto 0) & (not cal_tmp(i)(cal_WIDTH));
divisor_tmp(i+1) <= divisor_tmp(i);
if cal_tmp(i)(cal_WIDTH) = '1' then
remd_tmp(i+1) <= comb_tmp(i);
else
remd_tmp(i+1) <= cal_tmp(i)(in0_WIDTH-1 downto 0);
end if;
end if;
end if;
end process;
end generate run_proc;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hls_saturation_enbkb_div is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
end entity;
architecture rtl of hls_saturation_enbkb_div is
component hls_saturation_enbkb_div_u is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
end component;
signal dividend0 : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
signal divisor0 : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
signal dividend_u : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
signal divisor_u : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
signal quot_u : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
signal remd_u : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
begin
hls_saturation_enbkb_div_u_0 : hls_saturation_enbkb_div_u
generic map(
in0_WIDTH => in0_WIDTH,
in1_WIDTH => in1_WIDTH,
out_WIDTH => out_WIDTH)
port map(
clk => clk,
reset => reset,
ce => ce,
dividend => dividend_u,
divisor => divisor_u,
quot => quot_u,
remd => remd_u);
dividend_u <= dividend0;
divisor_u <= divisor0;
process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
dividend0 <= dividend;
divisor0 <= divisor;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
quot <= quot_u;
remd <= remd_u;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_saturation_enbkb is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_saturation_enbkb is
component hls_saturation_enbkb_div is
generic (
in0_WIDTH : INTEGER;
in1_WIDTH : INTEGER;
out_WIDTH : INTEGER);
port (
dividend : IN STD_LOGIC_VECTOR;
divisor : IN STD_LOGIC_VECTOR;
quot : OUT STD_LOGIC_VECTOR;
remd : OUT STD_LOGIC_VECTOR;
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
reset : IN STD_LOGIC);
end component;
signal sig_quot : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
signal sig_remd : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
begin
hls_saturation_enbkb_div_U : component hls_saturation_enbkb_div
generic map (
in0_WIDTH => din0_WIDTH,
in1_WIDTH => din1_WIDTH,
out_WIDTH => dout_WIDTH)
port map (
dividend => din0,
divisor => din1,
quot => dout,
remd => sig_remd,
clk => clk,
ce => ce,
reset => reset);
end architecture;
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