content stringlengths 1 1.04M ⌀ |
|---|
entity assert1 is
end entity;
architecture test of assert1 is
begin
process is
variable b : boolean;
begin
b := true;
assert b; -- Should be optimised in vcode
wait;
end process;
end architecture;
|
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_dac_1c_2p_f is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
rst : in std_logic;
dac_clk_in_p : in std_logic;
dac_clk_in_n : in std_logic;
dac_clk_out_p : out std_logic;
dac_clk_out_n : out std_logic;
dac_frame_out_p : out std_logic;
dac_frame_out_n : out std_logic;
dac_data_out_a_p : out std_logic_vector(13 downto 0);
dac_data_out_a_n : out std_logic_vector(13 downto 0);
dac_data_out_b_p : out std_logic_vector(13 downto 0);
dac_data_out_b_n : out std_logic_vector(13 downto 0);
spi_cs0n : out std_logic;
spi_cs1n : out std_logic;
spi_clk : out std_logic;
spi_sd_o : out std_logic;
spi_sd_i : in std_logic;
up_status : out std_logic_vector(7 downto 0);
debug_clk : out std_logic;
debug_data : out std_logic_vector(79 downto 0);
debug_trigger : out std_logic_vector(7 downto 0);
delay_clk : in std_logic;
vdma_clk : in std_logic;
M_AXIS_MM2S_TVALID : in std_logic;
M_AXIS_MM2S_TKEEP : in std_logic_vector(7 downto 0);
M_AXIS_MM2S_TDATA : in std_logic_vector(63 downto 0);
M_AXIS_MM2S_TLAST : in std_logic;
M_AXIS_MM2S_TREADY : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_dac_1c_2p_f;
architecture IMP of axi_dac_1c_2p_f is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
rst : in std_logic;
dac_clk_in_p : in std_logic;
dac_clk_in_n : in std_logic;
dac_clk_out_p : out std_logic;
dac_clk_out_n : out std_logic;
dac_frame_out_p : out std_logic;
dac_frame_out_n : out std_logic;
dac_data_out_a_p : out std_logic_vector(13 downto 0);
dac_data_out_a_n : out std_logic_vector(13 downto 0);
dac_data_out_b_p : out std_logic_vector(13 downto 0);
dac_data_out_b_n : out std_logic_vector(13 downto 0);
vdma_clk : in std_logic;
vdma_valid : in std_logic;
vdma_data : in std_logic_vector(63 downto 0);
vdma_ready : out std_logic;
spi_cs0n : out std_logic;
spi_cs1n : out std_logic;
spi_clk : out std_logic;
spi_sd_o : out std_logic;
spi_sd_i : in std_logic;
up_status : out std_logic_vector(7 downto 0);
debug_clk : out std_logic;
debug_data : out std_logic_vector(79 downto 0);
debug_trigger : out std_logic_vector(7 downto 0);
delay_clk : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
rst => rst,
dac_clk_in_p => dac_clk_in_p,
dac_clk_in_n => dac_clk_in_n,
dac_clk_out_p => dac_clk_out_p,
dac_clk_out_n => dac_clk_out_n,
dac_frame_out_p => dac_frame_out_p,
dac_frame_out_n => dac_frame_out_n,
dac_data_out_a_p => dac_data_out_a_p,
dac_data_out_a_n => dac_data_out_a_n,
dac_data_out_b_p => dac_data_out_b_p,
dac_data_out_b_n => dac_data_out_b_n,
vdma_clk => vdma_clk,
vdma_valid => M_AXIS_MM2S_TVALID,
vdma_data => M_AXIS_MM2S_TDATA,
vdma_ready => M_AXIS_MM2S_TREADY,
spi_cs0n => spi_cs0n,
spi_cs1n => spi_cs1n,
spi_clk => spi_clk,
spi_sd_o => spi_sd_o,
spi_sd_i => spi_sd_i,
up_status => up_status,
debug_clk => debug_clk,
debug_data => debug_data,
debug_trigger => debug_trigger,
delay_clk => delay_clk,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_1 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_1 is
SIGNAL mem : UNSIGNED(31 downto 0);
signal val0, val1, val2, val3, min, max , max_tmp, min_tmp: std_logic_vector(7 downto 0);
signal max01, max23, max0123, min01, min23, min0123: std_logic_vector(7 downto 0);
begin
-- Registres contenant les valeurs du min et du max courant
-- Quand reset actif, alors on initialise min et max
-- A chaque écriture dans le coproc, on met à jour le min et le max avec les 4 nouvelles valeurs
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
min <= (others => '1');
max <= (others => '0');
ELSE
IF INPUT_1_valid = '1' THEN
min <= min_tmp;
max <= max_tmp;
ELSE
min <= min;
max <= max;
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
val0 <= INPUT_1(31 downto 24 );
val1 <= INPUT_1(23 downto 16 );
val2 <= INPUT_1(15 downto 8 );
val3 <= INPUT_1(7 downto 0 );
compute_max : process(max, val0, val1, val2, val3, max01, max23, max0123)
begin
if(val0 > val1) then
max01 <= val0;
else
max01 <= val1;
end if;
if(val2 > val3) then
max23 <= val2;
else
max23 <= val3;
end if;
if(max01 > max23) then
max0123 <= max01;
else
max0123 <= max23;
end if;
if(max0123 > max) then
max_tmp <= max0123;
else
max_tmp <= max;
end if;
end process;
compute_min : process(min, val0, val1, val2, val3, min01, min23, min0123)
begin
if(val0 < val1) then
min01 <= val0;
else
min01 <= val1;
end if;
if(val2 < val3) then
min23 <= val2;
else
min23 <= val3;
end if;
if(min01 < min23) then
min0123 <= min01;
else
min0123 <= min23;
end if;
if(min0123 < min) then
min_tmp <= min0123;
else
min_tmp <= min;
end if;
end process;
OUTPUT_1 <= "0000000000000000"&min&max;
end; --architecture logic
|
function next_power_2(len: positive) return positive is
variable n: positive;
begin
n := 1;
while n <= len loop
n := n * 2;
end loop;
return n;
end;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_ila.vhd
-- /___/ /\ Timestamp : Thu Oct 30 16:23:18 BRST 2014
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_ila IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(63 downto 0);
TRIG0: in std_logic_vector(7 downto 0));
END chipscope_ila;
ARCHITECTURE chipscope_ila_a OF chipscope_ila IS
BEGIN
END chipscope_ila_a;
|
-------------------------------------------------------------------------------
-- Title : iMotor UART receiver
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Simple UART that receives serial data.
--
-- This implementation does not have a baud rate generator. As the intention
-- of this entity is to be used in parallel a global baud rate generator is
-- used.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_uart_rx is
generic (
START_BITS : positive := 1;
DATA_BITS : positive := 8;
STOP_BITS : positive := 1;
PARITY : parity_type := None
);
port (
data_out_p : in std_logic_vector(DATA_BITS - 1 downto 0); -- parallel
-- data out
rxd_in_p : in std_logic; -- Serial in
deaf_in_p : in std_logic; -- Ignore rxd_in_p when high.
ready_out_p : out std_logic; -- High for one clock when new data
-- received
parity_error_out_p : out std_logic; -- High when the frame had a parity
-- error
clock_rx_in_p : in std_logic; -- Bit clock for receiver
clk : in std_logic
);
end imotor_uart_rx;
-------------------------------------------------------------------------------
architecture behavioural of imotor_uart_rx is
type imotor_uart_rx_state_type is (
IDLE, -- Idle state:
STATE1, -- State 1:
STATE2 -- State 2:
);
type imotor_uart_rx_type is record
state : imotor_uart_rx_state_type;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : imotor_uart_rx_type := (state => IDLE);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
parity_error_out_p <= '0';
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(r)
variable v : imotor_uart_rx_type;
variable parity_bit : std_logic := '1'; -- Computed parity, default '1'
-- for parity = None
begin
v := r;
case r.state is
when IDLE => null;
when STATE1 => null;
when STATE2 => null;
when others =>
v.state := IDLE;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
|
-------------------------------------------------------------------------------
-- Title : iMotor UART receiver
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Simple UART that receives serial data.
--
-- This implementation does not have a baud rate generator. As the intention
-- of this entity is to be used in parallel a global baud rate generator is
-- used.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_uart_rx is
generic (
START_BITS : positive := 1;
DATA_BITS : positive := 8;
STOP_BITS : positive := 1;
PARITY : parity_type := None
);
port (
data_out_p : in std_logic_vector(DATA_BITS - 1 downto 0); -- parallel
-- data out
rxd_in_p : in std_logic; -- Serial in
deaf_in_p : in std_logic; -- Ignore rxd_in_p when high.
ready_out_p : out std_logic; -- High for one clock when new data
-- received
parity_error_out_p : out std_logic; -- High when the frame had a parity
-- error
clock_rx_in_p : in std_logic; -- Bit clock for receiver
clk : in std_logic
);
end imotor_uart_rx;
-------------------------------------------------------------------------------
architecture behavioural of imotor_uart_rx is
type imotor_uart_rx_state_type is (
IDLE, -- Idle state:
STATE1, -- State 1:
STATE2 -- State 2:
);
type imotor_uart_rx_type is record
state : imotor_uart_rx_state_type;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : imotor_uart_rx_type := (state => IDLE);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
parity_error_out_p <= '0';
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(r)
variable v : imotor_uart_rx_type;
variable parity_bit : std_logic := '1'; -- Computed parity, default '1'
-- for parity = None
begin
v := r;
case r.state is
when IDLE => null;
when STATE1 => null;
when STATE2 => null;
when others =>
v.state := IDLE;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_b
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-e.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_b-e.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_b
--
entity ent_b is
-- Generics:
-- No Generated Generics for Entity ent_b
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic;
port_b_3 : in std_ulogic;
port_b_4 : out std_ulogic;
port_b_5_1 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0);
port_b_6o : out std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2)
-- End of Generated Port for Entity ent_b
);
end ent_b;
--
-- End of Generated Entity ent_b
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
--Date : Wed Mar 30 17:30:47 2016
--Host : csteach0 running 64-bit Ubuntu 14.04.4 LTS
--Command : generate_target kuuga_test_harness_wrapper.bd
--Design : kuuga_test_harness_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity kuuga_test_harness_wrapper is
port (
Agito_Done : out STD_LOGIC;
Agito_Input_Loc : in STD_LOGIC_VECTOR ( 31 downto 0 );
Agito_Result : out STD_LOGIC_VECTOR ( 31 downto 0 );
Kuuga_CLK : in STD_LOGIC;
Kuuga_Input_Loc : in STD_LOGIC_VECTOR ( 31 downto 0 );
Kuuga_RST : in STD_LOGIC;
Kuuga_Result : out STD_LOGIC_VECTOR ( 31 downto 0 );
Kuuga_done : out STD_LOGIC;
start : in STD_LOGIC
);
end kuuga_test_harness_wrapper;
architecture STRUCTURE of kuuga_test_harness_wrapper is
component kuuga_test_harness is
port (
start : in STD_LOGIC;
Kuuga_done : out STD_LOGIC;
Kuuga_Result : out STD_LOGIC_VECTOR ( 31 downto 0 );
Kuuga_CLK : in STD_LOGIC;
Kuuga_RST : in STD_LOGIC;
Kuuga_Input_Loc : in STD_LOGIC_VECTOR ( 31 downto 0 );
Agito_Input_Loc : in STD_LOGIC_VECTOR ( 31 downto 0 );
Agito_Done : out STD_LOGIC;
Agito_Result : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component kuuga_test_harness;
begin
kuuga_test_harness_i: component kuuga_test_harness
port map (
Agito_Done => Agito_Done,
Agito_Input_Loc(31 downto 0) => Agito_Input_Loc(31 downto 0),
Agito_Result(31 downto 0) => Agito_Result(31 downto 0),
Kuuga_CLK => Kuuga_CLK,
Kuuga_Input_Loc(31 downto 0) => Kuuga_Input_Loc(31 downto 0),
Kuuga_RST => Kuuga_RST,
Kuuga_Result(31 downto 0) => Kuuga_Result(31 downto 0),
Kuuga_done => Kuuga_done,
start => start
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_subtractor is
generic
(
width : integer := 4
);
port
(
input1, input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_subtractor;
architecture behavior of c_subtractor is
function bits_to_int (input : std_logic_vector) return integer is
variable ret_val : integer := 0;
begin
for i in input'range loop
if input(i) = '1' then
ret_val := 2 ** i + ret_val;
end if;
end loop; return ret_val;
end bits_to_int;
begin
process (input1, input2)
variable value : integer;
variable result : std_logic_vector((width - 1) downto 0);
begin
value := bits_to_int(input1) - bits_to_int(input2);
if (value < 0) then
value := (2 ** width) + value;
end if;
for i in 0 to width - 1 loop
if (value rem 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
value := value / 2;
end loop;
output <= result;
end process;
end behavior;
|
-- Hello world program.
use std.textio.all; -- Imports the standard textio package.
-- Defines a design entity, without any ports.
entity hello_world is
end hello_world;
architecture behaviour of hello_world is
begin
process
variable l : line;
begin
write (l, String'("Hello world!"));
writeline (output, l);
wait;
end process;
end behaviour;
|
----- Libraries------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----- Entity ------
entity reset_logic is
port( reset_in : in std_logic;
reset_out : out std_logic;
hrs_bin1, hrs_bin10 : in std_logic_vector(3 downto 0)
);
end reset_logic;
-----Architecture-----
architecture resetter of reset_logic is
begin
process(reset_in, hrs_bin1, hrs_bin10)
begin
if (reset_in = '0' or ((hrs_bin10 & hrs_bin1) > "00100011")) then
reset_out <= '0';
else
reset_out <= '1';
end if;
end process;
end resetter; |
----- Libraries------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----- Entity ------
entity reset_logic is
port( reset_in : in std_logic;
reset_out : out std_logic;
hrs_bin1, hrs_bin10 : in std_logic_vector(3 downto 0)
);
end reset_logic;
-----Architecture-----
architecture resetter of reset_logic is
begin
process(reset_in, hrs_bin1, hrs_bin10)
begin
if (reset_in = '0' or ((hrs_bin10 & hrs_bin1) > "00100011")) then
reset_out <= '0';
else
reset_out <= '1';
end if;
end process;
end resetter; |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_12_fg_12_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book
entity D_flipflop is
generic ( Tpd_clk_q, Tsu_d_clk, Th_d_clk : delay_length );
port ( clk, d : in bit; q : out bit );
end entity D_flipflop;
--------------------------------------------------
architecture basic of D_flipflop is
begin
behavior : q <= d after Tpd_clk_q when clk = '1' and clk'event;
check_setup : process is
begin
wait until clk = '1';
assert d'last_event >= Tsu_d_clk
report "setup violation";
end process check_setup;
check_hold : process is
begin
wait until clk'delayed(Th_d_clk) = '1';
assert d'delayed'last_event >= Th_d_clk
report "hold violation";
end process check_hold;
end architecture basic;
-- end code from book
entity fg_12_02 is
end entity fg_12_02;
architecture test of fg_12_02 is
signal system_clock, request, request_pending : bit := '0';
begin
-- code from book (in text)
request_flipflop : entity work.D_flipflop(basic)
generic map ( Tpd_clk_q => 4 ns,
Tsu_d_clk => 3 ns, Th_d_clk => 1 ns )
port map ( clk => system_clock,
d => request, q => request_pending );
-- end code from book
clock_gen : system_clock <= '1' after 10 ns,
'0' after 20 ns when system_clock = '0';
stimulus : request <= '1' after 25 ns, '0' after 35 ns,
'1' after 67 ns, '0' after 71 ns,
'1' after 108 ns, '0' after 110.5 ns;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_12_fg_12_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book
entity D_flipflop is
generic ( Tpd_clk_q, Tsu_d_clk, Th_d_clk : delay_length );
port ( clk, d : in bit; q : out bit );
end entity D_flipflop;
--------------------------------------------------
architecture basic of D_flipflop is
begin
behavior : q <= d after Tpd_clk_q when clk = '1' and clk'event;
check_setup : process is
begin
wait until clk = '1';
assert d'last_event >= Tsu_d_clk
report "setup violation";
end process check_setup;
check_hold : process is
begin
wait until clk'delayed(Th_d_clk) = '1';
assert d'delayed'last_event >= Th_d_clk
report "hold violation";
end process check_hold;
end architecture basic;
-- end code from book
entity fg_12_02 is
end entity fg_12_02;
architecture test of fg_12_02 is
signal system_clock, request, request_pending : bit := '0';
begin
-- code from book (in text)
request_flipflop : entity work.D_flipflop(basic)
generic map ( Tpd_clk_q => 4 ns,
Tsu_d_clk => 3 ns, Th_d_clk => 1 ns )
port map ( clk => system_clock,
d => request, q => request_pending );
-- end code from book
clock_gen : system_clock <= '1' after 10 ns,
'0' after 20 ns when system_clock = '0';
stimulus : request <= '1' after 25 ns, '0' after 35 ns,
'1' after 67 ns, '0' after 71 ns,
'1' after 108 ns, '0' after 110.5 ns;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_12_fg_12_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book
entity D_flipflop is
generic ( Tpd_clk_q, Tsu_d_clk, Th_d_clk : delay_length );
port ( clk, d : in bit; q : out bit );
end entity D_flipflop;
--------------------------------------------------
architecture basic of D_flipflop is
begin
behavior : q <= d after Tpd_clk_q when clk = '1' and clk'event;
check_setup : process is
begin
wait until clk = '1';
assert d'last_event >= Tsu_d_clk
report "setup violation";
end process check_setup;
check_hold : process is
begin
wait until clk'delayed(Th_d_clk) = '1';
assert d'delayed'last_event >= Th_d_clk
report "hold violation";
end process check_hold;
end architecture basic;
-- end code from book
entity fg_12_02 is
end entity fg_12_02;
architecture test of fg_12_02 is
signal system_clock, request, request_pending : bit := '0';
begin
-- code from book (in text)
request_flipflop : entity work.D_flipflop(basic)
generic map ( Tpd_clk_q => 4 ns,
Tsu_d_clk => 3 ns, Th_d_clk => 1 ns )
port map ( clk => system_clock,
d => request, q => request_pending );
-- end code from book
clock_gen : system_clock <= '1' after 10 ns,
'0' after 20 ns when system_clock = '0';
stimulus : request <= '1' after 25 ns, '0' after 35 ns,
'1' after 67 ns, '0' after 71 ns,
'1' after 108 ns, '0' after 110.5 ns;
end architecture test;
|
--
-- PhaseMemory.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity PhaseMemory is
port (
clk : in std_logic;
reset : in std_logic;
slot : in SLOT_TYPE;
memwr : in std_logic;
memout : out PHASE_TYPE;
memin : in PHASE_TYPE
);
end PhaseMemory;
architecture RTL of PhaseMemory is
type PHASE_ARRAY_TYPE is array (0 to MAXSLOT-1) of PHASE_TYPE;
signal phase_array : PHASE_ARRAY_TYPE;
begin
process (clk, reset)
variable init_slot : integer range 0 to MAXSLOT;
begin
if reset = '1' then
init_slot := 0;
elsif clk'event and clk = '1' then
if init_slot /= MAXSLOT then
phase_array(init_slot) <= (others=>'0');
init_slot := init_slot + 1;
elsif memwr = '1' then
phase_array(slot) <= memin;
end if;
memout <= phase_array(slot);
end if;
end process;
end RTL; |
--
-- PhaseMemory.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity PhaseMemory is
port (
clk : in std_logic;
reset : in std_logic;
slot : in SLOT_TYPE;
memwr : in std_logic;
memout : out PHASE_TYPE;
memin : in PHASE_TYPE
);
end PhaseMemory;
architecture RTL of PhaseMemory is
type PHASE_ARRAY_TYPE is array (0 to MAXSLOT-1) of PHASE_TYPE;
signal phase_array : PHASE_ARRAY_TYPE;
begin
process (clk, reset)
variable init_slot : integer range 0 to MAXSLOT;
begin
if reset = '1' then
init_slot := 0;
elsif clk'event and clk = '1' then
if init_slot /= MAXSLOT then
phase_array(init_slot) <= (others=>'0');
init_slot := init_slot + 1;
elsif memwr = '1' then
phase_array(slot) <= memin;
end if;
memout <= phase_array(slot);
end if;
end process;
end RTL; |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0;
USE axi_bram_ctrl_v4_0.axi_bram_ctrl;
ENTITY axi_bram_ctrl_16b IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END axi_bram_ctrl_16b;
ARCHITECTURE axi_bram_ctrl_16b_arch OF axi_bram_ctrl_16b IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_bram_ctrl_16b_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF axi_bram_ctrl_16b_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2014.3.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF axi_bram_ctrl_16b_arch : ARCHITECTURE IS "axi_bram_ctrl_16b,axi_bram_ctrl,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF axi_bram_ctrl_16b_arch: ARCHITECTURE IS "axi_bram_ctrl_16b,axi_bram_ctrl,{x_ipProduct=Vivado 2014.3.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=16384,C_BRAM_ADDR_WIDTH=14,C_S_AXI_ADDR_WIDTH=16,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4LITE,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 16384,
C_BRAM_ADDR_WIDTH => 14,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4LITE",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => '0',
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => '0',
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => '0',
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END axi_bram_ctrl_16b_arch;
|
entity issue116 is
end issue116;
architecture behav of issue116 is
signal intstat : BIT_VECTOR (7 DOWNTO 0);
ALIAS INT_int : BIT is intstat(7);
begin
INT_int <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
--intstat(7) <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
process
begin
assert intstat(7) = '0';
intstat(6 downto 0) <= "0000001";
wait for 1 ns;
assert INT_int = '1';
intstat(6 downto 0) <= "0000000";
wait for 1 ns;
assert INT_int = '1';
wait;
end process;
end behav;
|
entity issue116 is
end issue116;
architecture behav of issue116 is
signal intstat : BIT_VECTOR (7 DOWNTO 0);
ALIAS INT_int : BIT is intstat(7);
begin
INT_int <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
--intstat(7) <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
process
begin
assert intstat(7) = '0';
intstat(6 downto 0) <= "0000001";
wait for 1 ns;
assert INT_int = '1';
intstat(6 downto 0) <= "0000000";
wait for 1 ns;
assert INT_int = '1';
wait;
end process;
end behav;
|
entity issue116 is
end issue116;
architecture behav of issue116 is
signal intstat : BIT_VECTOR (7 DOWNTO 0);
ALIAS INT_int : BIT is intstat(7);
begin
INT_int <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
--intstat(7) <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
process
begin
assert intstat(7) = '0';
intstat(6 downto 0) <= "0000001";
wait for 1 ns;
assert INT_int = '1';
intstat(6 downto 0) <= "0000000";
wait for 1 ns;
assert INT_int = '1';
wait;
end process;
end behav;
|
entity issue116 is
end issue116;
architecture behav of issue116 is
signal intstat : BIT_VECTOR (7 DOWNTO 0);
ALIAS INT_int : BIT is intstat(7);
begin
INT_int <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
--intstat(7) <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
process
begin
assert intstat(7) = '0';
intstat(6 downto 0) <= "0000001";
wait for 1 ns;
assert INT_int = '1';
intstat(6 downto 0) <= "0000000";
wait for 1 ns;
assert INT_int = '1';
wait;
end process;
end behav;
|
entity issue116 is
end issue116;
architecture behav of issue116 is
signal intstat : BIT_VECTOR (7 DOWNTO 0);
ALIAS INT_int : BIT is intstat(7);
begin
INT_int <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
--intstat(7) <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
process
begin
assert intstat(7) = '0';
intstat(6 downto 0) <= "0000001";
wait for 1 ns;
assert INT_int = '1';
intstat(6 downto 0) <= "0000000";
wait for 1 ns;
assert INT_int = '1';
wait;
end process;
end behav;
|
-- test_ng.vhd
entity issue309 is
end issue309;
architecture MODEL of issue309 is
function check return boolean is
constant org_data : bit_vector(31 downto 0) := "01110110010101000011001000010000";
variable val_data : bit_vector(31 downto 0);
begin
val_data := (others => '0');
for i in 7 downto 0 loop
val_data(31 downto 4) := val_data(27 downto 0);
val_data( 3 downto 0) := org_data(i*4+3 downto i*4);
end loop;
return (val_data = org_data);
end function;
function check2 return boolean is
constant org_data : bit_vector(0 to 31) := "01110110010101000011001000010000";
variable val_data : bit_vector(0 to 31);
begin
val_data := (others => '0');
for i in 7 downto 0 loop
val_data(4 to 31) := val_data(0 to 27);
val_data(0 to 3) := org_data(i*4 to i*4+3);
end loop;
return (val_data = org_data);
end function;
constant c : boolean := check;
constant d : boolean := check2;
begin
g1: if c generate
assert true report "c";
end generate;
g2: if d generate
assert true report "d";
end generate;
end MODEL;
|
-- test_ng.vhd
entity issue309 is
end issue309;
architecture MODEL of issue309 is
function check return boolean is
constant org_data : bit_vector(31 downto 0) := "01110110010101000011001000010000";
variable val_data : bit_vector(31 downto 0);
begin
val_data := (others => '0');
for i in 7 downto 0 loop
val_data(31 downto 4) := val_data(27 downto 0);
val_data( 3 downto 0) := org_data(i*4+3 downto i*4);
end loop;
return (val_data = org_data);
end function;
function check2 return boolean is
constant org_data : bit_vector(0 to 31) := "01110110010101000011001000010000";
variable val_data : bit_vector(0 to 31);
begin
val_data := (others => '0');
for i in 7 downto 0 loop
val_data(4 to 31) := val_data(0 to 27);
val_data(0 to 3) := org_data(i*4 to i*4+3);
end loop;
return (val_data = org_data);
end function;
constant c : boolean := check;
constant d : boolean := check2;
begin
g1: if c generate
assert true report "c";
end generate;
g2: if d generate
assert true report "d";
end generate;
end MODEL;
|
-------------------------------------------------------------------------------
-- my_core_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library osif_tb_v1_00_c;
use osif_tb_v1_00_c.All;
entity my_core_wrapper is
port (
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MErr : out std_logic_vector(0 to 1);
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_BE : in std_logic_vector(0 to 7);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_BE : out std_logic_vector(0 to 7);
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to 63);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end my_core_wrapper;
architecture STRUCTURE of my_core_wrapper is
component osif_tb is
generic (
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_PLB_AWIDTH : integer;
C_PLB_DWIDTH : integer;
C_PLB_NUM_MASTERS : integer;
C_PLB_MID_WIDTH : integer;
C_FAMILY : string
);
port (
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_PLB_NUM_MASTERS-1));
Sl_MErr : out std_logic_vector(0 to (C_PLB_NUM_MASTERS-1));
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_PLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to (3));
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to (1));
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to (C_PLB_AWIDTH-1));
PLB_BE : in std_logic_vector(0 to (C_PLB_DWIDTH/8-1));
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_PLB_MID_WIDTH-1));
PLB_MSize : in std_logic_vector(0 to (1));
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to (1));
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to (1));
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to (3));
PLB_type : in std_logic_vector(0 to (2));
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to (C_PLB_AWIDTH-1));
M_BE : out std_logic_vector(0 to (C_PLB_DWIDTH/8-1));
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to (1));
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to (1));
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to (3));
M_type : out std_logic_vector(0 to (2));
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to ((C_PLB_DWIDTH-1)));
PLB_MRdWdAddr : in std_logic_vector(0 to (3));
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to (1));
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
begin
my_core : osif_tb
generic map (
C_BASEADDR => X"30000000",
C_HIGHADDR => X"3000ffff",
C_PLB_AWIDTH => 32,
C_PLB_DWIDTH => 64,
C_PLB_NUM_MASTERS => 2,
C_PLB_MID_WIDTH => 1,
C_FAMILY => "virtex2p"
)
port map (
PLB_Clk => PLB_Clk,
PLB_Rst => PLB_Rst,
Sl_addrAck => Sl_addrAck,
Sl_MBusy => Sl_MBusy,
Sl_MErr => Sl_MErr,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
PLB_abort => PLB_abort,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_PAValid => PLB_PAValid,
PLB_pendPri => PLB_pendPri,
PLB_pendReq => PLB_pendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_compress => M_compress,
M_guarded => M_guarded,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_ordered => M_ordered,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize,
SYNCH_IN => SYNCH_IN,
SYNCH_OUT => SYNCH_OUT
);
end architecture STRUCTURE;
|
architecture RTL of RxDataStateMachine is
-- States of the TxDataStateMachine
type StatesRX is (stIdle, stReadStart, stReadData, stReadParity, stReadStop);
-- WriteParallel maybe not neccesaray
-- Signal for the States
signal CurrentState : StatesRX;
signal NextState : StatesRX;
-- Signal for the DataBits
signal DataBitsCounterMax : STD_LOGIC_VECTOR((BitSelCounterSize-1) downto 0);
signal DataBitsCounter : STD_LOGIC_VECTOR((BitSelCounterSize-1) downto 0);
signal DataBitsCounterIncEn : STD_LOGIC;
signal DataBitsCounterResetEn : STD_LOGIC;
signal ParallelWriteData : STD_LOGIC_VECTOR((MaxDataWidth-1) downto 0);
-- Enable Sampling of Input
signal SampleEnable : STD_LOGIC;
-- Enable Deciding and Taking databit into register
-- decide what bit was sent
signal DataEnable : STD_LOGIC;
signal IdleEnable : STD_LOGIC;
-- Enable ParityEnable (to check if received bit is received ParityBit = DetectedParityBit)
signal ParityEnable : STD_LOGIC;
-- Enable StopBit Write ( indicate state stReadStop)
signal StopBitEnable : STD_LOGIC;
-- indicate the bit detected
signal BitDetected : STD_LOGIC;
-- 3 samples of each bit
signal SampledBits : STD_LOGIC_VECTOR((2**Oversampling - 2) downto 0);
-- RxD_i is taken, and in SamplingProcess taken
signal ParityBit : STD_LOGIC;
signal ParityReset : STD_LOGIC;
signal ParityBitErrorReset : STD_LOGIC;
-- error signals
signal ParityBitError : STD_LOGIC;
-- set when ParityError, StopBitError or RxBufferFullError occured
signal ErrorOccured : STD_LOGIC;
begin
StateReg: process(Clk_i, Reset_i_n)
begin
if Reset_i_n = '0' then
CurrentState <= stIdle;
elsif rising_edge(Clk_i) then
CurrentState <= NextState;
end if;
end process StateReg;
StateMachine: process(CurrentState, RxD_i, BaudClk_i, BitDetected, ParityOn_i, DataBitsCounter)
begin
case CurrentState is
when stIdle =>
-- counters enable signals
DataBitsCounterIncEn <= '0';
DataBitsCounterResetEn <= '0';
-- enable bits
SampleEnable <= '0';
DataEnable <= '0';
ParityEnable <= '0';
StopBitEnable <= '0';
IdleEnable <= '1';
-- ParityReset
ParityReset <= '1';
ParityBitErrorReset <= '1';
-- '0' is detected -> go to next state ReadStart and make
-- a majority decission to decide if a real start bit is send
if RxD_i = '0' then
NextState <= stReadStart;
else
NextState <= CurrentState;
end if;
when stReadStart =>
-- counters enable, reset just in this single state
DataBitsCounterIncEn <= '0';
DataBitsCounterResetEn <= '1';
-- enable bits
SampleEnable <= '1';
DataEnable <= '0';
ParityEnable <= '0';
StopBitEnable <= '0';
IdleEnable <= '0';
-- ParityReset
ParityReset <= '0';
ParityBitErrorReset <= '1';
-- BaudClk_i indicates the end of one bit
-- go to next state
if BaudClk_i = '1'then
if BitDetected = '0' then
NextState <= stReadData;
else
NextState <= stIdle;
end if;
else
NextState <= CurrentState;
end if;
when stReadData =>
-- counters enable
DataBitsCounterResetEn <= '0';
DataBitsCounterIncEn <= '1';
-- enable bits
DataEnable <= '1';
SampleEnable <= '1';
ParityEnable <= '0';
StopBitEnable <= '0';
IdleEnable <= '0';
-- ParityReset
ParityReset <= '0';
ParityBitErrorReset <= '0';
if BaudClk_i = '1' then
if (to_integer(unsigned(DataBitsCounter)) = 0) then
if (ParityOn_i = '1') then
NextState <= stReadParity;
else
NextState <= stReadStop;
end if;
else
NextState <= CurrentState;
end if;
else
NextState <= CurrentState;
end if;
when stReadParity =>
-- counters enable
DataBitsCounterIncEn <= '0';
DataBitsCounterResetEn <= '0';
-- enable bits
SampleEnable <= '1';
DataEnable <= '0';
ParityEnable <= '1';
StopBitEnable <= '0';
IdleEnable <= '0';
-- ParityReset
ParityReset <= '0';
ParityBitErrorReset <= '0';
if BaudClk_i = '1' then
NextState <= stReadStop;
else
NextState <= CurrentState;
end if;
when stReadStop =>
-- counters enable
DataBitsCounterIncEn <= '0';
DataBitsCounterResetEn <= '0';
-- enable bits
SampleEnable <= '1';
DataEnable <= '0';
ParityEnable <= '0';
StopBitEnable <= '1';
IdleEnable <= '0';
-- parityreset
ParityReset <= '1';
ParityBitErrorReset <= '0';
if BaudClk_i = '1' then
NextState <= stIdle;
else
NextState <= CurrentState;
end if;
end case;
end process StateMachine;
-- sample 3 bits
-- shift received bits into a register
SamplingPr: process (Clk_i, Reset_i_n)
begin
if Reset_i_n = '0' then
SampledBits <= (others => '0');
elsif rising_edge(Clk_i) then
if SampleEnable = '1' and SamplingBaudClk_i = '1' and BaudClk_i = '0' then
-- shift bits
SampledBits <= SampledBits(SampledBits'length - 2 downto 0) & RxD_i;
else
SampledBits <= SampledBits;
end if;
end if;
end process SamplingPr;
-- de-serializer
DataPr: process (Clk_i, Reset_i_n)
begin
if Reset_i_n = '0' then
ParallelWriteData <= (others => '0');
elsif rising_edge(Clk_i) then
if DataEnable = '1' and BaudClk_i = '1' then
-- shift bits right and then override the bit
-- at Position DataBitsCounterMax with BitDetected
ParallelWriteData(MaxDataWidth-2 downto 0) <= ParallelWriteData(MaxDataWidth-1 downto 1);
ParallelWriteData(to_integer(unsigned(DataBitsCounterMax))) <= BitDetected;
end if;
end if;
end process DataPr;
-- count the DataBits
DataCountPr: process(Clk_i, Reset_i_n)
begin
if Reset_i_n ='0' then
-- reset value to 0, reset on correct value happens before stRead with DataBitsCounerResetEn
DataBitsCounter <= (others => '0');
elsif rising_edge(Clk_i) then
if DataBitsCounterResetEn = '1' then
DataBitsCounter <= DataBitsCounterMax;
elsif BaudClk_i = '1' and DataBitsCounterIncEn = '1' then
DataBitsCounter <= std_logic_vector(unsigned(DataBitsCounter) - 1);
else
DataBitsCounter <= DataBitsCounter;
end if;
end if;
end process DataCountPr;
-- better solution: use state information to enable parity
-- instead of DataEnable = '1' use CurrentState = stReadData
-- or for sampling Current State = not stIdle
-- therefore DataEnable and SamplingEnable do not have to be set in the Statemachine
-- but hardware afford would be higher
-- to optimize current implementation use one hot encoding
ParityBitPr: process (Clk_i, Reset_i_n, ParityEvenOdd_i)
begin
if Reset_i_n = '0' then
ParityBit <= '0';
elsif rising_edge(Clk_i) then
if ParityReset = '1' then
if (ParityEvenOdd_i = Even) then
ParityBit <= '0';
else
ParityBit <= '1';
end if;
elsif DataEnable = '1' and BaudClk_i = '1' then
ParityBit <= ParityBit xor BitDetected;
else
ParityBit <= ParityBit;
end if;
end if;
end process ParityBitPr;
-- manage ParityError
ParityBitErrPr: process(Clk_i, Reset_i_n)
begin
if Reset_i_n = '0' then
ParityBitError <= '0';
elsif rising_edge(Clk_i) then
if ParityBitErrorReset = '1' then
ParityBitError <= '0';
elsif BaudClk_i ='1' and ParityEnable = '1' then
if BitDetected = ParityBit then
ParityBitError <= '0';
else
ParityBitError <= '1';
end if;
else
ParityBitError <= ParityBitError;
end if;
end if;
end process ParityBitErrPr;
-- combinatory part
-- result of DataPr written on output
ParallelData_o <= ParallelWriteData;
-- error bits
ParityError_o <= '1' when (BaudClk_i = '1' and StopBitEnable = '1' and ParityBitError = '1') else
'0';
StopBitError_o <= '1' when (BaudClk_i = '1' and StopBitEnable = '1' and BitDetected = '0') else
'0';
RxBufferFullError_o <= '1' when (BaudClk_i = '1' and StopBitEnable = '1' and FifoFull_i = '1') else
'0';
WriteParallelData_o <= '1' when (BaudClk_i = '1' and StopBitEnable = '1' and ErrorOccured = '0') else
'0';
-- BGEnable is 1 if receiving 0 and IdleState, 0 if in idle state
BGEnable_o <= '1' when ((Rxd_i = '0' and IdleEnable = '1') or IdleEnable = '0') else
'0';
-- Error detected
-- indicates if an error occured during receiving data
-- (BitDetected indicates if a StopBit occured in stReadStop)
-- Error Occured is just sampled at the 4th sample bit of stReadStop by the
-- process WriteDataPr
-- only ParityBitError maybe set in this state
ErrorOccured <= '1' when (BitDetected = '0' or FifoFull_i = '1' or ParityBitError = '1') else
'0';
-- majority decision which bit was detected
BitDetected <= '0' when (SampledBits = "000") else
'0' when (SampledBits = "001") else
'0' when (SampledBits = "010") else
'0' when (SampledBits = "100") else
'1';
-- convert the enum to a std_logic
DataBitsCounterMax <= "0100" when (BitSelect_i = Sel5Bits) else -- 5
"0101" when (BitSelect_i = Sel6Bits) else -- 6
"0110" when (BitSelect_i = Sel7Bits) else -- 7
"0111" when (BitSelect_i = Sel8Bits) else -- 8
"1000" when (BitSelect_i = Sel9Bits) else -- 9
(others => '-');
end RTL;
|
-------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : io.vhd
-- Author : Daniel Sun <dcsun88osh@gmail.com>
-- Company :
-- Created : 2016-05-21
-- Last update: 2016-08-17
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: GPIO tri-state buffer and clock domain transfer
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-21 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
--
-- Address range: 0x412_0000 - 0x4120_0004
-- | 1 | 0 |
-- |5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|
-- default T T T T T T T T 0 0 T 1 T T 1 1
--
-- 0x4120_0000 | gpio |d|a| |g| |l|p|o| Read/Write
-- | | | | | |
-- | | | | | OCXO enable (power) R/W
-- | | | | PLL reset bar R/W
-- | | | PLL Locked R
-- | | GPS enable (power) R/W
-- | DAC Controller enable R/W
-- Display controller enable R/W
--
-- 0x4120_0004 | | | Tri state control
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.util_pkg.all;
entity io is
port (
fclk_rst_n : in std_logic;
fclk : in std_logic;
rst_n : in std_logic;
clk : in std_logic;
-- fclk
GPIO_tri_i : out std_logic_vector (15 downto 0);
GPIO_tri_o : in std_logic_vector (15 downto 0);
GPIO_tri_t : in std_logic_vector (15 downto 0);
-- clk
locked : in std_logic;
dac_ena : out std_logic;
dac_tri : out std_logic;
disp_ena : out std_logic;
-- fclk
pll_rst_n : out std_logic;
ocxo_ena : inout std_logic;
gps_ena : inout std_logic;
gps_tri : out std_logic;
gpio : inout std_logic_vector (7 DOWNTO 0)
);
end io;
architecture rtl of io is
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal gpio_o_d : std_logic_vector (15 downto 0);
signal gpio_t_d : std_logic_vector (15 downto 0);
signal reset_n : std_logic;
signal ocxo_ena_tri : std_logic;
signal ocxo_pwr_ena : std_logic;
signal ocxo_pwr_on : std_logic;
signal ocxo_on_ctr : std_logic_vector(12 downto 0); -- 25 us turn on
signal gps_ena_tri : std_logic;
signal gps_pwr_ena : std_logic;
signal gps_pwr_on : std_logic;
signal gps_on_ctr : std_logic_vector(12 downto 0);
attribute keep : string;
attribute keep of gps_pwr_ena : signal is "true";
begin
-- Generic gpio interface output register
io_oreg: delay_vec generic map (1) port map (fclk_rst_n, fclk, GPIO_tri_o, gpio_o_d);
io_treg: delay_vec generic map (1) port map (fclk_rst_n, fclk, GPIO_tri_t, gpio_t_d);
-- gpio control interface
-- gpio(0)
ocxo_ena <= gpio_o_d(0) when gpio_t_d(0) = '0' else 'Z';
xtal_ena: delay_sig generic map (1) port map (fclk_rst_n, fclk, ocxo_ena, GPIO_tri_i(0));
xtal_pwr: delay_sig generic map (2) port map (rst_n, clk, GPIO_tri_o(0), ocxo_pwr_ena);
-- gpio(1)
reset_n <= gpio_o_d(1) and fclk_rst_n;
GPIO_tri_i(1) <= reset_n;
pll_rst_n <= reset_n;
-- gpio(2)
pll_lock: delay_sig generic map (2) port map (fclk_rst_n, fclk, locked, GPIO_tri_i(2));
-- gpio(3)
GPIO_tri_i(3) <= '0';
-- gpio(4)
gps_ena <= gpio_o_d(4) when gpio_t_d(4) = '0' else 'Z';
loc_ena: delay_sig generic map (1) port map (fclk_rst_n, fclk, gps_ena, GPIO_tri_i(4));
-- gpio(5)
GPIO_tri_i(5) <= '0';
-- gpio(6)
gpio_dac_ena: delay_sig generic map (2) port map (rst_n, clk, GPIO_tri_o(6), dac_ena);
GPIO_tri_i(6) <= GPIO_tri_o(6);
-- gpio(7)
gpio_disp_ena: delay_sig generic map (2) port map (rst_n, clk, GPIO_tri_o(7), disp_ena);
GPIO_tri_i(7) <= GPIO_tri_o(7);
-- gpio(15 downto 8)
io_tri: for i in 8 to 15 generate
begin
--io_tri_iobuf: component IOBUF
-- port map (
-- I => GPIO_tri_o(i),
-- IO => gpio(i),
-- O => GPIO_tri_i(i),
-- T => GPIO_tri_t(i)
-- );
gpio(i - 8) <= gpio_o_d(i) when gpio_t_d(i) = '0' else 'Z';
end generate;
io_ireg: delay_vec generic map (1) port map (fclk_rst_n, fclk, gpio, GPIO_tri_i(15 downto 8));
--gpio(0) <= gpio_o_d(8) when gpio_t_d(8) = '0' else 'Z';
--gpio(1) <= gpio_o_d(9) when gpio_t_d(9) = '0' else 'Z';
--gpio(2) <= gpio_o_d(10) when gpio_t_d(10) = '0' else 'Z';
--gpio(3) <= gpio_o_d(11) when gpio_t_d(11) = '0' else 'Z';
--gpio(4) <= gpio_o_d(12) when gpio_t_d(12) = '0' else 'Z';
--gpio(5) <= gpio_o_d(13) when gpio_t_d(13) = '0' else 'Z';
--gpio(6) <= gpio_o_d(14) when gpio_t_d(14) = '0' else 'Z';
--gpio(7) <= gpio_o_d(15) when gpio_t_d(15) = '0' else 'Z';
-- The ocxo dac 50 us tristate enable delay
ocxo_tristate:
process (rst_n, clk) is
begin
if (rst_n = '0') then
ocxo_on_ctr <= conv_std_logic_vector(5000, ocxo_on_ctr'length);
ocxo_pwr_on <= '0';
dac_tri <= '1';
elsif (clk'event and clk = '1') then
if (ocxo_pwr_ena = '0' or ocxo_pwr_on = '1') then
ocxo_on_ctr <= conv_std_logic_vector(5000, ocxo_on_ctr'length);
else
ocxo_on_ctr <= ocxo_on_ctr - 1;
end if;
if (ocxo_pwr_ena = '0') then
ocxo_pwr_on <= '0';
elsif (ocxo_on_ctr = 1) then
ocxo_pwr_on <= '1';
else
ocxo_pwr_on <= '0';
end if;
if (ocxo_pwr_ena = '0') then
dac_tri <= '1';
elsif (ocxo_pwr_on = '1') then
dac_tri <= '0';
end if;
end if;
end process;
--loc_pwr: delay_sig generic map (1) port map (fclk_rst_n, fclk, GPIO_tri_o(4), gps_pwr_ena);
-- Duplicate output buffer for enable
gps_ena_dup:
process (fclk_rst_n, fclk) is
begin
if (fclk_rst_n = '0') then
gps_pwr_ena <= '0';
elsif (fclk'event and fclk = '1') then
gps_pwr_ena <= GPIO_tri_o(4);
end if;
end process;
-- The gps rs232 tx 50 us tristate enable delay
gps_tristate:
process (fclk_rst_n, fclk) is
begin
if (fclk_rst_n = '0') then
gps_on_ctr <= conv_std_logic_vector(5000, gps_on_ctr'length);
gps_pwr_on <= '0';
gps_tri <= '1';
elsif (fclk'event and fclk = '1') then
if (gps_pwr_ena = '0' or gps_pwr_on = '1') then
gps_on_ctr <= conv_std_logic_vector(5000, gps_on_ctr'length);
else
gps_on_ctr <= gps_on_ctr - 1;
end if;
if (gps_pwr_ena = '0') then
gps_pwr_on <= '0';
elsif (gps_on_ctr = 1) then
gps_pwr_on <= '1';
else
gps_pwr_on <= '0';
end if;
if (gps_pwr_ena = '0') then
gps_tri <= '1';
elsif (gps_pwr_on = '1') then
gps_tri <= '0';
end if;
end if;
end process;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1935.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01935ent IS
END c07s02b01x00p01n04i01935ent;
ARCHITECTURE c07s02b01x00p01n04i01935arch OF c07s02b01x00p01n04i01935ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
z := (x nand y); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01935 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01935arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1935.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01935ent IS
END c07s02b01x00p01n04i01935ent;
ARCHITECTURE c07s02b01x00p01n04i01935arch OF c07s02b01x00p01n04i01935ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
z := (x nand y); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01935 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01935arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1935.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01935ent IS
END c07s02b01x00p01n04i01935ent;
ARCHITECTURE c07s02b01x00p01n04i01935arch OF c07s02b01x00p01n04i01935ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
z := (x nand y); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01935 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01935arch;
|
---------- ---------------------------------------------------------------------
-- Title : Sub Bytes
-- Project : AES-GCM
-------------------------------------------------------------------------------
-- File : sub_bytes_ea.vhd
-- Author : Bill MacDowell <bill@bill-macdowell-laptop>
-- Company :
-- Created : 2017-03-15
-- Last update: 2017-03-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This is a wrapper around 16 s-box instantiations. There is one
-- s-box instantiated for each byte in the 4x4 matrix that makes up a block.
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-03-15 1.0 bill Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sub_bytes is
port (
clk : in std_logic;
rst : in std_logic;
block_in : in std_logic_vector(127 downto 0);
block_out : out std_logic_vector(127 downto 0));
end entity sub_bytes;
architecture struct of sub_bytes is
component s_box is
port (
clk : in std_logic;
rst : in std_logic;
byte_in : in std_logic_vector(7 downto 0);
byte_out : out std_logic_vector(7 downto 0));
end component s_box;
begin -- architecture rtl
GEN_SBOXES: for byte_idx in 0 to 15 generate
s_box_0: s_box
port map (
clk => clk,
rst => rst,
byte_in => block_in(8*byte_idx+7 downto 8*byte_idx),
byte_out => block_out(8*byte_idx+7 downto 8*byte_idx));
end generate GEN_SBOXES;
end struct;
|
-------------------------------------------------------------------------------
--
-- Parametrizable, generic RAM with enable.
--
-- $Id: generic_ram_ena.vhd,v 1.3 2008-04-27 22:13:15 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity generic_ram_ena is
generic (
addr_width_g : integer := 10;
data_width_g : integer := 8
);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(addr_width_g-1 downto 0);
we_i : in std_logic;
ena_i : in std_logic;
d_i : in std_logic_vector(data_width_g-1 downto 0);
d_o : out std_logic_vector(data_width_g-1 downto 0)
);
end generic_ram_ena;
library ieee;
use ieee.numeric_std.all;
architecture rtl of generic_ram_ena is
type mem_t is array (natural range 0 to 2**addr_width_g-1) of
std_logic_vector(d_i'range);
signal mem_q : mem_t
-- pragma translate_off
:= (others => (others => '0'))
-- pragma translate_on
;
begin
mem: process (clk_i)
begin
if clk_i'event and clk_i = '1' then
if ena_i = '1' then
if we_i = '1' then
mem_q(to_integer(unsigned(a_i))) <= d_i;
end if;
d_o <= mem_q(to_integer(unsigned(a_i)));
end if;
end if;
end process mem;
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
use Ieee.std_logic_unsigned.all;
entity TextAndRowToAddr is
Port (
Texture : in STD_LOGIC_VECTOR (3 downto 0);
Row : in STD_LOGIC_VECTOR (4 downto 0);
AddressOut : out STD_LOGIC_VECTOR (7 downto 0)
);
end TextAndRowToAddr;
architecture Behavioral of TextAndRowToAddr is
begin
AddressOut <= conv_std_logic_vector(conv_integer((Texture-1))*23+conv_integer(Row)-1,8);
end Behavioral;
|
-------------------------------------------------------------------------------
-- system_fmc_imageon_iic_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_iic_v1_02_a;
use axi_iic_v1_02_a.all;
entity system_fmc_imageon_iic_0_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2INTC_Irpt : out std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Gpo : out std_logic_vector(0 to 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_fmc_imageon_iic_0_wrapper : entity is "axi_iic_v1_02_a";
end system_fmc_imageon_iic_0_wrapper;
architecture STRUCTURE of system_fmc_imageon_iic_0_wrapper is
component axi_iic is
generic (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_IIC_FREQ : INTEGER;
C_TEN_BIT_ADR : INTEGER;
C_GPO_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_SCL_INERTIAL_DELAY : INTEGER;
C_SDA_INERTIAL_DELAY : INTEGER;
C_SDA_LEVEL : INTEGER
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2INTC_Irpt : out std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Gpo : out std_logic_vector((C_GPO_WIDTH-1) to 0)
);
end component;
begin
fmc_imageon_iic_0 : axi_iic
generic map (
C_FAMILY => "zynq",
C_INSTANCE => "fmc_imageon_iic_0",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_IIC_FREQ => 100000,
C_TEN_BIT_ADR => 0,
C_GPO_WIDTH => 1,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_SCL_INERTIAL_DELAY => 0,
C_SDA_INERTIAL_DELAY => 0,
C_SDA_LEVEL => 1
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
IIC2INTC_Irpt => IIC2INTC_Irpt,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
Sda_I => Sda_I,
Sda_O => Sda_O,
Sda_T => Sda_T,
Scl_I => Scl_I,
Scl_O => Scl_O,
Scl_T => Scl_T,
Gpo => Gpo
);
end architecture STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity assert1 is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end assert1;
architecture behav of assert1 is
signal val : unsigned (3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => '0');
else
val <= val + 1;
end if;
end if;
end process;
cnt <= val;
end behav;
vunit verif1 (assert1)
{
default clock is rising_edge(clk);
assert always cnt /= 5 abort rst;
}
|
-------------------------------------------------------------------------------
-- bfm_monitor_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_monitor_bfm_v1_00_a;
use plbv46_monitor_bfm_v1_00_a.all;
entity bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 0);
M_priority : in std_logic_vector(0 to 1);
M_buslock : in std_logic_vector(0 to 0);
M_RNW : in std_logic_vector(0 to 0);
M_BE : in std_logic_vector(0 to 15);
M_msize : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 3);
M_type : in std_logic_vector(0 to 2);
M_TAttribute : in std_logic_vector(0 to 15);
M_lockErr : in std_logic_vector(0 to 0);
M_abort : in std_logic_vector(0 to 0);
M_UABus : in std_logic_vector(0 to 31);
M_ABus : in std_logic_vector(0 to 31);
M_wrDBus : in std_logic_vector(0 to 127);
M_wrBurst : in std_logic_vector(0 to 0);
M_rdBurst : in std_logic_vector(0 to 0);
PLB_MAddrAck : in std_logic_vector(0 to 0);
PLB_MRearbitrate : in std_logic_vector(0 to 0);
PLB_MTimeout : in std_logic_vector(0 to 0);
PLB_MBusy : in std_logic_vector(0 to 0);
PLB_MRdErr : in std_logic_vector(0 to 0);
PLB_MWrErr : in std_logic_vector(0 to 0);
PLB_MIRQ : in std_logic_vector(0 to 0);
PLB_MWrDAck : in std_logic_vector(0 to 0);
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic_vector(0 to 0);
PLB_MRdBTerm : in std_logic_vector(0 to 0);
PLB_MWrBTerm : in std_logic_vector(0 to 0);
PLB_Mssize : in std_logic_vector(0 to 1);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to 1);
PLB_wrPrim : in std_logic_vector(0 to 1);
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 1);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 1);
Sl_ssize : in std_logic_vector(0 to 3);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 127);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 0);
PLB_SMRdErr : in std_logic_vector(0 to 0);
PLB_SMWrErr : in std_logic_vector(0 to 0);
PLB_SMIRQ : in std_logic_vector(0 to 0);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end bfm_monitor_wrapper;
architecture STRUCTURE of bfm_monitor_wrapper is
component plbv46_monitor_bfm is
generic (
PLB_MONITOR_NUM : std_logic_vector(0 to 3);
PLB_SLAVE0_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_1 : std_logic_vector(0 to 31);
C_MON_PLB_AWIDTH : integer;
C_MON_PLB_DWIDTH : integer;
C_MON_PLB_NUM_MASTERS : integer;
C_MON_PLB_NUM_SLAVES : integer;
C_MON_PLB_MID_WIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_priority : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
M_buslock : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_RNW : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_BE : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_DWIDTH/8)-1));
M_msize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
M_size : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1));
M_type : in std_logic_vector(0 to ((3*C_MON_PLB_NUM_MASTERS)-1));
M_TAttribute : in std_logic_vector(0 to 16*C_MON_PLB_NUM_MASTERS-1);
M_lockErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_UABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_ABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_wrDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_wrBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_rdBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MAddrAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MTimeout : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1));
PLB_MRdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1));
PLB_MRdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_Mssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
PLB_wrPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
PLB_MasterID : in std_logic_vector(0 to C_MON_PLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH/8)-1));
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to (C_MON_PLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wait : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_SLAVES)-1));
Sl_rdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_SLAVES)-1));
Sl_rdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_MBusy : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MRdErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MWrErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MIRQ : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_ssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_SLAVES)-1));
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to C_MON_PLB_DWIDTH-1);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
begin
bfm_monitor : plbv46_monitor_bfm
generic map (
PLB_MONITOR_NUM => B"0000",
PLB_SLAVE0_ADDR_LO_0 => X"00000000",
PLB_SLAVE0_ADDR_HI_0 => X"00000000",
PLB_SLAVE1_ADDR_LO_0 => X"00000000",
PLB_SLAVE1_ADDR_HI_0 => X"00000000",
PLB_SLAVE2_ADDR_LO_0 => X"00000000",
PLB_SLAVE2_ADDR_HI_0 => X"00000000",
PLB_SLAVE3_ADDR_LO_0 => X"00000000",
PLB_SLAVE3_ADDR_HI_0 => X"00000000",
PLB_SLAVE4_ADDR_LO_0 => X"00000000",
PLB_SLAVE4_ADDR_HI_0 => X"00000000",
PLB_SLAVE5_ADDR_LO_0 => X"00000000",
PLB_SLAVE5_ADDR_HI_0 => X"00000000",
PLB_SLAVE6_ADDR_LO_0 => X"00000000",
PLB_SLAVE6_ADDR_HI_0 => X"00000000",
PLB_SLAVE7_ADDR_LO_0 => X"00000000",
PLB_SLAVE7_ADDR_HI_0 => X"00000000",
PLB_SLAVE0_ADDR_LO_1 => X"00000000",
PLB_SLAVE0_ADDR_HI_1 => X"00000000",
PLB_SLAVE1_ADDR_LO_1 => X"00000000",
PLB_SLAVE1_ADDR_HI_1 => X"00000000",
PLB_SLAVE2_ADDR_LO_1 => X"00000000",
PLB_SLAVE2_ADDR_HI_1 => X"00000000",
PLB_SLAVE3_ADDR_LO_1 => X"00000000",
PLB_SLAVE3_ADDR_HI_1 => X"00000000",
PLB_SLAVE4_ADDR_LO_1 => X"00000000",
PLB_SLAVE4_ADDR_HI_1 => X"00000000",
PLB_SLAVE5_ADDR_LO_1 => X"00000000",
PLB_SLAVE5_ADDR_HI_1 => X"00000000",
PLB_SLAVE6_ADDR_LO_1 => X"00000000",
PLB_SLAVE6_ADDR_HI_1 => X"00000000",
PLB_SLAVE7_ADDR_LO_1 => X"00000000",
PLB_SLAVE7_ADDR_HI_1 => X"00000000",
C_MON_PLB_AWIDTH => 32,
C_MON_PLB_DWIDTH => 128,
C_MON_PLB_NUM_MASTERS => 1,
C_MON_PLB_NUM_SLAVES => 2,
C_MON_PLB_MID_WIDTH => 1
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
M_request => M_request,
M_priority => M_priority,
M_buslock => M_buslock,
M_RNW => M_RNW,
M_BE => M_BE,
M_msize => M_msize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_Mssize => PLB_Mssize,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_MasterID => PLB_MasterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_msize => PLB_msize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_UABus => PLB_UABus,
PLB_ABus => PLB_ABus,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_rdpendReq => PLB_rdpendReq,
PLB_wrpendReq => PLB_wrpendReq,
PLB_rdpendPri => PLB_rdpendPri,
PLB_wrpendPri => PLB_wrpendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MIRQ => Sl_MIRQ,
Sl_ssize => Sl_ssize,
PLB_SaddrAck => PLB_SaddrAck,
PLB_Swait => PLB_Swait,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_SwrDAck => PLB_SwrDAck,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SMBusy => PLB_SMBusy,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMIRQ => PLB_SMIRQ,
PLB_Sssize => PLB_Sssize
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- bfm_monitor_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_monitor_bfm_v1_00_a;
use plbv46_monitor_bfm_v1_00_a.all;
entity bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 0);
M_priority : in std_logic_vector(0 to 1);
M_buslock : in std_logic_vector(0 to 0);
M_RNW : in std_logic_vector(0 to 0);
M_BE : in std_logic_vector(0 to 15);
M_msize : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 3);
M_type : in std_logic_vector(0 to 2);
M_TAttribute : in std_logic_vector(0 to 15);
M_lockErr : in std_logic_vector(0 to 0);
M_abort : in std_logic_vector(0 to 0);
M_UABus : in std_logic_vector(0 to 31);
M_ABus : in std_logic_vector(0 to 31);
M_wrDBus : in std_logic_vector(0 to 127);
M_wrBurst : in std_logic_vector(0 to 0);
M_rdBurst : in std_logic_vector(0 to 0);
PLB_MAddrAck : in std_logic_vector(0 to 0);
PLB_MRearbitrate : in std_logic_vector(0 to 0);
PLB_MTimeout : in std_logic_vector(0 to 0);
PLB_MBusy : in std_logic_vector(0 to 0);
PLB_MRdErr : in std_logic_vector(0 to 0);
PLB_MWrErr : in std_logic_vector(0 to 0);
PLB_MIRQ : in std_logic_vector(0 to 0);
PLB_MWrDAck : in std_logic_vector(0 to 0);
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic_vector(0 to 0);
PLB_MRdBTerm : in std_logic_vector(0 to 0);
PLB_MWrBTerm : in std_logic_vector(0 to 0);
PLB_Mssize : in std_logic_vector(0 to 1);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to 1);
PLB_wrPrim : in std_logic_vector(0 to 1);
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 1);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 1);
Sl_ssize : in std_logic_vector(0 to 3);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 127);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 0);
PLB_SMRdErr : in std_logic_vector(0 to 0);
PLB_SMWrErr : in std_logic_vector(0 to 0);
PLB_SMIRQ : in std_logic_vector(0 to 0);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end bfm_monitor_wrapper;
architecture STRUCTURE of bfm_monitor_wrapper is
component plbv46_monitor_bfm is
generic (
PLB_MONITOR_NUM : std_logic_vector(0 to 3);
PLB_SLAVE0_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_1 : std_logic_vector(0 to 31);
C_MON_PLB_AWIDTH : integer;
C_MON_PLB_DWIDTH : integer;
C_MON_PLB_NUM_MASTERS : integer;
C_MON_PLB_NUM_SLAVES : integer;
C_MON_PLB_MID_WIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_priority : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
M_buslock : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_RNW : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_BE : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_DWIDTH/8)-1));
M_msize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
M_size : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1));
M_type : in std_logic_vector(0 to ((3*C_MON_PLB_NUM_MASTERS)-1));
M_TAttribute : in std_logic_vector(0 to 16*C_MON_PLB_NUM_MASTERS-1);
M_lockErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_UABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_ABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_wrDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_wrBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_rdBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MAddrAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MTimeout : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1));
PLB_MRdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1));
PLB_MRdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_Mssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
PLB_wrPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
PLB_MasterID : in std_logic_vector(0 to C_MON_PLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH/8)-1));
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to (C_MON_PLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wait : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_SLAVES)-1));
Sl_rdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_SLAVES)-1));
Sl_rdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_MBusy : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MRdErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MWrErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MIRQ : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_ssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_SLAVES)-1));
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to C_MON_PLB_DWIDTH-1);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
begin
bfm_monitor : plbv46_monitor_bfm
generic map (
PLB_MONITOR_NUM => B"0000",
PLB_SLAVE0_ADDR_LO_0 => X"00000000",
PLB_SLAVE0_ADDR_HI_0 => X"00000000",
PLB_SLAVE1_ADDR_LO_0 => X"00000000",
PLB_SLAVE1_ADDR_HI_0 => X"00000000",
PLB_SLAVE2_ADDR_LO_0 => X"00000000",
PLB_SLAVE2_ADDR_HI_0 => X"00000000",
PLB_SLAVE3_ADDR_LO_0 => X"00000000",
PLB_SLAVE3_ADDR_HI_0 => X"00000000",
PLB_SLAVE4_ADDR_LO_0 => X"00000000",
PLB_SLAVE4_ADDR_HI_0 => X"00000000",
PLB_SLAVE5_ADDR_LO_0 => X"00000000",
PLB_SLAVE5_ADDR_HI_0 => X"00000000",
PLB_SLAVE6_ADDR_LO_0 => X"00000000",
PLB_SLAVE6_ADDR_HI_0 => X"00000000",
PLB_SLAVE7_ADDR_LO_0 => X"00000000",
PLB_SLAVE7_ADDR_HI_0 => X"00000000",
PLB_SLAVE0_ADDR_LO_1 => X"00000000",
PLB_SLAVE0_ADDR_HI_1 => X"00000000",
PLB_SLAVE1_ADDR_LO_1 => X"00000000",
PLB_SLAVE1_ADDR_HI_1 => X"00000000",
PLB_SLAVE2_ADDR_LO_1 => X"00000000",
PLB_SLAVE2_ADDR_HI_1 => X"00000000",
PLB_SLAVE3_ADDR_LO_1 => X"00000000",
PLB_SLAVE3_ADDR_HI_1 => X"00000000",
PLB_SLAVE4_ADDR_LO_1 => X"00000000",
PLB_SLAVE4_ADDR_HI_1 => X"00000000",
PLB_SLAVE5_ADDR_LO_1 => X"00000000",
PLB_SLAVE5_ADDR_HI_1 => X"00000000",
PLB_SLAVE6_ADDR_LO_1 => X"00000000",
PLB_SLAVE6_ADDR_HI_1 => X"00000000",
PLB_SLAVE7_ADDR_LO_1 => X"00000000",
PLB_SLAVE7_ADDR_HI_1 => X"00000000",
C_MON_PLB_AWIDTH => 32,
C_MON_PLB_DWIDTH => 128,
C_MON_PLB_NUM_MASTERS => 1,
C_MON_PLB_NUM_SLAVES => 2,
C_MON_PLB_MID_WIDTH => 1
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
M_request => M_request,
M_priority => M_priority,
M_buslock => M_buslock,
M_RNW => M_RNW,
M_BE => M_BE,
M_msize => M_msize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_Mssize => PLB_Mssize,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_MasterID => PLB_MasterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_msize => PLB_msize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_UABus => PLB_UABus,
PLB_ABus => PLB_ABus,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_rdpendReq => PLB_rdpendReq,
PLB_wrpendReq => PLB_wrpendReq,
PLB_rdpendPri => PLB_rdpendPri,
PLB_wrpendPri => PLB_wrpendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MIRQ => Sl_MIRQ,
Sl_ssize => Sl_ssize,
PLB_SaddrAck => PLB_SaddrAck,
PLB_Swait => PLB_Swait,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_SwrDAck => PLB_SwrDAck,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SMBusy => PLB_SMBusy,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMIRQ => PLB_SMIRQ,
PLB_Sssize => PLB_Sssize
);
end architecture STRUCTURE;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: genclkbuf
-- File: genclkbuf.vhd
-- Author: Jiri Gaisler, Marko Isomaki - Gaisler Research
-- Description: Hard buffers with tech wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity techbuf is
generic(
buftype : integer range 0 to 6 := 0;
tech : integer range 0 to NTECH := inferred);
port( i : in std_ulogic; o : out std_ulogic);
end entity;
architecture rtl of techbuf is
component clkbuf_fusion is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_apa3 is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_apa3e is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_apa3l is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_actel is generic( buftype : integer range 0 to 6 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_xilinx is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_ut025crh is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_ut130hbd is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_nextreme is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_n2x is generic(buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
gen : if has_techbuf(tech) = 0 generate
o <= i;
end generate;
fus : if (tech = actfus) generate
fus0 : clkbuf_fusion generic map (buftype => buftype) port map(i => i, o => o);
end generate;
pa3 : if (tech = apa3) generate
pa30 : clkbuf_apa3 generic map (buftype => buftype) port map(i => i, o => o);
end generate;
pa3e : if (tech = apa3e) generate
pae30 : clkbuf_apa3e generic map (buftype => buftype) port map(i => i, o => o);
end generate;
pa3l : if (tech = apa3l) generate
pa3l0 : clkbuf_apa3l generic map (buftype => buftype) port map(i => i, o => o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
axc0 : clkbuf_actel generic map (buftype => buftype) port map(i => i, o => o);
end generate;
xil : if (is_unisim(tech) = 1) generate
xil0 : clkbuf_xilinx generic map (buftype => buftype) port map(i => i, o => o);
end generate;
ut : if (tech = ut25) generate
ut0 : clkbuf_ut025crh generic map (buftype => buftype) port map(i => i, o => o);
end generate;
ut13 : if (tech = ut130) generate
ut0 : clkbuf_ut130hbd generic map (buftype => buftype) port map(i => i, o => o);
end generate;
ut09 : if (tech = ut90) generate
ut0 : clkand_ut90nhbd port map(i => i, en => vcc, o => o, tsten => gnd);
end generate;
easic: if tech = easic90 generate
eas : clkbuf_nextreme generic map (buftype => buftype) port map(i => i, o => o);
end generate easic;
n2x : if tech = easic45 generate
n2x0 : clkbuf_n2x generic map (buftype => buftype) port map(i => i, o => o);
end generate;
end architecture;
|
/home/andrey/Anna/Programming/fpga/core/pipistrello/minsoc1/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl//altera_virtual_jtag.vhd
|
architecture RTL of FIFO is
begin
process
begin
sig1 <= sig2; -- This comment is okay
end process;
-- Violations below
process
begin
sig1 <= sig2 and
sig3 or -- This comment is okay
sig4;
end process;
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2572.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s05b00x00p16n03i02572ent IS
END c07s05b00x00p16n03i02572ent;
ARCHITECTURE c07s05b00x00p16n03i02572arch OF c07s05b00x00p16n03i02572ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(2.12E80 = (1.06E40*2.0E40))
report "***PASSED TEST: c07s05b00x00p16n03i02572"
severity NOTE;
assert (2.12E80 = (1.06E40*2.0E40))
report "***FAILED TEST: c07s05b00x00p16n03i02572 - Integer operands and result lie outside the bounds of floating point type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s05b00x00p16n03i02572arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2572.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s05b00x00p16n03i02572ent IS
END c07s05b00x00p16n03i02572ent;
ARCHITECTURE c07s05b00x00p16n03i02572arch OF c07s05b00x00p16n03i02572ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(2.12E80 = (1.06E40*2.0E40))
report "***PASSED TEST: c07s05b00x00p16n03i02572"
severity NOTE;
assert (2.12E80 = (1.06E40*2.0E40))
report "***FAILED TEST: c07s05b00x00p16n03i02572 - Integer operands and result lie outside the bounds of floating point type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s05b00x00p16n03i02572arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2572.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s05b00x00p16n03i02572ent IS
END c07s05b00x00p16n03i02572ent;
ARCHITECTURE c07s05b00x00p16n03i02572arch OF c07s05b00x00p16n03i02572ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(2.12E80 = (1.06E40*2.0E40))
report "***PASSED TEST: c07s05b00x00p16n03i02572"
severity NOTE;
assert (2.12E80 = (1.06E40*2.0E40))
report "***FAILED TEST: c07s05b00x00p16n03i02572 - Integer operands and result lie outside the bounds of floating point type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s05b00x00p16n03i02572arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;
entity morten2 is
end entity;
architecture foo of morten2 is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal cnt_1: unsigned (7 downto 0);
signal cnt_3: unsigned (7 downto 0);
function to_bstring(sl : std_logic) return string is
alias bstring: string is std_logic'image(sl);
begin
--return "" & string'(std_logic'image(sl))(2); -- "" & character to get string
return "" & bstring(2);
end function;
function to_bstring(slv : std_logic_vector) return string is
alias slv_norm : std_logic_vector(1 to slv'length) is slv;
begin
if slv_norm'length = 0 then
return "";
elsif slv_norm'length = 1 then
return to_bstring(slv_norm(1));
else -- slv_norm'length > 0
return to_bstring(slv_norm(1)) & to_bstring(slv_norm(2 to slv_norm'length));
end if;
end function;
begin
PRINT:
process (clk) is
variable line_v : line;
file out_file : text open write_mode is "out.txt";
begin
if rising_edge(clk) then
write(line_v, to_bstring(rst) & " " &
to_bstring(std_logic_vector(cnt_1)) & " " &
to_bstring(std_logic_vector(cnt_3))
);
writeline(out_file, line_v);
end if;
end process;
COUNTER1:
process (clk,rst)
begin
if rst = '1' then
cnt_1 <= (others => '0');
elsif rising_edge(clk) then
cnt_1 <= cnt_1 + 1;
end if;
end process;
COUNTER3:
process (clk,rst)
begin
if rst = '1' then
cnt_3 <= (others => '0');
elsif rising_edge(clk) then
cnt_3 <= cnt_3 + 3;
end if;
end process;
RESET:
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
rst <= '0';
wait;
end process;
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if Now > 210 ns then
wait;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;
entity morten2 is
end entity;
architecture foo of morten2 is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal cnt_1: unsigned (7 downto 0);
signal cnt_3: unsigned (7 downto 0);
function to_bstring(sl : std_logic) return string is
alias bstring: string is std_logic'image(sl);
begin
--return "" & string'(std_logic'image(sl))(2); -- "" & character to get string
return "" & bstring(2);
end function;
function to_bstring(slv : std_logic_vector) return string is
alias slv_norm : std_logic_vector(1 to slv'length) is slv;
begin
if slv_norm'length = 0 then
return "";
elsif slv_norm'length = 1 then
return to_bstring(slv_norm(1));
else -- slv_norm'length > 0
return to_bstring(slv_norm(1)) & to_bstring(slv_norm(2 to slv_norm'length));
end if;
end function;
begin
PRINT:
process (clk) is
variable line_v : line;
file out_file : text open write_mode is "out.txt";
begin
if rising_edge(clk) then
write(line_v, to_bstring(rst) & " " &
to_bstring(std_logic_vector(cnt_1)) & " " &
to_bstring(std_logic_vector(cnt_3))
);
writeline(out_file, line_v);
end if;
end process;
COUNTER1:
process (clk,rst)
begin
if rst = '1' then
cnt_1 <= (others => '0');
elsif rising_edge(clk) then
cnt_1 <= cnt_1 + 1;
end if;
end process;
COUNTER3:
process (clk,rst)
begin
if rst = '1' then
cnt_3 <= (others => '0');
elsif rising_edge(clk) then
cnt_3 <= cnt_3 + 3;
end if;
end process;
RESET:
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
rst <= '0';
wait;
end process;
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if Now > 210 ns then
wait;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;
entity morten2 is
end entity;
architecture foo of morten2 is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal cnt_1: unsigned (7 downto 0);
signal cnt_3: unsigned (7 downto 0);
function to_bstring(sl : std_logic) return string is
alias bstring: string is std_logic'image(sl);
begin
--return "" & string'(std_logic'image(sl))(2); -- "" & character to get string
return "" & bstring(2);
end function;
function to_bstring(slv : std_logic_vector) return string is
alias slv_norm : std_logic_vector(1 to slv'length) is slv;
begin
if slv_norm'length = 0 then
return "";
elsif slv_norm'length = 1 then
return to_bstring(slv_norm(1));
else -- slv_norm'length > 0
return to_bstring(slv_norm(1)) & to_bstring(slv_norm(2 to slv_norm'length));
end if;
end function;
begin
PRINT:
process (clk) is
variable line_v : line;
file out_file : text open write_mode is "out.txt";
begin
if rising_edge(clk) then
write(line_v, to_bstring(rst) & " " &
to_bstring(std_logic_vector(cnt_1)) & " " &
to_bstring(std_logic_vector(cnt_3))
);
writeline(out_file, line_v);
end if;
end process;
COUNTER1:
process (clk,rst)
begin
if rst = '1' then
cnt_1 <= (others => '0');
elsif rising_edge(clk) then
cnt_1 <= cnt_1 + 1;
end if;
end process;
COUNTER3:
process (clk,rst)
begin
if rst = '1' then
cnt_3 <= (others => '0');
elsif rising_edge(clk) then
cnt_3 <= cnt_3 + 3;
end if;
end process;
RESET:
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
rst <= '0';
wait;
end process;
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if Now > 210 ns then
wait;
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:52:15 01/15/2015
-- Design Name:
-- Module Name: porteAND - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity porteAND is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC);
end porteAND;
architecture Behavioral of porteAND is
begin
s <= a and b;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:52:15 01/15/2015
-- Design Name:
-- Module Name: porteAND - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity porteAND is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC);
end porteAND;
architecture Behavioral of porteAND is
begin
s <= a and b;
end Behavioral;
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_constants.all;
--! @brief Instruction fetch unit.
entity pp_fetch is
generic(
RESET_ADDRESS : std_logic_vector(31 downto 0)
);
port(
clk : in std_logic;
reset : in std_logic;
-- Instruction memory connections:
imem_address : out std_logic_vector(31 downto 0);
imem_data_in : in std_logic_vector(31 downto 0);
imem_req : out std_logic;
imem_ack : in std_logic;
-- Control inputs:
stall : in std_logic;
flush : in std_logic;
branch : in std_logic;
exception : in std_logic;
branch_target : in std_logic_vector(31 downto 0);
evec : in std_logic_vector(31 downto 0);
-- Outputs to the instruction decode unit:
instruction_data : out std_logic_vector(31 downto 0);
instruction_address : out std_logic_vector(31 downto 0);
instruction_ready : out std_logic
);
end entity pp_fetch;
architecture behaviour of pp_fetch is
signal pc : std_logic_vector(31 downto 0);
signal pc_next : std_logic_vector(31 downto 0);
signal cancel_fetch : std_logic;
begin
imem_address <= pc_next when cancel_fetch = '0' else pc;
instruction_data <= imem_data_in;
instruction_ready <= imem_ack and (not stall) and (not cancel_fetch);
instruction_address <= pc;
imem_req <= not reset;
set_pc: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
pc <= RESET_ADDRESS;
cancel_fetch <= '0';
else
if (exception = '1' or branch = '1') and imem_ack = '0' then
cancel_fetch <= '1';
pc <= pc_next;
elsif cancel_fetch = '1' and imem_ack = '1' then
cancel_fetch <= '0';
else
pc <= pc_next;
end if;
end if;
end if;
end process set_pc;
calc_next_pc: process(reset, stall, branch, exception, imem_ack, branch_target, evec, pc, cancel_fetch)
begin
if exception = '1' then
pc_next <= evec;
elsif branch = '1' then
pc_next <= branch_target;
elsif imem_ack = '1' and stall = '0' and cancel_fetch = '0' then
pc_next <= std_logic_vector(unsigned(pc) + 4);
else
pc_next <= pc;
end if;
end process calc_next_pc;
end architecture behaviour;
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round_f IS
END tb_round_f;
ARCHITECTURE behavior OF tb_round_f IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
PORT(
enc : in std_logic;
rc_in : IN std_logic_vector(31 downto 0);
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal enc : std_logic := '0';
signal rc_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
enc => enc,
rc_in => rc_in,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rc_in <= X"00000080";
a_0_in <= X"61396c93";
a_1_in <= X"637434b8";
a_2_in <= X"fc6559a9";
a_3_in <= X"5b643f2c";
k_0_in <= X"1c1c1c1c";
k_1_in <= X"1c1c1c1c";
k_2_in <= X"1c1c1c1c";
k_3_in <= X"1c1c1c1c";
wait for clk_period;
assert a_0_out = X"febb00d0"
report "ROUND ERROR (a_0)" severity FAILURE;
assert a_1_out = X"074ee42e"
report "ROUND ERROR (a_1)" severity FAILURE;
assert a_2_out = X"dde647ab"
report "ROUND ERROR (a_2)" severity FAILURE;
assert a_3_out = X"3207ef78"
report "ROUND ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round_f IS
END tb_round_f;
ARCHITECTURE behavior OF tb_round_f IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
PORT(
enc : in std_logic;
rc_in : IN std_logic_vector(31 downto 0);
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal enc : std_logic := '0';
signal rc_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
enc => enc,
rc_in => rc_in,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rc_in <= X"00000080";
a_0_in <= X"61396c93";
a_1_in <= X"637434b8";
a_2_in <= X"fc6559a9";
a_3_in <= X"5b643f2c";
k_0_in <= X"1c1c1c1c";
k_1_in <= X"1c1c1c1c";
k_2_in <= X"1c1c1c1c";
k_3_in <= X"1c1c1c1c";
wait for clk_period;
assert a_0_out = X"febb00d0"
report "ROUND ERROR (a_0)" severity FAILURE;
assert a_1_out = X"074ee42e"
report "ROUND ERROR (a_1)" severity FAILURE;
assert a_2_out = X"dde647ab"
report "ROUND ERROR (a_2)" severity FAILURE;
assert a_3_out = X"3207ef78"
report "ROUND ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
|
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity sdrc_queens_slave is
generic (
-- Design Parameters
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 90;
COUNT_CYCLES : boolean := false;
-- Local Clock Parameters
CLK_FREQ : FREQ := 16 MHz; -- external clock
CLK_MUL : positive := 31; -- computation clock:
CLK_DIV : positive := 4 -- CLK_FREQ / CLK_DIV * CLK_MUL
);
port (
---------------------------------------------------------------------------
-- 16-MHz Input Clock
CLK16_U : in std_logic;
---------------------------------------------------------------------------
-- Ring Bus
-- Input
BUS_IN_CLKP : in std_logic;
BUS_IN_CLKN : in std_logic;
BUS_IN_PRE_DAT : in std_logic_vector(8 downto 0);
BUS_IN_PRE_PUT : in std_logic;
BUS_IN_PRE_GO : out std_logic;
BUS_IN_SOL_DAT : in std_logic_vector(8 downto 0);
BUS_IN_SOL_PUT : in std_logic;
BUS_IN_SOL_GO : out std_logic;
-- Output
BUS_OUT_CLKP : out std_logic;
BUS_OUT_CLKN : out std_logic;
BUS_OUT_PRE_DAT : out std_logic_vector(8 downto 0);
BUS_OUT_PRE_PUT : out std_logic;
BUS_OUT_PRE_GO : in std_logic;
BUS_OUT_SOL_DAT : out std_logic_vector(8 downto 0);
BUS_OUT_SOL_PUT : out std_logic;
BUS_OUT_SOL_GO : in std_logic;
---------------------------------------------------------------------------
-- State
led : out std_logic_vector(3 downto 0)
);
end sdrc_queens_slave;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.fifo.all;
library UNISIM;
use UNISIM.vcomponents.all;
architecture rtl of sdrc_queens_slave is
-- Bit Length of Pre-Placement
constant PRE_BITS : positive := 4*L*log2ceil(N)-1;
constant PRE_BYTES : positive := (PRE_BITS+7)/8;
-- FIFO Dimensioning
constant FIFO_DEPTH : positive := 5*(SOLVERS+5);
----------------------------------------------------------------------------
-- Global Control: Clocks and Resets
signal clk_comp : std_logic; -- Computation Clock
signal rst_comp : std_logic;
signal clk_out : std_logic; -- Communication Clock (Output Side)
signal rst_out : std_logic;
-----------------------------------------------------------------------------
-- Solver Chain Connectivity
signal piful : std_logic;
signal pidat : byte;
signal pieof : std_logic;
signal piput : std_logic;
signal sivld : std_logic;
signal sidat : byte;
signal sieof : std_logic;
signal sigot : std_logic;
signal poful : std_logic;
signal podat : byte;
signal poeof : std_logic;
signal poput : std_logic;
signal sovld : std_logic;
signal sodat : byte;
signal soeof : std_logic;
signal sogot : std_logic;
begin
----------------------------------------------------------------------------
-- Clock Generation
blkClock: block
-- Intermediate Clock Signals
signal clk16 : std_logic; -- Buffered Input Clock
signal clk_comp_u : std_logic;
signal locked_comp : std_logic;
begin
-- 16 MHz Board Clock -> Computation Clock
clk16_buf : IBUFG
port map (
I => CLK16_U,
O => clk16
);
DCM0 : DCM_BASE
generic map (
CLKIN_PERIOD => to_real(1.0/CLK_FREQ, 1 ns),
CLKIN_DIVIDE_BY_2 => FALSE,
PHASE_SHIFT => 0,
CLKFX_MULTIPLY => CLK_MUL,
CLKFX_DIVIDE => CLK_DIV,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE", -- only using clkfx
DLL_FREQUENCY_MODE => "LOW",
DFS_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
STARTUP_WAIT => TRUE,
DCM_AUTOCALIBRATION => FALSE
)
port map (
CLKIN => clk16,
CLKFB => '0',
RST => '0',
CLK0 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => clk_comp_u,
CLKFX180 => open,
LOCKED => locked_comp
);
clk_comp_buf : BUFGCE
port map (
CE => locked_comp,
I => clk_comp_u,
O => clk_comp
);
rst_comp <= '0';
clk_out_buf : BUFGCE
port map (
CE => locked_comp,
I => clk16,
O => clk_out
);
rst_out <= '0';
led(0) <= locked_comp;
end block blkClock;
---------------------------------------------------------------------------
-- Solver Chain
blkChain: block is
signal pful : std_logic;
signal pdat : byte;
signal peof : std_logic;
signal pput : std_logic;
begin
chain: entity work.queens_chain
generic map (
N => N,
L => L,
SOLVERS => SOLVERS,
COUNT_CYCLES => COUNT_CYCLES
)
port map (
clk => clk_comp,
rst => rst_comp,
piful => piful,
pidat => pidat,
pieof => pieof,
piput => piput,
sivld => '0',
sidat => (others => '-'),
sieof => '-',
sigot => open,
poful => pful,
podat => pdat,
poeof => peof,
poput => pput,
sovld => sovld,
sodat => sodat,
soeof => soeof,
sogot => sogot
);
-- Resync stream so that frames are taken out in one piece
sync: entity work.msg_tap
generic map (
D => PRE_BYTES
)
port map (
clk => clk_comp,
rst => rst_comp,
iful => pful,
idat => pdat,
ieof => peof,
iput => pput,
oful => poful,
odat => podat,
oeof => poeof,
oput => poput,
tful => '1',
tdat => open,
tput => open
);
end block blkChain;
-----------------------------------------------------------------------------
-- Input Stream -> feeds pi(ful|dat|eof|put) and si(vld|dat|eof|got)
blkInput: block
-- Source synchronous clock domain
signal clk_in : std_logic;
signal rst_in : std_logic;
-- Incoming Bus Data Capture Registers
signal InPreDat : std_logic_vector(8 downto 0) := (others => '-');
signal InPrePut : std_logic := '0';
signal InPreCap : std_logic_vector(1 downto 0);
signal InSolDat : std_logic_vector(8 downto 0) := (others => '-');
signal InSolPut : std_logic := '0';
signal InSolCap : std_logic_vector(1 downto 0);
signal pivld : std_logic;
begin
---------------------------------------------------------------------------
-- Reading the Bus
-- Clock reconstruction
blkClock : block
signal clk_in0 : std_logic;
begin
IBUFGDS_inst : IBUFGDS
port map (
O => clk_in0,
I => BUS_IN_CLKP,
IB => BUS_IN_CLKN
);
BUFG_inst : BUFR
port map (
I => clk_in0,
O => clk_in,
CE => '1',
CLR => '0'
);
rst_in <= '0';
end block blkClock;
-- Bus Input Capture
process(clk_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
InPreDat <= (others => '-');
InPrePut <= '0';
InSolDat <= (others => '-');
InSolPut <= '0';
else
InPreDat <= BUS_IN_PRE_DAT;
InPrePut <= BUS_IN_PRE_PUT;
InSolDat <= BUS_IN_SOL_DAT;
InSolPut <= BUS_IN_SOL_PUT;
end if;
end if;
end process;
-- Input FIFO (ic): Pre-Placements
buf_pre : fifo_ic_got
generic map (
D_BITS => 9,
MIN_DEPTH => 64,
ESTATE_WR_BITS => InPreCap'length
)
port map (
clk_wr => clk_in,
rst_wr => rst_in,
put => InPrePut,
din => InPreDat,
full => open,
estate_wr => InPreCap,
clk_rd => clk_comp,
rst_rd => rst_comp,
got => piput,
dout(8) => pieof,
dout(7 downto 0) => pidat,
valid => pivld
);
piput <= pivld and not piful;
BUS_IN_PRE_GO <= '0' when InPreCap = (InPreCap'range => '0') else '1';
-- Input FIFO (ic): Solutions
buf_sol : fifo_ic_got
generic map (
D_BITS => 9,
MIN_DEPTH => 64,
ESTATE_WR_BITS => InSolCap'length
)
port map (
clk_wr => clk_in,
rst_wr => rst_in,
put => InSolPut,
din => InSolDat,
full => open,
estate_wr => InSolCap,
clk_rd => clk_out,
rst_rd => rst_out,
got => sigot,
dout(8) => sieof,
dout(7 downto 0) => sidat,
valid => sivld
);
BUS_IN_SOL_GO <= '0' when InSolCap = (InSolCap'range => '0') else '1';
end block blkInput;
blkOutput : block
begin
-------------------------------------------------------------------------
-- Output Inverted Clock
blkClock : block
signal clk_inv : std_logic;
begin
invert : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '1',
SRTYPE => "SYNC"
)
port map (
Q => clk_inv, -- 1-bit DDR output
C => clk_out, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => '0', -- 1-bit data input (positive edge)
D2 => '1', -- 1-bit data input (negative edge)
R => rst_out, -- 1-bit reset input
S => '0' -- 1-bit set input
);
OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "DEFAULT",
SLEW => "FAST"
)
port map (
O => BUS_OUT_CLKP,
OB => BUS_OUT_CLKN,
I => clk_inv
);
end block blkClock;
blkPre: block
-- Syncing the go input
signal go_s : std_logic_vector(1 downto 0) := (others => '0');
-- Output FIFO
signal pgot : std_logic;
signal pdat : std_logic_vector(8 downto 0);
signal pvld : std_logic;
-- Outgoing Output Registers
signal PreOutDat : std_logic_vector(8 downto 0) := (others => '0');
signal PreOutPut : std_logic := '0';
begin
-- Syncing go input
process(clk_out)
begin
if rising_edge(clk_out) then
if rst_out = '1' then
go_s <= (others => '0');
else
go_s <= BUS_OUT_PRE_GO & go_s(go_s'left downto 1);
end if;
end if;
end process;
-- Output FIFO (ic): Pre-Placements
fifob : fifo_ic_got
generic map (
D_BITS => 9,
MIN_DEPTH => 64
)
port map (
clk_wr => clk_comp,
rst_wr => rst_comp,
put => poput,
din(8) => poeof,
din(7 downto 0) => podat,
full => poful,
clk_rd => clk_out,
rst_rd => rst_out,
got => pgot,
dout => pdat,
valid => pvld
);
pgot <= pvld and go_s(0);
-- Output Registers
process(clk_out)
begin
if rising_edge(clk_out) then
if rst_out = '1' then
PreOutDat <= (others => '0');
PreOutPut <= '0';
else
PreOutDat <= pdat;
PreOutPut <= pgot;
end if;
end if;
end process;
BUS_OUT_PRE_DAT <= PreOutDat;
BUS_OUT_PRE_PUT <= PreOutPut;
end block blkPre;
blkSol: block
-- Syncing the go input
signal go_s : std_logic_vector(1 downto 0) := (others => '0');
-- Chain -> fifo_ic [clk_comp->clk_out]
signal soful : std_logic;
-- fifo_ic -> funnel
signal scvld : std_logic;
signal scdat : std_logic_vector(8 downto 0);
signal scgot : std_logic;
-- funnel -> fifo_glue
signal sjful : std_logic;
signal sjdat : std_logic_vector(8 downto 0);
signal sjput : std_logic;
-- fifo_glue -> output
signal sfvld : std_logic;
signal sfdat : std_logic_vector(8 downto 0);
signal sfgot : std_logic;
-- Outgoing Output Registers
signal SolOutDat : std_logic_vector(8 downto 0) := (others => '0');
signal SolOutPut : std_logic := '0';
begin
-- Syncing go input
process(clk_out)
begin
if rising_edge(clk_out) then
if rst_out = '1' then
go_s <= (others => '0');
else
go_s <= BUS_OUT_SOL_GO & go_s(go_s'left downto 1);
end if;
end if;
end process;
-- fifo_ic: clk_comp -> clk_out
fifob : fifo_ic_got
generic map (
D_BITS => 9,
MIN_DEPTH => 64
)
port map (
clk_wr => clk_comp,
rst_wr => rst_comp,
put => sogot,
din(8) => soeof,
din(7 downto 0) => sodat,
full => soful,
clk_rd => clk_out,
rst_rd => rst_out,
got => scgot,
dout => scdat,
valid => scvld
);
sogot <= sovld and not soful;
-- funnel: si* + sc* -> sj*
join: entity work.msg_funnel
generic map (
N => 2
)
port map (
clk => clk_out,
rst => rst_out,
ivld(0) => scvld,
ivld(1) => sivld,
idat(0) => scdat(7 downto 0),
idat(1) => sidat,
ieof(0) => scdat(8),
ieof(1) => sieof,
igot(0) => scgot,
igot(1) => sigot,
oful => sjful,
odat => sjdat(7 downto 0),
oeof => sjdat(8),
oput => sjput
);
-- fifo_glue
glue: fifo_glue
generic map (
D_BITS => 9
)
port map (
clk => clk_out,
rst => rst_out,
put => sjput,
di => sjdat,
ful => sjful,
vld => sfvld,
do => sfdat,
got => sfgot
);
sfgot <= sfvld and go_s(0);
-- Output Registers
process(clk_out)
begin
if rising_edge(clk_out) then
if rst_out = '1' then
SolOutDat <= (others => '0');
SolOutPut <= '0';
else
SolOutDat <= sfdat;
SolOutPut <= sfgot;
end if;
end if;
end process;
BUS_OUT_SOL_DAT <= SolOutDat;
BUS_OUT_SOL_PUT <= SolOutPut;
end block blkSol;
end block blkOutput;
led(3 downto 1) <= "110";
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity s3a_clockgen is
port (
clk_50 : in std_logic;
reset_in : in std_logic;
dcm_lock : out std_logic;
sys_clock : out std_logic; -- 50 MHz
sys_reset : out std_logic;
sys_clock_2x : out std_logic;
sys_clock_4x : out std_logic;
drive_stop : in std_logic := '0';
drv_clock_en : out std_logic; -- 1/12.5 (4 MHz)
cpu_clock_en : out std_logic; -- 1/50 (1 MHz)
eth_clock : out std_logic; -- / 2.5 (20 MHz)
iec_reset_n : in std_logic := '1';
iec_reset_o : out std_logic );
end s3a_clockgen;
architecture Gideon of s3a_clockgen is
signal clk_in_buf : std_logic;
signal sys_clk_buf : std_logic;
signal reset_dcm : std_logic;
signal reset_cnt : integer range 0 to 63 := 0;
signal dcm1_locked : std_logic := '1';
signal sys_clk_i : std_logic := '0';
signal sys_reset_i : std_logic := '1';
signal sys_reset_p : std_logic := '1';
signal div_cnt : std_logic_vector(3 downto 0) := "0000";
signal pre_cnt : std_logic_vector(1 downto 0) := "00";
signal cpu_cke_i : std_logic := '0';
signal toggle : std_logic := '0';
signal reset_c : std_logic;
signal reset_out : std_logic := '1';
signal sysrst_cnt : integer range 0 to 63;
signal iec_reset_sh : std_logic_vector(0 to 2) := "000";
-- signal reset_sample_cnt : integer range 0 to 127 := 0;
-- signal reset_float : std_logic := '1';
attribute register_duplication : string;
attribute register_duplication of sys_reset_i : signal is "no";
signal clk_0_pre : std_logic;
signal clk_2x_pre : std_logic;
signal clk_4x_pre : std_logic;
begin
dcm_lock <= dcm1_locked;
bufg_in : BUFG port map (I => clk_50, O => clk_in_buf);
process(clk_in_buf)
begin
if rising_edge(clk_in_buf) then
if reset_cnt = 63 then
reset_dcm <= '0';
else
reset_cnt <= reset_cnt + 1;
reset_dcm <= '1';
end if;
end if;
if reset_in='1' then
reset_dcm <= '1';
reset_cnt <= 0;
end if;
end process;
dcm_shft: DCM
generic map
(
CLKIN_PERIOD => 20.0,
-- CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
-- PHASE_SHIFT => -20,
CLKDV_DIVIDE => 2.5,
CLKFX_MULTIPLY => 4,
CLKFX_DIVIDE => 1,
STARTUP_WAIT => true
)
port map
(
CLKIN => clk_in_buf,
CLKFB => sys_clk_buf,
CLK0 => clk_0_pre,
CLK2X => clk_2x_pre,
CLKFX => clk_4x_pre,
CLKDV => eth_clock,
LOCKED => dcm1_locked,
RST => reset_dcm
);
bufg_sys: BUFG port map (I => clk_0_pre, O => sys_clk_buf);
bufg_sys2x: BUFG port map (I => clk_2x_pre, O => sys_clock_2x);
bufg_sys4x: BUFG port map (I => clk_4x_pre, O => sys_clock_4x);
sys_clk_i <= sys_clk_buf;
sys_clock <= sys_clk_buf;
process(sys_clk_i, dcm1_locked)
begin
if rising_edge(sys_clk_i) then
if sysrst_cnt = 63 then
sys_reset_i <= '0';
else
sysrst_cnt <= sysrst_cnt + 1;
end if;
sys_reset_p <= sys_reset_i;
drv_clock_en <= '0';
cpu_cke_i <= '0';
if drive_stop='0' then
if (div_cnt = X"B" and toggle='0') or
(div_cnt = X"C" and toggle='1') then
div_cnt <= X"0";
drv_clock_en <= '1';
toggle <= not toggle;
pre_cnt <= pre_cnt + 1;
if pre_cnt = "11" then
cpu_cke_i <= '1';
else
cpu_cke_i <= '0';
end if;
else
div_cnt <= div_cnt + 1;
end if;
end if;
if cpu_cke_i = '1' then
iec_reset_sh(0) <= not iec_reset_n;
iec_reset_sh(1 to 2) <= iec_reset_sh(0 to 1);
end if;
if sys_reset_p='1' then
toggle <= '0';
pre_cnt <= (others => '0');
div_cnt <= (others => '0');
end if;
end if;
if dcm1_locked='0' then
sysrst_cnt <= 0;
sys_reset_i <= '1';
sys_reset_p <= '1';
end if;
end process;
sys_reset <= sys_reset_p;
cpu_clock_en <= cpu_cke_i;
iec_reset_o <= '1' when iec_reset_sh="111" else '0';
end Gideon; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity s3a_clockgen is
port (
clk_50 : in std_logic;
reset_in : in std_logic;
dcm_lock : out std_logic;
sys_clock : out std_logic; -- 50 MHz
sys_reset : out std_logic;
sys_clock_2x : out std_logic;
sys_clock_4x : out std_logic;
drive_stop : in std_logic := '0';
drv_clock_en : out std_logic; -- 1/12.5 (4 MHz)
cpu_clock_en : out std_logic; -- 1/50 (1 MHz)
eth_clock : out std_logic; -- / 2.5 (20 MHz)
iec_reset_n : in std_logic := '1';
iec_reset_o : out std_logic );
end s3a_clockgen;
architecture Gideon of s3a_clockgen is
signal clk_in_buf : std_logic;
signal sys_clk_buf : std_logic;
signal reset_dcm : std_logic;
signal reset_cnt : integer range 0 to 63 := 0;
signal dcm1_locked : std_logic := '1';
signal sys_clk_i : std_logic := '0';
signal sys_reset_i : std_logic := '1';
signal sys_reset_p : std_logic := '1';
signal div_cnt : std_logic_vector(3 downto 0) := "0000";
signal pre_cnt : std_logic_vector(1 downto 0) := "00";
signal cpu_cke_i : std_logic := '0';
signal toggle : std_logic := '0';
signal reset_c : std_logic;
signal reset_out : std_logic := '1';
signal sysrst_cnt : integer range 0 to 63;
signal iec_reset_sh : std_logic_vector(0 to 2) := "000";
-- signal reset_sample_cnt : integer range 0 to 127 := 0;
-- signal reset_float : std_logic := '1';
attribute register_duplication : string;
attribute register_duplication of sys_reset_i : signal is "no";
signal clk_0_pre : std_logic;
signal clk_2x_pre : std_logic;
signal clk_4x_pre : std_logic;
begin
dcm_lock <= dcm1_locked;
bufg_in : BUFG port map (I => clk_50, O => clk_in_buf);
process(clk_in_buf)
begin
if rising_edge(clk_in_buf) then
if reset_cnt = 63 then
reset_dcm <= '0';
else
reset_cnt <= reset_cnt + 1;
reset_dcm <= '1';
end if;
end if;
if reset_in='1' then
reset_dcm <= '1';
reset_cnt <= 0;
end if;
end process;
dcm_shft: DCM
generic map
(
CLKIN_PERIOD => 20.0,
-- CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
-- PHASE_SHIFT => -20,
CLKDV_DIVIDE => 2.5,
CLKFX_MULTIPLY => 4,
CLKFX_DIVIDE => 1,
STARTUP_WAIT => true
)
port map
(
CLKIN => clk_in_buf,
CLKFB => sys_clk_buf,
CLK0 => clk_0_pre,
CLK2X => clk_2x_pre,
CLKFX => clk_4x_pre,
CLKDV => eth_clock,
LOCKED => dcm1_locked,
RST => reset_dcm
);
bufg_sys: BUFG port map (I => clk_0_pre, O => sys_clk_buf);
bufg_sys2x: BUFG port map (I => clk_2x_pre, O => sys_clock_2x);
bufg_sys4x: BUFG port map (I => clk_4x_pre, O => sys_clock_4x);
sys_clk_i <= sys_clk_buf;
sys_clock <= sys_clk_buf;
process(sys_clk_i, dcm1_locked)
begin
if rising_edge(sys_clk_i) then
if sysrst_cnt = 63 then
sys_reset_i <= '0';
else
sysrst_cnt <= sysrst_cnt + 1;
end if;
sys_reset_p <= sys_reset_i;
drv_clock_en <= '0';
cpu_cke_i <= '0';
if drive_stop='0' then
if (div_cnt = X"B" and toggle='0') or
(div_cnt = X"C" and toggle='1') then
div_cnt <= X"0";
drv_clock_en <= '1';
toggle <= not toggle;
pre_cnt <= pre_cnt + 1;
if pre_cnt = "11" then
cpu_cke_i <= '1';
else
cpu_cke_i <= '0';
end if;
else
div_cnt <= div_cnt + 1;
end if;
end if;
if cpu_cke_i = '1' then
iec_reset_sh(0) <= not iec_reset_n;
iec_reset_sh(1 to 2) <= iec_reset_sh(0 to 1);
end if;
if sys_reset_p='1' then
toggle <= '0';
pre_cnt <= (others => '0');
div_cnt <= (others => '0');
end if;
end if;
if dcm1_locked='0' then
sysrst_cnt <= 0;
sys_reset_i <= '1';
sys_reset_p <= '1';
end if;
end process;
sys_reset <= sys_reset_p;
cpu_clock_en <= cpu_cke_i;
iec_reset_o <= '1' when iec_reset_sh="111" else '0';
end Gideon; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity s3a_clockgen is
port (
clk_50 : in std_logic;
reset_in : in std_logic;
dcm_lock : out std_logic;
sys_clock : out std_logic; -- 50 MHz
sys_reset : out std_logic;
sys_clock_2x : out std_logic;
sys_clock_4x : out std_logic;
drive_stop : in std_logic := '0';
drv_clock_en : out std_logic; -- 1/12.5 (4 MHz)
cpu_clock_en : out std_logic; -- 1/50 (1 MHz)
eth_clock : out std_logic; -- / 2.5 (20 MHz)
iec_reset_n : in std_logic := '1';
iec_reset_o : out std_logic );
end s3a_clockgen;
architecture Gideon of s3a_clockgen is
signal clk_in_buf : std_logic;
signal sys_clk_buf : std_logic;
signal reset_dcm : std_logic;
signal reset_cnt : integer range 0 to 63 := 0;
signal dcm1_locked : std_logic := '1';
signal sys_clk_i : std_logic := '0';
signal sys_reset_i : std_logic := '1';
signal sys_reset_p : std_logic := '1';
signal div_cnt : std_logic_vector(3 downto 0) := "0000";
signal pre_cnt : std_logic_vector(1 downto 0) := "00";
signal cpu_cke_i : std_logic := '0';
signal toggle : std_logic := '0';
signal reset_c : std_logic;
signal reset_out : std_logic := '1';
signal sysrst_cnt : integer range 0 to 63;
signal iec_reset_sh : std_logic_vector(0 to 2) := "000";
-- signal reset_sample_cnt : integer range 0 to 127 := 0;
-- signal reset_float : std_logic := '1';
attribute register_duplication : string;
attribute register_duplication of sys_reset_i : signal is "no";
signal clk_0_pre : std_logic;
signal clk_2x_pre : std_logic;
signal clk_4x_pre : std_logic;
begin
dcm_lock <= dcm1_locked;
bufg_in : BUFG port map (I => clk_50, O => clk_in_buf);
process(clk_in_buf)
begin
if rising_edge(clk_in_buf) then
if reset_cnt = 63 then
reset_dcm <= '0';
else
reset_cnt <= reset_cnt + 1;
reset_dcm <= '1';
end if;
end if;
if reset_in='1' then
reset_dcm <= '1';
reset_cnt <= 0;
end if;
end process;
dcm_shft: DCM
generic map
(
CLKIN_PERIOD => 20.0,
-- CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
-- PHASE_SHIFT => -20,
CLKDV_DIVIDE => 2.5,
CLKFX_MULTIPLY => 4,
CLKFX_DIVIDE => 1,
STARTUP_WAIT => true
)
port map
(
CLKIN => clk_in_buf,
CLKFB => sys_clk_buf,
CLK0 => clk_0_pre,
CLK2X => clk_2x_pre,
CLKFX => clk_4x_pre,
CLKDV => eth_clock,
LOCKED => dcm1_locked,
RST => reset_dcm
);
bufg_sys: BUFG port map (I => clk_0_pre, O => sys_clk_buf);
bufg_sys2x: BUFG port map (I => clk_2x_pre, O => sys_clock_2x);
bufg_sys4x: BUFG port map (I => clk_4x_pre, O => sys_clock_4x);
sys_clk_i <= sys_clk_buf;
sys_clock <= sys_clk_buf;
process(sys_clk_i, dcm1_locked)
begin
if rising_edge(sys_clk_i) then
if sysrst_cnt = 63 then
sys_reset_i <= '0';
else
sysrst_cnt <= sysrst_cnt + 1;
end if;
sys_reset_p <= sys_reset_i;
drv_clock_en <= '0';
cpu_cke_i <= '0';
if drive_stop='0' then
if (div_cnt = X"B" and toggle='0') or
(div_cnt = X"C" and toggle='1') then
div_cnt <= X"0";
drv_clock_en <= '1';
toggle <= not toggle;
pre_cnt <= pre_cnt + 1;
if pre_cnt = "11" then
cpu_cke_i <= '1';
else
cpu_cke_i <= '0';
end if;
else
div_cnt <= div_cnt + 1;
end if;
end if;
if cpu_cke_i = '1' then
iec_reset_sh(0) <= not iec_reset_n;
iec_reset_sh(1 to 2) <= iec_reset_sh(0 to 1);
end if;
if sys_reset_p='1' then
toggle <= '0';
pre_cnt <= (others => '0');
div_cnt <= (others => '0');
end if;
end if;
if dcm1_locked='0' then
sysrst_cnt <= 0;
sys_reset_i <= '1';
sys_reset_p <= '1';
end if;
end process;
sys_reset <= sys_reset_p;
cpu_clock_en <= cpu_cke_i;
iec_reset_o <= '1' when iec_reset_sh="111" else '0';
end Gideon; |
entity test is
constant a : b :=
??foo + bar;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grgpio
-- File: grgpio.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Scalable general-purpose I/O port
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity grgpio is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0; -- Only synchronous reset
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#;
pirq : integer := 0;
irqgen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end;
architecture rtl of grgpio is
constant REVISION : integer := 2;
constant PIMASK : std_logic_vector(31 downto 0) := '0' & conv_std_logic_vector(imask, 31);
constant BPMASK : std_logic_vector(31 downto 0) := conv_std_logic_vector(bypass, 32);
constant BPDIRM : std_logic_vector(31 downto 0) := conv_std_logic_vector(bpdir, 32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GPIO, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
-- Prevent tools from issuing index errors for unused code
function calc_nirqmux return integer is
begin
if irqgen = 0 then return 1; end if;
return irqgen;
end;
constant NIRQMUX : integer := calc_nirqmux;
subtype irqmap_type is std_logic_vector(log2x(NIRQMUX)-1 downto 0);
type irqmap_array_type is array (natural range <>) of irqmap_type;
type registers is record
din1 : std_logic_vector(nbits-1 downto 0);
din2 : std_logic_vector(nbits-1 downto 0);
dout : std_logic_vector(nbits-1 downto 0);
imask : std_logic_vector(nbits-1 downto 0);
level : std_logic_vector(nbits-1 downto 0);
edge : std_logic_vector(nbits-1 downto 0);
ilat : std_logic_vector(nbits-1 downto 0);
dir : std_logic_vector(nbits-1 downto 0);
bypass : std_logic_vector(nbits-1 downto 0);
irqmap : irqmap_array_type(nbits-1 downto 0);
end record;
constant nbitszero : std_logic_vector(nbits-1 downto 0) := (others => '0');
constant irqmapzero : irqmap_array_type(nbits-1 downto 0) := (others => (others => '0'));
function dirzero_func return std_logic_vector is
variable vres : std_logic_vector(nbits-1 downto 0);
begin
vres := (others => '0');
if oepol = 0 then vres := (others => '1'); end if;
return vres;
end function dirzero_func;
constant dirzero : std_logic_vector(nbits-1 downto 0) := dirzero_func;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : registers := (
din1 => nbitszero, din2 => nbitszero, -- Sync. regs, not reset
dout => nbitszero,imask => nbitszero, level => nbitszero, edge => nbitszero,
ilat => nbitszero, dir => dirzero, bypass => nbitszero, irqmap => irqmapzero);
signal r, rin : registers;
signal arst : std_ulogic;
begin
arst <= apbi.testrst when (scantest = 1) and (apbi.testen = '1') else rst;
comb : process(rst, r, apbi, gpioi)
variable readdata, tmp2, dout, dir, pval, din : std_logic_vector(31 downto 0);
variable v : registers;
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
din := (others => '0');
din(nbits-1 downto 0) := gpioi.din(nbits-1 downto 0);
v := r; v.din2 := r.din1; v.din1 := din(nbits-1 downto 0);
v.ilat := r.din2; dout := (others => '0'); dir := (others => '0');
dir(nbits-1 downto 0) := r.dir(nbits-1 downto 0);
if (syncrst = 1) and (rst = '0') then
if oepol = 0 then dir(nbits-1 downto 0) := (others => '1');
else dir(nbits-1 downto 0) := (others => '0'); end if;
end if;
dout(nbits-1 downto 0) := r.dout(nbits-1 downto 0);
-- read registers
readdata := (others => '0');
case apbi.paddr(5 downto 2) is
when "0000" => readdata(nbits-1 downto 0) := r.din2;
when "0001" => readdata(nbits-1 downto 0) := r.dout;
when "0010" =>
if oepol = 0 then readdata(nbits-1 downto 0) := not r.dir;
else readdata(nbits-1 downto 0) := r.dir; end if;
when "0011" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.imask(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0100" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.level(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0101" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.edge(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0110" =>
if (bypass /= 0) then
readdata(nbits-1 downto 0) :=
r.bypass(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when "0111" =>
readdata(12 downto 8) := conv_std_logic_vector(irqgen, 5);
readdata(4 downto 0) := conv_std_logic_vector(nbits-1, 5);
when others =>
if irqgen > 1 then
for i in 0 to (nbits+3)/4-1 loop
if i = conv_integer(apbi.paddr(4 downto 2)) then
for j in 0 to 3 loop
if (j+i*4) > (nbits-1) then
exit;
end if;
readdata((24+log2x(NIRQMUX)-1-j*8) downto (24-j*8)) := r.irqmap(i*4+j);
end loop;
end if;
end loop;
end if;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" => null;
when "0001" => v.dout := apbi.pwdata(nbits-1 downto 0);
when "0010" =>
if oepol = 0 then v.dir := not apbi.pwdata(nbits-1 downto 0);
else v.dir := apbi.pwdata(nbits-1 downto 0); end if;
when "0011" =>
if (imask /= 0) then
v.imask := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0100" =>
if (imask /= 0) then
v.level := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0101" =>
if (imask /= 0) then
v.edge := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0110" =>
if (bypass /= 0) then
v.bypass := apbi.pwdata(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when "0111" =>
null;
when others =>
if irqgen > 1 then
for i in 0 to (nbits+3)/4-1 loop
if i = conv_integer(apbi.paddr(4 downto 2)) then
for j in 0 to 3 loop
if (j+i*4) > (nbits-1) then
exit;
end if;
v.irqmap(i*4+j) := apbi.pwdata((24+log2x(NIRQMUX)-1-j*8) downto (24-j*8));
end loop;
end if;
end loop;
end if;
end case;
end if;
-- interrupt filtering and routing
xirq := (others => '0'); tmp2 := (others => '0');
if (imask /= 0) then
tmp2(nbits-1 downto 0) := r.din2;
for i in 0 to nbits-1 loop
if (PIMASK(i) and r.imask(i)) = '1' then
if r.edge(i) = '1' then
if r.level(i) = '1' then tmp2(i) := r.din2(i) and not r.ilat(i);
else tmp2(i) := not r.din2(i) and r.ilat(i); end if;
else tmp2(i) := r.din2(i) xor not r.level(i); end if;
else
tmp2(i) := '0';
end if;
end loop;
for i in 0 to nbits-1 loop
if irqgen = 0 then
-- IRQ for line i = i + pirq
if (i+pirq) > NAHBIRQ-1 then
exit;
end if;
xirq(i+pirq) := tmp2(i);
else
-- IRQ for line i determined by irq select register i
for j in 0 to NIRQMUX-1 loop
if (j+pirq) > NAHBIRQ-1 then
exit;
end if;
if (irqgen = 1) or (j = conv_integer(r.irqmap(i))) then
xirq(j+pirq) := xirq(j+pirq) or tmp2(i);
end if;
end loop;
end if;
end loop;
end if;
-- drive filtered inputs on the output record
pval := (others => '0');
pval(nbits-1 downto 0) := r.din2;
-- Drive output with gpioi.sig_in for bypassed registers
if bypass /= 0 then
for i in 0 to nbits-1 loop
if r.bypass(i) = '1' then
dout(i) := gpioi.sig_in(i);
end if;
end loop;
end if;
-- Drive output with gpioi.sig_in for bypassed registers
if bpdir /= 0 then
for i in 0 to nbits-1 loop
if (BPDIRM(i) and gpioi.sig_en(i)) = '1' then
dout(i) := gpioi.sig_in(i);
if oepol = 0 then dir(i) := '0'; else dir(i) := '1'; end if;
end if;
end loop;
end if;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.imask := RES.imask; v.bypass := RES.bypass;
v.dir := RES.dir; v.dout := RES.dout;
v.irqmap := RES.irqmap;
end if;
if irqgen < 2 then v.irqmap := (others => (others => '0')); end if;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
if (scantest = 1) and (apbi.testen = '1') then
dir := (others => apbi.testoen);
elsif (syncrst = 1 ) and (rst = '0') then
if oepol = 1 then dir := (others => '0');
else dir := (others => '1'); end if;
end if;
gpioo.dout <= dout;
gpioo.oen <= dir;
gpioo.val <= pval;
-- non filtered input
gpioo.sig_out <= din;
end process;
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk, arst)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers din1 and din2 not reset
r.din1 <= rin.din1;
r.din2 <= rin.din2;
end if;
end if;
if (syncrst = 0 ) and (arst = '0') then
if oepol = 1 then r.dir <= (others => '0');
else r.dir <= (others => '1'); end if;
end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("grgpio" & tost(pindex) &
": " & tost(nbits) & "-bit GPIO Unit rev " & tost(REVISION));
-- pragma translate_on
end;
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: memory_test-bench.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 21:10:12 $
--
--------------------------------------------------------------------------
--
-- Architecture for test bench for behavioural architecture of memory
--
use std.textio.all,
work.dlx_types.all,
work.mem_types.all,
work.bv_arithmetic.bv_addu,
work.images.image_hex;
architecture bench of memory_test is
component clock_gen
port (phi1, phi2 : out bit;
reset : out bit);
end component;
component memory
port (phi1, phi2 : in bit;
a : in dlx_address;
d : inout dlx_word_bus bus;
width : in mem_width;
write_enable : in bit;
burst : in bit;
mem_enable : in bit;
ready : out bit);
end component;
for cg : clock_gen
use entity work.clock_gen(behaviour)
generic map (Tpw => 8 ns, Tps => 2 ns);
for mem : memory
use entity work.memory(behaviour)
generic map (mem_size => 65536,
Tac1 => 95 ns, Tacb => 15 ns, Tpd_clk_out => 2 ns);
signal phi1, phi2, reset : bit;
signal a : dlx_address;
signal d : dlx_word_bus bus;
signal width : mem_width;
signal write_enable, mem_enable, burst, ifetch, ready : bit;
begin
cg : clock_gen
port map (phi1, phi2, reset);
mem : memory
port map (phi1, phi2, a, d, width, write_enable, burst, mem_enable, ready);
test: process
variable data_word : dlx_word;
variable L : line;
VARIABLE blk : dlx_word_array(1 to 4);
procedure write (address : in dlx_address;
data_width : in mem_width;
data : in dlx_word;
Tpd_clk_out : in time -- clock to output delay
) is
begin -- write
wait until phi1 = '1';
if reset = '1' then
return;
end if;
a <= address after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
d <= data after Tpd_clk_out;
write_enable <= '1' after Tpd_clk_out;
burst <= '0' after Tpd_Clk_Out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= '0' after Tpd_clk_out;
loop
wait until phi2 = '0';
exit when ready = '1' or reset = '1';
end loop;
d <= null after Tpd_clk_out;
write_enable <= '0' after Tpd_clk_out;
mem_enable <= '0' after Tpd_clk_out;
end write;
procedure read (address : in dlx_address;
data_width : in mem_width;
instr_fetch : in boolean;
data : out dlx_word;
Tpd_clk_out : in time -- clock to output delay
) is
begin -- read
wait until phi1 = '1';
if reset = '1' then
return;
end if;
a <= address after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
write_enable <= '0' after Tpd_clk_out;
burst <= '0' after Tpd_Clk_Out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= bit'val(boolean'pos(instr_fetch)) after Tpd_clk_out;
loop
wait until phi2 = '0';
exit when ready = '1' or reset = '1';
end loop;
data := d;
mem_enable <= '0' after Tpd_clk_out;
end read;
procedure write_burst (address : in dlx_address;
data : in dlx_word_array;
Tpd_clk_out : in time -- clock to output delay
) is
VARIABLE next_address : dlx_address := address;
VARIABLE ignore_overflow : boolean;
VARIABLE index : natural;
begin -- write_burst
wait until phi1 = '1';
if reset = '1' then
return;
end if;
width <= width_word after Tpd_clk_out;
write_enable <= '1' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= '0' after Tpd_clk_out;
burst <= '1' after Tpd_Clk_Out;
index := data'left;
burst_loop : LOOP
IF (index = data'right) THEN
burst <= '0' after Tpd_Clk_Out;
END IF;
a <= next_address after Tpd_clk_out;
d <= data(index) after Tpd_clk_out;
wait_loop : LOOP
WAIT UNTIL phi2 = '0';
EXIT burst_loop WHEN reset = '1' OR (ready = '1' AND index = data'right);
EXIT wait_loop WHEN ready = '1';
END LOOP wait_loop;
index := index + 1;
bv_addu(next_address, X"00000004", next_address, ignore_overflow);
END LOOP burst_loop;
d <= null after Tpd_clk_out;
write_enable <= '0' after Tpd_clk_out;
mem_enable <= '0' after Tpd_clk_out;
end write_burst;
procedure read_burst (address : in dlx_address;
data : out dlx_word_array;
Tpd_clk_out : in time -- clock to output delay
) is
VARIABLE next_address : dlx_address := address;
VARIABLE ignore_overflow : boolean;
VARIABLE index : natural;
begin -- read_burst
wait until phi1 = '1';
if reset = '1' then
return;
end if;
width <= width_word after Tpd_clk_out;
write_enable <= '0' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= '0' after Tpd_clk_out;
burst <= '1' after Tpd_Clk_Out;
index := data'left;
burst_loop : LOOP
IF (index = data'right) THEN
burst <= '0' after Tpd_Clk_Out;
END IF;
a <= next_address after Tpd_clk_out;
wait_loop : LOOP
WAIT UNTIL phi2 = '0';
data(index) := d;
EXIT burst_loop WHEN reset = '1' OR (ready = '1' AND index = data'right);
EXIT wait_loop WHEN ready = '1';
END LOOP wait_loop;
index := index + 1;
bv_addu(next_address, X"00000004", next_address, ignore_overflow);
END LOOP burst_loop;
mem_enable <= '0' after Tpd_clk_out;
end read_burst;
begin
wait until reset = '0';
write(L, string'("Write word X""00000004"" to 4:"));
writeline(output, L);
write(X"0000_0004", width_word, X"00000004", 2 ns);
--
write(L, string'("Read word from X""00000004"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0004", width_word, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Write halfword X""2222"" to 0:"));
writeline(output, L);
write(X"0000_0000", width_halfword, X"2222_0000", 2 ns);
--
write(L, string'("Write halfword X""3333"" to 2:"));
writeline(output, L);
write(X"0000_0002", width_halfword, X"0000_3333", 2 ns);
--
write(L, string'("Read word from X""00000000"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0000", width_word, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Read halfword from X""00000003"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0003", width_halfword, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Write bytes X""44"" to 4, X""55"" to 5, X""66"" to 6, X""77"" to 7:"));
writeline(output, L);
write(X"0000_0004", width_byte, X"44_00_00_00", 2 ns);
write(X"0000_0005", width_byte, X"00_55_00_00", 2 ns);
write(X"0000_0006", width_byte, X"00_00_66_00", 2 ns);
write(X"0000_0007", width_byte, X"00_00_00_77", 2 ns);
--
write(L, string'("Read word from X""00000004"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0004", width_word, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Read byte from X""00000004"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0004", width_byte, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Read byte from X""00000005"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0005", width_byte, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Read byte from X""00000006"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0006", width_byte, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Read byte from X""00000007"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0007", width_byte, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Write burst to 8..11:"));
writeline(output, L);
blk := (X"88888888", X"99999999", X"AAAAAAAA", X"BBBBBBBB");
write_burst(X"0000_0008", blk, 2 ns);
--
write(L, string'("Read burst from 8..11:"));
writeline(output, L);
blk := (OTHERS => X"0000_0000");
read_burst(X"0000_0008", blk, 2 ns);
write(L, string'(" result: ("));
FOR i IN blk'range LOOP
write(L, image_hex(blk(i)));
IF (i /= blk'right) THEN
write(L, string'(", "));
END IF;
END LOOP; -- i
write(L, ')');
writeline(output, L);
--
-- This should hang
write(L, string'("Read word from X""00100000"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0010_0000", width_word, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, data_word);
writeline(output, L);
--
end process test;
end bench;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 02:34:31 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zybo_zynq_design_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : zybo_zynq_design_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_asr : in STD_LOGIC;
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
aux_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => p_1_in,
I2 => p_2_in,
I3 => \^scndry_out\,
I4 => asr_lpf(0),
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
signal exr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => exr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => exr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(1),
I2 => p_3_out(2),
I3 => \^scndry_out\,
I4 => p_3_out(0),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => dcm_locked,
I1 => lpf_exr,
I2 => lpf_asr,
I3 => Q,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
port (
MB_out : out STD_LOGIC;
Bsr_out : out STD_LOGIC;
Pr_out : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
signal \^bsr_out\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^mb_out\ : STD_LOGIC;
signal \^pr_out\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Bsr_out <= \^bsr_out\;
MB_out <= \^mb_out\;
Pr_out <= \^pr_out\;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr_out\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr_out\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mb_out\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^mb_out\,
S => lpf_int
);
SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0090"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(4),
I2 => seq_cnt(3),
I3 => seq_cnt(5),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr_out\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr_out\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9000"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(4),
I2 => seq_cnt(3),
I3 => seq_cnt(5),
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^mb_out\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0018"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(0),
I2 => seq_cnt(2),
I3 => seq_cnt(1),
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0480"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr_out\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr_out\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
signal Bsr_out : STD_LOGIC;
signal MB_out : STD_LOGIC;
signal Pr_out : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal lpf_int : STD_LOGIC;
attribute box_type : string;
attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE";
attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE";
attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE";
attribute box_type of FDRE_inst : label is "PRIMITIVE";
attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Bsr_out,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
FDRE_inst: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => MB_out,
Q => mb_reset,
R => '0'
);
\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Pr_out,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4,
Bsr_out => Bsr_out,
MB_out => MB_out,
Pr_out => Pr_out,
lpf_int => lpf_int,
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zybo_zynq_design_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2018.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
attribute x_interface_parameter : string;
attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST";
attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST";
attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
-- --------------------------------------------------------------------
-- "fixed_pkg_c.vhdl" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_float_types.all;
-- use ieee_proposed.fixed_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers
-- synthesis tools. Please note the "%%%" comments. These are where we
-- diverge from the VHDL-200X LRM.
-- --------------------------------------------------------------------
-- Version : $Revision: 1.21 $
-- Date : $Date: 2007/09/26 18:08:53 $
-- Version : $Revision: 2.0 $
-- Date : $Date: 2011/01/26 15:55:27 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library IEEE_PROPOSED;
use IEEE_PROPOSED.fixed_float_types.all;
package fixed_pkg is
-- generic (
-- Rounding routine to use in fixed point, fixed_round or fixed_truncate
constant fixed_round_style : fixed_round_style_type := fixed_round;
-- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap
constant fixed_overflow_style : fixed_overflow_style_type := fixed_saturate;
-- Extra bits used in divide routines
constant fixed_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (false
);
-- Author David Bishop (dbishop@vhdl.org)
-- base Unsigned fixed point type, downto direction assumed
type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC;
-- base Signed fixed point type, downto direction assumed
type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC;
subtype U_ufixed is UNRESOLVED_ufixed;
subtype U_sfixed is UNRESOLVED_sfixed;
subtype ufixed is UNRESOLVED_ufixed;
subtype sfixed is UNRESOLVED_sfixed;
--=====
-- Arithmetic Operators:
--=====
-- Absolute value, 2's complement
-- abs sfixed(a downto b) = sfixed(a+1 downto b)
function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Negation, 2's complement
-- - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the binary point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED) return UNRESOLVED_sfixed;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN;
--=====
-- Comparison Operators
--=====
function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "maximum(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function maximum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function minimum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "maximum(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function maximum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function minimum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
--=====
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--=====
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
-- Reduction operators, same as numeric_std functions
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
-- returns arg'low-1 if not found
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
-- returns arg'high+1 if not found
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
--=====
-- RESIZE Functions
--=====
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is fixed_round, then the result will be rounded.
-- If the MSB of the remainder is a "1" AND the LSB of the unrounded result
-- is a '1' or the lower bits of the remainder include a '1' then the result
-- will be increased by the smallest representable number for that type.
-- "overflow_style" can be fixed_saturate or fixed_wrap.
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- "size_res" functions create the size of the output from the indices
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
--=====
-- Conversion Functions
--=====
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Performs a conversion. ufixed (arg'range) is returned
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
size_res : UNSIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : UNRESOLVED_ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL;
-- Integer to UNRESOLVED_sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- signed to sfixed
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed;
-- Conversion from ufixed to sfixed
function to_sfixed (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_sfixed;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to real
function to_real (
arg : UNRESOLVED_sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
--
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed;
--=====
-- Translation Functions
--=====
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_ufixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed;
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_sfixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed;
function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN;
function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not convert these vectors because of their negative index.
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- rtl_synthesis off
-- pragma synthesis_off
--=====
-- string and textio Functions
--=====
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias bread is READ [LINE, UNRESOLVED_ufixed];
alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias bread is READ [LINE, UNRESOLVED_sfixed];
alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (value : UNRESOLVED_ufixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_ufixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING];
function to_ostring (value : UNRESOLVED_ufixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING];
function to_hstring (value : UNRESOLVED_ufixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING];
function to_string (value : UNRESOLVED_sfixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_sfixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING];
function to_ostring (value : UNRESOLVED_sfixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING];
function to_hstring (value : UNRESOLVED_sfixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING];
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed];
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed];
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed];
-- rtl_synthesis on
-- pragma synthesis_on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
end package fixed_pkg;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT fixed_pkg package
-- (Fixed point math package)
-- This package body supplies a recommended implementation of these functions
-- Version : $Revision: 1.21 $
-- Date : $Date: 2007/09/26 18:08:53 $
-- Version : $Revision: 2.0 $
-- Date : $Date: 2011/01/26 15:55:27 $
--
-- Created for VHDL-200X-ft, David Bishop (dbishop@vhdl.org)
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
package body fixed_pkg is
-- Author David Bishop (dbishop@vhdl.org)
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0');
constant NASF : UNRESOLVED_sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
-- %%% Replicated functions
function maximum (
l, r : integer) -- inputs
return integer is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
l, r : integer) -- inputs
return integer is
begin -- function min
if l > r then return r;
else return l;
end if;
end function minimum;
function "sra" (arg : SIGNED; count : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(arg, count);
else
return SHIFT_LEFT(arg, -count);
end if;
end function "sra";
function or_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reduce (BUS_int (BUS_int'left downto Half));
Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reduce;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reduce (BUS_int (BUS_int'left downto Half));
Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reduce;
function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reduce (BUS_int (BUS_int'left downto Half));
Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reduce;
function nand_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not and_reduce (arg);
end function nand_reduce;
function nor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not or_reduce (arg);
end function nor_reduce;
function xnor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not xor_reduce (arg);
end function xnor_reduce;
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- "?=" operator is similar to "std_match", but returns a std_ulogic..
-- Id: M.2B
function \?=\ (L, R: UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\(LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- Id: M.3B
function \?=\ (L, R: SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
function \?/=\ (L, R : UNSIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
result := 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function \?/=\ (L, R : SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function Is_X ( s : UNSIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X ( s : SIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>"\;
function \?>\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<";
function \?<\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<=";
function \?<=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END replicated functions
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition, silent
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report fixed_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_sfixed) -- input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_sfixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_ufixed) -- input
return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_ufixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type convert a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_ufixed(arg);
return result;
end function to_fixed;
-- Type convert a "signed" into an "sfixed", used internally
function to_fixed (
arg : SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_sfixed(arg);
return result;
end function to_fixed;
-- Type convert a "ufixed" into an "unsigned", used internally
function to_uns (
arg : UNRESOLVED_ufixed) -- fp vector
return UNSIGNED is
subtype t is UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
return slv;
end function to_uns;
-- Type convert an "sfixed" into a "signed", used internally
function to_s (
arg : UNRESOLVED_sfixed) -- fp vector
return SIGNED is
subtype t is SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
return slv;
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_ufixed;
result : out UNRESOLVED_ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0)
:= (others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_sfixed;
result : out UNRESOLVED_sfixed;
overflowx : out BOOLEAN) is
variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or_reduce (STD_ULOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : UNRESOLVED_ufixed;
remainder : UNRESOLVED_ufixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_ufixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : UNRESOLVED_sfixed;
remainder : UNRESOLVED_sfixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_sfixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- Sign bit not fixed when wrapping
end if;
end if;
return result;
end function round_fixed;
-- converts an sfixed into a ufixed. The output is the same length as the
-- input, because abs("1000") = "1000" = 8.
function to_ufixed (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_ufixed
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : UNRESOLVED_sfixed(left_index+1 downto right_index);
variable result : UNRESOLVED_ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := UNRESOLVED_ufixed (xarg (left_index downto right_index));
return result;
end function to_ufixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- Conversion functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector(to_sulv(arg));
end function to_slv;
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector(to_sulv(arg));
end function to_slv;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report fixed_pkg'instance_name & "TO_UFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report fixed_pkg'instance_name & "TO_SFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
-- Addition
function "+" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a+c+1 downto b+d)
variable lslv : UNSIGNED (l'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a+c+1 downto b+d)
variable lslv : SIGNED (l'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (l'high - mine(r'low, r'low) downto
mine (l'low, l'low) - r'high -1);
variable dresult : UNRESOLVED_ufixed (result'high downto result'low -guard_bits);
variable lresize : UNRESOLVED_ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report fixed_pkg'instance_name
& "DIVIDE(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (l'high - mine(r'low, r'low) + 1 downto
mine (l'low, l'low) - r'high);
variable dresult : UNRESOLVED_sfixed (result'high downto result'low-guard_bits);
variable lresize : UNRESOLVED_sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : SIGNED (lresize'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report fixed_pkg'instance_name
& "DIVIDE(sfixed) Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
constant one : UNRESOLVED_ufixed (0 downto 0) := "1";
begin
return divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
constant one : UNRESOLVED_sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : UNRESOLVED_sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return remainder (l, r);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return remainder (l, r);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (minimum(l'high, r'high) downto
mine(l'low, r'low));
variable lresize : UNRESOLVED_ufixed (maximum(l'high, r'low) downto
mins(r'low, r'low)-guard_bits);
variable rresize : UNRESOLVED_ufixed (r'high downto r'low-guard_bits);
variable dresult : UNRESOLVED_ufixed (rresize'range);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (rresize'length-1 downto 0);
variable result_slv : UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rresize := resize (arg => r,
left_index => rresize'high,
right_index => rresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
rslv := to_uns (rresize);
if (rslv = 0) then
report fixed_pkg'instance_name
& "remainder(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- can't overflow
round_style => round_style);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (minimum(r'high, l'high) downto
mine(r'low, l'low));
variable neg_result : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
result := UNRESOLVED_sfixed (remainder (
l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return modulo (l, r);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return modulo(l, r);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style,
guard_bits => guard_bits);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (r'high downto
mine(r'low, l'low));
variable dresult : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
dresult := "0" & UNRESOLVED_sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
variable cx : UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
c_out := result_slv(left_index-right_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index
downto 0);
variable result_slv : SIGNED (left_index-right_index
downto 0);
variable cx : SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
c_out := result_slv(left_index-right_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED)
return UNRESOLVED_ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED)
return UNRESOLVED_sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operator_reduces
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
-- End reduction operator_reduces
function \?=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
function \?=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : UNRESOLVED_ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report fixed_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : UNRESOLVED_sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report fixed_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
-- compare functions
function "=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw);
variable sresult : UNRESOLVED_ufixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : NATURAL; -- internal version of arg
begin
if (result'length < 1) then
return NAUF;
end if;
if arg /= 0 then
argx := arg;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := '0';
else
sresult(I) := '1';
end if;
argx := argx/2;
end loop;
if argx /= 0 then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_UFIXED(NATURAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
return saturate (left_index, right_index);
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw);
variable sresult : UNRESOLVED_sfixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : INTEGER; -- internal version of arg
variable sign : STD_ULOGIC; -- sign of input
begin
if (result'length < 1) then -- null range
return NASF;
end if;
if arg /= 0 then
if (arg < 0) then
sign := '1';
argx := -(arg + 1);
else
sign := '0';
argx := arg;
end if;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := sign;
else
sresult(I) := not sign;
end if;
argx := argx/2;
end loop;
if argx /= 0 or left_index < 0 or sign /= sresult(sresult'left) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_saturate then -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_ufixed (left_index downto
fw-guard_bits) :=
(others => '0');
variable presult : REAL;
-- variable overflow_needed : BOOLEAN;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report fixed_pkg'instance_name
& "TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report fixed_pkg'instance_name
& "TO_UFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_sfixed (left_index+1 downto fw-guard_bits) :=
(others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report fixed_pkg'instance_name
& "TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NAUF;
end if;
result := resize (arg => UNRESOLVED_ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- converted version
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return UNRESOLVED_ufixed(xarg);
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NASF;
end if;
result := resize (arg => UNRESOLVED_sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- converted version
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return UNRESOLVED_sfixed(xarg);
end function to_sfixed;
function to_sfixed (arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := UNRESOLVED_sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function to_sfixed;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
constant sat : UNRESOLVED_ufixed (left_index downto right_index) :=
(others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable sat : UNRESOLVED_sfixed (left_index downto right_index) :=
(others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_pkg'instance_name
& "TO_UFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_pkg'instance_name
& "TO_SFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
size_res : UNSIGNED; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : UNRESOLVED_ufixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_REAL (ufixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : UNRESOLVED_sfixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : UNRESOLVED_ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_REAL (sfixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := to_ufixed (arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNSIGNED (left_index+1 downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (ufixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : SIGNED (left_index+1 downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (sfixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : UNRESOLVED_ufixed; -- ufixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (s'range); -- result
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_01(ufixed): null detected, returning NULL"
severity warning;
return NAUF;
end if;
return to_fixed (to_01(to_uns(s), XMAP), s'high, s'low);
end function to_01;
function to_01 (
s : UNRESOLVED_sfixed; -- sfixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (s'range);
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_01(sfixed): null detected, returning NULL"
severity warning;
return NASF;
end if;
return to_fixed (to_01(to_s(s), XMAP), s'high, s'low);
end function to_01;
function Is_X (
arg : UNRESOLVED_ufixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function Is_X (
arg : UNRESOLVED_sfixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function To_X01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_ufixed (arghigh downto arglow);
variable result : UNRESOLVED_ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or_reduce(to_sulv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style = fixed_saturate and
or_reduce (to_sulv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_sfixed (arghigh downto arglow);
variable result : UNRESOLVED_sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) then
reduced := or_reduce (to_sulv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or_reduce (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and_reduce (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded math functions for real
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) + r);
end function "+";
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) - r);
end function "-";
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) * r);
end function "*";
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) mod r);
end function "mod";
-- Overloaded math functions for integers
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, 0));
end function "+";
function "+" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, 0));
end function "+";
function "+" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) + r);
end function "+";
-- Overloaded functions
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, 0));
end function "-";
function "-" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, 0));
end function "-";
function "-" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) - r);
end function "-";
-- Overloaded functions
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, 0));
end function "*";
function "*" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, 0));
end function "*";
function "*" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) * r);
end function "*";
-- Overloaded functions
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, 0));
end function "/";
function "/" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, 0));
end function "/";
function "/" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, 0));
end function "rem";
function "rem" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, 0));
end function "rem";
function "rem" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, 0));
end function "mod";
function "mod" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, 0));
end function "mod";
function "mod" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) mod r);
end function "mod";
-- overloaded ufixed compare functions with integer
function "=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- NATURAL to ufixed
function "=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded ufixed compare functions with real
function "=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- real and ufixed
function "=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with integer
function "=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- integer and sfixed
function "=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with real
function "=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- REAL and sfixed
function "=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- rtl_synthesis off
-- pragma synthesis_off
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- %%% Replicated Textio functions
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_pkg'instance_name
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_pkg'instance_name
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-- %%% END replicated textio functions
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : ufixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_pkg'instance_name & "READ(ufixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_pkg'instance_name & "READ(ufixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_pkg'instance_name & "READ(ufixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_pkg'instance_name & "READ(ufixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : ufixed (VALUE'range);
variable i : INTEGER; -- index variable
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := value'high;
GOOD := false;
while i >= VALUE'low loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
return;
elsif i /= -1 then -- Seperator in the wrong spot
return;
end if;
founddot := true;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character/short read
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then -- reading done
GOOD := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : sfixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_pkg'instance_name & "READ(sfixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_pkg'instance_name & "READ(sfixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_pkg'instance_name & "READ(sfixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_pkg'instance_name & "READ(sfixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
variable value_ufixed : UNRESOLVED_ufixed (VALUE'range);
begin -- READ
READ (L => L, VALUE => value_ufixed, GOOD => GOOD);
VALUE := UNRESOLVED_sfixed (value_ufixed);
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
-- purpose: Routines common to the OREAD routines
procedure OREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_pkg'instance_name
& "OREAD(sfixed) "
& mess
severity error;
else
report fixed_pkg'instance_name
& "OREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (2 downto 0); -- 3 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2triBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-2) := nybble;
i := i - 3;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
igood := true; -- read into a null array
idex := -1;
end if;
end procedure OREAD_common;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD (L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => false);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_pkg'instance_name
& "OREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "OREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_pkg'instance_name
& "OREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "OREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: Routines common to the OREAD routines
procedure HREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_pkg'instance_name
& "HREAD(sfixed) "
& mess
severity error;
else
report fixed_pkg'instance_name
& "HREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (3 downto 0); -- 4 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2QuadBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-3) := nybble;
i := i - 4;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
idex := -1;
igood := true; -- read null string
end if;
end procedure HREAD_common;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if igood then
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_pkg'instance_name
& "HREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "HREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_pkg'instance_name
& "HREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "HREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_ufixed) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable subval : UNRESOLVED_ufixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_string (resize (sfixed(value), 0, value'low));
else
return to_string (resize (value, 0, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_string (value : UNRESOLVED_sfixed) return STRING is
variable s : STRING(1 to value'length + 1) := (others => ' ');
variable subval : UNRESOLVED_sfixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_ostring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_ufixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_ostring (resize (sfixed(value), 2, value'low));
else
return to_ostring (resize (value, 2, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value (value'low));
else
lpad := (others => '0');
end if;
return to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_ufixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_hstring (resize (sfixed(value), 3, value'low));
else
return to_hstring (resize (value, 3, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad);
end if;
end if;
end function to_hstring;
function to_ostring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_sfixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
pad := (others => value(value'high));
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_ostring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_sfixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
pad := (others => value(value'high));
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_hstring(hstring, size_res'high, size_res'low);
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_hstring (hstring, size_res'high, size_res'low);
end function from_hstring;
-- purpose: Calculate the string boundaries
procedure calculate_string_boundry (
arg : in STRING; -- input string
left_index : out INTEGER; -- left
right_index : out INTEGER) is -- right
-- examples "10001.111" would return +4, -3
-- "07X.44" would return +2, -2 (then the octal routine would multiply)
-- "A_B_._C" would return +1, -1 (then the hex routine would multiply)
alias xarg : STRING (arg'length downto 1) is arg; -- make it downto range
variable l, r : INTEGER; -- internal indexes
variable founddot : BOOLEAN := false;
begin
if arg'length > 0 then
l := xarg'high - 1;
r := 0;
for i in xarg'range loop
if xarg(i) = '_' then
if r = 0 then
l := l - 1;
else
r := r + 1;
end if;
elsif xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT then
report fixed_pkg'instance_name
& "Found a space in the input STRING " & xarg
severity error;
elsif xarg(i) = '.' then
if founddot then
report fixed_pkg'instance_name
& "Found two binary points in input string " & xarg
severity error;
else
l := l - i;
r := -i + 1;
founddot := true;
end if;
end if;
end loop;
left_index := l;
right_index := r;
else
left_index := 0;
right_index := 0;
end if;
end procedure calculate_string_boundry;
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
-- pragma synthesis_on
-- rtl_synthesis on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
begin
return to_UFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
begin
return to_SFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_SFix;
end package body fixed_pkg;
|
entity tb_repro_uns is
end tb_repro_uns;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_repro_uns is
signal clk : std_logic;
signal a : unsigned(7 downto 0);
signal b : unsigned(7 downto 0);
begin
dut: entity work.repro_uns
port map (
clk => clk, a => a, b => b);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
a <= x"ab";
pulse;
assert b = x"ab" severity failure;
a <= x"12";
pulse;
assert b = x"12" severity failure;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_780 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_780;
architecture augh of cmp_780 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_780 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_780;
architecture augh of cmp_780 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
-------------------------------------------------------------------------------
-- xor18.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: xor18.vhd
--
-- Description: Basic 18-bit input XOR function.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add default on C_USE_LUT6 parameter.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity XOR18 is
generic (
C_USE_LUT6 : boolean := FALSE );
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end entity XOR18;
architecture IMP of XOR18 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
begin -- architecture IMP
Using_LUT6: if (C_USE_LUT6) generate
signal xor6_1 : std_logic;
signal xor6_2 : std_logic;
signal xor6_3 : std_logic;
signal xor18_c1 : std_logic;
signal xor18_c2 : std_logic;
begin -- generate Using_LUT6
XOR6_1_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => xor6_1,
I0 => InA(17),
I1 => InA(16),
I2 => InA(15),
I3 => InA(14),
I4 => InA(13),
I5 => InA(12));
XOR_1st_MUXCY : MUXCY_L
port map (
DI => '1',
CI => '0',
S => xor6_1,
LO => xor18_c1);
XOR6_2_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => xor6_2,
I0 => InA(11),
I1 => InA(10),
I2 => InA(9),
I3 => InA(8),
I4 => InA(7),
I5 => InA(6));
XOR_2nd_MUXCY : MUXCY_L
port map (
DI => xor6_1,
CI => xor18_c1,
S => xor6_2,
LO => xor18_c2);
XOR6_3_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => xor6_3,
I0 => InA(5),
I1 => InA(4),
I2 => InA(3),
I3 => InA(2),
I4 => InA(1),
I5 => InA(0));
XOR18_XORCY : XORCY
port map (
LI => xor6_3,
CI => xor18_c2,
O => res);
end generate Using_LUT6;
Not_Using_LUT6: if (not C_USE_LUT6) generate
begin -- generate Not_Using_LUT6
res <= InA(17) xor InA(16) xor InA(15) xor InA(14) xor InA(13) xor InA(12) xor
InA(11) xor InA(10) xor InA(9) xor InA(8) xor InA(7) xor InA(6) xor
InA(5) xor InA(4) xor InA(3) xor InA(2) xor InA(1) xor InA(0);
end generate Not_Using_LUT6;
end architecture IMP;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2016 Cobham Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.STARTUPE2;
--pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
use_ahbram_sim : integer := 0
);
port (
clk : in std_ulogic;
-- Switches
sw : in std_logic_vector(15 downto 0);
-- LEDs
led : out std_logic_vector(15 downto 0);
-- Buttons
btnc : in std_ulogic;
btnu : in std_ulogic;
btnl : in std_ulogic;
btnr : in std_ulogic;
btnd : in std_ulogic;
-- VGA connector
vgared : out std_logic_vector(3 downto 0);
vgablue : out std_logic_vector(3 downto 0);
vgagreen : out std_logic_vector(3 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
-- USB-RS232 interface
rstx : in std_logic;
rsrx : out std_logic;
-- SPI
--pragma translate_off
spi_sim_sck : out std_ulogic;
--pragma translate_on
qspicsn : out std_ulogic;
qspidb : inout std_logic_vector(3 downto 0)
);
end;
architecture rtl of leon3mp is
component STARTUPE2
generic (
PROG_USR : string := "FALSE";
SIM_CCLK_FREQ : real := 0.0
);
port (
CFGCLK : out std_ulogic;
CFGMCLK : out std_ulogic;
EOS : out std_ulogic;
PREQ : out std_ulogic;
CLK : in std_ulogic;
GSR : in std_ulogic;
GTS : in std_ulogic;
KEYCLEARB : in std_ulogic;
PACK : in std_ulogic;
USRCCLKO : in std_ulogic;
USRCCLKTS : in std_ulogic;
USRDONEO : in std_ulogic;
USRDONETS : in std_ulogic
);
end component;
signal vcc : std_logic;
signal gnd : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo, cgo1 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal clkm : std_ulogic
-- pragma translate_off
:= '0'
-- pragma translate_on
;
signal rstn : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_ulogic;
signal lbtnc : std_ulogic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
btnc_pad : inpad generic map (tech => padtech) port map (btnc, lbtnc);
rst0 : rstgen generic map (acthigh => 1)
port map (lbtnc, clkm, cgo.clklock, rstn, rstraw);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
nahbs => 6)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR,
CFG_REX, CFG_ALTWIN)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
led(3) <= not dbgo(0).error;
led(2) <= not dsuo.active;
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ahbpf => CFG_AHBPF,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
--dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= rxd1;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
urx_pad : inpad generic map (tech => padtech) port map (rstx, rxd1);
utx_pad : outpad generic map (tech => padtech) port map (rsrx, txd1);
txd1 <= duo.txd when sw(0) = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- SPI Memory controller -------------------------------------------
----------------------------------------------------------------------
spi_gen: if CFG_SPIMCTRL = 1 generate
-- OPTIONALY set the offset generic (only affect reads).
-- The first 4MB are used for loading the FPGA.
-- For dual ouptut: readcmd => 16#3B#, dualoutput => 1
spimctrl1 : spimctrl
generic map (hindex => 0, hirq => 7, faddr => 16#000#, fmask => 16#ff0#,
ioaddr => 16#700#, iomask => 16#fff#, spliten => CFG_SPLIT,
sdcard => CFG_SPIMCTRL_SDCARD, readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT, scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER)
port map (rstn, clkm, ahbsi, ahbso(0), spmi, spmo);
spi_mosi_pad : outpad generic map (tech => padtech)
port map (qspidb(0), spmo.mosi);
spi_miso_pad : inpad generic map (tech => padtech)
port map (qspidb(1), spmi.miso);
spi_slvsel0_pad : outpad generic map (tech => padtech)
port map (qspicsn, spmo.csn);
--spi_sck_pad : outpad generic map (tech => padtech) -- FIXME
-- port map (scl, spmo.sck);
spicclk: STARTUPE2
port map (--CFGCLK => open, CFGMCLK => open, EOS => open, PREQ => open,
CLK => '0', GSR => '0', GTS => '0', KEYCLEARB => '0', PACK => '0',
USRCCLKO => spmo.sck, USRCCLKTS => '0', USRDONEO => '1', USRDONETS => '0' );
--pragma translate_off
spi_sim_sck <= spmo.sck;
--pragma translate_on
end generate;
nospi: if CFG_SPIMCTRL = 0 generate
ahbso(0) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Timer Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 4, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(4));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(4) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
--pragma translate_off
phys : if use_ahbram_sim = 0 generate
--pragma translate_on
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
--pragma translate_off
end generate;
simram : if use_ahbram_sim /= 0 generate
ahbram0 : ahbram_sim
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => 1024, pipe => CFG_AHBRPIPE, fname => "ram.srec")
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
--pragma translate_on
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent Basys3 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_10.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_10
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLROM_3_10
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.fft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_10 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_10_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_10_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_10_vld : OUT std_logic
);
END TWDLROM_3_10;
ARCHITECTURE rtl OF TWDLROM_3_10 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_10_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_10_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#1#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#2#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#2#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_10_re_tmp <= twdlIn_re;
twdl_3_10_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_10_re <= std_logic_vector(twdl_3_10_re_tmp);
twdl_3_10_im <= std_logic_vector(twdl_3_10_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_10_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_10_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
-- Rota posiciones (x,y,z) usando el algoritmo CORDIC iterativamente
library ieee;
use ieee.std_logic_1164.all;
entity pos_rotator is
generic(
Nxy : natural := 16;
Nangle : natural := 16;
Nits : natural := 16
);
port (
clock : in std_logic;
reset : in std_logic;
load : in std_logic;
RxRdy : out std_logic;
alfa, beta, gama : in std_logic_vector(Nangle-1 downto 0);
x0, y0, z0 : in std_logic_vector(Nxy-1 downto 0);
x1, y1, z1 : out std_logic_vector(Nxy-1 downto 0)
);
end;
architecture pos_rotator_arq of pos_rotator is
constant n_reg_in : natural := 1+3*Nxy+3*Nangle-1; -- tamaño de registro de entrada
-- Señales entre etapas
signal xrot_load : std_logic := '0';
signal xrot_RxRdy : std_logic := '0';
signal xrot_angle: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal xrot_x0: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal xrot_y0: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal xrot_x1: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal xrot_x1_delay: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal xrot_y1: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal yrot_load : std_logic := '0';
signal yrot_RxRdy : std_logic := '0';
signal yrot_angle: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal yrot_x0: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal yrot_y0: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal yrot_x1: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal yrot_x1_delay: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal yrot_y1: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal zrot_load : std_logic := '0';
signal zrot_RxRdy : std_logic := '0';
signal zrot_angle: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal zrot_x0: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal zrot_y0: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal zrot_x1: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal zrot_y1: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal out_reg_in : std_logic_vector(1+3*Nxy-1 downto 0) := (others => '0');
signal out_reg_out : std_logic_vector(1+3*Nxy-1 downto 0) := (others => '0');
signal in_reg_in : std_logic_vector(n_reg_in downto 0) := (others => '0');
signal in_reg_out : std_logic_vector(n_reg_in downto 0) := (others => '0');
signal load_delay : std_logic := '0';
signal x0_delay: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal x0_delay_delay: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal y0_delay: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal z0_delay: std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal alfa_delay : std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal beta_delay : std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal gama_delay : std_logic_vector(Nangle-1 downto 0) := (others => '0');
begin
-- Registro de entrada
in_reg_in <= load & x0 & y0 & z0 & alfa & beta & gama;
pipe_reg_in: entity work.registroNb
generic map(
N => 1 + 3*Nxy + 3*Nangle
) port map(
clk => clock,
rst => reset,
ena => '1',
d => in_reg_in,
q => in_reg_out
);
load_delay <= in_reg_out(n_reg_in);
x0_delay <= in_reg_out( n_reg_in -1 downto n_reg_in -Nxy);
y0_delay <= in_reg_out( n_reg_in -Nxy-1 downto n_reg_in -2*Nxy);
z0_delay <= in_reg_out( n_reg_in -2*Nxy-1 downto n_reg_in -3*Nxy);
alfa_delay <= in_reg_out(n_reg_in -3*Nxy -1 downto n_reg_in -3*Nxy -Nangle);
beta_delay <= in_reg_out(n_reg_in -3*Nxy -Nangle-1 downto n_reg_in -3*Nxy -2*Nangle);
gama_delay <= in_reg_out(n_reg_in -3*Nxy -2*Nangle-1 downto n_reg_in -3*Nxy -3*Nangle);
-------------------------------------
-- Rotador según eje X
-------------------------------------
xrot_load <= load_delay;
xrot_x0 <= y0_delay;
xrot_y0 <= z0_delay;
xrot_angle <= alfa_delay;
X_rot: entity work.cordic
generic map(
---Nxy => Nxy,
---Nangle => Nangle,
P => Nits
) port map(
clk => clock,
rst => reset,
load => xrot_load,
x_in => xrot_x0,
y_in => xrot_y0,
angle => xrot_angle,
x_rot => xrot_x1,
y_rot => xrot_y1,
rotRdy => xrot_RxRdy
);
-------------------------------------
-- Delay para x
-------------------------------------
X_del: entity work.delay_reg
generic map(
N => Nxy,
DELAY => Nits +1
)
port map(
clock => clock,
reset => reset,
enable => '1',
A => x0_delay,
B => x0_delay_delay
);
-------------------------------------
-- Rotador según eje Y
-------------------------------------
yrot_load <= xrot_RxRdy;
yrot_x0 <= xrot_y1;
yrot_y0 <= x0_delay_delay;
yrot_angle <= beta_delay;
Y_rot: entity work.cordic
generic map(
---Nxy => Nxy,
---Nangle => Nangle,
P => Nits
) port map(
clk => clock,
rst => reset,
load => yrot_load,
x_in => yrot_x0,
y_in => yrot_y0,
angle => yrot_angle,
x_rot => yrot_x1,
y_rot => yrot_y1,
rotRdy => yrot_RxRdy
);
-------------------------------------
-- Delay para y
-------------------------------------
Y_del: entity work.delay_reg
generic map(
N => Nxy,
DELAY => Nits+1
)
port map(
clock => clock,
reset => reset,
enable => '1',
A => xrot_x1,
B => xrot_x1_delay
);
-------------------------------------
-- Rotador según eje Z (plano XY)
-------------------------------------
zrot_load <= yrot_RxRdy;
zrot_x0 <= yrot_y1;
zrot_y0 <= xrot_x1_delay;
zrot_angle <= gama_delay;
Z_rot: entity work.cordic
generic map(
---Nxy => Nxy,
---Nangle => Nangle,
P => Nits
) port map(
clk => clock,
rst => reset,
load => zrot_load,
x_in => zrot_x0,
y_in => zrot_y0,
angle => zrot_angle,
x_rot => zrot_x1,
y_rot => zrot_y1,
rotRdy => zrot_RxRdy
);
-------------------------------------
-- Delay para Z
-------------------------------------
Z_del: entity work.delay_reg
generic map(
N => Nxy,
DELAY => Nits +1
)
port map(
clock => clock,
reset => reset,
enable => '1',
A => yrot_x1,
B => yrot_x1_delay
);
-- Registro de salida
out_reg_in <= zrot_RxRdy & zrot_x1 & zrot_y1 & yrot_x1_delay;
pipe_reg_out: entity work.registroNb
generic map(
N => 1 + 3*Nxy
)
port map(
clk => clock,
rst => reset,
ena => '1',
d => out_reg_in,
q => out_reg_out
);
RxRdy <= out_reg_out(1+3*Nxy-1);
x1 <= out_reg_out(1+3*Nxy-1-1 downto 1+3*Nxy-1-Nxy);
y1 <= out_reg_out(1+3*Nxy-1-Nxy-1 downto 1+3*Nxy-1-2*Nxy);
z1 <= out_reg_out(1+3*Nxy-1-2*Nxy-1 downto 0);
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1077.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p01n01i01077ent IS
END c06s05b00x00p01n01i01077ent;
ARCHITECTURE c06s05b00x00p01n01i01077arch OF c06s05b00x00p01n01i01077ent IS
BEGIN
TESTING: PROCESS
variable A : bit_vector (1 to 32);
constant AA : bit_vector (1 to 32) := x"0000ffff";
variable B : bit_vector (32 downto 1);
variable C : bit_vector (15 downto 0);
variable D, DD : bit_vector (0 to 15);
variable E : bit_vector (0 to 47);
variable F : bit_vector (47 downto 0);
alias FF : bit_vector (47 downto 0) is F;
alias FH : bit_vector (0 to 31) is F (47 downto 16);
BEGIN
A := x"0000ffff";
B := x"00ff00ff";
C := x"00ff";
D := x"0f0f";
E := x"000000ffffff";
FF := x"000fff000fff";
assert NOT( ( A(1 to 32) = x"0000ffff") and
( A(1 to 20) = x"0000f") and
( A(9 to 32) = x"00ffff") and
( A(9 to 28) = x"00fff") and
( C(15 downto 0) = x"00ff") and
( C(11 downto 0) = x"0ff") and
( C(15 downto 4) = x"00f") and
( C(11 downto 4) = x"0f") and
( F(47 downto 0) = x"000fff000fff") and
( F(39 downto 0) = x"0fff000fff") and
( F(47 downto 8) = x"000fff000f") and
( F(39 downto 8) = x"0fff000f") and
( F(47 downto 36) = x"000") and
( F(11 downto 0) = x"fff") and
( F(35 downto 20) = x"fff0") and
( FF(47 downto 0) = x"000fff000fff") and
( FF(39 downto 0) = x"0fff000fff") and
( FF(47 downto 8) = x"000fff000f") and
( FF(39 downto 8) = x"0fff000f") and
( FF(47 downto 36) = x"000") and
( FF(11 downto 0) = x"fff") and
( FF(35 downto 20) = x"fff0") and
( FH(0 to 31) = x"000fff00") and
( FH(8 to 31) = x"0fff00") and
( FH(0 to 11) = x"000") and
( FH(12 to 27) = x"fff0") )
report "***PASSED TEST: c06s05b00x00p01n01i01077"
severity NOTE;
assert ( ( A(1 to 32) = x"0000ffff") and
( A(1 to 20) = x"0000f") and
( A(9 to 32) = x"00ffff") and
( A(9 to 28) = x"00fff") and
( C(15 downto 0) = x"00ff") and
( C(11 downto 0) = x"0ff") and
( C(15 downto 4) = x"00f") and
( C(11 downto 4) = x"0f") and
( F(47 downto 0) = x"000fff000fff") and
( F(39 downto 0) = x"0fff000fff") and
( F(47 downto 8) = x"000fff000f") and
( F(39 downto 8) = x"0fff000f") and
( F(47 downto 36) = x"000") and
( F(11 downto 0) = x"fff") and
( F(35 downto 20) = x"fff0") and
( FF(47 downto 0) = x"000fff000fff") and
( FF(39 downto 0) = x"0fff000fff") and
( FF(47 downto 8) = x"000fff000f") and
( FF(39 downto 8) = x"0fff000f") and
( FF(47 downto 36) = x"000") and
( FF(11 downto 0) = x"fff") and
( FF(35 downto 20) = x"fff0") and
( FH(0 to 31) = x"000fff00") and
( FH(8 to 31) = x"0fff00") and
( FH(0 to 11) = x"000") and
( FH(12 to 27) = x"fff0") )
report "***FAILED TEST: c06s05b00x00p01n01i01077 - A slice name denotes a one-dimensional array composed of a sequence of consecutive elements of another one-dimensional array test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p01n01i01077arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1077.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p01n01i01077ent IS
END c06s05b00x00p01n01i01077ent;
ARCHITECTURE c06s05b00x00p01n01i01077arch OF c06s05b00x00p01n01i01077ent IS
BEGIN
TESTING: PROCESS
variable A : bit_vector (1 to 32);
constant AA : bit_vector (1 to 32) := x"0000ffff";
variable B : bit_vector (32 downto 1);
variable C : bit_vector (15 downto 0);
variable D, DD : bit_vector (0 to 15);
variable E : bit_vector (0 to 47);
variable F : bit_vector (47 downto 0);
alias FF : bit_vector (47 downto 0) is F;
alias FH : bit_vector (0 to 31) is F (47 downto 16);
BEGIN
A := x"0000ffff";
B := x"00ff00ff";
C := x"00ff";
D := x"0f0f";
E := x"000000ffffff";
FF := x"000fff000fff";
assert NOT( ( A(1 to 32) = x"0000ffff") and
( A(1 to 20) = x"0000f") and
( A(9 to 32) = x"00ffff") and
( A(9 to 28) = x"00fff") and
( C(15 downto 0) = x"00ff") and
( C(11 downto 0) = x"0ff") and
( C(15 downto 4) = x"00f") and
( C(11 downto 4) = x"0f") and
( F(47 downto 0) = x"000fff000fff") and
( F(39 downto 0) = x"0fff000fff") and
( F(47 downto 8) = x"000fff000f") and
( F(39 downto 8) = x"0fff000f") and
( F(47 downto 36) = x"000") and
( F(11 downto 0) = x"fff") and
( F(35 downto 20) = x"fff0") and
( FF(47 downto 0) = x"000fff000fff") and
( FF(39 downto 0) = x"0fff000fff") and
( FF(47 downto 8) = x"000fff000f") and
( FF(39 downto 8) = x"0fff000f") and
( FF(47 downto 36) = x"000") and
( FF(11 downto 0) = x"fff") and
( FF(35 downto 20) = x"fff0") and
( FH(0 to 31) = x"000fff00") and
( FH(8 to 31) = x"0fff00") and
( FH(0 to 11) = x"000") and
( FH(12 to 27) = x"fff0") )
report "***PASSED TEST: c06s05b00x00p01n01i01077"
severity NOTE;
assert ( ( A(1 to 32) = x"0000ffff") and
( A(1 to 20) = x"0000f") and
( A(9 to 32) = x"00ffff") and
( A(9 to 28) = x"00fff") and
( C(15 downto 0) = x"00ff") and
( C(11 downto 0) = x"0ff") and
( C(15 downto 4) = x"00f") and
( C(11 downto 4) = x"0f") and
( F(47 downto 0) = x"000fff000fff") and
( F(39 downto 0) = x"0fff000fff") and
( F(47 downto 8) = x"000fff000f") and
( F(39 downto 8) = x"0fff000f") and
( F(47 downto 36) = x"000") and
( F(11 downto 0) = x"fff") and
( F(35 downto 20) = x"fff0") and
( FF(47 downto 0) = x"000fff000fff") and
( FF(39 downto 0) = x"0fff000fff") and
( FF(47 downto 8) = x"000fff000f") and
( FF(39 downto 8) = x"0fff000f") and
( FF(47 downto 36) = x"000") and
( FF(11 downto 0) = x"fff") and
( FF(35 downto 20) = x"fff0") and
( FH(0 to 31) = x"000fff00") and
( FH(8 to 31) = x"0fff00") and
( FH(0 to 11) = x"000") and
( FH(12 to 27) = x"fff0") )
report "***FAILED TEST: c06s05b00x00p01n01i01077 - A slice name denotes a one-dimensional array composed of a sequence of consecutive elements of another one-dimensional array test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p01n01i01077arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1077.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p01n01i01077ent IS
END c06s05b00x00p01n01i01077ent;
ARCHITECTURE c06s05b00x00p01n01i01077arch OF c06s05b00x00p01n01i01077ent IS
BEGIN
TESTING: PROCESS
variable A : bit_vector (1 to 32);
constant AA : bit_vector (1 to 32) := x"0000ffff";
variable B : bit_vector (32 downto 1);
variable C : bit_vector (15 downto 0);
variable D, DD : bit_vector (0 to 15);
variable E : bit_vector (0 to 47);
variable F : bit_vector (47 downto 0);
alias FF : bit_vector (47 downto 0) is F;
alias FH : bit_vector (0 to 31) is F (47 downto 16);
BEGIN
A := x"0000ffff";
B := x"00ff00ff";
C := x"00ff";
D := x"0f0f";
E := x"000000ffffff";
FF := x"000fff000fff";
assert NOT( ( A(1 to 32) = x"0000ffff") and
( A(1 to 20) = x"0000f") and
( A(9 to 32) = x"00ffff") and
( A(9 to 28) = x"00fff") and
( C(15 downto 0) = x"00ff") and
( C(11 downto 0) = x"0ff") and
( C(15 downto 4) = x"00f") and
( C(11 downto 4) = x"0f") and
( F(47 downto 0) = x"000fff000fff") and
( F(39 downto 0) = x"0fff000fff") and
( F(47 downto 8) = x"000fff000f") and
( F(39 downto 8) = x"0fff000f") and
( F(47 downto 36) = x"000") and
( F(11 downto 0) = x"fff") and
( F(35 downto 20) = x"fff0") and
( FF(47 downto 0) = x"000fff000fff") and
( FF(39 downto 0) = x"0fff000fff") and
( FF(47 downto 8) = x"000fff000f") and
( FF(39 downto 8) = x"0fff000f") and
( FF(47 downto 36) = x"000") and
( FF(11 downto 0) = x"fff") and
( FF(35 downto 20) = x"fff0") and
( FH(0 to 31) = x"000fff00") and
( FH(8 to 31) = x"0fff00") and
( FH(0 to 11) = x"000") and
( FH(12 to 27) = x"fff0") )
report "***PASSED TEST: c06s05b00x00p01n01i01077"
severity NOTE;
assert ( ( A(1 to 32) = x"0000ffff") and
( A(1 to 20) = x"0000f") and
( A(9 to 32) = x"00ffff") and
( A(9 to 28) = x"00fff") and
( C(15 downto 0) = x"00ff") and
( C(11 downto 0) = x"0ff") and
( C(15 downto 4) = x"00f") and
( C(11 downto 4) = x"0f") and
( F(47 downto 0) = x"000fff000fff") and
( F(39 downto 0) = x"0fff000fff") and
( F(47 downto 8) = x"000fff000f") and
( F(39 downto 8) = x"0fff000f") and
( F(47 downto 36) = x"000") and
( F(11 downto 0) = x"fff") and
( F(35 downto 20) = x"fff0") and
( FF(47 downto 0) = x"000fff000fff") and
( FF(39 downto 0) = x"0fff000fff") and
( FF(47 downto 8) = x"000fff000f") and
( FF(39 downto 8) = x"0fff000f") and
( FF(47 downto 36) = x"000") and
( FF(11 downto 0) = x"fff") and
( FF(35 downto 20) = x"fff0") and
( FH(0 to 31) = x"000fff00") and
( FH(8 to 31) = x"0fff00") and
( FH(0 to 11) = x"000") and
( FH(12 to 27) = x"fff0") )
report "***FAILED TEST: c06s05b00x00p01n01i01077 - A slice name denotes a one-dimensional array composed of a sequence of consecutive elements of another one-dimensional array test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p01n01i01077arch;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: WR_FLASH_PRE_FIFO_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity WR_FLASH_PRE_FIFO_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end WR_FLASH_PRE_FIFO_top;
architecture xilinx of WR_FLASH_PRE_FIFO_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component WR_FLASH_PRE_FIFO is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : WR_FLASH_PRE_FIFO PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity bcd_multiplier is
port (a, b : in std_logic_vector (3 downto 0);
r : out std_logic_vector (7 downto 0));
end entity;
architecture structeral of bcd_multiplier is
component two_bit_multiplier is
port (a, b : in std_logic_vector (1 downto 0);
m : out std_logic_vector (3 downto 0));
end component;
component fulladder is
port(a, b, c_in : in std_logic;
sum, c_out : out std_logic);
end component fulladder;
component halfadder is
port (a, b : in std_logic;
s : out std_logic;
c : out std_logic);
end component;
component binary_to_bcd is
port(
binary: in std_logic_vector(7 downto 0);
bcd: out std_logic_vector(7 downto 0)
);
end component;
signal tmp : std_logic_vector (27 downto 0);
signal v : std_logic_vector (7 downto 0);
begin
V(0) <= tmp(0);
V(1) <= tmp(1);
m0: two_bit_multiplier port map (A(1 downto 0), B(1 downto 0), tmp(3 downto 0));
m1: two_bit_multiplier port map (A(3 downto 2), B(1 downto 0), tmp(7 downto 4));
m2: two_bit_multiplier port map (A(1 downto 0), B(3 downto 2), tmp(11 downto 8));
m3: two_bit_multiplier port map (A(3 downto 2), B(3 downto 2), tmp(15 downto 12));
F0: fulladder port map(tmp(2), tmp(4), tmp(8), V(2), tmp(16));
F1: fulladder port map(tmp(3), tmp(5), tmp(9), tmp(17), tmp(18));
F2: fulladder port map(tmp(18), tmp(6), tmp(10), tmp(19), tmp(20));
F3: fulladder port map(tmp(21), tmp(19), tmp(12), V(4), tmp(22));
F4: fulladder port map(tmp(20), tmp(7), tmp(11), tmp(23), tmp(24));
F5: fulladder port map(tmp(24), tmp(26), tmp(14), V(6), tmp(25));
F6: fulladder port map(tmp(22), tmp(23), tmp(13), V(5), tmp(26));
H0: halfadder port map(tmp(16), tmp(17), V(3), tmp(21));
H1: halfadder port map(tmp(25), tmp(15), V(7), tmp(27));
btb: binary_to_bcd port map(v, r);
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Rvwp5EPfpEhcrcRNmIO41E0vMlvKlP2i4Ydhk7ZEgYcfx0HUz4j4V7X3hr5VndDdL2qgRtMGOgqT
kAaEdIMhDw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
S41SWhcMH8PO0wxqQ0aWU10EBGFUi8nttyLAB0SHa72ecVX51QM64hRqZafFf0OoUUdmr6y7BcMY
QMwQh4G47B9tp5kJsr7GDZRIq8oAuDpMgkkMjshLOC4k4/jKbAyjJpAF7RVI74pgJN7T8MWm1Eni
s762QsGYMDFjcaS1qgo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Uw4HZBkusWhYSdXu/RiLDvboWYhdEi3DKfZivigGCS58Yn97RScPQG0QGfBM4yfpf2v8myp+yXQp
fj3aaXso7sMC1HYLM1yrf3N4ktJcGIibSPVNYynsoKaXBqO/CSx95zrLNxR1T5TqVkX/j9h3MGaB
LgRu6A1iieK8Bh2HOgPXFpNa77Vv8hhhqlmd6/IreYli9qNwl8gaTpmS4r6y36u8lgnxc5QPCRQJ
3uSdRqDvzfremIDDJYnKh1siILHHLzBcyrnoysZFUaImJe7duPoB28Va7Yqjb0F+dGakV/K+isPN
jqGZUZSq2qF5fkdQDnuqjkAMEulbTgRqlETlxw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CwrRQyUW9iteXMfNnymRJCWEr7Sv7ED3RaslHuPJ1s8DkvyS13DM+Reok4hMDnLMXMZYIm0s/fLA
Fr0j/N1ZAwAcWONLwnecKGwxak4PGibno8ZNKaPMzFs4eIZwLQ4m5nOM11nkttdA63BUB6yZNbsX
0pptcVlglQFpSqsbqVc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Dv/lZbGMVtZnXJoLxkPg18fYDB7aJxGa7eeQ/fXe2psQ8cAUTSbk8XoAMxEoa3za/QEErpwdQ5+k
1Y9NNaADsKLnDZixB4YasEIeOB/EdRYCTQ4QVoZFRPFF+sWf7AOW6w30O/EQ4r37cC1O/+9qwE0i
UETW7QJJ/P6LBHeHfQJnRZavefS0BI/hl0zMTPAcpWubXHQhGst+XU2AmqcJwc13tduwHORWU0Ww
nOKVv/Af07yOF2yZA/JPz5Vqrh+FqAXFY3ehZki8pro8W0njKCLdslGXIzNznFabjzwdUyVJv7B+
es9S8EpW3JLI+au6UC5BYN0SYFsctsUMnoi/Cw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13248)
`protect data_block
dHdMbBVooleduvTd8NaJy3iuPD8njG3bCR7Lbu/k/TxVV07H5BZOkeR43efgCUM5tPS/LQ+bjo6D
ZXuKWxRQGsiuBvqX31clkgAEzuEkpcLapDK1UG98PwdYyZlKKt7E7AVesC7LJbFckOCp5jWPvDqt
n5/9PenFby/a9hAw4A+f6gOvl7qHWDy3NYBrCERqe33AxRtQglSi/oJqzv1888XdlgmfRhJF5gpY
U2N9x/UNcUPy0QxMu0RbnXcWIb8H46vuljkRJUGpOt4D+rE1xCuGHHy0ivmjDCvHy137VI8Z9p2w
P1ZYkFRoedhp5gKbYejRi1YLFA5ZjfBcHIZOfZDo8j8lyVeJf+CtYOC3jT2cCBLiXEpxjO8qw5w5
v6tZl23PT/J8XbbqD+o75WJkDfQ0uG6oy/DbOUjMBziV/TEIIRUpopEcD5YljtD2hvSZ0fpj9500
HheEyiS9z//uo+ovwJ0TYLIZVVT965LOBh3TZ89RybgTVgRL2Ei9ww+G+TMUvToZxzIr8JLE0dOO
pu3JMjhTsBmm393MTb9qKq+Lr1xkQEp9mWwhsp7eyiiT2hmHL3t22nTMk6gn9Wqiv3W++XtLp2VP
aPEHFxA6yXOuZDLkHGzLvBFpKuQZ31zKJE5QRib/UDXyvwy70zxCx9lgoJM/A7sUmBWh1dKvnpE5
MI+u1z6crclzTyv91ZUoPFCjMCAkpQttsH04pwlYRAcpqxG2LHEWfDWWMAJvVqhHuVq+1Olqr0R3
l8RllxP4qvCW0Rgt1MJXRzGsE45KRRgmDTU00L+yARFL3nq+982vqTENFBfuugOqrM/u8tqcJVJ7
LJ6Xw+U5LB3Q3QhbwRglDfZzIt68BjbXRcpN6L1LHGgl9CsDdApyI+bzi0E5ok6wCUOGyX5gWe9D
OOYpRUtcbBFOAquc+naENH4+CsAOV+GmPQEusYRYcUkaT0iydZMJ+TjqKAm+Lc4QpvAA0y40lRuq
7rwToJTdIM4Qqa0ZXGom28Clsic0xDMRtx4CMfPZkfXPfbh9deCJ8ewtIWSTku5rxChcU+zuoVfr
9g7YNl1NARRLmjVK9UbZZT93saq+rulgAyyDTHV7q3qLCmuJnvg7d8X1IUH3pBJUSv9Hmf/0xT/l
+A34AHsDeGpLLkGg7qL2aURTngHX6ArCz1BEW6Qj0CWJZ6JbWu0SsvSRKIHDehcI0e+jAI/EQT1d
dKMkmqwtYk7UOtz2QveZQMFVIzVa4t98X4pUNFKHCxE9qA1RgNm97V826NPQhASB9S28FVnA79JV
8QPn0Jhst+yCtmbG3bkQT3OksE2t40LnL31oZraIyREz/qOX6fXkZXunTyBqRHHwuj4kaUUvdpxy
9NUCvTgxqilsegI/2bAPGtrxhmbH7gGhwBo5zgxNhWa75ElqGC+NO1kZbvUDnX1b78XjokUOP2Is
MQVaDFoN+I/9cb7IBGhG+SzSQFvxF+NSS8YwR3vHimqtNC8likIq5OfvRr1PW30/slTgCDSodPkN
gyqGMHqWXMoI5IOw7XALGxQ1Dt5L9ADcjuC4RrKYq2bL5Jq/4/ee5iXMj821nHguS5p5tawQdM0q
FjwCrZBqQS3Up67CEhvHtgL15eO5Mnxhr/59IJTPo4Uryf2r6M6GFaqsXaFWwt/6tcMTl3PHafIs
TsUIYM5OTpF//PInOA109JJedWq0zrDN6k0Mu+Avnv10FtWYdL5/BO+7RLfotK/HvsC2U4hj3Kiy
h98WiMbhC/U2ZN3Cee+2C1YXYia0QwjsSPSYH0UpN8XnhFFyATX6RJGiPu9zQu3T24ql9KCuNXK+
KV6evXH+MDppICWOJrMvxQCU/qsbKNno8sVMUrx1Qo5IkL2sbk5zt39e4pccM7VlJjrj45SSLoUl
LcBiywqqUNZ0r9+YCIN5oA7m1vpfZHFECcQGpgDzZJaBi7TON6P2zikbkGF9gNlL4sxLn+nJ2lNs
l7pds62XXFQPSn9LOXWxXCciwcr+HJ5g3kk839MxM/+7hjHoPROls1AJoZ6EbeaypKBvh5Rq0WBH
+oS3iI2KHhK6WtpfbytljI8JzYnHDYZrFXw9tLwv72peGmhUChiYklT5qKh605cntpEGZvVLUOKI
7h5Obnmqtjm6djiAgzaEDa7YNBBhLXk7cZPhjB4y1c6I+17+xG+IphOqNBjgaCtOcOekW0OhrvBm
qkkJLsICY9fQUkkPiRa9mFpJRzl2s5W0rdWr/Uh/8+jKKMGfldKsyHuwmbYXL2RD0CjjJ70SgPyq
+LeKet1VQ7N3YnVijEiCYFUWbH76ARCheDeYDWLuMe/ySbaknXqTlXXzHQYhhhLeRFIDDlwCPd6O
BNIulCJHMJ02KGwqm3yCskhhc9bmDOJBd+K56pfe07o6sznx3geu+9cfhgGN4zg5cP1BFfeA4Mio
Ri3SoF3IeV+2vkF58trS4Mt/QjZ3WAA4yD6HgekZo1GtH/Ahue8D2FY5WTwQ4j03RwAR+ox7DUN0
7DPK6xcQyGeXEJH4kjJbTWZ+9N+OdFdei51Q0typayG/eRYVP5hRNlQzffOIpviZhNWfQWyiNvM9
0tepgFEH+B/dKylIlXJGDMcm5y8CtWLexmEJ5sIxxTMFWPVyhQ53zN0QnwUgZZgw6T9/AMziYGUB
TqZPUptrBxUV03epEKgy+FUONAcSROhJLm5fMX4O4Se1uRYKNCQTVD9N68G6pBRkAF4JVd3C6QAx
cEpBZe30veCvJx644CMkjFwa6P9S48xhMXn3Ei632HIWV7MOhGbLBnGerQ/UQDxHffV4HVr1yrDM
2lUrgxNmhXYiJV6KgDoPpIYdX54QwHG2kZO/MMRrFVtggaZNwcW7KaykuX0ZvAKKQH/5hwMH5hSL
qXeefvyqri+u3S/nshlCtJy/D7lMAF4ctFozWWHwi6xC1LwTS3Z8MUET3Kq7GdP8/7iRoefmfYDp
G5X63vuVVYHlk+l6Oo4qDYn7oH0TJFGEPPcng1QwXf2X0BQXL2Yd63h3ePMR8hy6qDgX7UnsXsSZ
MtgJqfuYsP5bL/V+XwnnMUaGiBqhBepDFXfLxnKsXPMyH4gfMCa7gRKL54Mxft4CJr9oMYgH0Qyj
PztttFaz6XGtTMuwdC4cEr3hPordiPn0hpCF4MuZ33/yw4UjIbM7h9xh5Q15Mq9EIhoiP0btBVDo
8DCxnMFYSyGZ2+O+0PXLRHFqIAmJv46s9xSnrqu65tWCocgawEYBo7T0WMREIlb165qntlvx4mAK
B7mIqd+IkMPpPzARZV2wnJFqwPCF6C7YHu2xM1sKb4AIHrGSUL+dcZYFCtpUYgylxVcpbwhOfCjh
R5I/bwHehxbKn1NL+2bdALhL3aVY0ZiA+lO94G/qK4MYADaU6jRy5PngbK0HyjU3xA5khq/volXg
GqzMqKPPB0nctxIZKK+By4LTXq9b8aPKUAn+OIxgGsXEOaTRp0U4fUBLRdzgVAyu5HH1dB00EzyW
jf5IyNhOKf5yXRvQzvwTq85FvuunrMpxJiQ9SXYWwvSccQYkHiHRTwKW0ZTSdrzAHuFAAkBuQ7DF
cDKAZYpfDT2/ydRJwjBk/Edc8DmYFY+CrXrh3m9DyulqWNDnMxI2n7pA3W0BU/sxbbDOkgL+iiSv
lR1V3IDMJth+VqA0DN9BS1uhq5OHoXaokv5rDey+o30DFd/WIy1jVi0Ddqm2ZR5++FmfiPFx43jF
GuTDynMlqUxyvCG8+geKw752nMNsP4rwtJBdtfAS4+UkPbZokxlU8Jdnz3pJ00hXXLcb490Q033R
8vxYQfjwHcmMigWwHCJp5whgcMZQggOjFraX86c7E81wfqCRhU0ufjRcCpogq1MZaVideg5LT5kc
PsM7DbKdFzH/VhuVgYEcz2Wypc79lFFgp8Gia3bewNxuaXZkVXuFhmgqc/6r4j9o+HLJ2Y/7nWaE
Zydtpawmzd1hEgXoijl3PeKBBXW4Mg83zgJQXv8bt17gYHq6jGIxNLz6/zyfGguRhUYvO9O1wOHo
kB9olYpMZr76uCHPE1YcNC2qy9WKzyHyFsF00Nq/T2UYC3U8Dnf6eU40Pk8MVqg1Nxx9yJdjWDgV
9rcebgkt+FcptNc72N2pweTRauJkgEjBx6RvP7QRzVCREXusrmVM4HRBxE9fQnuaqGt1IukJHCRM
Db2MuUfPExvuoBaXo/SOoGh8zSEgzLNCQqgXLt8JA7t76CE7WF9i74U2e8w6QWcA68cQ82Rtz7I2
7tBaWU655Kn/THMVvPnzfMvohRh8ni+XRXzP+736oDQfjzCMfUzZYcBaxYVRnN8PcnQMtzdrE0LY
29wYr04RGCYkJVJWMi2tisADkarLtTzGBMcPDFyD7xBmx1H/layqXNtXiYQjKw3Z9bHnuykXODdd
mAN4naf8fWCuGHTRbUPgCk/2h6HGfvB9j5ZwV2yud/gt9VMJ2rCNi3d2YQ2DzM8phehCqRo+IwOi
GovgYDKbB1sM3BBRJKHoelf0y1Kumj9pd/ySH0QOdAzt8oCKqofFSF5tpXkObtJFqPDBF8OaXgr/
tZszZeG/MpRKSJEGSMNxCA946T4p0dtnC9sWCkesukm+7Ov73zw4ZauznhqTxyj88zr3DCkXzJLF
fXDcZ7ewjYWpglN4t43BAG/PUmKJBnbb3qYqahH0p9RudsBrswjrD2T63ylcnzPMg1ZONyjXvUqy
AN8aO66lMmSR4soTUacRt85MvluQCSi6CkEKq2fbnmnaHkJC4+h8H2MQ+/k1sb12x0G5kHNiuTcs
K4d2Fy8zWeDkCSOJjlsuWXhyAWPRI4VhufIeJj/XqlWY0/cEUgKIfIb7UdWQXrz3kluSkWXdUKDa
Pu9jAEHscnSIibY+pA6mHY9TsSoxOkb5Y6T6e331+m3ftH842dZedagtfUDmTMWEP+9v84suRYeq
jFleAcnGb71yiCtvd4E+Njd/sIRVQNVgfRUS3+l1bezJBuiryAph4D0HEZSuej7/WxDirCGQ8Jsa
ZmWiv+2Ulc1NQD4i2j2E47KCQLeHdSHP3Zdnr0E/dJvRIFsA8MlSSJEeuw0H2jQ1MLWfyIiTFwF4
PPh29zI+8CggNrxOhrjeXXEQvniK8qh7lU0buUR7p4hJUFaMjecy+euf/Hp6rlSLUf+n1WJJTSHz
+wRT+RH6ce3l+FBdUOKimBcAYBLoT0zQJFqNjBbTpbEj4q/TQirICmFig5hF7exCIYJmKCAoEznX
0j2+MMhPMH7yWHwqTTb3fr7EtrkGW6FXwCBFcHBQE8NEgajJ5Q50/oGuP5icbS82bf/dBRuBuM4m
+rLF7UcpMVRidFRoC74T6BfQhE1DprcnwWh2Jhg8Nubqwrl2kWVTWr/9zP5++LeptemrmPStVuKz
2cjQ2I/F0OSjUzkF9NyrhwlxsJdrclzDi+BtvA9mgz4pTJI4WgB/h8Cs0SaQCMoFcTj0EOQrgnFL
3cOxbRoqAZlb2YG1Tll1CHzPDE8S/HypnOIiLVeo7FIvjxc+ly6eKnCEjHBQOWjxjB7KUI2wslJc
UZ8KzgD0y2eTRYlLGSyLQF0qwCBwhqkIQLqURKY0pxbWHlUFHn4JPhPeNP9wNH2dMC6wezonoSQ8
FZRzeBg/dG7wQDEr/gVIedG845yeZrBHHvfY2feSeatsAvaGlj8D1lpe5fj4HQtVH/E3QFhtq023
nm8rM4WFXdNvcUhly9ZPPRU0TdQJKmLbavPGcjbYQ7ggyvB3/z2B1R8s+JSg9TMxzBlxNBjvKrEY
AsRCG8cO/UroFOKejr7LRBIg1Jt4/wRaZBbtCJRsFnb9I6/q95x1bL6S/VCTpwkiPpzyCFvQ1p2h
xmSeNp4VDxM3wd+EdYtZh0KqdqVIhsm+8g25IgaxmfshnZD9dg1NPGr2JKwgV7538dKjtgzNYIXu
OGj3Kb93XEszpiZQpPF4GNKZ9XJgWZFzkRwg6NpM4cRPWUGtRZVyIykgctVqEC5ZWe8gft7b53ky
UA4T0H50D60FvRu7R84aMrwRhF5sMDuVWCoixPEwnu4QpyRe88Ot7gX1XRE1kB5TilvJbeM7UGOo
KbpzgDFstKIpHR5KnuldH9KPpRMy2KC4+bpcF8cLXIiRar4FEU/xLv/PXcZIkj/1r9taushJsvt5
NAXhA2iKy1NuH+rLvmlEMBTuS0muOFFqqOEWXVWee2XU5wEpIPvs22RGGUl43BtKk/D7gb3EK0iD
OEkCwegz4emWNJUO97t8XMaQRzkgCwP+22M7B4v6zZmcKlbGIJE2dpDGZkPe0gPa6wptiKvKrXHV
FdtpEcGI4xqsEa0NgzxPtqotTo3OcIJD1pfzVIJXZl3+zQzQVP1f7qMPEkLjV3p39vtcifFh+2Ap
FNoLh6dT8QbIENXetskABEcK4gxi4oLlP2iEuLYM/uyZLcENCfE5/qRgvvS0nNWPI3dW083Vgu0o
l79fV6G/rzgPQvj/EHk/ZYALxe4Q7Mj0nQdUov3dF2GNwtELw0V9CFkRqa4YvtxE86Lak8jpmx6v
ffoWqm4oziqLZjHtzhrGFH7EBeNDF+vpEbrjzQQXCli6iZS3XesXF7O66T5bH5vOBe9Ge3UogHeV
eOYENdsDgqwLrtYeYoMI7uluJbsf89pzWJjCEDDS6fzL6VguK6hTU/Gz6asQDb2e9FNS9rYWlCNU
9R3LV79Lx/kAxCvMrejryDdKtG3XxxLF05S6iC9vJTM1lvChhRnEXG3LPqSAeiQy+KyxKzC7EzXj
BzhAXgKiZLWx8RYROTYP7T2jznihUtJVwf1RHbmjkDaFmEDSSXN02Qfj9LgFkBY1NKqK/H5K+nNc
KQPzudQpdgQQ9AIDFrDRagxKhqeBU2/lCh7J+hCAQQ3fLkOM0Dxo3Q0bzNGAifOov6Kv6WrzKsud
XPQJLAUIqxJ9/1Y2jrIV/bXYwWaAwPdkkdfUU6AoR7Lvszp5cmcjPObVy18HY2MrtjnYbgTXUDUz
SkIaReVIejLsbbdRgyDF2dTOP9Y2l4zk5wBaxjO6G0h/odKwakgX3RNDsAH0s4DKZa4oTKotSNs1
VPSAFMuaTd70kunHfPElKIQfXNKRKrZMnSuNJ8Uat1PCKrtRvdzqoIYPuYao88oPaAKpznnyDfcM
NxgDFCR+G+BmOPrHaRwFMw4/FCtTjvFS42p7XmL8e1G7K0hYXqxuPje4Z7MUOSFKzVYSJXqIUUSW
YQQdZfovLXA4rT5rD/8sBBDQeLJCiPMGZuXEWDaZGJlZwJodBJGtSZkJu+RJIstVhgUOLNi8OZsq
DNeMqb+QfamJKddekRG+0JpdtC+VG1edI4Dv35ztBz4cZk5uYpKaINp0yFql0dpeKQLR1Sd1z7gJ
/wIssQ9xCCY8CgGH2iupL0vPZkb9fyZq1EDc9X67QNSPj+99wcHnAOXU4/Maffwo0AJMstbUSYs0
6tYDKtZ4dKBMcAan/QZdS4N91B4HKAJ2GdGMXWGWPVDlgQsJBHDNwGXiuVWr6PElvDO2PZkPtFQI
e9tovwiXZiujwK463msn4/qrsdPqGXWco/KXcU0i7WWk9lKT+SG+Sq9DZAruXaheWzbHCENtj3wV
YnlIq+uJL+s2nRJcqqKRqiO2/G0SpC0B8enCpybAhDJhKhBYshmBPs4rQwg3zEmjmliLuwYumpN8
drwYtLC0Mh5brRjOi2EyNJJv8qlbW1tqcby+2qbrJHE4EcBq3MtffHB0LlAIakSD7d5YdpAGoLnj
4uZ+S5PxCDWtAh6UpFgf8QWoSWdMJEBrXUCAr9b90R1SkjkgfV0RURQAYM/8ucqXv4fTaGkcJ+Bj
i/IBYgjY+mrJaZ1XDM/XjmeTtlc7tauWhF/b/BKXTlfKkBU7APwWr5DLRAYZaXhqdzoMMUb+Dag1
0sd/kiqCgUGTXizuC3F8NV3AuclwGAsDclGonWIkCov/5dniu5OmIfACRopK5yw3/juNKEgVz4hV
NMKuea81apikPm+ClBYasMoJ9+BsMTxHHomrNBRfNA6q/yM/caZaUIReVbEDnye/fiLZygmkrnDZ
TxkM8F5TjAKVi7cwLl20qIykSAo/NotH87kFB2h/v824EGDUnPhA43oX7Grxglsij8A+Q+VWBGWF
ryuRvJ1x2CkhxGjPQa1U07X0YD9M4Skx4JrxTcfpzbkkoiWvGHoaENjUvFEIo/69/G9w3ogpyWoa
4nIC5HcvKFju0pr1XinRcjRlfH5DTwNEmiM90igVlE+4hErbNe189fBYY55n7Z3Cq/G9+NGirHXz
RJtsNncVd/byEnlBxnNB+0V4wsg/ZmB4LhQZTQTKh/SgZGfT+m8olU/hQup/uAgVBCcu2YYX+aG2
ubPMSaWbz8/rRQuTjAmqPnwU35xVQNpoXhn7I6MssksA0tSIjCJdEuFi3+V6c2FqogcVIsXY/P9I
rSmmAmc+xNQUn9ObDv9YlLIF7v63HIqfm7PGyMhnCYG6vhFp+qSdr5cmvoFmBhw9acmaVKah02sC
EzeS6CRzyEkqY+nJC2a7KJc4mVSK//+r75Dtg93bLFS9WRV8nCcl6Tjuie7z1OBsjyP2BsA/kFqP
LFrLUKWO+m+Vg1orvnLBFdN9WtvgTySc3hRi8ddMqChJOcoazUK1RjPHnroa0hEC4imoJuxh2KJB
dx1iV9v5rMo/BQgPAfR6B3FwRPybtHQBUBZk1ev86SPlvRf1PpcT8bh9htlgAZm3pJBP/tQbwDgj
nViir5KhUdAiR282Ko7bpzUmT4uuK3nsfHxvXzLJGK38Z2foVtF5hIIPArOtgFYFmnmQjeQz4JBy
G2DuHcapaEInFWo5uymXi80fpYfEJHqDomKDPHWmqfHrnQgBBeVOyCkCvNO6N9CyPel8mtNcufai
FW+/dIacfcd8xoL3qQmpy4Fk0tKWuHWrGWPXKCeqwJmiSs3vvDsHdQX2tPWwHafoIeTjHGUsV8bg
mPQJz1zNn9iuKqa+ioW5rQbAccEqu61d7VFAr3dTaC9r8yOTp3kAYLeuqJ3fs740hS5VRtYhEMke
qYYPDl1lauCAClHKi4lRzcW2ibpIiL0w0IWIxzcuWYIW6ehGRAn3Sa9/I9wEb0Jm5wSnMsnpWKV7
MAqi0oPGQcbdJjuItocNaKn5AYOv5nAToqtx1W5PeJFFzfxaPzNBXf2ae27sF87Mdv1gmp5Wdl5j
QbHwnQ4erRs76Df+YbJ4UYi8eqdNmZ73uWQ5CsubCC1jD9e05G3oNSN0sVHiSHXkUFLgnOiJPgwU
hjUOj15QWID0crYWaDcqxFMdYcZc8FfP0hhNIqdIYywzc2LRqslZ/wdjJqTYi/C8iwZArkfKVr5F
vEMcaKF6YG3ErlQo/hQ99Hy6AE0FaWfFNIbuVCtBeaVOFcviJVSe7XyBFKgO7G+zO/QVfyikBaMU
aWZqVIPYbz+ZErHBeCQng1yMOBlLspZ5Cl6obgq5kwxzN6Jw6Ck/1rrfv94CQa8dU73tEXTPZEFs
st8tFQcA89ul0KChznqGYSV3Dpc2VJtK/r/GCvAcC3wILOP6MxJ48BJMj6RYiiA89Yojr1eJJ6tl
IAQZE2v6SgYGfMZglYJqvsfhkoCdRENbLHH1k//LJep9sdUghu06R8e2kZ5jPCbkgM32Do+okCug
KRMY57mK3iWq6t84bNWZzXfhIEgdbs1lipSzK3CmGIMY6GaKmpxvj1d1gc0FzzrKIsYjKqtNRZsM
MMAYeV6GpoGY8mr4suuvJEzGOPkpXOXgnIU3sAxgmLFOKiRgrL9TuNdKzNg7u4SWZus+swX7HNwV
pDddukd8r6Ad920q2UQNPJwSnnQume6d9giPdRpBu6L8AM8SiNURNKaMFI3YPPb4OmaI9sCmg/o8
CuAJ4c3rXNgk44ZcbBhNIM0sGy2aR8iNsU2V99nwFF/TamsTXACL/P6y5DCEk4dq6NHhIlKgvsD4
afUNoL5K6siK7TwvsLS38b2mpeYumoXSe3b7lPxKBWs/jDlR7oY3Qf7sc8SolztymT/SXP3f71Mr
aAmXkmpPs/oyHndCAE8JvgFmZ5YeXofk+1eQCVjy9tSPg/4eDzjYsTluzsoB7VWYqP0Ly8gE9TTh
BuhW4Icso8WXNzU7qihvFKksXrtMeZjonBIkDQh/nMbFG82vDzWCqQUhl8lNCSipkA8vJBFf4qj7
utJq8udvtBNwxfsq+agB//exDnmA9FdGNRVEZLNuMB7Tm2qPIEdmZIPkd/yQu0R5H0Ljq2tRy3np
lQptXXKlrpdU83OLi5P59yvH9LATWAEeQWIvJyo6NOj/ncIaeZr5ViRAeQuZTpcKBxAh+axNLsIf
v38QQSchb0a1dgMURMkNiH5WYSlGIrQz4Bo6sUxHSOBDqhkWxqTmOLVj+8faP78rjFsa4gaND4LU
VnBw4bxECKs5xKZM4XJlyLoPgnu8RDbFYfenZ6K1SMNnClYA1fZVGRMPBCVEdT3df1xqILzrUyCP
BOfC0NeIfi395u1/GTowc9FaPJuXeRX3o2tRcxTXnIOx1HeA6U1J9xLTsUcrP7Fa1GbNOAUICE8E
6zO7HRtn92Vs6tqk1+2b/oNf/Ndq48P6gAMO/U/ES7gfaVGfVOXb8XuDdjy2iKWj0VDpmz1vy09O
BtxxxEIVWyGeU7RrOjinP4171wdr/JlY9QqPvd/EiW+4Tr8GH8ksERHsGqnF2tmVQSnpccMBidUp
m2dM2+bzw5w7YMc0pPnbN2VQ+xpyEMz4ESGxVrq8+yf5PTIHkt0ZFDZ7DW1o4xGUB1gZ5+qUkFIV
lPPEQ55oLtOc58uXQTkI0cRnZkfOBfBP3KbEJXsTIkUuOI+3dm0/0sCLPwz5VOXZKkxVmcz56AUp
eCPbD7jO5LSz3GbYl3OzL5VW1vrjMSmnzmIDWuSQoorpL94mdmPYVpu1X/XhtR71GwoLNZpTTqEO
F4jZTC8Qzgw8OWvLhAlBhZnCGNuLDgXZs4JBOC22xQ2tc/S4aVc1o+hnyl9DXI9Ee428yB+eFvA0
RMtLoLJ0UlqasX49jvp2ovpg+5D3gI4lhxZuOsQwMWMntJb4BJRcWR3D/NP9WlHJuPZXGDPH1zTA
Y45emzl3aMn/pRPX/XBB6oQZT52FatVx/KZWqWJHjm32DJ5GFAErHf7gYV/8cN/IgXSRmSGbgA4C
iNUdgtdLBSDjVk9LsWrR+taKVMj9dFUhssCDob1zCDo3KcKNQawTEZZjkIQW9EZabILuJk9V6mKO
Yczb4aEKPT57x4V9uOZ/M/fwbaexJrana1YT/mFOF8Jo4NgQ4D2/SqwPMl5Dhfekp1Ql+M7ceTTm
ThRQlqfyhrbakMgZJzL5ehxf3R0PawdBAw570Zw1qLv+XXN+GHnXgout4KoCdGAIMBlwRGksbdpl
aKMD4wPnfRKpVZcLgDDjjS7sdZZykBcA5LU8dkhoixuttr11dXSn6FwPBx+qDdwLBdF7WQFa+Izf
mMFsIK7CsB1eJiGOMYCwsrmZZeuR9x9mKnKpI74OxrQ2rDbQgEUN3CLMAgcymptzJ17O5FnqTDnC
03xyyCBlwCK/QMsBkwRbH9M0C8lHjrwK5mtSYrtnI3H/GUJX6mAn+EJvc2JvaVUzZb2UttKQqCEA
kO9WfLfCe0MM1XOiCGRghy0e6W92GT2TqdytUxkasIadJd14p5QWw1T28wVqrkhgNxU+BdqM91ws
FEzjZbZLotuDUUH5FKCpXgP0huOw2KEA2PxUgsV8m+I0clnZ5Vy0RtwImR898uF2cm9RpYk9dbi/
IdWsvhvGzGaVxQ14HrRtzI2TYMppTcPfG9v6PiNDBUuRITTVZXvT9AWnsIH2/0j8/MIfv1kVU7qA
g5DKRSY32hLgXdaB+hcW4c3aHOZBE/7VT9YzjAmMcG3aeO+jqNs7wvpfSRl5BQDZxkgTL87pWWNC
SB4mhOFgKbOHJ0Z+CSI+Ml5drrQTmgNSxRJrwsrpxxu/XKUBVPhxVcIIbaXxlisC3U2K7ZQZk+as
xBhV3hH2EurE1rH/25OVb+J1H+A9FGJwcViCGFZpgRNzl1jhm2wJHnxOn1Xk2WJBJh4Zmfg7G6Rb
q9idPst82k1qBZeN8NtW0N2eflk8vRe8ZZFoS/QLmowRFV0L6lujHY5B1lbc90eFum5sGA34nnAP
oANvWAjlKMbF8/fjYMG1QyYsu/3E8m6u9hP8A4h76NZ4a2JL+8Tei6RGvbvxJ2U9RklM16YVJx4B
YgoiN94OZitB4pLn1ZjbriD2t87pJzYGKMmiC8G3sKqSRrnhqVqgnX4UPbAakrmTb1fc2qI7wG1P
ROqQas0fE6s+PooRrxELyPWwDt+AHgvYdF3elNMa764AxppGj/4Aj/xz+x8P0WU4QHNk2+F1pdHm
NgLzyDY+TdMHBKiy9b4+KWTeP7c870IZdZhFD3/ureJo+ANF8rV+YgmkB/R3LEZRE0BqqovCeylY
fGXVmG6PeboHzywKa8cVOBDVi1QuJ+7cqhEYjEqfOhIp049QXql0q3NG9/I9g8QiIxG5SfFXG7U8
RKiyH7snZXdt1KCC89ZbdHqOGVZsLy9JVcoWY6NxeGGLYqn+ykDs8WgxgdPGVlv2EZKaDQoAQjau
Ko0pek/fytxtv36qKWVIvS7Kld9mU0Iw1P5ftFvOM+jrF8xg21RGpJ6+esC9Ia9xF0P6uVi2ZFS4
I2XgtKfeJmYPwMeUXzLBLJ/tvKG6M4Jv4K14iv0kVu67md0VZNMpmITGAti3GKfMjdEU6JEHTf4s
0zw1uf5Y000HaTLyIR4PnXn+1wt+tbeNqJ0Vxie2chhEguk4wK5nly0D5SnlKpMSIdwtrO15sBLu
E2KH1X0foApg7+fpgHxKb1fjjlyu3WmdknxHUzgG5urlYa8T0oJwgfRvPjPUe+sjG655Sp58Z8/n
h2yu5RDmfUOVtXBdYm8Qcbx7xH3CSAIPiVX4FlSM6FICdc0zk3I3QYQI1txhsUDLlB4ybQqCketc
9PV4Ji0idQ3xXCYAuxZF0PM5EWcYFbuq3OrSc01B7/Phd2BQ9OgY5qhjWYc5AIvE9HSsTZmR94vy
Mr6xIoTMRr3DNdWx0Qw0QDE7rDO0rcHD+0UF6XAaZ4UC6AItUMGFT6dWrNvFRfbm8AUxBTwJ3KGU
QSZzj2xARm/MiE2b8eg4i71bJ+W5mbCZfV6MyyvuVPhBsd0YKWhgICiqq+YrHOHM6ZnmvYFnnZZm
brT3iEzoaDehmZpXuONwEmf/G7jpq32BFKefgAmhMYR52/PGEcEOVE3KfVeKBiBnk4eDnTHiiHU1
rcqJuGq19yHK1ssPv4Ncxl0Bj2cNvW9eF+4Xl0vnKR9wycpqmjaZpeQ7ShlSfty1DcDk7HPWaWv6
089s9BGcRgn6u8kQnw2n/4Bu5iIvAktxXyslYqAsiUtfGJZVRo3fw+jdsw6wHMtTB1+Oqz7kfEJV
ZXGeD1EtpPZWECf1iwHPRqRkS2qYmreBTgx8pYomfWRZFqX6IQPEkO1kOxMvA2K1Ejz9O9Fik8gx
HlOstKnAelD2tCUHnFDf0yzew8R1NUIO7+dPczgWIWLpeQJmnXyosA7LrlsixnIX/TwHAswLOsXt
DvfeeQL9ARm4dsdqnOGHQsFy9dRxF8GAccNMKzGrs/FV1bJfOxObbjbriw0t8XzmWMEi/5BW9OTO
4yGZsV5n4F2M3BoM5SIQBAGUe1LeYPYFrr43e8xRFB0AerMnqou5ikwK+N6soClXctk2Z5U8nBkx
3DhVi1G6AHs+KAvWSGiQFs+7yYMa2mASh07ZPLUD3Tiu5o8N/ta2r5czpJ9YPSAhW/4UDXau0BHF
Qdjp3MEcbl7D6dFdvAJOXuXnmqu7ze761Qc6JLe9PgmuH8Qyntfhzqdb40W1XqBqdMoT7U0ja2Wa
TvaPFTH8qquaLCW22cK5oSvY2sI2pzEqbhgpAsPiDEKQwh7OjRSrFMegCdNeL4NR7BFZdCQtyp0y
xeqKaQn359gTfo2ZvbcE/aB7iEPl2w0v3gZQc9jH/yuHXA/7CcQ8U6kr3c/fZkb5ychHRGD+WtOq
gTIQAtF3KzB8wMC3O6W9rQo/IKMfBxOAXp2Z8j6KjpbIvJiGi+PMKXzziG4lZzPxLHMmr86paLWG
kBDOg0gRj1iUfhA6/+5MkRhWR3HlkPW0e4zl7R0qIVfb6oBDbvKKA0sfnkJNgrbm3DigFZYMKaUU
7rmFUwoGrugl7kwh9sSJZbKjYTQuzWK8KQ5kT8p9IrHtl1Nt7jrTGYDm2N9Wciebnmt0fI9u/084
4lmqSTlwBnnzZYxEkyYrxo5Lsv1c1ARw1BOBoQtauOgk6baX+2/Hnc3B550JSHe8eBKykeC/C30E
FWgRoT3lr4mj69HvBwtovudax2GZSHgu9yR/+GD3qrzIRFnaFiV9hu66cLYj1UetQYzB+Ti2vr4w
a391pMbT3/IDK/URuoMfqLr9opJ8Ad9KyqYDUgdlN4zfcnmxXWsgTObtJ7gqWguBXJW3dDnOKOsM
pFjJA9cm28cOdzRuhT/JpitOOulHhXwB/fosjZVoGb1xALxOrgWrti8Sx7yV2y7DMF1VE39Jwr6I
nNQbTXlnG1D0h8NogvXFI070gyDOlLgvj3UmJrQgrkyrGpDuKAu3UCcqaYpMzvyow4lRiVn23Q0t
Vj9EMLDoYX6QMcpa7X0FbgeD0moKs6D16p4lHMzgAITtCjAkQKCDfals/qBedKsA0ToQzJ819cUt
9RzxicoJObL3Ks7Gj5UCP6VWhKZyo3uz8OLYvD+McMv40MJwTy3vijIDfGLsEyZ1nXa4bOu7sfa4
iokMMaz/M9jMiSM4OBq+WkyzseQDzFGkjPzz6pIkmAZShEOQWsEZJE5rN2ko86/ELcY/LLRT/pBi
9mFiMYi4gXB3RnBj6+obWwugh7LjwFFLprZVwb2CETiak3jLAQ+foR0/QURGaBxTf9rZ/1FRYZ16
xQnxPnUuGmOiKmWPqM3JibMF9bdI1oD2EQy7/4SD5yFH/hApvqP6tOnMmtWoDatminjEfAdSvSfz
rrNUmOVTwo/o9XCCgvx/8wmTtAHVbRFLeuhLPlmiad4WmQL6SDnW8tBEjKe4P5riFyIBsZ5JzLfO
yXC2CJp5pNYUb8WvOGwhn/CqQlqxdA6MczA7Xzuc1kUWsEQKDqWjANB1v5mxvX4urznp+i0zZbKQ
1YBC2pQX7opcAz+2v1qWtuHk6kvNGh5vKJe3OdvTDePZxdkFd5VW6frBNRGB1n/s5DW07rY97Fj1
iOB56c6LK3sZXqyH29TB+m/LRkw4pXMItNHrLPzAOq/2nDWU4FJxoRUF3+XxTKuEM4UwodegUzuO
OiXaleNcKB8pTErhjwNLmaXMPKb03BJ3AUH0E5yl4V3Bkjx4JTMUhuPlrR9wKk1OIWxTFlTk/+iR
v/4Qj4U4hO5PpkcPo7/cyJp93XtPSfVEwPTj9F44leYbINah0bskyqsHDPfqr492b90GztpzW6tf
jMaoO/ODpnzzr0itsdc+Mw69NjoY6AegHSVV+9dv602ejUyB2ufX0/M186+lvfNGnjgBOHOOMD+2
zEOvOYOuvbi9ojaCq5M3NSCt4bkIW+GjvpZALOJgg750xZq1hTuYP3MYDumts/Stctp/XUWtGHTl
eSwbFMceSTvxDuL9PiSu4zNzTo1jZfCz4jSIfnaCKi8vyIGLmzKBn2z7RSKyyb4GOkMbjih7C8eO
rHWQslAurW/xZrlZ48exrZwZa0wJcGiCLdG6/Z7xA6gc6WAznt2PQyTwSb02n3n/Elu9grT2OD1S
3ERyPACE1naPn7rrj9+WBbjRxVKt36MckoxHXQXqy1K+68oiqXJrAORC7sHN9SjGuX1YQezCbBvL
MuruUK/zYjks8ArjnMFr8rlVwD877TfY5rx4DsYy2iObbXqYCKWHeMBUX6OohpbFmT1rFCqMdOQQ
amX3V5xCl1dsWKF6dHMvuFyN5btioEVx1revNvSkrreNPxHJN6bWNB9j5rAMWnkvjfWVWasDv76I
fgyfDnMdHlgZ9OXmoyKuwdMpMdf+DAGK9iEallePZZh2zeN1eqmnGy2xXE6Dv9/QJz1H+qHUcP35
QKnBDrl6FcGZNrhv1gDqfBNOYUgch7EEX6tcM3CoDhvXfzljtP/Q6aSZ9pHjOEnQYuAK10g2TwZ/
B7ZVgJo5a988dCfUXMg4Q5MHVyQTL0Q/h5yzv6CDgf1DMRytvt9fqJGeRFzp4XZH4Crer/ESpN1t
cqTtSNZpHST+QziSDBu8ZdSkdLLEODOciTs0PPoIU571WQpwQbXfn/tYfcN2BM6rQ/vxdGzyYZCy
E6QqNxXpsT21eks8gzzuqSylIEKBODCPKDOiT0iYkTon1bKVIh9peWRqXzmPkPyWYzWBegB7AjpO
rpeG2dhchCeC60Hto0O6Kh6r9mNKUHrd5xPcgj0fJVNRxtwCDL5GTPuploOIdHur+YGFQMm7BYKk
2f5i2D/HH01rKeNsed36OKoWUBIZfRycWE//Bvkm1A2RMvG0EyynngJ577VSKoiGzfcmNnONnDvI
MNA25uZ/6oiLq/gSlZgN6FVCGVN7IkUKzoGqeGjnckIhy0B1qGb75Fzu5cIQU50QTJIa8NI2UHR9
VgrD5gss+Mf3ZXqwc8UwlCEDvgyihPc448NL9LipPgzpFTmpZPvDvzjvo+sF4XlaB3stuCk4Wwgt
JutDVgxF/MEZMKtvOmAzBSlLv72grfJbReq+kBmMD102jALyiIG9dUNfeD0MOTz6PgvSmGvhlrqf
oi15jINHBXH/C2m8E7/kJRjkiaCl0w09b+saHYvGfgeWEACXvmH8iP0D6miMsi3tWywd2Apo/oa2
mWUZdFc+4dYdeN3DcwCjf4fUB4vCaUPhLITim1a4prJ5cDSjzpN35uL6hO+ZRD5KIfjZ3Qyaf+px
tLfXDkqXOeVbMl+CwgqOyexxsteOU+uVD0b1vdnfXntt7mf+QMQefTB9YRZoy27QjwZ34drnj9Sk
caTNnXotxYYODsYIkxjOMaXatymzfyVYqgrTsf7JhwmQX2jc6iteLa7xg9qf7S/eVdoRrLfebtsl
49jK7YL43XZ9bz4szUsyWz2kFvfoOysABPbaB6tUQ/pAWwH2zgP/iYUZgtRHFeloZd1wDEBbo5qg
oogXBzwMjVoV+L7kXKKXFXsWeGVwRS8D60afZIoYvFZfzUSgcOk4NCc3nnWvJ5BFuW478JoHOmbx
4fWN6w5xH3NS6collCTM3vRmiRlTp/nFK/nkygY4i7c0lKt5tQ/UyrUBoGBbl7x92LyuSy26OBcQ
HmRr9dR3hcIZ62N90Yzbcn5SLqnlf1zQJJu5REo9ZregFezCd/jMpftmB3YOZwwocz8h/nduHhw9
v1LHfZYfxGEj6mcjLi85jB2w3SI6/bjnrmvh+CYdyTdXYdTPt6QjClksb5ldCx0FnNUGO2reUvJN
al6i4JNtfcOY6wCodGZL/hRs6uE2rzkt9U1CTwRabnNwTwH0dSNmwwRpeRW/L3RXSOxt9ardRAtD
y09vSIiYUq1qKPgglQPEAQTYturevvoegniJWibIpSWEV2a/6Pxx33g8hWO9U/37oiCp42F5dhV/
+x1Y6GuqHCwQnAS5gG6uRYMvYjdk/4lq
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Rvwp5EPfpEhcrcRNmIO41E0vMlvKlP2i4Ydhk7ZEgYcfx0HUz4j4V7X3hr5VndDdL2qgRtMGOgqT
kAaEdIMhDw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
S41SWhcMH8PO0wxqQ0aWU10EBGFUi8nttyLAB0SHa72ecVX51QM64hRqZafFf0OoUUdmr6y7BcMY
QMwQh4G47B9tp5kJsr7GDZRIq8oAuDpMgkkMjshLOC4k4/jKbAyjJpAF7RVI74pgJN7T8MWm1Eni
s762QsGYMDFjcaS1qgo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Uw4HZBkusWhYSdXu/RiLDvboWYhdEi3DKfZivigGCS58Yn97RScPQG0QGfBM4yfpf2v8myp+yXQp
fj3aaXso7sMC1HYLM1yrf3N4ktJcGIibSPVNYynsoKaXBqO/CSx95zrLNxR1T5TqVkX/j9h3MGaB
LgRu6A1iieK8Bh2HOgPXFpNa77Vv8hhhqlmd6/IreYli9qNwl8gaTpmS4r6y36u8lgnxc5QPCRQJ
3uSdRqDvzfremIDDJYnKh1siILHHLzBcyrnoysZFUaImJe7duPoB28Va7Yqjb0F+dGakV/K+isPN
jqGZUZSq2qF5fkdQDnuqjkAMEulbTgRqlETlxw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CwrRQyUW9iteXMfNnymRJCWEr7Sv7ED3RaslHuPJ1s8DkvyS13DM+Reok4hMDnLMXMZYIm0s/fLA
Fr0j/N1ZAwAcWONLwnecKGwxak4PGibno8ZNKaPMzFs4eIZwLQ4m5nOM11nkttdA63BUB6yZNbsX
0pptcVlglQFpSqsbqVc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Dv/lZbGMVtZnXJoLxkPg18fYDB7aJxGa7eeQ/fXe2psQ8cAUTSbk8XoAMxEoa3za/QEErpwdQ5+k
1Y9NNaADsKLnDZixB4YasEIeOB/EdRYCTQ4QVoZFRPFF+sWf7AOW6w30O/EQ4r37cC1O/+9qwE0i
UETW7QJJ/P6LBHeHfQJnRZavefS0BI/hl0zMTPAcpWubXHQhGst+XU2AmqcJwc13tduwHORWU0Ww
nOKVv/Af07yOF2yZA/JPz5Vqrh+FqAXFY3ehZki8pro8W0njKCLdslGXIzNznFabjzwdUyVJv7B+
es9S8EpW3JLI+au6UC5BYN0SYFsctsUMnoi/Cw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13248)
`protect data_block
dHdMbBVooleduvTd8NaJy3iuPD8njG3bCR7Lbu/k/TxVV07H5BZOkeR43efgCUM5tPS/LQ+bjo6D
ZXuKWxRQGsiuBvqX31clkgAEzuEkpcLapDK1UG98PwdYyZlKKt7E7AVesC7LJbFckOCp5jWPvDqt
n5/9PenFby/a9hAw4A+f6gOvl7qHWDy3NYBrCERqe33AxRtQglSi/oJqzv1888XdlgmfRhJF5gpY
U2N9x/UNcUPy0QxMu0RbnXcWIb8H46vuljkRJUGpOt4D+rE1xCuGHHy0ivmjDCvHy137VI8Z9p2w
P1ZYkFRoedhp5gKbYejRi1YLFA5ZjfBcHIZOfZDo8j8lyVeJf+CtYOC3jT2cCBLiXEpxjO8qw5w5
v6tZl23PT/J8XbbqD+o75WJkDfQ0uG6oy/DbOUjMBziV/TEIIRUpopEcD5YljtD2hvSZ0fpj9500
HheEyiS9z//uo+ovwJ0TYLIZVVT965LOBh3TZ89RybgTVgRL2Ei9ww+G+TMUvToZxzIr8JLE0dOO
pu3JMjhTsBmm393MTb9qKq+Lr1xkQEp9mWwhsp7eyiiT2hmHL3t22nTMk6gn9Wqiv3W++XtLp2VP
aPEHFxA6yXOuZDLkHGzLvBFpKuQZ31zKJE5QRib/UDXyvwy70zxCx9lgoJM/A7sUmBWh1dKvnpE5
MI+u1z6crclzTyv91ZUoPFCjMCAkpQttsH04pwlYRAcpqxG2LHEWfDWWMAJvVqhHuVq+1Olqr0R3
l8RllxP4qvCW0Rgt1MJXRzGsE45KRRgmDTU00L+yARFL3nq+982vqTENFBfuugOqrM/u8tqcJVJ7
LJ6Xw+U5LB3Q3QhbwRglDfZzIt68BjbXRcpN6L1LHGgl9CsDdApyI+bzi0E5ok6wCUOGyX5gWe9D
OOYpRUtcbBFOAquc+naENH4+CsAOV+GmPQEusYRYcUkaT0iydZMJ+TjqKAm+Lc4QpvAA0y40lRuq
7rwToJTdIM4Qqa0ZXGom28Clsic0xDMRtx4CMfPZkfXPfbh9deCJ8ewtIWSTku5rxChcU+zuoVfr
9g7YNl1NARRLmjVK9UbZZT93saq+rulgAyyDTHV7q3qLCmuJnvg7d8X1IUH3pBJUSv9Hmf/0xT/l
+A34AHsDeGpLLkGg7qL2aURTngHX6ArCz1BEW6Qj0CWJZ6JbWu0SsvSRKIHDehcI0e+jAI/EQT1d
dKMkmqwtYk7UOtz2QveZQMFVIzVa4t98X4pUNFKHCxE9qA1RgNm97V826NPQhASB9S28FVnA79JV
8QPn0Jhst+yCtmbG3bkQT3OksE2t40LnL31oZraIyREz/qOX6fXkZXunTyBqRHHwuj4kaUUvdpxy
9NUCvTgxqilsegI/2bAPGtrxhmbH7gGhwBo5zgxNhWa75ElqGC+NO1kZbvUDnX1b78XjokUOP2Is
MQVaDFoN+I/9cb7IBGhG+SzSQFvxF+NSS8YwR3vHimqtNC8likIq5OfvRr1PW30/slTgCDSodPkN
gyqGMHqWXMoI5IOw7XALGxQ1Dt5L9ADcjuC4RrKYq2bL5Jq/4/ee5iXMj821nHguS5p5tawQdM0q
FjwCrZBqQS3Up67CEhvHtgL15eO5Mnxhr/59IJTPo4Uryf2r6M6GFaqsXaFWwt/6tcMTl3PHafIs
TsUIYM5OTpF//PInOA109JJedWq0zrDN6k0Mu+Avnv10FtWYdL5/BO+7RLfotK/HvsC2U4hj3Kiy
h98WiMbhC/U2ZN3Cee+2C1YXYia0QwjsSPSYH0UpN8XnhFFyATX6RJGiPu9zQu3T24ql9KCuNXK+
KV6evXH+MDppICWOJrMvxQCU/qsbKNno8sVMUrx1Qo5IkL2sbk5zt39e4pccM7VlJjrj45SSLoUl
LcBiywqqUNZ0r9+YCIN5oA7m1vpfZHFECcQGpgDzZJaBi7TON6P2zikbkGF9gNlL4sxLn+nJ2lNs
l7pds62XXFQPSn9LOXWxXCciwcr+HJ5g3kk839MxM/+7hjHoPROls1AJoZ6EbeaypKBvh5Rq0WBH
+oS3iI2KHhK6WtpfbytljI8JzYnHDYZrFXw9tLwv72peGmhUChiYklT5qKh605cntpEGZvVLUOKI
7h5Obnmqtjm6djiAgzaEDa7YNBBhLXk7cZPhjB4y1c6I+17+xG+IphOqNBjgaCtOcOekW0OhrvBm
qkkJLsICY9fQUkkPiRa9mFpJRzl2s5W0rdWr/Uh/8+jKKMGfldKsyHuwmbYXL2RD0CjjJ70SgPyq
+LeKet1VQ7N3YnVijEiCYFUWbH76ARCheDeYDWLuMe/ySbaknXqTlXXzHQYhhhLeRFIDDlwCPd6O
BNIulCJHMJ02KGwqm3yCskhhc9bmDOJBd+K56pfe07o6sznx3geu+9cfhgGN4zg5cP1BFfeA4Mio
Ri3SoF3IeV+2vkF58trS4Mt/QjZ3WAA4yD6HgekZo1GtH/Ahue8D2FY5WTwQ4j03RwAR+ox7DUN0
7DPK6xcQyGeXEJH4kjJbTWZ+9N+OdFdei51Q0typayG/eRYVP5hRNlQzffOIpviZhNWfQWyiNvM9
0tepgFEH+B/dKylIlXJGDMcm5y8CtWLexmEJ5sIxxTMFWPVyhQ53zN0QnwUgZZgw6T9/AMziYGUB
TqZPUptrBxUV03epEKgy+FUONAcSROhJLm5fMX4O4Se1uRYKNCQTVD9N68G6pBRkAF4JVd3C6QAx
cEpBZe30veCvJx644CMkjFwa6P9S48xhMXn3Ei632HIWV7MOhGbLBnGerQ/UQDxHffV4HVr1yrDM
2lUrgxNmhXYiJV6KgDoPpIYdX54QwHG2kZO/MMRrFVtggaZNwcW7KaykuX0ZvAKKQH/5hwMH5hSL
qXeefvyqri+u3S/nshlCtJy/D7lMAF4ctFozWWHwi6xC1LwTS3Z8MUET3Kq7GdP8/7iRoefmfYDp
G5X63vuVVYHlk+l6Oo4qDYn7oH0TJFGEPPcng1QwXf2X0BQXL2Yd63h3ePMR8hy6qDgX7UnsXsSZ
MtgJqfuYsP5bL/V+XwnnMUaGiBqhBepDFXfLxnKsXPMyH4gfMCa7gRKL54Mxft4CJr9oMYgH0Qyj
PztttFaz6XGtTMuwdC4cEr3hPordiPn0hpCF4MuZ33/yw4UjIbM7h9xh5Q15Mq9EIhoiP0btBVDo
8DCxnMFYSyGZ2+O+0PXLRHFqIAmJv46s9xSnrqu65tWCocgawEYBo7T0WMREIlb165qntlvx4mAK
B7mIqd+IkMPpPzARZV2wnJFqwPCF6C7YHu2xM1sKb4AIHrGSUL+dcZYFCtpUYgylxVcpbwhOfCjh
R5I/bwHehxbKn1NL+2bdALhL3aVY0ZiA+lO94G/qK4MYADaU6jRy5PngbK0HyjU3xA5khq/volXg
GqzMqKPPB0nctxIZKK+By4LTXq9b8aPKUAn+OIxgGsXEOaTRp0U4fUBLRdzgVAyu5HH1dB00EzyW
jf5IyNhOKf5yXRvQzvwTq85FvuunrMpxJiQ9SXYWwvSccQYkHiHRTwKW0ZTSdrzAHuFAAkBuQ7DF
cDKAZYpfDT2/ydRJwjBk/Edc8DmYFY+CrXrh3m9DyulqWNDnMxI2n7pA3W0BU/sxbbDOkgL+iiSv
lR1V3IDMJth+VqA0DN9BS1uhq5OHoXaokv5rDey+o30DFd/WIy1jVi0Ddqm2ZR5++FmfiPFx43jF
GuTDynMlqUxyvCG8+geKw752nMNsP4rwtJBdtfAS4+UkPbZokxlU8Jdnz3pJ00hXXLcb490Q033R
8vxYQfjwHcmMigWwHCJp5whgcMZQggOjFraX86c7E81wfqCRhU0ufjRcCpogq1MZaVideg5LT5kc
PsM7DbKdFzH/VhuVgYEcz2Wypc79lFFgp8Gia3bewNxuaXZkVXuFhmgqc/6r4j9o+HLJ2Y/7nWaE
Zydtpawmzd1hEgXoijl3PeKBBXW4Mg83zgJQXv8bt17gYHq6jGIxNLz6/zyfGguRhUYvO9O1wOHo
kB9olYpMZr76uCHPE1YcNC2qy9WKzyHyFsF00Nq/T2UYC3U8Dnf6eU40Pk8MVqg1Nxx9yJdjWDgV
9rcebgkt+FcptNc72N2pweTRauJkgEjBx6RvP7QRzVCREXusrmVM4HRBxE9fQnuaqGt1IukJHCRM
Db2MuUfPExvuoBaXo/SOoGh8zSEgzLNCQqgXLt8JA7t76CE7WF9i74U2e8w6QWcA68cQ82Rtz7I2
7tBaWU655Kn/THMVvPnzfMvohRh8ni+XRXzP+736oDQfjzCMfUzZYcBaxYVRnN8PcnQMtzdrE0LY
29wYr04RGCYkJVJWMi2tisADkarLtTzGBMcPDFyD7xBmx1H/layqXNtXiYQjKw3Z9bHnuykXODdd
mAN4naf8fWCuGHTRbUPgCk/2h6HGfvB9j5ZwV2yud/gt9VMJ2rCNi3d2YQ2DzM8phehCqRo+IwOi
GovgYDKbB1sM3BBRJKHoelf0y1Kumj9pd/ySH0QOdAzt8oCKqofFSF5tpXkObtJFqPDBF8OaXgr/
tZszZeG/MpRKSJEGSMNxCA946T4p0dtnC9sWCkesukm+7Ov73zw4ZauznhqTxyj88zr3DCkXzJLF
fXDcZ7ewjYWpglN4t43BAG/PUmKJBnbb3qYqahH0p9RudsBrswjrD2T63ylcnzPMg1ZONyjXvUqy
AN8aO66lMmSR4soTUacRt85MvluQCSi6CkEKq2fbnmnaHkJC4+h8H2MQ+/k1sb12x0G5kHNiuTcs
K4d2Fy8zWeDkCSOJjlsuWXhyAWPRI4VhufIeJj/XqlWY0/cEUgKIfIb7UdWQXrz3kluSkWXdUKDa
Pu9jAEHscnSIibY+pA6mHY9TsSoxOkb5Y6T6e331+m3ftH842dZedagtfUDmTMWEP+9v84suRYeq
jFleAcnGb71yiCtvd4E+Njd/sIRVQNVgfRUS3+l1bezJBuiryAph4D0HEZSuej7/WxDirCGQ8Jsa
ZmWiv+2Ulc1NQD4i2j2E47KCQLeHdSHP3Zdnr0E/dJvRIFsA8MlSSJEeuw0H2jQ1MLWfyIiTFwF4
PPh29zI+8CggNrxOhrjeXXEQvniK8qh7lU0buUR7p4hJUFaMjecy+euf/Hp6rlSLUf+n1WJJTSHz
+wRT+RH6ce3l+FBdUOKimBcAYBLoT0zQJFqNjBbTpbEj4q/TQirICmFig5hF7exCIYJmKCAoEznX
0j2+MMhPMH7yWHwqTTb3fr7EtrkGW6FXwCBFcHBQE8NEgajJ5Q50/oGuP5icbS82bf/dBRuBuM4m
+rLF7UcpMVRidFRoC74T6BfQhE1DprcnwWh2Jhg8Nubqwrl2kWVTWr/9zP5++LeptemrmPStVuKz
2cjQ2I/F0OSjUzkF9NyrhwlxsJdrclzDi+BtvA9mgz4pTJI4WgB/h8Cs0SaQCMoFcTj0EOQrgnFL
3cOxbRoqAZlb2YG1Tll1CHzPDE8S/HypnOIiLVeo7FIvjxc+ly6eKnCEjHBQOWjxjB7KUI2wslJc
UZ8KzgD0y2eTRYlLGSyLQF0qwCBwhqkIQLqURKY0pxbWHlUFHn4JPhPeNP9wNH2dMC6wezonoSQ8
FZRzeBg/dG7wQDEr/gVIedG845yeZrBHHvfY2feSeatsAvaGlj8D1lpe5fj4HQtVH/E3QFhtq023
nm8rM4WFXdNvcUhly9ZPPRU0TdQJKmLbavPGcjbYQ7ggyvB3/z2B1R8s+JSg9TMxzBlxNBjvKrEY
AsRCG8cO/UroFOKejr7LRBIg1Jt4/wRaZBbtCJRsFnb9I6/q95x1bL6S/VCTpwkiPpzyCFvQ1p2h
xmSeNp4VDxM3wd+EdYtZh0KqdqVIhsm+8g25IgaxmfshnZD9dg1NPGr2JKwgV7538dKjtgzNYIXu
OGj3Kb93XEszpiZQpPF4GNKZ9XJgWZFzkRwg6NpM4cRPWUGtRZVyIykgctVqEC5ZWe8gft7b53ky
UA4T0H50D60FvRu7R84aMrwRhF5sMDuVWCoixPEwnu4QpyRe88Ot7gX1XRE1kB5TilvJbeM7UGOo
KbpzgDFstKIpHR5KnuldH9KPpRMy2KC4+bpcF8cLXIiRar4FEU/xLv/PXcZIkj/1r9taushJsvt5
NAXhA2iKy1NuH+rLvmlEMBTuS0muOFFqqOEWXVWee2XU5wEpIPvs22RGGUl43BtKk/D7gb3EK0iD
OEkCwegz4emWNJUO97t8XMaQRzkgCwP+22M7B4v6zZmcKlbGIJE2dpDGZkPe0gPa6wptiKvKrXHV
FdtpEcGI4xqsEa0NgzxPtqotTo3OcIJD1pfzVIJXZl3+zQzQVP1f7qMPEkLjV3p39vtcifFh+2Ap
FNoLh6dT8QbIENXetskABEcK4gxi4oLlP2iEuLYM/uyZLcENCfE5/qRgvvS0nNWPI3dW083Vgu0o
l79fV6G/rzgPQvj/EHk/ZYALxe4Q7Mj0nQdUov3dF2GNwtELw0V9CFkRqa4YvtxE86Lak8jpmx6v
ffoWqm4oziqLZjHtzhrGFH7EBeNDF+vpEbrjzQQXCli6iZS3XesXF7O66T5bH5vOBe9Ge3UogHeV
eOYENdsDgqwLrtYeYoMI7uluJbsf89pzWJjCEDDS6fzL6VguK6hTU/Gz6asQDb2e9FNS9rYWlCNU
9R3LV79Lx/kAxCvMrejryDdKtG3XxxLF05S6iC9vJTM1lvChhRnEXG3LPqSAeiQy+KyxKzC7EzXj
BzhAXgKiZLWx8RYROTYP7T2jznihUtJVwf1RHbmjkDaFmEDSSXN02Qfj9LgFkBY1NKqK/H5K+nNc
KQPzudQpdgQQ9AIDFrDRagxKhqeBU2/lCh7J+hCAQQ3fLkOM0Dxo3Q0bzNGAifOov6Kv6WrzKsud
XPQJLAUIqxJ9/1Y2jrIV/bXYwWaAwPdkkdfUU6AoR7Lvszp5cmcjPObVy18HY2MrtjnYbgTXUDUz
SkIaReVIejLsbbdRgyDF2dTOP9Y2l4zk5wBaxjO6G0h/odKwakgX3RNDsAH0s4DKZa4oTKotSNs1
VPSAFMuaTd70kunHfPElKIQfXNKRKrZMnSuNJ8Uat1PCKrtRvdzqoIYPuYao88oPaAKpznnyDfcM
NxgDFCR+G+BmOPrHaRwFMw4/FCtTjvFS42p7XmL8e1G7K0hYXqxuPje4Z7MUOSFKzVYSJXqIUUSW
YQQdZfovLXA4rT5rD/8sBBDQeLJCiPMGZuXEWDaZGJlZwJodBJGtSZkJu+RJIstVhgUOLNi8OZsq
DNeMqb+QfamJKddekRG+0JpdtC+VG1edI4Dv35ztBz4cZk5uYpKaINp0yFql0dpeKQLR1Sd1z7gJ
/wIssQ9xCCY8CgGH2iupL0vPZkb9fyZq1EDc9X67QNSPj+99wcHnAOXU4/Maffwo0AJMstbUSYs0
6tYDKtZ4dKBMcAan/QZdS4N91B4HKAJ2GdGMXWGWPVDlgQsJBHDNwGXiuVWr6PElvDO2PZkPtFQI
e9tovwiXZiujwK463msn4/qrsdPqGXWco/KXcU0i7WWk9lKT+SG+Sq9DZAruXaheWzbHCENtj3wV
YnlIq+uJL+s2nRJcqqKRqiO2/G0SpC0B8enCpybAhDJhKhBYshmBPs4rQwg3zEmjmliLuwYumpN8
drwYtLC0Mh5brRjOi2EyNJJv8qlbW1tqcby+2qbrJHE4EcBq3MtffHB0LlAIakSD7d5YdpAGoLnj
4uZ+S5PxCDWtAh6UpFgf8QWoSWdMJEBrXUCAr9b90R1SkjkgfV0RURQAYM/8ucqXv4fTaGkcJ+Bj
i/IBYgjY+mrJaZ1XDM/XjmeTtlc7tauWhF/b/BKXTlfKkBU7APwWr5DLRAYZaXhqdzoMMUb+Dag1
0sd/kiqCgUGTXizuC3F8NV3AuclwGAsDclGonWIkCov/5dniu5OmIfACRopK5yw3/juNKEgVz4hV
NMKuea81apikPm+ClBYasMoJ9+BsMTxHHomrNBRfNA6q/yM/caZaUIReVbEDnye/fiLZygmkrnDZ
TxkM8F5TjAKVi7cwLl20qIykSAo/NotH87kFB2h/v824EGDUnPhA43oX7Grxglsij8A+Q+VWBGWF
ryuRvJ1x2CkhxGjPQa1U07X0YD9M4Skx4JrxTcfpzbkkoiWvGHoaENjUvFEIo/69/G9w3ogpyWoa
4nIC5HcvKFju0pr1XinRcjRlfH5DTwNEmiM90igVlE+4hErbNe189fBYY55n7Z3Cq/G9+NGirHXz
RJtsNncVd/byEnlBxnNB+0V4wsg/ZmB4LhQZTQTKh/SgZGfT+m8olU/hQup/uAgVBCcu2YYX+aG2
ubPMSaWbz8/rRQuTjAmqPnwU35xVQNpoXhn7I6MssksA0tSIjCJdEuFi3+V6c2FqogcVIsXY/P9I
rSmmAmc+xNQUn9ObDv9YlLIF7v63HIqfm7PGyMhnCYG6vhFp+qSdr5cmvoFmBhw9acmaVKah02sC
EzeS6CRzyEkqY+nJC2a7KJc4mVSK//+r75Dtg93bLFS9WRV8nCcl6Tjuie7z1OBsjyP2BsA/kFqP
LFrLUKWO+m+Vg1orvnLBFdN9WtvgTySc3hRi8ddMqChJOcoazUK1RjPHnroa0hEC4imoJuxh2KJB
dx1iV9v5rMo/BQgPAfR6B3FwRPybtHQBUBZk1ev86SPlvRf1PpcT8bh9htlgAZm3pJBP/tQbwDgj
nViir5KhUdAiR282Ko7bpzUmT4uuK3nsfHxvXzLJGK38Z2foVtF5hIIPArOtgFYFmnmQjeQz4JBy
G2DuHcapaEInFWo5uymXi80fpYfEJHqDomKDPHWmqfHrnQgBBeVOyCkCvNO6N9CyPel8mtNcufai
FW+/dIacfcd8xoL3qQmpy4Fk0tKWuHWrGWPXKCeqwJmiSs3vvDsHdQX2tPWwHafoIeTjHGUsV8bg
mPQJz1zNn9iuKqa+ioW5rQbAccEqu61d7VFAr3dTaC9r8yOTp3kAYLeuqJ3fs740hS5VRtYhEMke
qYYPDl1lauCAClHKi4lRzcW2ibpIiL0w0IWIxzcuWYIW6ehGRAn3Sa9/I9wEb0Jm5wSnMsnpWKV7
MAqi0oPGQcbdJjuItocNaKn5AYOv5nAToqtx1W5PeJFFzfxaPzNBXf2ae27sF87Mdv1gmp5Wdl5j
QbHwnQ4erRs76Df+YbJ4UYi8eqdNmZ73uWQ5CsubCC1jD9e05G3oNSN0sVHiSHXkUFLgnOiJPgwU
hjUOj15QWID0crYWaDcqxFMdYcZc8FfP0hhNIqdIYywzc2LRqslZ/wdjJqTYi/C8iwZArkfKVr5F
vEMcaKF6YG3ErlQo/hQ99Hy6AE0FaWfFNIbuVCtBeaVOFcviJVSe7XyBFKgO7G+zO/QVfyikBaMU
aWZqVIPYbz+ZErHBeCQng1yMOBlLspZ5Cl6obgq5kwxzN6Jw6Ck/1rrfv94CQa8dU73tEXTPZEFs
st8tFQcA89ul0KChznqGYSV3Dpc2VJtK/r/GCvAcC3wILOP6MxJ48BJMj6RYiiA89Yojr1eJJ6tl
IAQZE2v6SgYGfMZglYJqvsfhkoCdRENbLHH1k//LJep9sdUghu06R8e2kZ5jPCbkgM32Do+okCug
KRMY57mK3iWq6t84bNWZzXfhIEgdbs1lipSzK3CmGIMY6GaKmpxvj1d1gc0FzzrKIsYjKqtNRZsM
MMAYeV6GpoGY8mr4suuvJEzGOPkpXOXgnIU3sAxgmLFOKiRgrL9TuNdKzNg7u4SWZus+swX7HNwV
pDddukd8r6Ad920q2UQNPJwSnnQume6d9giPdRpBu6L8AM8SiNURNKaMFI3YPPb4OmaI9sCmg/o8
CuAJ4c3rXNgk44ZcbBhNIM0sGy2aR8iNsU2V99nwFF/TamsTXACL/P6y5DCEk4dq6NHhIlKgvsD4
afUNoL5K6siK7TwvsLS38b2mpeYumoXSe3b7lPxKBWs/jDlR7oY3Qf7sc8SolztymT/SXP3f71Mr
aAmXkmpPs/oyHndCAE8JvgFmZ5YeXofk+1eQCVjy9tSPg/4eDzjYsTluzsoB7VWYqP0Ly8gE9TTh
BuhW4Icso8WXNzU7qihvFKksXrtMeZjonBIkDQh/nMbFG82vDzWCqQUhl8lNCSipkA8vJBFf4qj7
utJq8udvtBNwxfsq+agB//exDnmA9FdGNRVEZLNuMB7Tm2qPIEdmZIPkd/yQu0R5H0Ljq2tRy3np
lQptXXKlrpdU83OLi5P59yvH9LATWAEeQWIvJyo6NOj/ncIaeZr5ViRAeQuZTpcKBxAh+axNLsIf
v38QQSchb0a1dgMURMkNiH5WYSlGIrQz4Bo6sUxHSOBDqhkWxqTmOLVj+8faP78rjFsa4gaND4LU
VnBw4bxECKs5xKZM4XJlyLoPgnu8RDbFYfenZ6K1SMNnClYA1fZVGRMPBCVEdT3df1xqILzrUyCP
BOfC0NeIfi395u1/GTowc9FaPJuXeRX3o2tRcxTXnIOx1HeA6U1J9xLTsUcrP7Fa1GbNOAUICE8E
6zO7HRtn92Vs6tqk1+2b/oNf/Ndq48P6gAMO/U/ES7gfaVGfVOXb8XuDdjy2iKWj0VDpmz1vy09O
BtxxxEIVWyGeU7RrOjinP4171wdr/JlY9QqPvd/EiW+4Tr8GH8ksERHsGqnF2tmVQSnpccMBidUp
m2dM2+bzw5w7YMc0pPnbN2VQ+xpyEMz4ESGxVrq8+yf5PTIHkt0ZFDZ7DW1o4xGUB1gZ5+qUkFIV
lPPEQ55oLtOc58uXQTkI0cRnZkfOBfBP3KbEJXsTIkUuOI+3dm0/0sCLPwz5VOXZKkxVmcz56AUp
eCPbD7jO5LSz3GbYl3OzL5VW1vrjMSmnzmIDWuSQoorpL94mdmPYVpu1X/XhtR71GwoLNZpTTqEO
F4jZTC8Qzgw8OWvLhAlBhZnCGNuLDgXZs4JBOC22xQ2tc/S4aVc1o+hnyl9DXI9Ee428yB+eFvA0
RMtLoLJ0UlqasX49jvp2ovpg+5D3gI4lhxZuOsQwMWMntJb4BJRcWR3D/NP9WlHJuPZXGDPH1zTA
Y45emzl3aMn/pRPX/XBB6oQZT52FatVx/KZWqWJHjm32DJ5GFAErHf7gYV/8cN/IgXSRmSGbgA4C
iNUdgtdLBSDjVk9LsWrR+taKVMj9dFUhssCDob1zCDo3KcKNQawTEZZjkIQW9EZabILuJk9V6mKO
Yczb4aEKPT57x4V9uOZ/M/fwbaexJrana1YT/mFOF8Jo4NgQ4D2/SqwPMl5Dhfekp1Ql+M7ceTTm
ThRQlqfyhrbakMgZJzL5ehxf3R0PawdBAw570Zw1qLv+XXN+GHnXgout4KoCdGAIMBlwRGksbdpl
aKMD4wPnfRKpVZcLgDDjjS7sdZZykBcA5LU8dkhoixuttr11dXSn6FwPBx+qDdwLBdF7WQFa+Izf
mMFsIK7CsB1eJiGOMYCwsrmZZeuR9x9mKnKpI74OxrQ2rDbQgEUN3CLMAgcymptzJ17O5FnqTDnC
03xyyCBlwCK/QMsBkwRbH9M0C8lHjrwK5mtSYrtnI3H/GUJX6mAn+EJvc2JvaVUzZb2UttKQqCEA
kO9WfLfCe0MM1XOiCGRghy0e6W92GT2TqdytUxkasIadJd14p5QWw1T28wVqrkhgNxU+BdqM91ws
FEzjZbZLotuDUUH5FKCpXgP0huOw2KEA2PxUgsV8m+I0clnZ5Vy0RtwImR898uF2cm9RpYk9dbi/
IdWsvhvGzGaVxQ14HrRtzI2TYMppTcPfG9v6PiNDBUuRITTVZXvT9AWnsIH2/0j8/MIfv1kVU7qA
g5DKRSY32hLgXdaB+hcW4c3aHOZBE/7VT9YzjAmMcG3aeO+jqNs7wvpfSRl5BQDZxkgTL87pWWNC
SB4mhOFgKbOHJ0Z+CSI+Ml5drrQTmgNSxRJrwsrpxxu/XKUBVPhxVcIIbaXxlisC3U2K7ZQZk+as
xBhV3hH2EurE1rH/25OVb+J1H+A9FGJwcViCGFZpgRNzl1jhm2wJHnxOn1Xk2WJBJh4Zmfg7G6Rb
q9idPst82k1qBZeN8NtW0N2eflk8vRe8ZZFoS/QLmowRFV0L6lujHY5B1lbc90eFum5sGA34nnAP
oANvWAjlKMbF8/fjYMG1QyYsu/3E8m6u9hP8A4h76NZ4a2JL+8Tei6RGvbvxJ2U9RklM16YVJx4B
YgoiN94OZitB4pLn1ZjbriD2t87pJzYGKMmiC8G3sKqSRrnhqVqgnX4UPbAakrmTb1fc2qI7wG1P
ROqQas0fE6s+PooRrxELyPWwDt+AHgvYdF3elNMa764AxppGj/4Aj/xz+x8P0WU4QHNk2+F1pdHm
NgLzyDY+TdMHBKiy9b4+KWTeP7c870IZdZhFD3/ureJo+ANF8rV+YgmkB/R3LEZRE0BqqovCeylY
fGXVmG6PeboHzywKa8cVOBDVi1QuJ+7cqhEYjEqfOhIp049QXql0q3NG9/I9g8QiIxG5SfFXG7U8
RKiyH7snZXdt1KCC89ZbdHqOGVZsLy9JVcoWY6NxeGGLYqn+ykDs8WgxgdPGVlv2EZKaDQoAQjau
Ko0pek/fytxtv36qKWVIvS7Kld9mU0Iw1P5ftFvOM+jrF8xg21RGpJ6+esC9Ia9xF0P6uVi2ZFS4
I2XgtKfeJmYPwMeUXzLBLJ/tvKG6M4Jv4K14iv0kVu67md0VZNMpmITGAti3GKfMjdEU6JEHTf4s
0zw1uf5Y000HaTLyIR4PnXn+1wt+tbeNqJ0Vxie2chhEguk4wK5nly0D5SnlKpMSIdwtrO15sBLu
E2KH1X0foApg7+fpgHxKb1fjjlyu3WmdknxHUzgG5urlYa8T0oJwgfRvPjPUe+sjG655Sp58Z8/n
h2yu5RDmfUOVtXBdYm8Qcbx7xH3CSAIPiVX4FlSM6FICdc0zk3I3QYQI1txhsUDLlB4ybQqCketc
9PV4Ji0idQ3xXCYAuxZF0PM5EWcYFbuq3OrSc01B7/Phd2BQ9OgY5qhjWYc5AIvE9HSsTZmR94vy
Mr6xIoTMRr3DNdWx0Qw0QDE7rDO0rcHD+0UF6XAaZ4UC6AItUMGFT6dWrNvFRfbm8AUxBTwJ3KGU
QSZzj2xARm/MiE2b8eg4i71bJ+W5mbCZfV6MyyvuVPhBsd0YKWhgICiqq+YrHOHM6ZnmvYFnnZZm
brT3iEzoaDehmZpXuONwEmf/G7jpq32BFKefgAmhMYR52/PGEcEOVE3KfVeKBiBnk4eDnTHiiHU1
rcqJuGq19yHK1ssPv4Ncxl0Bj2cNvW9eF+4Xl0vnKR9wycpqmjaZpeQ7ShlSfty1DcDk7HPWaWv6
089s9BGcRgn6u8kQnw2n/4Bu5iIvAktxXyslYqAsiUtfGJZVRo3fw+jdsw6wHMtTB1+Oqz7kfEJV
ZXGeD1EtpPZWECf1iwHPRqRkS2qYmreBTgx8pYomfWRZFqX6IQPEkO1kOxMvA2K1Ejz9O9Fik8gx
HlOstKnAelD2tCUHnFDf0yzew8R1NUIO7+dPczgWIWLpeQJmnXyosA7LrlsixnIX/TwHAswLOsXt
DvfeeQL9ARm4dsdqnOGHQsFy9dRxF8GAccNMKzGrs/FV1bJfOxObbjbriw0t8XzmWMEi/5BW9OTO
4yGZsV5n4F2M3BoM5SIQBAGUe1LeYPYFrr43e8xRFB0AerMnqou5ikwK+N6soClXctk2Z5U8nBkx
3DhVi1G6AHs+KAvWSGiQFs+7yYMa2mASh07ZPLUD3Tiu5o8N/ta2r5czpJ9YPSAhW/4UDXau0BHF
Qdjp3MEcbl7D6dFdvAJOXuXnmqu7ze761Qc6JLe9PgmuH8Qyntfhzqdb40W1XqBqdMoT7U0ja2Wa
TvaPFTH8qquaLCW22cK5oSvY2sI2pzEqbhgpAsPiDEKQwh7OjRSrFMegCdNeL4NR7BFZdCQtyp0y
xeqKaQn359gTfo2ZvbcE/aB7iEPl2w0v3gZQc9jH/yuHXA/7CcQ8U6kr3c/fZkb5ychHRGD+WtOq
gTIQAtF3KzB8wMC3O6W9rQo/IKMfBxOAXp2Z8j6KjpbIvJiGi+PMKXzziG4lZzPxLHMmr86paLWG
kBDOg0gRj1iUfhA6/+5MkRhWR3HlkPW0e4zl7R0qIVfb6oBDbvKKA0sfnkJNgrbm3DigFZYMKaUU
7rmFUwoGrugl7kwh9sSJZbKjYTQuzWK8KQ5kT8p9IrHtl1Nt7jrTGYDm2N9Wciebnmt0fI9u/084
4lmqSTlwBnnzZYxEkyYrxo5Lsv1c1ARw1BOBoQtauOgk6baX+2/Hnc3B550JSHe8eBKykeC/C30E
FWgRoT3lr4mj69HvBwtovudax2GZSHgu9yR/+GD3qrzIRFnaFiV9hu66cLYj1UetQYzB+Ti2vr4w
a391pMbT3/IDK/URuoMfqLr9opJ8Ad9KyqYDUgdlN4zfcnmxXWsgTObtJ7gqWguBXJW3dDnOKOsM
pFjJA9cm28cOdzRuhT/JpitOOulHhXwB/fosjZVoGb1xALxOrgWrti8Sx7yV2y7DMF1VE39Jwr6I
nNQbTXlnG1D0h8NogvXFI070gyDOlLgvj3UmJrQgrkyrGpDuKAu3UCcqaYpMzvyow4lRiVn23Q0t
Vj9EMLDoYX6QMcpa7X0FbgeD0moKs6D16p4lHMzgAITtCjAkQKCDfals/qBedKsA0ToQzJ819cUt
9RzxicoJObL3Ks7Gj5UCP6VWhKZyo3uz8OLYvD+McMv40MJwTy3vijIDfGLsEyZ1nXa4bOu7sfa4
iokMMaz/M9jMiSM4OBq+WkyzseQDzFGkjPzz6pIkmAZShEOQWsEZJE5rN2ko86/ELcY/LLRT/pBi
9mFiMYi4gXB3RnBj6+obWwugh7LjwFFLprZVwb2CETiak3jLAQ+foR0/QURGaBxTf9rZ/1FRYZ16
xQnxPnUuGmOiKmWPqM3JibMF9bdI1oD2EQy7/4SD5yFH/hApvqP6tOnMmtWoDatminjEfAdSvSfz
rrNUmOVTwo/o9XCCgvx/8wmTtAHVbRFLeuhLPlmiad4WmQL6SDnW8tBEjKe4P5riFyIBsZ5JzLfO
yXC2CJp5pNYUb8WvOGwhn/CqQlqxdA6MczA7Xzuc1kUWsEQKDqWjANB1v5mxvX4urznp+i0zZbKQ
1YBC2pQX7opcAz+2v1qWtuHk6kvNGh5vKJe3OdvTDePZxdkFd5VW6frBNRGB1n/s5DW07rY97Fj1
iOB56c6LK3sZXqyH29TB+m/LRkw4pXMItNHrLPzAOq/2nDWU4FJxoRUF3+XxTKuEM4UwodegUzuO
OiXaleNcKB8pTErhjwNLmaXMPKb03BJ3AUH0E5yl4V3Bkjx4JTMUhuPlrR9wKk1OIWxTFlTk/+iR
v/4Qj4U4hO5PpkcPo7/cyJp93XtPSfVEwPTj9F44leYbINah0bskyqsHDPfqr492b90GztpzW6tf
jMaoO/ODpnzzr0itsdc+Mw69NjoY6AegHSVV+9dv602ejUyB2ufX0/M186+lvfNGnjgBOHOOMD+2
zEOvOYOuvbi9ojaCq5M3NSCt4bkIW+GjvpZALOJgg750xZq1hTuYP3MYDumts/Stctp/XUWtGHTl
eSwbFMceSTvxDuL9PiSu4zNzTo1jZfCz4jSIfnaCKi8vyIGLmzKBn2z7RSKyyb4GOkMbjih7C8eO
rHWQslAurW/xZrlZ48exrZwZa0wJcGiCLdG6/Z7xA6gc6WAznt2PQyTwSb02n3n/Elu9grT2OD1S
3ERyPACE1naPn7rrj9+WBbjRxVKt36MckoxHXQXqy1K+68oiqXJrAORC7sHN9SjGuX1YQezCbBvL
MuruUK/zYjks8ArjnMFr8rlVwD877TfY5rx4DsYy2iObbXqYCKWHeMBUX6OohpbFmT1rFCqMdOQQ
amX3V5xCl1dsWKF6dHMvuFyN5btioEVx1revNvSkrreNPxHJN6bWNB9j5rAMWnkvjfWVWasDv76I
fgyfDnMdHlgZ9OXmoyKuwdMpMdf+DAGK9iEallePZZh2zeN1eqmnGy2xXE6Dv9/QJz1H+qHUcP35
QKnBDrl6FcGZNrhv1gDqfBNOYUgch7EEX6tcM3CoDhvXfzljtP/Q6aSZ9pHjOEnQYuAK10g2TwZ/
B7ZVgJo5a988dCfUXMg4Q5MHVyQTL0Q/h5yzv6CDgf1DMRytvt9fqJGeRFzp4XZH4Crer/ESpN1t
cqTtSNZpHST+QziSDBu8ZdSkdLLEODOciTs0PPoIU571WQpwQbXfn/tYfcN2BM6rQ/vxdGzyYZCy
E6QqNxXpsT21eks8gzzuqSylIEKBODCPKDOiT0iYkTon1bKVIh9peWRqXzmPkPyWYzWBegB7AjpO
rpeG2dhchCeC60Hto0O6Kh6r9mNKUHrd5xPcgj0fJVNRxtwCDL5GTPuploOIdHur+YGFQMm7BYKk
2f5i2D/HH01rKeNsed36OKoWUBIZfRycWE//Bvkm1A2RMvG0EyynngJ577VSKoiGzfcmNnONnDvI
MNA25uZ/6oiLq/gSlZgN6FVCGVN7IkUKzoGqeGjnckIhy0B1qGb75Fzu5cIQU50QTJIa8NI2UHR9
VgrD5gss+Mf3ZXqwc8UwlCEDvgyihPc448NL9LipPgzpFTmpZPvDvzjvo+sF4XlaB3stuCk4Wwgt
JutDVgxF/MEZMKtvOmAzBSlLv72grfJbReq+kBmMD102jALyiIG9dUNfeD0MOTz6PgvSmGvhlrqf
oi15jINHBXH/C2m8E7/kJRjkiaCl0w09b+saHYvGfgeWEACXvmH8iP0D6miMsi3tWywd2Apo/oa2
mWUZdFc+4dYdeN3DcwCjf4fUB4vCaUPhLITim1a4prJ5cDSjzpN35uL6hO+ZRD5KIfjZ3Qyaf+px
tLfXDkqXOeVbMl+CwgqOyexxsteOU+uVD0b1vdnfXntt7mf+QMQefTB9YRZoy27QjwZ34drnj9Sk
caTNnXotxYYODsYIkxjOMaXatymzfyVYqgrTsf7JhwmQX2jc6iteLa7xg9qf7S/eVdoRrLfebtsl
49jK7YL43XZ9bz4szUsyWz2kFvfoOysABPbaB6tUQ/pAWwH2zgP/iYUZgtRHFeloZd1wDEBbo5qg
oogXBzwMjVoV+L7kXKKXFXsWeGVwRS8D60afZIoYvFZfzUSgcOk4NCc3nnWvJ5BFuW478JoHOmbx
4fWN6w5xH3NS6collCTM3vRmiRlTp/nFK/nkygY4i7c0lKt5tQ/UyrUBoGBbl7x92LyuSy26OBcQ
HmRr9dR3hcIZ62N90Yzbcn5SLqnlf1zQJJu5REo9ZregFezCd/jMpftmB3YOZwwocz8h/nduHhw9
v1LHfZYfxGEj6mcjLi85jB2w3SI6/bjnrmvh+CYdyTdXYdTPt6QjClksb5ldCx0FnNUGO2reUvJN
al6i4JNtfcOY6wCodGZL/hRs6uE2rzkt9U1CTwRabnNwTwH0dSNmwwRpeRW/L3RXSOxt9ardRAtD
y09vSIiYUq1qKPgglQPEAQTYturevvoegniJWibIpSWEV2a/6Pxx33g8hWO9U/37oiCp42F5dhV/
+x1Y6GuqHCwQnAS5gG6uRYMvYjdk/4lq
`protect end_protected
|
-------------------------------------------------------------------------------
-- memory mapping package for pdi
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- package for memory mapping
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
package memMap is
type memoryMapping_t is
record
base : integer;
span : integer;
end record;
function align32 (inVal : integer) return integer;
end package memMap;
package body memMap is
function align32 (inVal : integer) return integer is
variable tmp : std_logic_vector(31 downto 0);
variable result : integer;
begin
tmp := (conv_std_logic_vector(inVal, tmp'length) + x"00000003") and not x"00000003";
result := conv_integer(tmp);
return result;
end function;
end package body memMap;
|
-------------------------------------------------------------------------------
-- memory mapping package for pdi
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- package for memory mapping
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
package memMap is
type memoryMapping_t is
record
base : integer;
span : integer;
end record;
function align32 (inVal : integer) return integer;
end package memMap;
package body memMap is
function align32 (inVal : integer) return integer is
variable tmp : std_logic_vector(31 downto 0);
variable result : integer;
begin
tmp := (conv_std_logic_vector(inVal, tmp'length) + x"00000003") and not x"00000003";
result := conv_integer(tmp);
return result;
end function;
end package body memMap;
|
library ieee;
use ieee.std_logic_1164.all;
entity mem_bank_tb is
end entity;
architecture test_bench of mem_bank_tb is
component mem_bank is
port(clk : in std_logic;
reset : in std_logic;
wr_en : in std_logic;
rd_en : in std_logic;
rd_ack : out std_logic;
addr : in std_logic_vector(15 downto 0);
wr_data : in std_logic_vector(31 downto 0);
rd_data : out std_logic_vector(31 downto 0));
end component;
signal tb_clk : std_logic := '0';
signal tb_reset : std_logic := '0';
signal tb_wr_en : std_logic := '0';
signal tb_rd_en : std_logic := '0';
signal tb_rd_ack : std_logic := '0';
signal tb_addr : std_logic_vector(15 downto 0) := (others => '0');
signal tb_wr_data : std_logic_vector(31 downto 0) := (others => '0');
signal tb_rd_data : std_logic_vector(31 downto 0) := (others => '0');
begin
tb_clk <= not tb_clk after 10 ns;
mem_bank_0: mem_bank port map(clk => tb_clk,
reset => tb_reset,
wr_en => tb_wr_en,
rd_en => tb_rd_en,
rd_ack => tb_rd_ack,
addr => tb_addr,
wr_data => tb_wr_data,
rd_data => tb_rd_data);
process
type pattern_type is record
--inputs
reset : std_logic;
wr_en : std_logic;
rd_en : std_logic;
addr : std_logic_vector(15 downto 0);
wr_data : std_logic_vector(31 downto 0);
--outputs
rd_ack : std_logic;
rd_data : std_logic_vector(31 downto 0);
end record;
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(('0', '1', '0', x"0000", x"aaaaaaaa", '0', x"00000000"),
('0', '1', '0', x"0001", x"bbbbbbbb", '0', x"00000000"),
('0', '1', '0', x"0002", x"cccccccc", '0', x"00000000"),
('0', '1', '0', x"0003", x"dddddddd", '0', x"00000000"),
('0', '1', '0', x"00e7", x"eeeeeeee", '0', x"00000000"),
('0', '0', '0', x"0000", x"00000000", '0', x"00000000"),
('0', '0', '1', x"0000", x"00000000", '0', x"00000000"),
('0', '0', '1', x"0001", x"00000000", '1', x"aaaaaaaa"),
('0', '0', '1', x"0002", x"00000000", '1', x"bbbbbbbb"),
('0', '0', '1', x"0003", x"00000000", '1', x"cccccccc"),
('0', '0', '1', x"00e7", x"00000000", '1', x"dddddddd"),
('0', '0', '0', x"0000", x"00000000", '1', x"eeeeeeee"),
('0', '0', '0', x"0000", x"00000000", '0', x"00000000"),
('1', '0', '0', x"0000", x"00000000", '0', x"00000000"),
('0', '0', '1', x"0000", x"00000000", '0', x"00000000"),
('0', '0', '1', x"0001", x"00000000", '1', x"01234567"),
('0', '0', '1', x"0002", x"00000000", '1', x"89abcde7"),
('0', '0', '1', x"0003", x"00000000", '1', x"0a0b0c0d"),
('0', '0', '1', x"00e7", x"00000000", '1', x"10203040"),
('0', '0', '0', x"0000", x"00000000", '1', x"deadbeef"),
('0', '0', '0', x"0000", x"00000000", '0', x"00000000"));
begin
assert false report "Start of test." severity note;
for i in patterns'range loop
wait until rising_edge(tb_clk);
tb_reset <= patterns(i).reset;
tb_wr_en <= patterns(i).wr_en;
tb_rd_en <= patterns(i).rd_en;
tb_addr <= patterns(i).addr;
tb_wr_data <= patterns(i).wr_data;
wait for 1 ns;
assert tb_rd_ack = patterns(i).rd_ack
report "Bad rd_ack value." severity error;
assert tb_rd_data = patterns(i).rd_data
report "Bad rd_data value." severity error;
end loop;
assert false report "End of test." severity note;
wait;
end process;
end test_bench; |
-- NEED RESULT: ARCH00428: Based literals passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00428
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 13.4.2 (1)
-- 13.4.2 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00428)
-- ENT00428_Test_Bench(ARCH00428_Test_Bench)
--
-- REVISION HISTORY:
--
-- 3-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00428 of E00000 is
begin
process
begin
test_report ( "ARCH00428" ,
"Based literals" ,
-- these test 13.4.2 (1) for integers
(16#aA# = 16*10+10) and
(16#bB# = 16*11+11) and
(16#cC# = 16*12+12) and
(16#dD# = 16*13+13) and
(16#eE# = 16*14+14) and
(16#fF# = 16*15+15) and
-- these test 13.4.2 (1) for reals
(16#aA.c# = 16.0*10.0+10.0+0.75) and
(16#bB.C# = 16.0*11.0+11.0+0.75) and
(16#cC.c# = 16.0*12.0+12.0+0.75) and
(16#dD.C# = 16.0*13.0+13.0+0.75) and
(16#eE.c# = 16.0*14.0+14.0+0.75) and
(16#fF.C# = 16.0*15.0+15.0+0.75) and
-- these test 13.4.2 (2)
(2#100# = 2**2) and
(3#100# = 3**2) and
(4#100# = 4**2) and
(5#100# = 5**2) and
(6#100# = 6**2) and
(7#100# = 7**2) and
(8#100# = 8**2) and
(9#100# = 9**2) and
(10#100# = 10**2) and
(11#100# = 11**2) and
(12#100# = 12**2) and
(13#100# = 13**2) and
(14#100# = 14**2) and
(15#100# = 15**2) and
(16#100# = 16**2)
) ;
wait ;
end process ;
end ARCH00428 ;
entity ENT00428_Test_Bench is
end ENT00428_Test_Bench ;
architecture ARCH00428_Test_Bench of ENT00428_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00428 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00428_Test_Bench ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.test_utils.all;
entity test_test_utils is
end test_test_utils;
architecture behavioural of test_test_utils is
begin
process
variable test_chr : character;
variable test_str : string(1 to 8);
begin
test_chr := '0';
assert sl2chr('0') = test_chr report "Mismatch" severity error;
test_chr := '1';
assert sl2chr('1') = test_chr report "Mismatch" severity error;
test_chr := 'X';
assert sl2chr('X') = test_chr report "Mismatch" severity error;
test_chr := 'U';
assert sl2chr('U') = test_chr report "Mismatch" severity error;
test_chr := 'H';
assert sl2chr('H') = test_chr report "Mismatch" severity error;
test_chr := 'L';
assert sl2chr('L') = test_chr report "Mismatch" severity error;
test_chr := 'Z';
assert sl2chr('Z') = test_chr report "Mismatch" severity error;
test_chr := '-';
assert sl2chr('-') = test_chr report "Mismatch" severity error;
-- Sanity check to make sure that I'm not just comparing chars (should not compile)
-- test_chr := 'Y';
-- assert sl2chr('Y') = test_chr report "Mismatch" severity error;
test_str := "01XUHLZ-";
assert slv2str("01XUHLZ-") = test_str report "Mismatch" severity error;
test_str := "01010101";
assert slv2str("01010101") = test_str report "Mismatch" severity error;
wait;
end process;
end behavioural;
|
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Implements a binary to one-hot decoder with enable signal.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity decoder is
generic (
SELBITS : positive := 2
);
port (
en : in std_logic;
sel : in std_logic_vector(SELBITS-1 downto 0);
hot : out std_logic_vector(2**SELBITS-1 downto 0)
);
end decoder;
architecture BHV of decoder is
begin
process(en, sel)
begin
hot <= (others => '0');
if(en = '1') then
hot(to_integer(unsigned(sel))) <= '1';
end if;
end process;
end BHV;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 08 17:41:52 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_processing_system7_0_0 -prefix
-- system_processing_system7_0_0_ system_processing_system7_0_0_sim_netlist.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "system_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end system_processing_system7_0_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_processing_system7_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_processing_system7_0_0 : entity is "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_processing_system7_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
end system_processing_system7_0_0;
architecture STRUCTURE of system_processing_system7_0_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "system_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.system_processing_system7_0_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
|
-- $Id: ibdr_lp11.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2009-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_lp11 - syn
-- Description: ibus dev(rem): LP11
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 12 35 0 24 s 5.6
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 11 30 0 19 s 5.8
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-24 1138 1.3.3 add csr.ir (intreq monitor)
-- 2019-03-10 1121 1.3.2 ignore buf write if csr.err=1 for lp11_buf compat
-- 2019-03-03 1118 1.3.1 VAL in bit 15 and 8 for lp11_buf compat
-- 2013-05-04 515 1.3 BUGFIX: r.err was cleared in racc read !
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-06-21 228 1.0.1 generate interrupt locally when err=1
-- 2009-05-30 220 1.0 Initial version
------------------------------------------------------------------------------
--
-- Notes:
-- - the ERR bit is just a status flag
-- - no hardware interlock (DONE forced 0 when ERR=1), like in simh
-- - also no interrupt when ERR goes 1, like in simh
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_lp11 is -- ibus dev(rem): LP11
-- fixed address: 177514
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibdr_lp11;
architecture syn of ibdr_lp11 is
constant ibaddr_lp11 : slv16 := slv(to_unsigned(8#177514#,16));
constant ibaddr_csr : slv1 := "0"; -- csr address offset
constant ibaddr_buf : slv1 := "1"; -- buf address offset
constant csr_ibf_err : integer := 15;
constant csr_ibf_done : integer := 7;
constant csr_ibf_ie : integer := 6;
constant csr_ibf_ir : integer := 5;
constant buf_ibf_val : integer := 15;
constant buf_ibf_val8: integer := 8;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
err : slbit; -- csr: error flag
done : slbit; -- csr: done flag
ie : slbit; -- csr: interrupt enable
buf : slv7; -- buf:
intreq : slbit; -- interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'1', -- err !! is set !!
'1', -- done !! is set !!
'0', -- ie
(others=>'0'), -- buf
'0' -- intreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.err <= N_REGS.err; -- don't reset ERR flag
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 2)=ibaddr_lp11(12 downto 2) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(1 downto 1) is
when ibaddr_csr => -- CSR -- control status -------------
idout(csr_ibf_err) := r.err;
idout(csr_ibf_done) := r.done;
idout(csr_ibf_ie) := r.ie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.ie := IB_MREQ.din(csr_ibf_ie);
if IB_MREQ.din(csr_ibf_ie) = '1' then
if r.done='1' and r.ie='0' then -- ie set while done=1
n.intreq := '1'; -- request interrupt
end if;
else
n.intreq := '0';
end if;
end if;
else -- rri ---------------------
idout(csr_ibf_ir) := r.intreq;
if ibw1 = '1' then
n.err := IB_MREQ.din(csr_ibf_err);
if IB_MREQ.din(csr_ibf_err) = '1' then
n.done := '1';
n.intreq := '0'; -- clear irupt (like simh!)
end if;
end if;
end if;
when ibaddr_buf => -- BUF -- data buffer ----------------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
if r.done = '1' then -- ignore buf write when done=0
n.buf := IB_MREQ.din(n.buf'range);
if r.err = '0' then -- if online (handle via rbus)
ilam := '1'; -- request attention
n.done := '0'; -- clear done
n.intreq := '0'; -- clear interrupt
else -- if offline (discard locally)
n.done := '1'; -- set done
if r.ie = '1' then -- if interrupts enabled
n.intreq := '1'; -- request interrupt
end if;
end if; -- r.err = '0'
end if; -- r.done = '1'
end if; -- ibw0 = '1'
else -- rri ---------------------
idout(r.buf'range) := r.buf;
idout(buf_ibf_val) := not r.done;
idout(buf_ibf_val8) := not r.done;
if ibrd = '1' then
n.done := '1';
if r.ie = '1' then
n.intreq := '1';
end if;
end if;
end if;
when others => null;
end case;
end if;
-- other state changes
if EI_ACK = '1' then
n.intreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ <= r.intreq;
end process proc_next;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
library src;
use src.bus_pkg.all;
entity bus_singleport_ram_tb is
generic (
runner_cfg : string);
end entity;
architecture tb of bus_singleport_ram_tb is
type mem_type is record
rst : std_logic;
mst2slv : bus_mst2slv_type;
slv2mst : bus_slv2mst_type;
done : boolean;
success : boolean;
end record;
constant MEM_TYPE_DEFAULT : mem_type := (
rst => '0',
mst2slv => BUS_MST2SLV_IDLE,
slv2mst => BUS_SLV2MST_IDLE,
done => false,
success => false
);
constant clk_period : time := 20 ns;
signal mem_256_byte_control : mem_type := MEM_TYPE_DEFAULT;
signal mem_32_byte_control : mem_type := MEM_TYPE_DEFAULT;
signal clk : std_logic := '0';
begin
clk <= not clk after (clk_period/2);
main : process
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("test_ack_low_at_start") then
wait for clk_period;
check_equal(mem_256_byte_control.slv2mst.ack, '0');
elsif run ("test_write_then_read") then
wait for clk_period;
mem_256_byte_control.mst2slv.address <= std_logic_vector(to_unsigned(16, bus_address_type'length));
mem_256_byte_control.mst2slv.writeData <= std_logic_vector(to_unsigned(14, bus_data_type'length));
mem_256_byte_control.mst2slv.writeEnable <= '1';
mem_256_byte_control.mst2slv.writeMask <= (others => '1');
wait until mem_256_byte_control.slv2mst.ack = '1';
mem_256_byte_control.mst2slv.writeEnable <= '0';
wait for 2*clk_period;
check_equal(mem_256_byte_control.slv2mst.ack, '0');
mem_256_byte_control.mst2slv.address <= std_logic_vector(to_unsigned(24, bus_address_type'length));
mem_256_byte_control.mst2slv.writeData <= std_logic_vector(to_unsigned(15, bus_data_type'length));
mem_256_byte_control.mst2slv.writeEnable <= '1';
wait until mem_256_byte_control.slv2mst.ack = '1';
mem_256_byte_control.mst2slv.writeEnable <= '0';
wait for 2*clk_period;
check_equal(mem_256_byte_control.slv2mst.ack, '0');
mem_256_byte_control.mst2slv.address <= std_logic_vector(to_unsigned(16, bus_address_type'length));
mem_256_byte_control.mst2slv.readEnable <= '1';
wait until mem_256_byte_control.slv2mst.ack = '1';
check_equal(to_integer(unsigned(mem_256_byte_control.slv2mst.readData)), 14);
mem_256_byte_control.mst2slv.readEnable <= '0';
wait for 2*clk_period;
check_equal(mem_256_byte_control.slv2mst.ack, '0');
mem_256_byte_control.mst2slv.address <= std_logic_vector(to_unsigned(16, bus_address_type'length));
mem_256_byte_control.mst2slv.writeData <= std_logic_vector(to_unsigned(20, bus_data_type'length));
mem_256_byte_control.mst2slv.writeEnable <= '1';
mem_256_byte_control.mst2slv.writeMask <= (others => '0');
wait until mem_256_byte_control.slv2mst.ack = '1';
mem_256_byte_control.mst2slv.writeEnable <= '0';
wait for 2*clk_period;
check_equal(mem_256_byte_control.slv2mst.ack, '0');
mem_256_byte_control.mst2slv.readEnable <= '1';
wait until mem_256_byte_control.slv2mst.ack = '1';
check_equal(14, to_integer(unsigned(mem_256_byte_control.slv2mst.readData)));
elsif run("Test address space mirroring") then
mem_32_byte_control.mst2slv.address <= std_logic_vector(to_unsigned(0, bus_address_type'length));
mem_32_byte_control.mst2slv.writeData <= std_logic_vector(to_unsigned(14, bus_data_type'length));
mem_32_byte_control.mst2slv.writeEnable <= '1';
mem_32_byte_control.mst2slv.writeMask <= (others => '1');
wait until mem_32_byte_control.slv2mst.ack = '1';
mem_32_byte_control.mst2slv.writeEnable <= '0';
wait for 2*clk_period;
check_equal(mem_32_byte_control.slv2mst.ack, '0');
mem_32_byte_control.mst2slv.address <= std_logic_vector(to_unsigned(32, bus_address_type'length));
mem_32_byte_control.mst2slv.readEnable <= '1';
wait until mem_32_byte_control.slv2mst.ack = '1';
check_equal(14, to_integer(unsigned(mem_32_byte_control.slv2mst.readData)));
mem_32_byte_control.mst2slv.readEnable <= '0';
wait for 2*clk_period;
check_equal(mem_32_byte_control.slv2mst.ack, '0');
end if;
end loop;
wait until rising_edge(clk) or falling_edge(clk);
test_runner_cleanup(runner);
wait;
end process;
test_runner_watchdog(runner, 10 ms);
mem_256_byte : entity src.bus_singleport_ram
generic map (
DEPTH_LOG2B => 8
)
port map (
rst => mem_256_byte_control.rst,
clk => clk,
mst2mem => mem_256_byte_control.mst2slv,
mem2mst => mem_256_byte_control.slv2mst
);
mem_32_byte : entity src.bus_singleport_ram
generic map (
DEPTH_LOG2B => 4
)
port map (
rst => mem_32_byte_control.rst,
clk => clk,
mst2mem => mem_32_byte_control.mst2slv,
mem2mst => mem_32_byte_control.slv2mst
);
end architecture;
|
------------------------------------------------------
------------------------------------------------------
-- Description: --
-- Implementation of a simple multiplier --
-- --
-- Generics: --
-- X_WIDTH - Width of the input x --
-- X_FRACTION - Width of the fractional part of x --
-- Y_WIDTH - Width of the input y --
-- Y_FRACTION - Width of the fractional part of y --
-- S_WIDTH - Desired width of the output s --
-- S_FRACTION - Desired width of the fractional --
-- part of s --
-- --
-- Input/Output: --
-- x - First factor --
-- y - Second factor --
-- s - Product --
-- --
------------------------------------------------------
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Multiplier is
generic (X_WIDTH : natural := 16;
X_FRACTION : natural := 14;
Y_WIDTH : natural := 16;
Y_FRACTION : natural := 14;
S_WIDTH : natural := 16;
S_FRACTION : natural := 13);
port(x : in std_logic_vector(X_WIDTH-1 downto 0);
y : in std_logic_vector(Y_WIDTH-1 downto 0);
s : out std_logic_vector(S_WIDTH-1 downto 0));
end Multiplier;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Multiplier is
-- Functions -----------------------------------------------------------------
function paddedLength(old_width : integer ;upper_limit : integer) return integer is
begin
if(upper_limit > old_width) then
return upper_limit;
else
return old_width;
end if;
end paddedLength;
-- Constants -----------------------------------------------------------------
constant UPPER_LIMIT : integer := X_FRACTION+Y_FRACTION-S_FRACTION+S_WIDTH-1;
constant LOWER_LIMIT : integer := X_FRACTION+Y_FRACTION-S_FRACTION;
constant X_LENGTH : integer := paddedLength(X_WIDTH, UPPER_LIMIT);
constant Y_LENGTH : integer := paddedLength(Y_WIDTH, UPPER_LIMIT);
-- Signals -------------------------------------------------------------------
signal x_padded : std_logic_vector(X_LENGTH-1 downto 0);
signal y_padded : std_logic_vector(Y_LENGTH-1 downto 0);
signal product : std_logic_vector(X_LENGTH + Y_LENGTH - 1 downto 0);
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
-- Fill upper bits if necessary
x_padder:
if(UPPER_LIMIT > X_WIDTH) generate
x_padded(UPPER_LIMIT-1 downto X_WIDTH) <= (others => x(X_WIDTH-1));
end generate x_padder;
y_padder:
if(UPPER_LIMIT > Y_WIDTH) generate
y_padded(UPPER_LIMIT-1 downto Y_WIDTH) <= (others => y(Y_WIDTH-1));
end generate y_padder;
-- Put the input onto the multiplier
x_padded(X_WIDTH-1 downto 0) <= x;
y_padded(Y_WIDTH-1 downto 0) <= y;
-- Multiply and cast result into appropriate size
product <= std_logic_vector(signed(x_padded) * signed(y_padded));
s <= product(UPPER_LIMIT downto LOWER_LIMIT);
end architecture; |
-------------------------------------------------------------------------------
-- Author: David Wolf, Leonhardt Schwarz
-- Project: FPGA Project
--
-- Copyright (C) 2014 David Wolf, Leonhardt Schwarz
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity debounce is
generic (
WIDTH : natural := 2;
DELAY : natural := 156);
port ( clk50 : in std_logic;
keyin_i : in std_logic_vector(WIDTH-1 downto 0);
keyout_o : out std_logic_vector(WIDTH-1 downto 0));
end debounce; |
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, type, subtype, case, enumerations, array, for-loop, Attributes-of-the-array-type-or-objects-of-the-array-type
use work.std_logic_1164_for_tst.all;
entity ENT00023_Test_Bench is
end ENT00023_Test_Bench;
architecture ARCH00023_Test_Bench of ENT00023_Test_Bench is
subtype byte is bit_vector(1 to 8);
type IntArray is array (natural range <>) of integer;
type std_array is array (0 to 3) of std_logic;
signal I_sa : std_array := "1010";
type enum is (a_v, b_v, c_v, d_v, e_v, f_v);
type BooleanVector is array (integer range <>) of boolean;
type StateType is (init, assign, analize, waiting);
signal state : StateType := init;
begin
process (state)
variable vv1 : IntArray(7 downto 0) := (others => 7);
variable bv : bit_vector(9 downto 2);
variable vv3, vv4, vv5, vv6, vv7, vv8, vv9, vv10, vv11 : IntArray(7 downto 0);
variable vv2 : IntArray(107 downto 100);
subtype IntArray8 is IntArray(1 to 8);
variable int : IntArray(1 to 35) := (others => 0);
variable r_1, r_2, r_3, r_4 : real;
variable bool : BooleanVector(1 to 12) := (others => false);
type EnumArray is array (integer range <>) of enum;
variable ea : EnumArray(1 to 4);
subtype EnumArray4 is EnumArray(2 to 5);
begin
case state is
when init =>
vv2 := (107 => 10, 100 => 0, others => 3);
bv := x"A0";
state <= assign;
when assign =>
state <= analize;
-- bit_vector
int(5) := bv'low;
int(6) := bv'high;
int(7) := bv'left;
int(8) := bv'right;
int(17) := bv'length;
bool(2) := not bv'ascending;
int(27) := byte'low;
int(28) := byte'high;
int(29) := byte'left;
int(30) := byte'right;
int(31) := byte'length;
bool(6) := byte'ascending;
-- boolean vector
int(9) := bool'low;
int(10) := bool'high;
int(11) := bool'left;
int(12) := bool'right;
int(18) := bool'length;
bool(1) := bool'ascending;
-- IntArray
int(1) := vv2'low;
int(2) := vv2'high;
int(3) := vv2'left;
int(4) := vv2'right;
int(19) := vv2'length;
bool(3) := not vv2'ascending;
bool(4) := IntArray8'ascending;
int(20) := IntArray8'length;
int(32) := IntArray8'low;
int(33) := IntArray8'high;
int(34) := IntArray8'left;
int(35) := IntArray8'right;
-- EnumArray
int(13) := ea'Low;
int(14) := ea'High;
int(15) := ea'Left;
int(16) := ea'Right;
int(21) := ea'length;
bool(5) := ea'Ascending;
int(22) := EnumArray4'Low;
int(23) := EnumArray4'High;
int(24) := EnumArray4'Left;
int(25) := EnumArray4'Right;
int(26) := EnumArray4'Length;
bool(7) := EnumArray4'Ascending;
-- range
l1: for i in I_sa'range loop
vv1(i) := i;
end loop l1;
l2: for i in IntArray8'range loop
vv3(i-1) := i-1;
end loop l2;
l3: for i in bv'range loop
vv4(i-2) := i-2;
end loop l3;
l4: for i in std_array'range loop
vv5(i) := i;
vv5(i+4) := i+4;
end loop l4;
l5: for i in EnumArray4'range loop
vv6(i-2) := i-2;
vv6(i-2+4) := i-2+4;
end loop l5;
-- reverse_range
l6: for i in I_sa'reverse_range loop
vv7(i) := i;
vv7(i+4) := i+4;
end loop l6;
l7: for i in IntArray8'reverse_range loop
vv8(i-1) := i-1;
end loop l7;
l8: for i in bv'reverse_range loop
vv9(i-2) := i-2;
end loop l8;
l9: for i in std_array'reverse_range loop
vv10(i) := i;
vv10(i+4) := i+4;
end loop l9;
l10: for i in EnumArray4'reverse_range loop
vv11(i-2) := i-2;
vv11(i-2+4) := i-2+4;
end loop l10;
when analize =>
state <= waiting;
-- bit_vector
assert int(5) /= 2
report "Attribute A'Low(0) worked with the object of the type Bit_Vector correctly"
severity NOTE;
assert int(5) = 2
report "Attribute A'Low(0) does not work with the object of the type Bit_Vector"
severity NOTE;
assert int(6) /= 9
report "Attribute A'High(0) worked with the object of the type Bit_Vector correctly"
severity NOTE;
assert int(6) = 9
report "Attribute A'High(0) does not work with the object of the type Bit_Vector"
severity NOTE;
assert int(7) /= 9
report "Attribute A'Left(0) worked with the object of the type Bit_Vector correctly"
severity NOTE;
assert int(7) = 9
report "Attribute A'Left(0) does not work with the object of the type Bit_Vector"
severity NOTE;
assert int(8) /= 2
report "Attribute A'Right(0) worked with the object of the type Bit_Vector correctly"
severity NOTE;
assert int(8) = 2
report "Attribute A'Right(0) does not work with the object of the type Bit_Vector"
severity NOTE;
assert int(17) /= 8
report "Attribute A'Length(0) worked with the object of the type Bit_Vector correctly"
severity NOTE;
assert int(17) = 8
report "Attribute A'Length(0) does not work with the object of the type Bit_Vector"
severity NOTE;
assert not bool(2)
report "Attribute A'Ascending(0) worked with the object of the type Bit_Vector correctly"
severity NOTE;
assert bool(2)
report "Attribute A'Ascending(0) does not work with the object of the type Bit_Vector"
severity NOTE;
assert int(27) /= 1
report "Attribute A'Low(0) worked with the boarded subtype of the type Bit_Vector correctly"
severity NOTE;
assert int(27) = 1
report "Attribute A'Low(0) does not work with the boarded subtype of the type Bit_Vector"
severity NOTE;
assert int(28) /= 8
report "Attribute A'High(0) worked with the boarded subtype of the type Bit_Vector correctly"
severity NOTE;
assert int(28) = 8
report "Attribute A'High(0) does not work with the boarded subtype of the type Bit_Vector"
severity NOTE;
assert int(29) /= 1
report "Attribute A'Left(0) worked with the boarded subtype of the type Bit_Vector correctly"
severity NOTE;
assert int(29) = 1
report "Attribute A'Left(0) does not work with the boarded subtype of the type Bit_Vector"
severity NOTE;
assert int(30) /= 8
report "Attribute A'Right(0) worked with the boarded subtype of the type Bit_Vector correctly"
severity NOTE;
assert int(30) = 8
report "Attribute A'Right(0) does not work with the boarded subtype of the type Bit_Vector"
severity NOTE;
assert int(31) /= 8
report "Attribute A'Length(0) worked with the boarded subtype of the type Bit_Vector correctly"
severity NOTE;
assert int(31) = 8
report "Attribute A'Length(0) does not work with the boarded subtype of the type Bit_Vector"
severity NOTE;
assert not bool(6)
report "Attribute A'Ascending(0) worked with the boarded subtype of the type Bit_Vector correctly"
severity NOTE;
assert bool(6)
report "Attribute A'Ascending(0) does not work with the boarded subtype of the type Bit_Vector"
severity NOTE;
-- boolean vector
assert int(9) /= 1
report "Attribute A'Low(0) worked with the object of the boarded type Boolean Array correctly"
severity NOTE;
assert int(9) = 1
report "Attribute A'Low(0) does not work with the object of the boarded type Boolean Array"
severity NOTE;
assert int(10) /= 16#C#
report "Attribute A'High(0) worked with the object of the boarded type Boolean Array correctly"
severity NOTE;
assert int(10) = 16#C#
report "Attribute A'High(0) does not work with the object of the boarded type Boolean Array"
severity NOTE;
assert int(11) /= 1
report "Attribute A'Left(0) worked with the object of the boarded type Boolean Array correctly"
severity NOTE;
assert int(11) = 1
report "Attribute A'Left(0) does not work with the object of the boarded type Boolean Array"
severity NOTE;
assert int(12) /= 16#C#
report "Attribute A'Right(0) worked with the object of the boarded type Boolean Array correctly"
severity NOTE;
assert int(12) = 16#C#
report "Attribute A'Right(0) does not work with the object of the boarded type Boolean Array"
severity NOTE;
assert int(18) /= 16#C#
report "Attribute A'Length(0) worked with the object of the boarded type Boolean Array correctly"
severity NOTE;
assert int(18) = 16#C#
report "Attribute A'Length(0) does not work with the object of the boarded type Boolean Array"
severity NOTE;
assert not bool(1)
report "Attribute A'Ascending(0) worked with the object of the boarded type Boolean Array correctly"
severity NOTE;
assert bool(1)
report "Attribute A'Ascending(0) does not work with the object of the boarded type Boolean Array"
severity NOTE;
-- IntArray
assert int(1) /= 100
report "Attribute A'Low(0) worked with the object of the boarded type Integer Array correctly"
severity NOTE;
assert int(1) = 100
report "Attribute A'Low(0) does not work with the object of the boarded type Integer Array"
severity NOTE;
assert int(2) /= 107
report "Attribute A'High(0) worked with the object of the boarded type Integer Array correctly"
severity NOTE;
assert int(2) = 107
report "Attribute A'High(0) does not work with the object of the boarded type Integer Array"
severity NOTE;
assert int(3) /= 107
report "Attribute A'Left(0) worked with the object of the boarded type Integer Array correctly"
severity NOTE;
assert int(3) = 107
report "Attribute A'Left(0) does not work with the object of the boarded type Integer Array"
severity NOTE;
assert int(4) /= 100
report "Attribute A'Right(0) worked with the object of the boarded type Integer Array correctly"
severity NOTE;
assert int(4) = 100
report "Attribute A'Right(0) does not work with the object of the boarded type Integer Array"
severity NOTE;
assert int(19) /= 8
report "Attribute A'Length(0) worked with the object of the boarded type Integer Array correctly"
severity NOTE;
assert int(19) = 8
report "Attribute A'Length(0) does not work with the object of the boarded type Integer Array"
severity NOTE;
assert not bool(3)
report "Attribute A'Ascending(0) worked with the object of the boarded type Integer Array correctly"
severity NOTE;
assert bool(3)
report "Attribute A'Ascending(0) does not work with the object of the type boarded type Integer Array"
severity NOTE;
assert int(32) /= 1
report "Attribute A'Low(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert int(32) = 1
report "Attribute A'Low(0) does not work with the boarded subtype Integer Array"
severity NOTE;
assert int(33) /= 8
report "Attribute A'High(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert int(33) = 8
report "Attribute A'High(0) does not work with the boarded subtype Integer Array"
severity NOTE;
assert int(34) /= 1
report "Attribute A'Left(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert int(34) = 1
report "Attribute A'Left(0) does not work with the boarded subtype Integer Array"
severity NOTE;
assert int(35) /= 8
report "Attribute A'Right(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert int(35) = 8
report "Attribute A'Right(0) does not work with the boarded subtype Integer Array"
severity NOTE;
assert int(20) /= 8
report "Attribute A'Length(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert int(20) = 8
report "Attribute A'Length(0) does not work with the boarded subtype Integer Array"
severity NOTE;
assert not bool(4)
report "Attribute A'Ascending(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert bool(4)
report "Attribute A'Ascending(0) does not work with the type boarded subtype Integer Array"
severity NOTE;
-- EnumArray
assert int(13) /= 1
report "Attribute A'Low(0) worked with the object of the boarded type Enum Array correctly"
severity NOTE;
assert int(13) = 1
report "Attribute A'Low(0) does not work with the object of the boarded type Enum Array"
severity NOTE;
assert int(14) /= 4
report "Attribute A'High(0) worked with the object of the boarded type Enum Array correctly"
severity NOTE;
assert int(14) = 4
report "Attribute A'High(0) does not work with the object of the boarded type Enum Array"
severity NOTE;
assert int(15) /= 1
report "Attribute A'Left(0) worked with the object of the boarded type Enum Array correctly"
severity NOTE;
assert int(15) = 1
report "Attribute A'Left(0) does not work with the object of the boarded type Enum Array"
severity NOTE;
assert int(16) /= 4
report "Attribute A'Right(0) worked with the object of the boarded type Enum Array correctly"
severity NOTE;
assert int(16) = 4
report "Attribute A'Right(0) does not work with the object of the boarded type Enum Array"
severity NOTE;
assert int(21) /= 4
report "Attribute A'Length(0) worked with the object of the boarded type Enum Array correctly"
severity NOTE;
assert int(21) = 4
report "Attribute A'Length(0) does not work with the object of the boarded type Enum Array"
severity NOTE;
assert not bool(5)
report "Attribute A'Ascending(0) worked with the object of the boarded type Enum Array correctly"
severity NOTE;
assert bool(5)
report "Attribute A'Ascending(0) does not work with the object of the type boarded type Enum Array"
severity NOTE;
assert int(22) /= 2
report "Attribute A'Low(0) worked with the boarded type Enum Array correctly"
severity NOTE;
assert int(22) = 2
report "Attribute A'Low(0) does not work with the boarded type Enum Array"
severity NOTE;
assert int(23) /= 5
report "Attribute A'High(0) worked with the boarded type Enum Array correctly"
severity NOTE;
assert int(23) = 5
report "Attribute A'High(0) does not work with the boarded type Enum Array"
severity NOTE;
assert int(24) /= 2
report "Attribute A'Left(0) worked with the boarded type Enum Array correctly"
severity NOTE;
assert int(24) = 2
report "Attribute A'Left(0) does not work with the boarded type Enum Array"
severity NOTE;
assert int(25) /= 5
report "Attribute A'Right(0) worked with the boarded type Enum Array correctly"
severity NOTE;
assert int(25) = 5
report "Attribute A'Right(0) does not work with the boarded type Enum Array"
severity NOTE;
assert int(26) /= 4
report "Attribute A'Length(0) worked with the boarded type Enum Array correctly"
severity NOTE;
assert int(26) = 4
report "Attribute A'Length(0) does not work with the boarded type Enum Array"
severity NOTE;
assert not bool(7)
report "Attribute A'Ascending(0) worked with the boarded type Enum Array correctly"
severity NOTE;
assert bool(7)
report "Attribute A'Ascending(0) does not work with the type boarded type Enum Array"
severity NOTE;
-- Range
-- obj of std_logic array
assert vv1 /= 7 & 7 & 7 & 7 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) worked with the object of the boarded type Std_logic Array correctly"
severity NOTE;
assert vv1 = 7 & 7 & 7 & 7 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) does not work with the object of the boarded type Std_logic Array"
severity NOTE;
-- Boarded Integer Array
assert vv3 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert vv3 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) does not work with the boarded subtype Integer Array"
severity NOTE;
-- obj of boarded bit_vector
assert vv4 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) worked with the object of the bit_vector correctly"
severity NOTE;
assert vv4 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) does not work with the object of the bit_vector"
severity NOTE;
-- boarded std_logic array
assert vv5 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) worked with the boarded type Std_logic Array correctly"
severity NOTE;
assert vv5 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) does not work with the boarded type Std_logic Array"
severity NOTE;
-- boarded enum array
assert vv6 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) worked with the boarded subtype Enumeration Array correctly"
severity NOTE;
assert vv6 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) does not work with the boarded subtype Enumeration Array"
severity NOTE;
-- Reverse_Range
-- obj of std_logic array
assert vv7 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) worked with the object of the boarded type Std_logic Array correctly"
severity NOTE;
assert vv7 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) does not work with the object of the boarded type Std_logic Array"
severity NOTE;
-- Boarded Integer Array
assert vv8 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert vv8 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) does not work with the boarded subtype Integer Array"
severity NOTE;
-- obj of boarded bit_vector
assert vv9 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) worked with the object of the bit_vector correctly"
severity NOTE;
assert vv9 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) does not work with the object of the bit_vector"
severity NOTE;
-- boarded std_logic array
assert vv10 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) worked with the boarded type Std_logic Array correctly"
severity NOTE;
assert vv10 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) does not work with the boarded type Std_logic Array"
severity NOTE;
-- boarded enum array
assert vv11 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) worked with the boarded subtype Enumeration Array correctly"
severity NOTE;
assert vv11 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) does not work with the boarded subtype Enumeration Array"
severity NOTE;
when waiting =>
null;
end case;
end process;
end ARCH00023_Test_Bench ; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: regfile_3p_l3
-- File: regfile_3p_l3.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: 3-port regfile implemented with two 2-port rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
library techmap;
use techmap.gencomp.all;
use grlib.stdlib.all;
entity regfile_3p_l3 is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
wrfst : integer := 0; numregs : integer := 64;
testen : integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of regfile_3p_l3 is
constant rfinfer : boolean := (regfile_3p_infer(tech) = 1);
signal wd1, wd2 : std_logic_vector((dbits -1 + 8) downto 0);
signal e1, e2 : std_logic_vector((dbits-1) downto 0);
signal we1, we2 : std_ulogic;
signal vcc, gnd : std_ulogic;
signal vgnd : std_logic_vector(dbits-1 downto 0);
signal write2, renable2 : std_ulogic;
begin
vcc <= '1'; gnd <= '0'; vgnd <= (others => '0');
we1 <= we
;
we2 <= we
;
s0 : if rfinfer generate
inf : regfile_3p generic map (0, abits, dbits, wrfst, numregs, testen, memtest_vlen)
port map ( wclk, waddr, wdata, we, rclk, raddr1, re1, rdata1, raddr2, re2, rdata2,
open, open, testin
);
end generate;
s1 : if not rfinfer generate
rhu : regfile_3p generic map (tech, abits, dbits, wrfst, numregs, testen, memtest_vlen)
port map ( wclk, waddr, wdata, we, rclk, raddr1, re1, rdata1, raddr2, re2, rdata2,
open, open, testin
);
end generate;
end;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
--signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
--signal reg5, reg5_next : std_logic_vector(0 to 31);
--signal reg6, reg6_next : std_logic_vector(0 to 31);
--signal reg7, reg7_next : std_logic_vector(0 to 31);
--signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
--retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
--reg5 <= reg5_next;
--reg6 <= reg6_next;
--reg7 <= reg7_next;
--reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
--retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
--reg5_next <= reg5;
--reg6_next <= reg6;
--reg7_next <= reg7;
--reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: mutex_init_stress_1
-- reg1 = numberOfTestsToComplete
-- reg2 = * numberOfTestsCompleted
-- reg3 = * completedMutex
-- reg4 = * mutex
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Read the value of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg1_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of completedMutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg3_next <= intrfc2thrd_value;
next_state <= STATE_6;
-- while( *(data->numberOfTestsCompleted) < *(data->numberOfTestsToComplete) )
when STATE_6 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- Do the comparision between completed and toBeCompleted
if ( intrfc2thrd_value < reg1 ) then
next_state <= STATE_8;
else
next_state <= FUNCTION_EXIT;
end if;
-- mutex = (hthread_mutex_t *) malloc( sizeof( hthread_mutex_t ) );
when STATE_8 =>
-- push 8B, the size of a hthread_mutex_t
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- call malloc
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_MALLOC;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_10;
next_state <= WAIT_STATE;
-- if ( mutex == NULL ) thread_exit_WITHERROR( NULL );
when STATE_10 =>
reg4_next <= intrfc2thrd_value;
case intrfc2thrd_value is
when x"00000000" =>
-- push null and call exit
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when others =>
next_state <= STATE_12;
end case;
when STATE_11 =>
-- Call exit with error
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT_ERROR;
thrd2intrfc_value <= Z32;
-- hthread_mutex_init( mutex, NULL );
when STATE_12 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
-- push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_14;
when STATE_14 =>
-- call MUTEX_INIT
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_15;
next_state <= WAIT_STATE;
-- hthread_mutex_lock( mutex );
when STATE_15 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
when STATE_16 =>
-- call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_27;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( mutex );
when STATE_27 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_28;
when STATE_28 =>
-- call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_17;
next_state <= WAIT_STATE;
-- hthread_mutex_destroy( mutex );
when STATE_17 =>
-- push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
-- call hthread_mutex_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_19;
next_state <= WAIT_STATE;
-- free( mutex );
when STATE_19 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_20;
when STATE_20 =>
-- call free
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_FREE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_21;
next_state <= WAIT_STATE;
-- hthread_mutex_lock( data->completedMutex );
when STATE_21 =>
-- push data->completedMutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_22;
when STATE_22 =>
-- call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_23;
next_state <= WAIT_STATE;
-- *( data->numberOfTestsCompleted) += 1;
when STATE_23 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_24;
when STATE_24 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= reg2;
thrd2intrfc_value <= intrfc2thrd_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_25;
-- hthread_mutex_unlock( data->completedMutex );
when STATE_25 =>
-- push data->completedMutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_26;
when STATE_26 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_TDM_FSM is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
SSE_TS_CTRL0 : in vl_logic;
FPGA_TRIGGER : in vl_logic;
TDM_CNT : out vl_logic_vector(2 downto 0);
APB_SLOT : out vl_logic
);
end F2DSS_SSE_TDM_FSM;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_TDM_FSM is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
SSE_TS_CTRL0 : in vl_logic;
FPGA_TRIGGER : in vl_logic;
TDM_CNT : out vl_logic_vector(2 downto 0);
APB_SLOT : out vl_logic
);
end F2DSS_SSE_TDM_FSM;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_TDM_FSM is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
SSE_TS_CTRL0 : in vl_logic;
FPGA_TRIGGER : in vl_logic;
TDM_CNT : out vl_logic_vector(2 downto 0);
APB_SLOT : out vl_logic
);
end F2DSS_SSE_TDM_FSM;
|
-- Altera Microperipheral Reference Design Version 0802
--**********************************************************************************************
--
-- System: A8251
-- Component: Test Bench Stimulus
--
-- File: tb_A8251.vhd
-- Function: Sequences character transmission
--
--
--Copyright © 2002 Altera Corporation. All rights reserved. Altera products are
--protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
--other intellectual property laws.
--This reference design file, and your use thereof, is subject to and governed by
--the terms and conditions of the applicable Altera Reference Design License Agreement.
--By using this reference design file, you indicate your acceptance of such terms and
--conditions between you and Altera Corporation. In the event that you do not agree with
--such terms and conditions, you may not use the reference design file. Please promptly
--destroy any copies you have made.
--This reference design file being provided on an "as-is" basis and as an accommodation
--and therefore all warranties, representations or guarantees of any kind
--(whether express, implied or statutory) including, without limitation, warranties of
--merchantability, non-infringement, or fitness for a particular purpose, are
--specifically disclaimed. By making this reference design file available, Altera
--expressly does not recommend, suggest or require that this reference design file be
--used in combination with any other product not provided by Altera.
--**********************************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY conversions;
USE conversions.conversions.all;
----------------------------
-- Entity Declaration
----------------------------
ENTITY a8251tb IS
--
-- 82C51A processor bus timing parameters taken from the Intel data sheet.
--
GENERIC
(
Tcy : TIME := 320 ns; -- System clock period (min)
Tar : TIME := 20 ns; -- Address stable before read (min)
Tra : TIME := 20 ns; -- Address hold time for read (min)
Trr : TIME := 130 ns; -- Read pulse width (min)
Trd : TIME := 100 ns; -- Data delay from read (max)
Tdf : TIME := 75 ns; -- Read strobe inactive to data float (max)
Trvr : TIME := 960 ns; -- Data read recovery time (min)
Taw : TIME := 20 ns; -- Address stable before write (min)
Twa : TIME := 20 ns; -- Address hold time for write (min)
Tww : TIME := 100 ns; -- Write width parameter (min)
Tdw : TIME := 100 ns; -- Data setup time for write (min)
Twd : TIME := 0 ns -- Data hold time for write (min)
);
PORT
(
-- Common signals
clk : OUT std_logic;
reset : OUT std_logic;
txd_to_rxd : IN std_logic;
rxd_to_txd : IN std_logic;
nDTR_to_nDSR : IN std_logic;
nDSR_to_nDTR : IN std_logic;
-- Signals for the Tx USART
tx_txrdy : IN std_logic;
tx_txempty : IN std_logic;
tx_rxrdy : IN std_logic;
tx_syn_brk : IN std_logic;
tx_nEN : IN std_logic;
tx_dout : IN std_logic_vector (7 DOWNTO 0);
tx_nWR : OUT std_logic;
tx_nRD : OUT std_logic;
tx_nCS : OUT std_logic;
tx_CnD : OUT std_logic;
tx_nRTS_to_nCTS : IN std_logic;
tx_ExtSyncD : OUT std_logic;
tx_nTxC : OUT std_logic;
tx_nRxC : OUT std_logic;
tx_din : OUT std_logic_vector (7 DOWNTO 0);
-- Signals for the Rx USART
rx_txrdy : IN std_logic;
rx_txempty : IN std_logic;
rx_rxrdy : IN std_logic;
rx_syn_brk : IN std_logic;
rx_nEN : IN std_logic;
rx_dout : IN std_logic_vector (7 DOWNTO 0);
rx_nWR : OUT std_logic;
rx_nRD : OUT std_logic;
rx_nCS : OUT std_logic;
rx_CnD : OUT std_logic;
rx_nRTS_to_nCTS : IN std_logic;
rx_ExtSyncD : OUT std_logic;
rx_nTxC : OUT std_logic;
rx_nRxC : OUT std_logic;
rx_din : OUT std_logic_vector (7 DOWNTO 0)
);
END a8251tb;
-----------------------------
-- Architecture Body
-----------------------------
ARCHITECTURE MainTest OF a8251tb IS
--
-- Enumerated test state dumped with vectors to make reading
-- waveforms easier.
--
TYPE test_state IS
(
initializing,
single_sync,
dual_sync,
async_16x,
Kofu_mode,
Fuchu_mode,
Collins_mode,
framing_error_mode,
parity_error_mode,
overrun_error_mode,
break_mode,
cts_mode
);
TYPE test_mode IS
(
sync_mode,
async_mode
);
SIGNAL clk_Stim : std_logic := '0';
SIGNAL reset_Stim : std_logic := '0';
SIGNAL nTxC_Stim : std_logic := '0';
SIGNAL nRxC_Stim : std_logic := '0';
SIGNAL tx_nWR_Stim : std_logic := '1';
SIGNAL tx_nRD_Stim : std_logic := '1';
SIGNAL tx_nCS_Stim : std_logic := '1';
SIGNAL tx_CnD_Stim : std_logic := '1';
SIGNAL tx_ExtSyncD_Stim : std_logic := '0';
SIGNAL rx_nWR_Stim : std_logic := '1';
SIGNAL rx_nRD_Stim : std_logic := '1';
SIGNAL rx_nCS_Stim : std_logic := '1';
SIGNAL rx_CnD_Stim : std_logic := '1';
SIGNAL rx_ExtSyncD_Stim : std_logic := '0';
SIGNAL rxc_per : TIME := 30 * tcy;
SIGNAL txc_per : TIME := 30 * tcy;
BEGIN
--
-- Concurrent signal assignments
--
clk <= clk_Stim;
reset <= reset_Stim;
tx_nWR <= tx_nWR_Stim;
tx_nRD <= tx_nRD_Stim;
tx_nCS <= tx_nCS_Stim;
tx_CnD <= tx_CnD_Stim;
tx_ExtSyncD <= tx_ExtSyncD_Stim;
tx_nTxC <= nTxC_Stim;
tx_nRxC <= nRxC_Stim;
rx_nWR <= rx_nWR_Stim;
rx_nRD <= rx_nRD_Stim;
rx_nCS <= rx_nCS_Stim;
rx_CnD <= rx_CnD_Stim;
rx_ExtSyncD <= rx_ExtSyncD_Stim;
rx_nTxC <= nRxC_Stim;
rx_nRxC <= nTxC_Stim;
--
-- Bus clock generation
--
clk_Stim <= '0' WHEN clk_Stim = 'U' ELSE
NOT clk_Stim AFTER Tcy/2;
--
-- Rx clock generation
--
Rx_clk_gen_proc : PROCESS
BEGIN
nRxC_Stim <= '0' AFTER rxc_per/2, '1' AFTER rxc_per;
WAIT FOR rxc_per;
END PROCESS;
--
-- Tx clock generation
--
Tx_clk_gen_proc : PROCESS
BEGIN
nTxC_Stim <= '0' AFTER txc_per/2, '1' AFTER txc_per;
WAIT FOR txc_per;
END PROCESS;
GeneralStimulus : PROCESS
VARIABLE current_test_state : test_state;
VARIABLE current_test_mode : test_mode;
-----------------------------------------------------------------------
--
-- Procedure to perform master reset
--
-----------------------------------------------------------------------
PROCEDURE MasterReset IS
BEGIN
reset_Stim <= '0';
WAIT FOR 6 * Tcy;
reset_Stim <= '1';
END MasterReset;
-----------------------------------------------------------------------
--
-- Procedure to write the MODE initialization words to the Tx USART
--
-----------------------------------------------------------------------
PROCEDURE WrTxMode ( mode : IN std_logic_vector(7 DOWNTO 0);
sync1 : IN std_logic_vector(7 DOWNTO 0);
sync2 : IN std_logic_vector(7 DOWNTO 0)
) IS
BEGIN
tx_CnD_Stim <= '1';
tx_nCS_Stim <= '0';
tx_din <= mode;
WAIT FOR Taw;
tx_nWR_Stim <= '0';
WAIT FOR Tww;
tx_nWR_Stim <= '1';
WAIT FOR Twa;
tx_nCS_Stim <= '1';
WAIT FOR 6 * Tcy;
IF (mode(1) = '0') AND (mode(0) = '0') AND (mode(6) = '0') THEN
tx_CnD_Stim <= '1';
tx_nCS_Stim <= '0';
tx_din <= sync1;
WAIT FOR Taw;
tx_nWR_Stim <= '0';
WAIT FOR Tww;
tx_nWR_Stim <= '1';
WAIT FOR Twa;
tx_nCS_Stim <= '1';
WAIT FOR 6 * Tcy;
END IF;
IF (mode(1) = '0') AND (mode(0) = '0') AND (mode(7) = '0') AND (mode(6) = '0') THEN
tx_CnD_Stim <= '1';
tx_nCS_Stim <= '0';
tx_din <= sync2;
WAIT FOR Taw;
tx_nWR_Stim <= '0';
WAIT FOR Tww;
tx_nWR_Stim <= '1';
WAIT FOR Twa;
tx_nCS_Stim <= '1';
END IF;
IF ( current_test_mode = async_mode ) THEN
WAIT FOR 8 * Tcy;
ELSE
WAIT FOR 18 * Tcy;
END IF;
END WrTxMode;
-----------------------------------------------------------------------
--
-- Procedure to write the MODE initialization words to the Rx USART
--
-----------------------------------------------------------------------
PROCEDURE WrRxMode ( mode : IN std_logic_vector(7 DOWNTO 0);
sync1 : IN std_logic_vector(7 DOWNTO 0);
sync2 : IN std_logic_vector(7 DOWNTO 0)
) IS
BEGIN
rx_CnD_Stim <= '1';
rx_nCS_Stim <= '0';
rx_din <= mode;
WAIT FOR Taw;
rx_nWR_Stim <= '0';
WAIT FOR Tww;
rx_nWR_Stim <= '1';
WAIT FOR Twa;
rx_nCS_Stim <= '1';
WAIT FOR 6 * Tcy;
IF (mode(1) = '0') AND (mode(0) = '0') AND (mode(6) = '0') THEN
rx_CnD_Stim <= '1';
rx_nCS_Stim <= '0';
rx_din <= sync1;
WAIT FOR Taw;
rx_nWR_Stim <= '0';
WAIT FOR Tww;
rx_nWR_Stim <= '1';
WAIT FOR Twa;
rx_nCS_Stim <= '1';
WAIT FOR 6 * Tcy;
END IF;
IF (mode(1) = '0') AND (mode(0) = '0') AND (mode(7) = '0') AND (mode(6) = '0') THEN
rx_CnD_Stim <= '1';
rx_nCS_Stim <= '0';
rx_din <= sync2;
WAIT FOR Taw;
rx_nWR_Stim <= '0';
WAIT FOR Tww;
rx_nWR_Stim <= '1';
WAIT FOR Twa;
rx_nCS_Stim <= '1';
END IF;
IF ( current_test_mode = async_mode ) THEN
WAIT FOR 8 * Tcy;
ELSE
WAIT FOR 18 * Tcy;
END IF;
END WrRxMode;
-----------------------------------------------------------------------
--
-- Define procedure to write Command Word to Tx USART
--
-----------------------------------------------------------------------
PROCEDURE WrTxCmd ( cmdwrd : IN std_logic_vector(7 DOWNTO 0) ) IS
BEGIN
tx_CnD_Stim <= '1';
tx_nCS_Stim <= '0';
tx_din <= cmdwrd;
WAIT FOR Taw;
tx_nWR_Stim <= '0';
WAIT FOR Tww;
tx_nWR_Stim <= '1';
WAIT FOR Twa;
tx_nCS_Stim <= '1';
IF ( current_test_mode = async_mode ) THEN
WAIT FOR 8 * Tcy;
ELSE
WAIT FOR 18 * Tcy;
END IF;
END WrTxCmd;
-----------------------------------------------------------------------
--
-- Define procedure to write Command Word to Rx USART
--
-----------------------------------------------------------------------
PROCEDURE WrRxCmd ( cmdwrd : IN std_logic_vector(7 DOWNTO 0) ) IS
BEGIN
rx_CnD_Stim <= '1';
rx_nCS_Stim <= '0';
rx_din <= cmdwrd;
WAIT FOR Taw;
rx_nWR_Stim <= '0';
WAIT FOR Tww;
rx_nWR_Stim <= '1';
WAIT FOR Twa;
rx_nCS_Stim <= '1';
WAIT FOR 6 * Tcy;
IF ( current_test_mode = async_mode ) THEN
WAIT FOR 8 * Tcy;
ELSE
WAIT FOR 18 * Tcy;
END IF;
END WrRxCmd;
-----------------------------------------------------------------------
--
-- Define procedure to write Transmit Data to the Tx USART
--
-----------------------------------------------------------------------
PROCEDURE WrTxTxD ( TxIn : IN std_logic_vector(7 DOWNTO 0) ) IS
BEGIN
tx_CnD_Stim <= '0';
tx_nCS_Stim <= '0';
tx_din <= TxIn;
WAIT FOR Taw;
tx_nWR_Stim <= '0';
WAIT FOR Tww;
tx_nWR_Stim <= '1';
WAIT FOR Twa;
tx_nCS_Stim <= '1';
WAIT FOR 6 * Tcy;
END WrTxTxD;
-----------------------------------------------------------------------
--
-- Define procedure to write Transmit Data to the Rx USART
--
-----------------------------------------------------------------------
PROCEDURE WrRxTxD ( TxIn : IN std_logic_vector(7 DOWNTO 0) ) IS
BEGIN
rx_CnD_Stim <= '0';
rx_nCS_Stim <= '0';
rx_din <= TxIn;
WAIT FOR Taw;
rx_nWR_Stim <= '0';
WAIT FOR Tww;
rx_nWR_Stim <= '1';
WAIT FOR Twa;
rx_nCS_Stim <= '1';
WAIT FOR 6 * Tcy;
END WrRxTxD;
-----------------------------------------------------------------------
--
-- Procedure to read the Status Register in the Tx USART and
-- check the data.
--
-----------------------------------------------------------------------
PROCEDURE CheckTxStat ( ExpectedData : IN std_logic_vector(7 DOWNTO 0) ) IS
VARIABLE ExpectDataString : STRING(1 TO 6);
VARIABLE GotDataString : STRING(1 TO 6);
VARIABLE TempData : std_logic_vector(7 DOWNTO 0);
BEGIN
tx_CnD_Stim <= '1';
tx_nCS_Stim <= '0';
WAIT FOR Tar;
tx_nRD_Stim <= '0';
WAIT FOR Trr;
TempData := tx_dout;
tx_nRD_Stim <= '1';
WAIT FOR Tra;
tx_nCS_Stim <= '1';
WAIT FOR Tra;
ExpectDataString := to_hex_str(ExpectedData, 6);
GotDataString := to_hex_str(TempData, 6);
ASSERT ( TempData = ExpectedData )
REPORT "*** Check Status Error on Tx USART *** Expected: " & ExpectDataString & " got: " & GotDataString SEVERITY ERROR;
END CheckTxStat;
-----------------------------------------------------------------------
--
-- Procedure to read the Status Register in the Rx USART and
-- check the data.
--
-----------------------------------------------------------------------
PROCEDURE CheckRxStat ( ExpectedData : IN std_logic_vector(7 DOWNTO 0) ) IS
VARIABLE ExpectDataString : STRING(1 TO 6);
VARIABLE GotDataString : STRING(1 TO 6);
VARIABLE TempData : std_logic_vector(7 DOWNTO 0);
BEGIN
rx_CnD_Stim <= '1';
rx_nCS_Stim <= '0';
WAIT FOR Tar;
rx_nRD_Stim <= '0';
WAIT FOR Trr;
TempData := rx_dout;
rx_nRD_Stim <= '1';
WAIT FOR Tra;
rx_nCS_Stim <= '1';
WAIT FOR Tra;
ExpectDataString := to_hex_str(ExpectedData, 6);
GotDataString := to_hex_str(TempData, 6);
ASSERT ( TempData = ExpectedData )
REPORT "*** Check Status Error on Rx USART *** Expected: " & ExpectDataString & " got: " & GotDataString SEVERITY ERROR;
END CheckRxStat;
-----------------------------------------------------------------------
--
-- Procedure to read the Rx Data Register in the Tx USART and
-- check the data.
--
-----------------------------------------------------------------------
PROCEDURE CheckTxRxd ( ExpectedData : IN std_logic_vector(7 DOWNTO 0) ) IS
VARIABLE ExpectDataString : STRING(1 TO 6);
VARIABLE GotDataString : STRING(1 TO 6);
VARIABLE TempData : std_logic_vector(7 DOWNTO 0);
BEGIN
tx_CnD_Stim <= '0';
tx_nCS_Stim <= '0';
WAIT FOR Tar;
tx_nRD_Stim <= '0';
WAIT FOR Trr;
TempData := tx_dout;
tx_nRD_Stim <= '1';
WAIT FOR Tra;
tx_nCS_Stim <= '1';
WAIT FOR Tra;
ExpectDataString := to_hex_str(ExpectedData, 6);
GotDataString := to_hex_str(TempData, 6);
ASSERT ( TempData = ExpectedData )
REPORT "*** Check Rx Data Error on Tx USART *** Expected: " & ExpectDataString & " got: " & GotDataString SEVERITY ERROR;
END CheckTxRxd;
-----------------------------------------------------------------------
--
-- Procedure to read the Rx Data Register in the Rx USART and
-- check the data.
--
-----------------------------------------------------------------------
PROCEDURE CheckRxRxd ( ExpectedData : IN std_logic_vector(7 DOWNTO 0) ) IS
VARIABLE ExpectDataString : STRING(1 TO 6);
VARIABLE GotDataString : STRING(1 TO 6);
VARIABLE TempData : std_logic_vector(7 DOWNTO 0);
BEGIN
rx_CnD_Stim <= '0';
rx_nCS_Stim <= '0';
WAIT FOR Tar;
rx_nRD_Stim <= '0';
WAIT FOR Trr;
TempData := rx_dout;
rx_nRD_Stim <= '1';
WAIT FOR Tra;
rx_nCS_Stim <= '1';
WAIT FOR Tra;
ExpectDataString := to_hex_str(ExpectedData, 6);
GotDataString := to_hex_str(TempData, 6);
ASSERT ( TempData = ExpectedData )
REPORT "*** Check Rx Data Error on Rx USART *** Expected: " & ExpectDataString & " got: " & GotDataString SEVERITY ERROR;
END CheckRxRxd;
-----------------------------------------------------------------------
--
-- Procedure to wait for N cycles of the Tx clock
--
-----------------------------------------------------------------------
PROCEDURE TxWait ( Cycles : natural ) IS
VARIABLE Count : natural;
BEGIN
WAIT FOR ( txc_per * Cycles );
-- Count := 0;
--
-- WAIT UNTIL ( nTxC_Stim = '1' ); -- The first partial clock
--
-- WHILE ( Count < Cycles ) LOOP
--
-- WAIT UNTIL ( nTxC_Stim = '1' );
--
-- Count := Count + 1;
--
-- END LOOP;
END TxWait;
-----------------------------------------------------------------------
--
-- Procedure to set period of the Tx clock
--
-----------------------------------------------------------------------
PROCEDURE TxClkSet ( Period : TIME ) IS
BEGIN
txc_per <= Period; -- Set the clock period
WAIT UNTIL ( nTxC_Stim = '1' ); -- Block till it takes effect
END TxClkSet;
-----------------------------------------------------------------------
--
-- Procedure to set period of the Rx clock
--
-----------------------------------------------------------------------
PROCEDURE RxClkSet ( Period : TIME ) IS
BEGIN
rxc_per <= Period; -- Set the clock period
WAIT UNTIL ( nRxC_Stim = '1' ); -- Block till it takes effect
END RxClkSet;
---------------------------------------------------------------
-- Main Test Program
---------------------------------------------------------------
BEGIN
ASSERT false REPORT "INITIALIZING" SEVERITY NOTE;
current_test_state := initializing;
current_test_mode := sync_mode;
MasterReset;
TxClkSet(30 * tcy);
RxClkSet(30 * tcy);
--
-- Perform the Intel recommended initialization sequence
-- for both the Tx and Rx USARTs.
--
WrTxMode ("00000000", "00000000", "00000000"); -- Initialize the mode
WrTxCmd ("01000000"); -- Write a reset command
WrRxMode ("00000000", "00000000", "00000000"); -- Initialize the mode
WrRxCmd ("01000000"); -- Write a reset command
--
-- Setup any mode to prepare for the I/O discrete test
-- that follows.
--
WrTxMode ("00000000", "00000000", "00000000"); -- Initialize the mode
WrRxMode ("00000000", "00000000", "00000000"); -- Initialize the mode
--
-- Check the abilty to manipulate DTR, DSR, and assert break.
--
WrTxCmd ("00000010");
TxWait(3);
IF ( nDTR_to_nDSR = '1' ) THEN ASSERT false REPORT "DTR CLEAR FAILED" SEVERITY NOTE; END IF;
WrTxCmd ("00000000");
TxWait(3);
IF ( nDTR_to_nDSR = '0' ) THEN ASSERT false REPORT "DTR SET FAILED" SEVERITY NOTE; END IF;
WrTxCmd ("00100000");
TxWait(3);
IF ( tx_nRTS_to_nCTS = '1' ) THEN ASSERT false REPORT "RTS CLEAR FAILED" SEVERITY NOTE; END IF;
WrTxCmd ("00000000");
TxWait(3);
IF ( tx_nRTS_to_nCTS = '0' ) THEN ASSERT false REPORT "RTS SET FAILED" SEVERITY NOTE; END IF;
--
-- Start synch mode, single sync character test using HDLC format.
--
-- Synchronous mode
-- 8 bit characters
-- No parity
-- Internal sync detection
-- Single sync character
-- Maximum Tx rate (64 Kbps)
-- Maximum Rx rate (64 Kbps)
--
ASSERT false REPORT "START SYNC MODE TEST - SINGLE SYNC CHARACTER" SEVERITY NOTE;
current_test_state := single_sync;
current_test_mode := sync_mode;
TxClkSet(15625 ns);
RxClkSet(15625 ns);
--
-- Init the Tx USART
--
WrTxCmd ("01000000"); -- Write a reset command
WrTxMode ("10001100", "01111110", "00000000"); -- Initialize the mode use an HDLC flag character for sync
WrTxCmd ("10100111"); -- Enter hunt mode
--
-- Init the Rx USART
--
WrRxCmd ("01000000"); -- Write a reset command
WrRxMode ("10001100", "01111110", "00000000"); -- Initialize the mode, use an HDLC flag character for sync
WrRxCmd ("10100111"); -- Enter hunt mode
TxWait(24); -- Wait for three character times, during this time the line
-- should be in a marking state.
IF ( tx_txrdy = '0' ) THEN -- Wait for tx_txrdy
WAIT UNTIL ( tx_txrdy = '1' );
END IF;
WrTxTxD ("01111110"); -- Send first character, a sync character
IF ( tx_txrdy = '0' ) THEN -- Wait for tx_txrdy
WAIT UNTIL ( tx_txrdy = '1' );
END IF;
WrTxTxD ("01010101"); -- Send a single character that requires no bit stuffing
IF ( rx_rxrdy = '0' ) THEN -- Wait for the Rx USART to receive it
WAIT UNTIL ( rx_rxrdy = '1' );
ELSE
WAIT UNTIL ( rx_rxrdy = '0' );
WAIT UNTIL ( rx_rxrdy = '1' );
END IF;
CheckRxStat ("10000111"); -- Check Status, there should be no errors and a character waiting
CheckRxRxd("01010101"); -- check the data
CheckRxStat ("10000101"); -- Check Status, the RXRDY bit should have been cleared
TxWait(24); -- Wait for three character times, during this time the
-- transmitter should be transmitting flag characters.
--
-- Start synch mode, dual sync character test
--
-- Synchronous mode
-- 8 bit characters
-- No parity
-- Internal sync detection
-- Two sync characters
-- Maximum Tx rate (64 Kbps)
-- Maximum Rx rate (64 Kbps)
--
ASSERT false REPORT "START SYNC MODE TEST - DUAL SYNC CHARACTER" SEVERITY NOTE;
current_test_state := dual_sync;
current_test_mode := sync_mode;
TxClkSet(15625 ns);
RxClkSet(15625 ns);
--
-- Init the Tx USART
--
WrTxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrTxMode ("00001100", "01100110", "10011001"); -- Initialize the mode, use a BISYNC sequence for sync
WrTxCmd ("10100111"); -- Enter hunt mode
--
-- Init the Rx USART
--
WrRxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrRxMode ("00001100", "01100110", "10011001"); -- Initialize the mode use a BISYNC sequence for sync
WrRxCmd ("10100111"); -- Enter hunt mode
TxWait(24); -- Wait for three character times, during this time the line
-- should be in a marking state.
IF ( tx_txrdy = '0' ) THEN -- Wait for tx_txrdy
WAIT UNTIL ( tx_txrdy = '1' );
END IF;
WrTxTxD ("01100110"); -- Send the first sync character
IF ( tx_txrdy = '0' ) THEN -- Wait for tx_txrdy
WAIT UNTIL ( tx_txrdy = '1' );
END IF;
WrTxTxD ("10011001"); -- Send the second sync character
IF ( tx_txrdy = '0' ) THEN -- Wait for tx_txrdy
WAIT UNTIL ( tx_txrdy = '1' );
END IF;
WrTxTxD ("10101010"); -- Send a single character
IF ( rx_rxrdy = '0' ) THEN -- Wait for the Rx USART to receive it
WAIT UNTIL ( rx_rxrdy = '1' );
ELSE
WAIT UNTIL ( rx_rxrdy = '0' );
WAIT UNTIL ( rx_rxrdy = '1' );
END IF;
CheckRxStat("10000111"); -- Check Status, there should be no errors and a character waiting
CheckRxRxd("10101010"); -- Check the data
CheckRxStat("10000101"); -- Check Status, the RXRDY bit should have been cleared
TxWait(24); -- Wait for three character times, during this time the
-- transmitter should be transmitting flag characters.
--
-- Start asynch mode, 16x clock test (NEC Kofu test)
--
-- Asynchronous mode
-- 8 bit characters
-- Even parity
-- 1 stop bit
-- 19.2 Kbps Tx rate
-- 19.2 Kbps Rx rate
--
ASSERT false REPORT "START ASYNC MODE TEST - 16X CLOCK, 8 BIT DATA, EVEN PARITY" SEVERITY NOTE;
current_test_state := Kofu_mode;
current_test_mode := async_mode;
TxClkSet(3255 ns);
RxClkSet(3255 ns);
--
-- Init the Tx USART
--
WrTxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrTxMode ("01111110", "00000000", "00000000"); -- Initialize the mode
WrTxCmd ("00100111"); -- Write a setup command
--
-- Init the Rx USART
--
WrRxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrRxMode ("01111110", "00000000", "00000000"); -- Initialize the mode
WrRxCmd ("00100111"); -- Enter hunt mode
TxWait(8); -- Wait for one character time, during this time the line
-- should be in a marking state.
IF ( tx_txrdy = '0' ) THEN -- Wait for tx_txrdy
WAIT UNTIL ( tx_txrdy = '1' );
END IF;
WrTxTxD ("10101010"); -- Send a single character
IF ( rx_rxrdy = '0' ) THEN -- Wait for the Rx USART to receive it
WAIT UNTIL ( rx_rxrdy = '1' );
ELSE
WAIT UNTIL ( rx_rxrdy = '0' );
WAIT UNTIL ( rx_rxrdy = '1' );
END IF;
CheckRxStat ("10000111"); -- Check Status, there should be no errors and a character waiting
CheckRxRxd("10101010"); -- Check the data
CheckRxStat ("10000101"); -- Check Status, the RXRDY bit should have been cleared
TxWait(8); -- Wait for one character time, during this time the
-- transmitter should be transmitting idle line state.
--
-- Start asynch mode, 16x clock test ( NEC Fuchu test )
--
-- Asynchronous mode
-- 8 bit characters
-- Odd parity
-- 1 stop bit
-- 200 bps Tx rate
-- 115 bps Rx rate
--
ASSERT false REPORT "START ASYNC MODE TEST - 16X CLOCK, 8 BIT DATA, ODD PARITY" SEVERITY NOTE;
current_test_state := Fuchu_mode;
current_test_mode := async_mode;
TxClkSet(8680 ns);
RxClkSet(8680 ns);
--
-- Init the Tx USART
--
WrTxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrTxMode ("01011110", "00000000", "00000000"); -- Initialize the mode
WrTxCmd ("00100111"); -- Write a setup command
--
-- Init the Rx USART
--
WrRxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrRxMode ("01011110", "00000000", "00000000"); -- Initialize the mode
WrRxCmd ("00100111"); -- Enter hunt mode
TxWait(8); -- Wait for one character time, during this time the line
-- should be in a marking state.
IF ( tx_txrdy = '0' ) THEN -- Wait for tx_txrdy
WAIT UNTIL ( tx_txrdy = '1' );
END IF;
WrTxTxD ("01010101"); -- Send a single character
IF ( rx_rxrdy = '0' ) THEN -- Wait for the Rx USART to receive it
WAIT UNTIL ( rx_rxrdy = '1' );
ELSE
WAIT UNTIL ( rx_rxrdy = '0' );
WAIT UNTIL ( rx_rxrdy = '1' );
END IF;
CheckRxStat ("10000111"); -- Check Status, there should be no errors and a character waiting
CheckRxRxd("01010101"); -- Check the data
CheckRxStat ("10000101"); -- Check Status, the RXRDY bit should have been cleared
TxWait(8); -- Wait for one character time, during this time the
-- transmitter should be transmitting idle line state.
--
-- Start asynch mode, 1x clock test ( Collins test )
--
-- Asynchronous mode
-- 8 bit characters
-- Even parity
-- 1 stop bit
-- 38.5 kbps Tx rate
-- 38.5 kbps Rx rate
--
ASSERT false REPORT "START ASYNC MODE TEST - 1X CLOCK, 8 BIT DATA, EVEN PARITY" SEVERITY NOTE;
current_test_state := Collins_mode;
current_test_mode := async_mode;
TxClkSet(26000 ns);
RxClkSet(26000 ns);
--
-- Init the Tx USART
--
WrTxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrTxMode ("01111101", "00000000", "00000000"); -- Initialize the mode
WrTxCmd ("00100111"); -- Write a setup command
--
-- Init the Rx USART
--
WrRxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrRxMode ("01111101", "00000000", "00000000"); -- Initialize the mode
WrRxCmd ("00100111"); -- Write a setup command
CheckTxStat ("10000101"); -- Check the state of the Status register
CheckTxRxd ("00000000"); -- Check the data
TxWait(1); -- Wait for one Tx clock time for the Rx UART
-- to complete configuration
IF ( tx_txrdy = '0' ) THEN -- Wait for tx_txrdy
WAIT UNTIL ( tx_txrdy = '1' );
END IF;
WrTxTxD ("01010101"); -- Send a single character
IF ( rx_rxrdy = '0' ) THEN -- Wait for the Rx USART to receive it
WAIT UNTIL ( rx_rxrdy = '1' );
ELSE
WAIT UNTIL ( rx_rxrdy = '0' );
WAIT UNTIL ( rx_rxrdy = '1' );
END IF;
CheckRxStat ("10000111"); -- Check Status, there should be no errors and a character waiting
CheckRxRxd("01010101"); -- Check the data
CheckRxStat ("10000101"); -- Check Status, the RXRDY bit should have been cleared
TxWait(8); -- Wait for one character time, during this time the
-- transmitter should be transmitting idle line state.
WrTxCmd ("00100101"); -- Write a command to take DTR high
TxWait(8); -- Wait for one character time to make sure that nothing
-- else happens.
--
-- Start Framing Error test
--
-- Tx USART Mode
-- Asynchronous mode
-- 8 bit characters
-- Odd parity
-- 1 stop bit
-- 38.5 kbps Tx rate
-- 38.5 kbps Rx rate
--
-- Rx USART Mode
-- Asynchronous mode
-- 6 bit characters
-- Odd parity
-- 1 stop bit
-- 38.5 kbps Tx rate
-- 38.5 kbps Rx rate
--
ASSERT false REPORT "START FRAMING ERROR TEST" SEVERITY NOTE;
current_test_state := framing_error_mode;
current_test_mode := async_mode;
TxClkSet(26000 ns);
RxClkSet(26000 ns);
--
-- Init the Tx USART
--
WrTxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrTxMode ("01011101", "00000000", "00000000"); -- Initialize the mode
WrTxCmd ("00100111"); -- Write a setup command
--
-- Init the Rx USART
--
WrRxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrRxMode ("01010101", "00000000", "00000000"); -- Initialize the mode
WrRxCmd ("00100111"); -- Write a setup command
CheckRxStat ("10000101"); -- Check Status, there should be no errors
CheckRxRxd ("00000000"); -- Check for data, it should be zero
TxWait(1); -- Wait for one Tx clock time for the Rx UART
-- to complete configuration
IF ( tx_txrdy = '0' ) THEN -- Wait for tx_txrdy
WAIT UNTIL ( tx_txrdy = '1' );
END IF;
WrTxTxD ("00000001"); -- Send a single character to generate a framing error
IF ( rx_rxrdy = '0' ) THEN -- Wait for the Rx USART to receive it
WAIT UNTIL ( rx_rxrdy = '1' );
ELSE
WAIT UNTIL ( rx_rxrdy = '0' );
WAIT UNTIL ( rx_rxrdy = '1' );
END IF;
CheckRxStat ("10100111"); -- Check Status, there should be a framing error only
CheckRxRxd ("00000001"); -- Check for data
WrRxCmd ("00110111"); -- Clear the framing error
CheckRxStat ("10000101"); -- Check Status, the framing error should have cleared
TxWait(8); -- Wait for one character time to let the receiver to
-- recover.
--
-- Start Parity Error test
--
-- Tx USART Mode
-- Asynchronous mode
-- 8 bit characters
-- Even parity
-- 1 stop bit
-- 38.5 kbps Tx rate
-- 38.5 kbps Rx rate
--
-- Rx USART Mode
-- Asynchronous mode
-- 6 bit characters
-- Odd parity
-- 1 stop bit
-- 38.5 kbps Tx rate
-- 38.5 kbps Rx rate
--
ASSERT false REPORT "START PARITY ERROR TEST" SEVERITY NOTE;
current_test_state := parity_error_mode;
current_test_mode := async_mode;
TxClkSet(26000 ns);
RxClkSet(26000 ns);
--
-- Init the Tx USART
--
WrTxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrTxMode ("01111101", "00000000", "00000000"); -- Initialize the mode
WrTxCmd ("00100111"); -- Write a setup command
--
-- Init the Rx USART
--
WrRxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrRxMode ("01010101", "00000000", "00000000"); -- Initialize the mode
WrRxCmd ("00100111"); -- Write a setup command
CheckRxStat ("10000101"); -- Check Status, there should be no errors
CheckRxRxd ("00000000"); -- Check for data, it should be zero
TxWait(1); -- Wait for one Tx clock time for the Rx UART
-- to complete configuration
IF ( tx_txrdy = '0' ) THEN -- Wait for tx_txrdy
WAIT UNTIL ( tx_txrdy = '1' );
END IF;
WrTxTxD ("11000001"); -- Send a single character to generate a parity error
IF ( rx_rxrdy = '0' ) THEN -- Wait for the Rx USART to receive it
WAIT UNTIL ( rx_rxrdy = '1' );
ELSE
WAIT UNTIL ( rx_rxrdy = '0' );
WAIT UNTIL ( rx_rxrdy = '1' );
END IF;
CheckRxStat ("10001111"); -- Check Status, there should be a parity error only
CheckRxRxd ("00000001"); -- Check for data
WrRxCmd ("00110111"); -- Clear the parity error
CheckRxStat ("10000101"); -- Check Status, the parity error should have cleared
TxWait(8); -- Wait for two clock times to let the transmitter finish
--
-- Start Overrun Error test
--
-- Asynchronous mode
-- 8 bit characters
-- Even parity
-- 1 stop bit
-- 38.5 kbps Tx rate
-- 38.5 kbps Rx rate
--
ASSERT false REPORT "START OVERRUN ERROR TEST" SEVERITY NOTE;
current_test_state := overrun_error_mode;
current_test_mode := async_mode;
TxClkSet(26000 ns);
RxClkSet(26000 ns);
--
-- Init the Tx USART
--
WrTxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrTxMode ("01111101", "00000000", "00000000"); -- Initialize the mode
WrTxCmd ("00100111"); -- Write a setup command
--
-- Init the Rx USART
--
WrRxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrRxMode ("01111101", "00000000", "00000000"); -- Initialize the mode
WrRxCmd ("00100111"); -- Write a setup command
CheckTxStat ("10000101"); -- Check the state of the Status register
CheckTxRxd ("00000000"); -- Check the data
TxWait(1); -- Wait for one Tx clock time for the Rx UART
-- to complete configuration
IF ( tx_txrdy = '0' ) THEN -- Wait for tx_txrdy
WAIT UNTIL ( tx_txrdy = '1' );
END IF;
WrTxTxD ("10101010"); -- Send the first character
IF ( rx_rxrdy = '0' ) THEN -- Wait for the Rx USART to receive it
WAIT UNTIL ( rx_rxrdy = '1' );
ELSE
WAIT UNTIL ( rx_rxrdy = '0' );
WAIT UNTIL ( rx_rxrdy = '1' );
END IF;
CheckRxStat ("10000111"); -- Check Status, there should be a character ready and no errors
IF ( tx_txrdy = '0' ) THEN -- Wait for tx_txrdy
WAIT UNTIL ( tx_txrdy = '1' );
END IF;
WrTxTxD ("01010101"); -- Send the second character
TxWait(12); -- Wait for one start bit time + character time
-- + parity bit time + one stop bit time + one bit time
-- since we can't use RXRDY as a reference.
CheckRxStat ("10010111"); -- Check Status, there should be a character ready and an
-- overrun error
CheckRxRxd ("01010101"); -- Check for data, it should be the second character
WrRxCmd ("00110111"); -- Clear the overrun error
CheckRxStat ("10000101"); -- Check Status, the overrun error should have cleared
--
-- Start break test
--
-- Asynchronous mode
-- 8 bit characters
-- Even parity
-- 1 stop bit
-- 38.5 kbps Tx rate
-- 38.5 kbps Rx rate
--
ASSERT false REPORT "START BREAK TEST" SEVERITY NOTE;
current_test_state := break_mode;
current_test_mode := async_mode;
TxClkSet(26000 ns);
RxClkSet(26000 ns);
--
-- Init the Tx USART
--
WrTxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrTxMode ("01111101", "00000000", "00000000"); -- Initialize the mode
WrTxCmd ("00100111"); -- Write a setup command
--
-- Init the Rx USART
--
WrRxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrRxMode ("01111101", "00000000", "00000000"); -- Initialize the mode
WrRxCmd ("00100111"); -- Write a setup command
CheckRxStat ("10000101"); -- Check the state of the Status register
CheckTxRxd ("00000000"); -- Check the data
TxWait(1); -- Wait for one Tx clock time for the Rx UART
-- to complete configuration
WAIT UNTIL ( nTxC_Stim = '1' ); -- Wait for the falling edge of Tx clock
WAIT UNTIL ( nTxC_Stim = '0' );
WrTxCmd ("00101111"); -- Assert a line break
TxWait(10); -- Wait for 10 Tx bit times:
-- (8 data bit + 1 start bit + 1 parity bit)
CheckRxStat ("10000101"); -- Check the state of the Status register, the
-- overrun error bit should be set
TxWait(11); -- Wait for 11 Tx bit times:
-- (8 data bit + 1 start bit + 1 parity bit) + 1 stop bit
IF ( rx_syn_brk = '0' ) THEN -- Check to make sure that the break was detected
ASSERT false REPORT "*** Line break not detected by Rx USART ***" SEVERITY ERROR;
END IF;
TxWait(4); -- Wait for a character time to make sure that everything
-- has settled.
WrTxCmd ("00100111"); -- Clear the line break
TxWait(1); -- Wait for a character time to make sure that everything
IF ( rx_syn_brk = '1' ) THEN -- Check to make sure that the break was cleared
ASSERT false REPORT "*** Line break indication not cleared by Rx USART ***" SEVERITY ERROR;
END IF;
TxWait(4); -- Wait for a character time to make sure that everything
WrRxCmd ("00110111"); -- Clear the overrun error
CheckRxStat ("10000101"); -- Check Status, the overrun error should have cleared
--
-- Start CTS flow control test
--
-- Asynchronous mode
-- 8 bit characters
-- Even parity
-- 1 stop bit
-- 38.5 kbps Tx rate
-- 38.5 kbps Rx rate
--
ASSERT false REPORT "START CTS FLOW CONTROL TEST" SEVERITY NOTE;
current_test_state := cts_mode;
current_test_mode := async_mode;
TxClkSet(26000 ns);
RxClkSet(26000 ns);
--
-- Init the Tx USART
--
WrTxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrTxMode ("01111101", "00000000", "00000000"); -- Initialize the mode
WrTxCmd ("00000111"); -- Write a setup command, turn off CTS by turning
-- the looped back RTS
--
-- Init the Rx USART
--
WrRxCmd ("01010000"); -- Write a reset command, clear any errors from the last test
WrRxMode ("01111101", "00000000", "00000000"); -- Initialize the mode
WrRxCmd ("00100111"); -- Write a setup command
CheckRxStat ("10000101"); -- Check the state of the Status register
TxWait(1); -- Wait for one Tx clock time for the Rx UART
-- to complete configuration
WAIT UNTIL ( nTxC_Stim = '1' ); -- Wait for the falling edge of Tx clock
WAIT UNTIL ( nTxC_Stim = '0' );
WrTxTxD ("10101010"); -- Load the first character
TxWait(12); -- Wait for one character time
CheckRxStat ("10000101"); -- Check Status, there should be nothing in the Rx buffer
WrTxCmd ("00100111"); -- Turn on CTS
TxWait(2); -- Wait for two Tx clock times to enable transmission
WrTxCmd ("00000111"); -- Turn off CTS
TxWait(12); -- Wait for one character time
WrTxTxD ("01010101"); -- Load the second character, but CTS is not asserted
-- and transmission should not start.
IF ( rx_rxrdy = '0' ) THEN -- Wait for the Rx USART to receive it
WAIT UNTIL ( rx_rxrdy = '1' );
END IF;
CheckRxStat ("10000111"); -- Check Status, there should be a character ready and no errors
CheckRxRxd ("10101010"); -- Check for data, it should be the first character
TxWait(12); -- Wait for one character time
CheckRxStat ("10000101"); -- Check Status, there should be nothing in the Rx buffer
WrTxCmd ("00100111"); -- Now turn on CTS to enable transmission of the second character
IF ( rx_rxrdy = '0' ) THEN -- Wait for the Rx USART to receive it
WAIT UNTIL ( rx_rxrdy = '1' );
END IF;
CheckRxStat ("10000111"); -- Check Status, there should be a character ready and no errors
CheckRxRxd ("01010101"); -- Check for data, it should be the first character
ASSERT false REPORT "TEST COMPLETE" SEVERITY NOTE;
WAIT;
END PROCESS;
END MainTest; |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
rKWwB0sGGUajpurVPwhHzgsZATzg6CI2fy5teGZgwWn6RJSxvVrm7X6KC1NlYW5YtUDp2ese/Vrm
bw3OqIV60Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
BRuqFpGYGOGwcHOC9ByqxsqWUs+0okjDxEXI9LjsXxEyuWJLFUE7YYzNDASAihgXdiZINIm5es9z
yyLJWg7azDkuzQk8G9FmmXCb4GMcSNpaTGa1FVepRSL9Yvq1uMN0rfkU8OoTCb0JTco3mn42K2KI
S1jw6CGiZKnXjxgHNBU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
X3xfyzvjrmPkaI9JdFIRWVWKvQVaKvW3xkPmxmWB+Bg2oVsfAsBqh2i46hM/Bcj4vTlgRohMAtTw
mZrr7U78E4bYF8iEtFKLdIJEd7hVOOlmDwsFBDzxg0k47kX9A3ruJ30LrjKdxboHAuMIaT/XR/sU
upe6flMZr8VBlv8re7jyziDyWZOLqFpjufskTfv4OQj1KszofT4kUnArUhuQ6UVlh5i6v/pQEzIn
QBP9XWEv/eQfQZl33K/QbbRAZIttPtuWp1T04bWkTuCPPKG+pDFGGGHJZvQDtAaxZSkHqZAvfqlI
CAW2rOiYEadE7tUwZCBmG03wqqm+cZJmCFoaew==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
AUXv88ADQriH8V/F9F2bxLErHxhqOWkmnlCs9b253d+OgRvIOLCtaWRA9DjnqkOKIf1wnvs/R6pY
dJJExfXVZOjD4nIH7uFh77R1TOSQouJzgmqD+K5HYb0maU6PAGIafeBzcUv5XN4HOOPvm67+oI2c
ikEGUjjanBNxts7eGBk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UZCooc8nZi2nNWJ83Gcm6qAONngeeaBUnqNHZdi1nOU1iRX6MguqeK1oMSUjP/9bRjlw7Tp3sNmB
PWJn2GGi3l8Qe6b7auDrjGMr0IkAvVTyrVlPQlMaseSN4e4IeWhVyNWjm//n/TOKlr4NMKKu7xlw
UYk+ejL3Bl9bd8/cGgsVR5ZkQQavRAFBo8L2IT7ML5f1IYG78bF0KQzrmL9GYFMnToP9B7kVR7Du
Yb7rcfK2Zazdh5MpYg9XUjLic80aZcb4+8dYBu7XgEp/Ar3GApiNMnYJUmVK0q0n9Er1Tqahdfht
jdB1SKLd/YF5uaRclGtmIoZjAK3M+1SEWOps9w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12224)
`protect data_block
t5Spk6yve3uJ1YJ8JkRzUVqRYSeuRX7hvbRJ802Wf+RbaumUpGUGs1znFzR00sTUqUlo2CM6n9t5
idaQheZ7CEySEBoOnXCDFAPgPh8ykyAiFL3Y6sdSpbifGT0J/JOeKzMD5+nIp6kLlUBQc7VQSeug
M59+p40cD2Inb5oFM8hep8qN/6JeN/AvWyjNarzBXpsddtlR8UubbsDzFOoHP85gMfreqfxKQ4mV
L7Rk+vSOBcAjasibJdt8lGIhGi/lyefdAUQVTAcr6Rk65rUmtv0s/zold4FRI0PmGoGxfBownUjt
ID3OGTorR57ZiwQS9SYT/JxWJc4zudrYR4fD8DMzWdvENN1xnOhzMhMHt+838ogv5ctRUr1L6p2O
rtwRmv3wR/GKlGn8ybNwInmjtK4+BNX5gap6mk0YnCG4mJTIiP+FaOoM8wdxiYOIdNIw+rUEBT/r
F6GFBxG8/5onUxfWtczQimgRffRR0v7VnhSMzy2cgMSC7RSfU5tBTVhvUjiZIwBwd4dh59wwMbhe
ObgOq2fTje9tphNoAT3WxoQOthjG8xxXRsX5sR0k7TcuvWX4nQV9WbYTs0pleUmspnq1k9Xs0EIm
W3y6b9BoMzHXGL1IE8hJYlJd5MJzzouUlPN9Tfwh1wrNpCDlmJ9J4GDclsOU/CZjQsWM5EUzV+OH
J1jcgKJeqyL3hOLIX9Dzt78ChPYHG1qg0Mb4qDP88S3pODWbW4+1j2AsD7uCWlZNEuMljxUnEhE8
FIE3ZCbePEIUPc2Pf6/43pOUbTiGDWhWlgErsC5o1dI6noSg0LkHfdLy18FHnFWX9F4Ot9xbxQNo
Gz2CBeKdYc1PWDPlJvrALuh5AkKAz0HEA+nOrvYQQikIUnTo+jrneOXHX5udeFGKOGj7cGhNtvlf
Tf9HT1+I7uysbP5f9/Vy2tM5W9ioHXzlY1KX/AAIXi1jyj61mytFLzgfuX9qQ+d7eZQg975Qw7wv
2K3Rs5rSBCYTDlyZff8DwG1W75SxZa5ZEUnq2iIUAu/K7a57rlg+CagNL7UfcqLTet7lwWRb/36V
iakB2GyZPEZWgje1bPPgQp1xBoLyGizRUM+wS3Vvf5n/3MMSjth8mQJeFKioXxqm4h/cJw3QGSI5
UQpah2uMGNMkL9oOvnJ9B2m+nLKg7VNIXBGxIYAXGhvdZkHt4VLzwYGcaGFdZa3OnS5gjN4TMRly
fi6w4xlKfDC7FwkEBAFjRxbHczk1q4nNDzpStSec9d5uCH3awkL3L0IMNdShksbCWmv3wwEFhjOk
SjVTEdwHmcA4oi4aoPvyiGDR1JKY7w7HjpuqE4+zIGGQkcoOyvj2XQx7JThEuPl9ECrZb0TLBBDK
bVRSzEy8HMp850gBd9iZCkVAHfMngslcOITnvHBJ4tFmHTwKWmxUxCJQ5gg89B07OGUhV1Q+z1jG
me/hXjX9OUPElTDa6TrxMsw/u+OojNDTVFA8X+D6laQ40t9oXuk0KBLM2bdF8iNGxHL65Vp8l+38
RPifxux3QEZQW22MVYOiHY8Wpkxi8t6CP0qQwMYn4yC9yAAZYdFyCJ6i3Q7BwXQezdhvpEyEH15s
EawpqFjDMh1gp/QeoJc4eMiWdTRlR1MRpchkVSM2AIbdntg04ShmJIDrsoseAyfot2a/M6/3k8tg
2ekGAX86Z6p21WYEj+pBaBr9yiAyMfxzQeEGFIJli9AMB58eQJwXewlkB3BRp3bxqFeUuHdgBK08
HNzvjIpo+x+asZypiv1UG9P5yt8EJCVQLd55M77zucbLyq+9Tm15/ZrpMQiVQKtWwhGEFM/LdLsD
eOpGAo58unYogZ9jd61lpWzXjfk8K+1Gk5Rtj6GiuxaIOC+4AaBRjHtq2rot5XeTUEeXKPOc0iP0
SSJvQlTRnUtPLT2oWk+FaRwo8kG0Z5pnY93pyvl/GJkDHomt7zBb6Ii1YEesPyGd/DOWVShIC5UX
YzP2NsqRNU/flC/VJIvO3TqEyLi3DOxbzo6CBBOz9FGAO+JU3c83f8ReokkGQPChk8pO3LTeWZWT
N299EgGOEzhgB8EVBttsR06SQ7mnQqWKhInWrSCz4sn0qPhjTXfnqKWeZy7BreuOIoOviLrS2NYv
qHuYuMcnxnEf8jkB7HR8qx9yRwaWV8iOoG/QMCWt4RGLL1zZVYvwqeoH9FZQDcjLp20a2sQPRWdH
ExiZ7RXUn4f4MvIjQz6vuGqqNnt/+6HHpYhvRcdyUJEpPCA8bTQGvTxcnlso7/c2NLzXIkC9bgXV
bu4/DPLvHs+sCT/c+PFX+DLLQfSNW6ccbS+XSkti77jxD1xeot+dVvpsvxYrNQACiL+tF75evtLy
eXfXPlETyJlEj0SAF1sg4n7F3axNpo6T7h6LkFUgPwXJ/luGCQCV4nC5SOWYh3ks3wVCist/63ob
oQyj9LmJHDz+TypWnwqEufwnUMbf1155GsRyTcDwcN7eH9FBtO2WaPfmGqugOND3SNl6xuddm0fZ
+fMZB8vXcCRf8Me93X+hqMDcuRWzEbD2WeWDqxY9Y44XuBb0Up+0jn6fsrzjQe0nIBXyPCbHO+1Q
65qYy1YXZk4xb5PKb2dKUTNL3l/uJMwRE4tiru1XLfdfgL/7DoDwRJOd5ZwH9kNmhrWbppH0RGJh
woO1qE83rK4VGj+iTeY1etxKSiMPCKYxrvkms+cdDGsYrYgG+xgsoJULJ5Lb6/B7Afxz2WGj1Wa2
w3zzV/agOpG2Tg0NYHpZAH3t5JbIg/LnzvjV8hfqflx3ISnyqkJls6/SOPLLpR79KSDBtD4PILne
AO8cxuO7eV4kXFbQLFbjQkvHi4t+WnQ+TDOxbKGEalVYXrfGmtVx6q9+WO82B4ybbv4A5/9VwSE2
TeRlzDFUY/7qTqweXCi77Zd35i2f+CR2tEn/qOoVM1/YqhzbnfdGZqk/H93gSFcfd5mI9BgQSlOp
EiB9pUOxjJb6VS5Yw1w/DJHyiMXvwtOXbjIQf6y6EYqO9eCnONXjRZDmhEHFKDaUCKZSj0PXwQZn
48YTWU477JtQIEfRJcvsjN3QOuywTXiOsoEQcVLv9k8AUenCU0i8flflczz4ws+fohE8ZUpaTAd/
+hmCtlS34dUNMi/ySWLj9TEdh5E++trzjKG0bRS/jq6LXg3QgnKsCeHm3xkqdanznPzMUEpq4Plc
p4lxpMo1ej2vPeNs3pM3+WIad+XhZa4igdbtmQ4y8wQ6uJNA9/SlmpC8mu13lc2PfVMk3AO6K6GN
RUAEekBGZ3ZNLm3GoStPzyjjLqfaQdquC9epQR344gTNFnt0LMY2rokCWwpOLg6CEIUPxDDaf8ly
U58EYklkxVzV29CR7WgT5F2M3xI/zoCgltq7OWyQpTecKtzImUHGO4vwHedF+59J5BPSjcCw2dyr
UDOqt2FosErylnGyVie4L2XxAfjIxXA+2ivJhSe3VrozHSPUOAXa9Epcj3RFxLxM3PPMeBFgmDba
Bh6wk0efbRBdKInR37PkVOvNHLnAp2Viwlbpagrqyy5i9JEaWlo8DHLLOt3hSJPP/cK4AKEUadGQ
uxiVOA0lBQc2jTj883rz8KDflubh7hGTdwuxxNs8ZKgt6p/SXyTQGzXlMdZzD9BDBBszK8k0sKTl
sBHJg+hcv6aJ2K4PTWZ7SyIB6SundFTIswsh6e9JOZkCtWN+jjJgbf4y5gVAnjQUZ4DqNhcFXJjD
0TcZlgbOuhp8fU52OtXGQzS46IppFXlWl1UARmrcAST++wZ7Q+Ex/QQddavhiR27Ru+AUjGpGxjH
3M6XMoLbdcCmxaVHTKVACZWotIPdN6PjaUM0gZ3KjPyRRISgU/2RSJJ20Rww1M5KcFuT/no/7Vaf
5HSvkEiFY3B6zLrITtUi7XZtrR2CqC0ViPPZmV8gZMrIRGwhzXVoNO0vLmObcDpWy2H1RDeTpdbl
IOEWWgDnUhjzfbTWzIg0kfrf6yvotmSo8b9W4gNbAjW2jlRIt281MPq/1P9woLtDR5iMYaqf9uIU
xWf3j8FrNEGX8ZHFekeoSEhyVKAZf8eEvzLawlIoHNrX4MHqDJawNrdJmk84VDDeAfxKOpVCfYY3
wkpZqPls84YHcJVAGeJGHs+ILann2ztoH7fWsO5DUbCAkULwJ0M/OIWcMdlRTEpsvRT1KiaCT9oR
1O0EdgrSUwgUcK3UuIie3gGFTErONYutjvPfm+1n3H25MCv3xhF80sDYh1m7FC7/aJllG2WTM5nG
3QNfBKNvmGEej5gDYQ2rJTh688+Letc94vSNOnN96shi9aTYh+G5eq9WCVq6MxEh23xkZeAQQxC5
fpXiMRJMIdWFlmIa0QEZUbZ3ycR8IrNg6meCW9KuTedefl+JxNq9e1LIk5nDS06Wakzzwr+/AgMx
0c/k6R2cIVeJPlXUmr1Dfeebk+yeVQ7LijwNNFngkyCiw5TDXg5V/vWILNImm0U0UxrLbMSNVTVM
urtezlUUn4UyhmrgLJHAYt0VA5wyKtb3IIZxYpeleWl6wt2/vwZgRXOmEtQO/IKS94Wi1sPh4fjH
z9uqlim/uh9W+B3DNQo9bl4LpVhZ7h5wW5na2YiHUtuoN3E/YR5/IJyCXTJJea5CvtebTq843Za4
dqCqQqodRtdkraa98kjxqYJFI4m0Afcu8PIrRLFnKoys6p7CR1c6SlgudmFUieyZrsacDxi8ZP+Q
Li2NY+9u89U7SgKVzBolbm2PJAKDupl3ddqGJM4mDcMFNs47xIrF3lWBkXvXhW8dfT3DKrGaImvP
6C34DiUakYDHzKRSt+/k+2CBxeSegqLn/5U/tC7TYyu4P8aY7Husf4J2vwBxmatPTSlUsGrVT+uT
WeURFm5y46cZ/2y6eStVLR2A+OKh4Ks0uBKIGAo5w+FBOna6zgB7XVP8o2LbHnp2JCmTA2WJhOFC
g19RQ+pGCBLqNvfwqu+A92lBVpf/dFV5KVLwcndLiDN35qPnW9vmuIdJYjvj8QKmq/jX4fWFpc6j
cEmMxshMhi0HlaF/r9/dxA69OufvPRzqbmA9DqxXASuorQm23V/AQqkXZrV3OOba/PaLLEOhqBOT
L61oEeds65JH/EN6N8hF4T/sUZayuM8b+apWHqaeeMGdaTfSiID69oGTSuqInuRlktL6Pz9z1LV+
QFKKX1QDipyocsO8KaaIyfTvCkJyUOoN/HwnJxX3abtLC5InD92CY+WaBmPrb6tTw5m/kNhsi4q7
S3U7tL+q7+ouirgGvkY/uoxaunmSIKhuag5LvuSej8/+DYd75Y9moaNN32ewPzXo8LpBFYfrJBEm
DzVq0iZTAaO+3TpAtwUi3dkIyN2kNsTL7kbmJlSGZOVzh75aYV5IxleyFxwRVm+jJaYabQqyCrkl
0dnKXd+D4dsDqchiamAKpGe1X6RqIzDmIs8g7mWZ1LBYf3FOfspn0DGXQ5lHMFkcVlDzYcMosEEg
K1XlvTxekpQP74O+saPLTAMvek4d30pr9MCZMGAgh5U0KleS92n19OAZQC5IgdsIsYavnNKdMUeh
ZupuDS9cvPNFECrRPXiIXXqtYGRoQnuO+IvKSffHXnQoEeAnaJhKQj/FEeaQmtZzYflM9RO4mnL5
1gb4u0FpeA/nh0tGN3haGDt9/zULkdDGzCM3MYyJu+xcUNaxCtFqM1s+kqH+cAPS1xcJiGDj/Bgd
k8pleBG+5U30pOlEUMxkHlAPaW1VRKJD7Rdbb9lxlWbJFnH+95OA/FKVPYdmeq7WUcjar5Qjw58y
kjBoTtwmbP0P1Zgoha3qwCGQx4eiAjpmErNxV7th0RqLYvjBdNyHzGftdzYoAbbMe+EV1ANPgBiF
Q/hzJt4gaBHKaUoD2UsckFO+kXLXyJASNPkGHl/Rt83h2P3jkgicP9Q2ospUg07DJXcdp6NcdDMb
uX3OBwLcnxfHXY9pD0QvuuuuQVUFlY9AlSSizWDrFjbuAV3vMVa/kE8cC7OBTz7OYfEyPvRs+qE9
9wDh7UwzEWWCcWwFq/fk22kYKp6I0/bs0MZlYju8eYwco/3vDchMDBCYZYLHubDVSWJ0PaHb1/6n
dFCVIXvrEZgIkZXCr67waQhBlK7LJRt+ppKyuNpAJioBYK6NiX545XHy1lXppuSst06QF66bXdLw
2vJ1xHClfmFcXPhO60rPIPypdTL0KTObzGJ8TOcQaE2L0b7IsHnMR8tZy+T6YBoJCNUB/7+chVI8
R8BE1a9mCRfD8ieIPZB6iJ34ABdqfMLGbNEcRsP/lTUpSIo7W2+8bAFjTLzUm8IlZu8IjhQs54nE
KTf+y5bOTBPWH2Fn4p1Nj8BQO1iRbvezwlLCqlmSZB0FNRRouOKhp6DzRWQ9bS350ZHYZLnXKhy4
brrTzXX/pCkIQDwbjaeAUqm67LOej94Y7O0a3lmV6VBHva612iw4x4zTj7WOwKZjiwhlOvgFlZB7
vMAi5028dr6hx9PCDbePcA+AR8MaWhyXXo0tKBVdFKNy9W0eA8k4O3BDsgmXFtyqJhchoOExpLvE
2/G+MYDSa0SlCwbzevtN2YJGoxjm0oNoPm+BOtIMOS/TpE7L68gFyxPUvsPQS48LMarTDzv4onFw
GXU2Ah2QjiDTW0O6iavdPrCVisETovslk6oHAcZR3H2VRPBt/ift/ZCXuirUV3JzOVXUY7wIdNhs
h8QXwpjIm8G6mesNVPoLkh0kkvE+ZgRNuYxRnn96j/rNJKFnGYaVLi0iBuqgw96s989mHNWx1l6p
PfH0SDNAyGFgV0lJMEm/4U7xCueuSrNTy21EolR2gau3c+Dbggb3BsveF88jY9muwG4/nyy6svWj
ck3q8cvnaPiBcxNjVZ0N60O0R6wNcLgk3zB4+YZpye5W7yeneWQMPGZAKr+DE0opmJq6poa26TR/
9jbNOfSEVoCwQft+TkERXM17DYt2LYyN0jI8ifinUyWn/50S1JpuRKmcExH1yjr/tkGEzCdlUxv2
tV4F/hOnl+O7FKEHbU9DEelV+emS9pNbPLAWIAQ9Ol/uYYGoVT2zgknFBf+XM532ynnQPn1zBVk4
h4OZCK4oW7uAMnel05mgFsvhZCnMeI9BGdIgc7eZsztwNNR0xpnSPSR3GERN97XV8yD92p2MxB6g
wolHPYtyvwP7x6YU/hNP+1N848u/PgN4CQiaS1mjiHvWDaIMOwemxEJvjMZX4zjwxIUcZeluYOl4
26YQJ005H1uDxJhlMO8QT+yXcCD+qVPUPDlrUWv7fsnXS4UBrvOkEg2uTrSUIPcCFcyE5szrdR+H
akXBANJOs7CPbPzeb++YTV5tpUV0r56gRPn8FA9CddVr3IXsoTQeOQ6o6xiNytVbvwV6sAab8wJk
mU/hNmIVTI6G78cZ0P7lVQSo5+qoUgGm5rarcSYROOsHmZWMXrCaDvNNwZ4SX0AsKjcag4mxCYcx
fJS4nhv+1UnbjoX4epieaxzYtz9rID5rn7UVzSwRrw3RDGBYpIQYCNkUCTU7XVx1fpzUhSgR9RmY
6NH2cGbRsbSzzs/WAuPDx1JlfODxdsq7AszI1NHfnpwkkcMEhyhVgTBg9Xu6LKWeYINioxsTVypL
TASuTyOGlKW5ieor9XR53/F0EuaEPDb4ZUCI1EP04/u/W7VIO2vNOMA2RkrjJSkU9QIl2kx128VV
IZlrfHxy+Ooae0SgR4MIznzny12oG5kBY6CpYaN7Xxi9aYoWIuUtMsKUlf0EHke9GcRaSy1xJKEu
qB3ibzVcIl4npqgqMKQ6e/PxvFwSHO3WXfJ04S0+HbNbZWnd13t6Gpupo3uUIlG/984I7Rf5Q+dj
xvoYHVuD2ZlPu6uRJD50KwKMes4IqimNcBWVlNTRneH6uIq0ZHP2QLaxZf2Y85PD1er3NVw5go/5
bO/bEa+nhDSjcIENF/nFUBFcNkUogTzeUzT8w+Yh0Y/PWyH4PijtAnzm1NfKwtb+o3sZB/3gsecq
vdzVivfDYUAoubbKgsP9JB8B4aCmO9N4Kg3YAMnMzD2TWQjo4P8Ke3qcJ17VEe/04kWAmURRVsp4
YynOUTMcLbSk66K19EnV/E3ssCOf4DvVa0ppVIzaGSp/17fvC1f4Izy8T9/XA98os/MqCtSn+zIu
FHhFlFpSbb0g7Juz6w/0HMKH6Mug25X7LiH3rtqCsIJpgHGVP004MxAmy/SCyjHX7a3oAFDgyJPl
VjcLlj7TX1M4u7ngbjyJN4oP1WwaBsqnAxyS2PJOJVzfZALcEZCV5VAYzgEhoQJ30WeOzRwlxANb
tLT1f+TpF2quKah/UWjze1cqJVh1xhau+BoMQzNx2M7Zgo+1wNcIsoJp5SAjOEdL5oujGd5UQq7P
9bgsJ9Ckw83NSCNtSwFIt+HnCQl7fPZDUwYrDXUzP4I7AJ0BYRpXJwpS9V4eoJfO0KAmUpttq68C
w2DvDzREU2t4uN5vO4aUxyk9jHVgk/jS+qsdZdrPtMNrSqB1AAl58spSOGOHFgwcyiKUESdcEQNf
50Ph0x6Fodavdh7Srq2IHTGnqr52X8ksEY6LiYg67NCOGi/vXQtCGHyt8feKgVcfu+KNPzHzyXnP
xbI/ajOtgPBZB8VapXo47bL5yMiQGlUtjPv9L9DqwPsPrUKm8mE9Qh4UqcBRHvp1eGh2uQ8Meyyq
3YdBc8jUE+CHgy8RwNBMoHyKL0UUhianIFXH7XsYwPHjcT6QziEJPq4m6x8Mq84FvH00euqF+Vvm
sRRMHY2PSoqLaZpmG/gQM0G8M5fHpwbGdHtpI3GMPNcj880/tnDGTRJf1bD7tx78CTsfUKmMgjVh
Y6N2IkIk1haD7q5oesA8ENyZdEb99EtQIlOak619RKJvZW3Wgu3Vkn2ldkYEAZagvBmCMosSMsGq
wHygLYrBuzHDSKnP89SNmKGvZosIqBQTYoN20ChyWFLApcBCwQKe5U4FBvnXsmv3DpqLHCLkQBok
wTCgZ5jslgxs6tpNSb0LYJRAOaAyPuTRCpNkAMH3vwE5v3yJpkdAzU3lQvrqNDfXqDICOqbGmuW3
wqtRxnQd17ItFMfgKxN0mv2lsLT1FXu2wdLvkd0M7aEwz4ZKU6VdsIS3xHF1zrL410IQGG+74mTA
3eDT64/p+ctqW2v7OrYTvj3tGtmUoodGXcQ9nSdk+C9uB/C2lsuIKQwg5Jr++jp/rn4aHWoDbPpx
5Wzll1fTCkqy1u80QDTrVOHpYppj+GlIkJzYOGmbur6gAMGXdYtGR8R248BiOquek3oMkW8vlZ56
OhTrI5+LaPLXYO6zk1Fxs5nUdOIorA4jg0zme8n2yGWrCBA6Gcs7RAjCvCWfKsGKf7GaSBIZymwK
NAFS22p/ekzCbsAGzevc8XXG8q8HfcVGVdpHErRaWRCjbT//z4aK8vSm2+sa8BhQBO7dvLfkEi2D
qIq3eIsKQiNSy2pu4Zw9tq2zLAvm6s1JHpjL5Agm4zDbaJ+hqinoppCmsqHYdbKmipbdB5adS8OU
OeNF2f3F/BGV5HNFjfqFSGYlfk/sjoTkVwQuE6qepGA+KUZhY2nTZnsh6G5AVidRWfA7wSsZJw8z
PhQEyjMknPNvo/sWQMIfLPHGLyYZMce9MQamIo5YE7GMgIxgx73KQ65z9X2CNmkVBJ+QIcglrnym
WXsjaZvpVU0thbLp83GfKoR60hMEH/6qZ0ZcOEaLvk6GubLuv2Y2Lu+40Nb7/HTKc4ucy1Z+r3HX
k+6MOXGjA9wFH0BhxZ1uBqhQrNwd7RQ4ng0lfCg61ZAmQExlCZhJrohy9caThCIXjXEEFqy6HKP+
88LkdYN5X3yy7loZEcBKgTrVjqPMhc5Am6ehWeoal/+qa1TrkIguq+962D8mrFas1saBXy0W9v1R
S2iR6LIKXkPCXnrtTz4yf1aJRLkjUNQlWqhqsqDYvkSGVLSsRmwqGi5haEjgXuDjP/5vDGyRFgtE
mz/5IsA4KrY0WzNztdJx0PO4TD8obyMAASFL/QNQomtAJTvxnvaca2+DZFwawx/eTDrVayGNfqWJ
uSRaGFBkrQnX/A1AVl8EXSgv80A3ohPVmz8Znel51S+1JRfdfObOA05X6bVaKvT71KxKPeas1FDl
/mhYiwQQr8g/pp0RC8aVmZZkuaTLh9qOgVWQKRN2jvKxUHYWgc7jwf+TNnMiCuigL3QfcyCqtgJB
EuwsBfLoxlIH/ge/qEwAPG2N7epibQsRs9YzxbpUGprbFtKskt0gLh/iIZndxiZg19gtAkBcZiPt
WWovSosfbFCrhQq63IvsNSPxjsLDuwuqopNqn6Phv31lRFivdUkxcHEYYAHTo6eocaLWtr8CtCwP
bhHjWn7SwwGh5VQ8WexCveaw8R3TqSgtHHi+qyiyLa3XnV9KdKdkwttUCIXLQnW5a8N0WkafXnr2
z+iUPEdLAR01qBsZDsXP/Ct/qO6IZkYkgvuG1jMji9ObEfuRgDltainxHHZDgyZTIiXT5UdNfpqL
Em0w7C8f8+N0vmHlpqTf0S8JPUzfqXBH2n5Y6ySuNDbNoIayFAZ0SHA51Osmibf2IEuN3ReiJ8+e
hnM+s/odRjXYQAtsoHQaseDHLVngywDBecQQ6W7Sx4N0ta/71G60fMEojB6skDhCBfBs6DO7pVBL
nz/EC1fusay4UeAoSoIaLUElzVT+TriQg/rxx0vnqbhYHUBSGpDv5kuQ7Mi004KuAvHbvYLkFXGY
p6AI60d4TRacYGh4uBQh7eRMEkP4T6rruIGEtNQT+tU57IQ1oAgE4avScs4EDfAzcY+LRDge8UW+
8sTvZjBT38N0UnGcK31z5d57uNjzc96ZPnvXrxWhUgf2/A+gaimlBU13qOZjx47Lb9SXS4AHZQND
ApYooWzxodS4KsBZ/8i4qNczcMEqRpfQRqL2Zw/1lRZP5XX9ZC4WoOiK6oEhFfUQeRzvwbZ3MyX9
PtKSRlZUkr9jALimMkWCLlUIqaqTS/8bftRdw2RFlIXfqePcUMOoCSE7sktDiLK5TKK7KtpezvzY
Lg+Kv4LFQL/xRhcS4HQ4SHJFVwI+92VH22HONADNswhMCOwcFwBRb9qg7hqccQYb1xc8gW/+qTJ0
C9imAm+U/LAWvbAegESyaMwtLOZk/dpsy+gdUqFiURBoQaXxlBbwcpZRrbIx40XnrFXv+aaw+NFl
pe7xki3wX2E7KCTp/YdtbDjpFxjf0hHPu1yAof/tgayZECIcyJyz91GoWU9dWK52WslBM5ClZxbc
TV2OzrHMU5zxUodNS5KU2qU0uMrfwldlQfdOYPjvIOtFzSOK3iAcAd0K0FRk9e/oChYI/p5hlYIb
I4tVDxDOJ079qaOvAchCLQkqXBFEvKbfdVndA6AadTEd3NeSPh3MGpa26KR+aNhLYO2hgyntVoe/
nyOJRVGi869wF/ZAS1v11XcChQOJTJKJXaj81n5g18FzJYbYUTfnhc28G9uF4i50aTRsRCop0GdV
D7j5snjr8BKXVnVtdwiPHSQ7EtEYJitSQu1ZNONYEdTu2t/tF6Ti5qjH7NcOO+1AVDxwUoRUOKc/
PNI9glCPTsnNBAFR98odk60H6jn6DIGPrwZgj2s93Hn7U+PHnY6OBenjS0NTk7MWae33/TnkMls7
Tn2kk4enFrWpjyKin2ihgt98Y3gLBJ6Qsvd5GdZzgCw0ZK7PTX2N07vFW4oTFWK3X64sHoiyNONb
xmPRd+Qm9WdqCpCKDl6VGC4mvWFf4i0dHzVBITwkonGMJH8nFyMviaOWRpOLZ2tMsSVDOQ9zfyJQ
YNNLqZUWQEeFmI4qC2yiNpsR6lDThvO3MVyIddLQsviV96+rc/e8pjv24VJ2VoxFzlfWoUcb6KOK
R96EMyxPEH5oMZ+NUnekKPaBEXrMuAQuDMNzP3jd96JyeSobabmT5O2JaoUXuTXRBXsK+4Pcrb5a
T6jrNBY4qj234TtZy5FqH1LiMq9+phO3A0IsvBWJmAUgnMRRzdjMX7P/Q9ExBv4dsufesvRsuZJ6
MnD7a1xFGvumEENoE3LPMfbzxMwCqxjvANp5obj+kkwqXxmHByMbMrZkjXEbVrU1K7lxdNeuX3iY
j4QyrdTDIHJQ3ZVgfSu9mnKOYv+bX+xwBhpPOX1DKQCt/npDDrNy5PWSM0IpRzBiHjedS54GK2wb
2DX/xZdAh77HijFMBAKYNZPlZ0Cza8567nxaJfqt0pT50CqkBROTE1qLr+lMDmUrM1IE5cKZNV0H
6cZkAOUWnZ21F7qZUXB7W/I22B7xH40IizvkVITdNZeKC+Nw8PzD+rcqGN5gopUgSlw/WR//KWG6
4jUzBvvkt+UPjVTQ8dNdgG4PfUewXeepzyRnPdIbtyEcMuWzv47uNC6s23hyir6/labE3pFcJhG8
WtAg9CZkigdCVtPMGrNJpCzAn4QuHgAWljUQKUJGZE6739JqA3yF+XK9Tadhf0Te6oMxVil+BSVZ
5QXT7XIgbMDXsnxQTjstbYuJTiU3iviQT1lHmSznfickji4GRmbucuUnQiFf6zUNf8WCNKwU9thc
8JVQqzj7mKg72+s+qhRhi2nfNo4ROP6oI/Hhlpm6O9tkP5EeWoVxmc8o7YynAFzuzODTglVAsLHJ
XdLkaFFgJ62USPCyKP1fYlmKFXnZ40n1s0xfTQxvdMr2g3WIr8iSDKHWpcqUozlnLVrMgZDx4RAd
wwX0V5hEIEa/5tb1wt8OlwTXNjXOFDL/3nuBBnhH4Jfn8ucWO4D576SVIX0i2QhvsBpxNmbAGKbr
0y+E0Vn0fweMyF3oDdBH2oKg0TQXvndW33PCuDKptgY50q5WIoi+e6Pc4IMc0/O6yIqLvZnnhE7Y
sErpvA/lg6qnRRcdJWnb5nT91iHJRBxtsX3G0micJQoEldaydpUUOw/TDyBdLCU509fDvPF7N/0I
plBCRY7UTKYlk9Iguqizs8ZG8dt9huT4r7TQD7wAwIjuW6a2LfkXd+oU2wtoNyibGl7rvdYaQBI3
gAdGN/M16me9v7ys9r3FhGoFbBjtaCvVkPASam+aiyYJe1wST/4WoSvZlz6jNC9LqS2eXdJ+qd7P
gXGCJ5Wlnkbnzs0qf9jBEItzhrEg/3n73B4ts0U36DrOWlQy/9ClyFnRqs6nDeS49h3d8mCiZAwZ
2KKpEKJd1UXT/EBgO+JxNFw3GIwyU2+atyp298amQjFu1HXmW7dpuK7qiu+Y9OG+lYAoS3gsGMXD
L3MowdEGo0NugG/aIJhJHgsxXiuf753YDUswSqr/h4vwyziHQTaCGQYDb3rnxZamSw7wv1ffiHVY
reqGCYk0b4FGOcdqdF4qzLkTLkJsDGqRXwAvP4OU/aKII3rYDnmD/oFRmI4gUDpQ3By7OrvqNus7
QIK96j7NySUHr6VFLWqVDwWFCp1UOr7/nmJgaY6BvextodzT/vcsGJ9JyvGLFdtn4mIufCTOP9Tt
drtZamBNFJ04YtFeGKbisVAJgQ5qbk7xdUqkq1HUKWn1SQDRQ8XeQWGrae8cu7fa3MQ/sSC/5DW5
ppTWQkS2KSUvG0z6OcOogrZCC6wo+oT0q0OU1KYvBdmR0VP8vJyoNtrHAWd9o99an34vzPhhOJwY
RlNaN11RZD2u1mz8FGtWSZUwBme8NZAS2DsfVLMYqIQebUB89Ezr1mGST2ID1zo7fCwkHhesqICk
FJjsQ5YL6vNd+vmS/lcIrLT1/BkdiYXnY6J7wYFDbnK1nWvWmiI9mV+o+h6BEs4uVbYtDM4sUQTa
IcA5LeycCSp6Qs6hNS1FZnYNG1Pt/kLay1FgU4eUyARwj1mGv1ZgkAuM2zWImNe1v4Ha3xInWdCL
tHI8spJNLhwgvOs4nI+vaitli+bB/IAizUBeeE16Ah3pQofx3wh7+qWs7HH3Q3brjDAiefqoDRdN
VoyWsgeL4MGgTdSId01jJ0QT1OnXthxlpncmsB77R1I5V7UT5kcIb4OYCvYnt99zKVP8/M1vLHo4
eJqoN1H8foezdKX4wSNVBHVTWKREMhU1zwjoF/5xd0eKTYTUwpPgdD/lkr3XEd6X+XMaBq5LyisN
TNWwOX/+phtC9Z+2/FRii0XTV+6x/Oo5l4V/0Ti+J7SZYy4tBfmlWWNqpOTwUV5qxrkRzPwAa3dr
luE29AkOjdT1hghDz9Tta245/pehRNy8Gv0Zbex/o/0cR+kPZ9CxLk6+RBmvA9F17pQjT0JdZYmD
sUmJO9t4WZeqny+crm4G9xBO+GsUhjbGhXRpNYWcNlsYWZnWtsLZ+NCQFV84XZ7HXDR0519Hqs2d
rBy2nK18UZVvPaaaBZhe6Dz9Vbx1IaiU64raMimLAIqDvnSs9khi+67qC1BqubqsYEEE+dnJhGhX
2rhVxsFt7Q532vSsW5yZiz+uyrY9qdj8Wl/NkkKq0D9vqmZ05yWA2T6MbY6cXRjgHfu/j9wRrf89
0wC5xV2HKcGMmt/cGDYF6y0WdnWWkJPb7bH/0FXgNMQZJorAvyi4hZxmWB2VWaVpoKCCQ/Trhq+3
J/XzVVC7n4LcOAjgytZvUJx50fNaB3f4MshbzjGW8fPYOzV09qEgZyZRJMqYBPCXctGhLcR+Qo7p
TK5AVx+v7Jp+Mi8rOzdJtxvIR7ySoXFehn/nLbyaccyvujY13w0Lq5TR0G1KgGVIn+2FOVgfGe9x
tDYubGwLgm0UeFtImZXJIRUfSd/gEDJTEKfGd29q4JOabvO/aDm73lMjTZ/tp6P6t/m+8UghJ3W2
2sW83i7gy5XUOtM/PnSwEqqqt6ZSheC91RS8Rp4ofeCyl0dm7vJ0k0m0ZCZA62MH7Z6kBJ1q9oDf
T1Q+X+eNTjO0oNUmj2l2HDWk6MHZApdyd3Okb9geO6AlSSFpv0jd9Hq1aZP+cNkOnpIUO0SGZAkt
xm7LBoku05bx4u6LkDKKPGp7AHiZc7XAMn3yz3ajvMf5zZotO7Ld2UxVoSiF0Wg1e0B2yFGVViwf
So+5Av564MHmU3Lv79EaReH1o1hBftessv9oPXcJvmLaHNXZ4Re2SBoiWT8L8UynCshmkRefaWgw
qimUpAgHptNWe3nDqDuWRNd/a+QSKJ+a2CWw7JZKN5RPQ1Eq8zKXC5sJb91QBtx6hqJsLLUFwJUp
iVGTTr56sZ/c+dlbl74ia+DfBrpNxrWx6l+Mp26xTI/eZn7jCpjpgd4pwpHyOK16iEr3OxDmI5CG
GhfimRpTgiRjjR5Q8GUK25wuIZztlWnLzIR4Lk17Xho+8Q7eYWRp6hayTLHxDW7K+qdB8cYsxl2I
TVtQwQ8F1jvtdKbBwOmAeGYmFJpewJLC9RsCfyZzmN5AWJVvqdDyEFrfequYervrCQKHk6Aa+M1k
SMGPd/GuwDG6Z7vPsna15FWU++eW5CPa/Xqhkrg+yKTZ+IcVHmXlenr1DwINb9v2EPZjvzvWh9NE
fyuY9x1MKrldJG1Ro9O+hzLJQlZuDw1MM4BBolStrXHIMF6/auRo3SOXGzZ9pHIDqwWf1uVVmxQC
UvWxv+tgpPHjHwZNZ2noubavTp8lXkIy/ZjZnlRK1OJLSFRkToEInItao1U1Fm7+OKFzdnIOepsH
0GiVeYiaV4r8QKVU6ZjxpNpH+qlAJEbuV1WRoRJYnN5twM3whDjaLRSpW3c8lnn3l9ngNHbnrbxe
FLjikR5sj/zFrzethj8v2acUyxlJ2ekuEOaQAk66cYJ9H6lUwOYrF3UNi8UCT30vmp+U6OdIPg4s
7qxqpQJfVLLG9OIFe36b9GVnlTNSaUWLA4rCotUdt+5o/ag2xExQHhX8Wa923gsHe4UfJ0yNlr04
59Zefekzph6BF+SAOL2mNJ6o/LrOdlMLMO7HzPKzbzZSDW1t1AjUrAy29Lp8BlQnfpw/dBWZnRQd
oophT/zt/Hsgb6g/82gsNezUGTMo/VgBObY+tMuLp9caRS6g/c7Atr7hmIakUVaUrNOzXQUdP6hG
rf5KXkrB3eT7XgapzjURc1rwW1ox0REn37Qu3N3wx8pTx3gY7mCWStcDC743zRCo+BiXj7lgx1El
TKSXzkmwYdEN6MEX21Khnp3Qs08MuLRjeHF/yRp+boGARnHCHZnm0LSIOlz4Z8YYoyIzYUgbzZ9K
hmW1x08sJP4NdMc3QNh33yO8HmI+tH+YlixohWAixeri1ZqyFqk9MiNDIRPe5hm5kNd98wwXBICA
xOnfBzEC7W8n66uYbuuzdIj0kiyFJYNpSMwh+Oe47UWxFO58R5Eh3ycrvD1+iDEPz6LRzU5oj8Ro
VawuXttSCnOB6T5mBNITOGgdi6o5p84MxPc=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
rKWwB0sGGUajpurVPwhHzgsZATzg6CI2fy5teGZgwWn6RJSxvVrm7X6KC1NlYW5YtUDp2ese/Vrm
bw3OqIV60Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
BRuqFpGYGOGwcHOC9ByqxsqWUs+0okjDxEXI9LjsXxEyuWJLFUE7YYzNDASAihgXdiZINIm5es9z
yyLJWg7azDkuzQk8G9FmmXCb4GMcSNpaTGa1FVepRSL9Yvq1uMN0rfkU8OoTCb0JTco3mn42K2KI
S1jw6CGiZKnXjxgHNBU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
X3xfyzvjrmPkaI9JdFIRWVWKvQVaKvW3xkPmxmWB+Bg2oVsfAsBqh2i46hM/Bcj4vTlgRohMAtTw
mZrr7U78E4bYF8iEtFKLdIJEd7hVOOlmDwsFBDzxg0k47kX9A3ruJ30LrjKdxboHAuMIaT/XR/sU
upe6flMZr8VBlv8re7jyziDyWZOLqFpjufskTfv4OQj1KszofT4kUnArUhuQ6UVlh5i6v/pQEzIn
QBP9XWEv/eQfQZl33K/QbbRAZIttPtuWp1T04bWkTuCPPKG+pDFGGGHJZvQDtAaxZSkHqZAvfqlI
CAW2rOiYEadE7tUwZCBmG03wqqm+cZJmCFoaew==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
AUXv88ADQriH8V/F9F2bxLErHxhqOWkmnlCs9b253d+OgRvIOLCtaWRA9DjnqkOKIf1wnvs/R6pY
dJJExfXVZOjD4nIH7uFh77R1TOSQouJzgmqD+K5HYb0maU6PAGIafeBzcUv5XN4HOOPvm67+oI2c
ikEGUjjanBNxts7eGBk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UZCooc8nZi2nNWJ83Gcm6qAONngeeaBUnqNHZdi1nOU1iRX6MguqeK1oMSUjP/9bRjlw7Tp3sNmB
PWJn2GGi3l8Qe6b7auDrjGMr0IkAvVTyrVlPQlMaseSN4e4IeWhVyNWjm//n/TOKlr4NMKKu7xlw
UYk+ejL3Bl9bd8/cGgsVR5ZkQQavRAFBo8L2IT7ML5f1IYG78bF0KQzrmL9GYFMnToP9B7kVR7Du
Yb7rcfK2Zazdh5MpYg9XUjLic80aZcb4+8dYBu7XgEp/Ar3GApiNMnYJUmVK0q0n9Er1Tqahdfht
jdB1SKLd/YF5uaRclGtmIoZjAK3M+1SEWOps9w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12224)
`protect data_block
t5Spk6yve3uJ1YJ8JkRzUVqRYSeuRX7hvbRJ802Wf+RbaumUpGUGs1znFzR00sTUqUlo2CM6n9t5
idaQheZ7CEySEBoOnXCDFAPgPh8ykyAiFL3Y6sdSpbifGT0J/JOeKzMD5+nIp6kLlUBQc7VQSeug
M59+p40cD2Inb5oFM8hep8qN/6JeN/AvWyjNarzBXpsddtlR8UubbsDzFOoHP85gMfreqfxKQ4mV
L7Rk+vSOBcAjasibJdt8lGIhGi/lyefdAUQVTAcr6Rk65rUmtv0s/zold4FRI0PmGoGxfBownUjt
ID3OGTorR57ZiwQS9SYT/JxWJc4zudrYR4fD8DMzWdvENN1xnOhzMhMHt+838ogv5ctRUr1L6p2O
rtwRmv3wR/GKlGn8ybNwInmjtK4+BNX5gap6mk0YnCG4mJTIiP+FaOoM8wdxiYOIdNIw+rUEBT/r
F6GFBxG8/5onUxfWtczQimgRffRR0v7VnhSMzy2cgMSC7RSfU5tBTVhvUjiZIwBwd4dh59wwMbhe
ObgOq2fTje9tphNoAT3WxoQOthjG8xxXRsX5sR0k7TcuvWX4nQV9WbYTs0pleUmspnq1k9Xs0EIm
W3y6b9BoMzHXGL1IE8hJYlJd5MJzzouUlPN9Tfwh1wrNpCDlmJ9J4GDclsOU/CZjQsWM5EUzV+OH
J1jcgKJeqyL3hOLIX9Dzt78ChPYHG1qg0Mb4qDP88S3pODWbW4+1j2AsD7uCWlZNEuMljxUnEhE8
FIE3ZCbePEIUPc2Pf6/43pOUbTiGDWhWlgErsC5o1dI6noSg0LkHfdLy18FHnFWX9F4Ot9xbxQNo
Gz2CBeKdYc1PWDPlJvrALuh5AkKAz0HEA+nOrvYQQikIUnTo+jrneOXHX5udeFGKOGj7cGhNtvlf
Tf9HT1+I7uysbP5f9/Vy2tM5W9ioHXzlY1KX/AAIXi1jyj61mytFLzgfuX9qQ+d7eZQg975Qw7wv
2K3Rs5rSBCYTDlyZff8DwG1W75SxZa5ZEUnq2iIUAu/K7a57rlg+CagNL7UfcqLTet7lwWRb/36V
iakB2GyZPEZWgje1bPPgQp1xBoLyGizRUM+wS3Vvf5n/3MMSjth8mQJeFKioXxqm4h/cJw3QGSI5
UQpah2uMGNMkL9oOvnJ9B2m+nLKg7VNIXBGxIYAXGhvdZkHt4VLzwYGcaGFdZa3OnS5gjN4TMRly
fi6w4xlKfDC7FwkEBAFjRxbHczk1q4nNDzpStSec9d5uCH3awkL3L0IMNdShksbCWmv3wwEFhjOk
SjVTEdwHmcA4oi4aoPvyiGDR1JKY7w7HjpuqE4+zIGGQkcoOyvj2XQx7JThEuPl9ECrZb0TLBBDK
bVRSzEy8HMp850gBd9iZCkVAHfMngslcOITnvHBJ4tFmHTwKWmxUxCJQ5gg89B07OGUhV1Q+z1jG
me/hXjX9OUPElTDa6TrxMsw/u+OojNDTVFA8X+D6laQ40t9oXuk0KBLM2bdF8iNGxHL65Vp8l+38
RPifxux3QEZQW22MVYOiHY8Wpkxi8t6CP0qQwMYn4yC9yAAZYdFyCJ6i3Q7BwXQezdhvpEyEH15s
EawpqFjDMh1gp/QeoJc4eMiWdTRlR1MRpchkVSM2AIbdntg04ShmJIDrsoseAyfot2a/M6/3k8tg
2ekGAX86Z6p21WYEj+pBaBr9yiAyMfxzQeEGFIJli9AMB58eQJwXewlkB3BRp3bxqFeUuHdgBK08
HNzvjIpo+x+asZypiv1UG9P5yt8EJCVQLd55M77zucbLyq+9Tm15/ZrpMQiVQKtWwhGEFM/LdLsD
eOpGAo58unYogZ9jd61lpWzXjfk8K+1Gk5Rtj6GiuxaIOC+4AaBRjHtq2rot5XeTUEeXKPOc0iP0
SSJvQlTRnUtPLT2oWk+FaRwo8kG0Z5pnY93pyvl/GJkDHomt7zBb6Ii1YEesPyGd/DOWVShIC5UX
YzP2NsqRNU/flC/VJIvO3TqEyLi3DOxbzo6CBBOz9FGAO+JU3c83f8ReokkGQPChk8pO3LTeWZWT
N299EgGOEzhgB8EVBttsR06SQ7mnQqWKhInWrSCz4sn0qPhjTXfnqKWeZy7BreuOIoOviLrS2NYv
qHuYuMcnxnEf8jkB7HR8qx9yRwaWV8iOoG/QMCWt4RGLL1zZVYvwqeoH9FZQDcjLp20a2sQPRWdH
ExiZ7RXUn4f4MvIjQz6vuGqqNnt/+6HHpYhvRcdyUJEpPCA8bTQGvTxcnlso7/c2NLzXIkC9bgXV
bu4/DPLvHs+sCT/c+PFX+DLLQfSNW6ccbS+XSkti77jxD1xeot+dVvpsvxYrNQACiL+tF75evtLy
eXfXPlETyJlEj0SAF1sg4n7F3axNpo6T7h6LkFUgPwXJ/luGCQCV4nC5SOWYh3ks3wVCist/63ob
oQyj9LmJHDz+TypWnwqEufwnUMbf1155GsRyTcDwcN7eH9FBtO2WaPfmGqugOND3SNl6xuddm0fZ
+fMZB8vXcCRf8Me93X+hqMDcuRWzEbD2WeWDqxY9Y44XuBb0Up+0jn6fsrzjQe0nIBXyPCbHO+1Q
65qYy1YXZk4xb5PKb2dKUTNL3l/uJMwRE4tiru1XLfdfgL/7DoDwRJOd5ZwH9kNmhrWbppH0RGJh
woO1qE83rK4VGj+iTeY1etxKSiMPCKYxrvkms+cdDGsYrYgG+xgsoJULJ5Lb6/B7Afxz2WGj1Wa2
w3zzV/agOpG2Tg0NYHpZAH3t5JbIg/LnzvjV8hfqflx3ISnyqkJls6/SOPLLpR79KSDBtD4PILne
AO8cxuO7eV4kXFbQLFbjQkvHi4t+WnQ+TDOxbKGEalVYXrfGmtVx6q9+WO82B4ybbv4A5/9VwSE2
TeRlzDFUY/7qTqweXCi77Zd35i2f+CR2tEn/qOoVM1/YqhzbnfdGZqk/H93gSFcfd5mI9BgQSlOp
EiB9pUOxjJb6VS5Yw1w/DJHyiMXvwtOXbjIQf6y6EYqO9eCnONXjRZDmhEHFKDaUCKZSj0PXwQZn
48YTWU477JtQIEfRJcvsjN3QOuywTXiOsoEQcVLv9k8AUenCU0i8flflczz4ws+fohE8ZUpaTAd/
+hmCtlS34dUNMi/ySWLj9TEdh5E++trzjKG0bRS/jq6LXg3QgnKsCeHm3xkqdanznPzMUEpq4Plc
p4lxpMo1ej2vPeNs3pM3+WIad+XhZa4igdbtmQ4y8wQ6uJNA9/SlmpC8mu13lc2PfVMk3AO6K6GN
RUAEekBGZ3ZNLm3GoStPzyjjLqfaQdquC9epQR344gTNFnt0LMY2rokCWwpOLg6CEIUPxDDaf8ly
U58EYklkxVzV29CR7WgT5F2M3xI/zoCgltq7OWyQpTecKtzImUHGO4vwHedF+59J5BPSjcCw2dyr
UDOqt2FosErylnGyVie4L2XxAfjIxXA+2ivJhSe3VrozHSPUOAXa9Epcj3RFxLxM3PPMeBFgmDba
Bh6wk0efbRBdKInR37PkVOvNHLnAp2Viwlbpagrqyy5i9JEaWlo8DHLLOt3hSJPP/cK4AKEUadGQ
uxiVOA0lBQc2jTj883rz8KDflubh7hGTdwuxxNs8ZKgt6p/SXyTQGzXlMdZzD9BDBBszK8k0sKTl
sBHJg+hcv6aJ2K4PTWZ7SyIB6SundFTIswsh6e9JOZkCtWN+jjJgbf4y5gVAnjQUZ4DqNhcFXJjD
0TcZlgbOuhp8fU52OtXGQzS46IppFXlWl1UARmrcAST++wZ7Q+Ex/QQddavhiR27Ru+AUjGpGxjH
3M6XMoLbdcCmxaVHTKVACZWotIPdN6PjaUM0gZ3KjPyRRISgU/2RSJJ20Rww1M5KcFuT/no/7Vaf
5HSvkEiFY3B6zLrITtUi7XZtrR2CqC0ViPPZmV8gZMrIRGwhzXVoNO0vLmObcDpWy2H1RDeTpdbl
IOEWWgDnUhjzfbTWzIg0kfrf6yvotmSo8b9W4gNbAjW2jlRIt281MPq/1P9woLtDR5iMYaqf9uIU
xWf3j8FrNEGX8ZHFekeoSEhyVKAZf8eEvzLawlIoHNrX4MHqDJawNrdJmk84VDDeAfxKOpVCfYY3
wkpZqPls84YHcJVAGeJGHs+ILann2ztoH7fWsO5DUbCAkULwJ0M/OIWcMdlRTEpsvRT1KiaCT9oR
1O0EdgrSUwgUcK3UuIie3gGFTErONYutjvPfm+1n3H25MCv3xhF80sDYh1m7FC7/aJllG2WTM5nG
3QNfBKNvmGEej5gDYQ2rJTh688+Letc94vSNOnN96shi9aTYh+G5eq9WCVq6MxEh23xkZeAQQxC5
fpXiMRJMIdWFlmIa0QEZUbZ3ycR8IrNg6meCW9KuTedefl+JxNq9e1LIk5nDS06Wakzzwr+/AgMx
0c/k6R2cIVeJPlXUmr1Dfeebk+yeVQ7LijwNNFngkyCiw5TDXg5V/vWILNImm0U0UxrLbMSNVTVM
urtezlUUn4UyhmrgLJHAYt0VA5wyKtb3IIZxYpeleWl6wt2/vwZgRXOmEtQO/IKS94Wi1sPh4fjH
z9uqlim/uh9W+B3DNQo9bl4LpVhZ7h5wW5na2YiHUtuoN3E/YR5/IJyCXTJJea5CvtebTq843Za4
dqCqQqodRtdkraa98kjxqYJFI4m0Afcu8PIrRLFnKoys6p7CR1c6SlgudmFUieyZrsacDxi8ZP+Q
Li2NY+9u89U7SgKVzBolbm2PJAKDupl3ddqGJM4mDcMFNs47xIrF3lWBkXvXhW8dfT3DKrGaImvP
6C34DiUakYDHzKRSt+/k+2CBxeSegqLn/5U/tC7TYyu4P8aY7Husf4J2vwBxmatPTSlUsGrVT+uT
WeURFm5y46cZ/2y6eStVLR2A+OKh4Ks0uBKIGAo5w+FBOna6zgB7XVP8o2LbHnp2JCmTA2WJhOFC
g19RQ+pGCBLqNvfwqu+A92lBVpf/dFV5KVLwcndLiDN35qPnW9vmuIdJYjvj8QKmq/jX4fWFpc6j
cEmMxshMhi0HlaF/r9/dxA69OufvPRzqbmA9DqxXASuorQm23V/AQqkXZrV3OOba/PaLLEOhqBOT
L61oEeds65JH/EN6N8hF4T/sUZayuM8b+apWHqaeeMGdaTfSiID69oGTSuqInuRlktL6Pz9z1LV+
QFKKX1QDipyocsO8KaaIyfTvCkJyUOoN/HwnJxX3abtLC5InD92CY+WaBmPrb6tTw5m/kNhsi4q7
S3U7tL+q7+ouirgGvkY/uoxaunmSIKhuag5LvuSej8/+DYd75Y9moaNN32ewPzXo8LpBFYfrJBEm
DzVq0iZTAaO+3TpAtwUi3dkIyN2kNsTL7kbmJlSGZOVzh75aYV5IxleyFxwRVm+jJaYabQqyCrkl
0dnKXd+D4dsDqchiamAKpGe1X6RqIzDmIs8g7mWZ1LBYf3FOfspn0DGXQ5lHMFkcVlDzYcMosEEg
K1XlvTxekpQP74O+saPLTAMvek4d30pr9MCZMGAgh5U0KleS92n19OAZQC5IgdsIsYavnNKdMUeh
ZupuDS9cvPNFECrRPXiIXXqtYGRoQnuO+IvKSffHXnQoEeAnaJhKQj/FEeaQmtZzYflM9RO4mnL5
1gb4u0FpeA/nh0tGN3haGDt9/zULkdDGzCM3MYyJu+xcUNaxCtFqM1s+kqH+cAPS1xcJiGDj/Bgd
k8pleBG+5U30pOlEUMxkHlAPaW1VRKJD7Rdbb9lxlWbJFnH+95OA/FKVPYdmeq7WUcjar5Qjw58y
kjBoTtwmbP0P1Zgoha3qwCGQx4eiAjpmErNxV7th0RqLYvjBdNyHzGftdzYoAbbMe+EV1ANPgBiF
Q/hzJt4gaBHKaUoD2UsckFO+kXLXyJASNPkGHl/Rt83h2P3jkgicP9Q2ospUg07DJXcdp6NcdDMb
uX3OBwLcnxfHXY9pD0QvuuuuQVUFlY9AlSSizWDrFjbuAV3vMVa/kE8cC7OBTz7OYfEyPvRs+qE9
9wDh7UwzEWWCcWwFq/fk22kYKp6I0/bs0MZlYju8eYwco/3vDchMDBCYZYLHubDVSWJ0PaHb1/6n
dFCVIXvrEZgIkZXCr67waQhBlK7LJRt+ppKyuNpAJioBYK6NiX545XHy1lXppuSst06QF66bXdLw
2vJ1xHClfmFcXPhO60rPIPypdTL0KTObzGJ8TOcQaE2L0b7IsHnMR8tZy+T6YBoJCNUB/7+chVI8
R8BE1a9mCRfD8ieIPZB6iJ34ABdqfMLGbNEcRsP/lTUpSIo7W2+8bAFjTLzUm8IlZu8IjhQs54nE
KTf+y5bOTBPWH2Fn4p1Nj8BQO1iRbvezwlLCqlmSZB0FNRRouOKhp6DzRWQ9bS350ZHYZLnXKhy4
brrTzXX/pCkIQDwbjaeAUqm67LOej94Y7O0a3lmV6VBHva612iw4x4zTj7WOwKZjiwhlOvgFlZB7
vMAi5028dr6hx9PCDbePcA+AR8MaWhyXXo0tKBVdFKNy9W0eA8k4O3BDsgmXFtyqJhchoOExpLvE
2/G+MYDSa0SlCwbzevtN2YJGoxjm0oNoPm+BOtIMOS/TpE7L68gFyxPUvsPQS48LMarTDzv4onFw
GXU2Ah2QjiDTW0O6iavdPrCVisETovslk6oHAcZR3H2VRPBt/ift/ZCXuirUV3JzOVXUY7wIdNhs
h8QXwpjIm8G6mesNVPoLkh0kkvE+ZgRNuYxRnn96j/rNJKFnGYaVLi0iBuqgw96s989mHNWx1l6p
PfH0SDNAyGFgV0lJMEm/4U7xCueuSrNTy21EolR2gau3c+Dbggb3BsveF88jY9muwG4/nyy6svWj
ck3q8cvnaPiBcxNjVZ0N60O0R6wNcLgk3zB4+YZpye5W7yeneWQMPGZAKr+DE0opmJq6poa26TR/
9jbNOfSEVoCwQft+TkERXM17DYt2LYyN0jI8ifinUyWn/50S1JpuRKmcExH1yjr/tkGEzCdlUxv2
tV4F/hOnl+O7FKEHbU9DEelV+emS9pNbPLAWIAQ9Ol/uYYGoVT2zgknFBf+XM532ynnQPn1zBVk4
h4OZCK4oW7uAMnel05mgFsvhZCnMeI9BGdIgc7eZsztwNNR0xpnSPSR3GERN97XV8yD92p2MxB6g
wolHPYtyvwP7x6YU/hNP+1N848u/PgN4CQiaS1mjiHvWDaIMOwemxEJvjMZX4zjwxIUcZeluYOl4
26YQJ005H1uDxJhlMO8QT+yXcCD+qVPUPDlrUWv7fsnXS4UBrvOkEg2uTrSUIPcCFcyE5szrdR+H
akXBANJOs7CPbPzeb++YTV5tpUV0r56gRPn8FA9CddVr3IXsoTQeOQ6o6xiNytVbvwV6sAab8wJk
mU/hNmIVTI6G78cZ0P7lVQSo5+qoUgGm5rarcSYROOsHmZWMXrCaDvNNwZ4SX0AsKjcag4mxCYcx
fJS4nhv+1UnbjoX4epieaxzYtz9rID5rn7UVzSwRrw3RDGBYpIQYCNkUCTU7XVx1fpzUhSgR9RmY
6NH2cGbRsbSzzs/WAuPDx1JlfODxdsq7AszI1NHfnpwkkcMEhyhVgTBg9Xu6LKWeYINioxsTVypL
TASuTyOGlKW5ieor9XR53/F0EuaEPDb4ZUCI1EP04/u/W7VIO2vNOMA2RkrjJSkU9QIl2kx128VV
IZlrfHxy+Ooae0SgR4MIznzny12oG5kBY6CpYaN7Xxi9aYoWIuUtMsKUlf0EHke9GcRaSy1xJKEu
qB3ibzVcIl4npqgqMKQ6e/PxvFwSHO3WXfJ04S0+HbNbZWnd13t6Gpupo3uUIlG/984I7Rf5Q+dj
xvoYHVuD2ZlPu6uRJD50KwKMes4IqimNcBWVlNTRneH6uIq0ZHP2QLaxZf2Y85PD1er3NVw5go/5
bO/bEa+nhDSjcIENF/nFUBFcNkUogTzeUzT8w+Yh0Y/PWyH4PijtAnzm1NfKwtb+o3sZB/3gsecq
vdzVivfDYUAoubbKgsP9JB8B4aCmO9N4Kg3YAMnMzD2TWQjo4P8Ke3qcJ17VEe/04kWAmURRVsp4
YynOUTMcLbSk66K19EnV/E3ssCOf4DvVa0ppVIzaGSp/17fvC1f4Izy8T9/XA98os/MqCtSn+zIu
FHhFlFpSbb0g7Juz6w/0HMKH6Mug25X7LiH3rtqCsIJpgHGVP004MxAmy/SCyjHX7a3oAFDgyJPl
VjcLlj7TX1M4u7ngbjyJN4oP1WwaBsqnAxyS2PJOJVzfZALcEZCV5VAYzgEhoQJ30WeOzRwlxANb
tLT1f+TpF2quKah/UWjze1cqJVh1xhau+BoMQzNx2M7Zgo+1wNcIsoJp5SAjOEdL5oujGd5UQq7P
9bgsJ9Ckw83NSCNtSwFIt+HnCQl7fPZDUwYrDXUzP4I7AJ0BYRpXJwpS9V4eoJfO0KAmUpttq68C
w2DvDzREU2t4uN5vO4aUxyk9jHVgk/jS+qsdZdrPtMNrSqB1AAl58spSOGOHFgwcyiKUESdcEQNf
50Ph0x6Fodavdh7Srq2IHTGnqr52X8ksEY6LiYg67NCOGi/vXQtCGHyt8feKgVcfu+KNPzHzyXnP
xbI/ajOtgPBZB8VapXo47bL5yMiQGlUtjPv9L9DqwPsPrUKm8mE9Qh4UqcBRHvp1eGh2uQ8Meyyq
3YdBc8jUE+CHgy8RwNBMoHyKL0UUhianIFXH7XsYwPHjcT6QziEJPq4m6x8Mq84FvH00euqF+Vvm
sRRMHY2PSoqLaZpmG/gQM0G8M5fHpwbGdHtpI3GMPNcj880/tnDGTRJf1bD7tx78CTsfUKmMgjVh
Y6N2IkIk1haD7q5oesA8ENyZdEb99EtQIlOak619RKJvZW3Wgu3Vkn2ldkYEAZagvBmCMosSMsGq
wHygLYrBuzHDSKnP89SNmKGvZosIqBQTYoN20ChyWFLApcBCwQKe5U4FBvnXsmv3DpqLHCLkQBok
wTCgZ5jslgxs6tpNSb0LYJRAOaAyPuTRCpNkAMH3vwE5v3yJpkdAzU3lQvrqNDfXqDICOqbGmuW3
wqtRxnQd17ItFMfgKxN0mv2lsLT1FXu2wdLvkd0M7aEwz4ZKU6VdsIS3xHF1zrL410IQGG+74mTA
3eDT64/p+ctqW2v7OrYTvj3tGtmUoodGXcQ9nSdk+C9uB/C2lsuIKQwg5Jr++jp/rn4aHWoDbPpx
5Wzll1fTCkqy1u80QDTrVOHpYppj+GlIkJzYOGmbur6gAMGXdYtGR8R248BiOquek3oMkW8vlZ56
OhTrI5+LaPLXYO6zk1Fxs5nUdOIorA4jg0zme8n2yGWrCBA6Gcs7RAjCvCWfKsGKf7GaSBIZymwK
NAFS22p/ekzCbsAGzevc8XXG8q8HfcVGVdpHErRaWRCjbT//z4aK8vSm2+sa8BhQBO7dvLfkEi2D
qIq3eIsKQiNSy2pu4Zw9tq2zLAvm6s1JHpjL5Agm4zDbaJ+hqinoppCmsqHYdbKmipbdB5adS8OU
OeNF2f3F/BGV5HNFjfqFSGYlfk/sjoTkVwQuE6qepGA+KUZhY2nTZnsh6G5AVidRWfA7wSsZJw8z
PhQEyjMknPNvo/sWQMIfLPHGLyYZMce9MQamIo5YE7GMgIxgx73KQ65z9X2CNmkVBJ+QIcglrnym
WXsjaZvpVU0thbLp83GfKoR60hMEH/6qZ0ZcOEaLvk6GubLuv2Y2Lu+40Nb7/HTKc4ucy1Z+r3HX
k+6MOXGjA9wFH0BhxZ1uBqhQrNwd7RQ4ng0lfCg61ZAmQExlCZhJrohy9caThCIXjXEEFqy6HKP+
88LkdYN5X3yy7loZEcBKgTrVjqPMhc5Am6ehWeoal/+qa1TrkIguq+962D8mrFas1saBXy0W9v1R
S2iR6LIKXkPCXnrtTz4yf1aJRLkjUNQlWqhqsqDYvkSGVLSsRmwqGi5haEjgXuDjP/5vDGyRFgtE
mz/5IsA4KrY0WzNztdJx0PO4TD8obyMAASFL/QNQomtAJTvxnvaca2+DZFwawx/eTDrVayGNfqWJ
uSRaGFBkrQnX/A1AVl8EXSgv80A3ohPVmz8Znel51S+1JRfdfObOA05X6bVaKvT71KxKPeas1FDl
/mhYiwQQr8g/pp0RC8aVmZZkuaTLh9qOgVWQKRN2jvKxUHYWgc7jwf+TNnMiCuigL3QfcyCqtgJB
EuwsBfLoxlIH/ge/qEwAPG2N7epibQsRs9YzxbpUGprbFtKskt0gLh/iIZndxiZg19gtAkBcZiPt
WWovSosfbFCrhQq63IvsNSPxjsLDuwuqopNqn6Phv31lRFivdUkxcHEYYAHTo6eocaLWtr8CtCwP
bhHjWn7SwwGh5VQ8WexCveaw8R3TqSgtHHi+qyiyLa3XnV9KdKdkwttUCIXLQnW5a8N0WkafXnr2
z+iUPEdLAR01qBsZDsXP/Ct/qO6IZkYkgvuG1jMji9ObEfuRgDltainxHHZDgyZTIiXT5UdNfpqL
Em0w7C8f8+N0vmHlpqTf0S8JPUzfqXBH2n5Y6ySuNDbNoIayFAZ0SHA51Osmibf2IEuN3ReiJ8+e
hnM+s/odRjXYQAtsoHQaseDHLVngywDBecQQ6W7Sx4N0ta/71G60fMEojB6skDhCBfBs6DO7pVBL
nz/EC1fusay4UeAoSoIaLUElzVT+TriQg/rxx0vnqbhYHUBSGpDv5kuQ7Mi004KuAvHbvYLkFXGY
p6AI60d4TRacYGh4uBQh7eRMEkP4T6rruIGEtNQT+tU57IQ1oAgE4avScs4EDfAzcY+LRDge8UW+
8sTvZjBT38N0UnGcK31z5d57uNjzc96ZPnvXrxWhUgf2/A+gaimlBU13qOZjx47Lb9SXS4AHZQND
ApYooWzxodS4KsBZ/8i4qNczcMEqRpfQRqL2Zw/1lRZP5XX9ZC4WoOiK6oEhFfUQeRzvwbZ3MyX9
PtKSRlZUkr9jALimMkWCLlUIqaqTS/8bftRdw2RFlIXfqePcUMOoCSE7sktDiLK5TKK7KtpezvzY
Lg+Kv4LFQL/xRhcS4HQ4SHJFVwI+92VH22HONADNswhMCOwcFwBRb9qg7hqccQYb1xc8gW/+qTJ0
C9imAm+U/LAWvbAegESyaMwtLOZk/dpsy+gdUqFiURBoQaXxlBbwcpZRrbIx40XnrFXv+aaw+NFl
pe7xki3wX2E7KCTp/YdtbDjpFxjf0hHPu1yAof/tgayZECIcyJyz91GoWU9dWK52WslBM5ClZxbc
TV2OzrHMU5zxUodNS5KU2qU0uMrfwldlQfdOYPjvIOtFzSOK3iAcAd0K0FRk9e/oChYI/p5hlYIb
I4tVDxDOJ079qaOvAchCLQkqXBFEvKbfdVndA6AadTEd3NeSPh3MGpa26KR+aNhLYO2hgyntVoe/
nyOJRVGi869wF/ZAS1v11XcChQOJTJKJXaj81n5g18FzJYbYUTfnhc28G9uF4i50aTRsRCop0GdV
D7j5snjr8BKXVnVtdwiPHSQ7EtEYJitSQu1ZNONYEdTu2t/tF6Ti5qjH7NcOO+1AVDxwUoRUOKc/
PNI9glCPTsnNBAFR98odk60H6jn6DIGPrwZgj2s93Hn7U+PHnY6OBenjS0NTk7MWae33/TnkMls7
Tn2kk4enFrWpjyKin2ihgt98Y3gLBJ6Qsvd5GdZzgCw0ZK7PTX2N07vFW4oTFWK3X64sHoiyNONb
xmPRd+Qm9WdqCpCKDl6VGC4mvWFf4i0dHzVBITwkonGMJH8nFyMviaOWRpOLZ2tMsSVDOQ9zfyJQ
YNNLqZUWQEeFmI4qC2yiNpsR6lDThvO3MVyIddLQsviV96+rc/e8pjv24VJ2VoxFzlfWoUcb6KOK
R96EMyxPEH5oMZ+NUnekKPaBEXrMuAQuDMNzP3jd96JyeSobabmT5O2JaoUXuTXRBXsK+4Pcrb5a
T6jrNBY4qj234TtZy5FqH1LiMq9+phO3A0IsvBWJmAUgnMRRzdjMX7P/Q9ExBv4dsufesvRsuZJ6
MnD7a1xFGvumEENoE3LPMfbzxMwCqxjvANp5obj+kkwqXxmHByMbMrZkjXEbVrU1K7lxdNeuX3iY
j4QyrdTDIHJQ3ZVgfSu9mnKOYv+bX+xwBhpPOX1DKQCt/npDDrNy5PWSM0IpRzBiHjedS54GK2wb
2DX/xZdAh77HijFMBAKYNZPlZ0Cza8567nxaJfqt0pT50CqkBROTE1qLr+lMDmUrM1IE5cKZNV0H
6cZkAOUWnZ21F7qZUXB7W/I22B7xH40IizvkVITdNZeKC+Nw8PzD+rcqGN5gopUgSlw/WR//KWG6
4jUzBvvkt+UPjVTQ8dNdgG4PfUewXeepzyRnPdIbtyEcMuWzv47uNC6s23hyir6/labE3pFcJhG8
WtAg9CZkigdCVtPMGrNJpCzAn4QuHgAWljUQKUJGZE6739JqA3yF+XK9Tadhf0Te6oMxVil+BSVZ
5QXT7XIgbMDXsnxQTjstbYuJTiU3iviQT1lHmSznfickji4GRmbucuUnQiFf6zUNf8WCNKwU9thc
8JVQqzj7mKg72+s+qhRhi2nfNo4ROP6oI/Hhlpm6O9tkP5EeWoVxmc8o7YynAFzuzODTglVAsLHJ
XdLkaFFgJ62USPCyKP1fYlmKFXnZ40n1s0xfTQxvdMr2g3WIr8iSDKHWpcqUozlnLVrMgZDx4RAd
wwX0V5hEIEa/5tb1wt8OlwTXNjXOFDL/3nuBBnhH4Jfn8ucWO4D576SVIX0i2QhvsBpxNmbAGKbr
0y+E0Vn0fweMyF3oDdBH2oKg0TQXvndW33PCuDKptgY50q5WIoi+e6Pc4IMc0/O6yIqLvZnnhE7Y
sErpvA/lg6qnRRcdJWnb5nT91iHJRBxtsX3G0micJQoEldaydpUUOw/TDyBdLCU509fDvPF7N/0I
plBCRY7UTKYlk9Iguqizs8ZG8dt9huT4r7TQD7wAwIjuW6a2LfkXd+oU2wtoNyibGl7rvdYaQBI3
gAdGN/M16me9v7ys9r3FhGoFbBjtaCvVkPASam+aiyYJe1wST/4WoSvZlz6jNC9LqS2eXdJ+qd7P
gXGCJ5Wlnkbnzs0qf9jBEItzhrEg/3n73B4ts0U36DrOWlQy/9ClyFnRqs6nDeS49h3d8mCiZAwZ
2KKpEKJd1UXT/EBgO+JxNFw3GIwyU2+atyp298amQjFu1HXmW7dpuK7qiu+Y9OG+lYAoS3gsGMXD
L3MowdEGo0NugG/aIJhJHgsxXiuf753YDUswSqr/h4vwyziHQTaCGQYDb3rnxZamSw7wv1ffiHVY
reqGCYk0b4FGOcdqdF4qzLkTLkJsDGqRXwAvP4OU/aKII3rYDnmD/oFRmI4gUDpQ3By7OrvqNus7
QIK96j7NySUHr6VFLWqVDwWFCp1UOr7/nmJgaY6BvextodzT/vcsGJ9JyvGLFdtn4mIufCTOP9Tt
drtZamBNFJ04YtFeGKbisVAJgQ5qbk7xdUqkq1HUKWn1SQDRQ8XeQWGrae8cu7fa3MQ/sSC/5DW5
ppTWQkS2KSUvG0z6OcOogrZCC6wo+oT0q0OU1KYvBdmR0VP8vJyoNtrHAWd9o99an34vzPhhOJwY
RlNaN11RZD2u1mz8FGtWSZUwBme8NZAS2DsfVLMYqIQebUB89Ezr1mGST2ID1zo7fCwkHhesqICk
FJjsQ5YL6vNd+vmS/lcIrLT1/BkdiYXnY6J7wYFDbnK1nWvWmiI9mV+o+h6BEs4uVbYtDM4sUQTa
IcA5LeycCSp6Qs6hNS1FZnYNG1Pt/kLay1FgU4eUyARwj1mGv1ZgkAuM2zWImNe1v4Ha3xInWdCL
tHI8spJNLhwgvOs4nI+vaitli+bB/IAizUBeeE16Ah3pQofx3wh7+qWs7HH3Q3brjDAiefqoDRdN
VoyWsgeL4MGgTdSId01jJ0QT1OnXthxlpncmsB77R1I5V7UT5kcIb4OYCvYnt99zKVP8/M1vLHo4
eJqoN1H8foezdKX4wSNVBHVTWKREMhU1zwjoF/5xd0eKTYTUwpPgdD/lkr3XEd6X+XMaBq5LyisN
TNWwOX/+phtC9Z+2/FRii0XTV+6x/Oo5l4V/0Ti+J7SZYy4tBfmlWWNqpOTwUV5qxrkRzPwAa3dr
luE29AkOjdT1hghDz9Tta245/pehRNy8Gv0Zbex/o/0cR+kPZ9CxLk6+RBmvA9F17pQjT0JdZYmD
sUmJO9t4WZeqny+crm4G9xBO+GsUhjbGhXRpNYWcNlsYWZnWtsLZ+NCQFV84XZ7HXDR0519Hqs2d
rBy2nK18UZVvPaaaBZhe6Dz9Vbx1IaiU64raMimLAIqDvnSs9khi+67qC1BqubqsYEEE+dnJhGhX
2rhVxsFt7Q532vSsW5yZiz+uyrY9qdj8Wl/NkkKq0D9vqmZ05yWA2T6MbY6cXRjgHfu/j9wRrf89
0wC5xV2HKcGMmt/cGDYF6y0WdnWWkJPb7bH/0FXgNMQZJorAvyi4hZxmWB2VWaVpoKCCQ/Trhq+3
J/XzVVC7n4LcOAjgytZvUJx50fNaB3f4MshbzjGW8fPYOzV09qEgZyZRJMqYBPCXctGhLcR+Qo7p
TK5AVx+v7Jp+Mi8rOzdJtxvIR7ySoXFehn/nLbyaccyvujY13w0Lq5TR0G1KgGVIn+2FOVgfGe9x
tDYubGwLgm0UeFtImZXJIRUfSd/gEDJTEKfGd29q4JOabvO/aDm73lMjTZ/tp6P6t/m+8UghJ3W2
2sW83i7gy5XUOtM/PnSwEqqqt6ZSheC91RS8Rp4ofeCyl0dm7vJ0k0m0ZCZA62MH7Z6kBJ1q9oDf
T1Q+X+eNTjO0oNUmj2l2HDWk6MHZApdyd3Okb9geO6AlSSFpv0jd9Hq1aZP+cNkOnpIUO0SGZAkt
xm7LBoku05bx4u6LkDKKPGp7AHiZc7XAMn3yz3ajvMf5zZotO7Ld2UxVoSiF0Wg1e0B2yFGVViwf
So+5Av564MHmU3Lv79EaReH1o1hBftessv9oPXcJvmLaHNXZ4Re2SBoiWT8L8UynCshmkRefaWgw
qimUpAgHptNWe3nDqDuWRNd/a+QSKJ+a2CWw7JZKN5RPQ1Eq8zKXC5sJb91QBtx6hqJsLLUFwJUp
iVGTTr56sZ/c+dlbl74ia+DfBrpNxrWx6l+Mp26xTI/eZn7jCpjpgd4pwpHyOK16iEr3OxDmI5CG
GhfimRpTgiRjjR5Q8GUK25wuIZztlWnLzIR4Lk17Xho+8Q7eYWRp6hayTLHxDW7K+qdB8cYsxl2I
TVtQwQ8F1jvtdKbBwOmAeGYmFJpewJLC9RsCfyZzmN5AWJVvqdDyEFrfequYervrCQKHk6Aa+M1k
SMGPd/GuwDG6Z7vPsna15FWU++eW5CPa/Xqhkrg+yKTZ+IcVHmXlenr1DwINb9v2EPZjvzvWh9NE
fyuY9x1MKrldJG1Ro9O+hzLJQlZuDw1MM4BBolStrXHIMF6/auRo3SOXGzZ9pHIDqwWf1uVVmxQC
UvWxv+tgpPHjHwZNZ2noubavTp8lXkIy/ZjZnlRK1OJLSFRkToEInItao1U1Fm7+OKFzdnIOepsH
0GiVeYiaV4r8QKVU6ZjxpNpH+qlAJEbuV1WRoRJYnN5twM3whDjaLRSpW3c8lnn3l9ngNHbnrbxe
FLjikR5sj/zFrzethj8v2acUyxlJ2ekuEOaQAk66cYJ9H6lUwOYrF3UNi8UCT30vmp+U6OdIPg4s
7qxqpQJfVLLG9OIFe36b9GVnlTNSaUWLA4rCotUdt+5o/ag2xExQHhX8Wa923gsHe4UfJ0yNlr04
59Zefekzph6BF+SAOL2mNJ6o/LrOdlMLMO7HzPKzbzZSDW1t1AjUrAy29Lp8BlQnfpw/dBWZnRQd
oophT/zt/Hsgb6g/82gsNezUGTMo/VgBObY+tMuLp9caRS6g/c7Atr7hmIakUVaUrNOzXQUdP6hG
rf5KXkrB3eT7XgapzjURc1rwW1ox0REn37Qu3N3wx8pTx3gY7mCWStcDC743zRCo+BiXj7lgx1El
TKSXzkmwYdEN6MEX21Khnp3Qs08MuLRjeHF/yRp+boGARnHCHZnm0LSIOlz4Z8YYoyIzYUgbzZ9K
hmW1x08sJP4NdMc3QNh33yO8HmI+tH+YlixohWAixeri1ZqyFqk9MiNDIRPe5hm5kNd98wwXBICA
xOnfBzEC7W8n66uYbuuzdIj0kiyFJYNpSMwh+Oe47UWxFO58R5Eh3ycrvD1+iDEPz6LRzU5oj8Ro
VawuXttSCnOB6T5mBNITOGgdi6o5p84MxPc=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
rKWwB0sGGUajpurVPwhHzgsZATzg6CI2fy5teGZgwWn6RJSxvVrm7X6KC1NlYW5YtUDp2ese/Vrm
bw3OqIV60Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
BRuqFpGYGOGwcHOC9ByqxsqWUs+0okjDxEXI9LjsXxEyuWJLFUE7YYzNDASAihgXdiZINIm5es9z
yyLJWg7azDkuzQk8G9FmmXCb4GMcSNpaTGa1FVepRSL9Yvq1uMN0rfkU8OoTCb0JTco3mn42K2KI
S1jw6CGiZKnXjxgHNBU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
X3xfyzvjrmPkaI9JdFIRWVWKvQVaKvW3xkPmxmWB+Bg2oVsfAsBqh2i46hM/Bcj4vTlgRohMAtTw
mZrr7U78E4bYF8iEtFKLdIJEd7hVOOlmDwsFBDzxg0k47kX9A3ruJ30LrjKdxboHAuMIaT/XR/sU
upe6flMZr8VBlv8re7jyziDyWZOLqFpjufskTfv4OQj1KszofT4kUnArUhuQ6UVlh5i6v/pQEzIn
QBP9XWEv/eQfQZl33K/QbbRAZIttPtuWp1T04bWkTuCPPKG+pDFGGGHJZvQDtAaxZSkHqZAvfqlI
CAW2rOiYEadE7tUwZCBmG03wqqm+cZJmCFoaew==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
AUXv88ADQriH8V/F9F2bxLErHxhqOWkmnlCs9b253d+OgRvIOLCtaWRA9DjnqkOKIf1wnvs/R6pY
dJJExfXVZOjD4nIH7uFh77R1TOSQouJzgmqD+K5HYb0maU6PAGIafeBzcUv5XN4HOOPvm67+oI2c
ikEGUjjanBNxts7eGBk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UZCooc8nZi2nNWJ83Gcm6qAONngeeaBUnqNHZdi1nOU1iRX6MguqeK1oMSUjP/9bRjlw7Tp3sNmB
PWJn2GGi3l8Qe6b7auDrjGMr0IkAvVTyrVlPQlMaseSN4e4IeWhVyNWjm//n/TOKlr4NMKKu7xlw
UYk+ejL3Bl9bd8/cGgsVR5ZkQQavRAFBo8L2IT7ML5f1IYG78bF0KQzrmL9GYFMnToP9B7kVR7Du
Yb7rcfK2Zazdh5MpYg9XUjLic80aZcb4+8dYBu7XgEp/Ar3GApiNMnYJUmVK0q0n9Er1Tqahdfht
jdB1SKLd/YF5uaRclGtmIoZjAK3M+1SEWOps9w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12224)
`protect data_block
t5Spk6yve3uJ1YJ8JkRzUVqRYSeuRX7hvbRJ802Wf+RbaumUpGUGs1znFzR00sTUqUlo2CM6n9t5
idaQheZ7CEySEBoOnXCDFAPgPh8ykyAiFL3Y6sdSpbifGT0J/JOeKzMD5+nIp6kLlUBQc7VQSeug
M59+p40cD2Inb5oFM8hep8qN/6JeN/AvWyjNarzBXpsddtlR8UubbsDzFOoHP85gMfreqfxKQ4mV
L7Rk+vSOBcAjasibJdt8lGIhGi/lyefdAUQVTAcr6Rk65rUmtv0s/zold4FRI0PmGoGxfBownUjt
ID3OGTorR57ZiwQS9SYT/JxWJc4zudrYR4fD8DMzWdvENN1xnOhzMhMHt+838ogv5ctRUr1L6p2O
rtwRmv3wR/GKlGn8ybNwInmjtK4+BNX5gap6mk0YnCG4mJTIiP+FaOoM8wdxiYOIdNIw+rUEBT/r
F6GFBxG8/5onUxfWtczQimgRffRR0v7VnhSMzy2cgMSC7RSfU5tBTVhvUjiZIwBwd4dh59wwMbhe
ObgOq2fTje9tphNoAT3WxoQOthjG8xxXRsX5sR0k7TcuvWX4nQV9WbYTs0pleUmspnq1k9Xs0EIm
W3y6b9BoMzHXGL1IE8hJYlJd5MJzzouUlPN9Tfwh1wrNpCDlmJ9J4GDclsOU/CZjQsWM5EUzV+OH
J1jcgKJeqyL3hOLIX9Dzt78ChPYHG1qg0Mb4qDP88S3pODWbW4+1j2AsD7uCWlZNEuMljxUnEhE8
FIE3ZCbePEIUPc2Pf6/43pOUbTiGDWhWlgErsC5o1dI6noSg0LkHfdLy18FHnFWX9F4Ot9xbxQNo
Gz2CBeKdYc1PWDPlJvrALuh5AkKAz0HEA+nOrvYQQikIUnTo+jrneOXHX5udeFGKOGj7cGhNtvlf
Tf9HT1+I7uysbP5f9/Vy2tM5W9ioHXzlY1KX/AAIXi1jyj61mytFLzgfuX9qQ+d7eZQg975Qw7wv
2K3Rs5rSBCYTDlyZff8DwG1W75SxZa5ZEUnq2iIUAu/K7a57rlg+CagNL7UfcqLTet7lwWRb/36V
iakB2GyZPEZWgje1bPPgQp1xBoLyGizRUM+wS3Vvf5n/3MMSjth8mQJeFKioXxqm4h/cJw3QGSI5
UQpah2uMGNMkL9oOvnJ9B2m+nLKg7VNIXBGxIYAXGhvdZkHt4VLzwYGcaGFdZa3OnS5gjN4TMRly
fi6w4xlKfDC7FwkEBAFjRxbHczk1q4nNDzpStSec9d5uCH3awkL3L0IMNdShksbCWmv3wwEFhjOk
SjVTEdwHmcA4oi4aoPvyiGDR1JKY7w7HjpuqE4+zIGGQkcoOyvj2XQx7JThEuPl9ECrZb0TLBBDK
bVRSzEy8HMp850gBd9iZCkVAHfMngslcOITnvHBJ4tFmHTwKWmxUxCJQ5gg89B07OGUhV1Q+z1jG
me/hXjX9OUPElTDa6TrxMsw/u+OojNDTVFA8X+D6laQ40t9oXuk0KBLM2bdF8iNGxHL65Vp8l+38
RPifxux3QEZQW22MVYOiHY8Wpkxi8t6CP0qQwMYn4yC9yAAZYdFyCJ6i3Q7BwXQezdhvpEyEH15s
EawpqFjDMh1gp/QeoJc4eMiWdTRlR1MRpchkVSM2AIbdntg04ShmJIDrsoseAyfot2a/M6/3k8tg
2ekGAX86Z6p21WYEj+pBaBr9yiAyMfxzQeEGFIJli9AMB58eQJwXewlkB3BRp3bxqFeUuHdgBK08
HNzvjIpo+x+asZypiv1UG9P5yt8EJCVQLd55M77zucbLyq+9Tm15/ZrpMQiVQKtWwhGEFM/LdLsD
eOpGAo58unYogZ9jd61lpWzXjfk8K+1Gk5Rtj6GiuxaIOC+4AaBRjHtq2rot5XeTUEeXKPOc0iP0
SSJvQlTRnUtPLT2oWk+FaRwo8kG0Z5pnY93pyvl/GJkDHomt7zBb6Ii1YEesPyGd/DOWVShIC5UX
YzP2NsqRNU/flC/VJIvO3TqEyLi3DOxbzo6CBBOz9FGAO+JU3c83f8ReokkGQPChk8pO3LTeWZWT
N299EgGOEzhgB8EVBttsR06SQ7mnQqWKhInWrSCz4sn0qPhjTXfnqKWeZy7BreuOIoOviLrS2NYv
qHuYuMcnxnEf8jkB7HR8qx9yRwaWV8iOoG/QMCWt4RGLL1zZVYvwqeoH9FZQDcjLp20a2sQPRWdH
ExiZ7RXUn4f4MvIjQz6vuGqqNnt/+6HHpYhvRcdyUJEpPCA8bTQGvTxcnlso7/c2NLzXIkC9bgXV
bu4/DPLvHs+sCT/c+PFX+DLLQfSNW6ccbS+XSkti77jxD1xeot+dVvpsvxYrNQACiL+tF75evtLy
eXfXPlETyJlEj0SAF1sg4n7F3axNpo6T7h6LkFUgPwXJ/luGCQCV4nC5SOWYh3ks3wVCist/63ob
oQyj9LmJHDz+TypWnwqEufwnUMbf1155GsRyTcDwcN7eH9FBtO2WaPfmGqugOND3SNl6xuddm0fZ
+fMZB8vXcCRf8Me93X+hqMDcuRWzEbD2WeWDqxY9Y44XuBb0Up+0jn6fsrzjQe0nIBXyPCbHO+1Q
65qYy1YXZk4xb5PKb2dKUTNL3l/uJMwRE4tiru1XLfdfgL/7DoDwRJOd5ZwH9kNmhrWbppH0RGJh
woO1qE83rK4VGj+iTeY1etxKSiMPCKYxrvkms+cdDGsYrYgG+xgsoJULJ5Lb6/B7Afxz2WGj1Wa2
w3zzV/agOpG2Tg0NYHpZAH3t5JbIg/LnzvjV8hfqflx3ISnyqkJls6/SOPLLpR79KSDBtD4PILne
AO8cxuO7eV4kXFbQLFbjQkvHi4t+WnQ+TDOxbKGEalVYXrfGmtVx6q9+WO82B4ybbv4A5/9VwSE2
TeRlzDFUY/7qTqweXCi77Zd35i2f+CR2tEn/qOoVM1/YqhzbnfdGZqk/H93gSFcfd5mI9BgQSlOp
EiB9pUOxjJb6VS5Yw1w/DJHyiMXvwtOXbjIQf6y6EYqO9eCnONXjRZDmhEHFKDaUCKZSj0PXwQZn
48YTWU477JtQIEfRJcvsjN3QOuywTXiOsoEQcVLv9k8AUenCU0i8flflczz4ws+fohE8ZUpaTAd/
+hmCtlS34dUNMi/ySWLj9TEdh5E++trzjKG0bRS/jq6LXg3QgnKsCeHm3xkqdanznPzMUEpq4Plc
p4lxpMo1ej2vPeNs3pM3+WIad+XhZa4igdbtmQ4y8wQ6uJNA9/SlmpC8mu13lc2PfVMk3AO6K6GN
RUAEekBGZ3ZNLm3GoStPzyjjLqfaQdquC9epQR344gTNFnt0LMY2rokCWwpOLg6CEIUPxDDaf8ly
U58EYklkxVzV29CR7WgT5F2M3xI/zoCgltq7OWyQpTecKtzImUHGO4vwHedF+59J5BPSjcCw2dyr
UDOqt2FosErylnGyVie4L2XxAfjIxXA+2ivJhSe3VrozHSPUOAXa9Epcj3RFxLxM3PPMeBFgmDba
Bh6wk0efbRBdKInR37PkVOvNHLnAp2Viwlbpagrqyy5i9JEaWlo8DHLLOt3hSJPP/cK4AKEUadGQ
uxiVOA0lBQc2jTj883rz8KDflubh7hGTdwuxxNs8ZKgt6p/SXyTQGzXlMdZzD9BDBBszK8k0sKTl
sBHJg+hcv6aJ2K4PTWZ7SyIB6SundFTIswsh6e9JOZkCtWN+jjJgbf4y5gVAnjQUZ4DqNhcFXJjD
0TcZlgbOuhp8fU52OtXGQzS46IppFXlWl1UARmrcAST++wZ7Q+Ex/QQddavhiR27Ru+AUjGpGxjH
3M6XMoLbdcCmxaVHTKVACZWotIPdN6PjaUM0gZ3KjPyRRISgU/2RSJJ20Rww1M5KcFuT/no/7Vaf
5HSvkEiFY3B6zLrITtUi7XZtrR2CqC0ViPPZmV8gZMrIRGwhzXVoNO0vLmObcDpWy2H1RDeTpdbl
IOEWWgDnUhjzfbTWzIg0kfrf6yvotmSo8b9W4gNbAjW2jlRIt281MPq/1P9woLtDR5iMYaqf9uIU
xWf3j8FrNEGX8ZHFekeoSEhyVKAZf8eEvzLawlIoHNrX4MHqDJawNrdJmk84VDDeAfxKOpVCfYY3
wkpZqPls84YHcJVAGeJGHs+ILann2ztoH7fWsO5DUbCAkULwJ0M/OIWcMdlRTEpsvRT1KiaCT9oR
1O0EdgrSUwgUcK3UuIie3gGFTErONYutjvPfm+1n3H25MCv3xhF80sDYh1m7FC7/aJllG2WTM5nG
3QNfBKNvmGEej5gDYQ2rJTh688+Letc94vSNOnN96shi9aTYh+G5eq9WCVq6MxEh23xkZeAQQxC5
fpXiMRJMIdWFlmIa0QEZUbZ3ycR8IrNg6meCW9KuTedefl+JxNq9e1LIk5nDS06Wakzzwr+/AgMx
0c/k6R2cIVeJPlXUmr1Dfeebk+yeVQ7LijwNNFngkyCiw5TDXg5V/vWILNImm0U0UxrLbMSNVTVM
urtezlUUn4UyhmrgLJHAYt0VA5wyKtb3IIZxYpeleWl6wt2/vwZgRXOmEtQO/IKS94Wi1sPh4fjH
z9uqlim/uh9W+B3DNQo9bl4LpVhZ7h5wW5na2YiHUtuoN3E/YR5/IJyCXTJJea5CvtebTq843Za4
dqCqQqodRtdkraa98kjxqYJFI4m0Afcu8PIrRLFnKoys6p7CR1c6SlgudmFUieyZrsacDxi8ZP+Q
Li2NY+9u89U7SgKVzBolbm2PJAKDupl3ddqGJM4mDcMFNs47xIrF3lWBkXvXhW8dfT3DKrGaImvP
6C34DiUakYDHzKRSt+/k+2CBxeSegqLn/5U/tC7TYyu4P8aY7Husf4J2vwBxmatPTSlUsGrVT+uT
WeURFm5y46cZ/2y6eStVLR2A+OKh4Ks0uBKIGAo5w+FBOna6zgB7XVP8o2LbHnp2JCmTA2WJhOFC
g19RQ+pGCBLqNvfwqu+A92lBVpf/dFV5KVLwcndLiDN35qPnW9vmuIdJYjvj8QKmq/jX4fWFpc6j
cEmMxshMhi0HlaF/r9/dxA69OufvPRzqbmA9DqxXASuorQm23V/AQqkXZrV3OOba/PaLLEOhqBOT
L61oEeds65JH/EN6N8hF4T/sUZayuM8b+apWHqaeeMGdaTfSiID69oGTSuqInuRlktL6Pz9z1LV+
QFKKX1QDipyocsO8KaaIyfTvCkJyUOoN/HwnJxX3abtLC5InD92CY+WaBmPrb6tTw5m/kNhsi4q7
S3U7tL+q7+ouirgGvkY/uoxaunmSIKhuag5LvuSej8/+DYd75Y9moaNN32ewPzXo8LpBFYfrJBEm
DzVq0iZTAaO+3TpAtwUi3dkIyN2kNsTL7kbmJlSGZOVzh75aYV5IxleyFxwRVm+jJaYabQqyCrkl
0dnKXd+D4dsDqchiamAKpGe1X6RqIzDmIs8g7mWZ1LBYf3FOfspn0DGXQ5lHMFkcVlDzYcMosEEg
K1XlvTxekpQP74O+saPLTAMvek4d30pr9MCZMGAgh5U0KleS92n19OAZQC5IgdsIsYavnNKdMUeh
ZupuDS9cvPNFECrRPXiIXXqtYGRoQnuO+IvKSffHXnQoEeAnaJhKQj/FEeaQmtZzYflM9RO4mnL5
1gb4u0FpeA/nh0tGN3haGDt9/zULkdDGzCM3MYyJu+xcUNaxCtFqM1s+kqH+cAPS1xcJiGDj/Bgd
k8pleBG+5U30pOlEUMxkHlAPaW1VRKJD7Rdbb9lxlWbJFnH+95OA/FKVPYdmeq7WUcjar5Qjw58y
kjBoTtwmbP0P1Zgoha3qwCGQx4eiAjpmErNxV7th0RqLYvjBdNyHzGftdzYoAbbMe+EV1ANPgBiF
Q/hzJt4gaBHKaUoD2UsckFO+kXLXyJASNPkGHl/Rt83h2P3jkgicP9Q2ospUg07DJXcdp6NcdDMb
uX3OBwLcnxfHXY9pD0QvuuuuQVUFlY9AlSSizWDrFjbuAV3vMVa/kE8cC7OBTz7OYfEyPvRs+qE9
9wDh7UwzEWWCcWwFq/fk22kYKp6I0/bs0MZlYju8eYwco/3vDchMDBCYZYLHubDVSWJ0PaHb1/6n
dFCVIXvrEZgIkZXCr67waQhBlK7LJRt+ppKyuNpAJioBYK6NiX545XHy1lXppuSst06QF66bXdLw
2vJ1xHClfmFcXPhO60rPIPypdTL0KTObzGJ8TOcQaE2L0b7IsHnMR8tZy+T6YBoJCNUB/7+chVI8
R8BE1a9mCRfD8ieIPZB6iJ34ABdqfMLGbNEcRsP/lTUpSIo7W2+8bAFjTLzUm8IlZu8IjhQs54nE
KTf+y5bOTBPWH2Fn4p1Nj8BQO1iRbvezwlLCqlmSZB0FNRRouOKhp6DzRWQ9bS350ZHYZLnXKhy4
brrTzXX/pCkIQDwbjaeAUqm67LOej94Y7O0a3lmV6VBHva612iw4x4zTj7WOwKZjiwhlOvgFlZB7
vMAi5028dr6hx9PCDbePcA+AR8MaWhyXXo0tKBVdFKNy9W0eA8k4O3BDsgmXFtyqJhchoOExpLvE
2/G+MYDSa0SlCwbzevtN2YJGoxjm0oNoPm+BOtIMOS/TpE7L68gFyxPUvsPQS48LMarTDzv4onFw
GXU2Ah2QjiDTW0O6iavdPrCVisETovslk6oHAcZR3H2VRPBt/ift/ZCXuirUV3JzOVXUY7wIdNhs
h8QXwpjIm8G6mesNVPoLkh0kkvE+ZgRNuYxRnn96j/rNJKFnGYaVLi0iBuqgw96s989mHNWx1l6p
PfH0SDNAyGFgV0lJMEm/4U7xCueuSrNTy21EolR2gau3c+Dbggb3BsveF88jY9muwG4/nyy6svWj
ck3q8cvnaPiBcxNjVZ0N60O0R6wNcLgk3zB4+YZpye5W7yeneWQMPGZAKr+DE0opmJq6poa26TR/
9jbNOfSEVoCwQft+TkERXM17DYt2LYyN0jI8ifinUyWn/50S1JpuRKmcExH1yjr/tkGEzCdlUxv2
tV4F/hOnl+O7FKEHbU9DEelV+emS9pNbPLAWIAQ9Ol/uYYGoVT2zgknFBf+XM532ynnQPn1zBVk4
h4OZCK4oW7uAMnel05mgFsvhZCnMeI9BGdIgc7eZsztwNNR0xpnSPSR3GERN97XV8yD92p2MxB6g
wolHPYtyvwP7x6YU/hNP+1N848u/PgN4CQiaS1mjiHvWDaIMOwemxEJvjMZX4zjwxIUcZeluYOl4
26YQJ005H1uDxJhlMO8QT+yXcCD+qVPUPDlrUWv7fsnXS4UBrvOkEg2uTrSUIPcCFcyE5szrdR+H
akXBANJOs7CPbPzeb++YTV5tpUV0r56gRPn8FA9CddVr3IXsoTQeOQ6o6xiNytVbvwV6sAab8wJk
mU/hNmIVTI6G78cZ0P7lVQSo5+qoUgGm5rarcSYROOsHmZWMXrCaDvNNwZ4SX0AsKjcag4mxCYcx
fJS4nhv+1UnbjoX4epieaxzYtz9rID5rn7UVzSwRrw3RDGBYpIQYCNkUCTU7XVx1fpzUhSgR9RmY
6NH2cGbRsbSzzs/WAuPDx1JlfODxdsq7AszI1NHfnpwkkcMEhyhVgTBg9Xu6LKWeYINioxsTVypL
TASuTyOGlKW5ieor9XR53/F0EuaEPDb4ZUCI1EP04/u/W7VIO2vNOMA2RkrjJSkU9QIl2kx128VV
IZlrfHxy+Ooae0SgR4MIznzny12oG5kBY6CpYaN7Xxi9aYoWIuUtMsKUlf0EHke9GcRaSy1xJKEu
qB3ibzVcIl4npqgqMKQ6e/PxvFwSHO3WXfJ04S0+HbNbZWnd13t6Gpupo3uUIlG/984I7Rf5Q+dj
xvoYHVuD2ZlPu6uRJD50KwKMes4IqimNcBWVlNTRneH6uIq0ZHP2QLaxZf2Y85PD1er3NVw5go/5
bO/bEa+nhDSjcIENF/nFUBFcNkUogTzeUzT8w+Yh0Y/PWyH4PijtAnzm1NfKwtb+o3sZB/3gsecq
vdzVivfDYUAoubbKgsP9JB8B4aCmO9N4Kg3YAMnMzD2TWQjo4P8Ke3qcJ17VEe/04kWAmURRVsp4
YynOUTMcLbSk66K19EnV/E3ssCOf4DvVa0ppVIzaGSp/17fvC1f4Izy8T9/XA98os/MqCtSn+zIu
FHhFlFpSbb0g7Juz6w/0HMKH6Mug25X7LiH3rtqCsIJpgHGVP004MxAmy/SCyjHX7a3oAFDgyJPl
VjcLlj7TX1M4u7ngbjyJN4oP1WwaBsqnAxyS2PJOJVzfZALcEZCV5VAYzgEhoQJ30WeOzRwlxANb
tLT1f+TpF2quKah/UWjze1cqJVh1xhau+BoMQzNx2M7Zgo+1wNcIsoJp5SAjOEdL5oujGd5UQq7P
9bgsJ9Ckw83NSCNtSwFIt+HnCQl7fPZDUwYrDXUzP4I7AJ0BYRpXJwpS9V4eoJfO0KAmUpttq68C
w2DvDzREU2t4uN5vO4aUxyk9jHVgk/jS+qsdZdrPtMNrSqB1AAl58spSOGOHFgwcyiKUESdcEQNf
50Ph0x6Fodavdh7Srq2IHTGnqr52X8ksEY6LiYg67NCOGi/vXQtCGHyt8feKgVcfu+KNPzHzyXnP
xbI/ajOtgPBZB8VapXo47bL5yMiQGlUtjPv9L9DqwPsPrUKm8mE9Qh4UqcBRHvp1eGh2uQ8Meyyq
3YdBc8jUE+CHgy8RwNBMoHyKL0UUhianIFXH7XsYwPHjcT6QziEJPq4m6x8Mq84FvH00euqF+Vvm
sRRMHY2PSoqLaZpmG/gQM0G8M5fHpwbGdHtpI3GMPNcj880/tnDGTRJf1bD7tx78CTsfUKmMgjVh
Y6N2IkIk1haD7q5oesA8ENyZdEb99EtQIlOak619RKJvZW3Wgu3Vkn2ldkYEAZagvBmCMosSMsGq
wHygLYrBuzHDSKnP89SNmKGvZosIqBQTYoN20ChyWFLApcBCwQKe5U4FBvnXsmv3DpqLHCLkQBok
wTCgZ5jslgxs6tpNSb0LYJRAOaAyPuTRCpNkAMH3vwE5v3yJpkdAzU3lQvrqNDfXqDICOqbGmuW3
wqtRxnQd17ItFMfgKxN0mv2lsLT1FXu2wdLvkd0M7aEwz4ZKU6VdsIS3xHF1zrL410IQGG+74mTA
3eDT64/p+ctqW2v7OrYTvj3tGtmUoodGXcQ9nSdk+C9uB/C2lsuIKQwg5Jr++jp/rn4aHWoDbPpx
5Wzll1fTCkqy1u80QDTrVOHpYppj+GlIkJzYOGmbur6gAMGXdYtGR8R248BiOquek3oMkW8vlZ56
OhTrI5+LaPLXYO6zk1Fxs5nUdOIorA4jg0zme8n2yGWrCBA6Gcs7RAjCvCWfKsGKf7GaSBIZymwK
NAFS22p/ekzCbsAGzevc8XXG8q8HfcVGVdpHErRaWRCjbT//z4aK8vSm2+sa8BhQBO7dvLfkEi2D
qIq3eIsKQiNSy2pu4Zw9tq2zLAvm6s1JHpjL5Agm4zDbaJ+hqinoppCmsqHYdbKmipbdB5adS8OU
OeNF2f3F/BGV5HNFjfqFSGYlfk/sjoTkVwQuE6qepGA+KUZhY2nTZnsh6G5AVidRWfA7wSsZJw8z
PhQEyjMknPNvo/sWQMIfLPHGLyYZMce9MQamIo5YE7GMgIxgx73KQ65z9X2CNmkVBJ+QIcglrnym
WXsjaZvpVU0thbLp83GfKoR60hMEH/6qZ0ZcOEaLvk6GubLuv2Y2Lu+40Nb7/HTKc4ucy1Z+r3HX
k+6MOXGjA9wFH0BhxZ1uBqhQrNwd7RQ4ng0lfCg61ZAmQExlCZhJrohy9caThCIXjXEEFqy6HKP+
88LkdYN5X3yy7loZEcBKgTrVjqPMhc5Am6ehWeoal/+qa1TrkIguq+962D8mrFas1saBXy0W9v1R
S2iR6LIKXkPCXnrtTz4yf1aJRLkjUNQlWqhqsqDYvkSGVLSsRmwqGi5haEjgXuDjP/5vDGyRFgtE
mz/5IsA4KrY0WzNztdJx0PO4TD8obyMAASFL/QNQomtAJTvxnvaca2+DZFwawx/eTDrVayGNfqWJ
uSRaGFBkrQnX/A1AVl8EXSgv80A3ohPVmz8Znel51S+1JRfdfObOA05X6bVaKvT71KxKPeas1FDl
/mhYiwQQr8g/pp0RC8aVmZZkuaTLh9qOgVWQKRN2jvKxUHYWgc7jwf+TNnMiCuigL3QfcyCqtgJB
EuwsBfLoxlIH/ge/qEwAPG2N7epibQsRs9YzxbpUGprbFtKskt0gLh/iIZndxiZg19gtAkBcZiPt
WWovSosfbFCrhQq63IvsNSPxjsLDuwuqopNqn6Phv31lRFivdUkxcHEYYAHTo6eocaLWtr8CtCwP
bhHjWn7SwwGh5VQ8WexCveaw8R3TqSgtHHi+qyiyLa3XnV9KdKdkwttUCIXLQnW5a8N0WkafXnr2
z+iUPEdLAR01qBsZDsXP/Ct/qO6IZkYkgvuG1jMji9ObEfuRgDltainxHHZDgyZTIiXT5UdNfpqL
Em0w7C8f8+N0vmHlpqTf0S8JPUzfqXBH2n5Y6ySuNDbNoIayFAZ0SHA51Osmibf2IEuN3ReiJ8+e
hnM+s/odRjXYQAtsoHQaseDHLVngywDBecQQ6W7Sx4N0ta/71G60fMEojB6skDhCBfBs6DO7pVBL
nz/EC1fusay4UeAoSoIaLUElzVT+TriQg/rxx0vnqbhYHUBSGpDv5kuQ7Mi004KuAvHbvYLkFXGY
p6AI60d4TRacYGh4uBQh7eRMEkP4T6rruIGEtNQT+tU57IQ1oAgE4avScs4EDfAzcY+LRDge8UW+
8sTvZjBT38N0UnGcK31z5d57uNjzc96ZPnvXrxWhUgf2/A+gaimlBU13qOZjx47Lb9SXS4AHZQND
ApYooWzxodS4KsBZ/8i4qNczcMEqRpfQRqL2Zw/1lRZP5XX9ZC4WoOiK6oEhFfUQeRzvwbZ3MyX9
PtKSRlZUkr9jALimMkWCLlUIqaqTS/8bftRdw2RFlIXfqePcUMOoCSE7sktDiLK5TKK7KtpezvzY
Lg+Kv4LFQL/xRhcS4HQ4SHJFVwI+92VH22HONADNswhMCOwcFwBRb9qg7hqccQYb1xc8gW/+qTJ0
C9imAm+U/LAWvbAegESyaMwtLOZk/dpsy+gdUqFiURBoQaXxlBbwcpZRrbIx40XnrFXv+aaw+NFl
pe7xki3wX2E7KCTp/YdtbDjpFxjf0hHPu1yAof/tgayZECIcyJyz91GoWU9dWK52WslBM5ClZxbc
TV2OzrHMU5zxUodNS5KU2qU0uMrfwldlQfdOYPjvIOtFzSOK3iAcAd0K0FRk9e/oChYI/p5hlYIb
I4tVDxDOJ079qaOvAchCLQkqXBFEvKbfdVndA6AadTEd3NeSPh3MGpa26KR+aNhLYO2hgyntVoe/
nyOJRVGi869wF/ZAS1v11XcChQOJTJKJXaj81n5g18FzJYbYUTfnhc28G9uF4i50aTRsRCop0GdV
D7j5snjr8BKXVnVtdwiPHSQ7EtEYJitSQu1ZNONYEdTu2t/tF6Ti5qjH7NcOO+1AVDxwUoRUOKc/
PNI9glCPTsnNBAFR98odk60H6jn6DIGPrwZgj2s93Hn7U+PHnY6OBenjS0NTk7MWae33/TnkMls7
Tn2kk4enFrWpjyKin2ihgt98Y3gLBJ6Qsvd5GdZzgCw0ZK7PTX2N07vFW4oTFWK3X64sHoiyNONb
xmPRd+Qm9WdqCpCKDl6VGC4mvWFf4i0dHzVBITwkonGMJH8nFyMviaOWRpOLZ2tMsSVDOQ9zfyJQ
YNNLqZUWQEeFmI4qC2yiNpsR6lDThvO3MVyIddLQsviV96+rc/e8pjv24VJ2VoxFzlfWoUcb6KOK
R96EMyxPEH5oMZ+NUnekKPaBEXrMuAQuDMNzP3jd96JyeSobabmT5O2JaoUXuTXRBXsK+4Pcrb5a
T6jrNBY4qj234TtZy5FqH1LiMq9+phO3A0IsvBWJmAUgnMRRzdjMX7P/Q9ExBv4dsufesvRsuZJ6
MnD7a1xFGvumEENoE3LPMfbzxMwCqxjvANp5obj+kkwqXxmHByMbMrZkjXEbVrU1K7lxdNeuX3iY
j4QyrdTDIHJQ3ZVgfSu9mnKOYv+bX+xwBhpPOX1DKQCt/npDDrNy5PWSM0IpRzBiHjedS54GK2wb
2DX/xZdAh77HijFMBAKYNZPlZ0Cza8567nxaJfqt0pT50CqkBROTE1qLr+lMDmUrM1IE5cKZNV0H
6cZkAOUWnZ21F7qZUXB7W/I22B7xH40IizvkVITdNZeKC+Nw8PzD+rcqGN5gopUgSlw/WR//KWG6
4jUzBvvkt+UPjVTQ8dNdgG4PfUewXeepzyRnPdIbtyEcMuWzv47uNC6s23hyir6/labE3pFcJhG8
WtAg9CZkigdCVtPMGrNJpCzAn4QuHgAWljUQKUJGZE6739JqA3yF+XK9Tadhf0Te6oMxVil+BSVZ
5QXT7XIgbMDXsnxQTjstbYuJTiU3iviQT1lHmSznfickji4GRmbucuUnQiFf6zUNf8WCNKwU9thc
8JVQqzj7mKg72+s+qhRhi2nfNo4ROP6oI/Hhlpm6O9tkP5EeWoVxmc8o7YynAFzuzODTglVAsLHJ
XdLkaFFgJ62USPCyKP1fYlmKFXnZ40n1s0xfTQxvdMr2g3WIr8iSDKHWpcqUozlnLVrMgZDx4RAd
wwX0V5hEIEa/5tb1wt8OlwTXNjXOFDL/3nuBBnhH4Jfn8ucWO4D576SVIX0i2QhvsBpxNmbAGKbr
0y+E0Vn0fweMyF3oDdBH2oKg0TQXvndW33PCuDKptgY50q5WIoi+e6Pc4IMc0/O6yIqLvZnnhE7Y
sErpvA/lg6qnRRcdJWnb5nT91iHJRBxtsX3G0micJQoEldaydpUUOw/TDyBdLCU509fDvPF7N/0I
plBCRY7UTKYlk9Iguqizs8ZG8dt9huT4r7TQD7wAwIjuW6a2LfkXd+oU2wtoNyibGl7rvdYaQBI3
gAdGN/M16me9v7ys9r3FhGoFbBjtaCvVkPASam+aiyYJe1wST/4WoSvZlz6jNC9LqS2eXdJ+qd7P
gXGCJ5Wlnkbnzs0qf9jBEItzhrEg/3n73B4ts0U36DrOWlQy/9ClyFnRqs6nDeS49h3d8mCiZAwZ
2KKpEKJd1UXT/EBgO+JxNFw3GIwyU2+atyp298amQjFu1HXmW7dpuK7qiu+Y9OG+lYAoS3gsGMXD
L3MowdEGo0NugG/aIJhJHgsxXiuf753YDUswSqr/h4vwyziHQTaCGQYDb3rnxZamSw7wv1ffiHVY
reqGCYk0b4FGOcdqdF4qzLkTLkJsDGqRXwAvP4OU/aKII3rYDnmD/oFRmI4gUDpQ3By7OrvqNus7
QIK96j7NySUHr6VFLWqVDwWFCp1UOr7/nmJgaY6BvextodzT/vcsGJ9JyvGLFdtn4mIufCTOP9Tt
drtZamBNFJ04YtFeGKbisVAJgQ5qbk7xdUqkq1HUKWn1SQDRQ8XeQWGrae8cu7fa3MQ/sSC/5DW5
ppTWQkS2KSUvG0z6OcOogrZCC6wo+oT0q0OU1KYvBdmR0VP8vJyoNtrHAWd9o99an34vzPhhOJwY
RlNaN11RZD2u1mz8FGtWSZUwBme8NZAS2DsfVLMYqIQebUB89Ezr1mGST2ID1zo7fCwkHhesqICk
FJjsQ5YL6vNd+vmS/lcIrLT1/BkdiYXnY6J7wYFDbnK1nWvWmiI9mV+o+h6BEs4uVbYtDM4sUQTa
IcA5LeycCSp6Qs6hNS1FZnYNG1Pt/kLay1FgU4eUyARwj1mGv1ZgkAuM2zWImNe1v4Ha3xInWdCL
tHI8spJNLhwgvOs4nI+vaitli+bB/IAizUBeeE16Ah3pQofx3wh7+qWs7HH3Q3brjDAiefqoDRdN
VoyWsgeL4MGgTdSId01jJ0QT1OnXthxlpncmsB77R1I5V7UT5kcIb4OYCvYnt99zKVP8/M1vLHo4
eJqoN1H8foezdKX4wSNVBHVTWKREMhU1zwjoF/5xd0eKTYTUwpPgdD/lkr3XEd6X+XMaBq5LyisN
TNWwOX/+phtC9Z+2/FRii0XTV+6x/Oo5l4V/0Ti+J7SZYy4tBfmlWWNqpOTwUV5qxrkRzPwAa3dr
luE29AkOjdT1hghDz9Tta245/pehRNy8Gv0Zbex/o/0cR+kPZ9CxLk6+RBmvA9F17pQjT0JdZYmD
sUmJO9t4WZeqny+crm4G9xBO+GsUhjbGhXRpNYWcNlsYWZnWtsLZ+NCQFV84XZ7HXDR0519Hqs2d
rBy2nK18UZVvPaaaBZhe6Dz9Vbx1IaiU64raMimLAIqDvnSs9khi+67qC1BqubqsYEEE+dnJhGhX
2rhVxsFt7Q532vSsW5yZiz+uyrY9qdj8Wl/NkkKq0D9vqmZ05yWA2T6MbY6cXRjgHfu/j9wRrf89
0wC5xV2HKcGMmt/cGDYF6y0WdnWWkJPb7bH/0FXgNMQZJorAvyi4hZxmWB2VWaVpoKCCQ/Trhq+3
J/XzVVC7n4LcOAjgytZvUJx50fNaB3f4MshbzjGW8fPYOzV09qEgZyZRJMqYBPCXctGhLcR+Qo7p
TK5AVx+v7Jp+Mi8rOzdJtxvIR7ySoXFehn/nLbyaccyvujY13w0Lq5TR0G1KgGVIn+2FOVgfGe9x
tDYubGwLgm0UeFtImZXJIRUfSd/gEDJTEKfGd29q4JOabvO/aDm73lMjTZ/tp6P6t/m+8UghJ3W2
2sW83i7gy5XUOtM/PnSwEqqqt6ZSheC91RS8Rp4ofeCyl0dm7vJ0k0m0ZCZA62MH7Z6kBJ1q9oDf
T1Q+X+eNTjO0oNUmj2l2HDWk6MHZApdyd3Okb9geO6AlSSFpv0jd9Hq1aZP+cNkOnpIUO0SGZAkt
xm7LBoku05bx4u6LkDKKPGp7AHiZc7XAMn3yz3ajvMf5zZotO7Ld2UxVoSiF0Wg1e0B2yFGVViwf
So+5Av564MHmU3Lv79EaReH1o1hBftessv9oPXcJvmLaHNXZ4Re2SBoiWT8L8UynCshmkRefaWgw
qimUpAgHptNWe3nDqDuWRNd/a+QSKJ+a2CWw7JZKN5RPQ1Eq8zKXC5sJb91QBtx6hqJsLLUFwJUp
iVGTTr56sZ/c+dlbl74ia+DfBrpNxrWx6l+Mp26xTI/eZn7jCpjpgd4pwpHyOK16iEr3OxDmI5CG
GhfimRpTgiRjjR5Q8GUK25wuIZztlWnLzIR4Lk17Xho+8Q7eYWRp6hayTLHxDW7K+qdB8cYsxl2I
TVtQwQ8F1jvtdKbBwOmAeGYmFJpewJLC9RsCfyZzmN5AWJVvqdDyEFrfequYervrCQKHk6Aa+M1k
SMGPd/GuwDG6Z7vPsna15FWU++eW5CPa/Xqhkrg+yKTZ+IcVHmXlenr1DwINb9v2EPZjvzvWh9NE
fyuY9x1MKrldJG1Ro9O+hzLJQlZuDw1MM4BBolStrXHIMF6/auRo3SOXGzZ9pHIDqwWf1uVVmxQC
UvWxv+tgpPHjHwZNZ2noubavTp8lXkIy/ZjZnlRK1OJLSFRkToEInItao1U1Fm7+OKFzdnIOepsH
0GiVeYiaV4r8QKVU6ZjxpNpH+qlAJEbuV1WRoRJYnN5twM3whDjaLRSpW3c8lnn3l9ngNHbnrbxe
FLjikR5sj/zFrzethj8v2acUyxlJ2ekuEOaQAk66cYJ9H6lUwOYrF3UNi8UCT30vmp+U6OdIPg4s
7qxqpQJfVLLG9OIFe36b9GVnlTNSaUWLA4rCotUdt+5o/ag2xExQHhX8Wa923gsHe4UfJ0yNlr04
59Zefekzph6BF+SAOL2mNJ6o/LrOdlMLMO7HzPKzbzZSDW1t1AjUrAy29Lp8BlQnfpw/dBWZnRQd
oophT/zt/Hsgb6g/82gsNezUGTMo/VgBObY+tMuLp9caRS6g/c7Atr7hmIakUVaUrNOzXQUdP6hG
rf5KXkrB3eT7XgapzjURc1rwW1ox0REn37Qu3N3wx8pTx3gY7mCWStcDC743zRCo+BiXj7lgx1El
TKSXzkmwYdEN6MEX21Khnp3Qs08MuLRjeHF/yRp+boGARnHCHZnm0LSIOlz4Z8YYoyIzYUgbzZ9K
hmW1x08sJP4NdMc3QNh33yO8HmI+tH+YlixohWAixeri1ZqyFqk9MiNDIRPe5hm5kNd98wwXBICA
xOnfBzEC7W8n66uYbuuzdIj0kiyFJYNpSMwh+Oe47UWxFO58R5Eh3ycrvD1+iDEPz6LRzU5oj8Ro
VawuXttSCnOB6T5mBNITOGgdi6o5p84MxPc=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
rKWwB0sGGUajpurVPwhHzgsZATzg6CI2fy5teGZgwWn6RJSxvVrm7X6KC1NlYW5YtUDp2ese/Vrm
bw3OqIV60Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
BRuqFpGYGOGwcHOC9ByqxsqWUs+0okjDxEXI9LjsXxEyuWJLFUE7YYzNDASAihgXdiZINIm5es9z
yyLJWg7azDkuzQk8G9FmmXCb4GMcSNpaTGa1FVepRSL9Yvq1uMN0rfkU8OoTCb0JTco3mn42K2KI
S1jw6CGiZKnXjxgHNBU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
X3xfyzvjrmPkaI9JdFIRWVWKvQVaKvW3xkPmxmWB+Bg2oVsfAsBqh2i46hM/Bcj4vTlgRohMAtTw
mZrr7U78E4bYF8iEtFKLdIJEd7hVOOlmDwsFBDzxg0k47kX9A3ruJ30LrjKdxboHAuMIaT/XR/sU
upe6flMZr8VBlv8re7jyziDyWZOLqFpjufskTfv4OQj1KszofT4kUnArUhuQ6UVlh5i6v/pQEzIn
QBP9XWEv/eQfQZl33K/QbbRAZIttPtuWp1T04bWkTuCPPKG+pDFGGGHJZvQDtAaxZSkHqZAvfqlI
CAW2rOiYEadE7tUwZCBmG03wqqm+cZJmCFoaew==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
AUXv88ADQriH8V/F9F2bxLErHxhqOWkmnlCs9b253d+OgRvIOLCtaWRA9DjnqkOKIf1wnvs/R6pY
dJJExfXVZOjD4nIH7uFh77R1TOSQouJzgmqD+K5HYb0maU6PAGIafeBzcUv5XN4HOOPvm67+oI2c
ikEGUjjanBNxts7eGBk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UZCooc8nZi2nNWJ83Gcm6qAONngeeaBUnqNHZdi1nOU1iRX6MguqeK1oMSUjP/9bRjlw7Tp3sNmB
PWJn2GGi3l8Qe6b7auDrjGMr0IkAvVTyrVlPQlMaseSN4e4IeWhVyNWjm//n/TOKlr4NMKKu7xlw
UYk+ejL3Bl9bd8/cGgsVR5ZkQQavRAFBo8L2IT7ML5f1IYG78bF0KQzrmL9GYFMnToP9B7kVR7Du
Yb7rcfK2Zazdh5MpYg9XUjLic80aZcb4+8dYBu7XgEp/Ar3GApiNMnYJUmVK0q0n9Er1Tqahdfht
jdB1SKLd/YF5uaRclGtmIoZjAK3M+1SEWOps9w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12224)
`protect data_block
t5Spk6yve3uJ1YJ8JkRzUVqRYSeuRX7hvbRJ802Wf+RbaumUpGUGs1znFzR00sTUqUlo2CM6n9t5
idaQheZ7CEySEBoOnXCDFAPgPh8ykyAiFL3Y6sdSpbifGT0J/JOeKzMD5+nIp6kLlUBQc7VQSeug
M59+p40cD2Inb5oFM8hep8qN/6JeN/AvWyjNarzBXpsddtlR8UubbsDzFOoHP85gMfreqfxKQ4mV
L7Rk+vSOBcAjasibJdt8lGIhGi/lyefdAUQVTAcr6Rk65rUmtv0s/zold4FRI0PmGoGxfBownUjt
ID3OGTorR57ZiwQS9SYT/JxWJc4zudrYR4fD8DMzWdvENN1xnOhzMhMHt+838ogv5ctRUr1L6p2O
rtwRmv3wR/GKlGn8ybNwInmjtK4+BNX5gap6mk0YnCG4mJTIiP+FaOoM8wdxiYOIdNIw+rUEBT/r
F6GFBxG8/5onUxfWtczQimgRffRR0v7VnhSMzy2cgMSC7RSfU5tBTVhvUjiZIwBwd4dh59wwMbhe
ObgOq2fTje9tphNoAT3WxoQOthjG8xxXRsX5sR0k7TcuvWX4nQV9WbYTs0pleUmspnq1k9Xs0EIm
W3y6b9BoMzHXGL1IE8hJYlJd5MJzzouUlPN9Tfwh1wrNpCDlmJ9J4GDclsOU/CZjQsWM5EUzV+OH
J1jcgKJeqyL3hOLIX9Dzt78ChPYHG1qg0Mb4qDP88S3pODWbW4+1j2AsD7uCWlZNEuMljxUnEhE8
FIE3ZCbePEIUPc2Pf6/43pOUbTiGDWhWlgErsC5o1dI6noSg0LkHfdLy18FHnFWX9F4Ot9xbxQNo
Gz2CBeKdYc1PWDPlJvrALuh5AkKAz0HEA+nOrvYQQikIUnTo+jrneOXHX5udeFGKOGj7cGhNtvlf
Tf9HT1+I7uysbP5f9/Vy2tM5W9ioHXzlY1KX/AAIXi1jyj61mytFLzgfuX9qQ+d7eZQg975Qw7wv
2K3Rs5rSBCYTDlyZff8DwG1W75SxZa5ZEUnq2iIUAu/K7a57rlg+CagNL7UfcqLTet7lwWRb/36V
iakB2GyZPEZWgje1bPPgQp1xBoLyGizRUM+wS3Vvf5n/3MMSjth8mQJeFKioXxqm4h/cJw3QGSI5
UQpah2uMGNMkL9oOvnJ9B2m+nLKg7VNIXBGxIYAXGhvdZkHt4VLzwYGcaGFdZa3OnS5gjN4TMRly
fi6w4xlKfDC7FwkEBAFjRxbHczk1q4nNDzpStSec9d5uCH3awkL3L0IMNdShksbCWmv3wwEFhjOk
SjVTEdwHmcA4oi4aoPvyiGDR1JKY7w7HjpuqE4+zIGGQkcoOyvj2XQx7JThEuPl9ECrZb0TLBBDK
bVRSzEy8HMp850gBd9iZCkVAHfMngslcOITnvHBJ4tFmHTwKWmxUxCJQ5gg89B07OGUhV1Q+z1jG
me/hXjX9OUPElTDa6TrxMsw/u+OojNDTVFA8X+D6laQ40t9oXuk0KBLM2bdF8iNGxHL65Vp8l+38
RPifxux3QEZQW22MVYOiHY8Wpkxi8t6CP0qQwMYn4yC9yAAZYdFyCJ6i3Q7BwXQezdhvpEyEH15s
EawpqFjDMh1gp/QeoJc4eMiWdTRlR1MRpchkVSM2AIbdntg04ShmJIDrsoseAyfot2a/M6/3k8tg
2ekGAX86Z6p21WYEj+pBaBr9yiAyMfxzQeEGFIJli9AMB58eQJwXewlkB3BRp3bxqFeUuHdgBK08
HNzvjIpo+x+asZypiv1UG9P5yt8EJCVQLd55M77zucbLyq+9Tm15/ZrpMQiVQKtWwhGEFM/LdLsD
eOpGAo58unYogZ9jd61lpWzXjfk8K+1Gk5Rtj6GiuxaIOC+4AaBRjHtq2rot5XeTUEeXKPOc0iP0
SSJvQlTRnUtPLT2oWk+FaRwo8kG0Z5pnY93pyvl/GJkDHomt7zBb6Ii1YEesPyGd/DOWVShIC5UX
YzP2NsqRNU/flC/VJIvO3TqEyLi3DOxbzo6CBBOz9FGAO+JU3c83f8ReokkGQPChk8pO3LTeWZWT
N299EgGOEzhgB8EVBttsR06SQ7mnQqWKhInWrSCz4sn0qPhjTXfnqKWeZy7BreuOIoOviLrS2NYv
qHuYuMcnxnEf8jkB7HR8qx9yRwaWV8iOoG/QMCWt4RGLL1zZVYvwqeoH9FZQDcjLp20a2sQPRWdH
ExiZ7RXUn4f4MvIjQz6vuGqqNnt/+6HHpYhvRcdyUJEpPCA8bTQGvTxcnlso7/c2NLzXIkC9bgXV
bu4/DPLvHs+sCT/c+PFX+DLLQfSNW6ccbS+XSkti77jxD1xeot+dVvpsvxYrNQACiL+tF75evtLy
eXfXPlETyJlEj0SAF1sg4n7F3axNpo6T7h6LkFUgPwXJ/luGCQCV4nC5SOWYh3ks3wVCist/63ob
oQyj9LmJHDz+TypWnwqEufwnUMbf1155GsRyTcDwcN7eH9FBtO2WaPfmGqugOND3SNl6xuddm0fZ
+fMZB8vXcCRf8Me93X+hqMDcuRWzEbD2WeWDqxY9Y44XuBb0Up+0jn6fsrzjQe0nIBXyPCbHO+1Q
65qYy1YXZk4xb5PKb2dKUTNL3l/uJMwRE4tiru1XLfdfgL/7DoDwRJOd5ZwH9kNmhrWbppH0RGJh
woO1qE83rK4VGj+iTeY1etxKSiMPCKYxrvkms+cdDGsYrYgG+xgsoJULJ5Lb6/B7Afxz2WGj1Wa2
w3zzV/agOpG2Tg0NYHpZAH3t5JbIg/LnzvjV8hfqflx3ISnyqkJls6/SOPLLpR79KSDBtD4PILne
AO8cxuO7eV4kXFbQLFbjQkvHi4t+WnQ+TDOxbKGEalVYXrfGmtVx6q9+WO82B4ybbv4A5/9VwSE2
TeRlzDFUY/7qTqweXCi77Zd35i2f+CR2tEn/qOoVM1/YqhzbnfdGZqk/H93gSFcfd5mI9BgQSlOp
EiB9pUOxjJb6VS5Yw1w/DJHyiMXvwtOXbjIQf6y6EYqO9eCnONXjRZDmhEHFKDaUCKZSj0PXwQZn
48YTWU477JtQIEfRJcvsjN3QOuywTXiOsoEQcVLv9k8AUenCU0i8flflczz4ws+fohE8ZUpaTAd/
+hmCtlS34dUNMi/ySWLj9TEdh5E++trzjKG0bRS/jq6LXg3QgnKsCeHm3xkqdanznPzMUEpq4Plc
p4lxpMo1ej2vPeNs3pM3+WIad+XhZa4igdbtmQ4y8wQ6uJNA9/SlmpC8mu13lc2PfVMk3AO6K6GN
RUAEekBGZ3ZNLm3GoStPzyjjLqfaQdquC9epQR344gTNFnt0LMY2rokCWwpOLg6CEIUPxDDaf8ly
U58EYklkxVzV29CR7WgT5F2M3xI/zoCgltq7OWyQpTecKtzImUHGO4vwHedF+59J5BPSjcCw2dyr
UDOqt2FosErylnGyVie4L2XxAfjIxXA+2ivJhSe3VrozHSPUOAXa9Epcj3RFxLxM3PPMeBFgmDba
Bh6wk0efbRBdKInR37PkVOvNHLnAp2Viwlbpagrqyy5i9JEaWlo8DHLLOt3hSJPP/cK4AKEUadGQ
uxiVOA0lBQc2jTj883rz8KDflubh7hGTdwuxxNs8ZKgt6p/SXyTQGzXlMdZzD9BDBBszK8k0sKTl
sBHJg+hcv6aJ2K4PTWZ7SyIB6SundFTIswsh6e9JOZkCtWN+jjJgbf4y5gVAnjQUZ4DqNhcFXJjD
0TcZlgbOuhp8fU52OtXGQzS46IppFXlWl1UARmrcAST++wZ7Q+Ex/QQddavhiR27Ru+AUjGpGxjH
3M6XMoLbdcCmxaVHTKVACZWotIPdN6PjaUM0gZ3KjPyRRISgU/2RSJJ20Rww1M5KcFuT/no/7Vaf
5HSvkEiFY3B6zLrITtUi7XZtrR2CqC0ViPPZmV8gZMrIRGwhzXVoNO0vLmObcDpWy2H1RDeTpdbl
IOEWWgDnUhjzfbTWzIg0kfrf6yvotmSo8b9W4gNbAjW2jlRIt281MPq/1P9woLtDR5iMYaqf9uIU
xWf3j8FrNEGX8ZHFekeoSEhyVKAZf8eEvzLawlIoHNrX4MHqDJawNrdJmk84VDDeAfxKOpVCfYY3
wkpZqPls84YHcJVAGeJGHs+ILann2ztoH7fWsO5DUbCAkULwJ0M/OIWcMdlRTEpsvRT1KiaCT9oR
1O0EdgrSUwgUcK3UuIie3gGFTErONYutjvPfm+1n3H25MCv3xhF80sDYh1m7FC7/aJllG2WTM5nG
3QNfBKNvmGEej5gDYQ2rJTh688+Letc94vSNOnN96shi9aTYh+G5eq9WCVq6MxEh23xkZeAQQxC5
fpXiMRJMIdWFlmIa0QEZUbZ3ycR8IrNg6meCW9KuTedefl+JxNq9e1LIk5nDS06Wakzzwr+/AgMx
0c/k6R2cIVeJPlXUmr1Dfeebk+yeVQ7LijwNNFngkyCiw5TDXg5V/vWILNImm0U0UxrLbMSNVTVM
urtezlUUn4UyhmrgLJHAYt0VA5wyKtb3IIZxYpeleWl6wt2/vwZgRXOmEtQO/IKS94Wi1sPh4fjH
z9uqlim/uh9W+B3DNQo9bl4LpVhZ7h5wW5na2YiHUtuoN3E/YR5/IJyCXTJJea5CvtebTq843Za4
dqCqQqodRtdkraa98kjxqYJFI4m0Afcu8PIrRLFnKoys6p7CR1c6SlgudmFUieyZrsacDxi8ZP+Q
Li2NY+9u89U7SgKVzBolbm2PJAKDupl3ddqGJM4mDcMFNs47xIrF3lWBkXvXhW8dfT3DKrGaImvP
6C34DiUakYDHzKRSt+/k+2CBxeSegqLn/5U/tC7TYyu4P8aY7Husf4J2vwBxmatPTSlUsGrVT+uT
WeURFm5y46cZ/2y6eStVLR2A+OKh4Ks0uBKIGAo5w+FBOna6zgB7XVP8o2LbHnp2JCmTA2WJhOFC
g19RQ+pGCBLqNvfwqu+A92lBVpf/dFV5KVLwcndLiDN35qPnW9vmuIdJYjvj8QKmq/jX4fWFpc6j
cEmMxshMhi0HlaF/r9/dxA69OufvPRzqbmA9DqxXASuorQm23V/AQqkXZrV3OOba/PaLLEOhqBOT
L61oEeds65JH/EN6N8hF4T/sUZayuM8b+apWHqaeeMGdaTfSiID69oGTSuqInuRlktL6Pz9z1LV+
QFKKX1QDipyocsO8KaaIyfTvCkJyUOoN/HwnJxX3abtLC5InD92CY+WaBmPrb6tTw5m/kNhsi4q7
S3U7tL+q7+ouirgGvkY/uoxaunmSIKhuag5LvuSej8/+DYd75Y9moaNN32ewPzXo8LpBFYfrJBEm
DzVq0iZTAaO+3TpAtwUi3dkIyN2kNsTL7kbmJlSGZOVzh75aYV5IxleyFxwRVm+jJaYabQqyCrkl
0dnKXd+D4dsDqchiamAKpGe1X6RqIzDmIs8g7mWZ1LBYf3FOfspn0DGXQ5lHMFkcVlDzYcMosEEg
K1XlvTxekpQP74O+saPLTAMvek4d30pr9MCZMGAgh5U0KleS92n19OAZQC5IgdsIsYavnNKdMUeh
ZupuDS9cvPNFECrRPXiIXXqtYGRoQnuO+IvKSffHXnQoEeAnaJhKQj/FEeaQmtZzYflM9RO4mnL5
1gb4u0FpeA/nh0tGN3haGDt9/zULkdDGzCM3MYyJu+xcUNaxCtFqM1s+kqH+cAPS1xcJiGDj/Bgd
k8pleBG+5U30pOlEUMxkHlAPaW1VRKJD7Rdbb9lxlWbJFnH+95OA/FKVPYdmeq7WUcjar5Qjw58y
kjBoTtwmbP0P1Zgoha3qwCGQx4eiAjpmErNxV7th0RqLYvjBdNyHzGftdzYoAbbMe+EV1ANPgBiF
Q/hzJt4gaBHKaUoD2UsckFO+kXLXyJASNPkGHl/Rt83h2P3jkgicP9Q2ospUg07DJXcdp6NcdDMb
uX3OBwLcnxfHXY9pD0QvuuuuQVUFlY9AlSSizWDrFjbuAV3vMVa/kE8cC7OBTz7OYfEyPvRs+qE9
9wDh7UwzEWWCcWwFq/fk22kYKp6I0/bs0MZlYju8eYwco/3vDchMDBCYZYLHubDVSWJ0PaHb1/6n
dFCVIXvrEZgIkZXCr67waQhBlK7LJRt+ppKyuNpAJioBYK6NiX545XHy1lXppuSst06QF66bXdLw
2vJ1xHClfmFcXPhO60rPIPypdTL0KTObzGJ8TOcQaE2L0b7IsHnMR8tZy+T6YBoJCNUB/7+chVI8
R8BE1a9mCRfD8ieIPZB6iJ34ABdqfMLGbNEcRsP/lTUpSIo7W2+8bAFjTLzUm8IlZu8IjhQs54nE
KTf+y5bOTBPWH2Fn4p1Nj8BQO1iRbvezwlLCqlmSZB0FNRRouOKhp6DzRWQ9bS350ZHYZLnXKhy4
brrTzXX/pCkIQDwbjaeAUqm67LOej94Y7O0a3lmV6VBHva612iw4x4zTj7WOwKZjiwhlOvgFlZB7
vMAi5028dr6hx9PCDbePcA+AR8MaWhyXXo0tKBVdFKNy9W0eA8k4O3BDsgmXFtyqJhchoOExpLvE
2/G+MYDSa0SlCwbzevtN2YJGoxjm0oNoPm+BOtIMOS/TpE7L68gFyxPUvsPQS48LMarTDzv4onFw
GXU2Ah2QjiDTW0O6iavdPrCVisETovslk6oHAcZR3H2VRPBt/ift/ZCXuirUV3JzOVXUY7wIdNhs
h8QXwpjIm8G6mesNVPoLkh0kkvE+ZgRNuYxRnn96j/rNJKFnGYaVLi0iBuqgw96s989mHNWx1l6p
PfH0SDNAyGFgV0lJMEm/4U7xCueuSrNTy21EolR2gau3c+Dbggb3BsveF88jY9muwG4/nyy6svWj
ck3q8cvnaPiBcxNjVZ0N60O0R6wNcLgk3zB4+YZpye5W7yeneWQMPGZAKr+DE0opmJq6poa26TR/
9jbNOfSEVoCwQft+TkERXM17DYt2LYyN0jI8ifinUyWn/50S1JpuRKmcExH1yjr/tkGEzCdlUxv2
tV4F/hOnl+O7FKEHbU9DEelV+emS9pNbPLAWIAQ9Ol/uYYGoVT2zgknFBf+XM532ynnQPn1zBVk4
h4OZCK4oW7uAMnel05mgFsvhZCnMeI9BGdIgc7eZsztwNNR0xpnSPSR3GERN97XV8yD92p2MxB6g
wolHPYtyvwP7x6YU/hNP+1N848u/PgN4CQiaS1mjiHvWDaIMOwemxEJvjMZX4zjwxIUcZeluYOl4
26YQJ005H1uDxJhlMO8QT+yXcCD+qVPUPDlrUWv7fsnXS4UBrvOkEg2uTrSUIPcCFcyE5szrdR+H
akXBANJOs7CPbPzeb++YTV5tpUV0r56gRPn8FA9CddVr3IXsoTQeOQ6o6xiNytVbvwV6sAab8wJk
mU/hNmIVTI6G78cZ0P7lVQSo5+qoUgGm5rarcSYROOsHmZWMXrCaDvNNwZ4SX0AsKjcag4mxCYcx
fJS4nhv+1UnbjoX4epieaxzYtz9rID5rn7UVzSwRrw3RDGBYpIQYCNkUCTU7XVx1fpzUhSgR9RmY
6NH2cGbRsbSzzs/WAuPDx1JlfODxdsq7AszI1NHfnpwkkcMEhyhVgTBg9Xu6LKWeYINioxsTVypL
TASuTyOGlKW5ieor9XR53/F0EuaEPDb4ZUCI1EP04/u/W7VIO2vNOMA2RkrjJSkU9QIl2kx128VV
IZlrfHxy+Ooae0SgR4MIznzny12oG5kBY6CpYaN7Xxi9aYoWIuUtMsKUlf0EHke9GcRaSy1xJKEu
qB3ibzVcIl4npqgqMKQ6e/PxvFwSHO3WXfJ04S0+HbNbZWnd13t6Gpupo3uUIlG/984I7Rf5Q+dj
xvoYHVuD2ZlPu6uRJD50KwKMes4IqimNcBWVlNTRneH6uIq0ZHP2QLaxZf2Y85PD1er3NVw5go/5
bO/bEa+nhDSjcIENF/nFUBFcNkUogTzeUzT8w+Yh0Y/PWyH4PijtAnzm1NfKwtb+o3sZB/3gsecq
vdzVivfDYUAoubbKgsP9JB8B4aCmO9N4Kg3YAMnMzD2TWQjo4P8Ke3qcJ17VEe/04kWAmURRVsp4
YynOUTMcLbSk66K19EnV/E3ssCOf4DvVa0ppVIzaGSp/17fvC1f4Izy8T9/XA98os/MqCtSn+zIu
FHhFlFpSbb0g7Juz6w/0HMKH6Mug25X7LiH3rtqCsIJpgHGVP004MxAmy/SCyjHX7a3oAFDgyJPl
VjcLlj7TX1M4u7ngbjyJN4oP1WwaBsqnAxyS2PJOJVzfZALcEZCV5VAYzgEhoQJ30WeOzRwlxANb
tLT1f+TpF2quKah/UWjze1cqJVh1xhau+BoMQzNx2M7Zgo+1wNcIsoJp5SAjOEdL5oujGd5UQq7P
9bgsJ9Ckw83NSCNtSwFIt+HnCQl7fPZDUwYrDXUzP4I7AJ0BYRpXJwpS9V4eoJfO0KAmUpttq68C
w2DvDzREU2t4uN5vO4aUxyk9jHVgk/jS+qsdZdrPtMNrSqB1AAl58spSOGOHFgwcyiKUESdcEQNf
50Ph0x6Fodavdh7Srq2IHTGnqr52X8ksEY6LiYg67NCOGi/vXQtCGHyt8feKgVcfu+KNPzHzyXnP
xbI/ajOtgPBZB8VapXo47bL5yMiQGlUtjPv9L9DqwPsPrUKm8mE9Qh4UqcBRHvp1eGh2uQ8Meyyq
3YdBc8jUE+CHgy8RwNBMoHyKL0UUhianIFXH7XsYwPHjcT6QziEJPq4m6x8Mq84FvH00euqF+Vvm
sRRMHY2PSoqLaZpmG/gQM0G8M5fHpwbGdHtpI3GMPNcj880/tnDGTRJf1bD7tx78CTsfUKmMgjVh
Y6N2IkIk1haD7q5oesA8ENyZdEb99EtQIlOak619RKJvZW3Wgu3Vkn2ldkYEAZagvBmCMosSMsGq
wHygLYrBuzHDSKnP89SNmKGvZosIqBQTYoN20ChyWFLApcBCwQKe5U4FBvnXsmv3DpqLHCLkQBok
wTCgZ5jslgxs6tpNSb0LYJRAOaAyPuTRCpNkAMH3vwE5v3yJpkdAzU3lQvrqNDfXqDICOqbGmuW3
wqtRxnQd17ItFMfgKxN0mv2lsLT1FXu2wdLvkd0M7aEwz4ZKU6VdsIS3xHF1zrL410IQGG+74mTA
3eDT64/p+ctqW2v7OrYTvj3tGtmUoodGXcQ9nSdk+C9uB/C2lsuIKQwg5Jr++jp/rn4aHWoDbPpx
5Wzll1fTCkqy1u80QDTrVOHpYppj+GlIkJzYOGmbur6gAMGXdYtGR8R248BiOquek3oMkW8vlZ56
OhTrI5+LaPLXYO6zk1Fxs5nUdOIorA4jg0zme8n2yGWrCBA6Gcs7RAjCvCWfKsGKf7GaSBIZymwK
NAFS22p/ekzCbsAGzevc8XXG8q8HfcVGVdpHErRaWRCjbT//z4aK8vSm2+sa8BhQBO7dvLfkEi2D
qIq3eIsKQiNSy2pu4Zw9tq2zLAvm6s1JHpjL5Agm4zDbaJ+hqinoppCmsqHYdbKmipbdB5adS8OU
OeNF2f3F/BGV5HNFjfqFSGYlfk/sjoTkVwQuE6qepGA+KUZhY2nTZnsh6G5AVidRWfA7wSsZJw8z
PhQEyjMknPNvo/sWQMIfLPHGLyYZMce9MQamIo5YE7GMgIxgx73KQ65z9X2CNmkVBJ+QIcglrnym
WXsjaZvpVU0thbLp83GfKoR60hMEH/6qZ0ZcOEaLvk6GubLuv2Y2Lu+40Nb7/HTKc4ucy1Z+r3HX
k+6MOXGjA9wFH0BhxZ1uBqhQrNwd7RQ4ng0lfCg61ZAmQExlCZhJrohy9caThCIXjXEEFqy6HKP+
88LkdYN5X3yy7loZEcBKgTrVjqPMhc5Am6ehWeoal/+qa1TrkIguq+962D8mrFas1saBXy0W9v1R
S2iR6LIKXkPCXnrtTz4yf1aJRLkjUNQlWqhqsqDYvkSGVLSsRmwqGi5haEjgXuDjP/5vDGyRFgtE
mz/5IsA4KrY0WzNztdJx0PO4TD8obyMAASFL/QNQomtAJTvxnvaca2+DZFwawx/eTDrVayGNfqWJ
uSRaGFBkrQnX/A1AVl8EXSgv80A3ohPVmz8Znel51S+1JRfdfObOA05X6bVaKvT71KxKPeas1FDl
/mhYiwQQr8g/pp0RC8aVmZZkuaTLh9qOgVWQKRN2jvKxUHYWgc7jwf+TNnMiCuigL3QfcyCqtgJB
EuwsBfLoxlIH/ge/qEwAPG2N7epibQsRs9YzxbpUGprbFtKskt0gLh/iIZndxiZg19gtAkBcZiPt
WWovSosfbFCrhQq63IvsNSPxjsLDuwuqopNqn6Phv31lRFivdUkxcHEYYAHTo6eocaLWtr8CtCwP
bhHjWn7SwwGh5VQ8WexCveaw8R3TqSgtHHi+qyiyLa3XnV9KdKdkwttUCIXLQnW5a8N0WkafXnr2
z+iUPEdLAR01qBsZDsXP/Ct/qO6IZkYkgvuG1jMji9ObEfuRgDltainxHHZDgyZTIiXT5UdNfpqL
Em0w7C8f8+N0vmHlpqTf0S8JPUzfqXBH2n5Y6ySuNDbNoIayFAZ0SHA51Osmibf2IEuN3ReiJ8+e
hnM+s/odRjXYQAtsoHQaseDHLVngywDBecQQ6W7Sx4N0ta/71G60fMEojB6skDhCBfBs6DO7pVBL
nz/EC1fusay4UeAoSoIaLUElzVT+TriQg/rxx0vnqbhYHUBSGpDv5kuQ7Mi004KuAvHbvYLkFXGY
p6AI60d4TRacYGh4uBQh7eRMEkP4T6rruIGEtNQT+tU57IQ1oAgE4avScs4EDfAzcY+LRDge8UW+
8sTvZjBT38N0UnGcK31z5d57uNjzc96ZPnvXrxWhUgf2/A+gaimlBU13qOZjx47Lb9SXS4AHZQND
ApYooWzxodS4KsBZ/8i4qNczcMEqRpfQRqL2Zw/1lRZP5XX9ZC4WoOiK6oEhFfUQeRzvwbZ3MyX9
PtKSRlZUkr9jALimMkWCLlUIqaqTS/8bftRdw2RFlIXfqePcUMOoCSE7sktDiLK5TKK7KtpezvzY
Lg+Kv4LFQL/xRhcS4HQ4SHJFVwI+92VH22HONADNswhMCOwcFwBRb9qg7hqccQYb1xc8gW/+qTJ0
C9imAm+U/LAWvbAegESyaMwtLOZk/dpsy+gdUqFiURBoQaXxlBbwcpZRrbIx40XnrFXv+aaw+NFl
pe7xki3wX2E7KCTp/YdtbDjpFxjf0hHPu1yAof/tgayZECIcyJyz91GoWU9dWK52WslBM5ClZxbc
TV2OzrHMU5zxUodNS5KU2qU0uMrfwldlQfdOYPjvIOtFzSOK3iAcAd0K0FRk9e/oChYI/p5hlYIb
I4tVDxDOJ079qaOvAchCLQkqXBFEvKbfdVndA6AadTEd3NeSPh3MGpa26KR+aNhLYO2hgyntVoe/
nyOJRVGi869wF/ZAS1v11XcChQOJTJKJXaj81n5g18FzJYbYUTfnhc28G9uF4i50aTRsRCop0GdV
D7j5snjr8BKXVnVtdwiPHSQ7EtEYJitSQu1ZNONYEdTu2t/tF6Ti5qjH7NcOO+1AVDxwUoRUOKc/
PNI9glCPTsnNBAFR98odk60H6jn6DIGPrwZgj2s93Hn7U+PHnY6OBenjS0NTk7MWae33/TnkMls7
Tn2kk4enFrWpjyKin2ihgt98Y3gLBJ6Qsvd5GdZzgCw0ZK7PTX2N07vFW4oTFWK3X64sHoiyNONb
xmPRd+Qm9WdqCpCKDl6VGC4mvWFf4i0dHzVBITwkonGMJH8nFyMviaOWRpOLZ2tMsSVDOQ9zfyJQ
YNNLqZUWQEeFmI4qC2yiNpsR6lDThvO3MVyIddLQsviV96+rc/e8pjv24VJ2VoxFzlfWoUcb6KOK
R96EMyxPEH5oMZ+NUnekKPaBEXrMuAQuDMNzP3jd96JyeSobabmT5O2JaoUXuTXRBXsK+4Pcrb5a
T6jrNBY4qj234TtZy5FqH1LiMq9+phO3A0IsvBWJmAUgnMRRzdjMX7P/Q9ExBv4dsufesvRsuZJ6
MnD7a1xFGvumEENoE3LPMfbzxMwCqxjvANp5obj+kkwqXxmHByMbMrZkjXEbVrU1K7lxdNeuX3iY
j4QyrdTDIHJQ3ZVgfSu9mnKOYv+bX+xwBhpPOX1DKQCt/npDDrNy5PWSM0IpRzBiHjedS54GK2wb
2DX/xZdAh77HijFMBAKYNZPlZ0Cza8567nxaJfqt0pT50CqkBROTE1qLr+lMDmUrM1IE5cKZNV0H
6cZkAOUWnZ21F7qZUXB7W/I22B7xH40IizvkVITdNZeKC+Nw8PzD+rcqGN5gopUgSlw/WR//KWG6
4jUzBvvkt+UPjVTQ8dNdgG4PfUewXeepzyRnPdIbtyEcMuWzv47uNC6s23hyir6/labE3pFcJhG8
WtAg9CZkigdCVtPMGrNJpCzAn4QuHgAWljUQKUJGZE6739JqA3yF+XK9Tadhf0Te6oMxVil+BSVZ
5QXT7XIgbMDXsnxQTjstbYuJTiU3iviQT1lHmSznfickji4GRmbucuUnQiFf6zUNf8WCNKwU9thc
8JVQqzj7mKg72+s+qhRhi2nfNo4ROP6oI/Hhlpm6O9tkP5EeWoVxmc8o7YynAFzuzODTglVAsLHJ
XdLkaFFgJ62USPCyKP1fYlmKFXnZ40n1s0xfTQxvdMr2g3WIr8iSDKHWpcqUozlnLVrMgZDx4RAd
wwX0V5hEIEa/5tb1wt8OlwTXNjXOFDL/3nuBBnhH4Jfn8ucWO4D576SVIX0i2QhvsBpxNmbAGKbr
0y+E0Vn0fweMyF3oDdBH2oKg0TQXvndW33PCuDKptgY50q5WIoi+e6Pc4IMc0/O6yIqLvZnnhE7Y
sErpvA/lg6qnRRcdJWnb5nT91iHJRBxtsX3G0micJQoEldaydpUUOw/TDyBdLCU509fDvPF7N/0I
plBCRY7UTKYlk9Iguqizs8ZG8dt9huT4r7TQD7wAwIjuW6a2LfkXd+oU2wtoNyibGl7rvdYaQBI3
gAdGN/M16me9v7ys9r3FhGoFbBjtaCvVkPASam+aiyYJe1wST/4WoSvZlz6jNC9LqS2eXdJ+qd7P
gXGCJ5Wlnkbnzs0qf9jBEItzhrEg/3n73B4ts0U36DrOWlQy/9ClyFnRqs6nDeS49h3d8mCiZAwZ
2KKpEKJd1UXT/EBgO+JxNFw3GIwyU2+atyp298amQjFu1HXmW7dpuK7qiu+Y9OG+lYAoS3gsGMXD
L3MowdEGo0NugG/aIJhJHgsxXiuf753YDUswSqr/h4vwyziHQTaCGQYDb3rnxZamSw7wv1ffiHVY
reqGCYk0b4FGOcdqdF4qzLkTLkJsDGqRXwAvP4OU/aKII3rYDnmD/oFRmI4gUDpQ3By7OrvqNus7
QIK96j7NySUHr6VFLWqVDwWFCp1UOr7/nmJgaY6BvextodzT/vcsGJ9JyvGLFdtn4mIufCTOP9Tt
drtZamBNFJ04YtFeGKbisVAJgQ5qbk7xdUqkq1HUKWn1SQDRQ8XeQWGrae8cu7fa3MQ/sSC/5DW5
ppTWQkS2KSUvG0z6OcOogrZCC6wo+oT0q0OU1KYvBdmR0VP8vJyoNtrHAWd9o99an34vzPhhOJwY
RlNaN11RZD2u1mz8FGtWSZUwBme8NZAS2DsfVLMYqIQebUB89Ezr1mGST2ID1zo7fCwkHhesqICk
FJjsQ5YL6vNd+vmS/lcIrLT1/BkdiYXnY6J7wYFDbnK1nWvWmiI9mV+o+h6BEs4uVbYtDM4sUQTa
IcA5LeycCSp6Qs6hNS1FZnYNG1Pt/kLay1FgU4eUyARwj1mGv1ZgkAuM2zWImNe1v4Ha3xInWdCL
tHI8spJNLhwgvOs4nI+vaitli+bB/IAizUBeeE16Ah3pQofx3wh7+qWs7HH3Q3brjDAiefqoDRdN
VoyWsgeL4MGgTdSId01jJ0QT1OnXthxlpncmsB77R1I5V7UT5kcIb4OYCvYnt99zKVP8/M1vLHo4
eJqoN1H8foezdKX4wSNVBHVTWKREMhU1zwjoF/5xd0eKTYTUwpPgdD/lkr3XEd6X+XMaBq5LyisN
TNWwOX/+phtC9Z+2/FRii0XTV+6x/Oo5l4V/0Ti+J7SZYy4tBfmlWWNqpOTwUV5qxrkRzPwAa3dr
luE29AkOjdT1hghDz9Tta245/pehRNy8Gv0Zbex/o/0cR+kPZ9CxLk6+RBmvA9F17pQjT0JdZYmD
sUmJO9t4WZeqny+crm4G9xBO+GsUhjbGhXRpNYWcNlsYWZnWtsLZ+NCQFV84XZ7HXDR0519Hqs2d
rBy2nK18UZVvPaaaBZhe6Dz9Vbx1IaiU64raMimLAIqDvnSs9khi+67qC1BqubqsYEEE+dnJhGhX
2rhVxsFt7Q532vSsW5yZiz+uyrY9qdj8Wl/NkkKq0D9vqmZ05yWA2T6MbY6cXRjgHfu/j9wRrf89
0wC5xV2HKcGMmt/cGDYF6y0WdnWWkJPb7bH/0FXgNMQZJorAvyi4hZxmWB2VWaVpoKCCQ/Trhq+3
J/XzVVC7n4LcOAjgytZvUJx50fNaB3f4MshbzjGW8fPYOzV09qEgZyZRJMqYBPCXctGhLcR+Qo7p
TK5AVx+v7Jp+Mi8rOzdJtxvIR7ySoXFehn/nLbyaccyvujY13w0Lq5TR0G1KgGVIn+2FOVgfGe9x
tDYubGwLgm0UeFtImZXJIRUfSd/gEDJTEKfGd29q4JOabvO/aDm73lMjTZ/tp6P6t/m+8UghJ3W2
2sW83i7gy5XUOtM/PnSwEqqqt6ZSheC91RS8Rp4ofeCyl0dm7vJ0k0m0ZCZA62MH7Z6kBJ1q9oDf
T1Q+X+eNTjO0oNUmj2l2HDWk6MHZApdyd3Okb9geO6AlSSFpv0jd9Hq1aZP+cNkOnpIUO0SGZAkt
xm7LBoku05bx4u6LkDKKPGp7AHiZc7XAMn3yz3ajvMf5zZotO7Ld2UxVoSiF0Wg1e0B2yFGVViwf
So+5Av564MHmU3Lv79EaReH1o1hBftessv9oPXcJvmLaHNXZ4Re2SBoiWT8L8UynCshmkRefaWgw
qimUpAgHptNWe3nDqDuWRNd/a+QSKJ+a2CWw7JZKN5RPQ1Eq8zKXC5sJb91QBtx6hqJsLLUFwJUp
iVGTTr56sZ/c+dlbl74ia+DfBrpNxrWx6l+Mp26xTI/eZn7jCpjpgd4pwpHyOK16iEr3OxDmI5CG
GhfimRpTgiRjjR5Q8GUK25wuIZztlWnLzIR4Lk17Xho+8Q7eYWRp6hayTLHxDW7K+qdB8cYsxl2I
TVtQwQ8F1jvtdKbBwOmAeGYmFJpewJLC9RsCfyZzmN5AWJVvqdDyEFrfequYervrCQKHk6Aa+M1k
SMGPd/GuwDG6Z7vPsna15FWU++eW5CPa/Xqhkrg+yKTZ+IcVHmXlenr1DwINb9v2EPZjvzvWh9NE
fyuY9x1MKrldJG1Ro9O+hzLJQlZuDw1MM4BBolStrXHIMF6/auRo3SOXGzZ9pHIDqwWf1uVVmxQC
UvWxv+tgpPHjHwZNZ2noubavTp8lXkIy/ZjZnlRK1OJLSFRkToEInItao1U1Fm7+OKFzdnIOepsH
0GiVeYiaV4r8QKVU6ZjxpNpH+qlAJEbuV1WRoRJYnN5twM3whDjaLRSpW3c8lnn3l9ngNHbnrbxe
FLjikR5sj/zFrzethj8v2acUyxlJ2ekuEOaQAk66cYJ9H6lUwOYrF3UNi8UCT30vmp+U6OdIPg4s
7qxqpQJfVLLG9OIFe36b9GVnlTNSaUWLA4rCotUdt+5o/ag2xExQHhX8Wa923gsHe4UfJ0yNlr04
59Zefekzph6BF+SAOL2mNJ6o/LrOdlMLMO7HzPKzbzZSDW1t1AjUrAy29Lp8BlQnfpw/dBWZnRQd
oophT/zt/Hsgb6g/82gsNezUGTMo/VgBObY+tMuLp9caRS6g/c7Atr7hmIakUVaUrNOzXQUdP6hG
rf5KXkrB3eT7XgapzjURc1rwW1ox0REn37Qu3N3wx8pTx3gY7mCWStcDC743zRCo+BiXj7lgx1El
TKSXzkmwYdEN6MEX21Khnp3Qs08MuLRjeHF/yRp+boGARnHCHZnm0LSIOlz4Z8YYoyIzYUgbzZ9K
hmW1x08sJP4NdMc3QNh33yO8HmI+tH+YlixohWAixeri1ZqyFqk9MiNDIRPe5hm5kNd98wwXBICA
xOnfBzEC7W8n66uYbuuzdIj0kiyFJYNpSMwh+Oe47UWxFO58R5Eh3ycrvD1+iDEPz6LRzU5oj8Ro
VawuXttSCnOB6T5mBNITOGgdi6o5p84MxPc=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
rKWwB0sGGUajpurVPwhHzgsZATzg6CI2fy5teGZgwWn6RJSxvVrm7X6KC1NlYW5YtUDp2ese/Vrm
bw3OqIV60Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
BRuqFpGYGOGwcHOC9ByqxsqWUs+0okjDxEXI9LjsXxEyuWJLFUE7YYzNDASAihgXdiZINIm5es9z
yyLJWg7azDkuzQk8G9FmmXCb4GMcSNpaTGa1FVepRSL9Yvq1uMN0rfkU8OoTCb0JTco3mn42K2KI
S1jw6CGiZKnXjxgHNBU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
X3xfyzvjrmPkaI9JdFIRWVWKvQVaKvW3xkPmxmWB+Bg2oVsfAsBqh2i46hM/Bcj4vTlgRohMAtTw
mZrr7U78E4bYF8iEtFKLdIJEd7hVOOlmDwsFBDzxg0k47kX9A3ruJ30LrjKdxboHAuMIaT/XR/sU
upe6flMZr8VBlv8re7jyziDyWZOLqFpjufskTfv4OQj1KszofT4kUnArUhuQ6UVlh5i6v/pQEzIn
QBP9XWEv/eQfQZl33K/QbbRAZIttPtuWp1T04bWkTuCPPKG+pDFGGGHJZvQDtAaxZSkHqZAvfqlI
CAW2rOiYEadE7tUwZCBmG03wqqm+cZJmCFoaew==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
AUXv88ADQriH8V/F9F2bxLErHxhqOWkmnlCs9b253d+OgRvIOLCtaWRA9DjnqkOKIf1wnvs/R6pY
dJJExfXVZOjD4nIH7uFh77R1TOSQouJzgmqD+K5HYb0maU6PAGIafeBzcUv5XN4HOOPvm67+oI2c
ikEGUjjanBNxts7eGBk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UZCooc8nZi2nNWJ83Gcm6qAONngeeaBUnqNHZdi1nOU1iRX6MguqeK1oMSUjP/9bRjlw7Tp3sNmB
PWJn2GGi3l8Qe6b7auDrjGMr0IkAvVTyrVlPQlMaseSN4e4IeWhVyNWjm//n/TOKlr4NMKKu7xlw
UYk+ejL3Bl9bd8/cGgsVR5ZkQQavRAFBo8L2IT7ML5f1IYG78bF0KQzrmL9GYFMnToP9B7kVR7Du
Yb7rcfK2Zazdh5MpYg9XUjLic80aZcb4+8dYBu7XgEp/Ar3GApiNMnYJUmVK0q0n9Er1Tqahdfht
jdB1SKLd/YF5uaRclGtmIoZjAK3M+1SEWOps9w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12224)
`protect data_block
t5Spk6yve3uJ1YJ8JkRzUVqRYSeuRX7hvbRJ802Wf+RbaumUpGUGs1znFzR00sTUqUlo2CM6n9t5
idaQheZ7CEySEBoOnXCDFAPgPh8ykyAiFL3Y6sdSpbifGT0J/JOeKzMD5+nIp6kLlUBQc7VQSeug
M59+p40cD2Inb5oFM8hep8qN/6JeN/AvWyjNarzBXpsddtlR8UubbsDzFOoHP85gMfreqfxKQ4mV
L7Rk+vSOBcAjasibJdt8lGIhGi/lyefdAUQVTAcr6Rk65rUmtv0s/zold4FRI0PmGoGxfBownUjt
ID3OGTorR57ZiwQS9SYT/JxWJc4zudrYR4fD8DMzWdvENN1xnOhzMhMHt+838ogv5ctRUr1L6p2O
rtwRmv3wR/GKlGn8ybNwInmjtK4+BNX5gap6mk0YnCG4mJTIiP+FaOoM8wdxiYOIdNIw+rUEBT/r
F6GFBxG8/5onUxfWtczQimgRffRR0v7VnhSMzy2cgMSC7RSfU5tBTVhvUjiZIwBwd4dh59wwMbhe
ObgOq2fTje9tphNoAT3WxoQOthjG8xxXRsX5sR0k7TcuvWX4nQV9WbYTs0pleUmspnq1k9Xs0EIm
W3y6b9BoMzHXGL1IE8hJYlJd5MJzzouUlPN9Tfwh1wrNpCDlmJ9J4GDclsOU/CZjQsWM5EUzV+OH
J1jcgKJeqyL3hOLIX9Dzt78ChPYHG1qg0Mb4qDP88S3pODWbW4+1j2AsD7uCWlZNEuMljxUnEhE8
FIE3ZCbePEIUPc2Pf6/43pOUbTiGDWhWlgErsC5o1dI6noSg0LkHfdLy18FHnFWX9F4Ot9xbxQNo
Gz2CBeKdYc1PWDPlJvrALuh5AkKAz0HEA+nOrvYQQikIUnTo+jrneOXHX5udeFGKOGj7cGhNtvlf
Tf9HT1+I7uysbP5f9/Vy2tM5W9ioHXzlY1KX/AAIXi1jyj61mytFLzgfuX9qQ+d7eZQg975Qw7wv
2K3Rs5rSBCYTDlyZff8DwG1W75SxZa5ZEUnq2iIUAu/K7a57rlg+CagNL7UfcqLTet7lwWRb/36V
iakB2GyZPEZWgje1bPPgQp1xBoLyGizRUM+wS3Vvf5n/3MMSjth8mQJeFKioXxqm4h/cJw3QGSI5
UQpah2uMGNMkL9oOvnJ9B2m+nLKg7VNIXBGxIYAXGhvdZkHt4VLzwYGcaGFdZa3OnS5gjN4TMRly
fi6w4xlKfDC7FwkEBAFjRxbHczk1q4nNDzpStSec9d5uCH3awkL3L0IMNdShksbCWmv3wwEFhjOk
SjVTEdwHmcA4oi4aoPvyiGDR1JKY7w7HjpuqE4+zIGGQkcoOyvj2XQx7JThEuPl9ECrZb0TLBBDK
bVRSzEy8HMp850gBd9iZCkVAHfMngslcOITnvHBJ4tFmHTwKWmxUxCJQ5gg89B07OGUhV1Q+z1jG
me/hXjX9OUPElTDa6TrxMsw/u+OojNDTVFA8X+D6laQ40t9oXuk0KBLM2bdF8iNGxHL65Vp8l+38
RPifxux3QEZQW22MVYOiHY8Wpkxi8t6CP0qQwMYn4yC9yAAZYdFyCJ6i3Q7BwXQezdhvpEyEH15s
EawpqFjDMh1gp/QeoJc4eMiWdTRlR1MRpchkVSM2AIbdntg04ShmJIDrsoseAyfot2a/M6/3k8tg
2ekGAX86Z6p21WYEj+pBaBr9yiAyMfxzQeEGFIJli9AMB58eQJwXewlkB3BRp3bxqFeUuHdgBK08
HNzvjIpo+x+asZypiv1UG9P5yt8EJCVQLd55M77zucbLyq+9Tm15/ZrpMQiVQKtWwhGEFM/LdLsD
eOpGAo58unYogZ9jd61lpWzXjfk8K+1Gk5Rtj6GiuxaIOC+4AaBRjHtq2rot5XeTUEeXKPOc0iP0
SSJvQlTRnUtPLT2oWk+FaRwo8kG0Z5pnY93pyvl/GJkDHomt7zBb6Ii1YEesPyGd/DOWVShIC5UX
YzP2NsqRNU/flC/VJIvO3TqEyLi3DOxbzo6CBBOz9FGAO+JU3c83f8ReokkGQPChk8pO3LTeWZWT
N299EgGOEzhgB8EVBttsR06SQ7mnQqWKhInWrSCz4sn0qPhjTXfnqKWeZy7BreuOIoOviLrS2NYv
qHuYuMcnxnEf8jkB7HR8qx9yRwaWV8iOoG/QMCWt4RGLL1zZVYvwqeoH9FZQDcjLp20a2sQPRWdH
ExiZ7RXUn4f4MvIjQz6vuGqqNnt/+6HHpYhvRcdyUJEpPCA8bTQGvTxcnlso7/c2NLzXIkC9bgXV
bu4/DPLvHs+sCT/c+PFX+DLLQfSNW6ccbS+XSkti77jxD1xeot+dVvpsvxYrNQACiL+tF75evtLy
eXfXPlETyJlEj0SAF1sg4n7F3axNpo6T7h6LkFUgPwXJ/luGCQCV4nC5SOWYh3ks3wVCist/63ob
oQyj9LmJHDz+TypWnwqEufwnUMbf1155GsRyTcDwcN7eH9FBtO2WaPfmGqugOND3SNl6xuddm0fZ
+fMZB8vXcCRf8Me93X+hqMDcuRWzEbD2WeWDqxY9Y44XuBb0Up+0jn6fsrzjQe0nIBXyPCbHO+1Q
65qYy1YXZk4xb5PKb2dKUTNL3l/uJMwRE4tiru1XLfdfgL/7DoDwRJOd5ZwH9kNmhrWbppH0RGJh
woO1qE83rK4VGj+iTeY1etxKSiMPCKYxrvkms+cdDGsYrYgG+xgsoJULJ5Lb6/B7Afxz2WGj1Wa2
w3zzV/agOpG2Tg0NYHpZAH3t5JbIg/LnzvjV8hfqflx3ISnyqkJls6/SOPLLpR79KSDBtD4PILne
AO8cxuO7eV4kXFbQLFbjQkvHi4t+WnQ+TDOxbKGEalVYXrfGmtVx6q9+WO82B4ybbv4A5/9VwSE2
TeRlzDFUY/7qTqweXCi77Zd35i2f+CR2tEn/qOoVM1/YqhzbnfdGZqk/H93gSFcfd5mI9BgQSlOp
EiB9pUOxjJb6VS5Yw1w/DJHyiMXvwtOXbjIQf6y6EYqO9eCnONXjRZDmhEHFKDaUCKZSj0PXwQZn
48YTWU477JtQIEfRJcvsjN3QOuywTXiOsoEQcVLv9k8AUenCU0i8flflczz4ws+fohE8ZUpaTAd/
+hmCtlS34dUNMi/ySWLj9TEdh5E++trzjKG0bRS/jq6LXg3QgnKsCeHm3xkqdanznPzMUEpq4Plc
p4lxpMo1ej2vPeNs3pM3+WIad+XhZa4igdbtmQ4y8wQ6uJNA9/SlmpC8mu13lc2PfVMk3AO6K6GN
RUAEekBGZ3ZNLm3GoStPzyjjLqfaQdquC9epQR344gTNFnt0LMY2rokCWwpOLg6CEIUPxDDaf8ly
U58EYklkxVzV29CR7WgT5F2M3xI/zoCgltq7OWyQpTecKtzImUHGO4vwHedF+59J5BPSjcCw2dyr
UDOqt2FosErylnGyVie4L2XxAfjIxXA+2ivJhSe3VrozHSPUOAXa9Epcj3RFxLxM3PPMeBFgmDba
Bh6wk0efbRBdKInR37PkVOvNHLnAp2Viwlbpagrqyy5i9JEaWlo8DHLLOt3hSJPP/cK4AKEUadGQ
uxiVOA0lBQc2jTj883rz8KDflubh7hGTdwuxxNs8ZKgt6p/SXyTQGzXlMdZzD9BDBBszK8k0sKTl
sBHJg+hcv6aJ2K4PTWZ7SyIB6SundFTIswsh6e9JOZkCtWN+jjJgbf4y5gVAnjQUZ4DqNhcFXJjD
0TcZlgbOuhp8fU52OtXGQzS46IppFXlWl1UARmrcAST++wZ7Q+Ex/QQddavhiR27Ru+AUjGpGxjH
3M6XMoLbdcCmxaVHTKVACZWotIPdN6PjaUM0gZ3KjPyRRISgU/2RSJJ20Rww1M5KcFuT/no/7Vaf
5HSvkEiFY3B6zLrITtUi7XZtrR2CqC0ViPPZmV8gZMrIRGwhzXVoNO0vLmObcDpWy2H1RDeTpdbl
IOEWWgDnUhjzfbTWzIg0kfrf6yvotmSo8b9W4gNbAjW2jlRIt281MPq/1P9woLtDR5iMYaqf9uIU
xWf3j8FrNEGX8ZHFekeoSEhyVKAZf8eEvzLawlIoHNrX4MHqDJawNrdJmk84VDDeAfxKOpVCfYY3
wkpZqPls84YHcJVAGeJGHs+ILann2ztoH7fWsO5DUbCAkULwJ0M/OIWcMdlRTEpsvRT1KiaCT9oR
1O0EdgrSUwgUcK3UuIie3gGFTErONYutjvPfm+1n3H25MCv3xhF80sDYh1m7FC7/aJllG2WTM5nG
3QNfBKNvmGEej5gDYQ2rJTh688+Letc94vSNOnN96shi9aTYh+G5eq9WCVq6MxEh23xkZeAQQxC5
fpXiMRJMIdWFlmIa0QEZUbZ3ycR8IrNg6meCW9KuTedefl+JxNq9e1LIk5nDS06Wakzzwr+/AgMx
0c/k6R2cIVeJPlXUmr1Dfeebk+yeVQ7LijwNNFngkyCiw5TDXg5V/vWILNImm0U0UxrLbMSNVTVM
urtezlUUn4UyhmrgLJHAYt0VA5wyKtb3IIZxYpeleWl6wt2/vwZgRXOmEtQO/IKS94Wi1sPh4fjH
z9uqlim/uh9W+B3DNQo9bl4LpVhZ7h5wW5na2YiHUtuoN3E/YR5/IJyCXTJJea5CvtebTq843Za4
dqCqQqodRtdkraa98kjxqYJFI4m0Afcu8PIrRLFnKoys6p7CR1c6SlgudmFUieyZrsacDxi8ZP+Q
Li2NY+9u89U7SgKVzBolbm2PJAKDupl3ddqGJM4mDcMFNs47xIrF3lWBkXvXhW8dfT3DKrGaImvP
6C34DiUakYDHzKRSt+/k+2CBxeSegqLn/5U/tC7TYyu4P8aY7Husf4J2vwBxmatPTSlUsGrVT+uT
WeURFm5y46cZ/2y6eStVLR2A+OKh4Ks0uBKIGAo5w+FBOna6zgB7XVP8o2LbHnp2JCmTA2WJhOFC
g19RQ+pGCBLqNvfwqu+A92lBVpf/dFV5KVLwcndLiDN35qPnW9vmuIdJYjvj8QKmq/jX4fWFpc6j
cEmMxshMhi0HlaF/r9/dxA69OufvPRzqbmA9DqxXASuorQm23V/AQqkXZrV3OOba/PaLLEOhqBOT
L61oEeds65JH/EN6N8hF4T/sUZayuM8b+apWHqaeeMGdaTfSiID69oGTSuqInuRlktL6Pz9z1LV+
QFKKX1QDipyocsO8KaaIyfTvCkJyUOoN/HwnJxX3abtLC5InD92CY+WaBmPrb6tTw5m/kNhsi4q7
S3U7tL+q7+ouirgGvkY/uoxaunmSIKhuag5LvuSej8/+DYd75Y9moaNN32ewPzXo8LpBFYfrJBEm
DzVq0iZTAaO+3TpAtwUi3dkIyN2kNsTL7kbmJlSGZOVzh75aYV5IxleyFxwRVm+jJaYabQqyCrkl
0dnKXd+D4dsDqchiamAKpGe1X6RqIzDmIs8g7mWZ1LBYf3FOfspn0DGXQ5lHMFkcVlDzYcMosEEg
K1XlvTxekpQP74O+saPLTAMvek4d30pr9MCZMGAgh5U0KleS92n19OAZQC5IgdsIsYavnNKdMUeh
ZupuDS9cvPNFECrRPXiIXXqtYGRoQnuO+IvKSffHXnQoEeAnaJhKQj/FEeaQmtZzYflM9RO4mnL5
1gb4u0FpeA/nh0tGN3haGDt9/zULkdDGzCM3MYyJu+xcUNaxCtFqM1s+kqH+cAPS1xcJiGDj/Bgd
k8pleBG+5U30pOlEUMxkHlAPaW1VRKJD7Rdbb9lxlWbJFnH+95OA/FKVPYdmeq7WUcjar5Qjw58y
kjBoTtwmbP0P1Zgoha3qwCGQx4eiAjpmErNxV7th0RqLYvjBdNyHzGftdzYoAbbMe+EV1ANPgBiF
Q/hzJt4gaBHKaUoD2UsckFO+kXLXyJASNPkGHl/Rt83h2P3jkgicP9Q2ospUg07DJXcdp6NcdDMb
uX3OBwLcnxfHXY9pD0QvuuuuQVUFlY9AlSSizWDrFjbuAV3vMVa/kE8cC7OBTz7OYfEyPvRs+qE9
9wDh7UwzEWWCcWwFq/fk22kYKp6I0/bs0MZlYju8eYwco/3vDchMDBCYZYLHubDVSWJ0PaHb1/6n
dFCVIXvrEZgIkZXCr67waQhBlK7LJRt+ppKyuNpAJioBYK6NiX545XHy1lXppuSst06QF66bXdLw
2vJ1xHClfmFcXPhO60rPIPypdTL0KTObzGJ8TOcQaE2L0b7IsHnMR8tZy+T6YBoJCNUB/7+chVI8
R8BE1a9mCRfD8ieIPZB6iJ34ABdqfMLGbNEcRsP/lTUpSIo7W2+8bAFjTLzUm8IlZu8IjhQs54nE
KTf+y5bOTBPWH2Fn4p1Nj8BQO1iRbvezwlLCqlmSZB0FNRRouOKhp6DzRWQ9bS350ZHYZLnXKhy4
brrTzXX/pCkIQDwbjaeAUqm67LOej94Y7O0a3lmV6VBHva612iw4x4zTj7WOwKZjiwhlOvgFlZB7
vMAi5028dr6hx9PCDbePcA+AR8MaWhyXXo0tKBVdFKNy9W0eA8k4O3BDsgmXFtyqJhchoOExpLvE
2/G+MYDSa0SlCwbzevtN2YJGoxjm0oNoPm+BOtIMOS/TpE7L68gFyxPUvsPQS48LMarTDzv4onFw
GXU2Ah2QjiDTW0O6iavdPrCVisETovslk6oHAcZR3H2VRPBt/ift/ZCXuirUV3JzOVXUY7wIdNhs
h8QXwpjIm8G6mesNVPoLkh0kkvE+ZgRNuYxRnn96j/rNJKFnGYaVLi0iBuqgw96s989mHNWx1l6p
PfH0SDNAyGFgV0lJMEm/4U7xCueuSrNTy21EolR2gau3c+Dbggb3BsveF88jY9muwG4/nyy6svWj
ck3q8cvnaPiBcxNjVZ0N60O0R6wNcLgk3zB4+YZpye5W7yeneWQMPGZAKr+DE0opmJq6poa26TR/
9jbNOfSEVoCwQft+TkERXM17DYt2LYyN0jI8ifinUyWn/50S1JpuRKmcExH1yjr/tkGEzCdlUxv2
tV4F/hOnl+O7FKEHbU9DEelV+emS9pNbPLAWIAQ9Ol/uYYGoVT2zgknFBf+XM532ynnQPn1zBVk4
h4OZCK4oW7uAMnel05mgFsvhZCnMeI9BGdIgc7eZsztwNNR0xpnSPSR3GERN97XV8yD92p2MxB6g
wolHPYtyvwP7x6YU/hNP+1N848u/PgN4CQiaS1mjiHvWDaIMOwemxEJvjMZX4zjwxIUcZeluYOl4
26YQJ005H1uDxJhlMO8QT+yXcCD+qVPUPDlrUWv7fsnXS4UBrvOkEg2uTrSUIPcCFcyE5szrdR+H
akXBANJOs7CPbPzeb++YTV5tpUV0r56gRPn8FA9CddVr3IXsoTQeOQ6o6xiNytVbvwV6sAab8wJk
mU/hNmIVTI6G78cZ0P7lVQSo5+qoUgGm5rarcSYROOsHmZWMXrCaDvNNwZ4SX0AsKjcag4mxCYcx
fJS4nhv+1UnbjoX4epieaxzYtz9rID5rn7UVzSwRrw3RDGBYpIQYCNkUCTU7XVx1fpzUhSgR9RmY
6NH2cGbRsbSzzs/WAuPDx1JlfODxdsq7AszI1NHfnpwkkcMEhyhVgTBg9Xu6LKWeYINioxsTVypL
TASuTyOGlKW5ieor9XR53/F0EuaEPDb4ZUCI1EP04/u/W7VIO2vNOMA2RkrjJSkU9QIl2kx128VV
IZlrfHxy+Ooae0SgR4MIznzny12oG5kBY6CpYaN7Xxi9aYoWIuUtMsKUlf0EHke9GcRaSy1xJKEu
qB3ibzVcIl4npqgqMKQ6e/PxvFwSHO3WXfJ04S0+HbNbZWnd13t6Gpupo3uUIlG/984I7Rf5Q+dj
xvoYHVuD2ZlPu6uRJD50KwKMes4IqimNcBWVlNTRneH6uIq0ZHP2QLaxZf2Y85PD1er3NVw5go/5
bO/bEa+nhDSjcIENF/nFUBFcNkUogTzeUzT8w+Yh0Y/PWyH4PijtAnzm1NfKwtb+o3sZB/3gsecq
vdzVivfDYUAoubbKgsP9JB8B4aCmO9N4Kg3YAMnMzD2TWQjo4P8Ke3qcJ17VEe/04kWAmURRVsp4
YynOUTMcLbSk66K19EnV/E3ssCOf4DvVa0ppVIzaGSp/17fvC1f4Izy8T9/XA98os/MqCtSn+zIu
FHhFlFpSbb0g7Juz6w/0HMKH6Mug25X7LiH3rtqCsIJpgHGVP004MxAmy/SCyjHX7a3oAFDgyJPl
VjcLlj7TX1M4u7ngbjyJN4oP1WwaBsqnAxyS2PJOJVzfZALcEZCV5VAYzgEhoQJ30WeOzRwlxANb
tLT1f+TpF2quKah/UWjze1cqJVh1xhau+BoMQzNx2M7Zgo+1wNcIsoJp5SAjOEdL5oujGd5UQq7P
9bgsJ9Ckw83NSCNtSwFIt+HnCQl7fPZDUwYrDXUzP4I7AJ0BYRpXJwpS9V4eoJfO0KAmUpttq68C
w2DvDzREU2t4uN5vO4aUxyk9jHVgk/jS+qsdZdrPtMNrSqB1AAl58spSOGOHFgwcyiKUESdcEQNf
50Ph0x6Fodavdh7Srq2IHTGnqr52X8ksEY6LiYg67NCOGi/vXQtCGHyt8feKgVcfu+KNPzHzyXnP
xbI/ajOtgPBZB8VapXo47bL5yMiQGlUtjPv9L9DqwPsPrUKm8mE9Qh4UqcBRHvp1eGh2uQ8Meyyq
3YdBc8jUE+CHgy8RwNBMoHyKL0UUhianIFXH7XsYwPHjcT6QziEJPq4m6x8Mq84FvH00euqF+Vvm
sRRMHY2PSoqLaZpmG/gQM0G8M5fHpwbGdHtpI3GMPNcj880/tnDGTRJf1bD7tx78CTsfUKmMgjVh
Y6N2IkIk1haD7q5oesA8ENyZdEb99EtQIlOak619RKJvZW3Wgu3Vkn2ldkYEAZagvBmCMosSMsGq
wHygLYrBuzHDSKnP89SNmKGvZosIqBQTYoN20ChyWFLApcBCwQKe5U4FBvnXsmv3DpqLHCLkQBok
wTCgZ5jslgxs6tpNSb0LYJRAOaAyPuTRCpNkAMH3vwE5v3yJpkdAzU3lQvrqNDfXqDICOqbGmuW3
wqtRxnQd17ItFMfgKxN0mv2lsLT1FXu2wdLvkd0M7aEwz4ZKU6VdsIS3xHF1zrL410IQGG+74mTA
3eDT64/p+ctqW2v7OrYTvj3tGtmUoodGXcQ9nSdk+C9uB/C2lsuIKQwg5Jr++jp/rn4aHWoDbPpx
5Wzll1fTCkqy1u80QDTrVOHpYppj+GlIkJzYOGmbur6gAMGXdYtGR8R248BiOquek3oMkW8vlZ56
OhTrI5+LaPLXYO6zk1Fxs5nUdOIorA4jg0zme8n2yGWrCBA6Gcs7RAjCvCWfKsGKf7GaSBIZymwK
NAFS22p/ekzCbsAGzevc8XXG8q8HfcVGVdpHErRaWRCjbT//z4aK8vSm2+sa8BhQBO7dvLfkEi2D
qIq3eIsKQiNSy2pu4Zw9tq2zLAvm6s1JHpjL5Agm4zDbaJ+hqinoppCmsqHYdbKmipbdB5adS8OU
OeNF2f3F/BGV5HNFjfqFSGYlfk/sjoTkVwQuE6qepGA+KUZhY2nTZnsh6G5AVidRWfA7wSsZJw8z
PhQEyjMknPNvo/sWQMIfLPHGLyYZMce9MQamIo5YE7GMgIxgx73KQ65z9X2CNmkVBJ+QIcglrnym
WXsjaZvpVU0thbLp83GfKoR60hMEH/6qZ0ZcOEaLvk6GubLuv2Y2Lu+40Nb7/HTKc4ucy1Z+r3HX
k+6MOXGjA9wFH0BhxZ1uBqhQrNwd7RQ4ng0lfCg61ZAmQExlCZhJrohy9caThCIXjXEEFqy6HKP+
88LkdYN5X3yy7loZEcBKgTrVjqPMhc5Am6ehWeoal/+qa1TrkIguq+962D8mrFas1saBXy0W9v1R
S2iR6LIKXkPCXnrtTz4yf1aJRLkjUNQlWqhqsqDYvkSGVLSsRmwqGi5haEjgXuDjP/5vDGyRFgtE
mz/5IsA4KrY0WzNztdJx0PO4TD8obyMAASFL/QNQomtAJTvxnvaca2+DZFwawx/eTDrVayGNfqWJ
uSRaGFBkrQnX/A1AVl8EXSgv80A3ohPVmz8Znel51S+1JRfdfObOA05X6bVaKvT71KxKPeas1FDl
/mhYiwQQr8g/pp0RC8aVmZZkuaTLh9qOgVWQKRN2jvKxUHYWgc7jwf+TNnMiCuigL3QfcyCqtgJB
EuwsBfLoxlIH/ge/qEwAPG2N7epibQsRs9YzxbpUGprbFtKskt0gLh/iIZndxiZg19gtAkBcZiPt
WWovSosfbFCrhQq63IvsNSPxjsLDuwuqopNqn6Phv31lRFivdUkxcHEYYAHTo6eocaLWtr8CtCwP
bhHjWn7SwwGh5VQ8WexCveaw8R3TqSgtHHi+qyiyLa3XnV9KdKdkwttUCIXLQnW5a8N0WkafXnr2
z+iUPEdLAR01qBsZDsXP/Ct/qO6IZkYkgvuG1jMji9ObEfuRgDltainxHHZDgyZTIiXT5UdNfpqL
Em0w7C8f8+N0vmHlpqTf0S8JPUzfqXBH2n5Y6ySuNDbNoIayFAZ0SHA51Osmibf2IEuN3ReiJ8+e
hnM+s/odRjXYQAtsoHQaseDHLVngywDBecQQ6W7Sx4N0ta/71G60fMEojB6skDhCBfBs6DO7pVBL
nz/EC1fusay4UeAoSoIaLUElzVT+TriQg/rxx0vnqbhYHUBSGpDv5kuQ7Mi004KuAvHbvYLkFXGY
p6AI60d4TRacYGh4uBQh7eRMEkP4T6rruIGEtNQT+tU57IQ1oAgE4avScs4EDfAzcY+LRDge8UW+
8sTvZjBT38N0UnGcK31z5d57uNjzc96ZPnvXrxWhUgf2/A+gaimlBU13qOZjx47Lb9SXS4AHZQND
ApYooWzxodS4KsBZ/8i4qNczcMEqRpfQRqL2Zw/1lRZP5XX9ZC4WoOiK6oEhFfUQeRzvwbZ3MyX9
PtKSRlZUkr9jALimMkWCLlUIqaqTS/8bftRdw2RFlIXfqePcUMOoCSE7sktDiLK5TKK7KtpezvzY
Lg+Kv4LFQL/xRhcS4HQ4SHJFVwI+92VH22HONADNswhMCOwcFwBRb9qg7hqccQYb1xc8gW/+qTJ0
C9imAm+U/LAWvbAegESyaMwtLOZk/dpsy+gdUqFiURBoQaXxlBbwcpZRrbIx40XnrFXv+aaw+NFl
pe7xki3wX2E7KCTp/YdtbDjpFxjf0hHPu1yAof/tgayZECIcyJyz91GoWU9dWK52WslBM5ClZxbc
TV2OzrHMU5zxUodNS5KU2qU0uMrfwldlQfdOYPjvIOtFzSOK3iAcAd0K0FRk9e/oChYI/p5hlYIb
I4tVDxDOJ079qaOvAchCLQkqXBFEvKbfdVndA6AadTEd3NeSPh3MGpa26KR+aNhLYO2hgyntVoe/
nyOJRVGi869wF/ZAS1v11XcChQOJTJKJXaj81n5g18FzJYbYUTfnhc28G9uF4i50aTRsRCop0GdV
D7j5snjr8BKXVnVtdwiPHSQ7EtEYJitSQu1ZNONYEdTu2t/tF6Ti5qjH7NcOO+1AVDxwUoRUOKc/
PNI9glCPTsnNBAFR98odk60H6jn6DIGPrwZgj2s93Hn7U+PHnY6OBenjS0NTk7MWae33/TnkMls7
Tn2kk4enFrWpjyKin2ihgt98Y3gLBJ6Qsvd5GdZzgCw0ZK7PTX2N07vFW4oTFWK3X64sHoiyNONb
xmPRd+Qm9WdqCpCKDl6VGC4mvWFf4i0dHzVBITwkonGMJH8nFyMviaOWRpOLZ2tMsSVDOQ9zfyJQ
YNNLqZUWQEeFmI4qC2yiNpsR6lDThvO3MVyIddLQsviV96+rc/e8pjv24VJ2VoxFzlfWoUcb6KOK
R96EMyxPEH5oMZ+NUnekKPaBEXrMuAQuDMNzP3jd96JyeSobabmT5O2JaoUXuTXRBXsK+4Pcrb5a
T6jrNBY4qj234TtZy5FqH1LiMq9+phO3A0IsvBWJmAUgnMRRzdjMX7P/Q9ExBv4dsufesvRsuZJ6
MnD7a1xFGvumEENoE3LPMfbzxMwCqxjvANp5obj+kkwqXxmHByMbMrZkjXEbVrU1K7lxdNeuX3iY
j4QyrdTDIHJQ3ZVgfSu9mnKOYv+bX+xwBhpPOX1DKQCt/npDDrNy5PWSM0IpRzBiHjedS54GK2wb
2DX/xZdAh77HijFMBAKYNZPlZ0Cza8567nxaJfqt0pT50CqkBROTE1qLr+lMDmUrM1IE5cKZNV0H
6cZkAOUWnZ21F7qZUXB7W/I22B7xH40IizvkVITdNZeKC+Nw8PzD+rcqGN5gopUgSlw/WR//KWG6
4jUzBvvkt+UPjVTQ8dNdgG4PfUewXeepzyRnPdIbtyEcMuWzv47uNC6s23hyir6/labE3pFcJhG8
WtAg9CZkigdCVtPMGrNJpCzAn4QuHgAWljUQKUJGZE6739JqA3yF+XK9Tadhf0Te6oMxVil+BSVZ
5QXT7XIgbMDXsnxQTjstbYuJTiU3iviQT1lHmSznfickji4GRmbucuUnQiFf6zUNf8WCNKwU9thc
8JVQqzj7mKg72+s+qhRhi2nfNo4ROP6oI/Hhlpm6O9tkP5EeWoVxmc8o7YynAFzuzODTglVAsLHJ
XdLkaFFgJ62USPCyKP1fYlmKFXnZ40n1s0xfTQxvdMr2g3WIr8iSDKHWpcqUozlnLVrMgZDx4RAd
wwX0V5hEIEa/5tb1wt8OlwTXNjXOFDL/3nuBBnhH4Jfn8ucWO4D576SVIX0i2QhvsBpxNmbAGKbr
0y+E0Vn0fweMyF3oDdBH2oKg0TQXvndW33PCuDKptgY50q5WIoi+e6Pc4IMc0/O6yIqLvZnnhE7Y
sErpvA/lg6qnRRcdJWnb5nT91iHJRBxtsX3G0micJQoEldaydpUUOw/TDyBdLCU509fDvPF7N/0I
plBCRY7UTKYlk9Iguqizs8ZG8dt9huT4r7TQD7wAwIjuW6a2LfkXd+oU2wtoNyibGl7rvdYaQBI3
gAdGN/M16me9v7ys9r3FhGoFbBjtaCvVkPASam+aiyYJe1wST/4WoSvZlz6jNC9LqS2eXdJ+qd7P
gXGCJ5Wlnkbnzs0qf9jBEItzhrEg/3n73B4ts0U36DrOWlQy/9ClyFnRqs6nDeS49h3d8mCiZAwZ
2KKpEKJd1UXT/EBgO+JxNFw3GIwyU2+atyp298amQjFu1HXmW7dpuK7qiu+Y9OG+lYAoS3gsGMXD
L3MowdEGo0NugG/aIJhJHgsxXiuf753YDUswSqr/h4vwyziHQTaCGQYDb3rnxZamSw7wv1ffiHVY
reqGCYk0b4FGOcdqdF4qzLkTLkJsDGqRXwAvP4OU/aKII3rYDnmD/oFRmI4gUDpQ3By7OrvqNus7
QIK96j7NySUHr6VFLWqVDwWFCp1UOr7/nmJgaY6BvextodzT/vcsGJ9JyvGLFdtn4mIufCTOP9Tt
drtZamBNFJ04YtFeGKbisVAJgQ5qbk7xdUqkq1HUKWn1SQDRQ8XeQWGrae8cu7fa3MQ/sSC/5DW5
ppTWQkS2KSUvG0z6OcOogrZCC6wo+oT0q0OU1KYvBdmR0VP8vJyoNtrHAWd9o99an34vzPhhOJwY
RlNaN11RZD2u1mz8FGtWSZUwBme8NZAS2DsfVLMYqIQebUB89Ezr1mGST2ID1zo7fCwkHhesqICk
FJjsQ5YL6vNd+vmS/lcIrLT1/BkdiYXnY6J7wYFDbnK1nWvWmiI9mV+o+h6BEs4uVbYtDM4sUQTa
IcA5LeycCSp6Qs6hNS1FZnYNG1Pt/kLay1FgU4eUyARwj1mGv1ZgkAuM2zWImNe1v4Ha3xInWdCL
tHI8spJNLhwgvOs4nI+vaitli+bB/IAizUBeeE16Ah3pQofx3wh7+qWs7HH3Q3brjDAiefqoDRdN
VoyWsgeL4MGgTdSId01jJ0QT1OnXthxlpncmsB77R1I5V7UT5kcIb4OYCvYnt99zKVP8/M1vLHo4
eJqoN1H8foezdKX4wSNVBHVTWKREMhU1zwjoF/5xd0eKTYTUwpPgdD/lkr3XEd6X+XMaBq5LyisN
TNWwOX/+phtC9Z+2/FRii0XTV+6x/Oo5l4V/0Ti+J7SZYy4tBfmlWWNqpOTwUV5qxrkRzPwAa3dr
luE29AkOjdT1hghDz9Tta245/pehRNy8Gv0Zbex/o/0cR+kPZ9CxLk6+RBmvA9F17pQjT0JdZYmD
sUmJO9t4WZeqny+crm4G9xBO+GsUhjbGhXRpNYWcNlsYWZnWtsLZ+NCQFV84XZ7HXDR0519Hqs2d
rBy2nK18UZVvPaaaBZhe6Dz9Vbx1IaiU64raMimLAIqDvnSs9khi+67qC1BqubqsYEEE+dnJhGhX
2rhVxsFt7Q532vSsW5yZiz+uyrY9qdj8Wl/NkkKq0D9vqmZ05yWA2T6MbY6cXRjgHfu/j9wRrf89
0wC5xV2HKcGMmt/cGDYF6y0WdnWWkJPb7bH/0FXgNMQZJorAvyi4hZxmWB2VWaVpoKCCQ/Trhq+3
J/XzVVC7n4LcOAjgytZvUJx50fNaB3f4MshbzjGW8fPYOzV09qEgZyZRJMqYBPCXctGhLcR+Qo7p
TK5AVx+v7Jp+Mi8rOzdJtxvIR7ySoXFehn/nLbyaccyvujY13w0Lq5TR0G1KgGVIn+2FOVgfGe9x
tDYubGwLgm0UeFtImZXJIRUfSd/gEDJTEKfGd29q4JOabvO/aDm73lMjTZ/tp6P6t/m+8UghJ3W2
2sW83i7gy5XUOtM/PnSwEqqqt6ZSheC91RS8Rp4ofeCyl0dm7vJ0k0m0ZCZA62MH7Z6kBJ1q9oDf
T1Q+X+eNTjO0oNUmj2l2HDWk6MHZApdyd3Okb9geO6AlSSFpv0jd9Hq1aZP+cNkOnpIUO0SGZAkt
xm7LBoku05bx4u6LkDKKPGp7AHiZc7XAMn3yz3ajvMf5zZotO7Ld2UxVoSiF0Wg1e0B2yFGVViwf
So+5Av564MHmU3Lv79EaReH1o1hBftessv9oPXcJvmLaHNXZ4Re2SBoiWT8L8UynCshmkRefaWgw
qimUpAgHptNWe3nDqDuWRNd/a+QSKJ+a2CWw7JZKN5RPQ1Eq8zKXC5sJb91QBtx6hqJsLLUFwJUp
iVGTTr56sZ/c+dlbl74ia+DfBrpNxrWx6l+Mp26xTI/eZn7jCpjpgd4pwpHyOK16iEr3OxDmI5CG
GhfimRpTgiRjjR5Q8GUK25wuIZztlWnLzIR4Lk17Xho+8Q7eYWRp6hayTLHxDW7K+qdB8cYsxl2I
TVtQwQ8F1jvtdKbBwOmAeGYmFJpewJLC9RsCfyZzmN5AWJVvqdDyEFrfequYervrCQKHk6Aa+M1k
SMGPd/GuwDG6Z7vPsna15FWU++eW5CPa/Xqhkrg+yKTZ+IcVHmXlenr1DwINb9v2EPZjvzvWh9NE
fyuY9x1MKrldJG1Ro9O+hzLJQlZuDw1MM4BBolStrXHIMF6/auRo3SOXGzZ9pHIDqwWf1uVVmxQC
UvWxv+tgpPHjHwZNZ2noubavTp8lXkIy/ZjZnlRK1OJLSFRkToEInItao1U1Fm7+OKFzdnIOepsH
0GiVeYiaV4r8QKVU6ZjxpNpH+qlAJEbuV1WRoRJYnN5twM3whDjaLRSpW3c8lnn3l9ngNHbnrbxe
FLjikR5sj/zFrzethj8v2acUyxlJ2ekuEOaQAk66cYJ9H6lUwOYrF3UNi8UCT30vmp+U6OdIPg4s
7qxqpQJfVLLG9OIFe36b9GVnlTNSaUWLA4rCotUdt+5o/ag2xExQHhX8Wa923gsHe4UfJ0yNlr04
59Zefekzph6BF+SAOL2mNJ6o/LrOdlMLMO7HzPKzbzZSDW1t1AjUrAy29Lp8BlQnfpw/dBWZnRQd
oophT/zt/Hsgb6g/82gsNezUGTMo/VgBObY+tMuLp9caRS6g/c7Atr7hmIakUVaUrNOzXQUdP6hG
rf5KXkrB3eT7XgapzjURc1rwW1ox0REn37Qu3N3wx8pTx3gY7mCWStcDC743zRCo+BiXj7lgx1El
TKSXzkmwYdEN6MEX21Khnp3Qs08MuLRjeHF/yRp+boGARnHCHZnm0LSIOlz4Z8YYoyIzYUgbzZ9K
hmW1x08sJP4NdMc3QNh33yO8HmI+tH+YlixohWAixeri1ZqyFqk9MiNDIRPe5hm5kNd98wwXBICA
xOnfBzEC7W8n66uYbuuzdIj0kiyFJYNpSMwh+Oe47UWxFO58R5Eh3ycrvD1+iDEPz6LRzU5oj8Ro
VawuXttSCnOB6T5mBNITOGgdi6o5p84MxPc=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
rKWwB0sGGUajpurVPwhHzgsZATzg6CI2fy5teGZgwWn6RJSxvVrm7X6KC1NlYW5YtUDp2ese/Vrm
bw3OqIV60Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
BRuqFpGYGOGwcHOC9ByqxsqWUs+0okjDxEXI9LjsXxEyuWJLFUE7YYzNDASAihgXdiZINIm5es9z
yyLJWg7azDkuzQk8G9FmmXCb4GMcSNpaTGa1FVepRSL9Yvq1uMN0rfkU8OoTCb0JTco3mn42K2KI
S1jw6CGiZKnXjxgHNBU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
X3xfyzvjrmPkaI9JdFIRWVWKvQVaKvW3xkPmxmWB+Bg2oVsfAsBqh2i46hM/Bcj4vTlgRohMAtTw
mZrr7U78E4bYF8iEtFKLdIJEd7hVOOlmDwsFBDzxg0k47kX9A3ruJ30LrjKdxboHAuMIaT/XR/sU
upe6flMZr8VBlv8re7jyziDyWZOLqFpjufskTfv4OQj1KszofT4kUnArUhuQ6UVlh5i6v/pQEzIn
QBP9XWEv/eQfQZl33K/QbbRAZIttPtuWp1T04bWkTuCPPKG+pDFGGGHJZvQDtAaxZSkHqZAvfqlI
CAW2rOiYEadE7tUwZCBmG03wqqm+cZJmCFoaew==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
AUXv88ADQriH8V/F9F2bxLErHxhqOWkmnlCs9b253d+OgRvIOLCtaWRA9DjnqkOKIf1wnvs/R6pY
dJJExfXVZOjD4nIH7uFh77R1TOSQouJzgmqD+K5HYb0maU6PAGIafeBzcUv5XN4HOOPvm67+oI2c
ikEGUjjanBNxts7eGBk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UZCooc8nZi2nNWJ83Gcm6qAONngeeaBUnqNHZdi1nOU1iRX6MguqeK1oMSUjP/9bRjlw7Tp3sNmB
PWJn2GGi3l8Qe6b7auDrjGMr0IkAvVTyrVlPQlMaseSN4e4IeWhVyNWjm//n/TOKlr4NMKKu7xlw
UYk+ejL3Bl9bd8/cGgsVR5ZkQQavRAFBo8L2IT7ML5f1IYG78bF0KQzrmL9GYFMnToP9B7kVR7Du
Yb7rcfK2Zazdh5MpYg9XUjLic80aZcb4+8dYBu7XgEp/Ar3GApiNMnYJUmVK0q0n9Er1Tqahdfht
jdB1SKLd/YF5uaRclGtmIoZjAK3M+1SEWOps9w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12224)
`protect data_block
t5Spk6yve3uJ1YJ8JkRzUVqRYSeuRX7hvbRJ802Wf+RbaumUpGUGs1znFzR00sTUqUlo2CM6n9t5
idaQheZ7CEySEBoOnXCDFAPgPh8ykyAiFL3Y6sdSpbifGT0J/JOeKzMD5+nIp6kLlUBQc7VQSeug
M59+p40cD2Inb5oFM8hep8qN/6JeN/AvWyjNarzBXpsddtlR8UubbsDzFOoHP85gMfreqfxKQ4mV
L7Rk+vSOBcAjasibJdt8lGIhGi/lyefdAUQVTAcr6Rk65rUmtv0s/zold4FRI0PmGoGxfBownUjt
ID3OGTorR57ZiwQS9SYT/JxWJc4zudrYR4fD8DMzWdvENN1xnOhzMhMHt+838ogv5ctRUr1L6p2O
rtwRmv3wR/GKlGn8ybNwInmjtK4+BNX5gap6mk0YnCG4mJTIiP+FaOoM8wdxiYOIdNIw+rUEBT/r
F6GFBxG8/5onUxfWtczQimgRffRR0v7VnhSMzy2cgMSC7RSfU5tBTVhvUjiZIwBwd4dh59wwMbhe
ObgOq2fTje9tphNoAT3WxoQOthjG8xxXRsX5sR0k7TcuvWX4nQV9WbYTs0pleUmspnq1k9Xs0EIm
W3y6b9BoMzHXGL1IE8hJYlJd5MJzzouUlPN9Tfwh1wrNpCDlmJ9J4GDclsOU/CZjQsWM5EUzV+OH
J1jcgKJeqyL3hOLIX9Dzt78ChPYHG1qg0Mb4qDP88S3pODWbW4+1j2AsD7uCWlZNEuMljxUnEhE8
FIE3ZCbePEIUPc2Pf6/43pOUbTiGDWhWlgErsC5o1dI6noSg0LkHfdLy18FHnFWX9F4Ot9xbxQNo
Gz2CBeKdYc1PWDPlJvrALuh5AkKAz0HEA+nOrvYQQikIUnTo+jrneOXHX5udeFGKOGj7cGhNtvlf
Tf9HT1+I7uysbP5f9/Vy2tM5W9ioHXzlY1KX/AAIXi1jyj61mytFLzgfuX9qQ+d7eZQg975Qw7wv
2K3Rs5rSBCYTDlyZff8DwG1W75SxZa5ZEUnq2iIUAu/K7a57rlg+CagNL7UfcqLTet7lwWRb/36V
iakB2GyZPEZWgje1bPPgQp1xBoLyGizRUM+wS3Vvf5n/3MMSjth8mQJeFKioXxqm4h/cJw3QGSI5
UQpah2uMGNMkL9oOvnJ9B2m+nLKg7VNIXBGxIYAXGhvdZkHt4VLzwYGcaGFdZa3OnS5gjN4TMRly
fi6w4xlKfDC7FwkEBAFjRxbHczk1q4nNDzpStSec9d5uCH3awkL3L0IMNdShksbCWmv3wwEFhjOk
SjVTEdwHmcA4oi4aoPvyiGDR1JKY7w7HjpuqE4+zIGGQkcoOyvj2XQx7JThEuPl9ECrZb0TLBBDK
bVRSzEy8HMp850gBd9iZCkVAHfMngslcOITnvHBJ4tFmHTwKWmxUxCJQ5gg89B07OGUhV1Q+z1jG
me/hXjX9OUPElTDa6TrxMsw/u+OojNDTVFA8X+D6laQ40t9oXuk0KBLM2bdF8iNGxHL65Vp8l+38
RPifxux3QEZQW22MVYOiHY8Wpkxi8t6CP0qQwMYn4yC9yAAZYdFyCJ6i3Q7BwXQezdhvpEyEH15s
EawpqFjDMh1gp/QeoJc4eMiWdTRlR1MRpchkVSM2AIbdntg04ShmJIDrsoseAyfot2a/M6/3k8tg
2ekGAX86Z6p21WYEj+pBaBr9yiAyMfxzQeEGFIJli9AMB58eQJwXewlkB3BRp3bxqFeUuHdgBK08
HNzvjIpo+x+asZypiv1UG9P5yt8EJCVQLd55M77zucbLyq+9Tm15/ZrpMQiVQKtWwhGEFM/LdLsD
eOpGAo58unYogZ9jd61lpWzXjfk8K+1Gk5Rtj6GiuxaIOC+4AaBRjHtq2rot5XeTUEeXKPOc0iP0
SSJvQlTRnUtPLT2oWk+FaRwo8kG0Z5pnY93pyvl/GJkDHomt7zBb6Ii1YEesPyGd/DOWVShIC5UX
YzP2NsqRNU/flC/VJIvO3TqEyLi3DOxbzo6CBBOz9FGAO+JU3c83f8ReokkGQPChk8pO3LTeWZWT
N299EgGOEzhgB8EVBttsR06SQ7mnQqWKhInWrSCz4sn0qPhjTXfnqKWeZy7BreuOIoOviLrS2NYv
qHuYuMcnxnEf8jkB7HR8qx9yRwaWV8iOoG/QMCWt4RGLL1zZVYvwqeoH9FZQDcjLp20a2sQPRWdH
ExiZ7RXUn4f4MvIjQz6vuGqqNnt/+6HHpYhvRcdyUJEpPCA8bTQGvTxcnlso7/c2NLzXIkC9bgXV
bu4/DPLvHs+sCT/c+PFX+DLLQfSNW6ccbS+XSkti77jxD1xeot+dVvpsvxYrNQACiL+tF75evtLy
eXfXPlETyJlEj0SAF1sg4n7F3axNpo6T7h6LkFUgPwXJ/luGCQCV4nC5SOWYh3ks3wVCist/63ob
oQyj9LmJHDz+TypWnwqEufwnUMbf1155GsRyTcDwcN7eH9FBtO2WaPfmGqugOND3SNl6xuddm0fZ
+fMZB8vXcCRf8Me93X+hqMDcuRWzEbD2WeWDqxY9Y44XuBb0Up+0jn6fsrzjQe0nIBXyPCbHO+1Q
65qYy1YXZk4xb5PKb2dKUTNL3l/uJMwRE4tiru1XLfdfgL/7DoDwRJOd5ZwH9kNmhrWbppH0RGJh
woO1qE83rK4VGj+iTeY1etxKSiMPCKYxrvkms+cdDGsYrYgG+xgsoJULJ5Lb6/B7Afxz2WGj1Wa2
w3zzV/agOpG2Tg0NYHpZAH3t5JbIg/LnzvjV8hfqflx3ISnyqkJls6/SOPLLpR79KSDBtD4PILne
AO8cxuO7eV4kXFbQLFbjQkvHi4t+WnQ+TDOxbKGEalVYXrfGmtVx6q9+WO82B4ybbv4A5/9VwSE2
TeRlzDFUY/7qTqweXCi77Zd35i2f+CR2tEn/qOoVM1/YqhzbnfdGZqk/H93gSFcfd5mI9BgQSlOp
EiB9pUOxjJb6VS5Yw1w/DJHyiMXvwtOXbjIQf6y6EYqO9eCnONXjRZDmhEHFKDaUCKZSj0PXwQZn
48YTWU477JtQIEfRJcvsjN3QOuywTXiOsoEQcVLv9k8AUenCU0i8flflczz4ws+fohE8ZUpaTAd/
+hmCtlS34dUNMi/ySWLj9TEdh5E++trzjKG0bRS/jq6LXg3QgnKsCeHm3xkqdanznPzMUEpq4Plc
p4lxpMo1ej2vPeNs3pM3+WIad+XhZa4igdbtmQ4y8wQ6uJNA9/SlmpC8mu13lc2PfVMk3AO6K6GN
RUAEekBGZ3ZNLm3GoStPzyjjLqfaQdquC9epQR344gTNFnt0LMY2rokCWwpOLg6CEIUPxDDaf8ly
U58EYklkxVzV29CR7WgT5F2M3xI/zoCgltq7OWyQpTecKtzImUHGO4vwHedF+59J5BPSjcCw2dyr
UDOqt2FosErylnGyVie4L2XxAfjIxXA+2ivJhSe3VrozHSPUOAXa9Epcj3RFxLxM3PPMeBFgmDba
Bh6wk0efbRBdKInR37PkVOvNHLnAp2Viwlbpagrqyy5i9JEaWlo8DHLLOt3hSJPP/cK4AKEUadGQ
uxiVOA0lBQc2jTj883rz8KDflubh7hGTdwuxxNs8ZKgt6p/SXyTQGzXlMdZzD9BDBBszK8k0sKTl
sBHJg+hcv6aJ2K4PTWZ7SyIB6SundFTIswsh6e9JOZkCtWN+jjJgbf4y5gVAnjQUZ4DqNhcFXJjD
0TcZlgbOuhp8fU52OtXGQzS46IppFXlWl1UARmrcAST++wZ7Q+Ex/QQddavhiR27Ru+AUjGpGxjH
3M6XMoLbdcCmxaVHTKVACZWotIPdN6PjaUM0gZ3KjPyRRISgU/2RSJJ20Rww1M5KcFuT/no/7Vaf
5HSvkEiFY3B6zLrITtUi7XZtrR2CqC0ViPPZmV8gZMrIRGwhzXVoNO0vLmObcDpWy2H1RDeTpdbl
IOEWWgDnUhjzfbTWzIg0kfrf6yvotmSo8b9W4gNbAjW2jlRIt281MPq/1P9woLtDR5iMYaqf9uIU
xWf3j8FrNEGX8ZHFekeoSEhyVKAZf8eEvzLawlIoHNrX4MHqDJawNrdJmk84VDDeAfxKOpVCfYY3
wkpZqPls84YHcJVAGeJGHs+ILann2ztoH7fWsO5DUbCAkULwJ0M/OIWcMdlRTEpsvRT1KiaCT9oR
1O0EdgrSUwgUcK3UuIie3gGFTErONYutjvPfm+1n3H25MCv3xhF80sDYh1m7FC7/aJllG2WTM5nG
3QNfBKNvmGEej5gDYQ2rJTh688+Letc94vSNOnN96shi9aTYh+G5eq9WCVq6MxEh23xkZeAQQxC5
fpXiMRJMIdWFlmIa0QEZUbZ3ycR8IrNg6meCW9KuTedefl+JxNq9e1LIk5nDS06Wakzzwr+/AgMx
0c/k6R2cIVeJPlXUmr1Dfeebk+yeVQ7LijwNNFngkyCiw5TDXg5V/vWILNImm0U0UxrLbMSNVTVM
urtezlUUn4UyhmrgLJHAYt0VA5wyKtb3IIZxYpeleWl6wt2/vwZgRXOmEtQO/IKS94Wi1sPh4fjH
z9uqlim/uh9W+B3DNQo9bl4LpVhZ7h5wW5na2YiHUtuoN3E/YR5/IJyCXTJJea5CvtebTq843Za4
dqCqQqodRtdkraa98kjxqYJFI4m0Afcu8PIrRLFnKoys6p7CR1c6SlgudmFUieyZrsacDxi8ZP+Q
Li2NY+9u89U7SgKVzBolbm2PJAKDupl3ddqGJM4mDcMFNs47xIrF3lWBkXvXhW8dfT3DKrGaImvP
6C34DiUakYDHzKRSt+/k+2CBxeSegqLn/5U/tC7TYyu4P8aY7Husf4J2vwBxmatPTSlUsGrVT+uT
WeURFm5y46cZ/2y6eStVLR2A+OKh4Ks0uBKIGAo5w+FBOna6zgB7XVP8o2LbHnp2JCmTA2WJhOFC
g19RQ+pGCBLqNvfwqu+A92lBVpf/dFV5KVLwcndLiDN35qPnW9vmuIdJYjvj8QKmq/jX4fWFpc6j
cEmMxshMhi0HlaF/r9/dxA69OufvPRzqbmA9DqxXASuorQm23V/AQqkXZrV3OOba/PaLLEOhqBOT
L61oEeds65JH/EN6N8hF4T/sUZayuM8b+apWHqaeeMGdaTfSiID69oGTSuqInuRlktL6Pz9z1LV+
QFKKX1QDipyocsO8KaaIyfTvCkJyUOoN/HwnJxX3abtLC5InD92CY+WaBmPrb6tTw5m/kNhsi4q7
S3U7tL+q7+ouirgGvkY/uoxaunmSIKhuag5LvuSej8/+DYd75Y9moaNN32ewPzXo8LpBFYfrJBEm
DzVq0iZTAaO+3TpAtwUi3dkIyN2kNsTL7kbmJlSGZOVzh75aYV5IxleyFxwRVm+jJaYabQqyCrkl
0dnKXd+D4dsDqchiamAKpGe1X6RqIzDmIs8g7mWZ1LBYf3FOfspn0DGXQ5lHMFkcVlDzYcMosEEg
K1XlvTxekpQP74O+saPLTAMvek4d30pr9MCZMGAgh5U0KleS92n19OAZQC5IgdsIsYavnNKdMUeh
ZupuDS9cvPNFECrRPXiIXXqtYGRoQnuO+IvKSffHXnQoEeAnaJhKQj/FEeaQmtZzYflM9RO4mnL5
1gb4u0FpeA/nh0tGN3haGDt9/zULkdDGzCM3MYyJu+xcUNaxCtFqM1s+kqH+cAPS1xcJiGDj/Bgd
k8pleBG+5U30pOlEUMxkHlAPaW1VRKJD7Rdbb9lxlWbJFnH+95OA/FKVPYdmeq7WUcjar5Qjw58y
kjBoTtwmbP0P1Zgoha3qwCGQx4eiAjpmErNxV7th0RqLYvjBdNyHzGftdzYoAbbMe+EV1ANPgBiF
Q/hzJt4gaBHKaUoD2UsckFO+kXLXyJASNPkGHl/Rt83h2P3jkgicP9Q2ospUg07DJXcdp6NcdDMb
uX3OBwLcnxfHXY9pD0QvuuuuQVUFlY9AlSSizWDrFjbuAV3vMVa/kE8cC7OBTz7OYfEyPvRs+qE9
9wDh7UwzEWWCcWwFq/fk22kYKp6I0/bs0MZlYju8eYwco/3vDchMDBCYZYLHubDVSWJ0PaHb1/6n
dFCVIXvrEZgIkZXCr67waQhBlK7LJRt+ppKyuNpAJioBYK6NiX545XHy1lXppuSst06QF66bXdLw
2vJ1xHClfmFcXPhO60rPIPypdTL0KTObzGJ8TOcQaE2L0b7IsHnMR8tZy+T6YBoJCNUB/7+chVI8
R8BE1a9mCRfD8ieIPZB6iJ34ABdqfMLGbNEcRsP/lTUpSIo7W2+8bAFjTLzUm8IlZu8IjhQs54nE
KTf+y5bOTBPWH2Fn4p1Nj8BQO1iRbvezwlLCqlmSZB0FNRRouOKhp6DzRWQ9bS350ZHYZLnXKhy4
brrTzXX/pCkIQDwbjaeAUqm67LOej94Y7O0a3lmV6VBHva612iw4x4zTj7WOwKZjiwhlOvgFlZB7
vMAi5028dr6hx9PCDbePcA+AR8MaWhyXXo0tKBVdFKNy9W0eA8k4O3BDsgmXFtyqJhchoOExpLvE
2/G+MYDSa0SlCwbzevtN2YJGoxjm0oNoPm+BOtIMOS/TpE7L68gFyxPUvsPQS48LMarTDzv4onFw
GXU2Ah2QjiDTW0O6iavdPrCVisETovslk6oHAcZR3H2VRPBt/ift/ZCXuirUV3JzOVXUY7wIdNhs
h8QXwpjIm8G6mesNVPoLkh0kkvE+ZgRNuYxRnn96j/rNJKFnGYaVLi0iBuqgw96s989mHNWx1l6p
PfH0SDNAyGFgV0lJMEm/4U7xCueuSrNTy21EolR2gau3c+Dbggb3BsveF88jY9muwG4/nyy6svWj
ck3q8cvnaPiBcxNjVZ0N60O0R6wNcLgk3zB4+YZpye5W7yeneWQMPGZAKr+DE0opmJq6poa26TR/
9jbNOfSEVoCwQft+TkERXM17DYt2LYyN0jI8ifinUyWn/50S1JpuRKmcExH1yjr/tkGEzCdlUxv2
tV4F/hOnl+O7FKEHbU9DEelV+emS9pNbPLAWIAQ9Ol/uYYGoVT2zgknFBf+XM532ynnQPn1zBVk4
h4OZCK4oW7uAMnel05mgFsvhZCnMeI9BGdIgc7eZsztwNNR0xpnSPSR3GERN97XV8yD92p2MxB6g
wolHPYtyvwP7x6YU/hNP+1N848u/PgN4CQiaS1mjiHvWDaIMOwemxEJvjMZX4zjwxIUcZeluYOl4
26YQJ005H1uDxJhlMO8QT+yXcCD+qVPUPDlrUWv7fsnXS4UBrvOkEg2uTrSUIPcCFcyE5szrdR+H
akXBANJOs7CPbPzeb++YTV5tpUV0r56gRPn8FA9CddVr3IXsoTQeOQ6o6xiNytVbvwV6sAab8wJk
mU/hNmIVTI6G78cZ0P7lVQSo5+qoUgGm5rarcSYROOsHmZWMXrCaDvNNwZ4SX0AsKjcag4mxCYcx
fJS4nhv+1UnbjoX4epieaxzYtz9rID5rn7UVzSwRrw3RDGBYpIQYCNkUCTU7XVx1fpzUhSgR9RmY
6NH2cGbRsbSzzs/WAuPDx1JlfODxdsq7AszI1NHfnpwkkcMEhyhVgTBg9Xu6LKWeYINioxsTVypL
TASuTyOGlKW5ieor9XR53/F0EuaEPDb4ZUCI1EP04/u/W7VIO2vNOMA2RkrjJSkU9QIl2kx128VV
IZlrfHxy+Ooae0SgR4MIznzny12oG5kBY6CpYaN7Xxi9aYoWIuUtMsKUlf0EHke9GcRaSy1xJKEu
qB3ibzVcIl4npqgqMKQ6e/PxvFwSHO3WXfJ04S0+HbNbZWnd13t6Gpupo3uUIlG/984I7Rf5Q+dj
xvoYHVuD2ZlPu6uRJD50KwKMes4IqimNcBWVlNTRneH6uIq0ZHP2QLaxZf2Y85PD1er3NVw5go/5
bO/bEa+nhDSjcIENF/nFUBFcNkUogTzeUzT8w+Yh0Y/PWyH4PijtAnzm1NfKwtb+o3sZB/3gsecq
vdzVivfDYUAoubbKgsP9JB8B4aCmO9N4Kg3YAMnMzD2TWQjo4P8Ke3qcJ17VEe/04kWAmURRVsp4
YynOUTMcLbSk66K19EnV/E3ssCOf4DvVa0ppVIzaGSp/17fvC1f4Izy8T9/XA98os/MqCtSn+zIu
FHhFlFpSbb0g7Juz6w/0HMKH6Mug25X7LiH3rtqCsIJpgHGVP004MxAmy/SCyjHX7a3oAFDgyJPl
VjcLlj7TX1M4u7ngbjyJN4oP1WwaBsqnAxyS2PJOJVzfZALcEZCV5VAYzgEhoQJ30WeOzRwlxANb
tLT1f+TpF2quKah/UWjze1cqJVh1xhau+BoMQzNx2M7Zgo+1wNcIsoJp5SAjOEdL5oujGd5UQq7P
9bgsJ9Ckw83NSCNtSwFIt+HnCQl7fPZDUwYrDXUzP4I7AJ0BYRpXJwpS9V4eoJfO0KAmUpttq68C
w2DvDzREU2t4uN5vO4aUxyk9jHVgk/jS+qsdZdrPtMNrSqB1AAl58spSOGOHFgwcyiKUESdcEQNf
50Ph0x6Fodavdh7Srq2IHTGnqr52X8ksEY6LiYg67NCOGi/vXQtCGHyt8feKgVcfu+KNPzHzyXnP
xbI/ajOtgPBZB8VapXo47bL5yMiQGlUtjPv9L9DqwPsPrUKm8mE9Qh4UqcBRHvp1eGh2uQ8Meyyq
3YdBc8jUE+CHgy8RwNBMoHyKL0UUhianIFXH7XsYwPHjcT6QziEJPq4m6x8Mq84FvH00euqF+Vvm
sRRMHY2PSoqLaZpmG/gQM0G8M5fHpwbGdHtpI3GMPNcj880/tnDGTRJf1bD7tx78CTsfUKmMgjVh
Y6N2IkIk1haD7q5oesA8ENyZdEb99EtQIlOak619RKJvZW3Wgu3Vkn2ldkYEAZagvBmCMosSMsGq
wHygLYrBuzHDSKnP89SNmKGvZosIqBQTYoN20ChyWFLApcBCwQKe5U4FBvnXsmv3DpqLHCLkQBok
wTCgZ5jslgxs6tpNSb0LYJRAOaAyPuTRCpNkAMH3vwE5v3yJpkdAzU3lQvrqNDfXqDICOqbGmuW3
wqtRxnQd17ItFMfgKxN0mv2lsLT1FXu2wdLvkd0M7aEwz4ZKU6VdsIS3xHF1zrL410IQGG+74mTA
3eDT64/p+ctqW2v7OrYTvj3tGtmUoodGXcQ9nSdk+C9uB/C2lsuIKQwg5Jr++jp/rn4aHWoDbPpx
5Wzll1fTCkqy1u80QDTrVOHpYppj+GlIkJzYOGmbur6gAMGXdYtGR8R248BiOquek3oMkW8vlZ56
OhTrI5+LaPLXYO6zk1Fxs5nUdOIorA4jg0zme8n2yGWrCBA6Gcs7RAjCvCWfKsGKf7GaSBIZymwK
NAFS22p/ekzCbsAGzevc8XXG8q8HfcVGVdpHErRaWRCjbT//z4aK8vSm2+sa8BhQBO7dvLfkEi2D
qIq3eIsKQiNSy2pu4Zw9tq2zLAvm6s1JHpjL5Agm4zDbaJ+hqinoppCmsqHYdbKmipbdB5adS8OU
OeNF2f3F/BGV5HNFjfqFSGYlfk/sjoTkVwQuE6qepGA+KUZhY2nTZnsh6G5AVidRWfA7wSsZJw8z
PhQEyjMknPNvo/sWQMIfLPHGLyYZMce9MQamIo5YE7GMgIxgx73KQ65z9X2CNmkVBJ+QIcglrnym
WXsjaZvpVU0thbLp83GfKoR60hMEH/6qZ0ZcOEaLvk6GubLuv2Y2Lu+40Nb7/HTKc4ucy1Z+r3HX
k+6MOXGjA9wFH0BhxZ1uBqhQrNwd7RQ4ng0lfCg61ZAmQExlCZhJrohy9caThCIXjXEEFqy6HKP+
88LkdYN5X3yy7loZEcBKgTrVjqPMhc5Am6ehWeoal/+qa1TrkIguq+962D8mrFas1saBXy0W9v1R
S2iR6LIKXkPCXnrtTz4yf1aJRLkjUNQlWqhqsqDYvkSGVLSsRmwqGi5haEjgXuDjP/5vDGyRFgtE
mz/5IsA4KrY0WzNztdJx0PO4TD8obyMAASFL/QNQomtAJTvxnvaca2+DZFwawx/eTDrVayGNfqWJ
uSRaGFBkrQnX/A1AVl8EXSgv80A3ohPVmz8Znel51S+1JRfdfObOA05X6bVaKvT71KxKPeas1FDl
/mhYiwQQr8g/pp0RC8aVmZZkuaTLh9qOgVWQKRN2jvKxUHYWgc7jwf+TNnMiCuigL3QfcyCqtgJB
EuwsBfLoxlIH/ge/qEwAPG2N7epibQsRs9YzxbpUGprbFtKskt0gLh/iIZndxiZg19gtAkBcZiPt
WWovSosfbFCrhQq63IvsNSPxjsLDuwuqopNqn6Phv31lRFivdUkxcHEYYAHTo6eocaLWtr8CtCwP
bhHjWn7SwwGh5VQ8WexCveaw8R3TqSgtHHi+qyiyLa3XnV9KdKdkwttUCIXLQnW5a8N0WkafXnr2
z+iUPEdLAR01qBsZDsXP/Ct/qO6IZkYkgvuG1jMji9ObEfuRgDltainxHHZDgyZTIiXT5UdNfpqL
Em0w7C8f8+N0vmHlpqTf0S8JPUzfqXBH2n5Y6ySuNDbNoIayFAZ0SHA51Osmibf2IEuN3ReiJ8+e
hnM+s/odRjXYQAtsoHQaseDHLVngywDBecQQ6W7Sx4N0ta/71G60fMEojB6skDhCBfBs6DO7pVBL
nz/EC1fusay4UeAoSoIaLUElzVT+TriQg/rxx0vnqbhYHUBSGpDv5kuQ7Mi004KuAvHbvYLkFXGY
p6AI60d4TRacYGh4uBQh7eRMEkP4T6rruIGEtNQT+tU57IQ1oAgE4avScs4EDfAzcY+LRDge8UW+
8sTvZjBT38N0UnGcK31z5d57uNjzc96ZPnvXrxWhUgf2/A+gaimlBU13qOZjx47Lb9SXS4AHZQND
ApYooWzxodS4KsBZ/8i4qNczcMEqRpfQRqL2Zw/1lRZP5XX9ZC4WoOiK6oEhFfUQeRzvwbZ3MyX9
PtKSRlZUkr9jALimMkWCLlUIqaqTS/8bftRdw2RFlIXfqePcUMOoCSE7sktDiLK5TKK7KtpezvzY
Lg+Kv4LFQL/xRhcS4HQ4SHJFVwI+92VH22HONADNswhMCOwcFwBRb9qg7hqccQYb1xc8gW/+qTJ0
C9imAm+U/LAWvbAegESyaMwtLOZk/dpsy+gdUqFiURBoQaXxlBbwcpZRrbIx40XnrFXv+aaw+NFl
pe7xki3wX2E7KCTp/YdtbDjpFxjf0hHPu1yAof/tgayZECIcyJyz91GoWU9dWK52WslBM5ClZxbc
TV2OzrHMU5zxUodNS5KU2qU0uMrfwldlQfdOYPjvIOtFzSOK3iAcAd0K0FRk9e/oChYI/p5hlYIb
I4tVDxDOJ079qaOvAchCLQkqXBFEvKbfdVndA6AadTEd3NeSPh3MGpa26KR+aNhLYO2hgyntVoe/
nyOJRVGi869wF/ZAS1v11XcChQOJTJKJXaj81n5g18FzJYbYUTfnhc28G9uF4i50aTRsRCop0GdV
D7j5snjr8BKXVnVtdwiPHSQ7EtEYJitSQu1ZNONYEdTu2t/tF6Ti5qjH7NcOO+1AVDxwUoRUOKc/
PNI9glCPTsnNBAFR98odk60H6jn6DIGPrwZgj2s93Hn7U+PHnY6OBenjS0NTk7MWae33/TnkMls7
Tn2kk4enFrWpjyKin2ihgt98Y3gLBJ6Qsvd5GdZzgCw0ZK7PTX2N07vFW4oTFWK3X64sHoiyNONb
xmPRd+Qm9WdqCpCKDl6VGC4mvWFf4i0dHzVBITwkonGMJH8nFyMviaOWRpOLZ2tMsSVDOQ9zfyJQ
YNNLqZUWQEeFmI4qC2yiNpsR6lDThvO3MVyIddLQsviV96+rc/e8pjv24VJ2VoxFzlfWoUcb6KOK
R96EMyxPEH5oMZ+NUnekKPaBEXrMuAQuDMNzP3jd96JyeSobabmT5O2JaoUXuTXRBXsK+4Pcrb5a
T6jrNBY4qj234TtZy5FqH1LiMq9+phO3A0IsvBWJmAUgnMRRzdjMX7P/Q9ExBv4dsufesvRsuZJ6
MnD7a1xFGvumEENoE3LPMfbzxMwCqxjvANp5obj+kkwqXxmHByMbMrZkjXEbVrU1K7lxdNeuX3iY
j4QyrdTDIHJQ3ZVgfSu9mnKOYv+bX+xwBhpPOX1DKQCt/npDDrNy5PWSM0IpRzBiHjedS54GK2wb
2DX/xZdAh77HijFMBAKYNZPlZ0Cza8567nxaJfqt0pT50CqkBROTE1qLr+lMDmUrM1IE5cKZNV0H
6cZkAOUWnZ21F7qZUXB7W/I22B7xH40IizvkVITdNZeKC+Nw8PzD+rcqGN5gopUgSlw/WR//KWG6
4jUzBvvkt+UPjVTQ8dNdgG4PfUewXeepzyRnPdIbtyEcMuWzv47uNC6s23hyir6/labE3pFcJhG8
WtAg9CZkigdCVtPMGrNJpCzAn4QuHgAWljUQKUJGZE6739JqA3yF+XK9Tadhf0Te6oMxVil+BSVZ
5QXT7XIgbMDXsnxQTjstbYuJTiU3iviQT1lHmSznfickji4GRmbucuUnQiFf6zUNf8WCNKwU9thc
8JVQqzj7mKg72+s+qhRhi2nfNo4ROP6oI/Hhlpm6O9tkP5EeWoVxmc8o7YynAFzuzODTglVAsLHJ
XdLkaFFgJ62USPCyKP1fYlmKFXnZ40n1s0xfTQxvdMr2g3WIr8iSDKHWpcqUozlnLVrMgZDx4RAd
wwX0V5hEIEa/5tb1wt8OlwTXNjXOFDL/3nuBBnhH4Jfn8ucWO4D576SVIX0i2QhvsBpxNmbAGKbr
0y+E0Vn0fweMyF3oDdBH2oKg0TQXvndW33PCuDKptgY50q5WIoi+e6Pc4IMc0/O6yIqLvZnnhE7Y
sErpvA/lg6qnRRcdJWnb5nT91iHJRBxtsX3G0micJQoEldaydpUUOw/TDyBdLCU509fDvPF7N/0I
plBCRY7UTKYlk9Iguqizs8ZG8dt9huT4r7TQD7wAwIjuW6a2LfkXd+oU2wtoNyibGl7rvdYaQBI3
gAdGN/M16me9v7ys9r3FhGoFbBjtaCvVkPASam+aiyYJe1wST/4WoSvZlz6jNC9LqS2eXdJ+qd7P
gXGCJ5Wlnkbnzs0qf9jBEItzhrEg/3n73B4ts0U36DrOWlQy/9ClyFnRqs6nDeS49h3d8mCiZAwZ
2KKpEKJd1UXT/EBgO+JxNFw3GIwyU2+atyp298amQjFu1HXmW7dpuK7qiu+Y9OG+lYAoS3gsGMXD
L3MowdEGo0NugG/aIJhJHgsxXiuf753YDUswSqr/h4vwyziHQTaCGQYDb3rnxZamSw7wv1ffiHVY
reqGCYk0b4FGOcdqdF4qzLkTLkJsDGqRXwAvP4OU/aKII3rYDnmD/oFRmI4gUDpQ3By7OrvqNus7
QIK96j7NySUHr6VFLWqVDwWFCp1UOr7/nmJgaY6BvextodzT/vcsGJ9JyvGLFdtn4mIufCTOP9Tt
drtZamBNFJ04YtFeGKbisVAJgQ5qbk7xdUqkq1HUKWn1SQDRQ8XeQWGrae8cu7fa3MQ/sSC/5DW5
ppTWQkS2KSUvG0z6OcOogrZCC6wo+oT0q0OU1KYvBdmR0VP8vJyoNtrHAWd9o99an34vzPhhOJwY
RlNaN11RZD2u1mz8FGtWSZUwBme8NZAS2DsfVLMYqIQebUB89Ezr1mGST2ID1zo7fCwkHhesqICk
FJjsQ5YL6vNd+vmS/lcIrLT1/BkdiYXnY6J7wYFDbnK1nWvWmiI9mV+o+h6BEs4uVbYtDM4sUQTa
IcA5LeycCSp6Qs6hNS1FZnYNG1Pt/kLay1FgU4eUyARwj1mGv1ZgkAuM2zWImNe1v4Ha3xInWdCL
tHI8spJNLhwgvOs4nI+vaitli+bB/IAizUBeeE16Ah3pQofx3wh7+qWs7HH3Q3brjDAiefqoDRdN
VoyWsgeL4MGgTdSId01jJ0QT1OnXthxlpncmsB77R1I5V7UT5kcIb4OYCvYnt99zKVP8/M1vLHo4
eJqoN1H8foezdKX4wSNVBHVTWKREMhU1zwjoF/5xd0eKTYTUwpPgdD/lkr3XEd6X+XMaBq5LyisN
TNWwOX/+phtC9Z+2/FRii0XTV+6x/Oo5l4V/0Ti+J7SZYy4tBfmlWWNqpOTwUV5qxrkRzPwAa3dr
luE29AkOjdT1hghDz9Tta245/pehRNy8Gv0Zbex/o/0cR+kPZ9CxLk6+RBmvA9F17pQjT0JdZYmD
sUmJO9t4WZeqny+crm4G9xBO+GsUhjbGhXRpNYWcNlsYWZnWtsLZ+NCQFV84XZ7HXDR0519Hqs2d
rBy2nK18UZVvPaaaBZhe6Dz9Vbx1IaiU64raMimLAIqDvnSs9khi+67qC1BqubqsYEEE+dnJhGhX
2rhVxsFt7Q532vSsW5yZiz+uyrY9qdj8Wl/NkkKq0D9vqmZ05yWA2T6MbY6cXRjgHfu/j9wRrf89
0wC5xV2HKcGMmt/cGDYF6y0WdnWWkJPb7bH/0FXgNMQZJorAvyi4hZxmWB2VWaVpoKCCQ/Trhq+3
J/XzVVC7n4LcOAjgytZvUJx50fNaB3f4MshbzjGW8fPYOzV09qEgZyZRJMqYBPCXctGhLcR+Qo7p
TK5AVx+v7Jp+Mi8rOzdJtxvIR7ySoXFehn/nLbyaccyvujY13w0Lq5TR0G1KgGVIn+2FOVgfGe9x
tDYubGwLgm0UeFtImZXJIRUfSd/gEDJTEKfGd29q4JOabvO/aDm73lMjTZ/tp6P6t/m+8UghJ3W2
2sW83i7gy5XUOtM/PnSwEqqqt6ZSheC91RS8Rp4ofeCyl0dm7vJ0k0m0ZCZA62MH7Z6kBJ1q9oDf
T1Q+X+eNTjO0oNUmj2l2HDWk6MHZApdyd3Okb9geO6AlSSFpv0jd9Hq1aZP+cNkOnpIUO0SGZAkt
xm7LBoku05bx4u6LkDKKPGp7AHiZc7XAMn3yz3ajvMf5zZotO7Ld2UxVoSiF0Wg1e0B2yFGVViwf
So+5Av564MHmU3Lv79EaReH1o1hBftessv9oPXcJvmLaHNXZ4Re2SBoiWT8L8UynCshmkRefaWgw
qimUpAgHptNWe3nDqDuWRNd/a+QSKJ+a2CWw7JZKN5RPQ1Eq8zKXC5sJb91QBtx6hqJsLLUFwJUp
iVGTTr56sZ/c+dlbl74ia+DfBrpNxrWx6l+Mp26xTI/eZn7jCpjpgd4pwpHyOK16iEr3OxDmI5CG
GhfimRpTgiRjjR5Q8GUK25wuIZztlWnLzIR4Lk17Xho+8Q7eYWRp6hayTLHxDW7K+qdB8cYsxl2I
TVtQwQ8F1jvtdKbBwOmAeGYmFJpewJLC9RsCfyZzmN5AWJVvqdDyEFrfequYervrCQKHk6Aa+M1k
SMGPd/GuwDG6Z7vPsna15FWU++eW5CPa/Xqhkrg+yKTZ+IcVHmXlenr1DwINb9v2EPZjvzvWh9NE
fyuY9x1MKrldJG1Ro9O+hzLJQlZuDw1MM4BBolStrXHIMF6/auRo3SOXGzZ9pHIDqwWf1uVVmxQC
UvWxv+tgpPHjHwZNZ2noubavTp8lXkIy/ZjZnlRK1OJLSFRkToEInItao1U1Fm7+OKFzdnIOepsH
0GiVeYiaV4r8QKVU6ZjxpNpH+qlAJEbuV1WRoRJYnN5twM3whDjaLRSpW3c8lnn3l9ngNHbnrbxe
FLjikR5sj/zFrzethj8v2acUyxlJ2ekuEOaQAk66cYJ9H6lUwOYrF3UNi8UCT30vmp+U6OdIPg4s
7qxqpQJfVLLG9OIFe36b9GVnlTNSaUWLA4rCotUdt+5o/ag2xExQHhX8Wa923gsHe4UfJ0yNlr04
59Zefekzph6BF+SAOL2mNJ6o/LrOdlMLMO7HzPKzbzZSDW1t1AjUrAy29Lp8BlQnfpw/dBWZnRQd
oophT/zt/Hsgb6g/82gsNezUGTMo/VgBObY+tMuLp9caRS6g/c7Atr7hmIakUVaUrNOzXQUdP6hG
rf5KXkrB3eT7XgapzjURc1rwW1ox0REn37Qu3N3wx8pTx3gY7mCWStcDC743zRCo+BiXj7lgx1El
TKSXzkmwYdEN6MEX21Khnp3Qs08MuLRjeHF/yRp+boGARnHCHZnm0LSIOlz4Z8YYoyIzYUgbzZ9K
hmW1x08sJP4NdMc3QNh33yO8HmI+tH+YlixohWAixeri1ZqyFqk9MiNDIRPe5hm5kNd98wwXBICA
xOnfBzEC7W8n66uYbuuzdIj0kiyFJYNpSMwh+Oe47UWxFO58R5Eh3ycrvD1+iDEPz6LRzU5oj8Ro
VawuXttSCnOB6T5mBNITOGgdi6o5p84MxPc=
`protect end_protected
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.