content stringlengths 1 1.04M ⌀ |
|---|
entity assert1 is
end entity;
architecture test of assert1 is
begin
process is
variable b : boolean;
begin
b := true;
assert b; -- Should be optimised in vcode
wait;
end process;
end architecture;
|
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
lib... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
function next_power_2(len: positive) return positive is
variable n: positive;
begin
n := 1;
while n <= len loop
n := n * 2;
end loop;
return n;
end;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1... |
-------------------------------------------------------------------------------
-- Title : iMotor UART receiver
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Sim... |
-------------------------------------------------------------------------------
-- Title : iMotor UART receiver
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Sim... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_b
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $... |
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
--Date : Wed Mar 30 17:30:47 2016
--Host : csteach0 running 64-bit Ubuntu 14.04.4 LT... |
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_subtractor is
generic
(
width : integer := 4
);
port
(
input1, input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_subtractor;
architecture behavior of c_subtractor ... |
-- Hello world program.
use std.textio.all; -- Imports the standard textio package.
-- Defines a design entity, without any ports.
entity hello_world is
end hello_world;
architecture behaviour of hello_world is
begin
process
variable l : line;
begin
write (l, String'("Hello world!"));
writel... |
----- Libraries------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----- Entity ------
entity reset_logic is
port( reset_in : in std_logic;
reset_out : out std_logic;
hrs_bin1, hrs_bin10 : in std_logic_vector(3 downto 0)
);
end reset_logic;
-----Architecture-----
architecture re... |
----- Libraries------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----- Entity ------
entity reset_logic is
port( reset_in : in std_logic;
reset_out : out std_logic;
hrs_bin1, hrs_bin10 : in std_logic_vector(3 downto 0)
);
end reset_logic;
-----Architecture-----
architecture re... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--
-- PhaseMemory.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity PhaseMemory is
port (
clk : in std_logic;
reset : in std_logic;
slot : in SLOT_TYPE;
memwr : in std_logic;
memout : out PHASE_TYPE;
me... |
--
-- PhaseMemory.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity PhaseMemory is
port (
clk : in std_logic;
reset : in std_logic;
slot : in SLOT_TYPE;
memwr : in std_logic;
memout : out PHASE_TYPE;
me... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
entity issue116 is
end issue116;
architecture behav of issue116 is
signal intstat : BIT_VECTOR (7 DOWNTO 0);
ALIAS INT_int : BIT is intstat(7);
begin
INT_int <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
--intstat(7) <= '1' when (intstat(6 downto 0) and "1111111") /= ... |
entity issue116 is
end issue116;
architecture behav of issue116 is
signal intstat : BIT_VECTOR (7 DOWNTO 0);
ALIAS INT_int : BIT is intstat(7);
begin
INT_int <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
--intstat(7) <= '1' when (intstat(6 downto 0) and "1111111") /= ... |
entity issue116 is
end issue116;
architecture behav of issue116 is
signal intstat : BIT_VECTOR (7 DOWNTO 0);
ALIAS INT_int : BIT is intstat(7);
begin
INT_int <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
--intstat(7) <= '1' when (intstat(6 downto 0) and "1111111") /= ... |
entity issue116 is
end issue116;
architecture behav of issue116 is
signal intstat : BIT_VECTOR (7 DOWNTO 0);
ALIAS INT_int : BIT is intstat(7);
begin
INT_int <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
--intstat(7) <= '1' when (intstat(6 downto 0) and "1111111") /= ... |
entity issue116 is
end issue116;
architecture behav of issue116 is
signal intstat : BIT_VECTOR (7 DOWNTO 0);
ALIAS INT_int : BIT is intstat(7);
begin
INT_int <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
--intstat(7) <= '1' when (intstat(6 downto 0) and "1111111") /= ... |
-- test_ng.vhd
entity issue309 is
end issue309;
architecture MODEL of issue309 is
function check return boolean is
constant org_data : bit_vector(31 downto 0) := "01110110010101000011001000010000";
variable val_data : bit_vector(31 downto 0);
begin
val_data := (others => '0');
... |
-- test_ng.vhd
entity issue309 is
end issue309;
architecture MODEL of issue309 is
function check return boolean is
constant org_data : bit_vector(31 downto 0) := "01110110010101000011001000010000";
variable val_data : bit_vector(31 downto 0);
begin
val_data := (others => '0');
... |
-------------------------------------------------------------------------------
-- my_core_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library osif_tb_v1_00_c;
use osif_tb_v1_00_c.All... |
architecture RTL of RxDataStateMachine is
-- States of the TxDataStateMachine
type StatesRX is (stIdle, stReadStart, stReadData, stReadParity, stReadStop);
-- WriteParallel maybe not neccesaray
-- Signal for the States
signal CurrentState : StatesRX;
signal NextState : StatesRX;
-- Signal for the ... |
-------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : io.vhd
-- Author : Daniel Sun <dcsun88osh@gmail.com>
-- Company :
-- Created : 2016-05-21
-- La... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------- ---------------------------------------------------------------------
-- Title : Sub Bytes
-- Project : AES-GCM
-------------------------------------------------------------------------------
-- File : sub_bytes_ea.vhd
-- Author : Bill MacDowell <bill@bill-macdowell-laptop>
-- Company... |
-------------------------------------------------------------------------------
--
-- Parametrizable, generic RAM with enable.
--
-- $Id: generic_ram_ena.vhd,v 1.3 2008-04-27 22:13:15 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in sou... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
use Ieee.std_logic_unsigned.all;
entity TextAndRowToAddr is
Port (
Texture : in STD_LOGIC_VECTOR (3 downto 0);
Row : in STD_LOGIC_VECTOR (4 downto 0);
AddressOut : out STD_LOGIC_V... |
-------------------------------------------------------------------------------
-- system_fmc_imageon_iic_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_iic_v1_02_a;
use ax... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity assert1 is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end assert1;
architecture behav of assert1 is
signal val : unsigned (3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
... |
-------------------------------------------------------------------------------
-- bfm_monitor_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_monitor_bfm_v1_00_a;
use plbv... |
-------------------------------------------------------------------------------
-- bfm_monitor_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_monitor_bfm_v1_00_a;
use plbv... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
/home/andrey/Anna/Programming/fpga/core/pipistrello/minsoc1/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl//altera_virtual_jtag.vhd
|
architecture RTL of FIFO is
begin
process
begin
sig1 <= sig2; -- This comment is okay
end process;
-- Violations below
process
begin
sig1 <= sig2 and
sig3 or -- This comment is okay
sig4;
end process;
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;
entity morten2 is
end entity;
architecture foo of morten2 is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal cnt_1: unsigned (7 downto 0);
signal cnt_3: unsigned (7 downto 0... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;
entity morten2 is
end entity;
architecture foo of morten2 is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal cnt_1: unsigned (7 downto 0);
signal cnt_3: unsigned (7 downto 0... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;
entity morten2 is
end entity;
architecture foo of morten2 is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal cnt_1: unsigned (7 downto 0);
signal cnt_3: unsigned (7 downto 0... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:52:15 01/15/2015
-- Design Name:
-- Module Name: porteAND - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:52:15 01/15/2015
-- Design Name:
-- Module Name: porteAND - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_constants.all;
--! @brief Inst... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity sdrc_queens_slave is
generic (
-- Design Parameters
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 90;
COUNT_CYCLES : boolean := false;
-- Local Clock Parameters
CLK_FREQ : FREQ :=... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity s3a_clockgen is
port (
clk_50 : in std_logic;
reset_in : in std_logic;
dcm_lock : out std_logic;
sys_clo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity s3a_clockgen is
port (
clk_50 : in std_logic;
reset_in : in std_logic;
dcm_lock : out std_logic;
sys_clo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity s3a_clockgen is
port (
clk_50 : in std_logic;
reset_in : in std_logic;
dcm_lock : out std_logic;
sys_clo... |
entity test is
constant a : b :=
??foo + bar;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 02:34:31 2019
-- Host : varun-laptop running 64-bit Service ... |
-- --------------------------------------------------------------------
-- "fixed_pkg_c.vhdl" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ... |
entity tb_repro_uns is
end tb_repro_uns;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_repro_uns is
signal clk : std_logic;
signal a : unsigned(7 downto 0);
signal b : unsigned(7 downto 0);
begin
dut: entity work.repro_uns
port map (
clk => clk, a => a... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_780 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_780;
architecture augh of cmp_780 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_780 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_780;
architecture augh of cmp_780 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
-------------------------------------------------------------------------------
-- xor18.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xi... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2016 Cobham Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler R... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_10.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -----------------------------------------------... |
-- Rota posiciones (x,y,z) usando el algoritmo CORDIC iterativamente
library ieee;
use ieee.std_logic_1164.all;
entity pos_rotator is
generic(
Nxy : natural := 16;
Nangle : natural := 16;
Nits : natural := 16
);
port (
clock : in std_logic;
reset : in std_logic;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and ... |
library IEEE;
use IEEE.std_logic_1164.all;
entity bcd_multiplier is
port (a, b : in std_logic_vector (3 downto 0);
r : out std_logic_vector (7 downto 0));
end entity;
architecture structeral of bcd_multiplier is
component two_bit_multiplier is
port (a, b : in std_logic_vector (1 downto 0);
m : out... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-- memory mapping package for pdi
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- ... |
-------------------------------------------------------------------------------
-- memory mapping package for pdi
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- ... |
library ieee;
use ieee.std_logic_1164.all;
entity mem_bank_tb is
end entity;
architecture test_bench of mem_bank_tb is
component mem_bank is
port(clk : in std_logic;
reset : in std_logic;
wr_en : in std_logic;
rd_en : in std_logic;
rd_ack : out std_logic;
addr : in std_logic_vector(15 downto 0... |
-- NEED RESULT: ARCH00428: Based literals passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- T... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.test_utils.all;
entity test_test_utils is
end test_test_utils;
architecture behavioural of test_test_utils is
begin
process
variable test_chr : character;
variable test_str : string(1 to 8);
begin
test_chr := '0';
ass... |
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Softw... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 08 17:41:52 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- $Id: ibdr_lp11.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2009-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_lp11 - syn
-- Description: ibus dev(rem... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
library src;
use src.bus_pkg.all;
entity bus_singleport_ram_tb is
generic (
runner_cfg : string);
end entity;
architecture tb of bus_singleport_ram_tb is... |
------------------------------------------------------
------------------------------------------------------
-- Description: --
-- Implementation of a simple multiplier --
-- --
-- Generics: ... |
-------------------------------------------------------------------------------
-- Author: David Wolf, Leonhardt Schwarz
-- Project: FPGA Project
--
-- Copyright (C) 2014 David Wolf, Leonhardt Schwarz
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.... |
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, type, subtype, case, enumerations, ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEE... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_TDM_FSM is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
SSE_TS_CTRL0 : in vl_logic;
FPGA_TRIGGER : in vl_logic;
TDM_CNT : out vl_logic_vector(2 downto 0);
... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_TDM_FSM is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
SSE_TS_CTRL0 : in vl_logic;
FPGA_TRIGGER : in vl_logic;
TDM_CNT : out vl_logic_vector(2 downto 0);
... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_TDM_FSM is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
SSE_TS_CTRL0 : in vl_logic;
FPGA_TRIGGER : in vl_logic;
TDM_CNT : out vl_logic_vector(2 downto 0);
... |
-- Altera Microperipheral Reference Design Version 0802
--**********************************************************************************************
--
-- System: A8251
-- Component: Test Bench Stimulus
--
-- File: tb_A8251.vhd
-- Function: Sequences character transmission
--
--
--Copyright © 2002 ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.