content stringlengths 1 1.04M ⌀ |
|---|
-- Dynamic Partial Reconfiguration
constant CFG_PRC : integer := CONFIG_PARTIAL;
constant CFG_CRC_EN : integer := CONFIG_CRC;
constant CFG_WORDS_BLOCK : integer := CONFIG_BLOCK;
constant CFG_DCM_FIFO : integer := CONFIG_DCM_FIFO;
constant CFG_DPR_FIFO : integer := CFG_DPRFIFO;
|
------------------------------------------------------------------------
-- Random additional utility package
--
-- Copyright (c) 2014-2014 Rinat Zakirov
-- SPDX-License-Identifier: BSL-1.0
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package util is
function toSuv(n: integer; size: integer) return std_ulogic_vector;
function toSuv(n: integer; outsig: std_ulogic_vector) return std_ulogic_vector;
function unsToSuv(sig: unsigned) return std_ulogic_vector;
function unsToSlv(sig: unsigned) return std_logic_vector;
function toSlv(n: integer; size: integer) return std_logic_vector;
function toSlv(n: integer; outsig: std_logic_vector) return std_logic_vector;
function toUns(n: integer; size: integer) return unsigned;
function toUns(n: integer; outsig: unsigned) return unsigned;
function toSuv(slv: std_logic_vector) return std_ulogic_vector;
function toSlv(suv: std_ulogic_vector) return std_logic_vector;
function toInt(slv: std_logic_vector) return integer;
function toInt(slv: std_ulogic_vector) return integer;
end package;
package body util is
function toSuv(n: integer; size: integer) return std_ulogic_vector is
begin
return std_ulogic_vector(to_unsigned(n, size));
end function;
function unsToSuv(sig: unsigned) return std_ulogic_vector is
begin
return std_ulogic_vector(sig);
end function;
function unsToSlv(sig: unsigned) return std_logic_vector is
begin
return std_logic_vector(sig);
end function;
function toSlv(n: integer; size: integer) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(n, size));
end function;
function toUns(n: integer; size: integer) return unsigned is
begin
return to_unsigned(n, size);
end function;
function toSuv(n: integer; outsig: std_ulogic_vector) return std_ulogic_vector is
begin
return std_ulogic_vector(to_unsigned(n, outsig'length));
end function;
function toSlv(n: integer; outsig: std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(n, outsig'length));
end function;
function toUns(n: integer; outsig: unsigned) return unsigned is
begin
return to_unsigned(n, outsig'length);
end function;
function toSlv(suv: std_ulogic_vector) return std_logic_vector is
begin
return std_logic_vector(suv);
end function;
function toSuv(slv: std_logic_vector) return std_ulogic_vector is
begin
return std_ulogic_vector(slv);
end function;
function toInt(slv: std_logic_vector) return integer is
begin
return to_integer(unsigned(slv));
end function;
function toInt(slv: std_ulogic_vector) return integer is
begin
return to_integer(unsigned(slv));
end function;
end package body;
|
-------------------------------------------------------------------------------
-- Model: inductor
--
-- Author: Vladimir Kolchuzhin, LMGT, TU Chemnitz
-- <vladimir.kolchuzhin@ieee.org>
--
-- Date: 21.06.2011
-- Library: kvl in hAMSter
-------------------------------------------------------------------------------
-- ID: inductor.vhd
-- Rev. 1.0
-------------------------------------------------------------------------------
use work.electromagnetic_system.all;
use work.all;
library ieee;
entity inductor is
generic (inductance:real); -- inductance value
port (terminal p,n:electrical); -- interface ports
end entity inductor;
architecture basic of inductor is
quantity v across i through p to n;
begin
v == inductance*i'dot;
end architecture basic;
|
-- $Id: sys_conf2.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.0 Initial version
-- 2011-10-25 419 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkudiv_usecdiv : integer := 100; -- default usec
constant sys_conf_clksdiv_usecdiv : integer := 60; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_uart_cdinit : integer := 521-1; -- 60000000/115200
end package sys_conf;
|
-- $Id: sys_conf2.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.0 Initial version
-- 2011-10-25 419 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkudiv_usecdiv : integer := 100; -- default usec
constant sys_conf_clksdiv_usecdiv : integer := 60; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_uart_cdinit : integer := 521-1; -- 60000000/115200
end package sys_conf;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RegistersMulticycle is
port(
RR1, RR2, WR: in std_logic_vector(4 downto 0);
WD: in std_logic_vector(31 downto 0);
RegWrite: in std_logic;
RD1, RD2: out std_logic_vector(31 downto 0)
);
end RegistersMulticycle;
Architecture Structural of RegistersMulticycle is
type mem_array is array(0 to 31) of std_logic_vector(31 downto 0);
signal reg_mem: mem_array := (
X"00000000", --0 $zero (constant value 0)
X"00000000", -- $at (reserved for the assembler)
X"00000000", -- $v0 (value for results and expression)
X"00000000", -- $v1
X"00000000", -- $a0 (arguments)
X"00000000", --5 $a1
X"00000000", -- $a2
X"00000000", -- $a3
X"00000000", -- $t0 (temporaries)
X"00000000", -- $t1
X"00000000", --10 $t2
X"00000000", -- $t3
X"00000000", -- $t4
X"00000000", -- $t5
X"00000000", -- $t6
X"00000000", --15 $t7
X"00000000", -- $s0 (saved)
X"00000000", -- $s1
X"00000000", -- $s2
X"00000000", -- $s3
X"0000000E", --20 $s4
X"00000005", -- $s5
X"00000000", -- $s6
X"00000000", -- $s7
X"00000000", -- $t8 (more temporaries)
X"00000000", --25 $t9
X"00000000", -- $k0 (reserved for the operating system)
X"00000000", -- $k1
X"00000000", -- $gp (global pointer)
X"00000000", -- $sp (stack pointer)
X"00000000", --30 $fp (frame pointer)
X"00000000" -- $ra (return address)
);
signal temp_data: std_logic_vector(31 downto 0) := X"00000000";
begin
RD1 <= reg_mem(to_integer(unsigned(RR1)));
RD2 <= reg_mem(to_integer(unsigned(RR2)));
process(WD, WR, RegWrite)
begin
if RegWrite = '1' then
reg_mem(to_integer(unsigned(WR))) <= WD;
end if;
end process;
end Structural;
|
LIBRARY ieee;
LIBRARY std;
use ieee.std_logic_textio.all;
use std.textio.all;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity clock_divider_test is
end clock_divider_test;
architecture behavior of clock_divider_test is
-- Component Declaration for the Unit Under Test (UUT)
component divider
GENERIC (
N: integer := 10
);
PORT(
clk : IN std_logic;
tc : OUT std_logic
);
end component;
signal tb_clk, tb_tc: STD_LOGIC;
signal clk_te : STD_LOGIC;
-- Clock period definitions
constant clk_period : time := 20 ns;
constant clk_te_period : time := 20 ns;
constant dT : real := 2.0; --ns
constant separator: String(1 to 1) := ";"; -- CSV separator
begin
-- Instantiate the Unit Under Test (UUT)
uut: divider PORT MAP (
clk => tb_clk,
tc => tb_tc
);
-- Clock process definitions
clk_process: process
begin
tb_clk <= '0';
wait for clk_period/2;
tb_clk <= '1';
wait for clk_period/2;
end process clk_process;
-- Clock process definitions
clk_te_process: process
begin
clk_te <= '0';
wait for clk_te_period/2;
clk_te <= '1';
wait for clk_te_period/2;
end process clk_te_process;
-- Stimulus process
stim_proc: process
begin
--wait for 100ms;
--tb_reset <= '1';
--wait for clk_period*10;
--tb_reset <= '0';
-- insert stimulus here
wait;
end process stim_proc;
result: process(clk_te)
file filedatas: text open WRITE_MODE is "clock_divider.csv";
variable s : line;
variable temps : real := 0.0;
begin
--if rising_edge(clk_te) then
write(s, temps); write(s, separator);
write(s, tb_clk); write(s, separator);
write(s, tb_tc); write(s, separator);
writeline(filedatas,s);
temps := temps + dT;
--end if;
end process result;
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_alu-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture behavior of alu is
begin
alu_op: process ( s1, s2, func ) is
variable bv_s1, bv_s2 : dlx_bv_word;
variable temp_result : dlx_bv_word;
variable temp_overflow : boolean;
type boolean_to_X01_table is array (boolean) of X01;
constant boolean_to_X01 : boolean_to_X01_table := ( '0', '1' );
begin
bv_s1 := To_bitvector(s1);
bv_s2 := To_bitvector(s2);
temp_overflow := false;
case func is
when alu_pass_s1 =>
temp_result := bv_s1;
when alu_pass_s2 =>
temp_result := bv_s2;
when alu_and =>
temp_result := bv_s1 and bv_s2;
when alu_or =>
temp_result := bv_s1 or bv_s2;
when alu_xor =>
temp_result := bv_s1 xor bv_s2;
when alu_sll =>
temp_result := bv_s1 sll bv_to_natural(bv_s2(27 to 31));
when alu_srl =>
temp_result := bv_s1 srl bv_to_natural(bv_s2(27 to 31));
when alu_sra =>
temp_result := bv_s1 sra bv_to_natural(bv_s2(27 to 31));
when alu_add =>
bv_add(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_addu =>
bv_addu(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_sub =>
bv_sub(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_subu =>
bv_subu(bv_s1, bv_s2, temp_result, temp_overflow);
when others =>
report "illegal function code" severity error;
temp_result := X"0000_0000";
end case;
result <= To_X01(temp_result) after Tpd;
zero <= boolean_to_X01(temp_result = X"0000_0000") after Tpd;
negative <= To_X01(temp_result(0)) after Tpd;
overflow <= boolean_to_X01(temp_overflow) after Tpd;
end process alu_op;
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_alu-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture behavior of alu is
begin
alu_op: process ( s1, s2, func ) is
variable bv_s1, bv_s2 : dlx_bv_word;
variable temp_result : dlx_bv_word;
variable temp_overflow : boolean;
type boolean_to_X01_table is array (boolean) of X01;
constant boolean_to_X01 : boolean_to_X01_table := ( '0', '1' );
begin
bv_s1 := To_bitvector(s1);
bv_s2 := To_bitvector(s2);
temp_overflow := false;
case func is
when alu_pass_s1 =>
temp_result := bv_s1;
when alu_pass_s2 =>
temp_result := bv_s2;
when alu_and =>
temp_result := bv_s1 and bv_s2;
when alu_or =>
temp_result := bv_s1 or bv_s2;
when alu_xor =>
temp_result := bv_s1 xor bv_s2;
when alu_sll =>
temp_result := bv_s1 sll bv_to_natural(bv_s2(27 to 31));
when alu_srl =>
temp_result := bv_s1 srl bv_to_natural(bv_s2(27 to 31));
when alu_sra =>
temp_result := bv_s1 sra bv_to_natural(bv_s2(27 to 31));
when alu_add =>
bv_add(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_addu =>
bv_addu(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_sub =>
bv_sub(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_subu =>
bv_subu(bv_s1, bv_s2, temp_result, temp_overflow);
when others =>
report "illegal function code" severity error;
temp_result := X"0000_0000";
end case;
result <= To_X01(temp_result) after Tpd;
zero <= boolean_to_X01(temp_result = X"0000_0000") after Tpd;
negative <= To_X01(temp_result(0)) after Tpd;
overflow <= boolean_to_X01(temp_overflow) after Tpd;
end process alu_op;
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_alu-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture behavior of alu is
begin
alu_op: process ( s1, s2, func ) is
variable bv_s1, bv_s2 : dlx_bv_word;
variable temp_result : dlx_bv_word;
variable temp_overflow : boolean;
type boolean_to_X01_table is array (boolean) of X01;
constant boolean_to_X01 : boolean_to_X01_table := ( '0', '1' );
begin
bv_s1 := To_bitvector(s1);
bv_s2 := To_bitvector(s2);
temp_overflow := false;
case func is
when alu_pass_s1 =>
temp_result := bv_s1;
when alu_pass_s2 =>
temp_result := bv_s2;
when alu_and =>
temp_result := bv_s1 and bv_s2;
when alu_or =>
temp_result := bv_s1 or bv_s2;
when alu_xor =>
temp_result := bv_s1 xor bv_s2;
when alu_sll =>
temp_result := bv_s1 sll bv_to_natural(bv_s2(27 to 31));
when alu_srl =>
temp_result := bv_s1 srl bv_to_natural(bv_s2(27 to 31));
when alu_sra =>
temp_result := bv_s1 sra bv_to_natural(bv_s2(27 to 31));
when alu_add =>
bv_add(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_addu =>
bv_addu(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_sub =>
bv_sub(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_subu =>
bv_subu(bv_s1, bv_s2, temp_result, temp_overflow);
when others =>
report "illegal function code" severity error;
temp_result := X"0000_0000";
end case;
result <= To_X01(temp_result) after Tpd;
zero <= boolean_to_X01(temp_result = X"0000_0000") after Tpd;
negative <= To_X01(temp_result(0)) after Tpd;
overflow <= boolean_to_X01(temp_overflow) after Tpd;
end process alu_op;
end architecture behavior;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:28:10 11/21/2013
-- Design Name:
-- Module Name: MEM_WB - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MEM_WB is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
WriteIn : in STD_LOGIC;
MemtoRegInput : in STD_LOGIC;
MemtoRegOutput : out STD_LOGIC;
RegWriteInput: in STD_LOGIC;
RegWriteOutput: out STD_LOGIC;
AluResultInput : in STD_LOGIC_VECTOR (15 downto 0);
AluResultOutput : out STD_LOGIC_VECTOR (15 downto 0);
MemResultInput: in STD_LOGIC_VECTOR (15 downto 0);
MemResultOutput: out STD_LOGIC_VECTOR (15 downto 0);
RegReadInput1 : in STD_LOGIC_VECTOR (3 downto 0);
RegReadInput2 : in STD_LOGIC_VECTOR (3 downto 0);
RegWriteToInput : in STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput1 : out STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput2 : out STD_LOGIC_VECTOR (3 downto 0);
RegWriteToOutput : out STD_LOGIC_VECTOR (3 downto 0);
retinput: in std_logic;
retoutput: out std_logic
);
end MEM_WB;
architecture Behavioral of MEM_WB is
begin
process (rst, clk, WriteIn)
begin
if (rst = '0') then
MemtoRegOutput <= '0';
RegWriteOutput <= '0';
retoutput <= '0';
elsif (clk'event and clk = '1') then
if (WriteIn = '1') then
MemtoRegOutput <= MemtoRegInput;
RegWriteOutput <= RegWriteInput;
AluResultOutput <= AluResultInput;
MemResultOutput <= MemResultInput;
RegReadOutput1 <= RegReadInput1;
RegReadOutput2 <= RegReadInput2;
RegWriteToOutput <= RegWriteToInput;
retoutput <= retinput;
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.math_real.all;
entity ent is
end ent;
architecture a of ent is
constant DELAY_NSEC : real := -1.0;
constant DELAY_TAPS_INT : integer :=
integer(round(DELAY_NSEC / 0.078125));
begin
end a;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux4x1_8:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux4x1_8_0_1 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_Mux4x1_8_0_1;
ARCHITECTURE RAT_Mux4x1_8_0_1_arch OF RAT_Mux4x1_8_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux4x1_8_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1_8 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT Mux4x1_8;
BEGIN
U0 : Mux4x1_8
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END RAT_Mux4x1_8_0_1_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 22:44:06 11/18/2009
-- Design Name:
-- Module Name: Offset - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: A generic module that applies an offset (through addition only)
-- to its input
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Offset is
generic ( size: integer;
offset: integer);
Port ( data_in : in STD_LOGIC_VECTOR((size-1) downto 0);
data_out : out STD_LOGIC_VECTOR((size-1) downto 0));
end Offset;
architecture Behavioral of Offset is
begin
main: process (data_in) is
begin
data_out <= (data_in + conv_std_logic_vector(offset, size));
end process;
end Behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
entity tb_control_system is
end tb_control_system;
architecture TB_control_system of tb_control_system is
-- Component declarations
-- Signal declarations
quantity in_src, fb : real;
quantity output : real;
begin
-- Signal assignments
-- Component instances
src3 : entity work.src_sine(ideal)
generic map(
freq => 100.0,
amplitude => 1.0
)
port map(
output => in_src
);
XCMP12 : entity work.control_system(simple_feedback)
port map(
target => in_src,
output => output,
feedback => fb
);
gain1 : entity work.gain(simple)
generic map(
k => 1.0
)
port map (
input => output,
output => fb
);
end TB_control_system;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
entity tb_control_system is
end tb_control_system;
architecture TB_control_system of tb_control_system is
-- Component declarations
-- Signal declarations
quantity in_src, fb : real;
quantity output : real;
begin
-- Signal assignments
-- Component instances
src3 : entity work.src_sine(ideal)
generic map(
freq => 100.0,
amplitude => 1.0
)
port map(
output => in_src
);
XCMP12 : entity work.control_system(simple_feedback)
port map(
target => in_src,
output => output,
feedback => fb
);
gain1 : entity work.gain(simple)
generic map(
k => 1.0
)
port map (
input => output,
output => fb
);
end TB_control_system;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
entity tb_control_system is
end tb_control_system;
architecture TB_control_system of tb_control_system is
-- Component declarations
-- Signal declarations
quantity in_src, fb : real;
quantity output : real;
begin
-- Signal assignments
-- Component instances
src3 : entity work.src_sine(ideal)
generic map(
freq => 100.0,
amplitude => 1.0
)
port map(
output => in_src
);
XCMP12 : entity work.control_system(simple_feedback)
port map(
target => in_src,
output => output,
feedback => fb
);
gain1 : entity work.gain(simple)
generic map(
k => 1.0
)
port map (
input => output,
output => fb
);
end TB_control_system;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc223.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p07n01i00223ent IS
END c03s01b01x00p07n01i00223ent;
ARCHITECTURE c03s01b01x00p07n01i00223arch OF c03s01b01x00p07n01i00223ent IS
type ENUM1 is (FF, GG);
type ENUM2 is (GG, HH);
type ENUM3 is (FALSE);
type ENUM4 is ('A', 'Z');
BEGIN
TESTING: PROCESS
BEGIN
if (FALSE = FALSE) then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c03s01b01x00p07n01i00223"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c03s01b01x00p07n01i00223 - Literal cannot be determined."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p07n01i00223arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc223.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p07n01i00223ent IS
END c03s01b01x00p07n01i00223ent;
ARCHITECTURE c03s01b01x00p07n01i00223arch OF c03s01b01x00p07n01i00223ent IS
type ENUM1 is (FF, GG);
type ENUM2 is (GG, HH);
type ENUM3 is (FALSE);
type ENUM4 is ('A', 'Z');
BEGIN
TESTING: PROCESS
BEGIN
if (FALSE = FALSE) then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c03s01b01x00p07n01i00223"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c03s01b01x00p07n01i00223 - Literal cannot be determined."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p07n01i00223arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc223.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p07n01i00223ent IS
END c03s01b01x00p07n01i00223ent;
ARCHITECTURE c03s01b01x00p07n01i00223arch OF c03s01b01x00p07n01i00223ent IS
type ENUM1 is (FF, GG);
type ENUM2 is (GG, HH);
type ENUM3 is (FALSE);
type ENUM4 is ('A', 'Z');
BEGIN
TESTING: PROCESS
BEGIN
if (FALSE = FALSE) then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c03s01b01x00p07n01i00223"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c03s01b01x00p07n01i00223 - Literal cannot be determined."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p07n01i00223arch;
|
library ieee;
use ieee.std_logic_1164.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.com_context;
entity test_tb is
generic (runner_cfg : runner_cfg_t);
end entity;
architecture beh of test_tb is
signal rx_data : std_logic_vector(159 downto 0);
function to_b(constant s : string) return std_logic is
begin
return '0';
end function;
function to_a(constant s : string) return std_logic is
variable a : std_logic := to_b(s);
begin
return '0';
end function;
procedure to_t( signal sa : out std_logic_vector(31 downto 0)) is
begin
sa <= (others => '1');
assert false report "lol";
end procedure;
begin
asd : for i in 0 to 4 generate
begin
process
constant s : string := "lane" & integer'image(i);
variable self : actor_t := create(s);
begin
--assert false report "Error: " & s;
rx_data(32*(i+1)-1 downto 32*i) <= (others => '0');
wait for 10 ns;
to_t(rx_data(32*(i+1)-1 downto 32*i));
wait;
end process;
end generate;
process
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("test1") then
null;
end if;
end loop;
test_runner_cleanup(runner); -- Simulation ends here
end process;
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.com_context;
entity test_tb is
generic (runner_cfg : runner_cfg_t);
end entity;
architecture beh of test_tb is
signal rx_data : std_logic_vector(159 downto 0);
function to_b(constant s : string) return std_logic is
begin
return '0';
end function;
function to_a(constant s : string) return std_logic is
variable a : std_logic := to_b(s);
begin
return '0';
end function;
procedure to_t( signal sa : out std_logic_vector(31 downto 0)) is
begin
sa <= (others => '1');
assert false report "lol";
end procedure;
begin
asd : for i in 0 to 4 generate
begin
process
constant s : string := "lane" & integer'image(i);
variable self : actor_t := create(s);
begin
--assert false report "Error: " & s;
rx_data(32*(i+1)-1 downto 32*i) <= (others => '0');
wait for 10 ns;
to_t(rx_data(32*(i+1)-1 downto 32*i));
wait;
end process;
end generate;
process
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("test1") then
null;
end if;
end loop;
test_runner_cleanup(runner); -- Simulation ends here
end process;
end architecture; |
-------------------------------------------------------------------------------
-- axi_sg_intrpt
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/14/10 v1_00_a
-- ^^^^^^
-- CR565366
-- Fixed issue where simultaneous sof and eof caused delay timer to not enable
-- thus missing a delay interrupt. This issue occurs with small packets(i.e.
-- 2 data beats)
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not. Renamed interrupt threshold decrement control here
-- to match change in upper level.
-- ~~~~~~
-- GAB 8/3/10 v1_00_a
-- ^^^^^^
-- CR570398
-- Routed dlyirq_wren to reset delay timer logic on assertion
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg_intrpt
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/14/10 v1_00_a
-- ^^^^^^
-- CR565366
-- Fixed issue where simultaneous sof and eof caused delay timer to not enable
-- thus missing a delay interrupt. This issue occurs with small packets(i.e.
-- 2 data beats)
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not. Renamed interrupt threshold decrement control here
-- to match change in upper level.
-- ~~~~~~
-- GAB 8/3/10 v1_00_a
-- ^^^^^^
-- CR570398
-- Routed dlyirq_wren to reset delay timer logic on assertion
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg_intrpt
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/14/10 v1_00_a
-- ^^^^^^
-- CR565366
-- Fixed issue where simultaneous sof and eof caused delay timer to not enable
-- thus missing a delay interrupt. This issue occurs with small packets(i.e.
-- 2 data beats)
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not. Renamed interrupt threshold decrement control here
-- to match change in upper level.
-- ~~~~~~
-- GAB 8/3/10 v1_00_a
-- ^^^^^^
-- CR570398
-- Routed dlyirq_wren to reset delay timer logic on assertion
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg_intrpt
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/14/10 v1_00_a
-- ^^^^^^
-- CR565366
-- Fixed issue where simultaneous sof and eof caused delay timer to not enable
-- thus missing a delay interrupt. This issue occurs with small packets(i.e.
-- 2 data beats)
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not. Renamed interrupt threshold decrement control here
-- to match change in upper level.
-- ~~~~~~
-- GAB 8/3/10 v1_00_a
-- ^^^^^^
-- CR570398
-- Routed dlyirq_wren to reset delay timer logic on assertion
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
|
-- NEED RESULT: ARCH00484: Function parameters of standard types or locally static size passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00484
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.1.1 (6)
-- 2.1.1 (7)
-- 2.1.1 (9)
-- 2.1.1 (12)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00484)
-- ENT00484_Test_Bench(ARCH00484_Test_Bench)
--
-- REVISION HISTORY:
--
-- 7-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00484 of E00000 is
begin
P :
process
-- this will test 2.1.1 (6) and 2.1.1 (12)
function f_1 ( bi : bit ;
bv : bit_vector ; -- this tests 2.1.1 (12)
bo : boolean ;
c : character ;
i : integer ;
r : real ;
s : string ;
t : time) return integer is
variable n : integer := 0 ;
begin
if bi = '1' then
n := n + 1 ;
end if ;
if bv(2) = '0' then
n := n + 1 ;
end if ;
if bo = true then
n := n + 1 ;
end if ;
if c = '!' then
n := n + 1 ;
end if ;
if i = 100 then
n := n + 1 ;
end if ;
if r = 100.0 then
n := n + 1 ;
end if ;
if s(2) = 'a' then
n := n + 1 ;
end if ;
if t = 100 ns then
n := n + 1 ;
end if ;
return n ;
end f_1 ;
-- this will test 2.1.1 (7)
-- (the various types are in STANDARD_TYPES)
function f_2 ( t_en : t_enum1 ;
st_en : st_enum1 ;
t_in : t_int1 ;
st_in : st_int1 ;
t_ph : t_phys1 ;
st_ph : st_phys1 ;
t_re : t_real1 ;
st_re : st_real1 ) return integer is
variable n : integer := 0 ;
begin
if t_en = en2 then
n := n + 1 ;
end if ;
if st_en = en3 then
n := n + 1 ;
end if ;
if t_in = 10 then
n := n + 1 ;
end if ;
if st_in = 12 then
n := n + 1 ;
end if ;
if t_ph = phys1_3 then
n := n + 1 ;
end if ;
if st_ph = phys1_4 then
n := n + 1 ;
end if ;
if t_re = 10.0 then
n := n + 1 ;
end if ;
if st_re = 12.0 then
n := n + 1 ;
end if ;
return n ;
end f_2 ;
-- this will test 2.1.1 (9)
-- (the various types are in STANDARD_TYPES)
function f_3 ( t_ar : t_arr1 ; -- this tests 2.1.1 (12) again
st_ar : st_arr1 ;
t_r1 : t_rec1 ;
t_r3 : t_rec3 ) return integer is
variable n : integer := 0 ;
begin
if t_ar(2) = c_st_int1_1 then
n := n + 1 ;
end if ;
if st_ar(2) = c_st_int1_2 then
n := n + 1 ;
end if ;
if t_r1.f2 = c_time_1 then
n := n + 1 ;
end if ;
if t_r3.f1 = c_boolean_1 then
n := n + 1 ;
end if ;
return n ;
end f_3 ;
variable b_vect : bit_vector (0 to 2) ;
begin
b_vect(0) := '0' ;
b_vect(1) := '1' ;
b_vect(2) := '0' ;
test_report ( "ARCH00484" ,
"Function parameters of standard types or locally static size" ,
(f_1('1', b_vect, true, '!', 100, 100.0, "cat", 100 ns) = 8) and
(f_2(en2, en3, 10, 12, phys1_3, phys1_4, 10.0, 12.0) = 8) and
(f_3(c_st_arr1_1, c_st_arr1_2, c_t_rec1_1, c_t_rec3_1) = 4)
) ;
wait ;
end process P ;
end ARCH00484 ;
entity ENT00484_Test_Bench is
end ENT00484_Test_Bench ;
architecture ARCH00484_Test_Bench of ENT00484_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00484 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00484_Test_Bench ;
|
----- Libraries -----
library ieee;
use ieee.std_logic_1164.all;
package my_gates is
function function_xor( signal a,b : in std_logic) return std_logic; --declaration
procedure procedure_and_or( signal a,b : in std_logic;
signal and_out, or_out : out std_logic);
end my_gates;
package body my_gates is
function function_xor(signal a,b : in std_logic) return std_logic is
-- Declarative items (constants, variables, etc.)
begin
-- Function body.
return a xor b;
end function;
procedure procedure_and_or(a,b : in std_logic;
signal and_out, or_out : out std_logic
) is
-- Declarative items (constants, variables, etc.)
begin
-- Procedure body.
and_out <= a and b;
or_out <= a or b;
end procedure;
end my_gates; |
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8592)
`protect data_block
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|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_oreg
-- File: ddr_oreg.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DDR output reg with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddr_oreg is generic (tech : integer; arch : integer := 0; scantest: integer := 0);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic;
testen: in std_ulogic;
testrst: in std_ulogic);
end;
architecture rtl of ddr_oreg is
begin
inf : if not ((tech = lattice) or (is_unisim(tech) = 1) or
(tech = axcel) or (tech = axdsp) or (tech = apa3) or
(tech = apa3e) or (tech = apa3l) or (tech = igloo2) or
(tech = rtg4)) generate
inf0 : gen_oddr_reg generic map (scantest,0) port map (Q, C1, C2, CE, D1, D2, R, S, testen, testrst);
end generate;
ax : if (tech = axcel) or (tech = axdsp) generate
ax0 : axcel_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
pa3 : if (tech = apa3) generate
pa0 : apa3_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
pa3e : if (tech = apa3e) generate
pa0 : apa3e_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
pa3l : if (tech = apa3l) generate
pa0 : apa3l_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
lat : if tech = lattice generate
lat0 : ec_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
igl20 : igloo2_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
xil : if is_unisim(tech) = 1 generate
xil0 : unisim_oddr_reg generic map (tech, arch)
port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
--pragma translate_off
assert (tech /= easic45) and (tech /= easic90)
report "ddr_oreg: Not supported on eASIC. Use DDR pad instead."
severity failure;
--pragma translate_on
end;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "cordic_core"
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_core_tb.vhd
-- Author : Vitor Finotti Ferreira <vfinotti@finotti-Inspiron-7520>
-- Company : Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- Created : 2015-11-19
-- Last update: 2015-11-24
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2015 Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-11-19 1.0 vfinotti Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.test_pkg.all;
-------------------------------------------------------------------------------
entity cordic_core_tb is
end entity cordic_core_tb;
-------------------------------------------------------------------------------
architecture test of cordic_core_tb is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
constant c_CLK_FREQ : real := 100.0e6;
constant c_CYCLES_TO_CE : natural := 4;
constant c_INPUT_FILE : string := "vectoring_in.samples";
constant c_INPUT_WIDTH : natural := 32;
constant c_OUTPUT_FILE : string := "vectoring_out.samples";
constant c_OUTPUT_WIDTH : natural := 32;
signal end_of_file : std_logic := '0';
constant cordic_delay : natural := 27;
-- component generics
constant g_stages : natural := 15;
constant g_bit_growth : natural := natural(ceil(log2(real(g_stages))));
constant g_mode : string := "rect_to_polar";
-- component ports
signal s_x_i : signed(c_INPUT_WIDTH-1 downto 0);
signal s_y_i : signed(c_INPUT_WIDTH-1 downto 0);
signal s_z_i : signed(c_INPUT_WIDTH-1 downto 0) := (c_INPUT_WIDTH-1 downto 0 => '0');
signal s_clk : std_logic;
signal s_ce : std_logic;
signal s_rst : std_logic;
signal s_valid_i : std_logic;
signal s_x_o : signed(c_INPUT_WIDTH-1 downto 0);
signal s_y_o : signed(c_INPUT_WIDTH-1 downto 0);
signal s_z_o : signed(c_INPUT_WIDTH-1 downto 0);
signal s_valid_o : std_logic;
signal s_req_data :std_logic := '1';
signal s_x_i_real :real;
signal s_y_i_real :real;
signal s_x_o_real :real;
signal s_y_o_real :real;
component cordic_core is
generic (
g_stages : natural;
g_bit_growth : natural;
g_mode : string);
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
valid_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed;
valid_o : out std_logic);
end component cordic_core;
begin -- architecture test
p_clk_gen (
clk => s_clk,
c_FREQ => c_CLK_FREQ);
p_rst_gen (
clk => s_clk,
rst => s_rst,
c_CYCLES => 2);
p_ce_gen (
clk => s_clk,
ce => s_ce,
rst => s_rst,
c_CYCLES => c_CYCLES_TO_CE);
p_read_tsv_file_signed (
c_INPUT_FILE_NAME => c_INPUT_FILE,
c_SAMPLES_PER_LINE => 2,
c_OUTPUT_WIDTH => c_INPUT_WIDTH, --input for the testbench, output for
--the procedure
clk => s_clk,
rst => s_rst,
ce => s_ce,
req => s_req_data,
sample(0) => s_x_i,
sample(1) => s_y_i,
valid => s_valid_i,
end_of_file => end_of_file);
-- component instantiation
DUT : cordic_core
generic map (
g_stages => g_stages,
g_bit_growth => g_bit_growth,
g_mode => g_mode)
port map (
x_i => s_x_i,
y_i => s_y_i,
z_i => s_z_i,
clk_i => s_clk,
ce_i => s_ce,
rst_i => s_rst,
valid_i => s_valid_i,
x_o => s_x_o,
y_o => s_y_o,
z_o => s_z_o,
valid_o => s_valid_o);
p_write_tsv_file_signed (
c_OUTPUT_FILE_NAME => c_OUTPUT_FILE,
c_SAMPLES_PER_LINE => 2,
c_OUTPUT_WIDTH => c_OUTPUT_WIDTH,
clk => s_clk,
rst => s_rst,
ce => s_ce,
sample(0) => s_x_o,
sample(1) => s_z_o,
valid => s_valid_o,
end_of_file => end_of_file);
end architecture test;
-------------------------------------------------------------------------------
configuration cordic_core_tb_test_cfg of cordic_core_tb is
for test
end for;
end cordic_core_tb_test_cfg;
-------------------------------------------------------------------------------
|
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920)
`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920)
`protect data_block
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|
`protect begin_protected
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|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
ENTITY tb_memory IS
END tb_memory;
ARCHITECTURE behavior OF tb_memory IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT memory_no_clk
PORT(
clk : IN std_logic;
write_en : IN std_logic;
addr_1 : IN std_logic_vector(31 downto 0);
addr_2 : IN std_logic_vector(31 downto 0);
data_w2 : IN std_logic_vector(31 downto 0);
data_r1 : OUT std_logic_vector(31 downto 0);
data_r2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal write_en : std_logic := '0';
signal addr_1 : std_logic_vector(31 downto 0) := (others => '0');
signal addr_2 : std_logic_vector(31 downto 0) := (others => '0');
signal data_w2 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal data_r1 : std_logic_vector(31 downto 0);
signal data_r2 : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: memory_no_clk PORT MAP (
clk => clk,
write_en => write_en,
addr_1 => addr_1,
addr_2 => addr_2,
data_w2 => data_w2,
data_r1 => data_r1,
data_r2 => data_r2
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
addr1_process :process
begin
if unsigned(addr_1) = 7 then
addr_1 <= (others=>'0');
else
addr_1 <= std_logic_vector(unsigned(addr_1) + 1);
end if;
wait for 2*clk_period;
end process;
addr2_process :process
begin
if unsigned(addr_2) = 7 then
addr_2 <= (others=>'0');
else
addr_2 <= std_logic_vector(unsigned(addr_2) + 1);
end if;
wait for 3*clk_period;
end process;
write_en_process :process
begin
write_en <= '1';
wait for 2*clk_period;
write_en <= '0';
wait for 8*clk_period;
end process;
data_process :process
begin
data_w2 <= std_logic_vector(unsigned(data_w2) + 1);
wait for clk_period;
end process;
END;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Arithmetic_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Artithmetic Unit
-- Operations - Add, Sub, Addi
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arith_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Arith_Unit;
architecture Combinational of Arith_Unit is
signal a1, b1 : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
signal arith : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
begin
-- Give extra bit to accound for carry,overflow,negative
a1 <= '0' & A;
b1 <= '0' & B;
with OP select
arith <=
a1 + b1 when "000", -- ADD
a1 - b1 when "001", -- SUB
a1 + b1 when "101", -- ADDI
a1 + b1 when OTHERS;
CCR(3) <= arith(7); -- Negative
CCR(2) <= '1' when arith(7 downto 0) = x"0000" else '0'; -- Zero
CCR(1) <= arith(8) xor arith(7); -- Overflow
CCR(0) <= arith(8); --Carry
RESULT <= arith(7 downto 0);
end Combinational;
|
-- file: tri_mode_ethernet_mac_0_clk_wiz.vhd
--
-- -----------------------------------------------------------------------------
-- (c) Copyright 2008-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1 125.000 0.000 50.0 91.364 85.928
-- CLK_OUT2 100.000 0.000 50.0 70.716 85.928
-- CLK_OUT2 200.000 0.000 50.0
--
------------------------------------------------------------------------------
-- Input Clock Input Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- primary 200.000 0.010
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity tri_mode_ethernet_mac_0_clk_wiz is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end tri_mode_ethernet_mac_0_clk_wiz;
architecture xilinx of tri_mode_ethernet_mac_0_clk_wiz is
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2 : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 5.000,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 5,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 5.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => CLK_IN1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkout1_buf : BUFGCE
port map
(O => CLK_OUT1,
CE => '1',
I => clkout0);
clkout2_buf : BUFGCE
port map
(O => CLK_OUT2,
CE => '1',
I => clkout1);
clkout3_buf : BUFGCE
port map
(O => CLK_OUT3,
CE => '1',
I => clkout2);
end xilinx;
|
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: phy_dq_iob.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:12 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Instantiates I/O-related logic for DQ. Contains logic for both write
-- and read paths.
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--$Id: phy_dq_iob.vhd,v 1.1 2011/06/02 07:18:12 mishra Exp $
--**$Date: 2011/06/02 07:18:12 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_dq_iob.vhd,v $
--******************************************************************************
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_dq_iob is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
nCWL : integer := 5; -- Write CAS latency (in clk cyc)
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
WRLVL : string := "ON"; -- "OFF" for "DDR3" component interface
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
IBUF_LPWR_MODE : string := "OFF"; -- Input buffer low power mode
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG" -- May be assigned unique name
-- when mult IP cores in design
);
port (
clk_mem : in std_logic;
clk : in std_logic;
rst : in std_logic;
clk_cpt : in std_logic;
clk_rsync : in std_logic;
rst_rsync : in std_logic;
-- IODELAY I/F
dlyval : in std_logic_vector(4 downto 0);
-- Write datapath I/F
inv_dqs : in std_logic;
wr_calib_dly : in std_logic_vector(1 downto 0);
dq_oe_n : in std_logic_vector(3 downto 0);
wr_data_rise0 : in std_logic;
wr_data_fall0 : in std_logic;
wr_data_rise1 : in std_logic;
wr_data_fall1 : in std_logic;
-- Read datapath I/F
rd_bitslip_cnt : in std_logic_vector(1 downto 0);
rd_clkdly_cnt : in std_logic_vector(1 downto 0);
rd_clkdiv_inv : in std_logic;
rd_data_rise0 : out std_logic;
rd_data_fall0 : out std_logic;
rd_data_rise1 : out std_logic;
rd_data_fall1 : out std_logic;
-- DDR3 bus signals
ddr_dq : inout std_logic;
dq_tap_cnt : out std_logic_vector(4 downto 0)
);
end phy_dq_iob;
architecture trans_phy_dq_iob of phy_dq_iob is
-- Set performance mode for IODELAY (power vs. performance tradeoff)
function CALC_HIGH_PERF_MODE return boolean is
begin
if (IODELAY_HP_MODE = "OFF") then
return FALSE;
elsif (IODELAY_HP_MODE = "ON") then
return TRUE;
else
return FALSE;
end if;
end function CALC_HIGH_PERF_MODE;
-- Enable low power mode for input buffer
function CALC_IBUF_LOW_PWR return boolean is
begin
if (IBUF_LPWR_MODE = "OFF") then
return FALSE;
elsif (IBUF_LPWR_MODE = "ON") then
return TRUE;
else
return FALSE;
end if;
end function CALC_IBUF_LOW_PWR;
constant HIGH_PERFORMANCE_MODE : boolean := CALC_HIGH_PERF_MODE;
constant IBUF_LOW_PWR : boolean := CALC_IBUF_LOW_PWR;
signal dq_in : std_logic;
signal dq_iodelay : std_logic;
signal dq_oe_n_r : std_logic;
signal dq_oq : std_logic;
signal iodelay_dout : std_logic;
signal iserdes_clk : std_logic;
signal iserdes_clkb : std_logic;
signal iserdes_q : std_logic_vector(5 downto 0);
signal iserdes_q_mux : std_logic_vector(5 downto 0);
signal iserdes_q_neg_r : std_logic_vector(5 downto 0);
signal iserdes_q_r : std_logic_vector(5 downto 0);
signal ocb_d1 : std_logic;
signal ocb_d2 : std_logic;
signal ocb_d3 : std_logic;
signal ocb_d4 : std_logic;
signal ocb_tfb : std_logic; -- Must be connected to T input of IODELAY
-- TFB turns IODELAY to ODELAY enabling
-- CLKPERFDELAY required to lock out TQ
signal rddata : std_logic_vector(3 downto 0);
signal tri_en1_r1 : std_logic;
signal tri_en2_r1 : std_logic;
signal tri_en3_r1 : std_logic;
signal tri_en4_r1 : std_logic;
signal wr_data_fall0_r1 : std_logic;
signal wr_data_fall0_r2 : std_logic;
signal wr_data_fall0_r3 : std_logic;
signal wr_data_fall0_r4 : std_logic;
signal wr_data_fall1_r1 : std_logic;
signal wr_data_fall1_r2 : std_logic;
signal wr_data_fall1_r3 : std_logic;
signal wr_data_fall1_r4 : std_logic;
signal wr_data_rise0_r1 : std_logic;
signal wr_data_rise0_r2 : std_logic;
signal wr_data_rise0_r3 : std_logic;
signal wr_data_rise0_r4 : std_logic;
signal wr_data_rise1_r1 : std_logic;
signal wr_data_rise1_r2 : std_logic;
signal wr_data_rise1_r3 : std_logic;
signal wr_data_rise1_r4 : std_logic;
signal xhdl1 : std_logic_vector(2 downto 0);
------ rd_bitslip component -------
component rd_bitslip
generic (
TCQ : integer := 100
);
port (
clk : in std_logic;
bitslip_cnt : in std_logic_vector(1 downto 0);
clkdly_cnt : in std_logic_vector(1 downto 0);
din : in std_logic_vector(5 downto 0);
qout : out std_logic_vector(3 downto 0)
);
end component;
attribute IODELAY_GROUP : string;
attribute IODELAY_GROUP of u_iodelay_dq : label is IODELAY_GRP;
begin
-- drive xhdl1 from xhdl1(1 downto 0) and inv_dqs
xhdl1 <= wr_calib_dly(1 downto 0) & inv_dqs;
--***************************************************************************
-- Bidirectional I/O
--***************************************************************************
u_iobuf_dq: IOBUF
generic map(
IBUF_LOW_PWR => IBUF_LOW_PWR
)
port map(
I => dq_iodelay,
T => dq_oe_n_r,
IO => ddr_dq,
O => dq_in
);
--***************************************************************************
-- Programmable Delay element - used for both input and output paths
--***************************************************************************
u_iodelay_dq : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "IO",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "VAR_LOADABLE",
IDELAY_VALUE => 0,
ODELAY_TYPE => "VAR_LOADABLE",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => dq_iodelay,
C => clk_rsync,
CE => '0',
DATAIN => '0',
IDATAIN => dq_in,
INC => '0',
ODATAIN => dq_oq, -- Input from OSERDES OQ
RST => '1',
T => ocb_tfb,
CNTVALUEIN => dlyval,
CNTVALUEOUT => dq_tap_cnt,
CLKIN => 'Z',
CINVCTRL => '0'
);
--***************************************************************************
-- Write Path
--***************************************************************************
--***********************************************************************
-- Write Bitslip
--***********************************************************************
-- dfi_wrdata_en0 - even clk cycles channel 0
-- dfi_wrdata_en1 - odd clk cycles channel 1
-- tphy_wrlat set to 0 clk cycle for CWL = 5,6,7,8
-- Valid dfi_wrdata* sent 1 clk cycle after dfi_wrdata_en* is asserted
-- WC for OCB (Output Circular Buffer) assertion for 1 clk cycle
-- WC aligned with dfi_wrdata_en*
-- first rising edge data (rise0)
-- first falling edge data (fall0)
-- second rising edge data (rise1)
-- second falling edge data (fall1)
process (clk)
begin
if (clk'event and clk = '1') then
wr_data_rise0_r1 <= wr_data_rise0 after (TCQ)*1 ps;
wr_data_fall0_r1 <= wr_data_fall0 after (TCQ)*1 ps;
wr_data_rise1_r1 <= wr_data_rise1 after (TCQ)*1 ps;
wr_data_fall1_r1 <= wr_data_fall1 after (TCQ)*1 ps;
wr_data_rise0_r2 <= wr_data_rise0_r1 after (TCQ)*1 ps;
wr_data_fall0_r2 <= wr_data_fall0_r1 after (TCQ)*1 ps;
wr_data_rise1_r2 <= wr_data_rise1_r1 after (TCQ)*1 ps;
wr_data_fall1_r2 <= wr_data_fall1_r1 after (TCQ)*1 ps;
wr_data_rise0_r3 <= wr_data_rise0_r2 after (TCQ)*1 ps;
wr_data_fall0_r3 <= wr_data_fall0_r2 after (TCQ)*1 ps;
wr_data_rise1_r3 <= wr_data_rise1_r2 after (TCQ)*1 ps;
wr_data_fall1_r3 <= wr_data_fall1_r2 after (TCQ)*1 ps;
wr_data_rise0_r4 <= wr_data_rise0_r3 after (TCQ)*1 ps;
wr_data_fall0_r4 <= wr_data_fall0_r3 after (TCQ)*1 ps;
wr_data_rise1_r4 <= wr_data_rise1_r3 after (TCQ)*1 ps;
wr_data_fall1_r4 <= wr_data_fall1_r3 after (TCQ)*1 ps;
end if;
end process;
-- Different nCWL values: 5, 6, 7, 8, 9
gen_ddr3_write_lat : if (DRAM_TYPE = "DDR3") generate
gen_ncwl5_odd : if ((nCWL = 5) or (nCWL = 7) or (nCWL = 9)) generate
process (clk)
begin
if (clk'event and clk = '1') then
if (WRLVL = "OFF") then
ocb_d1 <= wr_data_rise0_r1 after (TCQ)*1 ps;
ocb_d2 <= wr_data_fall0_r1 after (TCQ)*1 ps;
ocb_d3 <= wr_data_rise1_r1 after (TCQ)*1 ps;
ocb_d4 <= wr_data_fall1_r1 after (TCQ)*1 ps;
else
-- write command sent by MC on channel1
-- D3,D4 inputs of the OCB used to send write command to DDR3
-- Shift bitslip logic by 1 or 2 clk_mem cycles
-- Write calibration currently supports only upto 2 clk_mem cycles
case (xhdl1) is
-- 0 clk_mem delay required as per write calibration
when "000" =>
ocb_d1 <= wr_data_fall0_r1 after (TCQ)*1 ps;
ocb_d2 <= wr_data_rise1_r1 after (TCQ)*1 ps;
ocb_d3 <= wr_data_fall1_r1 after (TCQ)*1 ps;
ocb_d4 <= wr_data_rise0 after (TCQ)*1 ps;
-- DQS inverted during write leveling
when "001" =>
ocb_d1 <= wr_data_rise0_r1 after (TCQ)*1 ps;
ocb_d2 <= wr_data_fall0_r1 after (TCQ)*1 ps;
ocb_d3 <= wr_data_rise1_r1 after (TCQ)*1 ps;
ocb_d4 <= wr_data_fall1_r1 after (TCQ)*1 ps;
-- 1 clk_mem delay required as per write cal
when "010" =>
ocb_d1 <= wr_data_fall1_r2 after (TCQ)*1 ps;
ocb_d2 <= wr_data_rise0_r1 after (TCQ)*1 ps;
ocb_d3 <= wr_data_fall0_r1 after (TCQ)*1 ps;
ocb_d4 <= wr_data_rise1_r1 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 1 clk_mem delay required as per write cal
when "011" =>
ocb_d1 <= wr_data_rise1_r2 after (TCQ)*1 ps;
ocb_d2 <= wr_data_fall1_r2 after (TCQ)*1 ps;
ocb_d3 <= wr_data_rise0_r1 after (TCQ)*1 ps;
ocb_d4 <= wr_data_fall0_r1 after (TCQ)*1 ps;
-- 2 clk_mem delay required as per write cal
when "100" =>
ocb_d1 <= wr_data_fall0_r2 after (TCQ)*1 ps;
ocb_d2 <= wr_data_rise1_r2 after (TCQ)*1 ps;
ocb_d3 <= wr_data_fall1_r2 after (TCQ)*1 ps;
ocb_d4 <= wr_data_rise0_r1 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 2 clk_mem delay required as per write cal
when "101" =>
ocb_d1 <= wr_data_rise0_r2 after (TCQ)*1 ps;
ocb_d2 <= wr_data_fall0_r2 after (TCQ)*1 ps;
ocb_d3 <= wr_data_rise1_r2 after (TCQ)*1 ps;
ocb_d4 <= wr_data_fall1_r2 after (TCQ)*1 ps;
-- 3 clk_mem delay required as per write cal
when "110" =>
ocb_d1 <= wr_data_fall1_r3 after (TCQ)*1 ps;
ocb_d2 <= wr_data_rise0_r2 after (TCQ)*1 ps;
ocb_d3 <= wr_data_fall0_r2 after (TCQ)*1 ps;
ocb_d4 <= wr_data_rise1_r2 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 3 clk_mem delay required as per write cal
when "111" =>
ocb_d1 <= wr_data_rise1_r3 after (TCQ)*1 ps;
ocb_d2 <= wr_data_fall1_r3 after (TCQ)*1 ps;
ocb_d3 <= wr_data_rise0_r2 after (TCQ)*1 ps;
ocb_d4 <= wr_data_fall0_r2 after (TCQ)*1 ps;
-- defaults to 0 clk_mem delay
when others =>
ocb_d1 <= wr_data_fall0_r1 after (TCQ)*1 ps;
ocb_d2 <= wr_data_rise1_r1 after (TCQ)*1 ps;
ocb_d3 <= wr_data_fall1_r1 after (TCQ)*1 ps;
ocb_d4 <= wr_data_rise0 after (TCQ)*1 ps;
end case;
end if;
end if;
end process;
end generate;
gen_ncwl_even : if ((nCWL = 6) or (nCWL = 8)) generate
process (clk)
begin
if (clk'event and clk = '1') then
if (WRLVL = "OFF") then
ocb_d1 <= wr_data_rise1_r2 after (TCQ)*1 ps;
ocb_d2 <= wr_data_fall1_r2 after (TCQ)*1 ps;
ocb_d3 <= wr_data_rise0_r1 after (TCQ)*1 ps;
ocb_d4 <= wr_data_fall0_r1 after (TCQ)*1 ps;
else
-- write command sent by MC on channel1
-- D3,D4 inputs of the OCB used to send write command to DDR3
-- Shift bitslip logic by 1 or 2 clk_mem cycles
-- Write calibration currently supports only upto 2 clk_mem cycles
case (xhdl1) is
-- 0 clk_mem delay required as per write calibration
-- could not test 0011 case
when "000" =>
ocb_d1 <= wr_data_fall1_r2 after (TCQ)*1 ps;
ocb_d2 <= wr_data_rise0_r1 after (TCQ)*1 ps;
ocb_d3 <= wr_data_fall0_r1 after (TCQ)*1 ps;
ocb_d4 <= wr_data_rise1_r1 after (TCQ)*1 ps;
-- DQS inverted during write leveling
when "001" =>
ocb_d1 <= wr_data_rise1_r2 after (TCQ)*1 ps;
ocb_d2 <= wr_data_fall1_r2 after (TCQ)*1 ps;
ocb_d3 <= wr_data_rise0_r1 after (TCQ)*1 ps;
ocb_d4 <= wr_data_fall0_r1 after (TCQ)*1 ps;
-- 1 clk_mem delay required as per write cal
when "010" =>
ocb_d1 <= wr_data_fall0_r2 after (TCQ)*1 ps;
ocb_d2 <= wr_data_rise1_r2 after (TCQ)*1 ps;
ocb_d3 <= wr_data_fall1_r2 after (TCQ)*1 ps;
ocb_d4 <= wr_data_rise0_r1 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 1 clk_mem delay required as per write cal
when "011" =>
ocb_d1 <= wr_data_rise0_r2 after (TCQ)*1 ps;
ocb_d2 <= wr_data_fall0_r2 after (TCQ)*1 ps;
ocb_d3 <= wr_data_rise1_r2 after (TCQ)*1 ps;
ocb_d4 <= wr_data_fall1_r2 after (TCQ)*1 ps;
-- 2 clk_mem delay required as per write cal
when "100" =>
ocb_d1 <= wr_data_fall1_r3 after (TCQ)*1 ps;
ocb_d2 <= wr_data_rise0_r2 after (TCQ)*1 ps;
ocb_d3 <= wr_data_fall0_r2 after (TCQ)*1 ps;
ocb_d4 <= wr_data_rise1_r2 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 2 clk_mem delay required as per write cal
when "101" =>
ocb_d1 <= wr_data_rise1_r3 after (TCQ)*1 ps;
ocb_d2 <= wr_data_fall1_r3 after (TCQ)*1 ps;
ocb_d3 <= wr_data_rise0_r2 after (TCQ)*1 ps;
ocb_d4 <= wr_data_fall0_r2 after (TCQ)*1 ps;
-- 3 clk_mem delay required as per write cal
when "110" =>
ocb_d1 <= wr_data_fall0_r3 after (TCQ)*1 ps;
ocb_d2 <= wr_data_rise1_r3 after (TCQ)*1 ps;
ocb_d3 <= wr_data_fall1_r3 after (TCQ)*1 ps;
ocb_d4 <= wr_data_rise0_r2 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 3 clk_mem delay required as per write cal
when "111" =>
ocb_d1 <= wr_data_rise0_r3 after (TCQ)*1 ps;
ocb_d2 <= wr_data_fall0_r3 after (TCQ)*1 ps;
ocb_d3 <= wr_data_rise1_r3 after (TCQ)*1 ps;
ocb_d4 <= wr_data_fall1_r3 after (TCQ)*1 ps;
-- defaults to 0 clk_mem delay
when others =>
ocb_d1 <= wr_data_fall1_r2 after (TCQ)*1 ps;
ocb_d2 <= wr_data_rise0_r1 after (TCQ)*1 ps;
ocb_d3 <= wr_data_fall0_r1 after (TCQ)*1 ps;
ocb_d4 <= wr_data_rise1_r1 after (TCQ)*1 ps;
end case;
end if;
end if;
end process;
end generate;
end generate;
ddr2_write_lat : if (not(DRAM_TYPE = "DDR3")) generate
gen_ddr2_ncwl2 : if (nCWL = 2) generate
process (wr_data_rise1_r1, wr_data_fall1_r1, wr_data_rise0, wr_data_fall0)
begin
ocb_d1 <= wr_data_rise1_r1;
ocb_d2 <= wr_data_fall1_r1;
ocb_d3 <= wr_data_rise0;
ocb_d4 <= wr_data_fall0;
end process;
end generate;
gen_ddr2_ncwl3 : if (nCWL = 3) generate
process (clk)
begin
if (clk'event and clk = '1') then
ocb_d1 <= wr_data_rise0 after (TCQ)*1 ps;
ocb_d2 <= wr_data_fall0 after (TCQ)*1 ps;
ocb_d3 <= wr_data_rise1 after (TCQ)*1 ps;
ocb_d4 <= wr_data_fall1 after (TCQ)*1 ps;
end if;
end process;
end generate;
gen_ddr2_ncwl4 : if (nCWL = 4) generate
process (clk)
begin
if (clk'event and clk = '1') then
ocb_d1 <= wr_data_rise1_r1;
ocb_d2 <= wr_data_fall1_r1;
ocb_d3 <= wr_data_rise0;
ocb_d4 <= wr_data_fall0;
end if;
end process;
end generate;
gen_ddr2_ncwl5 : if (nCWL = 5) generate
process (clk)
begin
if (clk'event and clk = '1') then
ocb_d1 <= wr_data_rise0_r1 after (TCQ)*1 ps;
ocb_d2 <= wr_data_fall0_r1 after (TCQ)*1 ps;
ocb_d3 <= wr_data_rise1_r1 after (TCQ)*1 ps;
ocb_d4 <= wr_data_fall1_r1 after (TCQ)*1 ps;
end if;
end process;
end generate;
gen_ddr2_ncwl6 : if (nCWL = 6) generate
process (clk)
begin
if (clk'event and clk = '1') then
ocb_d1 <= wr_data_rise1_r2 after (TCQ)*1 ps;
ocb_d2 <= wr_data_fall1_r2 after (TCQ)*1 ps;
ocb_d3 <= wr_data_rise0_r1 after (TCQ)*1 ps;
ocb_d4 <= wr_data_fall0_r1 after (TCQ)*1 ps;
end if;
end process;
end generate;
end generate;
--***************************************************************************
-- on a write, rising edge of DQS corresponds to rising edge of clk_mem
-- We also know:
-- 1. DQS driven 1/2 clk_mem cycle after corresponding DQ edge
-- 2. first rising DQS edge driven on falling edge of clk_mem
-- 3. DQ to be delayed 1/4 clk_mem cycle using ODELAY taps
-- 4. therefore, rising data driven on rising edge of clk_mem
--***************************************************************************
u_oserdes_dq : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0',
INIT_TQ => '1',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => dq_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => dq_oe_n_r,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => ocb_d1,
D2 => ocb_d2,
D3 => ocb_d3,
D4 => ocb_d4,
D5 => 'Z',
D6 => 'Z',
OCE => '1',
ODV => '0',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst,
T1 => dq_oe_n(0),
T2 => dq_oe_n(1),
T3 => dq_oe_n(2),
T4 => dq_oe_n(3),
TFB => ocb_tfb,
TCE => '1',
WC => '0'
);
--***************************************************************************
-- Read Path
--***************************************************************************
-- Assign equally to avoid delta-delay issues in simulation
iserdes_clk <= clk_cpt;
iserdes_clkb <= not(clk_cpt);
u_iserdes_dq : ISERDESE1
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 4,
DYN_CLKDIV_INV_EN => TRUE,
DYN_CLK_INV_EN => FALSE,
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY_DDR3",
NUM_CE => 2,
IOBDELAY => "IFD",
OFB_USED => FALSE,
SERDES_MODE => "MASTER",
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
port map (
O => open,
Q1 => iserdes_q(0),
Q2 => iserdes_q(1),
Q3 => iserdes_q(2),
Q4 => iserdes_q(3),
Q5 => iserdes_q(4),
Q6 => iserdes_q(5),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => iserdes_clk,
CLKB => iserdes_clkb,
CLKDIV => clk_rsync,
D => 'Z',
DDLY => dq_iodelay,
DYNCLKDIVSEL => rd_clkdiv_inv,
DYNCLKSEL => '0',
OCLK => clk_mem, -- Not used, but connect to avoid DRC
OFB => '0',
RST => rst_rsync,
SHIFTIN1 => '0',
SHIFTIN2 => '0'
);
--*****************************************************************
-- Selectable registers on ISERDES data outputs depending on
-- whether DYNCLKDIVSEL is enabled or not
--*****************************************************************
-- Capture first using CLK_RSYNC falling edge domain, then transfer
-- to rising edge CLK_RSYNC. We could also attempt to transfer
-- directly from falling edge CLK_RSYNC domain (in ISERDES) to
-- rising edge CLK_RSYNC domain in fabric. This is allowed as long
-- as the half-cycle timing on these paths can be met.
process (clk_rsync)
begin
if (clk_rsync'event and clk_rsync = '0') then
iserdes_q_neg_r <= iserdes_q after (TCQ)*1 ps;
end if;
end process;
process (clk_rsync)
begin
if (clk_rsync'event and clk_rsync = '1') then
iserdes_q_r <= iserdes_q_neg_r after (TCQ)*1 ps;
end if;
end process;
iserdes_q_mux <= iserdes_q_r when (rd_clkdiv_inv = '1') else
iserdes_q;
--*****************************************************************
-- Read bitslip logic
--*****************************************************************
u_rd_bitslip: rd_bitslip
generic map(
TCQ => TCQ
)
port map(
clk => clk_rsync,
bitslip_cnt => rd_bitslip_cnt,
clkdly_cnt => rd_clkdly_cnt,
din => iserdes_q_mux,
qout => rddata
);
rd_data_rise0 <= rddata(3);
rd_data_fall0 <= rddata(2);
rd_data_rise1 <= rddata(1);
rd_data_fall1 <= rddata(0);
end trans_phy_dq_iob;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package serial_interface_defs is
subtype reg_address_vector is std_logic_vector(1 downto 0);
constant status_reg_address : reg_address_vector := B"00";
constant control_reg_address : reg_address_vector := B"01";
constant rx_data_register : reg_address_vector := B"10";
constant tx_data_register : reg_address_vector := B"11";
subtype data_vector is std_logic_vector(7 downto 0);
-- . . . -- other useful declarations
component serial_interface is
port ( clock_phi1, clock_phi2 : in std_logic;
serial_select : in std_logic;
reg_address : in reg_address_vector;
data : inout data_vector;
interrupt_request : out std_logic;
rx_serial_data : in std_logic;
tx_serial_data : out std_logic );
end component serial_interface;
end package serial_interface_defs;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package serial_interface_defs is
subtype reg_address_vector is std_logic_vector(1 downto 0);
constant status_reg_address : reg_address_vector := B"00";
constant control_reg_address : reg_address_vector := B"01";
constant rx_data_register : reg_address_vector := B"10";
constant tx_data_register : reg_address_vector := B"11";
subtype data_vector is std_logic_vector(7 downto 0);
-- . . . -- other useful declarations
component serial_interface is
port ( clock_phi1, clock_phi2 : in std_logic;
serial_select : in std_logic;
reg_address : in reg_address_vector;
data : inout data_vector;
interrupt_request : out std_logic;
rx_serial_data : in std_logic;
tx_serial_data : out std_logic );
end component serial_interface;
end package serial_interface_defs;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package serial_interface_defs is
subtype reg_address_vector is std_logic_vector(1 downto 0);
constant status_reg_address : reg_address_vector := B"00";
constant control_reg_address : reg_address_vector := B"01";
constant rx_data_register : reg_address_vector := B"10";
constant tx_data_register : reg_address_vector := B"11";
subtype data_vector is std_logic_vector(7 downto 0);
-- . . . -- other useful declarations
component serial_interface is
port ( clock_phi1, clock_phi2 : in std_logic;
serial_select : in std_logic;
reg_address : in reg_address_vector;
data : inout data_vector;
interrupt_request : out std_logic;
rx_serial_data : in std_logic;
tx_serial_data : out std_logic );
end component serial_interface;
end package serial_interface_defs;
|
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--This VHDL code is part of the OZ-3, a 32-bit processor
--
--Module Title: ID
--Module Description:
-- The Instruction Decode stage of the OZ-3.
-- This decodes the instructions it receives from the IF
-- stage and tells the rest of the processor how to handle
-- the instruction. It also exchanges most of the register
-- data in the processor.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ID is
Port ( --Inputs--
--Main inputs
clock : in STD_LOGIC;
reset : in STD_LOGIC;
instruction_from_IF : in STD_LOGIC_VECTOR(31 downto 0);
--External register file inputs
rfile_RAM_reg_addr_from_MEMIO : in STD_LOGIC_VECTOR(4 downto 0);
rfile_write_addr_from_WB : in STD_LOGIC_VECTOR(4 downto 0);
rfile_write_data_from_WB : in STD_LOGIC_VECTOR(31 downto 0);
rfile_write_e_from_WB : in STD_LOGIC;
--Forwarding logic inptus
forward_addr_EX : in STD_LOGIC_VECTOR(4 downto 0);
forward_data_EX : in STD_LOGIC_VECTOR(31 downto 0);
forward_addr_MEMIO : in STD_LOGIC_VECTOR(4 downto 0);
forward_data_MEMIO : in STD_LOGIC_VECTOR(31 downto 0);
forward_addr_WB : in STD_LOGIC_VECTOR(4 downto 0);
forward_data_WB : in STD_LOGIC_VECTOR(31 downto 0);
--Outputs--
--EX Control
ALU_A_to_EX : out STD_LOGIC_VECTOR(31 downto 0);
ALU_B_to_EX : out STD_LOGIC_VECTOR(31 downto 0);
EX_control : out STD_LOGIC_VECTOR(11 downto 0);
--MEMIO Control
RAM_reg_data_to_MEMIO : out STD_LOGIC_VECTOR(31 downto 0);
MEMIO_control : out STD_LOGIC_VECTOR(20 downto 0);
--WB Control
WB_control : out STD_LOGIC_VECTOR(5 downto 0));
end ID;
architecture Behavioral of ID is
--//Components\\--
--The register file
component RegFile is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
write_e : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(31 downto 0);
r_addr1 : in STD_LOGIC_VECTOR(4 downto 0);
r_addr2 : in STD_LOGIC_VECTOR(4 downto 0);
r_addr3 : in STD_LOGIC_VECTOR(4 downto 0);
w_addr1 : in STD_LOGIC_VECTOR(4 downto 0);
data_out_1 : out STD_LOGIC_VECTOR(31 downto 0);
data_out_2 : out STD_LOGIC_VECTOR(31 downto 0);
data_out_3 : out STD_LOGIC_VECTOR(31 downto 0));
end component;
--Generic rising-edge resgister
component GenReg is
generic (size : integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end component;
--\\Components//--
--//Signals\\--
--All of these are signals that carry possible addresses
--for the first output of the register file.
signal rfile_read_addr1_cntl : STD_LOGIC_VECTOR(4 downto 0);
signal rfile_read_addr1_arith_logic : STD_LOGIC_VECTOR(4 downto 0);
signal rfile_read_addr1_MEMIO : STD_LOGIC_VECTOR(4 downto 0);
signal rfile_read_addr1 : STD_LOGIC_VECTOR(4 downto 0);
--Signal that carries the address for the second output of the register file
signal rfile_read_addr2 : STD_LOGIC_VECTOR(4 downto 0);
--This signal carries the register file's third output to the forwarding/output logic
signal RAM_reg_data_from_rfile : STD_LOGIC_VECTOR(31 downto 0);
--These signals carry possible write enable signals that would go to the WB.
signal WB_WE_arith_logic : STD_LOGIC;
signal WB_WE_MEMIO : STD_LOGIC;
--For the two sections of the decoder that deal with instructions that store
--results in a register, the first two signals carry the address of that
--register for the current instruction.
signal result_reg_arith_logic : STD_LOGIC_VECTOR(4 downto 0);
signal result_reg_MEMIO : STD_LOGIC_VECTOR(4 downto 0);
signal result_reg : STD_LOGIC_VECTOR(4 downto 0);
--Carries the instruction out of the input register
signal instruction : STD_LOGIC_VECTOR(31 downto 0);
--All of this has to do with the output to the ALU.
--It'll mostly get handled by tricky ORing, due to the
--fact that the "do nothing" state for the drivers of these signals
--is all zeros, so I can OR them to allow the only used value through
signal rfile_out_1 : STD_LOGIC_VECTOR(31 downto 0);
signal rfile_out_2 : STD_LOGIC_VECTOR(31 downto 0);
signal arith_immediate : STD_LOGIC_VECTOR(31 downto 0);
signal MEMIO_immediate : STD_LOGIC_VECTOR(31 downto 0);
signal displacement : STD_LOGIC_VECTOR(31 downto 0);
signal ALU_B : STD_LOGIC_VECTOR(31 downto 0);
--\\Signals//--
begin
--This process takes care of control instructions
control: process (instruction) is
begin
--Signals to initialize to zero
EX_control(6 downto 4) <= b"000";
rfile_read_addr1_cntl <= b"00000";
displacement <= x"00000000";
if instruction(31) = '1' then --Testing the opcode
EX_control(6 downto 4) <= instruction(28 downto 26); --ALU operation select value (add)
rfile_read_addr1_cntl <= instruction(25 downto 21); --Address of the register being used
if (instruction(20) = '0') then --Sign extension of the displacement value
displacement <= b"00000000000" & instruction(20 downto 0);
else
displacement <= b"11111111111" & instruction(20 downto 0);
end if;
end if;
end process;
--This process decodes memory and I/O instructions
MEMIO: process (instruction) is
begin
--Signals to initialize as zero
MEMIO_immediate <= x"00000000";
MEMIO_control(20 downto 18) <= b"000";
MEMIO_control(12 downto 0) <= b"0000000000000";
rfile_read_addr1_MEMIO <= b"00000";
result_reg_MEMIO <= b"00000";
WB_WE_MEMIO <= '0';
if instruction(30) = '1' then --Testing the opcode
--Sign extension of the immediate value from MEMIO
if instruction(15) = '0' then
MEMIO_immediate <= (x"0000" & instruction(15 downto 0));
else
MEMIO_immediate <= (x"FFFF" & instruction(15 downto 0));
end if;
--If it's a store/load instruction
if instruction(29) = '1' then
--Control signal for the RAM section
MEMIO_control(2) <= '1';
--Detect load or store
if instruction(27) = '0' then
--Set up signals for a load instruction
result_reg_MEMIO <= instruction(25 downto 21); --result register
rfile_read_addr1_MEMIO <= instruction(20 downto 16); --the register specified
MEMIO_control(12 downto 8) <= instruction(25 downto 21); --dest/data register for RAM operations
MEMIO_control(19 downto 18) <= b"10"; --MUX control
WB_WE_MEMIO <= '1'; --write enable
else
--Set up signals for a store instruction
rfile_read_addr1_MEMIO <= instruction(20 downto 16); --register specified
MEMIO_control(12 downto 8) <= instruction(25 downto 21); --dest/data register for RAM operations
MEMIO_control(7) <= '1'; --change the dRAM write/read signal
end if;
--Upper/lower control signal
MEMIO_control(20) <= instruction(26);
end if;
--If it's a port instruction
if instruction(29 downto 27) = b"001" then
--Control signal for the port section
MEMIO_control(1) <= '1';
--Detect input/output with the ports
if instruction(26) = '0' then --Input
result_reg_MEMIO <= instruction(25 downto 21); --result register
WB_WE_MEMIO <= '1'; --write enable
MEMIO_control(19 downto 18) <= b"01"; --set select for MUX to iprt data
else --Output
rfile_read_addr1_MEMIO <= instruction(20 downto 16); --data register
MEMIO_control(6) <= '1'; --enable the oprt register clock
end if;
end if;
--If it's a pin instruction
if instruction(29 downto 28) = b"01" then
--Control signal for the pin section
MEMIO_control(0) <= '1';
--Detect if it's an output or inpupt pin instruction
if instruction(27) = '0' then --Output
MEMIO_control(5) <= instruction(26); --Opin 1/0 select
MEMIO_control(4) <= '1'; --Opin register clock enable
else --Input
MEMIO_control(3) <= '1'; --pin check enable
end if;
end if;
end if;
end process;
--This process decodes arithmetic and logic instructions
arith_logic: process (instruction) is
begin
--Signals to initialize as zero
EX_control(3 downto 0) <= b"0000";
arith_immediate <= x"00000000";
result_reg_arith_logic <= b"00000";
rfile_read_addr1_arith_logic <= b"00000";
rfile_read_addr2 <= b"00000";
WB_WE_arith_logic <= '0';
if instruction(30 downto 29) = b"01" then --Test the opcode
result_reg_arith_logic <= instruction(25 downto 21); --Register that the result is stored in
rfile_read_addr1_arith_logic <= instruction(20 downto 16); --Register that's the first operand
WB_WE_arith_logic <= '1'; --write enable
--Detecting a register verus immediate addressing mode instruction
if instruction(28 downto 26) = b"111" then
--This is getting the ALU select value
EX_control(3 downto 0) <= instruction(3 downto 0);
--Register file source 2 address
rfile_read_addr2 <= instruction(15 downto 11);
else
--ALU select value if the instruction is in the immediate addressing mode
EX_control(3 downto 0) <= ('0' & instruction(28 downto 26));
--Immediate value sign extension
if instruction(15) = '0' then
arith_immediate <= (x"0000" & instruction(15 downto 0));
else
arith_immediate <= (x"FFFF" & instruction(15 downto 0));
end if;
end if;
end if;
end process;
--This process handles the main outputs, along with
--forwarding logic (ALU A and B already ORed n such)
output: process (rfile_out_1, ALU_B, forward_data_EX, forward_data_MEMIO, forward_data_WB,
forward_addr_EX, forward_addr_MEMIO, forward_addr_WB, rfile_read_addr1,
rfile_read_addr2, rfile_RAM_reg_addr_from_MEMIO, RAM_reg_data_from_rfile) is
begin
--Logic for ALU_A/src1
if rfile_read_addr1 /= b"00000" then
--if the source register is EX's result register
if rfile_read_addr1 = forward_addr_EX then
ALU_A_to_EX <= forward_data_EX;
--if the source register is MEMIO's result register
elsif rfile_read_addr1 = forward_addr_MEMIO then
ALU_A_to_EX <= forward_data_MEMIO;
--if the source register is WB's result register
elsif rfile_read_addr1 = forward_addr_WB then
ALU_A_to_EX <= forward_data_WB;
else
ALU_A_to_EX <= rfile_out_1;
end if;
else
ALU_A_to_EX <= rfile_out_1;
end if;
--Logic for ALU_B/src2
--if the source register is EX's result register
if rfile_read_addr2 /= b"00000" then
if rfile_read_addr2 = forward_addr_EX then
ALU_B_to_EX <= forward_data_EX;
--if the source register is MEMIO's result register
elsif rfile_read_addr2 = forward_addr_MEMIO then
ALU_B_to_EX <= forward_data_MEMIO;
--if the source register is WB's result register
elsif rfile_read_addr2 = forward_addr_WB then
ALU_B_to_EX <= forward_data_WB;
else
ALU_B_to_EX <= ALU_B;
end if;
else
ALU_B_to_EX <= ALU_B;
end if;
--Logic for the RAM register
--if the source register is EX's RAM register
if rfile_RAM_reg_addr_from_MEMIO /= b"00000" then
--if the source register is EX's result register
if rfile_RAM_reg_addr_from_MEMIO = forward_addr_EX then
RAM_reg_data_to_MEMIO <= forward_data_EX;
--if the source register is MEMIO's result register
elsif rfile_RAM_reg_addr_from_MEMIO = forward_addr_MEMIO then
RAM_reg_data_to_MEMIO <= forward_data_MEMIO;
--if the source register is WB's result register
elsif rfile_RAM_reg_addr_from_MEMIO = forward_addr_WB then
RAM_reg_data_to_MEMIO <= forward_data_WB;
else
RAM_reg_data_to_MEMIO <= RAM_reg_data_from_rfile;
end if;
end if;
end process;
--Signals getting combined (I know this adds a lot of excess logic, will optimize later)
--I can do this because the modules that drive these signals output all zeros when they're inactive
rfile_read_addr1 <= (rfile_read_addr1_cntl or rfile_read_addr1_MEMIO or rfile_read_addr1_arith_logic);
result_reg <= (result_reg_MEMIO or result_reg_arith_logic);
WB_control(0) <= (WB_WE_MEMIO or WB_WE_arith_logic);
ALU_B <= (rfile_out_2 or arith_immediate or MEMIO_immediate or displacement);
--Finishing up the control signals (they need the result registers)
MEMIO_control(17 downto 13) <= result_reg;
EX_control(11 downto 7) <= result_reg;
WB_control(5 downto 1) <= result_reg;
--Register file
rfile: RegFile port map (clock => clock,
reset => reset,
write_e => rfile_write_e_from_WB,
data_in => rfile_write_data_from_WB,
r_addr1 => rfile_read_addr1,
r_addr2 => rfile_read_addr2,
r_addr3 => rfile_RAM_reg_addr_from_MEMIO,
w_addr1 => rfile_write_addr_from_WB,
data_out_1 => rfile_out_1,
data_out_2 => rfile_out_2,
data_out_3 => RAM_reg_data_from_rfile);
--Input register
inst_reg : GenReg generic map (32)
port map (clock => clock,
enable => '1',
reset => reset,
data => instruction_from_IF,
output => instruction);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity somadorSubtrador is
generic(largura: natural := 8);
port(
entradaA, entradaB: in std_logic_vector(largura-1 downto 0);
carryIn: in std_logic;
saida: out std_logic_vector(largura-1 downto 0)
);
end entity;
architecture comportamental of somadorSubtrador is
begin
saida <= std_logic_vector(signed(entradaA)+signed(entradaB)) when carryIn='0' else
std_logic_vector(signed(entradaA)-signed(entradaB));
end architecture;
|
--
-- This file is part of top_alphanumeric
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_alphanumeric is
Port ( clk : in STD_LOGIC;
w1a : inout STD_LOGIC_VECTOR (15 downto 0);
w1b : inout STD_LOGIC_VECTOR (15 downto 0);
w2c : inout STD_LOGIC_VECTOR (15 downto 0);
rx : in STD_LOGIC;
tx : inout STD_LOGIC
);
end top_alphanumeric;
architecture Behavioral of top_alphanumeric is
COMPONENT clock_25mhz
PORT(
CLKIN_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic
);
END COMPONENT;
-- Clock signal
signal clk_25mhz : std_logic;
signal reset : std_logic;
-- Screen control signals
signal vsync : std_logic;
signal hsync : std_logic;
signal enable : std_logic;
signal screen_right_left : std_logic;
signal screen_up_down : std_logic;
signal r : std_logic_vector ( 5 downto 0);
signal g : std_logic_vector ( 5 downto 0);
signal b : std_logic_vector ( 5 downto 0);
-- Audio signals
signal audio_right : std_logic;
signal audio_left : std_logic;
-- Signals coming from image contoler
signal x_out : std_logic_vector( 9 downto 0);
signal y_out : std_logic_vector( 8 downto 0);
signal vsync_ok : std_logic;
signal hsync_ok : std_logic;
signal enable_ok : std_logic;
-- Signals to write in screen memory
signal addr : std_logic_vector(12 downto 0) := (others => '0');
signal char_code : std_logic_vector(7 downto 0);
signal color_code : std_logic_vector(9 downto 0);
signal write_enable : std_logic := '0';
begin
Inst_clock_25mhz: clock_25mhz PORT MAP(
CLKIN_IN => clk,
CLKFX_OUT => clk_25mhz,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open
);
Inst_giovanni_card : entity work.giovanni_card PORT MAP(
w1a => w1a,
w1b => w1b,
scr_red => r,
scr_green => g,
scr_blue => b,
scr_clk => clk_25mhz,
scr_hsync => hsync_ok,
scr_vsync => vsync_ok,
scr_enable => enable_ok,
scr_right_left => screen_right_left,
scr_up_down => screen_up_down,
audio_right => audio_right,
audio_left => audio_left,
audio_stereo_ok => open,
audio_plugged => open,
io => open
);
Inst_driver_sharp : entity work.driver_sharp(behavorial) PORT MAP(
clk => clk_25mhz,
rst => reset,
vsync => vsync,
hsync => hsync,
enable => enable,
x_out => x_out,
y_out => y_out
);
inst_image_controler : entity work.image_controler PORT MAP(
clk => clk_25mhz,
rst => reset,
r => r,
g => g,
b => b,
x => x_out,
y => y_out,
hsync_in => hsync,
vsync_in => vsync,
enable_in => enable,
write_enable => write_enable,
write_addr => addr,
char_code => char_code,
color_code => color_code,
hsync_out => hsync_ok,
vsync_out => vsync_ok,
enable_out => enable_ok
);
reset <= '0';
screen_right_left <= '1';
screen_up_down <= '1';
audio_right <= '0';
audio_left <= '0';
end Behavioral;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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5Xv12OZHAg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4320)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4320)
`protect data_block
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`protect end_protected
|
-- Vhdl test bench created from schematic /home/emmanuel/current_projects/Xilinx/Workspace/cpu_mips32/add_32b.sch - Sat May 12 15:23:12 2012
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY add_32b_add_32b_sch_tb IS
END add_32b_add_32b_sch_tb;
ARCHITECTURE behavioral OF add_32b_add_32b_sch_tb IS
COMPONENT add_32b
PORT( CI : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
OFL : OUT STD_LOGIC;
CO : OUT STD_LOGIC;
S : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
END COMPONENT;
SIGNAL CI : STD_LOGIC;
SIGNAL A : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL B : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL OFL : STD_LOGIC;
SIGNAL CO : STD_LOGIC;
SIGNAL S : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
UUT: add_32b PORT MAP(
CI => CI,
A => A,
B => B,
OFL => OFL,
CO => CO,
S => S
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
CI <= '0';
A <= "00000000000000000000000000000000";
B <= "00000000000000000000000000000001";
wait for 1ms;
A <= "00000000000000000000000000000001";
B <= "00000000000000000000000000000001";
wait for 1ms;
A <= "00000000000000000000000000000111";
B <= "00000000000000000000000000000011";
wait for 1ms;
A <= "10000000000000000000000000000001";
B <= "00000000000000000000000000000011";
wait for 1ms;
A <= "11111111111111111111111111111111";
B <= "00000000000000000000000000000001";
wait for 1ms;
A <= "11111111111111111111111111110001";
B <= "00000000000000000000000000001110";
wait for 1ms;
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
|
-------------------------------------------------------------------------------
-- vga2tmds.vhd
-- Joris van Rantwijk
--
-- This entity takes VGA signals as input (in the form of 8-bit RGB words
-- and HSYNC/VSYNC signals) and produces TMDS signals as output.
--
-- The input side of this entity may be connected to SVGACTRL or APBVGA
-- components from GRLIB. The output side of this entity may be connected
-- to a TMDS transmitter for a HDMI or DVI output port.
--
-- The output operates in DVI mode: no guard bands and no data islands
-- are sent. This is actually not allowed on HDMI links, but HDMI devices
-- should just accept it in DVI-compatibility mode.
--
------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library unisim;
use unisim.vcomponents.ODDR2;
entity vga2tmds is
generic (
tech : integer := 0
);
port (
-- VGA pixel clock.
vgaclk : in std_logic;
-- Fast clock at 5 times pixel clock frequency.
fastclk : in std_logic;
-- Output signals from APBVGA or SVGACTRL.
vgao : in apbvga_out_type;
-- TMDS output signals.
tmdsclk : out std_logic;
tmdsdat : out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of vga2tmds is
-- registers in video coding pipeline
type video_coder_regs is record
q0_dat : std_logic_vector(8 downto 0); -- stage 0: partial XOR
q1_dat : std_logic_vector(8 downto 0); -- stage 1: transition minimized
q2_dat : std_logic_vector(8 downto 0); -- stage 2: transition minimized
q2_nd : signed(3 downto 0); -- stage 2: (N1 - N0) / 2
q3_dat : std_logic_vector(9 downto 0); -- stage 3: final output
q3_cnt : signed(3 downto 0); -- stage 3: DC counter
end record;
-- registers in pixel clock domain
type pregs_type is record
blank : std_logic_vector(3 downto 0); -- pipeline for blanking signal
vcode0 : video_coder_regs; -- coding pipeline for ch0
vcode1 : video_coder_regs; -- coding pipeline for ch1
vcode2 : video_coder_regs; -- coding pipeline for ch2
bufptr : std_ulogic; -- current buffer slot
dbuf0 : std_logic_vector(29 downto 0); -- 2-slot output buffer
dbuf1 : std_logic_vector(29 downto 0);
end record;
-- registers in fast clock domain
type fregs_type is record
bufptr : std_logic_vector(1 downto 0); -- resynced bufptr
shiftstate : std_logic_vector(3 downto 0); -- one-hot state
tm0shift : std_logic_vector(9 downto 0); -- output shift registers
tm1shift : std_logic_vector(9 downto 0);
tm2shift : std_logic_vector(9 downto 0);
tm0out : std_logic_vector(1 downto 0); -- DDR output registers
tm1out : std_logic_vector(1 downto 0);
tm2out : std_logic_vector(1 downto 0);
tmcout : std_logic_vector(1 downto 0);
end record;
-- reset values
constant video_coder_regs_reset: video_coder_regs := (
q0_dat => (others => '0'),
q1_dat => (others => '0'),
q2_dat => (others => '0'),
q2_nd => (others => '0'),
q3_dat => (others => '0'),
q3_cnt => (others => '0') );
constant pregs_reset: pregs_type := (
blank => (others => '0'),
vcode0 => video_coder_regs_reset,
vcode1 => video_coder_regs_reset,
vcode2 => video_coder_regs_reset,
bufptr => '0',
dbuf0 => (others => '0'),
dbuf1 => (others => '0') );
-- registers in pixel clock domain
signal pr : pregs_type := pregs_reset;
signal prin : pregs_type;
-- registers in fast clock domain
signal fr, frin : fregs_type;
signal vcc, gnd: std_ulogic;
signal fastclk_n: std_ulogic;
-- Control Period Coding
constant tmds_ctrl_code_00: std_logic_vector(9 downto 0) := "1101010100";
constant tmds_ctrl_code_01: std_logic_vector(9 downto 0) := "0010101011";
constant tmds_ctrl_code_10: std_logic_vector(9 downto 0) := "0101010100";
constant tmds_ctrl_code_11: std_logic_vector(9 downto 0) := "1010101011";
-----------------------------------------------------------------------------
-- Video Coding pipeline
-----------------------------------------------------------------------------
function count_bits(d: in std_logic_vector; n: in integer)
return unsigned is
variable y: unsigned(n-1 downto 0);
begin
y := to_unsigned(0, n);
for i in d'range loop
if d(i) = '1' then
y := y + 1;
end if;
end loop;
return y;
end function;
procedure tmds_video_coder(din: in std_logic_vector(7 downto 0);
clrn: in std_ulogic;
regs: in video_coder_regs;
vregs: out video_coder_regs ) is
variable v_cnt_din: unsigned(2 downto 0);
begin
-- stage 1: XOR first 5 bits and choose between XOR/XNOR coding
vregs.q0_dat(0) := din(0);
vregs.q0_dat(1) := din(0) xor din(1);
vregs.q0_dat(2) := din(0) xor din(1) xor din(2);
vregs.q0_dat(3) := din(0) xor din(1) xor din(2) xor din(3);
vregs.q0_dat(4) := din(0) xor din(1) xor din(2) xor din(3) xor din(4);
vregs.q0_dat(7 downto 5) := din(7 downto 5);
v_cnt_din := count_bits(din(7 downto 1), 3);
if v_cnt_din > 3 then
vregs.q0_dat(8) := '0';
else
vregs.q0_dat(8) := '1';
end if;
-- stage 2: XOR last 3 bits and apply XNOR if needed
vregs.q1_dat(0) := regs.q0_dat(0);
vregs.q1_dat(1) := regs.q0_dat(1) xor regs.q0_dat(8) xor '1';
vregs.q1_dat(2) := regs.q0_dat(2);
vregs.q1_dat(3) := regs.q0_dat(3) xor regs.q0_dat(0) xor '1';
vregs.q1_dat(4) := regs.q0_dat(4);
vregs.q1_dat(5) := regs.q0_dat(4) xor regs.q0_dat(5) xor regs.q0_dat(8) xor '1';
vregs.q1_dat(6) := regs.q0_dat(4) xor regs.q0_dat(5) xor regs.q0_dat(6);
vregs.q1_dat(7) := regs.q0_dat(4) xor regs.q0_dat(5) xor regs.q0_dat(6) xor regs.q0_dat(7) xor regs.q0_dat(8) xor '1';
vregs.q1_dat(8) := regs.q0_dat(8);
-- stage 3: count difference between nr of 1 and 0 bits (divided by 2)
vregs.q2_dat := regs.q1_dat;
vregs.q2_nd := signed(count_bits(regs.q1_dat(7 downto 0), 4)) - 4;
-- stage 4: DC balance
if (regs.q3_cnt < 0 and regs.q2_nd < 0) or
((regs.q3_cnt = 0 or regs.q2_nd = 0) and (regs.q2_dat(8) = '0')) then
-- flip bits
vregs.q3_dat(7 downto 0) := not regs.q2_dat(7 downto 0);
vregs.q3_dat(8) := regs.q2_dat(8);
vregs.q3_dat(9) := '1';
if regs.q2_dat(8) = '1' then
vregs.q3_cnt := regs.q3_cnt - regs.q2_nd + 1;
else
vregs.q3_cnt := regs.q3_cnt - regs.q2_nd;
end if;
else
-- keep bits
vregs.q3_dat(7 downto 0) := regs.q2_dat(7 downto 0);
vregs.q3_dat(8) := regs.q2_dat(8);
vregs.q3_dat(9) := '0';
if regs.q2_dat(8) = '1' then
vregs.q3_cnt := regs.q3_cnt + regs.q2_nd;
else
vregs.q3_cnt := regs.q3_cnt + regs.q2_nd - 1;
end if;
end if;
-- reset DC counter
if clrn = '0' then
vregs.q3_cnt := "0000";
end if;
end procedure;
begin
vcc <= '1'; gnd <= '0';
fastclk_n <= not fastclk;
-----------------------------------------------------------------------------
-- DDR output registers
-----------------------------------------------------------------------------
-- It would of course be nicer to do this with ddr_oreg from techmap,
-- but it can not handle the rising -> falling data path fast enough.
ddr0: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsdat(0), C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tm0out(0), D1 => fr.tm0out(1), R => gnd, S => gnd );
ddr1: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsdat(1), C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tm1out(0), D1 => fr.tm1out(1), R => gnd, S => gnd );
ddr2: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsdat(2), C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tm2out(0), D1 => fr.tm2out(1), R => gnd, S => gnd );
ddrc: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsclk, C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tmcout(0), D1 => fr.tmcout(1), R => gnd, S => gnd );
-----------------------------------------------------------------------------
-- Combinatorial process for slow signals (TMDS encoder)
-----------------------------------------------------------------------------
pcomb: process (pr, vgao) is
variable v: pregs_type;
variable vtm0: std_logic_vector(9 downto 0);
variable vtm1: std_logic_vector(9 downto 0);
variable vtm2: std_logic_vector(9 downto 0);
begin
v := pr;
-- Video Data Coding pipeline.
v.blank := pr.blank(2 downto 0) & vgao.blank;
tmds_video_coder(vgao.video_out_b, pr.blank(2), pr.vcode0, v.vcode0);
tmds_video_coder(vgao.video_out_g, pr.blank(2), pr.vcode1, v.vcode1);
tmds_video_coder(vgao.video_out_r, pr.blank(2), pr.vcode2, v.vcode2);
if pr.blank(3) = '0' then
-- Display blanking; use Control Period Coding.
-- Send D0=HSYNC and D1=VSYNC via channel 0.
if vgao.vsync = '0' and vgao.hsync = '0' then
vtm0 := tmds_ctrl_code_00;
elsif vgao.vsync = '0' and vgao.hsync = '1' then
vtm0 := tmds_ctrl_code_01;
elsif vgao.vsync = '1' and vgao.hsync = '0' then
vtm0 := tmds_ctrl_code_10;
else
vtm0 := tmds_ctrl_code_11;
end if;
-- Send Video Data Preamble via channels 1 and 2.
vtm1 := tmds_ctrl_code_01;
vtm2 := tmds_ctrl_code_00;
else
-- Send Video Data; use 24-bit RGB pixel encoding.
vtm0 := pr.vcode0.q3_dat;
vtm1 := pr.vcode1.q3_dat;
vtm2 := pr.vcode2.q3_dat;
end if;
-- Store output in buffer.
v.bufptr := not pr.bufptr;
if pr.bufptr = '1' then
v.dbuf0 := vtm2 & vtm1 & vtm0;
else
v.dbuf1 := vtm2 & vtm1 & vtm0;
end if;
prin <= v;
end process;
-----------------------------------------------------------------------------
-- Combinatorial process for fast signals (TMDS serializer)
-----------------------------------------------------------------------------
fcomb: process (pr, fr) is
variable v: fregs_type;
begin
v := fr;
-- Resynchronize buffer pointer in fast clock domain.
v.bufptr := pr.bufptr & fr.bufptr(1 downto 1);
-- Update shift state.
if fr.shiftstate(0) = '1' then
v.shiftstate := (others => '0');
else
v.shiftstate := "1" & fr.shiftstate(fr.shiftstate'high downto 1);
end if;
-- Update data shift registers.
if fr.shiftstate(0) = '1' then
-- Pick up a new set of 10-bit words once per 5 clock cycles.
if pr.bufptr = '0' then
v.tm0shift := pr.dbuf0(9 downto 0);
v.tm1shift := pr.dbuf0(19 downto 10);
v.tm2shift := pr.dbuf0(29 downto 20);
else
v.tm0shift := pr.dbuf1(9 downto 0);
v.tm1shift := pr.dbuf1(19 downto 10);
v.tm2shift := pr.dbuf1(29 downto 20);
end if;
else
v.tm0shift := "00" & fr.tm0shift(9 downto 2);
v.tm1shift := "00" & fr.tm1shift(9 downto 2);
v.tm2shift := "00" & fr.tm2shift(9 downto 2);
end if;
-- Select 2 output bits per channel per clock cycle.
v.tm0out := fr.tm0shift(1 downto 0);
v.tm1out := fr.tm1shift(1 downto 0);
v.tm2out := fr.tm2shift(1 downto 0);
v.tmcout := fr.shiftstate(2 downto 1);
frin <= v;
end process;
-----------------------------------------------------------------------------
-- Synchronous process in pixel clock domain
-----------------------------------------------------------------------------
pregs: process (vgaclk) is
begin
if rising_edge(vgaclk) then
pr <= prin;
end if;
end process;
-----------------------------------------------------------------------------
-- Synchronous process in fast clock domain
-----------------------------------------------------------------------------
fregs: process (fastclk) is
begin
if rising_edge(fastclk) then
fr <= frin;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- vga2tmds.vhd
-- Joris van Rantwijk
--
-- This entity takes VGA signals as input (in the form of 8-bit RGB words
-- and HSYNC/VSYNC signals) and produces TMDS signals as output.
--
-- The input side of this entity may be connected to SVGACTRL or APBVGA
-- components from GRLIB. The output side of this entity may be connected
-- to a TMDS transmitter for a HDMI or DVI output port.
--
-- The output operates in DVI mode: no guard bands and no data islands
-- are sent. This is actually not allowed on HDMI links, but HDMI devices
-- should just accept it in DVI-compatibility mode.
--
------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library unisim;
use unisim.vcomponents.ODDR2;
entity vga2tmds is
generic (
tech : integer := 0
);
port (
-- VGA pixel clock.
vgaclk : in std_logic;
-- Fast clock at 5 times pixel clock frequency.
fastclk : in std_logic;
-- Output signals from APBVGA or SVGACTRL.
vgao : in apbvga_out_type;
-- TMDS output signals.
tmdsclk : out std_logic;
tmdsdat : out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of vga2tmds is
-- registers in video coding pipeline
type video_coder_regs is record
q0_dat : std_logic_vector(8 downto 0); -- stage 0: partial XOR
q1_dat : std_logic_vector(8 downto 0); -- stage 1: transition minimized
q2_dat : std_logic_vector(8 downto 0); -- stage 2: transition minimized
q2_nd : signed(3 downto 0); -- stage 2: (N1 - N0) / 2
q3_dat : std_logic_vector(9 downto 0); -- stage 3: final output
q3_cnt : signed(3 downto 0); -- stage 3: DC counter
end record;
-- registers in pixel clock domain
type pregs_type is record
blank : std_logic_vector(3 downto 0); -- pipeline for blanking signal
vcode0 : video_coder_regs; -- coding pipeline for ch0
vcode1 : video_coder_regs; -- coding pipeline for ch1
vcode2 : video_coder_regs; -- coding pipeline for ch2
bufptr : std_ulogic; -- current buffer slot
dbuf0 : std_logic_vector(29 downto 0); -- 2-slot output buffer
dbuf1 : std_logic_vector(29 downto 0);
end record;
-- registers in fast clock domain
type fregs_type is record
bufptr : std_logic_vector(1 downto 0); -- resynced bufptr
shiftstate : std_logic_vector(3 downto 0); -- one-hot state
tm0shift : std_logic_vector(9 downto 0); -- output shift registers
tm1shift : std_logic_vector(9 downto 0);
tm2shift : std_logic_vector(9 downto 0);
tm0out : std_logic_vector(1 downto 0); -- DDR output registers
tm1out : std_logic_vector(1 downto 0);
tm2out : std_logic_vector(1 downto 0);
tmcout : std_logic_vector(1 downto 0);
end record;
-- reset values
constant video_coder_regs_reset: video_coder_regs := (
q0_dat => (others => '0'),
q1_dat => (others => '0'),
q2_dat => (others => '0'),
q2_nd => (others => '0'),
q3_dat => (others => '0'),
q3_cnt => (others => '0') );
constant pregs_reset: pregs_type := (
blank => (others => '0'),
vcode0 => video_coder_regs_reset,
vcode1 => video_coder_regs_reset,
vcode2 => video_coder_regs_reset,
bufptr => '0',
dbuf0 => (others => '0'),
dbuf1 => (others => '0') );
-- registers in pixel clock domain
signal pr : pregs_type := pregs_reset;
signal prin : pregs_type;
-- registers in fast clock domain
signal fr, frin : fregs_type;
signal vcc, gnd: std_ulogic;
signal fastclk_n: std_ulogic;
-- Control Period Coding
constant tmds_ctrl_code_00: std_logic_vector(9 downto 0) := "1101010100";
constant tmds_ctrl_code_01: std_logic_vector(9 downto 0) := "0010101011";
constant tmds_ctrl_code_10: std_logic_vector(9 downto 0) := "0101010100";
constant tmds_ctrl_code_11: std_logic_vector(9 downto 0) := "1010101011";
-----------------------------------------------------------------------------
-- Video Coding pipeline
-----------------------------------------------------------------------------
function count_bits(d: in std_logic_vector; n: in integer)
return unsigned is
variable y: unsigned(n-1 downto 0);
begin
y := to_unsigned(0, n);
for i in d'range loop
if d(i) = '1' then
y := y + 1;
end if;
end loop;
return y;
end function;
procedure tmds_video_coder(din: in std_logic_vector(7 downto 0);
clrn: in std_ulogic;
regs: in video_coder_regs;
vregs: out video_coder_regs ) is
variable v_cnt_din: unsigned(2 downto 0);
begin
-- stage 1: XOR first 5 bits and choose between XOR/XNOR coding
vregs.q0_dat(0) := din(0);
vregs.q0_dat(1) := din(0) xor din(1);
vregs.q0_dat(2) := din(0) xor din(1) xor din(2);
vregs.q0_dat(3) := din(0) xor din(1) xor din(2) xor din(3);
vregs.q0_dat(4) := din(0) xor din(1) xor din(2) xor din(3) xor din(4);
vregs.q0_dat(7 downto 5) := din(7 downto 5);
v_cnt_din := count_bits(din(7 downto 1), 3);
if v_cnt_din > 3 then
vregs.q0_dat(8) := '0';
else
vregs.q0_dat(8) := '1';
end if;
-- stage 2: XOR last 3 bits and apply XNOR if needed
vregs.q1_dat(0) := regs.q0_dat(0);
vregs.q1_dat(1) := regs.q0_dat(1) xor regs.q0_dat(8) xor '1';
vregs.q1_dat(2) := regs.q0_dat(2);
vregs.q1_dat(3) := regs.q0_dat(3) xor regs.q0_dat(0) xor '1';
vregs.q1_dat(4) := regs.q0_dat(4);
vregs.q1_dat(5) := regs.q0_dat(4) xor regs.q0_dat(5) xor regs.q0_dat(8) xor '1';
vregs.q1_dat(6) := regs.q0_dat(4) xor regs.q0_dat(5) xor regs.q0_dat(6);
vregs.q1_dat(7) := regs.q0_dat(4) xor regs.q0_dat(5) xor regs.q0_dat(6) xor regs.q0_dat(7) xor regs.q0_dat(8) xor '1';
vregs.q1_dat(8) := regs.q0_dat(8);
-- stage 3: count difference between nr of 1 and 0 bits (divided by 2)
vregs.q2_dat := regs.q1_dat;
vregs.q2_nd := signed(count_bits(regs.q1_dat(7 downto 0), 4)) - 4;
-- stage 4: DC balance
if (regs.q3_cnt < 0 and regs.q2_nd < 0) or
((regs.q3_cnt = 0 or regs.q2_nd = 0) and (regs.q2_dat(8) = '0')) then
-- flip bits
vregs.q3_dat(7 downto 0) := not regs.q2_dat(7 downto 0);
vregs.q3_dat(8) := regs.q2_dat(8);
vregs.q3_dat(9) := '1';
if regs.q2_dat(8) = '1' then
vregs.q3_cnt := regs.q3_cnt - regs.q2_nd + 1;
else
vregs.q3_cnt := regs.q3_cnt - regs.q2_nd;
end if;
else
-- keep bits
vregs.q3_dat(7 downto 0) := regs.q2_dat(7 downto 0);
vregs.q3_dat(8) := regs.q2_dat(8);
vregs.q3_dat(9) := '0';
if regs.q2_dat(8) = '1' then
vregs.q3_cnt := regs.q3_cnt + regs.q2_nd;
else
vregs.q3_cnt := regs.q3_cnt + regs.q2_nd - 1;
end if;
end if;
-- reset DC counter
if clrn = '0' then
vregs.q3_cnt := "0000";
end if;
end procedure;
begin
vcc <= '1'; gnd <= '0';
fastclk_n <= not fastclk;
-----------------------------------------------------------------------------
-- DDR output registers
-----------------------------------------------------------------------------
-- It would of course be nicer to do this with ddr_oreg from techmap,
-- but it can not handle the rising -> falling data path fast enough.
ddr0: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsdat(0), C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tm0out(0), D1 => fr.tm0out(1), R => gnd, S => gnd );
ddr1: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsdat(1), C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tm1out(0), D1 => fr.tm1out(1), R => gnd, S => gnd );
ddr2: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsdat(2), C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tm2out(0), D1 => fr.tm2out(1), R => gnd, S => gnd );
ddrc: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsclk, C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tmcout(0), D1 => fr.tmcout(1), R => gnd, S => gnd );
-----------------------------------------------------------------------------
-- Combinatorial process for slow signals (TMDS encoder)
-----------------------------------------------------------------------------
pcomb: process (pr, vgao) is
variable v: pregs_type;
variable vtm0: std_logic_vector(9 downto 0);
variable vtm1: std_logic_vector(9 downto 0);
variable vtm2: std_logic_vector(9 downto 0);
begin
v := pr;
-- Video Data Coding pipeline.
v.blank := pr.blank(2 downto 0) & vgao.blank;
tmds_video_coder(vgao.video_out_b, pr.blank(2), pr.vcode0, v.vcode0);
tmds_video_coder(vgao.video_out_g, pr.blank(2), pr.vcode1, v.vcode1);
tmds_video_coder(vgao.video_out_r, pr.blank(2), pr.vcode2, v.vcode2);
if pr.blank(3) = '0' then
-- Display blanking; use Control Period Coding.
-- Send D0=HSYNC and D1=VSYNC via channel 0.
if vgao.vsync = '0' and vgao.hsync = '0' then
vtm0 := tmds_ctrl_code_00;
elsif vgao.vsync = '0' and vgao.hsync = '1' then
vtm0 := tmds_ctrl_code_01;
elsif vgao.vsync = '1' and vgao.hsync = '0' then
vtm0 := tmds_ctrl_code_10;
else
vtm0 := tmds_ctrl_code_11;
end if;
-- Send Video Data Preamble via channels 1 and 2.
vtm1 := tmds_ctrl_code_01;
vtm2 := tmds_ctrl_code_00;
else
-- Send Video Data; use 24-bit RGB pixel encoding.
vtm0 := pr.vcode0.q3_dat;
vtm1 := pr.vcode1.q3_dat;
vtm2 := pr.vcode2.q3_dat;
end if;
-- Store output in buffer.
v.bufptr := not pr.bufptr;
if pr.bufptr = '1' then
v.dbuf0 := vtm2 & vtm1 & vtm0;
else
v.dbuf1 := vtm2 & vtm1 & vtm0;
end if;
prin <= v;
end process;
-----------------------------------------------------------------------------
-- Combinatorial process for fast signals (TMDS serializer)
-----------------------------------------------------------------------------
fcomb: process (pr, fr) is
variable v: fregs_type;
begin
v := fr;
-- Resynchronize buffer pointer in fast clock domain.
v.bufptr := pr.bufptr & fr.bufptr(1 downto 1);
-- Update shift state.
if fr.shiftstate(0) = '1' then
v.shiftstate := (others => '0');
else
v.shiftstate := "1" & fr.shiftstate(fr.shiftstate'high downto 1);
end if;
-- Update data shift registers.
if fr.shiftstate(0) = '1' then
-- Pick up a new set of 10-bit words once per 5 clock cycles.
if pr.bufptr = '0' then
v.tm0shift := pr.dbuf0(9 downto 0);
v.tm1shift := pr.dbuf0(19 downto 10);
v.tm2shift := pr.dbuf0(29 downto 20);
else
v.tm0shift := pr.dbuf1(9 downto 0);
v.tm1shift := pr.dbuf1(19 downto 10);
v.tm2shift := pr.dbuf1(29 downto 20);
end if;
else
v.tm0shift := "00" & fr.tm0shift(9 downto 2);
v.tm1shift := "00" & fr.tm1shift(9 downto 2);
v.tm2shift := "00" & fr.tm2shift(9 downto 2);
end if;
-- Select 2 output bits per channel per clock cycle.
v.tm0out := fr.tm0shift(1 downto 0);
v.tm1out := fr.tm1shift(1 downto 0);
v.tm2out := fr.tm2shift(1 downto 0);
v.tmcout := fr.shiftstate(2 downto 1);
frin <= v;
end process;
-----------------------------------------------------------------------------
-- Synchronous process in pixel clock domain
-----------------------------------------------------------------------------
pregs: process (vgaclk) is
begin
if rising_edge(vgaclk) then
pr <= prin;
end if;
end process;
-----------------------------------------------------------------------------
-- Synchronous process in fast clock domain
-----------------------------------------------------------------------------
fregs: process (fastclk) is
begin
if rising_edge(fastclk) then
fr <= frin;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- vga2tmds.vhd
-- Joris van Rantwijk
--
-- This entity takes VGA signals as input (in the form of 8-bit RGB words
-- and HSYNC/VSYNC signals) and produces TMDS signals as output.
--
-- The input side of this entity may be connected to SVGACTRL or APBVGA
-- components from GRLIB. The output side of this entity may be connected
-- to a TMDS transmitter for a HDMI or DVI output port.
--
-- The output operates in DVI mode: no guard bands and no data islands
-- are sent. This is actually not allowed on HDMI links, but HDMI devices
-- should just accept it in DVI-compatibility mode.
--
------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library unisim;
use unisim.vcomponents.ODDR2;
entity vga2tmds is
generic (
tech : integer := 0
);
port (
-- VGA pixel clock.
vgaclk : in std_logic;
-- Fast clock at 5 times pixel clock frequency.
fastclk : in std_logic;
-- Output signals from APBVGA or SVGACTRL.
vgao : in apbvga_out_type;
-- TMDS output signals.
tmdsclk : out std_logic;
tmdsdat : out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of vga2tmds is
-- registers in video coding pipeline
type video_coder_regs is record
q0_dat : std_logic_vector(8 downto 0); -- stage 0: partial XOR
q1_dat : std_logic_vector(8 downto 0); -- stage 1: transition minimized
q2_dat : std_logic_vector(8 downto 0); -- stage 2: transition minimized
q2_nd : signed(3 downto 0); -- stage 2: (N1 - N0) / 2
q3_dat : std_logic_vector(9 downto 0); -- stage 3: final output
q3_cnt : signed(3 downto 0); -- stage 3: DC counter
end record;
-- registers in pixel clock domain
type pregs_type is record
blank : std_logic_vector(3 downto 0); -- pipeline for blanking signal
vcode0 : video_coder_regs; -- coding pipeline for ch0
vcode1 : video_coder_regs; -- coding pipeline for ch1
vcode2 : video_coder_regs; -- coding pipeline for ch2
bufptr : std_ulogic; -- current buffer slot
dbuf0 : std_logic_vector(29 downto 0); -- 2-slot output buffer
dbuf1 : std_logic_vector(29 downto 0);
end record;
-- registers in fast clock domain
type fregs_type is record
bufptr : std_logic_vector(1 downto 0); -- resynced bufptr
shiftstate : std_logic_vector(3 downto 0); -- one-hot state
tm0shift : std_logic_vector(9 downto 0); -- output shift registers
tm1shift : std_logic_vector(9 downto 0);
tm2shift : std_logic_vector(9 downto 0);
tm0out : std_logic_vector(1 downto 0); -- DDR output registers
tm1out : std_logic_vector(1 downto 0);
tm2out : std_logic_vector(1 downto 0);
tmcout : std_logic_vector(1 downto 0);
end record;
-- reset values
constant video_coder_regs_reset: video_coder_regs := (
q0_dat => (others => '0'),
q1_dat => (others => '0'),
q2_dat => (others => '0'),
q2_nd => (others => '0'),
q3_dat => (others => '0'),
q3_cnt => (others => '0') );
constant pregs_reset: pregs_type := (
blank => (others => '0'),
vcode0 => video_coder_regs_reset,
vcode1 => video_coder_regs_reset,
vcode2 => video_coder_regs_reset,
bufptr => '0',
dbuf0 => (others => '0'),
dbuf1 => (others => '0') );
-- registers in pixel clock domain
signal pr : pregs_type := pregs_reset;
signal prin : pregs_type;
-- registers in fast clock domain
signal fr, frin : fregs_type;
signal vcc, gnd: std_ulogic;
signal fastclk_n: std_ulogic;
-- Control Period Coding
constant tmds_ctrl_code_00: std_logic_vector(9 downto 0) := "1101010100";
constant tmds_ctrl_code_01: std_logic_vector(9 downto 0) := "0010101011";
constant tmds_ctrl_code_10: std_logic_vector(9 downto 0) := "0101010100";
constant tmds_ctrl_code_11: std_logic_vector(9 downto 0) := "1010101011";
-----------------------------------------------------------------------------
-- Video Coding pipeline
-----------------------------------------------------------------------------
function count_bits(d: in std_logic_vector; n: in integer)
return unsigned is
variable y: unsigned(n-1 downto 0);
begin
y := to_unsigned(0, n);
for i in d'range loop
if d(i) = '1' then
y := y + 1;
end if;
end loop;
return y;
end function;
procedure tmds_video_coder(din: in std_logic_vector(7 downto 0);
clrn: in std_ulogic;
regs: in video_coder_regs;
vregs: out video_coder_regs ) is
variable v_cnt_din: unsigned(2 downto 0);
begin
-- stage 1: XOR first 5 bits and choose between XOR/XNOR coding
vregs.q0_dat(0) := din(0);
vregs.q0_dat(1) := din(0) xor din(1);
vregs.q0_dat(2) := din(0) xor din(1) xor din(2);
vregs.q0_dat(3) := din(0) xor din(1) xor din(2) xor din(3);
vregs.q0_dat(4) := din(0) xor din(1) xor din(2) xor din(3) xor din(4);
vregs.q0_dat(7 downto 5) := din(7 downto 5);
v_cnt_din := count_bits(din(7 downto 1), 3);
if v_cnt_din > 3 then
vregs.q0_dat(8) := '0';
else
vregs.q0_dat(8) := '1';
end if;
-- stage 2: XOR last 3 bits and apply XNOR if needed
vregs.q1_dat(0) := regs.q0_dat(0);
vregs.q1_dat(1) := regs.q0_dat(1) xor regs.q0_dat(8) xor '1';
vregs.q1_dat(2) := regs.q0_dat(2);
vregs.q1_dat(3) := regs.q0_dat(3) xor regs.q0_dat(0) xor '1';
vregs.q1_dat(4) := regs.q0_dat(4);
vregs.q1_dat(5) := regs.q0_dat(4) xor regs.q0_dat(5) xor regs.q0_dat(8) xor '1';
vregs.q1_dat(6) := regs.q0_dat(4) xor regs.q0_dat(5) xor regs.q0_dat(6);
vregs.q1_dat(7) := regs.q0_dat(4) xor regs.q0_dat(5) xor regs.q0_dat(6) xor regs.q0_dat(7) xor regs.q0_dat(8) xor '1';
vregs.q1_dat(8) := regs.q0_dat(8);
-- stage 3: count difference between nr of 1 and 0 bits (divided by 2)
vregs.q2_dat := regs.q1_dat;
vregs.q2_nd := signed(count_bits(regs.q1_dat(7 downto 0), 4)) - 4;
-- stage 4: DC balance
if (regs.q3_cnt < 0 and regs.q2_nd < 0) or
((regs.q3_cnt = 0 or regs.q2_nd = 0) and (regs.q2_dat(8) = '0')) then
-- flip bits
vregs.q3_dat(7 downto 0) := not regs.q2_dat(7 downto 0);
vregs.q3_dat(8) := regs.q2_dat(8);
vregs.q3_dat(9) := '1';
if regs.q2_dat(8) = '1' then
vregs.q3_cnt := regs.q3_cnt - regs.q2_nd + 1;
else
vregs.q3_cnt := regs.q3_cnt - regs.q2_nd;
end if;
else
-- keep bits
vregs.q3_dat(7 downto 0) := regs.q2_dat(7 downto 0);
vregs.q3_dat(8) := regs.q2_dat(8);
vregs.q3_dat(9) := '0';
if regs.q2_dat(8) = '1' then
vregs.q3_cnt := regs.q3_cnt + regs.q2_nd;
else
vregs.q3_cnt := regs.q3_cnt + regs.q2_nd - 1;
end if;
end if;
-- reset DC counter
if clrn = '0' then
vregs.q3_cnt := "0000";
end if;
end procedure;
begin
vcc <= '1'; gnd <= '0';
fastclk_n <= not fastclk;
-----------------------------------------------------------------------------
-- DDR output registers
-----------------------------------------------------------------------------
-- It would of course be nicer to do this with ddr_oreg from techmap,
-- but it can not handle the rising -> falling data path fast enough.
ddr0: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsdat(0), C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tm0out(0), D1 => fr.tm0out(1), R => gnd, S => gnd );
ddr1: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsdat(1), C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tm1out(0), D1 => fr.tm1out(1), R => gnd, S => gnd );
ddr2: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsdat(2), C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tm2out(0), D1 => fr.tm2out(1), R => gnd, S => gnd );
ddrc: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsclk, C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tmcout(0), D1 => fr.tmcout(1), R => gnd, S => gnd );
-----------------------------------------------------------------------------
-- Combinatorial process for slow signals (TMDS encoder)
-----------------------------------------------------------------------------
pcomb: process (pr, vgao) is
variable v: pregs_type;
variable vtm0: std_logic_vector(9 downto 0);
variable vtm1: std_logic_vector(9 downto 0);
variable vtm2: std_logic_vector(9 downto 0);
begin
v := pr;
-- Video Data Coding pipeline.
v.blank := pr.blank(2 downto 0) & vgao.blank;
tmds_video_coder(vgao.video_out_b, pr.blank(2), pr.vcode0, v.vcode0);
tmds_video_coder(vgao.video_out_g, pr.blank(2), pr.vcode1, v.vcode1);
tmds_video_coder(vgao.video_out_r, pr.blank(2), pr.vcode2, v.vcode2);
if pr.blank(3) = '0' then
-- Display blanking; use Control Period Coding.
-- Send D0=HSYNC and D1=VSYNC via channel 0.
if vgao.vsync = '0' and vgao.hsync = '0' then
vtm0 := tmds_ctrl_code_00;
elsif vgao.vsync = '0' and vgao.hsync = '1' then
vtm0 := tmds_ctrl_code_01;
elsif vgao.vsync = '1' and vgao.hsync = '0' then
vtm0 := tmds_ctrl_code_10;
else
vtm0 := tmds_ctrl_code_11;
end if;
-- Send Video Data Preamble via channels 1 and 2.
vtm1 := tmds_ctrl_code_01;
vtm2 := tmds_ctrl_code_00;
else
-- Send Video Data; use 24-bit RGB pixel encoding.
vtm0 := pr.vcode0.q3_dat;
vtm1 := pr.vcode1.q3_dat;
vtm2 := pr.vcode2.q3_dat;
end if;
-- Store output in buffer.
v.bufptr := not pr.bufptr;
if pr.bufptr = '1' then
v.dbuf0 := vtm2 & vtm1 & vtm0;
else
v.dbuf1 := vtm2 & vtm1 & vtm0;
end if;
prin <= v;
end process;
-----------------------------------------------------------------------------
-- Combinatorial process for fast signals (TMDS serializer)
-----------------------------------------------------------------------------
fcomb: process (pr, fr) is
variable v: fregs_type;
begin
v := fr;
-- Resynchronize buffer pointer in fast clock domain.
v.bufptr := pr.bufptr & fr.bufptr(1 downto 1);
-- Update shift state.
if fr.shiftstate(0) = '1' then
v.shiftstate := (others => '0');
else
v.shiftstate := "1" & fr.shiftstate(fr.shiftstate'high downto 1);
end if;
-- Update data shift registers.
if fr.shiftstate(0) = '1' then
-- Pick up a new set of 10-bit words once per 5 clock cycles.
if pr.bufptr = '0' then
v.tm0shift := pr.dbuf0(9 downto 0);
v.tm1shift := pr.dbuf0(19 downto 10);
v.tm2shift := pr.dbuf0(29 downto 20);
else
v.tm0shift := pr.dbuf1(9 downto 0);
v.tm1shift := pr.dbuf1(19 downto 10);
v.tm2shift := pr.dbuf1(29 downto 20);
end if;
else
v.tm0shift := "00" & fr.tm0shift(9 downto 2);
v.tm1shift := "00" & fr.tm1shift(9 downto 2);
v.tm2shift := "00" & fr.tm2shift(9 downto 2);
end if;
-- Select 2 output bits per channel per clock cycle.
v.tm0out := fr.tm0shift(1 downto 0);
v.tm1out := fr.tm1shift(1 downto 0);
v.tm2out := fr.tm2shift(1 downto 0);
v.tmcout := fr.shiftstate(2 downto 1);
frin <= v;
end process;
-----------------------------------------------------------------------------
-- Synchronous process in pixel clock domain
-----------------------------------------------------------------------------
pregs: process (vgaclk) is
begin
if rising_edge(vgaclk) then
pr <= prin;
end if;
end process;
-----------------------------------------------------------------------------
-- Synchronous process in fast clock domain
-----------------------------------------------------------------------------
fregs: process (fastclk) is
begin
if rising_edge(fastclk) then
fr <= frin;
end if;
end process;
end architecture;
|
-- file: clks.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___133.333______0.000______50.0______230.136____196.077
-- CLK_OUT2___133.333____180.000______50.0______230.136____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clks is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end clks;
architecture xilinx of clks is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clks,clk_wiz_v3_6,{component_name=clks,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 6,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 6,
CLKOUT1_PHASE => 180.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:24:10 10/20/2016
-- Design Name:
-- Module Name: ShiftRegister - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ShiftRegister is
Port ( Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
Enable : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end ShiftRegister;
architecture Behavioral of ShiftRegister is
signal salida : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
begin
Q <= salida;
Registro : process (Clk, Reset, Enable)
begin
if Reset = '0' then
salida <= (others => '0');
elsif Clk'event and Clk = '1' then
if Enable = '1' then
salida (6 downto 0) <= salida (7 downto 1);
salida(7) <= D;
end if;
end if;
end process;
end Behavioral;
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ipl_rom_mf.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ipl_rom_mf IS
PORT
(
address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ipl_rom_mf;
ARCHITECTURE SYN OF ipl_rom_mf IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../../ROMs/loader/loader.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 8192,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 13,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../../ROMs/loader/loader.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../../ROMs/loader/loader.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ipl_rom_mf.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ipl_rom_mf.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ipl_rom_mf.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ipl_rom_mf.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ipl_rom_mf_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_1.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_1_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_1_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_9_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_9_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_1_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_1_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_2_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_2_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_1_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1 IS
-- Signals
SIGNAL twdlXdin_1_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_1_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_9_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_9_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_1_re_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_1_im_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_2_re_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_2_im_tmp : signed(17 DOWNTO 0); -- sfix18
BEGIN
twdlXdin_1_re_signed <= signed(twdlXdin_1_re);
twdlXdin_1_im_signed <= signed(twdlXdin_1_im);
twdlXdin_9_re_signed <= signed(twdlXdin_9_re);
twdlXdin_9_im_signed <= signed(twdlXdin_9_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_1_re_signed,
twdlXdin_1_im_signed, twdlXdin_9_re_signed, twdlXdin_9_im_signed,
twdlXdin_1_vld)
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_1_re_signed, 19) + resize(twdlXdin_9_re_signed, 19);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_1_re_signed, 19) - resize(twdlXdin_9_re_signed, 19);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_1_im_signed, 19) + resize(twdlXdin_9_im_signed, 19);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_1_im_signed, 19) - resize(twdlXdin_9_im_signed, 19);
END IF;
dout_1_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(17 DOWNTO 0);
dout_1_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(17 DOWNTO 0);
dout_2_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(17 DOWNTO 0);
dout_2_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(17 DOWNTO 0);
dout_1_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_1_re <= std_logic_vector(dout_1_re_tmp);
dout_1_im <= std_logic_vector(dout_1_im_tmp);
dout_2_re <= std_logic_vector(dout_2_re_tmp);
dout_2_im <= std_logic_vector(dout_2_im_tmp);
END rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for a flag signal synchronizer
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity sync_Flag_tb is
end;
architecture test of sync_Flag_tb is
constant CLOCK_1_PERIOD : TIME := 10 ns;
constant CLOCK_2_PERIOD : TIME := 17 ns;
constant CLOCK_2_OFFSET : TIME := 2 ps;
signal Clock1 : STD_LOGIC := '1';
signal Clock2_i : STD_LOGIC := '1';
signal Clock2 : STD_LOGIC;
signal Sync_in : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal Sync_out : STD_LOGIC_VECTOR(0 downto 0);
begin
ClockProcess1 : process(Clock1)
begin
Clock1 <= not Clock1 after CLOCK_1_PERIOD / 2;
end process;
ClockProcess2 : process(Clock2_i)
begin
Clock2_i <= not Clock2_i after CLOCK_2_PERIOD / 2;
end process;
Clock2 <= Clock2_i'delayed(CLOCK_2_OFFSET);
process
begin
wait for 4 * CLOCK_1_PERIOD;
wait for 4 * CLOCK_1_PERIOD;
Sync_in <= "X";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 2 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 6 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 16 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 6 * CLOCK_1_PERIOD;
wait;
end process;
syncFlag : entity PoC.sync_Flag
generic map (
BITS => 1, -- number of bit to be synchronized
INIT => "0" --
)
port map (
Clock => Clock2, -- input clock domain
Input => Sync_in, -- input bits
Output => Sync_out -- output bits
);
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for a flag signal synchronizer
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity sync_Flag_tb is
end;
architecture test of sync_Flag_tb is
constant CLOCK_1_PERIOD : TIME := 10 ns;
constant CLOCK_2_PERIOD : TIME := 17 ns;
constant CLOCK_2_OFFSET : TIME := 2 ps;
signal Clock1 : STD_LOGIC := '1';
signal Clock2_i : STD_LOGIC := '1';
signal Clock2 : STD_LOGIC;
signal Sync_in : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal Sync_out : STD_LOGIC_VECTOR(0 downto 0);
begin
ClockProcess1 : process(Clock1)
begin
Clock1 <= not Clock1 after CLOCK_1_PERIOD / 2;
end process;
ClockProcess2 : process(Clock2_i)
begin
Clock2_i <= not Clock2_i after CLOCK_2_PERIOD / 2;
end process;
Clock2 <= Clock2_i'delayed(CLOCK_2_OFFSET);
process
begin
wait for 4 * CLOCK_1_PERIOD;
wait for 4 * CLOCK_1_PERIOD;
Sync_in <= "X";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 2 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 6 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 16 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 6 * CLOCK_1_PERIOD;
wait;
end process;
syncFlag : entity PoC.sync_Flag
generic map (
BITS => 1, -- number of bit to be synchronized
INIT => "0" --
)
port map (
Clock => Clock2, -- input clock domain
Input => Sync_in, -- input bits
Output => Sync_out -- output bits
);
end;
|
----------------------------------------------------------------------------------
-- Thibault Bailly
--
-- create date: 07-03-2017
-- design name:
-- module name: generic_Resync
-- description: Generic Resync
--
-- dependencies:
--
-- revision: Initial release
--
-- additional comments:
--
--
--
-- parameters :
--
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Libraries --
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.all;
----------------------------------------------------------------------------------
-- Entity --
----------------------------------------------------------------------------------
entity generic_Resync is
generic(
Number_of_flip_flop_g : natural := 2;
Input_width_g : natural := 1
);
port(
------globally routed signals-------
Clk : in std_logic;
Reset_n : in std_logic;
-------input data---------------
Input : in std_logic_vector ( (Input_width_g-1) downto 0) ;
Output : out std_logic_vector ( (Input_width_g-1) downto 0)
);
end generic_Resync;
----------------------------------------------------------------------------------
-- Architecture --
----------------------------------------------------------------------------------
architecture arch_generic_Resync of generic_Resync is
component generic_Flip_Flop is
generic(
data_width_g : natural := 8 -- Width of the Flip-Flop bus
);
port(
---- Global Inputs
Clk : in std_logic; -- main clock
Reset_n : in std_logic; -- reset synchrone, enable on LOW level
---- Inputs
Locked : in std_logic; -- lock the Flip-Flop, the Load is disable
Load : in std_logic; -- Load the input
Input_Data : in std_logic_vector ( (data_width_g-1) downto 0); --Input of the Flip-Flop
---- Outputs
Output_Data : out std_logic_vector ( (data_width_g-1) downto 0) -- Outputs of the Flip-Flop
);
end component generic_Flip_Flop;
type Output_array_type is array (natural range 0 to (Number_of_flip_flop_g-1) ) of std_logic_vector( (Input_width_g-1) downto 0);
signal Output_array : Output_array_type;
begin
-- Display generic
assert false
report "**** Generic report for generic_Resync : Number_of_flip_flop_g = " &natural'image(Number_of_flip_flop_g)
severity note;
assert false
report "**** Generic report for generic_Resync : Input_width_g = " &natural'image(Input_width_g)
severity note;
--check generic
assert (Number_of_flip_flop_g > 0)
report "-- generic_Memory.vhd : Number_of_flip_flop_g is less than 1 -- "
severity failure;
assert (Input_width_g > 0)
report "-- generic_Memory.vhd : Input_width_g is negative or egal to 0 -- "
severity failure;
-- First Flip-Flop
generic_Flip_Flop_0 : component generic_Flip_Flop
generic map(
data_width_g => Input_width_g -- Width of the Flip-Flop bus
)
port map(
---- Global Inputs
Clk => Clk, -- main clock
Reset_n => Reset_n, -- reset synchrone, enable on LOW level
---- Inputs
Locked => '0', -- lock the Flip-Flop, the Load is disable
Load => '1', -- Load the input
Input_Data => Input, --Input of the Flip-Flop
---- Outputs
Output_Data => Output_array(0) -- Outputs of the Flip-Flop
);
-- generate N Flip-Flop
flip_flop_generate : for I in 1 to (Number_of_flip_flop_g-1) generate
begin
generic_Flip_Flop_i : generic_Flip_Flop
generic map(
data_width_g => Input_width_g -- Width of the Flip-Flop bus
)
port map(
---- Global Inputs
Clk => Clk, -- main clock
Reset_n => Reset_n, -- reset synchrone, enable on LOW level
---- Inputs
Locked => '0', -- lock the Flip-Flop, the Load is disable
Load => '1', -- Load the input
Input_Data => Output_array(I-1), --Input of the Flip-Flop
---- Outputs
Output_Data => Output_array(I) -- Outputs of the Flip-Flop
);
end generate flip_flop_generate;
-- Forwading output
Output <= Output_array(Number_of_flip_flop_g-1);
end arch_generic_Resync;
----------------------------------------------------------------------------------
-- End --
---------------------------------------------------------------------------------- |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity faultify_simulator is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end faultify_simulator;
-- 866:0
architecture behav of faultify_simulator is
component faultify_binomial_gen
generic (
width : integer);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end component;
component circuit_under_test
port (
clk : in std_logic;
rst : in std_logic;
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector : out std_logic_vector(numOut-1 downto 0);
injectionvector : in std_logic_vector(621-1 downto 0));
end component;
component golden_circuit
port (
clk : in std_logic;
rst : in std_logic;
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector : out std_logic_vector(numOut-1 downto 0));
end component;
signal injectionvector : std_logic_vector(numInj-1 downto 0);
signal injectionvector_reg : std_logic_vector(numInj-1 downto 0);
signal injectionvector_reg_o : std_logic_vector(numInj-1 downto 0);
signal seed_chain : std_logic_vector(numInj downto 0);
signal prob_chain : std_logic_vector(numInj downto 0);
signal rst : std_logic;
signal clk_ce_m : std_logic;
signal testvector_reg : std_logic_vector(numIn-1 downto 0);
attribute syn_noprune : boolean;
attribute syn_noprune of circuit_under_test_inst : label is true;
attribute syn_noprune of golden_circuit_inst : label is true;
attribute xc_props : string;
attribute xc_props of circuit_under_test_inst : label is "KEEP_HIERARCHY=TRUE";
attribute xc_props of golden_circuit_inst : label is "KEEP_HIERARCHY=TRUE";
signal inj_vec_total : std_logic_vector(621-1 downto 0);
begin -- behav
rst <= not rst_n;
-----------------------------------------------------------------------------
-- debug...
-----------------------------------------------------------------------------
-- resultvector_f <= (others => '1');
-- resultvector_o <= (others => '1');
cgate : bufgce
port map (
I => clk_m,
O => clk_ce_m,
CE => circ_ce);
process (clk_ce_m, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
testvector_reg <= (others => '0');
elsif clk_ce_m'event and clk_ce_m = '1' then -- rising clock edge
testvector_reg <= testvector;
end if;
end process;
circuit_under_test_inst : circuit_under_test
port map (
clk => clk_ce_m,
rst => circ_rst,
testvector => testvector_reg,
resultvector => resultvector_f,
injectionvector => inj_vec_total);
inj_vec_total(299 downto 0) <= (others => '0');
inj_vec_total(621-1 downto 300) <= injectionvector_reg;
golden_circuit_inst : golden_circuit
port map (
clk => clk_ce_m,
rst => circ_rst,
testvector => testvector_reg,
resultvector => resultvector_o
);
seed_chain(0) <= seed_in;
prob_chain(0) <= prob_in;
prsn_loop : for i in 0 to numInj-1 generate
prsn_top_1 : faultify_binomial_gen
generic map (
width => 32)
port map (
clk => clk,
rst_n => rst_n,
seed_in_en => seed_in_en,
seed_in => seed_chain(i),
seed_out_c => seed_chain(i+1),
prob_in_en => prob_in_en,
prob_in => prob_chain(i),
prob_out_c => prob_chain(i+1),
shift_en => shift_en,
data_out => injectionvector(i),
data_out_valid => open);
end generate prsn_loop;
reg : process (clk_ce_m, rst_n)
begin -- process reg
if rst_n = '0' then -- asynchronous reset (active low)
injectionvector_reg <= (others => '0');
--injectionvector_reg_o <= (others => '0');
--test <= (others => '0');
elsif clk_ce_m'event and clk_ce_m = '1' then -- rising clock edge
injectionvector_reg <= injectionvector;
--injectionvector_reg <= (others => '0');
--test <= injectionvector_reg_o(31 downto 0);
--injectionvector_reg_o(31 downto 0) <= injectionvector_reg_o(31 downto 0) or (resultvector_f(31 downto 0) xor resultvector_o(31 downto 0));
end if;
end process reg;
end behav;
|
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB)
-- 0x10000000 - 0x100fffff External RAM (1MB)
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been instantiated!
-- * some changes has been applied to the ports of the CPU to facilitate the new NI!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 0;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector(3 downto 0);
signal ram_address, ram_address_late : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r, ram_data_r_ni : std_logic_vector(31 downto 0);
signal NI_irq_out : std_logic;
--signal NI_read_flag : std_logic;
--signal NI_write_flag : std_logic;
signal cache_access : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
constant reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
constant reserved_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000";
constant reserved_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
cache_miss or --Cache wait
(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
opt_cache: if use_cache = '0' generate
cache_access <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
cache_access => cache_access, --access 4KB cache
cache_checking => cache_checking, --checking if cache hit
cache_miss => cache_miss); --cache miss
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, ram_address_late, ram_data_r_ni,
data_read, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w)
begin
case cpu_address(30 downto 28) is
when "000" => --internal RAM
if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address)
or (ram_address_late = reserved_counter_address)) then
cpu_data_r <= ram_data_r_ni;
else
cpu_data_r <= ram_data_r;
end if;
when "001" => --external RAM
if cache_checking = '1' then
--cpu_data_r <= ram_data_r; --cache
if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address)
or (ram_address_late = reserved_counter_address)) then
cpu_data_r <= ram_data_r_ni;
else
cpu_data_r <= ram_data_r; --cache
end if;
else
cpu_data_r <= data_read; --DDR
end if;
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others =>
cpu_data_r <= gpioA_in;
end case;
when "011" => --flash
cpu_data_r <= data_read;
when others =>
cpu_data_r <= ZERO;
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
counter_reg <= bv_inc(counter_reg);
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
elsif cpu_address(6 downto 4) = "110" then
counter_reg <= cpu_data_w;
end if;
end if;
end if;
end if;
end process;
process(ram_address, reset, clk)begin
if reset = '1' then
ram_address_late <= (others => '0');
elsif clk'event and clk = '1' then
ram_address_late <= ram_address;
end if;
end process;
ram_proc: process(cache_access, cache_miss,
address_next, cpu_address,
byte_we_next, cpu_data_w, data_read)
begin
if cache_access = '1' then --Check if cache hit or write through
ram_enable <= '1';
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & address_next(11 downto 2);
ram_data_w <= cpu_data_w;
elsif cache_miss = '1' then --Update cache after cache miss
ram_enable <= '1';
ram_byte_we <= "1111";
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & cpu_address(11 downto 2);
ram_data_w <= data_read;
else --Normal non-cache access
if address_next(30 downto 28) = "000" then
ram_enable <= '1';
else
ram_enable <= '0';
end if;
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= address_next(31 downto 2);
ram_data_w <= cpu_data_w;
end if;
end process;
u2_ram: ram
generic map (memory_type => memory_type, stim_file => stim_file)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r);
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail);
dma_gen: if ethernet = '0' generate
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
irq_eth_send <= '0';
end generate;
dma_gen2: if ethernet = '1' generate
u4_eth: eth_dma
port map(
clk => clk,
reset => reset,
enable_eth => gpio0_reg(24),
select_eth => enable_eth,
rec_isr => irq_eth_rec,
send_isr => irq_eth_send,
address => address, --to DDR
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
pause_in => eth_pause_in,
mem_address => cpu_address(31 downto 2), --from CPU
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause,
E_RX_CLK => gpioA_in(20),
E_RX_DV => gpioA_in(19),
E_RXD => gpioA_in(18 downto 15),
E_TX_CLK => gpioA_in(14),
E_TX_EN => gpio0_out(28),
E_TXD => gpio0_out(27 downto 24));
end generate;
u4_ni: NI
generic map(current_address => current_address, SHMU_address => 0)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r_ni,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
irq_out => NI_irq_out,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX,
link_faults => link_faults,
turn_faults => turn_faults,
Rxy_reconf_PE => Rxy_reconf_PE,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command
);
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB)
-- 0x10000000 - 0x100fffff External RAM (1MB)
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been instantiated!
-- * some changes has been applied to the ports of the CPU to facilitate the new NI!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 0;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector(3 downto 0);
signal ram_address, ram_address_late : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r, ram_data_r_ni : std_logic_vector(31 downto 0);
signal NI_irq_out : std_logic;
--signal NI_read_flag : std_logic;
--signal NI_write_flag : std_logic;
signal cache_access : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
constant reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
constant reserved_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000";
constant reserved_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
cache_miss or --Cache wait
(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
opt_cache: if use_cache = '0' generate
cache_access <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
cache_access => cache_access, --access 4KB cache
cache_checking => cache_checking, --checking if cache hit
cache_miss => cache_miss); --cache miss
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, ram_address_late, ram_data_r_ni,
data_read, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w)
begin
case cpu_address(30 downto 28) is
when "000" => --internal RAM
if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address)
or (ram_address_late = reserved_counter_address)) then
cpu_data_r <= ram_data_r_ni;
else
cpu_data_r <= ram_data_r;
end if;
when "001" => --external RAM
if cache_checking = '1' then
--cpu_data_r <= ram_data_r; --cache
if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address)
or (ram_address_late = reserved_counter_address)) then
cpu_data_r <= ram_data_r_ni;
else
cpu_data_r <= ram_data_r; --cache
end if;
else
cpu_data_r <= data_read; --DDR
end if;
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others =>
cpu_data_r <= gpioA_in;
end case;
when "011" => --flash
cpu_data_r <= data_read;
when others =>
cpu_data_r <= ZERO;
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
counter_reg <= bv_inc(counter_reg);
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
elsif cpu_address(6 downto 4) = "110" then
counter_reg <= cpu_data_w;
end if;
end if;
end if;
end if;
end process;
process(ram_address, reset, clk)begin
if reset = '1' then
ram_address_late <= (others => '0');
elsif clk'event and clk = '1' then
ram_address_late <= ram_address;
end if;
end process;
ram_proc: process(cache_access, cache_miss,
address_next, cpu_address,
byte_we_next, cpu_data_w, data_read)
begin
if cache_access = '1' then --Check if cache hit or write through
ram_enable <= '1';
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & address_next(11 downto 2);
ram_data_w <= cpu_data_w;
elsif cache_miss = '1' then --Update cache after cache miss
ram_enable <= '1';
ram_byte_we <= "1111";
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & cpu_address(11 downto 2);
ram_data_w <= data_read;
else --Normal non-cache access
if address_next(30 downto 28) = "000" then
ram_enable <= '1';
else
ram_enable <= '0';
end if;
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= address_next(31 downto 2);
ram_data_w <= cpu_data_w;
end if;
end process;
u2_ram: ram
generic map (memory_type => memory_type, stim_file => stim_file)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r);
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail);
dma_gen: if ethernet = '0' generate
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
irq_eth_send <= '0';
end generate;
dma_gen2: if ethernet = '1' generate
u4_eth: eth_dma
port map(
clk => clk,
reset => reset,
enable_eth => gpio0_reg(24),
select_eth => enable_eth,
rec_isr => irq_eth_rec,
send_isr => irq_eth_send,
address => address, --to DDR
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
pause_in => eth_pause_in,
mem_address => cpu_address(31 downto 2), --from CPU
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause,
E_RX_CLK => gpioA_in(20),
E_RX_DV => gpioA_in(19),
E_RXD => gpioA_in(18 downto 15),
E_TX_CLK => gpioA_in(14),
E_TX_EN => gpio0_out(28),
E_TXD => gpio0_out(27 downto 24));
end generate;
u4_ni: NI
generic map(current_address => current_address, SHMU_address => 0)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r_ni,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
irq_out => NI_irq_out,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX,
link_faults => link_faults,
turn_faults => turn_faults,
Rxy_reconf_PE => Rxy_reconf_PE,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command
);
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB)
-- 0x10000000 - 0x100fffff External RAM (1MB)
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been instantiated!
-- * some changes has been applied to the ports of the CPU to facilitate the new NI!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 0;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector(3 downto 0);
signal ram_address, ram_address_late : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r, ram_data_r_ni : std_logic_vector(31 downto 0);
signal NI_irq_out : std_logic;
--signal NI_read_flag : std_logic;
--signal NI_write_flag : std_logic;
signal cache_access : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
constant reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
constant reserved_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000";
constant reserved_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
cache_miss or --Cache wait
(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
opt_cache: if use_cache = '0' generate
cache_access <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
cache_access => cache_access, --access 4KB cache
cache_checking => cache_checking, --checking if cache hit
cache_miss => cache_miss); --cache miss
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, ram_address_late, ram_data_r_ni,
data_read, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w)
begin
case cpu_address(30 downto 28) is
when "000" => --internal RAM
if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address)
or (ram_address_late = reserved_counter_address)) then
cpu_data_r <= ram_data_r_ni;
else
cpu_data_r <= ram_data_r;
end if;
when "001" => --external RAM
if cache_checking = '1' then
--cpu_data_r <= ram_data_r; --cache
if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address)
or (ram_address_late = reserved_counter_address)) then
cpu_data_r <= ram_data_r_ni;
else
cpu_data_r <= ram_data_r; --cache
end if;
else
cpu_data_r <= data_read; --DDR
end if;
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others =>
cpu_data_r <= gpioA_in;
end case;
when "011" => --flash
cpu_data_r <= data_read;
when others =>
cpu_data_r <= ZERO;
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
counter_reg <= bv_inc(counter_reg);
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
elsif cpu_address(6 downto 4) = "110" then
counter_reg <= cpu_data_w;
end if;
end if;
end if;
end if;
end process;
process(ram_address, reset, clk)begin
if reset = '1' then
ram_address_late <= (others => '0');
elsif clk'event and clk = '1' then
ram_address_late <= ram_address;
end if;
end process;
ram_proc: process(cache_access, cache_miss,
address_next, cpu_address,
byte_we_next, cpu_data_w, data_read)
begin
if cache_access = '1' then --Check if cache hit or write through
ram_enable <= '1';
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & address_next(11 downto 2);
ram_data_w <= cpu_data_w;
elsif cache_miss = '1' then --Update cache after cache miss
ram_enable <= '1';
ram_byte_we <= "1111";
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & cpu_address(11 downto 2);
ram_data_w <= data_read;
else --Normal non-cache access
if address_next(30 downto 28) = "000" then
ram_enable <= '1';
else
ram_enable <= '0';
end if;
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= address_next(31 downto 2);
ram_data_w <= cpu_data_w;
end if;
end process;
u2_ram: ram
generic map (memory_type => memory_type, stim_file => stim_file)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r);
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail);
dma_gen: if ethernet = '0' generate
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
irq_eth_send <= '0';
end generate;
dma_gen2: if ethernet = '1' generate
u4_eth: eth_dma
port map(
clk => clk,
reset => reset,
enable_eth => gpio0_reg(24),
select_eth => enable_eth,
rec_isr => irq_eth_rec,
send_isr => irq_eth_send,
address => address, --to DDR
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
pause_in => eth_pause_in,
mem_address => cpu_address(31 downto 2), --from CPU
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause,
E_RX_CLK => gpioA_in(20),
E_RX_DV => gpioA_in(19),
E_RXD => gpioA_in(18 downto 15),
E_TX_CLK => gpioA_in(14),
E_TX_EN => gpio0_out(28),
E_TXD => gpio0_out(27 downto 24));
end generate;
u4_ni: NI
generic map(current_address => current_address, SHMU_address => 0)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r_ni,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
irq_out => NI_irq_out,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX,
link_faults => link_faults,
turn_faults => turn_faults,
Rxy_reconf_PE => Rxy_reconf_PE,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command
);
end; --architecture logic
|
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_nios2_oci_itrace is
port(
clk : in vl_logic;
dbrk_traceoff : in vl_logic;
dbrk_traceon : in vl_logic;
jdo : in vl_logic_vector(15 downto 0);
jrst_n : in vl_logic;
take_action_tracectrl: in vl_logic;
trc_enb : in vl_logic;
xbrk_traceoff : in vl_logic;
xbrk_traceon : in vl_logic;
xbrk_wrap_traceoff: in vl_logic;
dct_buffer : out vl_logic_vector(29 downto 0);
dct_count : out vl_logic_vector(3 downto 0);
itm : out vl_logic_vector(35 downto 0);
trc_ctrl : out vl_logic_vector(15 downto 0);
trc_on : out vl_logic
);
end finalproject_cpu_nios2_oci_itrace;
|
-- $Id: tbd_tba_pdp11core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tbd_tba_pdp11core - syn
-- Description: tbd for testing pdp11_core_rbus plus ibdr_minisys
--
-- Dependencies: genlib/clkdivce
-- pdp11_core_rbus
-- pdp11_core
-- pdp11_bram
-- ibus/ibdr_minisys
-- rbus/rb_sres_or_2
--
-- Test bench: tb_rlink_tba_pdp11core
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
--
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.6.2 use rbaddr_ constants
-- 2018-10-07 1054 1.6.1 drop ITIMER from core
-- 2015-05-09 677 1.6 start/stop/suspend overhaul; reset overhaul
-- 2014-08-28 588 1.5.1 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
-- 2011-11-18 427 1.4.1 now numeric_std clean
-- 2010-12-30 351 1.4 renamed from tbd_pdp11core_rri; rbv3 port;
-- 2010-10-23 335 1.3.2 rename RRI_LAM->RB_LAM;
-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- remove pdp11_ibdr_rri
-- 2010-06-11 303 1.3 use IB_MREQ.racc instead of RRI_REQ
-- 2010-05-02 287 1.2.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- 2010-05-01 285 1.2 port to rri V2 interface
-- 2009-07-12 233 1.1.4 adapt to ibdr_minisys interface changes
-- 2008-08-22 161 1.1.3 use iblib, ibdlib
-- 2008-04-18 136 1.1.2 add RESET for ibdr_minisys
-- 2008-02-23 118 1.1.1 use sys_conf for bram size
-- 2008-02-17 117 1.1 adapt to em_ core interface; use pdp11_bram
-- 2008-01-20 113 1.0 Initial version (factored out from rrirp_pdp11core,
-- add rri access to ibdr now)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
use work.rblib.all;
entity tbd_tba_pdp11core is -- tbd pdp11_core_rbus plus ibdr_minisys
-- implements rbtba_aif
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ_aval : in slbit; -- rbus: request - aval
RB_MREQ_re : in slbit; -- rbus: request - re
RB_MREQ_we : in slbit; -- rbus: request - we
RB_MREQ_initt : in slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : in slv16; -- rbus: request - addr
RB_MREQ_din : in slv16; -- rbus: request - din
RB_SRES_ack : out slbit; -- rbus: response - ack
RB_SRES_busy : out slbit; -- rbus: response - busy
RB_SRES_err : out slbit; -- rbus: response - err
RB_SRES_dout : out slv16; -- rbus: response - dout
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv4 -- rbus: status flags
);
end entity tbd_tba_pdp11core;
architecture syn of tbd_tba_pdp11core is
signal CE_USEC : slbit := '0';
signal GRESET : slbit := '0';
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT : cp_stat_type := cp_stat_init;
signal CP_DOUT : slv16 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal BRESET : slbit := '0';
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES : ib_sres_type := ib_sres_init;
begin
RB_MREQ.aval <= RB_MREQ_aval;
RB_MREQ.re <= RB_MREQ_re;
RB_MREQ.we <= RB_MREQ_we;
RB_MREQ.init <= RB_MREQ_initt;
RB_MREQ.addr <= RB_MREQ_addr;
RB_MREQ.din <= RB_MREQ_din;
RB_SRES_ack <= RB_SRES.ack;
RB_SRES_busy <= RB_SRES.busy;
RB_SRES_err <= RB_SRES.err;
RB_SRES_dout <= RB_SRES.dout;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => open
);
RB2CP : pdp11_core_rbus
generic map (
RB_ADDR_CORE => rbaddr_cpu0_core,
RB_ADDR_IBUS => rbaddr_cpu0_ibus)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM(0),
GRESET => GRESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT
);
W11A : pdp11_core
port map (
CLK => CLK,
RESET => GRESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
ESUSP_O => open,
ESUSP_I => '0',
HBPT => '0',
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ,
IB_SRES_M => IB_SRES,
DM_STAT_SE => open,
DM_STAT_DP => open,
DM_STAT_VM => open,
DM_STAT_CO => open
);
MEM : pdp11_bram
generic map (
AWIDTH => sys_conf_bram_awidth)
port map (
CLK => CLK,
GRESET => GRESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES
);
IBDR_SYS : ibdr_minisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_USEC, -- !! in test benches msec = usec !!
RESET => GRESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => open
);
RB_SRES_OR : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_IBD,
RB_SRES_OR => RB_SRES
);
end syn;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_mod
-- File: can_mod.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: OpenCores CAN MAC with FIFO RAM
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library opencores;
use opencores.cancomp.all;
library grlib;
use grlib.stdlib.all;
entity can_mod is
generic (memtech : integer := DEFMEMTECH; syncrst : integer := 0;
ft : integer := 0);
port (
reset : in std_logic;
clk : in std_logic;
cs : in std_logic;
we : in std_logic;
addr : in std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq : out std_logic;
rxi : in std_logic;
txo : out std_logic;
testen : in std_logic
);
attribute sync_set_reset of reset : signal is "true";
end;
architecture rtl of can_mod is
type reg_type is record
waddr : std_logic_vector(5 downto 0);
ready : std_ulogic;
end record;
-- // port connections for Ram
--//64x8
signal q_dp_64x8 : std_logic_vector(7 downto 0);
signal data_64x8 : std_logic_vector(7 downto 0);
signal ldata_64x8 : std_logic_vector(7 downto 0);
signal wren_64x8 : std_logic;
signal lwren_64x8 : std_logic;
signal rden_64x8 : std_logic;
signal wraddress_64x8 : std_logic_vector(5 downto 0);
signal lwraddress_64x8 : std_logic_vector(5 downto 0);
signal rdaddress_64x8 : std_logic_vector(5 downto 0);
--//64x4
signal q_dp_64x4 : std_logic_vector(3 downto 0);
signal lq_dp_64x4 : std_logic_vector(4 downto 0);
signal data_64x4 : std_logic_vector(3 downto 0);
signal ldata_64x4 : std_logic_vector(4 downto 0);
signal wren_64x4x1 : std_logic;
signal lwren_64x4x1 : std_logic;
signal wraddress_64x4x1 : std_logic_vector(5 downto 0);
signal lwraddress_64x4x1 : std_logic_vector(5 downto 0);
signal rdaddress_64x4x1 : std_logic_vector(5 downto 0);
--//64x1
signal q_dp_64x1 : std_logic_vector(0 downto 0);
signal data_64x1 : std_logic_vector(0 downto 0);
signal ldata_64x1 : std_logic_vector(0 downto 0);
signal vcc, gnd : std_ulogic;
signal testin : std_logic_vector(3 downto 0);
signal r, rin : reg_type;
begin
ramclear : if syncrst = 2 generate
comb : process(r, reset, wren_64x8, data_64x8, wraddress_64x8,
data_64x4, wren_64x4x1, wraddress_64x4x1, data_64x1)
variable v : reg_type;
begin
v := r;
if r.ready = '0' then
v.waddr := r.waddr + 1;
if (r.waddr(5) and not v.waddr(5)) = '1' then v.ready := '1'; end if;
lwren_64x8 <= '1'; ldata_64x8 <= (others => '0');
lwraddress_64x8 <= r.waddr;
ldata_64x4 <= (others => '0'); lwren_64x4x1 <= '1';
lwraddress_64x4x1 <= r.waddr;
ldata_64x1 <= "0";
else
lwren_64x8 <= wren_64x8; ldata_64x8 <= data_64x8;
lwraddress_64x8 <= wraddress_64x8;
ldata_64x4 <= data_64x1 & data_64x4; lwren_64x4x1 <= wren_64x4x1;
lwraddress_64x4x1 <= wraddress_64x4x1;
ldata_64x1 <= data_64x1;
end if;
if reset = '1' then
v.ready := '0'; v.waddr := (others => '0');
end if;
rin <= v;
end process;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end generate;
noramclear : if syncrst /= 2 generate
lwren_64x8 <= wren_64x8; ldata_64x8 <= data_64x8;
lwraddress_64x8 <= wraddress_64x8;
ldata_64x4 <= data_64x1 & data_64x4; lwren_64x4x1 <= wren_64x4x1;
lwraddress_64x4x1 <= wraddress_64x4x1;
ldata_64x1 <= data_64x1;
end generate;
gnd <= '0'; vcc <= '1';
testin <= testen & "000";
async : if syncrst = 0 generate
can : can_top port map ( rst => reset, addr => addr, data_in => data_in,
data_out => data_out, cs => cs, we => we, clk_i => clk,
tx_o => txo, rx_i => rxi, bus_off_on => open, irq_on => irq,
clkout_o => open,
q_dp_64x8 => q_dp_64x8, data_64x8 => data_64x8, wren_64x8 => wren_64x8,
rden_64x8 => rden_64x8, wraddress_64x8 => wraddress_64x8,
rdaddress_64x8 => rdaddress_64x8, q_dp_64x4 => q_dp_64x4,
data_64x4 => data_64x4, wren_64x4x1 => wren_64x4x1,
wraddress_64x4x1 => wraddress_64x4x1,
rdaddress_64x4x1 => rdaddress_64x4x1,
q_dp_64x1 => q_dp_64x1(0), data_64x1 => data_64x1(0));
end generate;
sync : if syncrst /= 0 generate
can : can_top_sync port map ( rst => reset, addr => addr, data_in => data_in,
data_out => data_out, cs => cs, we => we, clk_i => clk,
tx_o => txo, rx_i => rxi, bus_off_on => open, irq_on => irq,
clkout_o => open,
q_dp_64x8 => q_dp_64x8, data_64x8 => data_64x8, wren_64x8 => wren_64x8,
rden_64x8 => rden_64x8, wraddress_64x8 => wraddress_64x8,
rdaddress_64x8 => rdaddress_64x8, q_dp_64x4 => q_dp_64x4,
data_64x4 => data_64x4, wren_64x4x1 => wren_64x4x1,
wraddress_64x4x1 => wraddress_64x4x1,
rdaddress_64x4x1 => rdaddress_64x4x1,
q_dp_64x1 => q_dp_64x1(0), data_64x1 => data_64x1(0));
end generate;
noft : if (ft = 0) or (memtech = 0) generate
fifo : syncram_2p generic map(memtech,6,8,0)
port map(rclk => clk, renable => rden_64x8, wclk => clk,
raddress => rdaddress_64x8, waddress => lwraddress_64x8,
datain => ldata_64x8, write => lwren_64x8, dataout => q_dp_64x8,
testin => testin);
info_fifo : syncram_2p generic map(memtech,6,5,0)
port map(rclk => clk, wclk => clk, raddress => rdaddress_64x4x1,
waddress => lwraddress_64x4x1, datain => ldata_64x4,
write => lwren_64x4x1, dataout => lq_dp_64x4, renable =>vcc,
testin => testin);
end generate;
ften : if not((ft = 0) or (memtech = 0)) generate
fifo : syncram_2pft generic map(memtech,6,8,0,0,2)
port map(rclk => clk, renable => rden_64x8, wclk => clk,
raddress => rdaddress_64x8, waddress => lwraddress_64x8,
datain => ldata_64x8, write => lwren_64x8, dataout => q_dp_64x8,
testin => testin);
info_fifo : syncram_2pft generic map(memtech,6,5,0,0,2)
port map(rclk => clk, wclk => clk, raddress => rdaddress_64x4x1,
waddress => lwraddress_64x4x1, datain => ldata_64x4,
write => lwren_64x4x1, dataout => lq_dp_64x4, renable =>vcc,
testin => testin);
end generate;
q_dp_64x4 <= lq_dp_64x4(3 downto 0);
q_dp_64x1 <= lq_dp_64x4(4 downto 4);
-- overrun_fifo : syncram_2p generic map(0,6,1,0)
-- port map(rclk => clk, wclk => clk, raddress => rdaddress_64x4x1,
-- waddress => lwraddress_64x4x1, datain => ldata_64x1,
-- write => lwren_64x4x1, dataout => q_dp_64x1, renable => vcc,
-- testin => testin);
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Martin Zabel
--
-- Module: Memory tester for Nexys4 DDR board using Xilinx MIG.
--
-- Description:
-- ------------------------------------
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
-- Copyrigth 2018 Martin Zabel
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library poc;
use poc.utils.all;
entity memtest_Nexys4DDR is
generic (
-- Must match configuration of generated mig_Nexys4DDR
ADDR_WIDTH : integer := 27;
BANK_WIDTH : integer := 3;
CK_WIDTH : integer := 1;
nCK_PER_CLK : integer := 4;
CS_WIDTH : integer := 1;
nCS_PER_RANK : integer := 1;
CKE_WIDTH : integer := 1;
DM_WIDTH : integer := 2;
DQ_WIDTH : integer := 16;
DQS_WIDTH : integer := 2;
PAYLOAD_WIDTH : integer := 16;
ROW_WIDTH : integer := 13;
ODT_WIDTH : integer := 1);
port (
sys_clk_i : in std_logic;
led : out std_logic_vector(7 downto 0);
ddr2_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr2_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
ddr2_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(ODT_WIDTH-1 downto 0));
end entity memtest_Nexys4DDR;
architecture rtl of memtest_Nexys4DDR is
signal sys_clk_unbuf : std_logic;
signal clk_ref : std_logic;
signal ref_clk_locked : std_logic;
signal memtest0_status : std_logic_vector(2 downto 0);
-- Memory Controller signals
signal app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_wdf_data : std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8-1 downto 0);
signal app_wdf_wren : std_logic;
signal app_rd_data : std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rdy : std_logic;
signal app_wdf_rdy : std_logic;
signal ui_clk : std_logic;
signal ui_clk_sync_rst : std_logic;
signal init_calib_complete : std_logic;
begin -- architecture rtl
----------------------------------------------------------------------------
-- Clocking
----------------------------------------------------------------------------
-- This system clock is used two-fold:
--
-- 1) It is used as the system clock for the memory controllers
-- (MIG). There it feeds only PLLs, so that, dedicated routing can be
-- used and no BUFG is required.
--
-- 2) It is also used to generate a 200 MHz reference clock used for the
-- IDELAYCTRL and temperature monitor logic.
-- This requires a BUFG, but could also be driven by another 200 MHz
-- clock source. If this other clock is not free-runnning, then
-- IDELAYCTRL and the temperature monitor must be hold in reset until
-- this other clock is stable.
sys_clk_ibufg : IBUFG port map (
I => sys_clk_i,
O => sys_clk_unbuf);
ref_clk_pll : entity work.pll_ref_clk
port map (
CLK_IN1 => sys_clk_unbuf,
CLK_OUT1 => clk_ref, -- 200 MHz reference clock driven by BUFG
LOCKED => ref_clk_locked); -- will hold IDELAYCTRL in reset by
-- by driving sys_rst of 'mig'
-----------------------------------------------------------------------------
-- MemoryTester for Port 0
-----------------------------------------------------------------------------
MemoryTester0 : block
constant BYTE_ADDR_BITS : natural := 4; -- 16 Byte / Word
constant WORD_ADDR_BITS : natural := ite(SIMULATION,
15, -- 32 KByte = 2 rows
27) -- 128 MB = 1 GBit
-BYTE_ADDR_BITS;
signal mem_rdy : std_logic;
signal mem_req : std_logic;
signal mem_write : std_logic;
signal mem_addr : unsigned(WORD_ADDR_BITS-1 downto 0);
signal mem_wdata : std_logic_vector(127 downto 0);
signal mem_rstb : std_logic;
signal mem_rdata : std_logic_vector(127 downto 0);
begin -- block MemoryTester0
fsm: entity work.memtest_fsm
generic map (
A_BITS => WORD_ADDR_BITS,
D_BITS => 128)
port map (
clk => ui_clk,
rst => ui_clk_sync_rst,
mem_rdy => mem_rdy,
mem_rstb => mem_rstb,
mem_rdata => mem_rdata,
mem_req => mem_req,
mem_write => mem_write,
mem_addr => mem_addr,
mem_wdata => mem_wdata,
status => memtest0_status);
adapter : entity poc.ddr3_mem2mig_adapter_Series7
generic map (
D_BITS => 128,
DQ_BITS => DQ_WIDTH,
MEM_A_BITS => WORD_ADDR_BITS,
APP_A_BITS => app_addr'length)
port map (
mem_req => mem_req,
mem_write => mem_write,
mem_addr => mem_addr,
mem_wdata => mem_wdata,
mem_rdy => mem_rdy,
mem_rstb => mem_rstb,
mem_rdata => mem_rdata,
init_calib_complete => init_calib_complete,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_mask => app_wdf_mask,
app_wdf_wren => app_wdf_wren);
end block MemoryTester0;
-----------------------------------------------------------------------------
-- Memory Controller Instantiation
-----------------------------------------------------------------------------
mig : entity work.mig_Nexys4DDR
port map (
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
sys_clk_i => sys_clk_unbuf,
clk_ref_i => clk_ref,
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_mask => app_wdf_mask,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => '0',
app_sr_active => open,
app_ref_req => '0',
app_ref_ack => open,
app_zq_req => '0',
app_zq_ack => open,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => init_calib_complete,
sys_rst => ref_clk_locked); -- active low
-----------------------------------------------------------------------------
-- Status outputs
-----------------------------------------------------------------------------
led(7) <= ui_clk_sync_rst;
led(6) <= ref_clk_locked;
led(5) <= '0';
led(4) <= '0';
led(3) <= init_calib_complete;
led(2 downto 0) <= memtest0_status;
end architecture rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:48:30 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_microblaze_0_0/system_microblaze_0_0_stub.vhdl
-- Design : system_microblaze_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_microblaze_0_0 is
Port (
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Interrupt : in STD_LOGIC;
Interrupt_Address : in STD_LOGIC_VECTOR ( 0 to 31 );
Interrupt_Ack : out STD_LOGIC_VECTOR ( 0 to 1 );
Instr_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
IFetch : out STD_LOGIC;
I_AS : out STD_LOGIC;
IReady : in STD_LOGIC;
IWAIT : in STD_LOGIC;
ICE : in STD_LOGIC;
IUE : in STD_LOGIC;
Data_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
Data_Write : out STD_LOGIC_VECTOR ( 0 to 31 );
D_AS : out STD_LOGIC;
Read_Strobe : out STD_LOGIC;
Write_Strobe : out STD_LOGIC;
DReady : in STD_LOGIC;
DWait : in STD_LOGIC;
DCE : in STD_LOGIC;
DUE : in STD_LOGIC;
Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 );
M_AXI_DP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_AWVALID : out STD_LOGIC;
M_AXI_DP_AWREADY : in STD_LOGIC;
M_AXI_DP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DP_WVALID : out STD_LOGIC;
M_AXI_DP_WREADY : in STD_LOGIC;
M_AXI_DP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_BVALID : in STD_LOGIC;
M_AXI_DP_BREADY : out STD_LOGIC;
M_AXI_DP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_ARVALID : out STD_LOGIC;
M_AXI_DP_ARREADY : in STD_LOGIC;
M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_RVALID : in STD_LOGIC;
M_AXI_DP_RREADY : out STD_LOGIC;
Dbg_Clk : in STD_LOGIC;
Dbg_TDI : in STD_LOGIC;
Dbg_TDO : out STD_LOGIC;
Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Shift : in STD_LOGIC;
Dbg_Capture : in STD_LOGIC;
Dbg_Update : in STD_LOGIC;
Debug_Rst : in STD_LOGIC;
Dbg_Disable : in STD_LOGIC;
M_AXI_IC_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_IC_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_AWLOCK : out STD_LOGIC;
M_AXI_IC_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_AWVALID : out STD_LOGIC;
M_AXI_IC_AWREADY : in STD_LOGIC;
M_AXI_IC_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_WLAST : out STD_LOGIC;
M_AXI_IC_WVALID : out STD_LOGIC;
M_AXI_IC_WREADY : in STD_LOGIC;
M_AXI_IC_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_BVALID : in STD_LOGIC;
M_AXI_IC_BREADY : out STD_LOGIC;
M_AXI_IC_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_IC_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_ARLOCK : out STD_LOGIC;
M_AXI_IC_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_ARVALID : out STD_LOGIC;
M_AXI_IC_ARREADY : in STD_LOGIC;
M_AXI_IC_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_RLAST : in STD_LOGIC;
M_AXI_IC_RVALID : in STD_LOGIC;
M_AXI_IC_RREADY : out STD_LOGIC;
M_AXI_DC_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_DC_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_AWLOCK : out STD_LOGIC;
M_AXI_DC_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_AWVALID : out STD_LOGIC;
M_AXI_DC_AWREADY : in STD_LOGIC;
M_AXI_DC_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_WLAST : out STD_LOGIC;
M_AXI_DC_WVALID : out STD_LOGIC;
M_AXI_DC_WREADY : in STD_LOGIC;
M_AXI_DC_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_BVALID : in STD_LOGIC;
M_AXI_DC_BREADY : out STD_LOGIC;
M_AXI_DC_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_DC_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_ARLOCK : out STD_LOGIC;
M_AXI_DC_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_ARVALID : out STD_LOGIC;
M_AXI_DC_ARREADY : in STD_LOGIC;
M_AXI_DC_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_RLAST : in STD_LOGIC;
M_AXI_DC_RVALID : in STD_LOGIC;
M_AXI_DC_RREADY : out STD_LOGIC
);
end system_microblaze_0_0;
architecture stub of system_microblaze_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Clk,Reset,Interrupt,Interrupt_Address[0:31],Interrupt_Ack[0:1],Instr_Addr[0:31],Instr[0:31],IFetch,I_AS,IReady,IWAIT,ICE,IUE,Data_Addr[0:31],Data_Read[0:31],Data_Write[0:31],D_AS,Read_Strobe,Write_Strobe,DReady,DWait,DCE,DUE,Byte_Enable[0:3],M_AXI_DP_AWADDR[31:0],M_AXI_DP_AWPROT[2:0],M_AXI_DP_AWVALID,M_AXI_DP_AWREADY,M_AXI_DP_WDATA[31:0],M_AXI_DP_WSTRB[3:0],M_AXI_DP_WVALID,M_AXI_DP_WREADY,M_AXI_DP_BRESP[1:0],M_AXI_DP_BVALID,M_AXI_DP_BREADY,M_AXI_DP_ARADDR[31:0],M_AXI_DP_ARPROT[2:0],M_AXI_DP_ARVALID,M_AXI_DP_ARREADY,M_AXI_DP_RDATA[31:0],M_AXI_DP_RRESP[1:0],M_AXI_DP_RVALID,M_AXI_DP_RREADY,Dbg_Clk,Dbg_TDI,Dbg_TDO,Dbg_Reg_En[0:7],Dbg_Shift,Dbg_Capture,Dbg_Update,Debug_Rst,Dbg_Disable,M_AXI_IC_AWID[0:0],M_AXI_IC_AWADDR[31:0],M_AXI_IC_AWLEN[7:0],M_AXI_IC_AWSIZE[2:0],M_AXI_IC_AWBURST[1:0],M_AXI_IC_AWLOCK,M_AXI_IC_AWCACHE[3:0],M_AXI_IC_AWPROT[2:0],M_AXI_IC_AWQOS[3:0],M_AXI_IC_AWVALID,M_AXI_IC_AWREADY,M_AXI_IC_WDATA[31:0],M_AXI_IC_WSTRB[3:0],M_AXI_IC_WLAST,M_AXI_IC_WVALID,M_AXI_IC_WREADY,M_AXI_IC_BID[0:0],M_AXI_IC_BRESP[1:0],M_AXI_IC_BVALID,M_AXI_IC_BREADY,M_AXI_IC_ARID[0:0],M_AXI_IC_ARADDR[31:0],M_AXI_IC_ARLEN[7:0],M_AXI_IC_ARSIZE[2:0],M_AXI_IC_ARBURST[1:0],M_AXI_IC_ARLOCK,M_AXI_IC_ARCACHE[3:0],M_AXI_IC_ARPROT[2:0],M_AXI_IC_ARQOS[3:0],M_AXI_IC_ARVALID,M_AXI_IC_ARREADY,M_AXI_IC_RID[0:0],M_AXI_IC_RDATA[31:0],M_AXI_IC_RRESP[1:0],M_AXI_IC_RLAST,M_AXI_IC_RVALID,M_AXI_IC_RREADY,M_AXI_DC_AWID[0:0],M_AXI_DC_AWADDR[31:0],M_AXI_DC_AWLEN[7:0],M_AXI_DC_AWSIZE[2:0],M_AXI_DC_AWBURST[1:0],M_AXI_DC_AWLOCK,M_AXI_DC_AWCACHE[3:0],M_AXI_DC_AWPROT[2:0],M_AXI_DC_AWQOS[3:0],M_AXI_DC_AWVALID,M_AXI_DC_AWREADY,M_AXI_DC_WDATA[31:0],M_AXI_DC_WSTRB[3:0],M_AXI_DC_WLAST,M_AXI_DC_WVALID,M_AXI_DC_WREADY,M_AXI_DC_BRESP[1:0],M_AXI_DC_BID[0:0],M_AXI_DC_BVALID,M_AXI_DC_BREADY,M_AXI_DC_ARID[0:0],M_AXI_DC_ARADDR[31:0],M_AXI_DC_ARLEN[7:0],M_AXI_DC_ARSIZE[2:0],M_AXI_DC_ARBURST[1:0],M_AXI_DC_ARLOCK,M_AXI_DC_ARCACHE[3:0],M_AXI_DC_ARPROT[2:0],M_AXI_DC_ARQOS[3:0],M_AXI_DC_ARVALID,M_AXI_DC_ARREADY,M_AXI_DC_RID[0:0],M_AXI_DC_RDATA[31:0],M_AXI_DC_RRESP[1:0],M_AXI_DC_RLAST,M_AXI_DC_RVALID,M_AXI_DC_RREADY";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "MicroBlaze,Vivado 2016.4";
begin
end;
|
-- VCORDIC module for Betty SDR
-- implements CORDIC in Vector Mode
-- file: vcordic.vhd
-- author: Sebastian Weiss DL3YC <dl3yc@darc.de>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
-- - functional testing with matlab as reference implementation
--
-- !!! because of the arctan table used in the CORDIC algorithm
-- !!! it only converges in the range of –1(rad) to +1(rad)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity vcordic is
generic
(
A : natural;
P : natural;
N : natural
);
port
(
clk : in std_logic;
i : in signed(A-1 downto 0);
q : in signed(A-1 downto 0);
amp : out unsigned(A-1 downto 0);
phi : out signed(P-1 downto 0)
);
end entity;
architecture behavioral of vcordic is
type alpha_t is array(0 to N-1) of signed(P-1 downto 0); -- -180°..180°
type xy_vector is array(natural range <>) of signed(A+2 downto 0); -- -3.999..+3.999
type z_vector is array(natural range <>) of signed(P-1 downto 0); -- -180°..180°
constant K : signed(A-1 downto 0) := to_signed(integer(0.6073*2**(A-1)),A);
signal alpha : alpha_t;
signal x,y : xy_vector(N downto 0) := (others => (others => '0'));
signal z : z_vector(N downto 0) := (others => (others => '0'));
begin
table: for i in 0 to N-1 generate
alpha(i) <= to_signed(integer( atan(1.0/real(2**i)) * (real(2**(P-1))-1.0) / math_pi ),P);
end generate;
process begin
wait until rising_edge(clk);
if i >= 0 then
x(0) <= resize(i,A+3);
y(0) <= resize(q,A+3);
z(0) <= (others => '0');
elsif q => 0 then
x(0) <= resize(q,A+3);
y(0) <= resize(-i,A+3);
z(0) <= to_signed(2**(P-3))-1,P);-- 90°
else
x(0) <= resize(-q,A+3);
y(0) <= resize(i,A+3);
z(0) <= to_signed(-2**(P-3))-1,P);-- -90°
end if;
for i in 1 to N loop
if x(i-1) >= 0 then
x(i) <= x(i-1) - y(i-1) / 2**(i-1);
y(i) <= y(i-1) + x(i-1) / 2**(i-1);
z(i) <= z(i-1) + alpha(i-1);
else
x(i) <= x(i-1) + y(i-1) / 2**(i-1);
y(i) <= y(i-1) - x(i-1) / 2**(i-1);
z(i) <= z(i-1) - alpha(i-1);
end if;
end loop;
amp <= resize(unsigned(shift_right((y(N) * K), (A-1))),A);
phi <= z(N);
end process;
end behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.MVL4.all;
entity tri_state_buffer is
port ( a, enable : in MVL4_ulogic; y : out MVL4_ulogic );
end entity tri_state_buffer;
--------------------------------------------------
architecture behavioral of tri_state_buffer is
begin
y <= 'Z' when enable = '0' else
a when enable = '1' and (a = '0' or a = '1') else
'X';
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.MVL4.all;
entity tri_state_buffer is
port ( a, enable : in MVL4_ulogic; y : out MVL4_ulogic );
end entity tri_state_buffer;
--------------------------------------------------
architecture behavioral of tri_state_buffer is
begin
y <= 'Z' when enable = '0' else
a when enable = '1' and (a = '0' or a = '1') else
'X';
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.MVL4.all;
entity tri_state_buffer is
port ( a, enable : in MVL4_ulogic; y : out MVL4_ulogic );
end entity tri_state_buffer;
--------------------------------------------------
architecture behavioral of tri_state_buffer is
begin
y <= 'Z' when enable = '0' else
a when enable = '1' and (a = '0' or a = '1') else
'X';
end architecture behavioral;
|
---------------------------------------------------------------------------------------------------
-- MX18 - CDP1802 Core
---------------------------------------------------------------------------------------------------
-- To save FPGA real estate this core has been coded in such away to try and persuade the synthesis
-- tool to implement the register file in distributed RAM. The core is designed to work with
-- synchronous memory. Interrupts, DMA and the SAV and MARK instructions have not been fully
-- implemented as yet although this will be done on future releases.
-- Each processor cycle or state uses 3 system clocks, a real 1802 uses 8.
---------------------------------------------------------------------------------------------------
-- This file is part of the PICO 1802 Tiny BASIC Project
-- Copyright 2016, Steve Teal: steveteal71@gmail.com
--
-- This source file may be used and distributed without restriction provided that this copyright
-- statement is not removed from the file and that any derivative work contains the original
-- copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms
-- of the GNU Lesser General Public License as published by the Free Software Foundation,
-- either version 3 of the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-3.0.en.html
---------------------------------------------------------------------------------------------------
-- Steve Teal, Northamptonshire, United Kingdom
---------------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mx18 is
port(
clock: in std_logic;
reset_n: in std_logic;
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
address: out std_logic_vector(15 downto 0);
ef: in std_logic_vector(3 downto 0);
nlines: out std_logic_vector(2 downto 0);
q: out std_logic;
rd_n: out std_logic;
wr_n: out std_logic);
end mx18;
architecture rtl of mx18 is
-- Timing and state signals
type state_type is (initialize,f1,f2,f3,e1,e2,e3,l1,l2,l3);
signal state : state_type;
signal init_counter : unsigned(3 downto 0);
-- Major state signals
signal fetch,execute,longbranch : std_logic;
-- Register file
type reg_file_type is array (0 to 15) of unsigned(15 downto 0);
signal reg_file : reg_file_type;
signal reg_file_out : unsigned(15 downto 0);
signal reg_file_in : unsigned(15 downto 0);
signal reg_file_index : unsigned(3 downto 0);
signal reg_file_adder : unsigned(15 downto 0);
signal reg_br_mux : unsigned(15 downto 0);
-- Register file control
signal rp,rx,rn,r2,r0 : std_logic;
signal reg_inc, reg_dec, reg_load_lo, reg_load_hi : std_logic;
-- Processor registers
signal n : std_logic_vector(3 downto 0);
signal i : std_logic_vector(3 downto 0);
signal p : std_logic_vector(3 downto 0);
signal x : std_logic_vector(3 downto 0);
signal t : std_logic_vector(7 downto 0);
signal d : std_logic_vector(7 downto 0);
signal b : std_logic_vector(7 downto 0);
signal df : std_logic;
signal ie : std_logic;
signal qq : std_logic;
-- ALU
signal alu_a : std_logic_vector(7 downto 0);
signal alu_b : std_logic_vector(7 downto 0);
signal alu_out : std_logic_vector(7 downto 0);
signal adder : unsigned(8 downto 0);
signal carry_in : std_logic;
-- ALU Control
signal inv_d : std_logic;
signal inv_data_in : std_logic;
signal alu_fn : std_logic_vector(1 downto 0);
-- Instruction decode signals
signal idl,ldn,inc,dec,sbr,lda,str,inp,outp,glo,ghi,plo,phi : std_logic;
signal lbr,sep,sex,ret,dis,ldxa,stxd,sav,mark,reqseq : std_logic;
signal rowf,shift,arithmetic,logic,immd,index : std_logic;
-- Memory control
signal memory_read,memory_write : std_logic;
-- Branch control
signal flag_mux, ef_mux, sbr_mux, branch_load_lo, branch_load_hi, branch_inc : std_logic;
signal d_zero, ie_skip_inhibit : std_logic;
begin
--
-- State machine
--
process(clock)
begin
if(rising_edge(clock))then
if(reset_n = '0')then
state <= initialize;
init_counter <= "0000";
else
case state is
when initialize =>
if(init_counter = "1111")then
state <= f1;
end if;
init_counter <= init_counter + 1;
when f1 => state <= f2;
when f2 => state <= f3;
when f3 => state <= e1;
when e1 => state <= e2;
when e2 => state <= e3;
when e3 =>
if(idl = '1')then
state <= e1;
elsif(lbr = '1')then
state <= l1;
else
state <= f1;
end if;
when l1 => state <= l2;
when l2 => state <= l3;
when l3 => state <= f1;
end case;
end if;
end if;
end process;
--
-- Major state logic
--
fetch <= '1' when state = f1 or state = f2 or state = f3 else '0';
execute <= '1' when state = e1 or state = e2 or state = e3 else '0';
longbranch <= '1' when state = l1 or state = l2 or state = l3 else '0';
--
-- Instruction Decoder
--
idl <= '1' when n = "0000" and i = "0000" else '0';
ldn <= '1' when n /= "0000" and i = "0000" else '0';
inc <= '1' when i = "0001" else '0';
dec <= '1' when i = "0010" else '0';
sbr <= '1' when i = "0011" else '0';
lda <= '1' when i = "0100" else '0';
str <= '1' when i = "0101" else '0';
outp <= '1' when i = "0110" and n(3) = '0' else '0';
inp <= '1' when i = "0110" and n(3) = '1' else '0';
ret <= '1' when i = "0111" and n = "0000" else '0';
dis <= '1' when i = "0111" and n = "0001" else '0';
ldxa <= '1' when i = "0111" and n = "0010" else '0';
stxd <= '1' when i = "0111" and n = "0011" else '0';
sav <= '1' when i = "0111" and n = "1000" else '0';
mark <= '1' when i = "0111" and n = "1001" else '0';
reqseq <= '1' when i = "0111" and n(3 downto 1) = "101" else '0';
glo <= '1' when i = "1000" else '0';
ghi <= '1' when i = "1001" else '0';
plo <= '1' when i = "1010" else '0';
phi <= '1' when i = "1011" else '0';
lbr <= '1' when i = "1100" else '0';
sep <= '1' when i = "1101" else '0';
sex <= '1' when i = "1110" else '0';
shift <= '1' when i(2 downto 0) = "111" and n(2 downto 0) = "110" else '0';
arithmetic <= '1' when i(2 downto 0) = "111" and n(2) = '1' else '0';
logic <= '1' when i = "1111" and n(2) = '0' and (n(0) = '1' or n(1) = '1') else '0';
rowf <= '1' when i = "1111" else '0';
immd <= '1' when (i = "0111" and n(3 downto 2) = "11") or (i = "1111" and n(3)='1') else '0';
index <= '1' when (i = "0111" and n(3 downto 2) = "01") or (i = "1111" and n(3)='0') else '0';
--
-- ALU and associated control logic
--
inv_data_in <= n(0) and n(1) and n(2);
inv_d <= n(2) and n(0) and not n(1);
carry_in <= (df and not i(3)) or (i(3) and (inv_data_in or inv_d));
alu_fn(0) <= n(0) and not n(2);
alu_fn(1) <= n(1) and not n(2);
alu_a <= not data_in when inv_data_in = '1' else data_in;
alu_b <= not d when inv_d = '1' else d;
adder <= ('0' & unsigned(alu_a)) + ('0' & unsigned(alu_b)) + ("00000000" & carry_in);
with alu_fn(1 downto 0) select alu_out <=
std_logic_vector(adder(7 downto 0)) when "00",
alu_a or alu_b when "01",
alu_a and alu_b when "10",
alu_a xor alu_b when others;
--
-- DF Register
--
process(clock)
begin
if(rising_edge(clock))then
if(state = initialize)then
df <= '0';
elsif(state = e3)then
if(shift = '1')then
if(n(3) = '1')then
df <= d(7);
else
df <= d(0);
end if;
elsif(arithmetic = '1')then
df <= adder(8);
end if;
end if;
end if;
end process;
--
-- D Register
--
process(clock)
begin
if(rising_edge(clock))then
if(state = initialize)then
d <= "00000000";
elsif(state = e3)then
if(shift = '1')then
if(n(3) = '1')then
d <= d(6 downto 0) & carry_in;
else
d <= carry_in & d(7 downto 1);
end if;
elsif(arithmetic = '1' or logic = '1')then
d <= alu_out;
elsif(glo = '1')then
d <= std_logic_vector(reg_file_out(7 downto 0));
elsif(ghi = '1')then
d <= std_logic_vector(reg_file_out(15 downto 8));
elsif(ldn = '1' or lda = '1' or ldxa = '1' or inp = '1' or rowf = '1')then
d <= data_in;
end if;
end if;
end if;
end process;
--
-- B Register
--
process(clock)
begin
if(rising_edge(clock))then
if(state = e3 and lbr = '1')then
b <= data_in;
end if;
end if;
end process;
--
-- I:N Registers
--
process(clock)
begin
if(rising_edge(clock))then
if(state = initialize)then
n <= "0000";
i <= "0000";
elsif(state = f3)then
n <= data_in(3 downto 0);
i <= data_in(7 downto 4);
end if;
end if;
end process;
--
-- X Register
--
process(clock)
begin
if(rising_edge(clock))then
if(state = initialize)then
x <= "0000";
elsif(state = e3)then
if(sex = '1')then
x <= n;
elsif(ret = '1' or dis = '1')then
x <= data_in(7 downto 4);
elsif(mark = '1')then
x <= p;
end if;
end if;
end if;
end process;
--
-- P Register
--
process(clock)
begin
if(rising_edge(clock))then
if(state = initialize)then
p <= "0000";
elsif(state = e3)then
if(sep = '1')then
p <= n;
elsif(ret = '1' or dis = '1')then
p <= data_in(3 downto 0);
end if;
end if;
end if;
end process;
--
-- Q Register
--
process(clock)
begin
if(rising_edge(clock))then
if(state = initialize)then
qq <= '0';
elsif(state = e3 and reqseq = '1')then
qq <= n(0);
end if;
end if;
end process;
q <= qq;
--
-- IE Register
--
process(clock)
begin
if(rising_edge(clock))then
if(state = initialize)then
ie <= '0';
elsif(state = e3)then
if(ret = '1')then
ie <= '1';
elsif(dis = '1')then
ie <= '0';
end if;
end if;
end if;
end process;
--
-- T Register
--
process(clock)
begin
if(rising_edge(clock))then
if(state = initialize)then
t <= "00000000";
elsif(state = e3 and mark = '1')then
t <= x & p;
end if;
end if;
end process;
--
-- Data out register
--
process(clock)
begin
if(rising_edge(clock))then
if(state = initialize or state = e3)then
data_out <= "00000000";
elsif(state = e2)then
if(str = '1' or stxd = '1')then
data_out <= d;
elsif(mark = '1' or sav = '1')then
data_out <= t;
end if;
end if;
end if;
end process;
--
-- Register file read/write
--
process(clock)
begin
if(rising_edge(clock))then
if(state = f1 or state = e1 or state = l1)then
reg_file_out <= reg_file(to_integer(reg_file_index));
elsif(state = f3 or state = e3 or state = l3 or state = initialize)then
reg_file(to_integer(reg_file_index)) <= reg_file_in;
end if;
end if;
end process;
address <= std_logic_vector(reg_file_out);
--
-- Register file indexing
--
reg_file_index(0) <= init_counter(0) or (p(0) and rp) or (n(0) and rn) or (x(0) and rx);
reg_file_index(1) <= init_counter(1) or (p(1) and rp) or (n(1) and rn) or (x(1) and rx) or r2;
reg_file_index(2) <= init_counter(2) or (p(2) and rp) or (n(2) and rn) or (x(2) and rx);
reg_file_index(3) <= init_counter(3) or (p(3) and rp) or (n(3) and rn) or (x(3) and rx);
r0 <= execute and idl;
r2 <= execute and mark;
rp <= fetch or longbranch or sbr or lbr or (execute and (immd or reqseq));
rx <= execute and (inp or outp or ret or dis or index or stxd or ldxa or sav);
rn <= not (r0 or r2 or rp or rx);
--
-- Register file data path
--
reg_file_adder <= reg_file_out - 1 when reg_dec = '1' else reg_file_out + 1 when reg_inc = '1' else X"0000" when state = initialize else reg_file_out;
reg_file_in(7 downto 0) <= reg_br_mux(7 downto 0) when reg_load_lo = '1' else reg_file_adder(7 downto 0);
reg_file_in(15 downto 8) <= reg_br_mux(15 downto 8) when reg_load_hi = '1' else reg_file_adder(15 downto 8);
reg_br_mux <= unsigned(b) & unsigned(data_in) when (lbr or sbr) = '1' else unsigned(d) & unsigned(d);
--
-- Register file control
--
reg_dec <= execute and (dec or stxd);
reg_inc <= fetch or (execute and (lda or inc or outp or immd or ldxa or ret or dis) and not shift) or ((execute or longbranch) and branch_inc);
reg_load_lo <= (execute and (plo or branch_load_lo)) or (longbranch and branch_load_lo);
reg_load_hi <= (execute and phi) or (longbranch and branch_load_hi);
--
-- Memory control
--
memory_read <= (ldn or lda or sbr or outp or ret or dis or ldxa or lbr or immd or index) and not shift;
memory_write <= str or inp or stxd or sav or mark;
process(clock)
begin
if(rising_edge(clock))then
if(state = initialize or state = e3)then
wr_n <= '1';
elsif(state = e2 and memory_write = '1')then
wr_n <= '0';
end if;
end if;
end process;
process(clock)
begin
if(rising_edge(clock))then
if(state = initialize or state = f3 or state = e3 or state = l3)then
rd_n <= '1';
elsif(state = f1 or state = l1 or (state = e1 and memory_read = '1'))then
rd_n <= '0';
end if;
end if;
end process;
--
-- Branch logic
--
d_zero <= '1' when d= "00000000" else '0';
ie_skip_inhibit <= '0' when n = "1100" and ie = '0' else '1';
with n(1 downto 0) select flag_mux <=
'1' when "00",
qq when "01",
d_zero when "10",
df when "11",
'X' when others;
with n(1 downto 0) select ef_mux <=
not ef(0) when "00",
not ef(1) when "01",
not ef(2) when "10",
not ef(3) when "11",
'X' when others;
sbr_mux <= flag_mux when n(2) = '0' else ef_mux;
branch_inc <= (sbr and (sbr_mux xnor n(3))) or (lbr and ie_skip_inhibit and (flag_mux xnor n(3))) or (execute and lbr and not n(2));
branch_load_lo <= '1' when (longbranch = '1' and n(2) = '0' and flag_mux /= n(3)) or (sbr = '1' and sbr_mux /= n(3)) else '0';
branch_load_hi <= '1' when longbranch = '1' and n(2) = '0' and flag_mux /= n(3) else '0';
--
-- N outputs
--
process(clock)
begin
if(rising_edge(clock))then
if(state = initialize)then
nlines <= "000";
elsif(state = e1 and (inp = '1' or outp = '1'))then
nlines <= n(2 downto 0);
elsif(state = e3)then
nlines <= "000";
end if;
end if;
end process;
end rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_2_block2.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block2
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_2_block2 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_7 : IN std_logic; -- ufix1
dout_7_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_7_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_15_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_15_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_7_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_8_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_8_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block2;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block2 IS
-- Signals
SIGNAL dout_7_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din1_re : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_7_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din1_im : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_15_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din2_re : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_15_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din2_im : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_7_re_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_7_im_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_8_re_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_8_im_tmp : signed(18 DOWNTO 0); -- sfix19
BEGIN
dout_7_re_signed <= signed(dout_7_re);
din1_re <= resize(dout_7_re_signed, 19);
dout_7_im_signed <= signed(dout_7_im);
din1_im <= resize(dout_7_im_signed, 19);
dout_15_re_signed <= signed(dout_15_re);
din2_re <= resize(dout_15_re_signed, 19);
dout_15_im_signed <= signed(dout_15_im);
din2_im <= resize(dout_15_im_signed, 19);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_7)
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_7 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 20) + resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 20) - resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 20) + resize(din2_re, 20);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 20) - resize(din2_re, 20);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 20) + resize(din2_re, 20);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 20) - resize(din2_re, 20);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 20) + resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 20) - resize(din2_im, 20);
END IF;
dout_7_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(18 DOWNTO 0);
dout_7_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(18 DOWNTO 0);
dout_8_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(18 DOWNTO 0);
dout_8_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(18 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_8_re <= std_logic_vector(dout_8_re_tmp);
dout_8_im <= std_logic_vector(dout_8_im_tmp);
dout_7_re_1 <= std_logic_vector(dout_7_re_tmp);
dout_7_im_1 <= std_logic_vector(dout_7_im_tmp);
END rtl;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 30-05-2016
-- Module Name: datapath.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity datapath is
port (clk, ent, ext : in std_logic;
output : out std_logic_vector (3 downto 0));
end entity;
architecture rtl of datapath is
component counter
generic (N : integer := 4);
port (inc, dec : in std_logic;
output : out std_logic_vector (N - 1 downto 0);
clk : in std_logic);
end component;
for all:counter use entity work.counter;
begin
cntr : counter port map (ent, ext, output, clk);
end architecture;
|
-- This entity is used to adapt the interface between the marvell (4 bits double data rate clocked on GE_RXCLK)
-- and the fpga (8 bits clocked on rising edge of CLK125)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_package.all;
entity interface_management is
port (
clk125 : in std_logic;
clk250_marvell : in std_logic;
clk250_fpga : in std_logic;
reset_n : in std_logic;
RX_i : in rgmii_t;
RX_o : out gmii_t;
TX_i : in gmii_t;
TX_o : out rgmii_t
);
end interface_management;
architecture RTL of interface_management is
type fsm_rcv is (idle,preamble,data);
signal state_rcv : fsm_rcv;
signal count_preamble : unsigned(3 downto 0);
signal TX_i_dl : rgmii_t;
signal half : std_logic;
signal reset : std_logic;
signal empty_rgmii2gmii : std_logic;
signal data_valid_sync : std_logic;
signal rd_en_sync : std_logic;
signal data_sync : std_logic_vector(7 downto 0);
signal RX_sync : gmii_t;
signal empty_gmii2rgmii : std_logic;
signal rd_en_tx,rd_en_tx_dl : std_logic;
signal data_valid_tx : std_logic;
signal data_tx : std_logic_vector(3 downto 0);
begin
reset <= not reset_n;
--- Data in : 4bits at 250MHz (GE_RXCLK x2) --- Data out : 8bits 125MHz
rgmii2gmii_fifo_inst : entity work.rgmii2gmii_fifo
port map (
wrclk => clk250_marvell,
wrreq => RX_i.dv,
data => RX_i.data,
rdclk => clk125,
rdreq => rd_en_sync,
q => data_sync,
rdempty => empty_rgmii2gmii
);
--- Process controling signals of rgmii2gmii fifo
process(clk125)
begin
if clk125'event and clk125='1' then
rd_en_sync <= not empty_rgmii2gmii;
data_valid_sync <= rd_en_sync and not empty_rgmii2gmii;
RX_sync.data <= data_sync;
RX_sync.dv <= data_valid_sync;
end if;
end process;
-------- Detect and remove Ethernet preamble
process(clk125,reset_n)
begin
if reset_n='0' then
state_rcv <= idle;
count_preamble <= x"0";
RX_o.dv <= '0';
RX_o.data <= x"00";
elsif (clk125'event and clk125='1') then
case (state_rcv) is
when idle =>
if RX_sync.dv='1' then
state_rcv <= preamble;
if RX_sync.data=x"55" then
count_preamble <= count_preamble +1;
end if;
else
count_preamble <= x"0";
state_rcv <= idle;
end if;
when preamble =>
if RX_sync.dv='1' and RX_sync.data=x"55" then
count_preamble <= count_preamble +1;
elsif RX_sync.data=x"D5" and count_preamble>=x"5" then
state_rcv <= data;
count_preamble <= x"0";
elsif RX_sync.dv='0' then
state_rcv <= idle;
end if;
when data =>
if RX_sync.dv='1' then
RX_o.dv <= '1';
RX_o.data <= RX_sync.data;
state_rcv <= data;
else
RX_o.dv <= '0';
RX_o.data <= x"00";
state_rcv <= idle;
end if;
when others =>
state_rcv <= idle;
end case;
end if;
end process;
------ Transmission GMII to RGMII
process(clk250_fpga,reset_n)
begin
if reset_n='0' then
TX_o.dv <= '0';
TX_o.data <= x"0";
elsif (clk250_fpga'event and clk250_fpga='1') then
TX_o.dv <= TX_i_dl.dv;
TX_o.data <= TX_i_dl.data;
TX_i_dl.dv <= TX_i.dv;
if TX_i.dv='1' and TX_i_dl.dv='0' then
TX_i_dl.data(3 downto 0) <= TX_i.data(7 downto 4);
half <= '1';
elsif TX_i_dl.dv='1' then
half <= not half;
if half='1' then
TX_i_dl.data(3 downto 0) <= TX_i.data(7 downto 4);
else
TX_i_dl.data(3 downto 0) <= TX_i.data(3 downto 0);
end if;
end if;
end if;
end process;
end RTL;
|
--This should pass
context c1 is
end context c1;
--These should fail
context c1 is
end context c1
;
context
c1
is
end
context c1 -- Some comment
;
context c1 is
end -- Some comment
context c1 -- Some other comment
-- other comments
;
context c1 -- Yet another commet
-- Some comment
is
end
-- Comment again
context c1
;
-- Test with missing end context keyword
context c1 is
end;
context c1 is
end context;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNDDTJRE6Q is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "010";
width : natural := 3);
port(
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNDDTJRE6Q is
Begin
-- Constant
output <= "010";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNDDTJRE6Q is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "010";
width : natural := 3);
port(
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNDDTJRE6Q is
Begin
-- Constant
output <= "010";
end architecture; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- In/out for top level module
entity VGAtonic_Firmware is
PORT(
CLK : in STD_LOGIC;
-- SPI Select (Master is AVR)
AVR_CPLD_EXT_1 : in STD_LOGIC;
-- SPI Pins from Outside World
EXT_SCK : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC := '0';
EXT_SEL_CPLD : in STD_LOGIC; -- Active low
-- SPI Pins from AVR
AVR_SCK : in STD_LOGIC;
-- Using this as our SEL pin due to timer issues
AVR_CPLD_EXT_2 : in STD_LOGIC;
AVR_MOSI : in STD_LOGIC;
-- AVR_MISO : out STD_LOGIC := 'Z';
-- VGA
PIXEL : inout STD_LOGIC_VECTOR(8 downto 0);
HSYNC : inout STD_LOGIC;
VSYNC : inout STD_LOGIC;
--CPLD_GPIO : out STD_LOGIC_VECTOR(16 downto 16) := "0";
-- Memory
DATA : inout STD_LOGIC_VECTOR(7 downto 0);
ADDR : out STD_LOGIC_VECTOR(18 downto 0);
OE_LOW : inout STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1'
);
end VGAtonic_Firmware;
architecture Behavioral of VGAtonic_Firmware is
-- Handshaking signals from SPI
signal SPI_DATA_CACHE : STD_LOGIC_VECTOR(7 downto 0);
signal SPI_CACHE_FULL_FLAG : STD_LOGIC;
signal SPI_CMD_RESET_FLAG : STD_LOGIC;
-- Handshaking signals to SPI
signal ACK_USER_RESET : STD_LOGIC;
signal ACK_SPI_BYTE : STD_LOGIC;
-- Instantiating our SPI slave code (see earlier entries)
COMPONENT SPI_Slave
PORT(
SEL_SPI : in STD_LOGIC;
-- SPI Pins from World
EXT_SCK : in STD_LOGIC;
EXT_SEL : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC;
-- SPI Pins from AVR
AVR_SCK : in STD_LOGIC;
AVR_SEL : in STD_LOGIC;
AVR_MOSI : in STD_LOGIC;
-- AVR_MISO : out STD_LOGIC;
ACK_USER_RESET : IN std_logic;
ACK_SPI_BYTE : IN std_logic;
SPI_DATA_CACHE : OUT std_logic_vector(7 downto 0);
SPI_CACHE_FULL_FLAG : OUT std_logic;
SPI_CMD_RESET_FLAG : OUT std_logic
);
END COMPONENT;
-- Instantiating our Display Controller code
-- Just VGA for now
COMPONENT Display_Controller
PORT(
CLK : IN std_logic;
SPI_DATA_CACHE : IN std_logic_vector(7 downto 0);
SPI_CACHE_FULL_FLAG : IN std_logic;
SPI_CMD_RESET_FLAG : IN std_logic;
PIXEL : INOUT std_logic_vector(8 downto 0);
HSYNC : INOUT std_logic;
VSYNC : INOUT std_logic;
--CPLD_GPIO : OUT std_logic_vector(16 to 16);
ACK_USER_RESET : INOUT std_logic;
ACK_SPI_BYTE : OUT std_logic;
ADDR : OUT std_logic_vector(18 downto 0);
DATA : INOUT std_logic_vector(7 downto 0);
OE_LOW : inout STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1'
);
END COMPONENT;
begin
-- Nothing special here; we don't even really change the names of the signals.
-- Here we map all of the internal and external signals to the respective
-- modules for SPI input and VGA output.
Inst_SPI_Slave: SPI_Slave PORT MAP(
SEL_SPI => AVR_CPLD_EXT_1,
EXT_SCK => EXT_SCK,
EXT_SEL => EXT_SEL_CPLD,
EXT_MOSI => EXT_MOSI,
EXT_MISO => EXT_MISO,
AVR_SCK => AVR_SCK,
AVR_SEL => AVR_CPLD_EXT_2,
AVR_MOSI => AVR_MOSI,
-- AVR_MISO => AVR_MISO,
SPI_DATA_CACHE => SPI_DATA_CACHE,
SPI_CACHE_FULL_FLAG => SPI_CACHE_FULL_FLAG,
SPI_CMD_RESET_FLAG => SPI_CMD_RESET_FLAG,
ACK_USER_RESET => ACK_USER_RESET,
ACK_SPI_BYTE => ACK_SPI_BYTE
);
Inst_Display_Controller: Display_Controller PORT MAP(
CLK => CLK,
PIXEL => PIXEL,
HSYNC => HSYNC,
VSYNC => VSYNC,
--CPLD_GPIO => CPLD_GPIO,
SPI_DATA_CACHE => SPI_DATA_CACHE,
SPI_CACHE_FULL_FLAG => SPI_CACHE_FULL_FLAG,
SPI_CMD_RESET_FLAG => SPI_CMD_RESET_FLAG,
ACK_USER_RESET => ACK_USER_RESET,
ACK_SPI_BYTE => ACK_SPI_BYTE,
DATA => DATA,
ADDR => ADDR,
OE_LOW => OE_LOW,
WE_LOW => WE_LOW,
CE_LOW => CE_LOW
);
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_37x512_hf_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(1-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(37-1 DOWNTO 0);
DOUT : OUT std_logic_vector(37-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use WORK.alu_types.all;
entity INIT_PG is
port(
A: in std_logic;
B: in std_logic;
PG: out std_logic_vector(1 downto 0)
);
end INIT_PG;
architecture BEHAVIORAL of INIT_PG is
begin
PG(0) <= A xor B;
PG(1) <= A and B;
end BEHAVIORAL;
|
-- tb_Gray_Binarization.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:20:48
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Gray_Binarization is
end entity tb_Gray_Binarization;
architecture rtl of tb_Gray_Binarization is
component Gray_Binarization_GN is
port (
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset_n
Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
Avalon_ST_Sink_endofpacket : in std_logic := 'X'; -- wire
Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
Avalon_ST_Source_valid : out std_logic; -- wire
Avalon_ST_Sink_valid : in std_logic := 'X'; -- wire
Avalon_ST_Source_endofpacket : out std_logic; -- wire
Avalon_ST_Source_startofpacket : out std_logic; -- wire
Avalon_ST_Source_ready : in std_logic := 'X'; -- wire
Avalon_MM_Slave_write : in std_logic := 'X'; -- wire
Avalon_ST_Sink_ready : out std_logic; -- wire
Avalon_ST_Sink_startofpacket : in std_logic := 'X'; -- wire
Avalon_ST_Source_data : out std_logic_vector(23 downto 0) -- wire
);
end component Gray_Binarization_GN;
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic; -- reset
clock_out : out std_logic; -- clk
reg_aclr_out : out std_logic; -- reset
tb_aclr : out std_logic -- reset
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
component alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GNOXVOQUET;
component alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic -- wire
);
end component alt_dspbuilder_testbench_salt_GNDBMPYDND;
component alt_dspbuilder_testbench_salt_GN6DKNTQ5M is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN6DKNTQ5M;
component alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN7Z4SHGOK;
component alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_testbench_capture_GNQX2JTRTZ;
component alt_dspbuilder_testbench_capture_GNHCRI5YMO is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_testbench_capture_GNHCRI5YMO;
signal salt_avalon_st_sink_data_output_wire : std_logic_vector(23 downto 0); -- salt_Avalon_ST_Sink_data:output -> dut:Avalon_ST_Sink_data
signal clock_clock_tb_reset : std_logic; -- Clock:tb_aclr -> [salt_Avalon_MM_Slave_address:aclr, salt_Avalon_MM_Slave_write:aclr, salt_Avalon_MM_Slave_writedata:aclr, salt_Avalon_ST_Sink_data:aclr, salt_Avalon_ST_Sink_endofpacket:aclr, salt_Avalon_ST_Sink_startofpacket:aclr, salt_Avalon_ST_Sink_valid:aclr, salt_Avalon_ST_Source_ready:aclr]
signal clock_clock_tb_clk : std_logic; -- Clock:clock_out -> [capture_Avalon_ST_Sink_ready:clock, capture_Avalon_ST_Source_data:clock, capture_Avalon_ST_Source_endofpacket:clock, capture_Avalon_ST_Source_startofpacket:clock, capture_Avalon_ST_Source_valid:clock, dut:Clock, salt_Avalon_MM_Slave_address:clock, salt_Avalon_MM_Slave_write:clock, salt_Avalon_MM_Slave_writedata:clock, salt_Avalon_ST_Sink_data:clock, salt_Avalon_ST_Sink_endofpacket:clock, salt_Avalon_ST_Sink_startofpacket:clock, salt_Avalon_ST_Sink_valid:clock, salt_Avalon_ST_Source_ready:clock]
signal salt_avalon_st_sink_endofpacket_output_wire : std_logic; -- salt_Avalon_ST_Sink_endofpacket:output -> dut:Avalon_ST_Sink_endofpacket
signal salt_avalon_mm_slave_address_output_wire : std_logic_vector(1 downto 0); -- salt_Avalon_MM_Slave_address:output -> dut:Avalon_MM_Slave_address
signal salt_avalon_mm_slave_writedata_output_wire : std_logic_vector(31 downto 0); -- salt_Avalon_MM_Slave_writedata:output -> dut:Avalon_MM_Slave_writedata
signal salt_avalon_st_sink_valid_output_wire : std_logic; -- salt_Avalon_ST_Sink_valid:output -> dut:Avalon_ST_Sink_valid
signal salt_avalon_st_source_ready_output_wire : std_logic; -- salt_Avalon_ST_Source_ready:output -> dut:Avalon_ST_Source_ready
signal salt_avalon_mm_slave_write_output_wire : std_logic; -- salt_Avalon_MM_Slave_write:output -> dut:Avalon_MM_Slave_write
signal salt_avalon_st_sink_startofpacket_output_wire : std_logic; -- salt_Avalon_ST_Sink_startofpacket:output -> dut:Avalon_ST_Sink_startofpacket
signal dut_avalon_st_source_valid_wire : std_logic; -- dut:Avalon_ST_Source_valid -> capture_Avalon_ST_Source_valid:input
signal clock_clock_reg_reset_reset : std_logic; -- Clock:reg_aclr_out -> [capture_Avalon_ST_Sink_ready:aclr, capture_Avalon_ST_Source_data:aclr, capture_Avalon_ST_Source_endofpacket:aclr, capture_Avalon_ST_Source_startofpacket:aclr, capture_Avalon_ST_Source_valid:aclr]
signal dut_avalon_st_source_endofpacket_wire : std_logic; -- dut:Avalon_ST_Source_endofpacket -> capture_Avalon_ST_Source_endofpacket:input
signal dut_avalon_st_source_startofpacket_wire : std_logic; -- dut:Avalon_ST_Source_startofpacket -> capture_Avalon_ST_Source_startofpacket:input
signal dut_avalon_st_sink_ready_wire : std_logic; -- dut:Avalon_ST_Sink_ready -> capture_Avalon_ST_Sink_ready:input
signal dut_avalon_st_source_data_wire : std_logic_vector(23 downto 0); -- dut:Avalon_ST_Source_data -> capture_Avalon_ST_Source_data:input
signal clock_clock_output_reset : std_logic; -- Clock:aclr_out -> clock_clock_output_reset:in
signal clock_clock_output_reset_ports_inv : std_logic; -- clock_clock_output_reset:inv -> dut:aclr
begin
dut : component Gray_Binarization_GN
port map (
Clock => clock_clock_tb_clk, -- Clock.clk
aclr => clock_clock_output_reset_ports_inv, -- .reset_n
Avalon_ST_Sink_data => salt_avalon_st_sink_data_output_wire, -- Avalon_ST_Sink_data.wire
Avalon_ST_Sink_endofpacket => salt_avalon_st_sink_endofpacket_output_wire, -- Avalon_ST_Sink_endofpacket.wire
Avalon_MM_Slave_address => salt_avalon_mm_slave_address_output_wire, -- Avalon_MM_Slave_address.wire
Avalon_MM_Slave_writedata => salt_avalon_mm_slave_writedata_output_wire, -- Avalon_MM_Slave_writedata.wire
Avalon_ST_Source_valid => dut_avalon_st_source_valid_wire, -- Avalon_ST_Source_valid.wire
Avalon_ST_Sink_valid => salt_avalon_st_sink_valid_output_wire, -- Avalon_ST_Sink_valid.wire
Avalon_ST_Source_endofpacket => dut_avalon_st_source_endofpacket_wire, -- Avalon_ST_Source_endofpacket.wire
Avalon_ST_Source_startofpacket => dut_avalon_st_source_startofpacket_wire, -- Avalon_ST_Source_startofpacket.wire
Avalon_ST_Source_ready => salt_avalon_st_source_ready_output_wire, -- Avalon_ST_Source_ready.wire
Avalon_MM_Slave_write => salt_avalon_mm_slave_write_output_wire, -- Avalon_MM_Slave_write.wire
Avalon_ST_Sink_ready => dut_avalon_st_sink_ready_wire, -- Avalon_ST_Sink_ready.wire
Avalon_ST_Sink_startofpacket => salt_avalon_st_sink_startofpacket_output_wire, -- Avalon_ST_Sink_startofpacket.wire
Avalon_ST_Source_data => dut_avalon_st_source_data_wire -- Avalon_ST_Source_data.wire
);
clock : component alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map (
SIMULATION_START_CYCLE => 5,
RESET_LATENCY => 0,
RESET_REGISTER_CASCADE_DEPTH => 0
)
port map (
clock_out => clock_clock_tb_clk, -- clock_tb.clk
tb_aclr => clock_clock_tb_reset, -- .reset
aclr_out => clock_clock_output_reset, -- clock_output.reset
reg_aclr_out => clock_clock_reg_reset_reset -- clock_reg_reset.reset
);
salt_avalon_st_sink_data : component alt_dspbuilder_testbench_salt_GNOXVOQUET
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_data.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_data_output_wire -- output.wire
);
salt_avalon_st_sink_endofpacket : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_endofpacket.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_endofpacket_output_wire -- output.wire
);
salt_avalon_mm_slave_address : component alt_dspbuilder_testbench_salt_GN6DKNTQ5M
generic map (
XFILE => "Gray%5FBinarization_Avalon-MM+Slave_address.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_address_output_wire -- output.wire
);
salt_avalon_mm_slave_writedata : component alt_dspbuilder_testbench_salt_GN7Z4SHGOK
generic map (
XFILE => "Gray%5FBinarization_Avalon-MM+Slave_writedata.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_writedata_output_wire -- output.wire
);
salt_avalon_st_sink_valid : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_valid.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_valid_output_wire -- output.wire
);
salt_avalon_st_source_ready : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_ready.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_source_ready_output_wire -- output.wire
);
salt_avalon_mm_slave_write : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-MM+Slave_write.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_write_output_wire -- output.wire
);
salt_avalon_st_sink_startofpacket : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_startofpacket.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_startofpacket_output_wire -- output.wire
);
capture_avalon_st_source_valid : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_valid.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_valid_wire -- input.wire
);
capture_avalon_st_source_endofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_endofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_endofpacket_wire -- input.wire
);
capture_avalon_st_source_startofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_startofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_startofpacket_wire -- input.wire
);
capture_avalon_st_sink_ready : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_ready.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_sink_ready_wire -- input.wire
);
capture_avalon_st_source_data : component alt_dspbuilder_testbench_capture_GNHCRI5YMO
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_data.capture.msim",
DSPBTYPE => "UINT [24, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_data_wire -- input.wire
);
clock_clock_output_reset_ports_inv <= not clock_clock_output_reset;
end architecture rtl; -- of tb_Gray_Binarization
|
-- tb_Gray_Binarization.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:20:48
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Gray_Binarization is
end entity tb_Gray_Binarization;
architecture rtl of tb_Gray_Binarization is
component Gray_Binarization_GN is
port (
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset_n
Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
Avalon_ST_Sink_endofpacket : in std_logic := 'X'; -- wire
Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
Avalon_ST_Source_valid : out std_logic; -- wire
Avalon_ST_Sink_valid : in std_logic := 'X'; -- wire
Avalon_ST_Source_endofpacket : out std_logic; -- wire
Avalon_ST_Source_startofpacket : out std_logic; -- wire
Avalon_ST_Source_ready : in std_logic := 'X'; -- wire
Avalon_MM_Slave_write : in std_logic := 'X'; -- wire
Avalon_ST_Sink_ready : out std_logic; -- wire
Avalon_ST_Sink_startofpacket : in std_logic := 'X'; -- wire
Avalon_ST_Source_data : out std_logic_vector(23 downto 0) -- wire
);
end component Gray_Binarization_GN;
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic; -- reset
clock_out : out std_logic; -- clk
reg_aclr_out : out std_logic; -- reset
tb_aclr : out std_logic -- reset
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
component alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GNOXVOQUET;
component alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic -- wire
);
end component alt_dspbuilder_testbench_salt_GNDBMPYDND;
component alt_dspbuilder_testbench_salt_GN6DKNTQ5M is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN6DKNTQ5M;
component alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN7Z4SHGOK;
component alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_testbench_capture_GNQX2JTRTZ;
component alt_dspbuilder_testbench_capture_GNHCRI5YMO is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_testbench_capture_GNHCRI5YMO;
signal salt_avalon_st_sink_data_output_wire : std_logic_vector(23 downto 0); -- salt_Avalon_ST_Sink_data:output -> dut:Avalon_ST_Sink_data
signal clock_clock_tb_reset : std_logic; -- Clock:tb_aclr -> [salt_Avalon_MM_Slave_address:aclr, salt_Avalon_MM_Slave_write:aclr, salt_Avalon_MM_Slave_writedata:aclr, salt_Avalon_ST_Sink_data:aclr, salt_Avalon_ST_Sink_endofpacket:aclr, salt_Avalon_ST_Sink_startofpacket:aclr, salt_Avalon_ST_Sink_valid:aclr, salt_Avalon_ST_Source_ready:aclr]
signal clock_clock_tb_clk : std_logic; -- Clock:clock_out -> [capture_Avalon_ST_Sink_ready:clock, capture_Avalon_ST_Source_data:clock, capture_Avalon_ST_Source_endofpacket:clock, capture_Avalon_ST_Source_startofpacket:clock, capture_Avalon_ST_Source_valid:clock, dut:Clock, salt_Avalon_MM_Slave_address:clock, salt_Avalon_MM_Slave_write:clock, salt_Avalon_MM_Slave_writedata:clock, salt_Avalon_ST_Sink_data:clock, salt_Avalon_ST_Sink_endofpacket:clock, salt_Avalon_ST_Sink_startofpacket:clock, salt_Avalon_ST_Sink_valid:clock, salt_Avalon_ST_Source_ready:clock]
signal salt_avalon_st_sink_endofpacket_output_wire : std_logic; -- salt_Avalon_ST_Sink_endofpacket:output -> dut:Avalon_ST_Sink_endofpacket
signal salt_avalon_mm_slave_address_output_wire : std_logic_vector(1 downto 0); -- salt_Avalon_MM_Slave_address:output -> dut:Avalon_MM_Slave_address
signal salt_avalon_mm_slave_writedata_output_wire : std_logic_vector(31 downto 0); -- salt_Avalon_MM_Slave_writedata:output -> dut:Avalon_MM_Slave_writedata
signal salt_avalon_st_sink_valid_output_wire : std_logic; -- salt_Avalon_ST_Sink_valid:output -> dut:Avalon_ST_Sink_valid
signal salt_avalon_st_source_ready_output_wire : std_logic; -- salt_Avalon_ST_Source_ready:output -> dut:Avalon_ST_Source_ready
signal salt_avalon_mm_slave_write_output_wire : std_logic; -- salt_Avalon_MM_Slave_write:output -> dut:Avalon_MM_Slave_write
signal salt_avalon_st_sink_startofpacket_output_wire : std_logic; -- salt_Avalon_ST_Sink_startofpacket:output -> dut:Avalon_ST_Sink_startofpacket
signal dut_avalon_st_source_valid_wire : std_logic; -- dut:Avalon_ST_Source_valid -> capture_Avalon_ST_Source_valid:input
signal clock_clock_reg_reset_reset : std_logic; -- Clock:reg_aclr_out -> [capture_Avalon_ST_Sink_ready:aclr, capture_Avalon_ST_Source_data:aclr, capture_Avalon_ST_Source_endofpacket:aclr, capture_Avalon_ST_Source_startofpacket:aclr, capture_Avalon_ST_Source_valid:aclr]
signal dut_avalon_st_source_endofpacket_wire : std_logic; -- dut:Avalon_ST_Source_endofpacket -> capture_Avalon_ST_Source_endofpacket:input
signal dut_avalon_st_source_startofpacket_wire : std_logic; -- dut:Avalon_ST_Source_startofpacket -> capture_Avalon_ST_Source_startofpacket:input
signal dut_avalon_st_sink_ready_wire : std_logic; -- dut:Avalon_ST_Sink_ready -> capture_Avalon_ST_Sink_ready:input
signal dut_avalon_st_source_data_wire : std_logic_vector(23 downto 0); -- dut:Avalon_ST_Source_data -> capture_Avalon_ST_Source_data:input
signal clock_clock_output_reset : std_logic; -- Clock:aclr_out -> clock_clock_output_reset:in
signal clock_clock_output_reset_ports_inv : std_logic; -- clock_clock_output_reset:inv -> dut:aclr
begin
dut : component Gray_Binarization_GN
port map (
Clock => clock_clock_tb_clk, -- Clock.clk
aclr => clock_clock_output_reset_ports_inv, -- .reset_n
Avalon_ST_Sink_data => salt_avalon_st_sink_data_output_wire, -- Avalon_ST_Sink_data.wire
Avalon_ST_Sink_endofpacket => salt_avalon_st_sink_endofpacket_output_wire, -- Avalon_ST_Sink_endofpacket.wire
Avalon_MM_Slave_address => salt_avalon_mm_slave_address_output_wire, -- Avalon_MM_Slave_address.wire
Avalon_MM_Slave_writedata => salt_avalon_mm_slave_writedata_output_wire, -- Avalon_MM_Slave_writedata.wire
Avalon_ST_Source_valid => dut_avalon_st_source_valid_wire, -- Avalon_ST_Source_valid.wire
Avalon_ST_Sink_valid => salt_avalon_st_sink_valid_output_wire, -- Avalon_ST_Sink_valid.wire
Avalon_ST_Source_endofpacket => dut_avalon_st_source_endofpacket_wire, -- Avalon_ST_Source_endofpacket.wire
Avalon_ST_Source_startofpacket => dut_avalon_st_source_startofpacket_wire, -- Avalon_ST_Source_startofpacket.wire
Avalon_ST_Source_ready => salt_avalon_st_source_ready_output_wire, -- Avalon_ST_Source_ready.wire
Avalon_MM_Slave_write => salt_avalon_mm_slave_write_output_wire, -- Avalon_MM_Slave_write.wire
Avalon_ST_Sink_ready => dut_avalon_st_sink_ready_wire, -- Avalon_ST_Sink_ready.wire
Avalon_ST_Sink_startofpacket => salt_avalon_st_sink_startofpacket_output_wire, -- Avalon_ST_Sink_startofpacket.wire
Avalon_ST_Source_data => dut_avalon_st_source_data_wire -- Avalon_ST_Source_data.wire
);
clock : component alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map (
SIMULATION_START_CYCLE => 5,
RESET_LATENCY => 0,
RESET_REGISTER_CASCADE_DEPTH => 0
)
port map (
clock_out => clock_clock_tb_clk, -- clock_tb.clk
tb_aclr => clock_clock_tb_reset, -- .reset
aclr_out => clock_clock_output_reset, -- clock_output.reset
reg_aclr_out => clock_clock_reg_reset_reset -- clock_reg_reset.reset
);
salt_avalon_st_sink_data : component alt_dspbuilder_testbench_salt_GNOXVOQUET
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_data.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_data_output_wire -- output.wire
);
salt_avalon_st_sink_endofpacket : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_endofpacket.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_endofpacket_output_wire -- output.wire
);
salt_avalon_mm_slave_address : component alt_dspbuilder_testbench_salt_GN6DKNTQ5M
generic map (
XFILE => "Gray%5FBinarization_Avalon-MM+Slave_address.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_address_output_wire -- output.wire
);
salt_avalon_mm_slave_writedata : component alt_dspbuilder_testbench_salt_GN7Z4SHGOK
generic map (
XFILE => "Gray%5FBinarization_Avalon-MM+Slave_writedata.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_writedata_output_wire -- output.wire
);
salt_avalon_st_sink_valid : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_valid.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_valid_output_wire -- output.wire
);
salt_avalon_st_source_ready : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_ready.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_source_ready_output_wire -- output.wire
);
salt_avalon_mm_slave_write : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-MM+Slave_write.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_write_output_wire -- output.wire
);
salt_avalon_st_sink_startofpacket : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_startofpacket.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_startofpacket_output_wire -- output.wire
);
capture_avalon_st_source_valid : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_valid.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_valid_wire -- input.wire
);
capture_avalon_st_source_endofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_endofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_endofpacket_wire -- input.wire
);
capture_avalon_st_source_startofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_startofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_startofpacket_wire -- input.wire
);
capture_avalon_st_sink_ready : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_ready.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_sink_ready_wire -- input.wire
);
capture_avalon_st_source_data : component alt_dspbuilder_testbench_capture_GNHCRI5YMO
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_data.capture.msim",
DSPBTYPE => "UINT [24, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_data_wire -- input.wire
);
clock_clock_output_reset_ports_inv <= not clock_clock_output_reset;
end architecture rtl; -- of tb_Gray_Binarization
|
library verilog;
use verilog.vl_types.all;
entity stratix_tx_outclk is
generic(
deserialization_factor: integer := 4;
bypass_serializer: string := "FALSE";
invert_clock : string := "FALSE";
use_falling_clock_edge: string := "FALSE"
);
port(
tx_in : in vl_logic_vector(9 downto 0);
tx_fastclk : in vl_logic;
tx_enable : in vl_logic;
tx_out : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of bypass_serializer : constant is 1;
attribute mti_svvh_generic_type of invert_clock : constant is 1;
attribute mti_svvh_generic_type of use_falling_clock_edge : constant is 1;
end stratix_tx_outclk;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1544.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01544ent IS
END c08s09b00x00p10n01i01544ent;
ARCHITECTURE c08s09b00x00p10n01i01544arch OF c08s09b00x00p10n01i01544ent IS
BEGIN
TESTING: PROCESS
variable counter : integer := 0;
BEGIN
for i in bit loop
counter := counter + 1;
end loop;
assert NOT(counter=bit'Pos(bit'High)-bit'Pos(bit'Low)+1)
report "***PASSED TEST: c08s09b00x00p10n01i01544"
severity NOTE;
assert (counter=bit'Pos(bit'High)-bit'Pos(bit'Low)+1)
report "***FAILED TEST: c08s09b00x00p10n01i01544 - The loop is executed once for each of the values in the range."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01544arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1544.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01544ent IS
END c08s09b00x00p10n01i01544ent;
ARCHITECTURE c08s09b00x00p10n01i01544arch OF c08s09b00x00p10n01i01544ent IS
BEGIN
TESTING: PROCESS
variable counter : integer := 0;
BEGIN
for i in bit loop
counter := counter + 1;
end loop;
assert NOT(counter=bit'Pos(bit'High)-bit'Pos(bit'Low)+1)
report "***PASSED TEST: c08s09b00x00p10n01i01544"
severity NOTE;
assert (counter=bit'Pos(bit'High)-bit'Pos(bit'Low)+1)
report "***FAILED TEST: c08s09b00x00p10n01i01544 - The loop is executed once for each of the values in the range."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01544arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1544.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01544ent IS
END c08s09b00x00p10n01i01544ent;
ARCHITECTURE c08s09b00x00p10n01i01544arch OF c08s09b00x00p10n01i01544ent IS
BEGIN
TESTING: PROCESS
variable counter : integer := 0;
BEGIN
for i in bit loop
counter := counter + 1;
end loop;
assert NOT(counter=bit'Pos(bit'High)-bit'Pos(bit'Low)+1)
report "***PASSED TEST: c08s09b00x00p10n01i01544"
severity NOTE;
assert (counter=bit'Pos(bit'High)-bit'Pos(bit'Low)+1)
report "***FAILED TEST: c08s09b00x00p10n01i01544 - The loop is executed once for each of the values in the range."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01544arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1921.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01921ent IS
END c07s02b01x00p01n01i01921ent;
ARCHITECTURE c07s02b01x00p01n01i01921arch OF c07s02b01x00p01n01i01921ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := b1 and b1;
assert NOT(b1 = TRUE)
report "***PASSED TEST: c07s02b01x00p01n01i01921"
severity NOTE;
assert (b1 = TRUE)
report "***FAILED TEST: c07s02b01x00p01n01i01921 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01921arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1921.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01921ent IS
END c07s02b01x00p01n01i01921ent;
ARCHITECTURE c07s02b01x00p01n01i01921arch OF c07s02b01x00p01n01i01921ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := b1 and b1;
assert NOT(b1 = TRUE)
report "***PASSED TEST: c07s02b01x00p01n01i01921"
severity NOTE;
assert (b1 = TRUE)
report "***FAILED TEST: c07s02b01x00p01n01i01921 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01921arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1921.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01921ent IS
END c07s02b01x00p01n01i01921ent;
ARCHITECTURE c07s02b01x00p01n01i01921arch OF c07s02b01x00p01n01i01921ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := b1 and b1;
assert NOT(b1 = TRUE)
report "***PASSED TEST: c07s02b01x00p01n01i01921"
severity NOTE;
assert (b1 = TRUE)
report "***FAILED TEST: c07s02b01x00p01n01i01921 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01921arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb888_to_rgb565:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb888_to_rgb565_0_0 IS
PORT (
rgb_888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_565 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_rgb888_to_rgb565_0_0;
ARCHITECTURE system_rgb888_to_rgb565_0_0_arch OF system_rgb888_to_rgb565_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb888_to_rgb565_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb888_to_rgb565 IS
PORT (
rgb_888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_565 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT rgb888_to_rgb565;
BEGIN
U0 : rgb888_to_rgb565
PORT MAP (
rgb_888 => rgb_888,
rgb_565 => rgb_565
);
END system_rgb888_to_rgb565_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb888_to_rgb565:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb888_to_rgb565_0_0 IS
PORT (
rgb_888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_565 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_rgb888_to_rgb565_0_0;
ARCHITECTURE system_rgb888_to_rgb565_0_0_arch OF system_rgb888_to_rgb565_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb888_to_rgb565_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb888_to_rgb565 IS
PORT (
rgb_888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_565 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT rgb888_to_rgb565;
BEGIN
U0 : rgb888_to_rgb565
PORT MAP (
rgb_888 => rgb_888,
rgb_565 => rgb_565
);
END system_rgb888_to_rgb565_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb888_to_rgb565:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb888_to_rgb565_0_0 IS
PORT (
rgb_888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_565 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_rgb888_to_rgb565_0_0;
ARCHITECTURE system_rgb888_to_rgb565_0_0_arch OF system_rgb888_to_rgb565_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb888_to_rgb565_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb888_to_rgb565 IS
PORT (
rgb_888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_565 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT rgb888_to_rgb565;
BEGIN
U0 : rgb888_to_rgb565
PORT MAP (
rgb_888 => rgb_888,
rgb_565 => rgb_565
);
END system_rgb888_to_rgb565_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb888_to_rgb565:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb888_to_rgb565_0_0 IS
PORT (
rgb_888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_565 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_rgb888_to_rgb565_0_0;
ARCHITECTURE system_rgb888_to_rgb565_0_0_arch OF system_rgb888_to_rgb565_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb888_to_rgb565_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb888_to_rgb565 IS
PORT (
rgb_888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_565 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT rgb888_to_rgb565;
BEGIN
U0 : rgb888_to_rgb565
PORT MAP (
rgb_888 => rgb_888,
rgb_565 => rgb_565
);
END system_rgb888_to_rgb565_0_0_arch;
|
--------------------------------------------------------------------------------
--! @file control_interface.vhd
--! @brief Control Interface
--! \verbatim
--! Author : JS <jschamba@physics.utexas.edu>
--! Company : University of Texas at Austin
--! Created : 2013-06-12
--! Last update: 2016-12-25
--! Description: Read words from command FIFO and interpret
--! This defines some example interfaces at different addresses:
--! Address 32 - 63: 16bit Configuration registers
--! These registers can be written and read.
--! Could be used to define operations parameters
--! Address 11: 16bit Pulse REGISTER
--! This register generates a pulse at the bits
--! set to 1 that is 3 clocks wide
--! Could be used to start some action, e.g. jtag
--! Address 0 - 10: 16bit Status registers
--! These are read-only.
--! Can be used to read the status of some external
--! device, .e.g an ADC, or input pins.
--! Address 16 - 20: 32bit memory interface
--! The idea is to write an address into 17 (LSB)
--! and 18 (MSB)
--! Then write the LSB16 into 19, and finally
--! the MSB16 into 20. On write to 20, the 32bit
--! data in 19 and 20 is written to the memory, AND
--! the address is auto-incremented, so that the NEXT
--! write seuqence doesn't need to re-write the address.
--! A Read on 20 reads the current address and returns
--! a 32bit data word into the FIFO, then increases
--! the memory. This read is repeated n times, where
--! "n" is the 16bit value at address 16.
--! Address 25: This address initiates a read from the DATA_FIFO
--! The value written `n' indicates the number of
--! words to copy from the DATA_FIFO to the FIFO.
--! Write `n' will result in n+1 words to be transferred.
--! Will wait indefinitely for all words to be transferred
--! should FIFOs stay in empty/full state.
--!
--! Revisions :
--! Date Version Author Description
--! 2013-06-12 1.0 jschamba Created
--! 2013-10-21 1.1 thorsten changed memory address space to 32 bit
--! added an interface to read a data fifo
--! 2016-12-25 ymei Adapt to FWFT FIFO
--! \endverbatim
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- Entity Declaration
ENTITY control_interface IS
PORT (
RESET : IN std_logic;
CLK : IN std_logic; -- system clock
-- From FPGA to PC
FIFO_Q : OUT std_logic_vector(35 DOWNTO 0); -- interface fifo data output port
FIFO_EMPTY : OUT std_logic; -- interface fifo "emtpy" signal
FIFO_RDREQ : IN std_logic; -- interface fifo read request
FIFO_RDCLK : IN std_logic; -- interface fifo read clock
-- From PC to FPGA, FWFT
CMD_FIFO_Q : IN std_logic_vector(35 DOWNTO 0); -- interface command fifo data out port
CMD_FIFO_EMPTY : IN std_logic; -- interface command fifo "emtpy" signal
CMD_FIFO_RDREQ : OUT std_logic; -- interface command fifo read request
-- Digital I/O
CONFIG_REG : OUT std_logic_vector(511 DOWNTO 0); -- thirtytwo 16bit registers
PULSE_REG : OUT std_logic_vector(15 DOWNTO 0); -- 16bit pulse register
STATUS_REG : IN std_logic_vector(175 DOWNTO 0); -- eleven 16bit registers
-- Memory interface
MEM_WE : OUT std_logic; -- memory write enable
MEM_ADDR : OUT std_logic_vector(31 DOWNTO 0);
MEM_DIN : OUT std_logic_vector(31 DOWNTO 0); -- memory data input
MEM_DOUT : IN std_logic_vector(31 DOWNTO 0); -- memory data output
-- Data FIFO interface, FWFT
DATA_FIFO_Q : IN std_logic_vector(31 DOWNTO 0);
DATA_FIFO_EMPTY : IN std_logic;
DATA_FIFO_RDREQ : OUT std_logic;
DATA_FIFO_RDCLK : OUT std_logic
);
END control_interface;
-- Architecture body
ARCHITECTURE a OF control_interface IS
COMPONENT fifo36x512
PORT (
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(35 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(35 DOWNTO 0);
full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
-- signals for FIFO
SIGNAL bMemNotReg : integer;
CONSTANT SEL_REG : integer := 0;
CONSTANT SEL_MEM : integer := 1;
CONSTANT SEL_FIFO : integer := 2;
SIGNAL sFifoD : std_logic_vector(35 DOWNTO 0);
SIGNAL sFifoFull : std_logic;
SIGNAL sFifoWren : std_logic;
SIGNAL sFifoWrreq : std_logic;
SIGNAL sFifoRst : std_logic;
SIGNAL sFifoClk : std_logic;
-- signals for single-port RAM
SIGNAL sWea : std_logic;
SIGNAL sAddrA : unsigned(31 DOWNTO 0);
SIGNAL sDinA : std_logic_vector(31 DOWNTO 0);
SIGNAL sDoutA : std_logic_vector(31 DOWNTO 0);
SIGNAL sDinReg : std_logic_vector(15 DOWNTO 0);
SIGNAL sMemioCnt : std_logic_vector(15 DOWNTO 0);
SIGNAL sMemLatch : std_logic_vector(31 DOWNTO 0);
-- Configuration registers: 8 x 16bit
SIGNAL sConfigReg : std_logic_vector(511 DOWNTO 0);
SIGNAL sPulseReg : std_logic_vector(15 DOWNTO 0);
SIGNAL sRegOut : std_logic_vector(15 DOWNTO 0);
-- signals for FIFO read
-- to read data from a FIFO
SIGNAL sDataFifoCount : std_logic_vector(15 DOWNTO 0);
-- State machine variable
TYPE cmdState_t IS (
INIT,
WAIT_CMD,
GET_CMD,
INTERPRET_CMD,
MEM_ADV,
MEM_RD_CNT,
PULSE_DELAY,
FIFO_ADV
);
SIGNAL cmdState : cmdState_t;
BEGIN
CONFIG_REG <= sConfigReg;
PULSE_REG <= sPulseReg;
MEM_WE <= sWea;
MEM_ADDR <= std_logic_vector(sAddrA);
MEM_DIN <= sDinA;
sDoutA <= MEM_DOUT;
-- memory input
sDinA(15 DOWNTO 0) <= sDinReg;
-- When FWFT FIFO is used, high 16 bits have to be registered by a cycled.
PROCESS (CLK) IS
BEGIN
IF rising_edge(CLK) THEN
sDinA(31 DOWNTO 16) <= CMD_FIFO_Q(15 DOWNTO 0);
END IF;
END PROCESS;
-- data fifo
DATA_FIFO_RDCLK <= CLK;
-- data/event FIFO
sFifoRst <= RESET;
sFifoClk <= CLK;
data_fifo : fifo36x512
PORT MAP (
rst => sFifoRst,
wr_clk => sFifoClk,
rd_clk => FIFO_RDCLK,
din => sFifoD,
wr_en => sFifoWren,
rd_en => FIFO_RDREQ,
dout => FIFO_Q,
full => sFifoFull,
empty => FIFO_EMPTY
);
sFifoD(35 DOWNTO 32) <= (OTHERS => '0'); -- these bits not used
sFifoD(31 DOWNTO 0) <= MEM_DOUT WHEN bMemNotReg = SEL_MEM ELSE
DATA_FIFO_Q WHEN bMemNotReg = SEL_FIFO ELSE
x"0000" & sRegOut;
sFifoWren <= (NOT DATA_FIFO_EMPTY) WHEN bMemNotReg = SEL_FIFO
ELSE sFifoWrreq;
DATA_FIFO_RDREQ <= (NOT sFifoFull) WHEN bMemNotReg = SEL_FIFO
ELSE '0';
cmdIF_inst : PROCESS (CLK, RESET) IS
VARIABLE counterV : integer RANGE 0 TO 65535 := 0;
VARIABLE address_i : integer RANGE 0 TO 4095 := 0;
VARIABLE counterFIFO : integer RANGE 0 TO 65535 := 0;
BEGIN
IF RESET = '1' THEN
counterV := 0;
cmdState <= INIT;
CMD_FIFO_RDREQ <= '0';
sConfigReg <= (OTHERS => '0');
sPulseReg <= (OTHERS => '0');
sDinReg <= (OTHERS => '0');
sMemioCnt <= (OTHERS => '0');
sWea <= '0';
sAddrA <= (OTHERS => '0');
bMemNotReg <= SEL_REG;
ELSIF rising_edge(CLK) THEN
-- defaults:
CMD_FIFO_RDREQ <= '0';
sFifoWrreq <= '0';
sWea <= '0';
sRegOut <= (OTHERS => '0');
CASE cmdState IS
-- //// initialize registers to some sensible values
WHEN INIT =>
-- currently all 0
sConfigReg <= (OTHERS => '0');
sPulseReg <= (OTHERS => '0');
sAddrA <= (OTHERS => '0');
-- at least 1 memory read
sMemioCnt <= x"0001";
cmdState <= WAIT_CMD;
-- //// Wait for CMD_FIFO words
WHEN WAIT_CMD =>
bMemNotReg <= SEL_REG; -- output registers
sPulseReg <= (OTHERS => '0'); -- reset pulse REGISTER
-- wait for FIFO not empty
IF CMD_FIFO_EMPTY = '0' THEN
CMD_FIFO_RDREQ <= '1';
cmdState <= INTERPRET_CMD; -- GET_CMD;
END IF;
-- //// one wait state to get next CMD_FIFO word
-- When FWFT FIFO is used, this state should be skipped.
-- WHEN GET_CMD =>
-- cmdState <= INTERPRET_CMD;
-- //// Now interpret the current CMD_FIFO output
WHEN INTERPRET_CMD =>
---------------------------------------------------------------------
-- CMD_FIFO_Q format:
-- Q(31) : READ/NOT_WRITE
-- Q(30:28) : not used
-- Q(27:16) : ADDRESS
-- Q(15:0) : DATA
---------------------------------------------------------------------
--address_i := conv_integer(unsigned(CMD_FIFO_Q(27 DOWNTO 16)));
address_i := to_integer(unsigned(CMD_FIFO_Q(27 DOWNTO 16)));
IF CMD_FIFO_Q(31) = '1' THEN
-- //// a READ transaction ////////
CASE address_i IS
WHEN 32 TO 63 => -- CONFIG_REG
sRegOut <= sConfigReg((address_i-32)*16+15 DOWNTO
(address_i-32)*16);
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 0 TO 10 => -- STATUS_REG
sRegOut <= STATUS_REG(address_i*16+15 DOWNTO address_i*16);
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 16 => -- memory count REGISTER
sRegOut <= sMemioCnt;
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 17 => -- memory address LSB REGISTER
sRegOut <= std_logic_vector(sAddrA (15 DOWNTO 0));
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 18 => -- memory address MSB REGISTER
sRegOut <= std_logic_vector(sAddrA (31 DOWNTO 16));
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 20 => -- read sMemioCnt 32bit memory words
-- reads 32bit memory words starting at the current
-- address sAddrA
counterV := to_integer(unsigned(sMemioCnt));
bMemNotReg <= SEL_MEM; -- switch FIFO input to memory output
IF sFifoFull = '0' THEN
sFifoWrreq <= '1'; -- latch current memory output
sAddrA <= sAddrA + 1; -- and advance the address
cmdState <= MEM_RD_CNT;
END IF;
WHEN OTHERS => -- bad address, return FFFF
sRegOut <= (OTHERS => '1');
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
END CASE;
ELSE
-- //// a WRITE transaction ////////
CASE address_i IS
WHEN 32 TO 63 => -- CONFIG_REG
sConfigReg((address_i-32)*16+15 DOWNTO
(address_i-32)*16) <= CMD_FIFO_Q(15 DOWNTO 0);
cmdState <= WAIT_CMD;
WHEN 11 => -- PULSE_REG
sPulseReg <= CMD_FIFO_Q(15 DOWNTO 0);
counterV := 2; -- 60ns
cmdState <= PULSE_DELAY;
WHEN 16 => -- memory count REGISTER
sMemioCnt <= CMD_FIFO_Q(15 DOWNTO 0);
cmdState <= WAIT_CMD;
WHEN 17 => -- memory address LSB REGISTER
sAddrA (15 DOWNTO 0) <= unsigned(CMD_FIFO_Q(15 DOWNTO 0));
cmdState <= WAIT_CMD;
WHEN 18 => -- memory address MSB REGISTER
--sAddrA <= CMD_FIFO_Q(15 DOWNTO 0);
sAddrA (31 DOWNTO 16) <= unsigned(CMD_FIFO_Q(15 DOWNTO 0));
cmdState <= WAIT_CMD;
WHEN 19 => -- memory LS16B
sDinReg <= CMD_FIFO_Q(15 DOWNTO 0);
cmdState <= WAIT_CMD;
WHEN 20 => -- memory MS16B
-- raise WriteEnable for one clock, which clocks IN
-- register 18 as LS16B and the data content of
-- the CMD_FIFO word as MS16B
sWea <= '1';
cmdState <= MEM_ADV;
WHEN 25 => -- Data Fifo read count
counterFIFO := to_integer(unsigned(CMD_FIFO_Q(15 DOWNTO 0)));
bMemNotReg <= SEL_FIFO;
cmdState <= FIFO_ADV;
WHEN OTHERS => -- bad address, do nothing
cmdState <= WAIT_CMD;
END CASE;
END IF;
-- //// advance memory address
WHEN MEM_ADV =>
sAddrA <= sAddrA + 1;
cmdState <= WAIT_CMD;
-- //// read sMemioCnt memory addresses
WHEN MEM_RD_CNT =>
counterV := counterV - 1;
-- wait for FIFO not FULL
IF (counterV = 0) THEN
-- Done
cmdState <= WAIT_CMD;
ELSIF sFifoFull = '0' THEN
-- latch current memory output
sFifoWrreq <= '1';
-- and advance address
sAddrA <= sAddrA + 1;
cmdState <= MEM_RD_CNT;
ELSE
-- FIFO Full:
-- go back to previous count and wait for FIFO not full
counterV := counterV + 1;
cmdState <= MEM_RD_CNT;
END IF;
-- //// delay two clocks to keep pulse high (total 3 clocks)
WHEN PULSE_DELAY =>
counterV := counterV - 1;
IF (counterV = 0) THEN
cmdState <= WAIT_CMD;
END IF;
-- //// Data FIFO read
WHEN FIFO_ADV =>
-- read data fifo, write reads to output fifo
-- exit when enough words were transferred
bMemNotReg <= SEL_FIFO;
cmdState <= FIFO_ADV;
IF (DATA_FIFO_EMPTY = '0') AND (sFifoFull = '0') THEN
IF counterFIFO = 0 THEN
-- we are done.
bMemNotReg <= SEL_REG;
cmdState <= WAIT_CMD;
ELSE
-- reduce the counter.
counterFIFO := counterFIFO - 1;
END IF;
END IF;
-- //// shouldn't happen
WHEN OTHERS =>
cmdState <= WAIT_CMD;
END CASE;
END IF;
END PROCESS cmdIF_inst;
END a;
|
--------------------------------------------------------------------------------
--! @file control_interface.vhd
--! @brief Control Interface
--! \verbatim
--! Author : JS <jschamba@physics.utexas.edu>
--! Company : University of Texas at Austin
--! Created : 2013-06-12
--! Last update: 2016-12-25
--! Description: Read words from command FIFO and interpret
--! This defines some example interfaces at different addresses:
--! Address 32 - 63: 16bit Configuration registers
--! These registers can be written and read.
--! Could be used to define operations parameters
--! Address 11: 16bit Pulse REGISTER
--! This register generates a pulse at the bits
--! set to 1 that is 3 clocks wide
--! Could be used to start some action, e.g. jtag
--! Address 0 - 10: 16bit Status registers
--! These are read-only.
--! Can be used to read the status of some external
--! device, .e.g an ADC, or input pins.
--! Address 16 - 20: 32bit memory interface
--! The idea is to write an address into 17 (LSB)
--! and 18 (MSB)
--! Then write the LSB16 into 19, and finally
--! the MSB16 into 20. On write to 20, the 32bit
--! data in 19 and 20 is written to the memory, AND
--! the address is auto-incremented, so that the NEXT
--! write seuqence doesn't need to re-write the address.
--! A Read on 20 reads the current address and returns
--! a 32bit data word into the FIFO, then increases
--! the memory. This read is repeated n times, where
--! "n" is the 16bit value at address 16.
--! Address 25: This address initiates a read from the DATA_FIFO
--! The value written `n' indicates the number of
--! words to copy from the DATA_FIFO to the FIFO.
--! Write `n' will result in n+1 words to be transferred.
--! Will wait indefinitely for all words to be transferred
--! should FIFOs stay in empty/full state.
--!
--! Revisions :
--! Date Version Author Description
--! 2013-06-12 1.0 jschamba Created
--! 2013-10-21 1.1 thorsten changed memory address space to 32 bit
--! added an interface to read a data fifo
--! 2016-12-25 ymei Adapt to FWFT FIFO
--! \endverbatim
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- Entity Declaration
ENTITY control_interface IS
PORT (
RESET : IN std_logic;
CLK : IN std_logic; -- system clock
-- From FPGA to PC
FIFO_Q : OUT std_logic_vector(35 DOWNTO 0); -- interface fifo data output port
FIFO_EMPTY : OUT std_logic; -- interface fifo "emtpy" signal
FIFO_RDREQ : IN std_logic; -- interface fifo read request
FIFO_RDCLK : IN std_logic; -- interface fifo read clock
-- From PC to FPGA, FWFT
CMD_FIFO_Q : IN std_logic_vector(35 DOWNTO 0); -- interface command fifo data out port
CMD_FIFO_EMPTY : IN std_logic; -- interface command fifo "emtpy" signal
CMD_FIFO_RDREQ : OUT std_logic; -- interface command fifo read request
-- Digital I/O
CONFIG_REG : OUT std_logic_vector(511 DOWNTO 0); -- thirtytwo 16bit registers
PULSE_REG : OUT std_logic_vector(15 DOWNTO 0); -- 16bit pulse register
STATUS_REG : IN std_logic_vector(175 DOWNTO 0); -- eleven 16bit registers
-- Memory interface
MEM_WE : OUT std_logic; -- memory write enable
MEM_ADDR : OUT std_logic_vector(31 DOWNTO 0);
MEM_DIN : OUT std_logic_vector(31 DOWNTO 0); -- memory data input
MEM_DOUT : IN std_logic_vector(31 DOWNTO 0); -- memory data output
-- Data FIFO interface, FWFT
DATA_FIFO_Q : IN std_logic_vector(31 DOWNTO 0);
DATA_FIFO_EMPTY : IN std_logic;
DATA_FIFO_RDREQ : OUT std_logic;
DATA_FIFO_RDCLK : OUT std_logic
);
END control_interface;
-- Architecture body
ARCHITECTURE a OF control_interface IS
COMPONENT fifo36x512
PORT (
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(35 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(35 DOWNTO 0);
full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
-- signals for FIFO
SIGNAL bMemNotReg : integer;
CONSTANT SEL_REG : integer := 0;
CONSTANT SEL_MEM : integer := 1;
CONSTANT SEL_FIFO : integer := 2;
SIGNAL sFifoD : std_logic_vector(35 DOWNTO 0);
SIGNAL sFifoFull : std_logic;
SIGNAL sFifoWren : std_logic;
SIGNAL sFifoWrreq : std_logic;
SIGNAL sFifoRst : std_logic;
SIGNAL sFifoClk : std_logic;
-- signals for single-port RAM
SIGNAL sWea : std_logic;
SIGNAL sAddrA : unsigned(31 DOWNTO 0);
SIGNAL sDinA : std_logic_vector(31 DOWNTO 0);
SIGNAL sDoutA : std_logic_vector(31 DOWNTO 0);
SIGNAL sDinReg : std_logic_vector(15 DOWNTO 0);
SIGNAL sMemioCnt : std_logic_vector(15 DOWNTO 0);
SIGNAL sMemLatch : std_logic_vector(31 DOWNTO 0);
-- Configuration registers: 8 x 16bit
SIGNAL sConfigReg : std_logic_vector(511 DOWNTO 0);
SIGNAL sPulseReg : std_logic_vector(15 DOWNTO 0);
SIGNAL sRegOut : std_logic_vector(15 DOWNTO 0);
-- signals for FIFO read
-- to read data from a FIFO
SIGNAL sDataFifoCount : std_logic_vector(15 DOWNTO 0);
-- State machine variable
TYPE cmdState_t IS (
INIT,
WAIT_CMD,
GET_CMD,
INTERPRET_CMD,
MEM_ADV,
MEM_RD_CNT,
PULSE_DELAY,
FIFO_ADV
);
SIGNAL cmdState : cmdState_t;
BEGIN
CONFIG_REG <= sConfigReg;
PULSE_REG <= sPulseReg;
MEM_WE <= sWea;
MEM_ADDR <= std_logic_vector(sAddrA);
MEM_DIN <= sDinA;
sDoutA <= MEM_DOUT;
-- memory input
sDinA(15 DOWNTO 0) <= sDinReg;
-- When FWFT FIFO is used, high 16 bits have to be registered by a cycled.
PROCESS (CLK) IS
BEGIN
IF rising_edge(CLK) THEN
sDinA(31 DOWNTO 16) <= CMD_FIFO_Q(15 DOWNTO 0);
END IF;
END PROCESS;
-- data fifo
DATA_FIFO_RDCLK <= CLK;
-- data/event FIFO
sFifoRst <= RESET;
sFifoClk <= CLK;
data_fifo : fifo36x512
PORT MAP (
rst => sFifoRst,
wr_clk => sFifoClk,
rd_clk => FIFO_RDCLK,
din => sFifoD,
wr_en => sFifoWren,
rd_en => FIFO_RDREQ,
dout => FIFO_Q,
full => sFifoFull,
empty => FIFO_EMPTY
);
sFifoD(35 DOWNTO 32) <= (OTHERS => '0'); -- these bits not used
sFifoD(31 DOWNTO 0) <= MEM_DOUT WHEN bMemNotReg = SEL_MEM ELSE
DATA_FIFO_Q WHEN bMemNotReg = SEL_FIFO ELSE
x"0000" & sRegOut;
sFifoWren <= (NOT DATA_FIFO_EMPTY) WHEN bMemNotReg = SEL_FIFO
ELSE sFifoWrreq;
DATA_FIFO_RDREQ <= (NOT sFifoFull) WHEN bMemNotReg = SEL_FIFO
ELSE '0';
cmdIF_inst : PROCESS (CLK, RESET) IS
VARIABLE counterV : integer RANGE 0 TO 65535 := 0;
VARIABLE address_i : integer RANGE 0 TO 4095 := 0;
VARIABLE counterFIFO : integer RANGE 0 TO 65535 := 0;
BEGIN
IF RESET = '1' THEN
counterV := 0;
cmdState <= INIT;
CMD_FIFO_RDREQ <= '0';
sConfigReg <= (OTHERS => '0');
sPulseReg <= (OTHERS => '0');
sDinReg <= (OTHERS => '0');
sMemioCnt <= (OTHERS => '0');
sWea <= '0';
sAddrA <= (OTHERS => '0');
bMemNotReg <= SEL_REG;
ELSIF rising_edge(CLK) THEN
-- defaults:
CMD_FIFO_RDREQ <= '0';
sFifoWrreq <= '0';
sWea <= '0';
sRegOut <= (OTHERS => '0');
CASE cmdState IS
-- //// initialize registers to some sensible values
WHEN INIT =>
-- currently all 0
sConfigReg <= (OTHERS => '0');
sPulseReg <= (OTHERS => '0');
sAddrA <= (OTHERS => '0');
-- at least 1 memory read
sMemioCnt <= x"0001";
cmdState <= WAIT_CMD;
-- //// Wait for CMD_FIFO words
WHEN WAIT_CMD =>
bMemNotReg <= SEL_REG; -- output registers
sPulseReg <= (OTHERS => '0'); -- reset pulse REGISTER
-- wait for FIFO not empty
IF CMD_FIFO_EMPTY = '0' THEN
CMD_FIFO_RDREQ <= '1';
cmdState <= INTERPRET_CMD; -- GET_CMD;
END IF;
-- //// one wait state to get next CMD_FIFO word
-- When FWFT FIFO is used, this state should be skipped.
-- WHEN GET_CMD =>
-- cmdState <= INTERPRET_CMD;
-- //// Now interpret the current CMD_FIFO output
WHEN INTERPRET_CMD =>
---------------------------------------------------------------------
-- CMD_FIFO_Q format:
-- Q(31) : READ/NOT_WRITE
-- Q(30:28) : not used
-- Q(27:16) : ADDRESS
-- Q(15:0) : DATA
---------------------------------------------------------------------
--address_i := conv_integer(unsigned(CMD_FIFO_Q(27 DOWNTO 16)));
address_i := to_integer(unsigned(CMD_FIFO_Q(27 DOWNTO 16)));
IF CMD_FIFO_Q(31) = '1' THEN
-- //// a READ transaction ////////
CASE address_i IS
WHEN 32 TO 63 => -- CONFIG_REG
sRegOut <= sConfigReg((address_i-32)*16+15 DOWNTO
(address_i-32)*16);
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 0 TO 10 => -- STATUS_REG
sRegOut <= STATUS_REG(address_i*16+15 DOWNTO address_i*16);
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 16 => -- memory count REGISTER
sRegOut <= sMemioCnt;
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 17 => -- memory address LSB REGISTER
sRegOut <= std_logic_vector(sAddrA (15 DOWNTO 0));
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 18 => -- memory address MSB REGISTER
sRegOut <= std_logic_vector(sAddrA (31 DOWNTO 16));
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 20 => -- read sMemioCnt 32bit memory words
-- reads 32bit memory words starting at the current
-- address sAddrA
counterV := to_integer(unsigned(sMemioCnt));
bMemNotReg <= SEL_MEM; -- switch FIFO input to memory output
IF sFifoFull = '0' THEN
sFifoWrreq <= '1'; -- latch current memory output
sAddrA <= sAddrA + 1; -- and advance the address
cmdState <= MEM_RD_CNT;
END IF;
WHEN OTHERS => -- bad address, return FFFF
sRegOut <= (OTHERS => '1');
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
END CASE;
ELSE
-- //// a WRITE transaction ////////
CASE address_i IS
WHEN 32 TO 63 => -- CONFIG_REG
sConfigReg((address_i-32)*16+15 DOWNTO
(address_i-32)*16) <= CMD_FIFO_Q(15 DOWNTO 0);
cmdState <= WAIT_CMD;
WHEN 11 => -- PULSE_REG
sPulseReg <= CMD_FIFO_Q(15 DOWNTO 0);
counterV := 2; -- 60ns
cmdState <= PULSE_DELAY;
WHEN 16 => -- memory count REGISTER
sMemioCnt <= CMD_FIFO_Q(15 DOWNTO 0);
cmdState <= WAIT_CMD;
WHEN 17 => -- memory address LSB REGISTER
sAddrA (15 DOWNTO 0) <= unsigned(CMD_FIFO_Q(15 DOWNTO 0));
cmdState <= WAIT_CMD;
WHEN 18 => -- memory address MSB REGISTER
--sAddrA <= CMD_FIFO_Q(15 DOWNTO 0);
sAddrA (31 DOWNTO 16) <= unsigned(CMD_FIFO_Q(15 DOWNTO 0));
cmdState <= WAIT_CMD;
WHEN 19 => -- memory LS16B
sDinReg <= CMD_FIFO_Q(15 DOWNTO 0);
cmdState <= WAIT_CMD;
WHEN 20 => -- memory MS16B
-- raise WriteEnable for one clock, which clocks IN
-- register 18 as LS16B and the data content of
-- the CMD_FIFO word as MS16B
sWea <= '1';
cmdState <= MEM_ADV;
WHEN 25 => -- Data Fifo read count
counterFIFO := to_integer(unsigned(CMD_FIFO_Q(15 DOWNTO 0)));
bMemNotReg <= SEL_FIFO;
cmdState <= FIFO_ADV;
WHEN OTHERS => -- bad address, do nothing
cmdState <= WAIT_CMD;
END CASE;
END IF;
-- //// advance memory address
WHEN MEM_ADV =>
sAddrA <= sAddrA + 1;
cmdState <= WAIT_CMD;
-- //// read sMemioCnt memory addresses
WHEN MEM_RD_CNT =>
counterV := counterV - 1;
-- wait for FIFO not FULL
IF (counterV = 0) THEN
-- Done
cmdState <= WAIT_CMD;
ELSIF sFifoFull = '0' THEN
-- latch current memory output
sFifoWrreq <= '1';
-- and advance address
sAddrA <= sAddrA + 1;
cmdState <= MEM_RD_CNT;
ELSE
-- FIFO Full:
-- go back to previous count and wait for FIFO not full
counterV := counterV + 1;
cmdState <= MEM_RD_CNT;
END IF;
-- //// delay two clocks to keep pulse high (total 3 clocks)
WHEN PULSE_DELAY =>
counterV := counterV - 1;
IF (counterV = 0) THEN
cmdState <= WAIT_CMD;
END IF;
-- //// Data FIFO read
WHEN FIFO_ADV =>
-- read data fifo, write reads to output fifo
-- exit when enough words were transferred
bMemNotReg <= SEL_FIFO;
cmdState <= FIFO_ADV;
IF (DATA_FIFO_EMPTY = '0') AND (sFifoFull = '0') THEN
IF counterFIFO = 0 THEN
-- we are done.
bMemNotReg <= SEL_REG;
cmdState <= WAIT_CMD;
ELSE
-- reduce the counter.
counterFIFO := counterFIFO - 1;
END IF;
END IF;
-- //// shouldn't happen
WHEN OTHERS =>
cmdState <= WAIT_CMD;
END CASE;
END IF;
END PROCESS cmdIF_inst;
END a;
|
--**********************************************************************************************
-- Frequency divider for AVR uC (40 MHz -> 4 MHz or 40 MHz -> 20 MHz)
-- Version 1.52(Dust Inc version)
-- Modified 16.01.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity FrqDiv is port(
clk_in : in std_logic;
clk_out : out std_logic
);
end FrqDiv;
architecture RTL of FrqDiv is
signal DivCnt : std_logic_vector(3 downto 0);
signal clk_out_int : std_logic;
constant Div2 : boolean := TRUE;
begin
-- Must be sequentially encoded
DivideBy10:if not Div2 generate
Gen:process(clk_in)
begin
if(clk_in='1' and clk_in'event) then -- Clock
if(DivCnt=x"4") then DivCnt <= x"0";
else DivCnt <= DivCnt + 1;
end if;
if(DivCnt=x"4") then clk_out_int <= not clk_out_int;
end if;
end if;
end process;
end generate;
DivideBy10:if Div2 generate
Gen:process(clk_in)
begin
if(clk_in='1' and clk_in'event) then -- Clock
clk_out_int <= not clk_out_int;
end if;
end process;
end generate;
clk_out <= clk_out_int;
end RTL;
|
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