content stringlengths 1 1.04M ⌀ |
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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12224)
`protect data_block
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VawuXttSCnOB6T5mBNITOGgdi6o5p84MxPc=
`protect end_protected
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: usbdcl
-- File: usbdcl.vhd
-- Author: Andreas Hansen
-- Modified: Marko Isomaki
-- Description: USB Debug Communication Link
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
use gaisler.usb.all;
library techmap;
use techmap.gencomp.all;
entity usbdcl is
generic (
hindex : integer := 0;
memtech : integer := DEFMEMTECH
);
port (
uclk : in std_ulogic;
usbi : in usb_in_type;
usbo : out usb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture bhv of usbdcl is
constant REVISION : amba_version_type := 0;
constant memibits : integer := 11;
constant memobits : integer := 11;
signal iri : usb_memi_in_type;
signal ori : usb_memo_in_type;
signal oraddr : std_logic_vector(memobits-1 downto 0);
signal iraddr : std_logic_vector(memibits-1 downto 0);
signal ordata : std_logic_vector(31 downto 0);
signal irdata : std_logic_vector(31 downto 0);
signal vcc : std_ulogic;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
component usbdclc is
port (
uclk : in std_ulogic;
usbi : in usb_in_type;
usbo : out usb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
iri : out usb_memi_in_type;
ori : out usb_memo_in_type;
dmai : out ahb_dma_in_type;
dmao : in ahb_dma_out_type;
oraddr : out std_logic_vector(10 downto 0);
iraddr : out std_logic_vector(10 downto 0);
ordata : in std_logic_vector(31 downto 0);
irdata : in std_logic_vector(31 downto 0)
);
end component;
begin
vcc <= '1';
u0 : usbdclc
port map ( uclk, usbi, usbo, hclk, hrst, iri,
ori, dmai, dmao, oraddr, iraddr, ordata, irdata);
inram : syncram_2p
generic map (memtech, memibits, 32, 1)
port map (
uclk, vcc, iraddr, irdata, hclk,
iri.wenable, iri.address, iri.din);
outram : syncram_2p
generic map (memtech, memobits, 32, 1)
port map (
hclk, vcc, oraddr, ordata, uclk,
ori.wenable, ori.address, ori.din);
ahbmst0 : ahbmst
generic map (incaddr => 0, hindex => hindex,
venid => VENDOR_GAISLER, devid => GAISLER_USBDCL)
port map (hrst, hclk, dmai, dmao, ahbi, ahbo);
-- pragma translate_off
bootmsg : report_version
generic map (
"grusb" & tost(hindex) & ": USB 2.0 DCL rev " & tost(REVISION)
& " " & tost(2**(memobits+2)) & " B Out Buffer " & tost(2**(memibits+2)) & " B In Buffer");
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: usbdcl
-- File: usbdcl.vhd
-- Author: Andreas Hansen
-- Modified: Marko Isomaki
-- Description: USB Debug Communication Link
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
use gaisler.usb.all;
library techmap;
use techmap.gencomp.all;
entity usbdcl is
generic (
hindex : integer := 0;
memtech : integer := DEFMEMTECH
);
port (
uclk : in std_ulogic;
usbi : in usb_in_type;
usbo : out usb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture bhv of usbdcl is
constant REVISION : amba_version_type := 0;
constant memibits : integer := 11;
constant memobits : integer := 11;
signal iri : usb_memi_in_type;
signal ori : usb_memo_in_type;
signal oraddr : std_logic_vector(memobits-1 downto 0);
signal iraddr : std_logic_vector(memibits-1 downto 0);
signal ordata : std_logic_vector(31 downto 0);
signal irdata : std_logic_vector(31 downto 0);
signal vcc : std_ulogic;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
component usbdclc is
port (
uclk : in std_ulogic;
usbi : in usb_in_type;
usbo : out usb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
iri : out usb_memi_in_type;
ori : out usb_memo_in_type;
dmai : out ahb_dma_in_type;
dmao : in ahb_dma_out_type;
oraddr : out std_logic_vector(10 downto 0);
iraddr : out std_logic_vector(10 downto 0);
ordata : in std_logic_vector(31 downto 0);
irdata : in std_logic_vector(31 downto 0)
);
end component;
begin
vcc <= '1';
u0 : usbdclc
port map ( uclk, usbi, usbo, hclk, hrst, iri,
ori, dmai, dmao, oraddr, iraddr, ordata, irdata);
inram : syncram_2p
generic map (memtech, memibits, 32, 1)
port map (
uclk, vcc, iraddr, irdata, hclk,
iri.wenable, iri.address, iri.din);
outram : syncram_2p
generic map (memtech, memobits, 32, 1)
port map (
hclk, vcc, oraddr, ordata, uclk,
ori.wenable, ori.address, ori.din);
ahbmst0 : ahbmst
generic map (incaddr => 0, hindex => hindex,
venid => VENDOR_GAISLER, devid => GAISLER_USBDCL)
port map (hrst, hclk, dmai, dmao, ahbi, ahbo);
-- pragma translate_off
bootmsg : report_version
generic map (
"grusb" & tost(hindex) & ": USB 2.0 DCL rev " & tost(REVISION)
& " " & tost(2**(memobits+2)) & " B Out Buffer " & tost(2**(memibits+2)) & " B In Buffer");
-- pragma translate_on
end;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ba
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ba-e.vhd,v 1.3 2005/11/30 14:04:01 wig Exp $
-- $Date: 2005/11/30 14:04:01 $
-- $Log: ent_ba-e.vhd,v $
-- Revision 1.3 2005/11/30 14:04:01 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_ba
--
entity ent_ba is
-- Generics:
-- No Generated Generics for Entity ent_ba
-- Generated Port Declaration:
-- No Generated Port for Entity ent_ba
end ent_ba;
--
-- End of Generated Entity ent_ba
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-----------------------------------------------------------------------------------
-- <description>
--
-- Author: Daniel Tavares (daniel.tavares@lnls.br)
-- Company: Brazilian Synchrotron Light Laboratory, Campinas, Brazil
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity strobe_lvds is
generic
(
C_DEFAULT_DELAY : natural := 0
);
port
(
clk_ctrl_i : in std_logic;
strobe_p_i : in std_logic;
strobe_n_i : in std_logic;
strobe_o : out std_logic;
ctrl_delay_update_i : in std_logic;
ctrl_delay_value_i : in std_logic_vector(4 downto 0);
ctrl_delay_value_o : out std_logic_vector(4 downto 0)
);
end strobe_lvds;
architecture rtl of strobe_lvds is
signal s_strobe_l : std_logic;
signal s_strobe_dly : std_logic;
begin
cmp_ibufgds : ibufds
generic map
(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map
(
i => strobe_p_i,
ib => strobe_n_i,
o => s_strobe_l
);
cmp_iodelay : iodelaye1
generic map
(
IDELAY_TYPE => "VAR_LOADABLE",
IDELAY_VALUE => C_DEFAULT_DELAY,
SIGNAL_PATTERN => "CLOCK",
DELAY_SRC => "I"
)
port map
(
idatain => s_strobe_l,
dataout => s_strobe_dly,
c => clk_ctrl_i,
ce => '0',
inc => '0',
datain => '0',
odatain => '0',
clkin => '0',
rst => ctrl_delay_update_i,
cntvaluein => ctrl_delay_value_i,
cntvalueout => ctrl_delay_value_o,
cinvctrl => '0',
t => '1'
);
cmp_bufr : bufr
generic map
(
SIM_DEVICE => "VIRTEX6",
BUFR_DIVIDE => "BYPASS"
)
port map
(
clr => '1',
ce => '1',
i => s_strobe_dly,
o => strobe_o
);
end rtl; |
-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 406 2011-08-14 21:06:44Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_xfirst_gen_unisim - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.0.2 cleaner code for L_DI(A|B) initialization
-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
-- 2008-03-08 123 1.0 Initial version (merged from _rfirst/_wfirst)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_xfirst_gen_unisim;
architecture syn of ram_2swsr_xfirst_gen_unisim is
constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+35)/36)=((DWIDTH+31)/32);
constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
((DWIDTH+17)/18)=((DWIDTH+16)/16);
constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+8)/9)=((DWIDTH+7)/8);
begin
assert AWIDTH>=9 and AWIDTH<=14
report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
severity failure;
AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
constant dw_mem : positive := ((DWIDTH+35)/36)*36;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/36-1 downto 0 generate
MEM : RAMB16_S36_S36
generic map (
INIT_A => O"000000000000",
INIT_B => O"000000000000",
SRVAL_A => O"000000000000",
SRVAL_B => O"000000000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(36*i+31 downto 36*i),
DOB => L_DOB(36*i+31 downto 36*i),
DOPA => L_DOA(36*i+35 downto 36*i+32),
DOPB => L_DOB(36*i+35 downto 36*i+32),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(36*i+31 downto 36*i),
DIB => L_DIB(36*i+31 downto 36*i),
DIPA => L_DIA(36*i+35 downto 36*i+32),
DIPB => L_DIB(36*i+35 downto 36*i+32),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_09_S36;
AW_09_S32: if AWIDTH=9 and ok_mod32 generate
GL: for i in DWIDTH/32-1 downto 0 generate
MEM : RAMB16_S36_S36
generic map (
INIT_A => X"00000000",
INIT_B => X"00000000",
SRVAL_A => X"00000000",
SRVAL_B => X"00000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(32*i+31 downto 32*i),
DOB => DOB(32*i+31 downto 32*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(32*i+31 downto 32*i),
DIB => DIB(32*i+31 downto 32*i),
DIPA => "0000",
DIPB => "0000",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_09_S32;
AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
constant dw_mem : positive := ((DWIDTH+17)/18)*18;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/18-1 downto 0 generate
MEM : RAMB16_S18_S18
generic map (
INIT_A => O"000000",
INIT_B => O"000000",
SRVAL_A => O"000000",
SRVAL_B => O"000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(18*i+15 downto 18*i),
DOB => L_DOB(18*i+15 downto 18*i),
DOPA => L_DOA(18*i+17 downto 18*i+16),
DOPB => L_DOB(18*i+17 downto 18*i+16),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(18*i+15 downto 18*i),
DIB => L_DIB(18*i+15 downto 18*i),
DIPA => L_DIA(18*i+17 downto 18*i+16),
DIPB => L_DIB(18*i+17 downto 18*i+16),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_10_S18;
AW_10_S16: if AWIDTH=10 and ok_mod16 generate
GL: for i in DWIDTH/16-1 downto 0 generate
MEM : RAMB16_S18_S18
generic map (
INIT_A => X"0000",
INIT_B => X"0000",
SRVAL_A => X"0000",
SRVAL_B => X"0000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(16*i+15 downto 16*i),
DOB => DOB(16*i+15 downto 16*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(16*i+15 downto 16*i),
DIB => DIB(16*i+15 downto 16*i),
DIPA => "00",
DIPB => "00",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_10_S16;
AW_11_S9: if AWIDTH=11 and not ok_mod08 generate
constant dw_mem : positive := ((DWIDTH+8)/9)*9;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/9-1 downto 0 generate
MEM : RAMB16_S9_S9
generic map (
INIT_A => O"000",
INIT_B => O"000",
SRVAL_A => O"000",
SRVAL_B => O"000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(9*i+7 downto 9*i),
DOB => L_DOB(9*i+7 downto 9*i),
DOPA => L_DOA(9*i+8 downto 9*i+8),
DOPB => L_DOB(9*i+8 downto 9*i+8),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(9*i+7 downto 9*i),
DIB => L_DIB(9*i+7 downto 9*i),
DIPA => L_DIA(9*i+8 downto 9*i+8),
DIPB => L_DIB(9*i+8 downto 9*i+8),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_11_S9;
AW_11_S8: if AWIDTH=11 and ok_mod08 generate
GL: for i in DWIDTH/8-1 downto 0 generate
MEM : RAMB16_S9_S9
generic map (
INIT_A => X"00",
INIT_B => X"00",
SRVAL_A => X"00",
SRVAL_B => X"00",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(8*i+7 downto 8*i),
DOB => DOB(8*i+7 downto 8*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(8*i+7 downto 8*i),
DIB => DIB(8*i+7 downto 8*i),
DIPA => "0",
DIPB => "0",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_11_S8;
AW_12_S4: if AWIDTH = 12 generate
constant dw_mem : positive := ((DWIDTH+3)/4)*4;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/4-1 downto 0 generate
MEM : RAMB16_S4_S4
generic map (
INIT_A => X"0",
INIT_B => X"0",
SRVAL_A => X"0",
SRVAL_B => X"0",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(4*i+3 downto 4*i),
DOB => L_DOB(4*i+3 downto 4*i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(4*i+3 downto 4*i),
DIB => L_DIB(4*i+3 downto 4*i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_12_S4;
AW_13_S2: if AWIDTH = 13 generate
constant dw_mem : positive := ((DWIDTH+1)/2)*2;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/2-1 downto 0 generate
MEM : RAMB16_S2_S2
generic map (
INIT_A => "00",
INIT_B => "00",
SRVAL_A => "00",
SRVAL_B => "00",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(2*i+1 downto 2*i),
DOB => L_DOB(2*i+1 downto 2*i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(2*i+1 downto 2*i),
DIB => L_DIB(2*i+1 downto 2*i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_13_S2;
AW_14_S1: if AWIDTH = 14 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAMB16_S1_S1
generic map (
INIT_A => "0",
INIT_B => "0",
SRVAL_A => "0",
SRVAL_B => "0",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(i downto i),
DOB => DOB(i downto i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(i downto i),
DIB => DIB(i downto i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_14_S1;
end syn;
-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
-- nonsense: INIT_A : bit_vector := X"000";
-- This is a 12 bit value, while a 9 bit one is needed. Thus the
-- explicit definition above.
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type expbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type aluleftdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal manleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal manrightff, manalignff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal invertleftnode, invertrightnode : STD_LOGIC;
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftnode, alurightnode, alucarrynode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftdelff : aluleftdelfftype;
signal subexpone, subexptwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal expzerochknode : STD_LOGIC;
signal expbaseff : expbasefftype;
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
expbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= (aaff(k+10) AND NOT(switch)) OR (bbff(k+10) AND switch);
manrightff(k) <= (bbff(k+10) AND NOT(switch)) OR (aaff(k+10) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
expbaseff(k)(10 DOWNTO 1) <= expbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
END LOOP;
--*** LEVEL 3 or 4 ***
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= (shiftbusnode(k) XOR invertrightnode) AND expzerochknode;
END LOOP;
--*** LEVEL 4 or 5 ***
aluff <= aluleftnode + alurightnode + alucarrynode;
END IF;
END IF;
END PROCESS;
gssa: IF (shiftspeed = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= manleftff(k) XOR invertleftnode;
END LOOP;
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftff;
invertrightnode <= invertrightff;
expzerochknode <= expzerochk(10);
aluleftnode <= aluleftff;
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(3);
END GENERATE;
gssb: IF (shiftspeed = 1) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftdelff(1)(k) <= '0';
aluleftdelff(2)(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluleftdelff(1)(mantissa DOWNTO 1) <= manleftff;
FOR k IN 1 TO mantissa LOOP
aluleftdelff(2)(k) <= aluleftdelff(1)(k) XOR invertleftnode;
END LOOP;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(10);
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftdelff;
invertrightnode <= invertrightdelff;
expzerochknode <= expzerochkff;
aluleftnode <= aluleftdelff(2)(mantissa DOWNTO 1);
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(4);
END GENERATE;
alurightnode <= manalignff;
subexpone <= aaff(10 DOWNTO 1) - bbff(10 DOWNTO 1);
subexptwo <= bbff(10 DOWNTO 1) - aaff(10 DOWNTO 1);
switch <= subexpone(10);
gsa: IF (mantissa = 32) GENERATE
expzerochk <= expshiftff - "0000100000"; -- 31 ok, 32 not
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
expzerochk <= expshiftff - "0000100100"; -- 35 ok, 36 not
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & expbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type expbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type aluleftdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal manleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal manrightff, manalignff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal invertleftnode, invertrightnode : STD_LOGIC;
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftnode, alurightnode, alucarrynode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftdelff : aluleftdelfftype;
signal subexpone, subexptwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal expzerochknode : STD_LOGIC;
signal expbaseff : expbasefftype;
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
expbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= (aaff(k+10) AND NOT(switch)) OR (bbff(k+10) AND switch);
manrightff(k) <= (bbff(k+10) AND NOT(switch)) OR (aaff(k+10) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
expbaseff(k)(10 DOWNTO 1) <= expbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
END LOOP;
--*** LEVEL 3 or 4 ***
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= (shiftbusnode(k) XOR invertrightnode) AND expzerochknode;
END LOOP;
--*** LEVEL 4 or 5 ***
aluff <= aluleftnode + alurightnode + alucarrynode;
END IF;
END IF;
END PROCESS;
gssa: IF (shiftspeed = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= manleftff(k) XOR invertleftnode;
END LOOP;
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftff;
invertrightnode <= invertrightff;
expzerochknode <= expzerochk(10);
aluleftnode <= aluleftff;
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(3);
END GENERATE;
gssb: IF (shiftspeed = 1) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftdelff(1)(k) <= '0';
aluleftdelff(2)(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluleftdelff(1)(mantissa DOWNTO 1) <= manleftff;
FOR k IN 1 TO mantissa LOOP
aluleftdelff(2)(k) <= aluleftdelff(1)(k) XOR invertleftnode;
END LOOP;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(10);
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftdelff;
invertrightnode <= invertrightdelff;
expzerochknode <= expzerochkff;
aluleftnode <= aluleftdelff(2)(mantissa DOWNTO 1);
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(4);
END GENERATE;
alurightnode <= manalignff;
subexpone <= aaff(10 DOWNTO 1) - bbff(10 DOWNTO 1);
subexptwo <= bbff(10 DOWNTO 1) - aaff(10 DOWNTO 1);
switch <= subexpone(10);
gsa: IF (mantissa = 32) GENERATE
expzerochk <= expshiftff - "0000100000"; -- 31 ok, 32 not
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
expzerochk <= expshiftff - "0000100100"; -- 35 ok, 36 not
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & expbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type expbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type aluleftdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal manleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal manrightff, manalignff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal invertleftnode, invertrightnode : STD_LOGIC;
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftnode, alurightnode, alucarrynode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftdelff : aluleftdelfftype;
signal subexpone, subexptwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal expzerochknode : STD_LOGIC;
signal expbaseff : expbasefftype;
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
expbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= (aaff(k+10) AND NOT(switch)) OR (bbff(k+10) AND switch);
manrightff(k) <= (bbff(k+10) AND NOT(switch)) OR (aaff(k+10) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
expbaseff(k)(10 DOWNTO 1) <= expbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
END LOOP;
--*** LEVEL 3 or 4 ***
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= (shiftbusnode(k) XOR invertrightnode) AND expzerochknode;
END LOOP;
--*** LEVEL 4 or 5 ***
aluff <= aluleftnode + alurightnode + alucarrynode;
END IF;
END IF;
END PROCESS;
gssa: IF (shiftspeed = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= manleftff(k) XOR invertleftnode;
END LOOP;
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftff;
invertrightnode <= invertrightff;
expzerochknode <= expzerochk(10);
aluleftnode <= aluleftff;
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(3);
END GENERATE;
gssb: IF (shiftspeed = 1) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftdelff(1)(k) <= '0';
aluleftdelff(2)(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluleftdelff(1)(mantissa DOWNTO 1) <= manleftff;
FOR k IN 1 TO mantissa LOOP
aluleftdelff(2)(k) <= aluleftdelff(1)(k) XOR invertleftnode;
END LOOP;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(10);
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftdelff;
invertrightnode <= invertrightdelff;
expzerochknode <= expzerochkff;
aluleftnode <= aluleftdelff(2)(mantissa DOWNTO 1);
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(4);
END GENERATE;
alurightnode <= manalignff;
subexpone <= aaff(10 DOWNTO 1) - bbff(10 DOWNTO 1);
subexptwo <= bbff(10 DOWNTO 1) - aaff(10 DOWNTO 1);
switch <= subexpone(10);
gsa: IF (mantissa = 32) GENERATE
expzerochk <= expshiftff - "0000100000"; -- 31 ok, 32 not
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
expzerochk <= expshiftff - "0000100100"; -- 35 ok, 36 not
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & expbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type expbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type aluleftdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal manleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal manrightff, manalignff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal invertleftnode, invertrightnode : STD_LOGIC;
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftnode, alurightnode, alucarrynode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftdelff : aluleftdelfftype;
signal subexpone, subexptwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal expzerochknode : STD_LOGIC;
signal expbaseff : expbasefftype;
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
expbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= (aaff(k+10) AND NOT(switch)) OR (bbff(k+10) AND switch);
manrightff(k) <= (bbff(k+10) AND NOT(switch)) OR (aaff(k+10) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
expbaseff(k)(10 DOWNTO 1) <= expbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
END LOOP;
--*** LEVEL 3 or 4 ***
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= (shiftbusnode(k) XOR invertrightnode) AND expzerochknode;
END LOOP;
--*** LEVEL 4 or 5 ***
aluff <= aluleftnode + alurightnode + alucarrynode;
END IF;
END IF;
END PROCESS;
gssa: IF (shiftspeed = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= manleftff(k) XOR invertleftnode;
END LOOP;
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftff;
invertrightnode <= invertrightff;
expzerochknode <= expzerochk(10);
aluleftnode <= aluleftff;
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(3);
END GENERATE;
gssb: IF (shiftspeed = 1) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftdelff(1)(k) <= '0';
aluleftdelff(2)(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluleftdelff(1)(mantissa DOWNTO 1) <= manleftff;
FOR k IN 1 TO mantissa LOOP
aluleftdelff(2)(k) <= aluleftdelff(1)(k) XOR invertleftnode;
END LOOP;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(10);
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftdelff;
invertrightnode <= invertrightdelff;
expzerochknode <= expzerochkff;
aluleftnode <= aluleftdelff(2)(mantissa DOWNTO 1);
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(4);
END GENERATE;
alurightnode <= manalignff;
subexpone <= aaff(10 DOWNTO 1) - bbff(10 DOWNTO 1);
subexptwo <= bbff(10 DOWNTO 1) - aaff(10 DOWNTO 1);
switch <= subexpone(10);
gsa: IF (mantissa = 32) GENERATE
expzerochk <= expshiftff - "0000100000"; -- 31 ok, 32 not
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
expzerochk <= expshiftff - "0000100100"; -- 35 ok, 36 not
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & expbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type expbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type aluleftdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal manleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal manrightff, manalignff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal invertleftnode, invertrightnode : STD_LOGIC;
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftnode, alurightnode, alucarrynode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftdelff : aluleftdelfftype;
signal subexpone, subexptwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal expzerochknode : STD_LOGIC;
signal expbaseff : expbasefftype;
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
expbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= (aaff(k+10) AND NOT(switch)) OR (bbff(k+10) AND switch);
manrightff(k) <= (bbff(k+10) AND NOT(switch)) OR (aaff(k+10) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
expbaseff(k)(10 DOWNTO 1) <= expbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
END LOOP;
--*** LEVEL 3 or 4 ***
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= (shiftbusnode(k) XOR invertrightnode) AND expzerochknode;
END LOOP;
--*** LEVEL 4 or 5 ***
aluff <= aluleftnode + alurightnode + alucarrynode;
END IF;
END IF;
END PROCESS;
gssa: IF (shiftspeed = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= manleftff(k) XOR invertleftnode;
END LOOP;
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftff;
invertrightnode <= invertrightff;
expzerochknode <= expzerochk(10);
aluleftnode <= aluleftff;
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(3);
END GENERATE;
gssb: IF (shiftspeed = 1) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftdelff(1)(k) <= '0';
aluleftdelff(2)(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluleftdelff(1)(mantissa DOWNTO 1) <= manleftff;
FOR k IN 1 TO mantissa LOOP
aluleftdelff(2)(k) <= aluleftdelff(1)(k) XOR invertleftnode;
END LOOP;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(10);
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftdelff;
invertrightnode <= invertrightdelff;
expzerochknode <= expzerochkff;
aluleftnode <= aluleftdelff(2)(mantissa DOWNTO 1);
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(4);
END GENERATE;
alurightnode <= manalignff;
subexpone <= aaff(10 DOWNTO 1) - bbff(10 DOWNTO 1);
subexptwo <= bbff(10 DOWNTO 1) - aaff(10 DOWNTO 1);
switch <= subexpone(10);
gsa: IF (mantissa = 32) GENERATE
expzerochk <= expshiftff - "0000100000"; -- 31 ok, 32 not
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
expzerochk <= expshiftff - "0000100100"; -- 35 ok, 36 not
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & expbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type expbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type aluleftdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal manleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal manrightff, manalignff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal invertleftnode, invertrightnode : STD_LOGIC;
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftnode, alurightnode, alucarrynode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftdelff : aluleftdelfftype;
signal subexpone, subexptwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal expzerochknode : STD_LOGIC;
signal expbaseff : expbasefftype;
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
expbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= (aaff(k+10) AND NOT(switch)) OR (bbff(k+10) AND switch);
manrightff(k) <= (bbff(k+10) AND NOT(switch)) OR (aaff(k+10) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
expbaseff(k)(10 DOWNTO 1) <= expbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
END LOOP;
--*** LEVEL 3 or 4 ***
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= (shiftbusnode(k) XOR invertrightnode) AND expzerochknode;
END LOOP;
--*** LEVEL 4 or 5 ***
aluff <= aluleftnode + alurightnode + alucarrynode;
END IF;
END IF;
END PROCESS;
gssa: IF (shiftspeed = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= manleftff(k) XOR invertleftnode;
END LOOP;
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftff;
invertrightnode <= invertrightff;
expzerochknode <= expzerochk(10);
aluleftnode <= aluleftff;
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(3);
END GENERATE;
gssb: IF (shiftspeed = 1) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftdelff(1)(k) <= '0';
aluleftdelff(2)(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluleftdelff(1)(mantissa DOWNTO 1) <= manleftff;
FOR k IN 1 TO mantissa LOOP
aluleftdelff(2)(k) <= aluleftdelff(1)(k) XOR invertleftnode;
END LOOP;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(10);
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftdelff;
invertrightnode <= invertrightdelff;
expzerochknode <= expzerochkff;
aluleftnode <= aluleftdelff(2)(mantissa DOWNTO 1);
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(4);
END GENERATE;
alurightnode <= manalignff;
subexpone <= aaff(10 DOWNTO 1) - bbff(10 DOWNTO 1);
subexptwo <= bbff(10 DOWNTO 1) - aaff(10 DOWNTO 1);
switch <= subexpone(10);
gsa: IF (mantissa = 32) GENERATE
expzerochk <= expshiftff - "0000100000"; -- 31 ok, 32 not
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
expzerochk <= expshiftff - "0000100100"; -- 35 ok, 36 not
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & expbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type expbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type aluleftdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal manleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal manrightff, manalignff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal invertleftnode, invertrightnode : STD_LOGIC;
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftnode, alurightnode, alucarrynode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftdelff : aluleftdelfftype;
signal subexpone, subexptwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal expzerochknode : STD_LOGIC;
signal expbaseff : expbasefftype;
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
expbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= (aaff(k+10) AND NOT(switch)) OR (bbff(k+10) AND switch);
manrightff(k) <= (bbff(k+10) AND NOT(switch)) OR (aaff(k+10) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
expbaseff(k)(10 DOWNTO 1) <= expbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
END LOOP;
--*** LEVEL 3 or 4 ***
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= (shiftbusnode(k) XOR invertrightnode) AND expzerochknode;
END LOOP;
--*** LEVEL 4 or 5 ***
aluff <= aluleftnode + alurightnode + alucarrynode;
END IF;
END IF;
END PROCESS;
gssa: IF (shiftspeed = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= manleftff(k) XOR invertleftnode;
END LOOP;
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftff;
invertrightnode <= invertrightff;
expzerochknode <= expzerochk(10);
aluleftnode <= aluleftff;
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(3);
END GENERATE;
gssb: IF (shiftspeed = 1) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftdelff(1)(k) <= '0';
aluleftdelff(2)(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluleftdelff(1)(mantissa DOWNTO 1) <= manleftff;
FOR k IN 1 TO mantissa LOOP
aluleftdelff(2)(k) <= aluleftdelff(1)(k) XOR invertleftnode;
END LOOP;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(10);
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftdelff;
invertrightnode <= invertrightdelff;
expzerochknode <= expzerochkff;
aluleftnode <= aluleftdelff(2)(mantissa DOWNTO 1);
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(4);
END GENERATE;
alurightnode <= manalignff;
subexpone <= aaff(10 DOWNTO 1) - bbff(10 DOWNTO 1);
subexptwo <= bbff(10 DOWNTO 1) - aaff(10 DOWNTO 1);
switch <= subexpone(10);
gsa: IF (mantissa = 32) GENERATE
expzerochk <= expshiftff - "0000100000"; -- 31 ok, 32 not
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
expzerochk <= expshiftff - "0000100100"; -- 35 ok, 36 not
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & expbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type expbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type aluleftdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal manleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal manrightff, manalignff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal invertleftnode, invertrightnode : STD_LOGIC;
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftnode, alurightnode, alucarrynode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftdelff : aluleftdelfftype;
signal subexpone, subexptwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal expzerochknode : STD_LOGIC;
signal expbaseff : expbasefftype;
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
expbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= (aaff(k+10) AND NOT(switch)) OR (bbff(k+10) AND switch);
manrightff(k) <= (bbff(k+10) AND NOT(switch)) OR (aaff(k+10) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
expbaseff(k)(10 DOWNTO 1) <= expbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
END LOOP;
--*** LEVEL 3 or 4 ***
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= (shiftbusnode(k) XOR invertrightnode) AND expzerochknode;
END LOOP;
--*** LEVEL 4 or 5 ***
aluff <= aluleftnode + alurightnode + alucarrynode;
END IF;
END IF;
END PROCESS;
gssa: IF (shiftspeed = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= manleftff(k) XOR invertleftnode;
END LOOP;
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftff;
invertrightnode <= invertrightff;
expzerochknode <= expzerochk(10);
aluleftnode <= aluleftff;
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(3);
END GENERATE;
gssb: IF (shiftspeed = 1) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftdelff(1)(k) <= '0';
aluleftdelff(2)(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluleftdelff(1)(mantissa DOWNTO 1) <= manleftff;
FOR k IN 1 TO mantissa LOOP
aluleftdelff(2)(k) <= aluleftdelff(1)(k) XOR invertleftnode;
END LOOP;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(10);
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftdelff;
invertrightnode <= invertrightdelff;
expzerochknode <= expzerochkff;
aluleftnode <= aluleftdelff(2)(mantissa DOWNTO 1);
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(4);
END GENERATE;
alurightnode <= manalignff;
subexpone <= aaff(10 DOWNTO 1) - bbff(10 DOWNTO 1);
subexptwo <= bbff(10 DOWNTO 1) - aaff(10 DOWNTO 1);
switch <= subexpone(10);
gsa: IF (mantissa = 32) GENERATE
expzerochk <= expshiftff - "0000100000"; -- 31 ok, 32 not
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
expzerochk <= expshiftff - "0000100100"; -- 35 ok, 36 not
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & expbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type expbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type aluleftdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal manleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal manrightff, manalignff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal invertleftnode, invertrightnode : STD_LOGIC;
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftnode, alurightnode, alucarrynode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftdelff : aluleftdelfftype;
signal subexpone, subexptwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal expzerochknode : STD_LOGIC;
signal expbaseff : expbasefftype;
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
expbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= (aaff(k+10) AND NOT(switch)) OR (bbff(k+10) AND switch);
manrightff(k) <= (bbff(k+10) AND NOT(switch)) OR (aaff(k+10) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
expbaseff(k)(10 DOWNTO 1) <= expbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
END LOOP;
--*** LEVEL 3 or 4 ***
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= (shiftbusnode(k) XOR invertrightnode) AND expzerochknode;
END LOOP;
--*** LEVEL 4 or 5 ***
aluff <= aluleftnode + alurightnode + alucarrynode;
END IF;
END IF;
END PROCESS;
gssa: IF (shiftspeed = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= manleftff(k) XOR invertleftnode;
END LOOP;
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftff;
invertrightnode <= invertrightff;
expzerochknode <= expzerochk(10);
aluleftnode <= aluleftff;
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(3);
END GENERATE;
gssb: IF (shiftspeed = 1) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftdelff(1)(k) <= '0';
aluleftdelff(2)(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluleftdelff(1)(mantissa DOWNTO 1) <= manleftff;
FOR k IN 1 TO mantissa LOOP
aluleftdelff(2)(k) <= aluleftdelff(1)(k) XOR invertleftnode;
END LOOP;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(10);
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftdelff;
invertrightnode <= invertrightdelff;
expzerochknode <= expzerochkff;
aluleftnode <= aluleftdelff(2)(mantissa DOWNTO 1);
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(4);
END GENERATE;
alurightnode <= manalignff;
subexpone <= aaff(10 DOWNTO 1) - bbff(10 DOWNTO 1);
subexptwo <= bbff(10 DOWNTO 1) - aaff(10 DOWNTO 1);
switch <= subexpone(10);
gsa: IF (mantissa = 32) GENERATE
expzerochk <= expshiftff - "0000100000"; -- 31 ok, 32 not
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
expzerochk <= expshiftff - "0000100100"; -- 35 ok, 36 not
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & expbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type expbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type aluleftdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal manleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal manrightff, manalignff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal invertleftnode, invertrightnode : STD_LOGIC;
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftnode, alurightnode, alucarrynode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftdelff : aluleftdelfftype;
signal subexpone, subexptwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal expzerochknode : STD_LOGIC;
signal expbaseff : expbasefftype;
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
expbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= (aaff(k+10) AND NOT(switch)) OR (bbff(k+10) AND switch);
manrightff(k) <= (bbff(k+10) AND NOT(switch)) OR (aaff(k+10) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
expbaseff(k)(10 DOWNTO 1) <= expbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
END LOOP;
--*** LEVEL 3 or 4 ***
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= (shiftbusnode(k) XOR invertrightnode) AND expzerochknode;
END LOOP;
--*** LEVEL 4 or 5 ***
aluff <= aluleftnode + alurightnode + alucarrynode;
END IF;
END IF;
END PROCESS;
gssa: IF (shiftspeed = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= manleftff(k) XOR invertleftnode;
END LOOP;
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftff;
invertrightnode <= invertrightff;
expzerochknode <= expzerochk(10);
aluleftnode <= aluleftff;
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(3);
END GENERATE;
gssb: IF (shiftspeed = 1) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftdelff(1)(k) <= '0';
aluleftdelff(2)(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluleftdelff(1)(mantissa DOWNTO 1) <= manleftff;
FOR k IN 1 TO mantissa LOOP
aluleftdelff(2)(k) <= aluleftdelff(1)(k) XOR invertleftnode;
END LOOP;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(10);
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftdelff;
invertrightnode <= invertrightdelff;
expzerochknode <= expzerochkff;
aluleftnode <= aluleftdelff(2)(mantissa DOWNTO 1);
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(4);
END GENERATE;
alurightnode <= manalignff;
subexpone <= aaff(10 DOWNTO 1) - bbff(10 DOWNTO 1);
subexptwo <= bbff(10 DOWNTO 1) - aaff(10 DOWNTO 1);
switch <= subexpone(10);
gsa: IF (mantissa = 32) GENERATE
expzerochk <= expshiftff - "0000100000"; -- 31 ok, 32 not
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
expzerochk <= expshiftff - "0000100100"; -- 35 ok, 36 not
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & expbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
|
-------------------------------------------------------------------------------
--
-- File: rgb2dvi.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 source interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure (optional), encoding and serialization logic.
-- On the input side it has 24-bit RGB video data bus, pixel clock and synchronization
-- signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rgb2dvi is
Generic (
kGenerateSerialClk : boolean := true;
kClkPrimitive : string := "MMCM"; -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kRstActiveHigh : boolean := true); --true, if active-high; false, if active-low
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : out std_logic;
TMDS_Clk_n : out std_logic;
TMDS_Data_p : out std_logic_vector(2 downto 0);
TMDS_Data_n : out std_logic_vector(2 downto 0);
-- Auxiliary signals
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video in
vid_pData : in std_logic_vector(23 downto 0);
vid_pVDE : in std_logic;
vid_pHSync : in std_logic;
vid_pVSync : in std_logic;
PixelClk : in std_logic; --pixel-clock recovered from the DVI interface
SerialClk : in std_logic); -- 5x PixelClk
end rgb2dvi;
architecture Behavioral of rgb2dvi is
type dataOut_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type dataOutRaw_t is array (2 downto 0) of std_logic_vector(9 downto 0);
signal pDataOut : dataOut_t;
signal pDataOutRaw : dataOutRaw_t;
signal pVde, pC0, pC1 : std_logic_vector(2 downto 0);
signal aRst_int, aPixelClkLckd : std_logic;
signal PixelClkIO, SerialClkIO, aRstLck, pRstLck : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
end generate ResetActiveHigh;
-- Generate SerialClk internally?
ClockGenInternal: if kGenerateSerialClk generate
ClockGenX: entity work.ClockGen
Generic map (
kClkRange => kClkRange, -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
kClkPrimitive => kClkPrimitive) -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
Port map (
PixelClkIn => PixelClk,
PixelClkOut => PixelClkIO,
SerialClk => SerialClkIO,
aRst => aRst_int,
aLocked => aPixelClkLckd);
--TODO revise this
aRstLck <= not aPixelClkLckd;
end generate ClockGenInternal;
ClockGenExternal: if not kGenerateSerialClk generate
PixelClkIO <= PixelClk;
SerialClkIO <= SerialClk;
aRstLck <= aRst_int;
end generate ClockGenExternal;
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRstLck,
OutClk => PixelClk,
oRst => pRstLck);
-- Clock needs no encoding, send a pulse
ClockSerializer: entity work.OutputSERDES
generic map (
kParallelWidth => 10) -- TMDS uses 1:10 serialization
port map(
PixelClk => PixelClkIO,
SerialClk => SerialClkIO,
sDataOut_p => TMDS_Clk_p,
sDataOut_n => TMDS_Clk_n,
--Encoded parallel data (raw)
pDataOut => "1111100000",
aRst => pRstLck);
DataEncoders: for i in 0 to 2 generate
DataEncoder: entity work.TMDS_Encoder
port map (
PixelClk => PixelClk,
SerialClk => SerialClk,
pDataOutRaw => pDataOutRaw(i),
aRst => pRstLck,
pDataOut => pDataOut(i),
pC0 => pC0(i),
pC1 => pC1(i),
pVde => pVde(i)
);
DataSerializer: entity work.OutputSERDES
generic map (
kParallelWidth => 10) -- TMDS uses 1:10 serialization
port map(
PixelClk => PixelClkIO,
SerialClk => SerialClkIO,
sDataOut_p => TMDS_Data_p(i),
sDataOut_n => TMDS_Data_n(i),
--Encoded parallel data (raw)
pDataOut => pDataOutRaw(i),
aRst => pRstLck);
end generate DataEncoders;
-- DVI Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason vid_data is packed in RBG order
pDataOut(2) <= vid_pData(23 downto 16); -- red is channel 2
pDataOut(0) <= vid_pData(7 downto 0); -- blue is channel 0
pDataOut(1) <= vid_pData(15 downto 8); -- green is channel 1
pC0(2 downto 1) <= (others => '0'); -- default is low for control signals
pC1(2 downto 1) <= (others => '0'); -- default is low for control signals
pC0(0) <= vid_pHSync; -- channel 0 carries control signals too
pC1(0) <= vid_pVSync; -- channel 0 carries control signals too
pVde <= vid_pVDE & vid_pVDE & vid_pVDE; -- all of them are either active or blanking at once
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_Divisor_Frecuencia IS
END TB_Divisor_Frecuencia;
ARCHITECTURE behavior OF TB_Divisor_Frecuencia IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Divisor_Frecuencia
PORT(
clk : IN std_logic;
Salida : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
--Outputs
signal Salida : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Divisor_Frecuencia PORT MAP (
clk => clk,
Salida => Salida
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company: Iowa State University
-- Engineer: Aaron Mills
--
-- Create Date: 19:44:42 09/21/2011
-- Design Name:
-- Module Name: puf_sram - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: a2b3 LUT configuration
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity puf_sram is
port(
rst: in std_logic;
clk: in std_logic;
en: in std_logic;
Q1: out std_logic;
Q2: out std_logic
);
end puf_sram;
architecture Behavioral of puf_sram is
signal i1: std_logic;
signal i2: std_logic;
signal rstin: std_logic;
attribute keep: boolean;
attribute lock_pins: string;
attribute lock_pins of tri1 : label is "all";
attribute lock_pins of tri2 : label is "all";
begin
----A2B3
tri1 : LUT4_D
generic map (
INIT => X"ff33")
port map (
--LO => i2, -- LUT local output
O => i2, -- LUT general output
I0 => '0', -- LUT input
I1 => i1 , -- LUT input
I2 => '0', -- LUT input
I3 => rstin -- LUT input
);
tri2 : LUT4_D
generic map (
INIT => X"ff0f")
port map (
--LO => i1, -- LUT local output
O => i1, -- LUT general output
I0 => '0', -- LUT input
I1 => '0', -- LUT input
I2 => i2, -- LUT input
I3 => rstin -- LUT input
);
RST_DFF : FDCE
generic map (
INIT => '1') -- Initial value of register ('0' or '1')
port map (
Q => rstin, -- Data output
C => clk, -- Clock input
CE => en, -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => rst -- Data input
);
Q1<=i1;
Q2<=i2;
end Behavioral;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
--=================================================================================================
package transaction_pkg is
--==========================================================================================
-- t_operation
-- - VVC and BFM operations
--==========================================================================================
type t_operation is (
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
WRITE,
READ,
EXPECT
);
-- Constants for the maximum sizes to use in this VVC.
-- You can create VVCs with smaller sizes than these constants, but not larger.
constant C_VVC_CMD_DATA_MAX_BYTES : natural := 2048;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--==========================================================================================
--
-- Transaction info types, constants and global signal
--
--==========================================================================================
-- Transaction status
type t_transaction_status is (INACTIVE, IN_PROGRESS, FAILED, SUCCEEDED);
constant C_TRANSACTION_STATUS_DEFAULT : t_transaction_status := INACTIVE;
-- VVC Meta
type t_vvc_meta is record
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : integer;
end record;
constant C_VVC_META_DEFAULT : t_vvc_meta := (
msg => (others => ' '),
cmd_idx => -1
);
-- Base transaction
type t_base_transaction is record
operation : t_operation;
data_array : t_slv_array(0 to C_VVC_CMD_DATA_MAX_BYTES-1)(7 downto 0);
vvc_meta : t_vvc_meta;
transaction_status : t_transaction_status;
end record;
constant C_BASE_TRANSACTION_SET_DEFAULT : t_base_transaction := (
operation => NO_OPERATION,
data_array => (others => (others => '0')),
vvc_meta => C_VVC_META_DEFAULT,
transaction_status => C_TRANSACTION_STATUS_DEFAULT
);
-- Transaction group
type t_transaction_group is record
bt : t_base_transaction;
end record;
constant C_TRANSACTION_GROUP_DEFAULT : t_transaction_group := (
bt => C_BASE_TRANSACTION_SET_DEFAULT
);
subtype t_sub_channel is t_channel range RX to TX;
-- Global transaction info trigger signal
type t_gmii_transaction_trigger_array is array (t_sub_channel range <>, natural range <>) of std_logic;
signal global_gmii_vvc_transaction_trigger : t_gmii_transaction_trigger_array(t_sub_channel'left to t_sub_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => (others => '0'));
-- Shared transaction info variable
type t_gmii_transaction_group_array is array (t_sub_channel range <>, natural range <>) of t_transaction_group;
shared variable shared_gmii_vvc_transaction_info : t_gmii_transaction_group_array(t_sub_channel'left to t_sub_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => (others => C_TRANSACTION_GROUP_DEFAULT));
end package transaction_pkg; |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
--========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_cmd_pkg is
--========================================================================================================================
-- t_operation
-- - VVC and BFM operations
--========================================================================================================================
type t_operation is (
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
START_CLOCK,
STOP_CLOCK,
SET_CLOCK_PERIOD,
SET_CLOCK_HIGH_TIME
);
--<USER_INPUT> Create constants for the maximum sizes to use in this VVC.
-- You can create VVCs with smaller sizes than these constants, but not larger.
-- For example, given a VVC with parallel data bus and address bus, constraints should be added for maximum data length
-- and address length
-- Example:
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 8;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--========================================================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--========================================================================================================================
type t_vvc_cmd_record is record
-- Common VVC fields
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued;
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
parent_msg_id_panel : t_msg_id_panel;
-- VVC dedicated fields
clock_period : time;
clock_high_time : time;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => FAILURE,
delay => 0 ns,
quietness => NON_QUIET,
parent_msg_id_panel => C_UNUSED_MSG_ID_PANEL,
-- VVC dedicated fields
clock_period => 10 ns,
clock_high_time => 5 ns
);
--========================================================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--========================================================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--========================================================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--========================================================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--========================================================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--========================================================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--========================================================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--========================================================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => -1));
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fmexg_core is
port(
clock: in std_logic;
--
spi_clk, spi_cs: in std_logic;
spi_miso: out std_logic;
adc_clk, adc_pdwn: out std_logic;
adc_data: in std_logic_vector(11 downto 0);
interrupt: out std_logic;
fmexg_mic_sync: in std_logic
);
end entity;
architecture a of fmexg_core is
signal counter_div12: unsigned(2 downto 0);
signal clkdiv12: std_logic;
--signal fifo_readclk: std_logic;
signal spi_bit_ctr: unsigned(2 downto 0);
signal spi_byte_ctr: unsigned(1 downto 0);
signal fifo_readclk_en: std_logic;
signal first_sample: unsigned(11 downto 0);
signal two_samples: unsigned(23 downto 0);
--signal fifo_bit: unsigned(3 downto 0);
--signal hacky_fix: unsigned(1 downto 0);
--signal spi_data: std_logic;
--signal interrupt_counter: unsigned(7 downto 0);
signal fifo_Data: std_logic_vector(11 downto 0);
signal fifo_WrClock: std_logic;
signal fifo_RdClock: std_logic;
signal fifo_WrEn: std_logic;
signal fifo_RdEn: std_logic;
signal fifo_Reset: std_logic;
signal fifo_RPReset: std_logic;
signal fifo_Q: std_logic_vector(11 downto 0);
signal fifo_Q_u: unsigned(11 downto 0);
signal fifo_Empty: std_logic;
signal fifo_Full: std_logic;
signal fifo_AlmostEmpty: std_logic;
signal fifo_AlmostFull: std_logic;
signal rampcounter: unsigned(11 downto 0);
component fmexg_fifo_8k_1025 is
port (
Data: in std_logic_vector(11 downto 0);
WrClock: in std_logic;
RdClock: in std_logic;
WrEn: in std_logic;
RdEn: in std_logic;
Reset: in std_logic;
RPReset: in std_logic;
Q: out std_logic_vector(11 downto 0);
Empty: out std_logic;
Full: out std_logic;
AlmostEmpty: out std_logic;
AlmostFull: out std_logic
);
end component;
begin
adc_pdwn <= '0';
process(clock) is begin
if rising_edge(clock) then
counter_div12 <= counter_div12 + 1;
if counter_div12 = "101" then
counter_div12 <= "000";
clkdiv12 <= not clkdiv12;
end if;
end if;
end process;
adc_clk <= not clkdiv12;
process(clkdiv12) is begin
if falling_edge(clkdiv12) then
rampcounter <= rampcounter + 1;
--interrupt_counter <= interrupt_counter + 1;
end if;
end process;
interrupt <= fifo_AlmostFull; --and (and interrupt_counter);
fifo: fmexg_fifo_8k_1025 port map(
Data => fifo_Data,
WrClock => fifo_WrClock,
RdClock => fifo_RdClock,
WrEn => fifo_WrEn,
RdEn => fifo_RdEn,
Reset => fifo_Reset,
RPReset => fifo_RPReset,
Q => fifo_Q,
Empty => fifo_Empty,
Full => fifo_Full,
AlmostEmpty => fifo_AlmostEmpty,
AlmostFull => fifo_AlmostFull
);
fifo_Q_u <= unsigned(fifo_Q);
fifo_Data <= "100000000000" when fmexg_mic_sync = '1' else adc_data; --std_logic_vector(rampcounter);
fifo_WrClock <= clkdiv12;
fifo_RdClock <= spi_clk;
fifo_WrEn <= '1';
fifo_RdEn <= fifo_readclk_en;
fifo_Reset <= '0';
fifo_RPReset <= '0';
process(spi_clk) is begin
if falling_edge(spi_clk) then
if spi_cs = '0' then
two_samples <= '0' & two_samples(23 downto 1);
-- Read new data on second-to-last two rising edges
if spi_byte_ctr = "10" and (spi_bit_ctr = "110" or spi_bit_ctr = "111") then
fifo_readclk_en <= '1';
else
fifo_readclk_en <= '0';
end if;
if spi_byte_ctr = "10" and spi_bit_ctr = "111" then
--Falling edge of second-to-last clock pulse
--Register first sample of pair
first_sample <= unsigned(fifo_Q);
elsif spi_byte_ctr = "00" and spi_bit_ctr = "000" then
--Falling edge of last clock pulse
--Register two samples, swizzle bits
--VHDL does NOT allow e.g. a(7 downto 0) <= b(0 to 7) to reverse a vector
two_samples <= fifo_Q_u(4)
& fifo_Q_u(5)
& fifo_Q_u(6)
& fifo_Q_u(7)
& fifo_Q_u(8)
& fifo_Q_u(9)
& fifo_Q_u(10)
& fifo_Q_u(11)
& first_sample(8)
& first_sample(9)
& first_sample(10)
& first_sample(11)
& fifo_Q_u(0)
& fifo_Q_u(1)
& fifo_Q_u(2)
& fifo_Q_u(3)
& first_sample(0)
& first_sample(1)
& first_sample(2)
& first_sample(3)
& first_sample(4)
& first_sample(5)
& first_sample(6)
& first_sample(7);
end if;
end if;
end if;
end process;
spi_miso <= two_samples(0);
process(spi_clk, spi_cs) is begin
if spi_cs = '1' then
spi_bit_ctr <= "000";
spi_byte_ctr <= "00";
elsif rising_edge(spi_clk) then
--Increment bit (8) and byte (3) counters
if spi_bit_ctr = "111" then
if spi_byte_ctr = "10" then
spi_byte_ctr <= "00";
else
spi_byte_ctr <= spi_byte_ctr + 1;
end if;
end if;
spi_bit_ctr <= spi_bit_ctr + 1;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- Interface Timing Checker.
--
-- $Id: if_timing.vhd,v 1.6 2005-11-01 21:20:36 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity if_timing is
port (
xtal_i : in std_logic;
ale_i : in std_logic;
psen_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
prog_n_i : in std_logic;
db_bus_i : in std_logic_vector(7 downto 0);
p2_i : in std_logic_vector(7 downto 0)
);
end if_timing;
architecture behav of if_timing is
signal last_xtal_rise_s : time;
signal period_s : time;
signal last_ale_rise_s,
last_ale_fall_s : time;
signal last_psen_n_rise_s,
last_psen_n_fall_s : time;
signal last_rd_n_rise_s,
last_rd_n_fall_s : time;
signal last_wr_n_rise_s,
last_wr_n_fall_s : time;
signal last_prog_n_rise_s,
last_prog_n_fall_s : time;
signal last_bus_change_s,
bus_change_ale_s : time;
signal last_p2_change_s : time;
signal t_CY : time;
begin
t_CY <= 15 * period_s;
-----------------------------------------------------------------------------
-- Check RD
--
rd_check: process (rd_n_i)
begin
case rd_n_i is
-- RD active
when '0' =>
-- tLAFC1: ALE to Control RD
assert (now - last_ale_fall_s) > (t_CY / 5 - 75 ns)
report "Timing violation of tLAFC1 on RD!"
severity error;
-- tAFC1: Addr Float to RD
assert (now - last_bus_change_s) > (t_CY * 2/15 - 40 ns)
report "Timing violation of tAFC1 on RD!"
severity error;
-- RD inactive
when '1' =>
-- tCC1: Control Pulse Width RD
assert (now - last_rd_n_fall_s) > (t_CY / 2 - 200 ns)
report "Timing violation of tCC1 on RD!"
severity error;
when others =>
null;
end case;
end process rd_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Check WR
--
wr_check: process (wr_n_i)
begin
case wr_n_i is
-- WR active
when '0' =>
-- tLAFC1: ALE to Control WR
assert (now - last_ale_fall_s) > (t_CY / 5 - 75 ns)
report "Timing violation of tLAFC1 on WR!"
severity error;
-- tAW: Addr Setup to WR
assert (now - bus_change_ale_s) > (t_CY / 3 - 150 ns)
report "Timing violation of tAW on WR!"
severity error;
-- WR inactive
when '1' =>
-- tCC1: Control Pulse Width WR
assert (now - last_wr_n_fall_s) > (t_CY / 2 - 200 ns)
report "Timing violation of tCC1 on WR!"
severity error;
-- tDW: Data Setup before WR
assert (now - last_bus_change_s) > (t_CY * 13/30 - 200 ns)
report "Timing violation of tDW on WR!"
severity error;
when others =>
null;
end case;
end process wr_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Check BUS
--
bus_check: process (db_bus_i)
begin
-- RD access
-- tAD1 and tRD1 are not checked as they are constraints for the
-- external memory, not the t48!
-- WR access
if wr_n_i = '0' then
-- tDW: Data Hold after WR
assert (now - last_wr_n_rise_s) > (t_CY / 15 - 50 ns)
report "Timing violation of tDW on BUS vs. WR!"
severity error;
end if;
-- Address strobe
if ale_i = '0' then
-- tLA: Addr Hold from ALE
assert (now - last_ale_fall_s) > (t_CY / 15 - 40 ns)
report "Timing violation of tLA on BUS vs. ALE!"
severity error;
end if;
-- PSEN
if psen_n_i = '0' then
-- tRD2: PSEN to Data In
assert (now - last_psen_n_fall_s) < (t_CY * 4/15 - 170 ns)
report "Timing violation of tRD2 on BUS vs. PSEN!"
severity error;
end if;
end process bus_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Check ALE
--
ale_check: process (ale_i)
variable t_CA1 : time;
variable t_AL : time;
begin
case ale_i is
when '0' =>
t_AL := t_CY * 2/15 - 110 ns;
-- tAL: Addr Setup to ALE
assert (now - last_bus_change_s) > t_AL
report "Timing violation of tAL on BUS vs. ALE!"
severity error;
assert (now - last_p2_change_s) > t_AL
report "Timing violation of tAL on P2 vs. ALE!"
severity error;
when '1' =>
-- tCA1: Control to ALE (RD, WR, PROG)
t_CA1 := t_CY / 15 - 40 ns;
assert (now - last_rd_n_rise_s) > t_CA1
report "Timing violation of tCA1 on RD vs. ALE!"
severity error;
assert (now - last_wr_n_rise_s) > t_CA1
report "Timing violation of tCA1 on WR vs. ALE!"
severity error;
assert (now - last_prog_n_rise_s) > t_CA1
report "Timing violation of tCA1 on PROG vs. ALE!"
severity error;
-- tCA2: Control to ALE (PSEN)
assert (now - last_psen_n_rise_s) > (t_CY * 4/15 - 40 ns)
report "Timing violation of tCA2 on PSEN vs. ALE!"
severity error;
-- tPL: Port 2 I/O Setup to ALE
assert (now - last_p2_change_s) > (t_CY * 4/15 - 200 ns)
report "Timing violation of tPL on P2 vs. ALE!"
severity error;
when others =>
null;
end case;
end process ale_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Check P2
--
p2_check: process (p2_i)
begin
case ale_i is
when '0' =>
-- tLA: Addr Hold from ALE
assert ((now - last_ale_fall_s) > (t_CY / 15 - 40 ns)) or
now = 0 ns
report "Timing violation of tLA on P2 vs. ALE!"
severity error;
if last_ale_fall_s < last_ale_rise_s then
-- tPV: Port Output from ALE
assert (now - last_ale_fall_s) < (t_CY * 3/10 + 100 ns)
report "Timing violation of tPV on P2 vs. ALE!"
severity error;
end if;
if prog_n_i = '1' then
-- tPD: Output Data Hold
assert ((now - last_prog_n_rise_s) > (t_CY / 10 - 50 ns)) or
now = 0 ns
report "Timing violation of tPD on P2 vs. PROG!"
severity error;
end if;
when '1' =>
-- tLP: Port 2 I/O to ALE
assert (now - last_ale_rise_s) > (t_CY / 30 - 30 ns)
report "Timing violation of tLP on P2 vs. ALE!"
severity error;
when others =>
null;
end case;
end process p2_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Check PROG
--
prog_check: process (prog_n_i)
begin
case prog_n_i is
when '0' =>
-- tCP: Port Control Setup to PROG'
assert (now - last_p2_change_s) > (t_CY * 2/15 - 80 ns)
report "Timing violation of tCP on P2 vs PROG'!"
severity error;
when '1' =>
-- tPP: PROG Pulse Width
assert (now - last_prog_n_fall_s) > (t_CY * 7/10 - 250 ns)
report "Timing violation of tPP!"
severity error;
-- tDP: Output Data Setup
assert (now - last_p2_change_s) > (t_CY * 2/5 - 150 ns)
report "Timing violation of tDP on P2 vs. PROG!"
severity error;
when others =>
null;
end case;
end process prog_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Check PSEN
--
psen_check: process (psen_n_i)
begin
case psen_n_i is
when '1' =>
-- tCC2: Control Pulse Width PSEN
assert (now - last_psen_n_fall_s) > (t_CY * 2/5 - 200 ns)
report "Timing violation of tCC2 on PSEN!"
severity error;
when '0' =>
-- tLAFC2: ALE to Control PSEN
assert (now - last_ale_fall_s) > (t_CY / 10 - 75 ns)
report "Timing violation of tLAFC2 on PSEN vs. ALE!"
severity error;
when others =>
null;
end case;
end process psen_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Check cycle overlap
--
cycle_overlap_check: process (psen_n_i,
rd_n_i,
wr_n_i)
variable tmp_v : std_logic_vector(2 downto 0);
begin
tmp_v := psen_n_i & rd_n_i & wr_n_i;
case tmp_v is
when "001" |
"010" |
"100" |
"000" =>
assert false
report "Cycle overlap deteced on PSEN, RD and WR!"
severity error;
when others =>
null;
end case;
end process cycle_overlap_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor XTAL
--
xtal_mon: process
begin
last_xtal_rise_s <= 0 ns;
period_s <= 90 ns;
while true loop
wait on xtal_i;
if xtal_i = '1' then
period_s <= now - last_xtal_rise_s;
last_xtal_rise_s <= now;
end if;
end loop;
end process xtal_mon;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor ALE
--
ale_mon: process
begin
last_ale_rise_s <= 0 ns;
last_ale_fall_s <= 0 ns;
while true loop
wait on ale_i;
case ale_i is
when '0' =>
last_ale_fall_s <= now;
when '1' =>
last_ale_rise_s <= now;
when others =>
null;
end case;
end loop;
end process ale_mon;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor PSEN
--
psen_mon: process
begin
last_psen_n_rise_s <= 0 ns;
last_psen_n_fall_s <= 0 ns;
while true loop
wait on psen_n_i;
case psen_n_i is
when '0' =>
last_psen_n_fall_s <= now;
when '1' =>
last_psen_n_rise_s <= now;
when others =>
null;
end case;
end loop;
end process psen_mon;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor RD
--
rd_mon: process
begin
last_rd_n_rise_s <= 0 ns;
last_rd_n_fall_s <= 0 ns;
while true loop
wait on rd_n_i;
case rd_n_i is
when '0' =>
last_rd_n_fall_s <= now;
when '1' =>
last_rd_n_rise_s <= now;
when others =>
null;
end case;
end loop;
end process rd_mon;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor WR
--
wr_mon: process
begin
last_wr_n_rise_s <= 0 ns;
last_wr_n_fall_s <= 0 ns;
while true loop
wait on wr_n_i;
case wr_n_i is
when '0' =>
last_wr_n_fall_s <= now;
when '1' =>
last_wr_n_rise_s <= now;
when others =>
null;
end case;
end loop;
end process wr_mon;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor PROG
--
prog_mon: process
begin
last_prog_n_rise_s <= 0 ns;
last_prog_n_fall_s <= 0 ns;
while true loop
wait on prog_n_i;
case prog_n_i is
when '0' =>
last_prog_n_fall_s <= now;
when '1' =>
last_prog_n_rise_s <= now;
when others =>
null;
end case;
end loop;
end process prog_mon;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor BUS
--
bus_mon: process
begin
last_bus_change_s <= 0 ns;
bus_change_ale_s <= 0 ns;
while true loop
wait on db_bus_i;
last_bus_change_s <= now;
if ale_i = '1' then
bus_change_ale_s <= now;
end if;
end loop;
end process bus_mon;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Monitor P2
--
p2_mon: process
begin
last_p2_change_s <= 0 ns;
while true loop
wait on p2_i;
last_p2_change_s <= now;
end loop;
end process p2_mon;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.5 2004/12/03 19:58:55 arniml
-- add others to case statement
--
-- Revision 1.4 2004/10/25 19:33:13 arniml
-- remove tAW sanity check
-- conflicts with OUTL A, BUS
--
-- Revision 1.3 2004/09/12 00:31:50 arniml
-- add checks for PSEN
--
-- Revision 1.2 2004/04/25 20:40:58 arniml
-- check expander timings
--
-- Revision 1.1 2004/04/25 16:24:10 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-08A1.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Clock generator - 4 phase (T1,T2,T3,T4 and P1,P2,P3,P4)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Add registers to all clock outputs and delay rising edge of Px and Tx clocks
---------------------------------------------------------------------------
library IEEE;
Library UNISIM;
use UNISIM.vcomponents.all;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Gates_package.all;
use work.all;
entity Clock is Port (
-- Clock stuff
CLOCK_IN : in std_logic;
T1,T2,T3,T4 : out std_logic;
P1,P2,P3,P4 : out std_logic;
OSC_T_LINE : out std_logic; -- 12A
M_CONV_OSC : out std_logic; -- 03C
P_CONV_OSC : out std_logic; -- 03D,03C
M_CONV_OSC_2 : out std_logic; -- 03C
CLOCK_ON : out std_logic; -- 03D,04A,03C,13B,12A,11B
CLOCK_OFF : out std_logic; -- 04B,06C,09B,03D
CLOCK_START : in std_logic; -- 03C
MACH_RST_3 : in std_logic; -- 03D
Sw_Slow : in std_logic -- '1' to run slow
);
end Clock;
architecture FMD of Clock is
-- Following 2 lines to run clock at 5.33MHz (standard)
-- subtype DividerSize is STD_LOGIC_VECTOR(5 downto 0);
subtype DividerSize is STD_LOGIC_VECTOR(25 downto 0);
constant RATIOFast : DividerSize := "00000000000000000000001000"; -- 5 gives 10MHz => 720ns cycle
-- Following 2 lines to run clock at 5Hz
constant RATIOSlow : DividerSize := "00100010010101010001000000"; -- 5M gives 10Hz => 720ms cycle
constant ZERO : DividerSize := (others=>'0');
constant ONE : DividerSize := (0=>'1',others=>'0');
signal DIVIDER : DividerSize := (others=>'0');
signal DIVIDER_MAX : DividerSize;
signal OSC2,OSC,M_DLYD_OSC,DLYN_OSC,T1A,T2A,T3A,T4A,OSC2_DLYD : STD_LOGIC := '0';
-- signal SETS,RSTS : STD_LOGIC_VECTOR(1 to 4);
signal CLK : STD_LOGIC_VECTOR(1 to 4) := "0001";
signal P1D,P2D,P3D,P4D : STD_LOGIC;
signal OSC_T_LINEA, CLOCK_ONA, CLOCK_OFFA, P_CONV_OSCA,M_CONV_OSC_2A, N_OSC : STD_LOGIC;
begin
-- Divide the 50MHz FPGA clock down
-- 1.5us storage cycle means T1-4 takes 750ns, or 1.33MHz
-- The clock to generate the four phases is therefore 2.66MHz
-- OSC2 is actually double the original oscillator (5.33MHz) as only one edge is used
DIVIDER_MAX <= RatioSlow when Sw_Slow='1' else RATIOFast;
OSC2 <= '1' when DIVIDER > '0' & DIVIDER_MAX(DIVIDER_MAX'left downto 1) else '0';
N_OSC <= not OSC;
process (CLOCK_IN)
begin
if CLOCK_IN'event and CLOCK_IN='1' then
if DIVIDER>=DIVIDER_MAX then
DIVIDER <= ZERO;
else
DIVIDER <= DIVIDER + ONE;
end if;
end if;
end process;
-- AC1K6,AC1C6 Probably have to re-do this lot to get it work
--SETS(1) <= not DLYD_OSC and CLOCK_START and not CLK(3) and CLK(4);
--SETS(2) <= DLYD_OSC not CLK(4) and CLK(1);
--SETS(3) <= not DLYD_OSC and not CLK(1) and CLK(2);
--SETS(4) <= (DLYD_OSC and not CLK(2) and CLK(3)) or MACH_RST_3='1';
--RSTS(1) <= (not DLYD_OSC and CLK(2)) or MACH_RST_3='1';
--RSTS(2) <= (OSC and CLK(3)) or MACH_RST_3='1';
--RSTS(3) <= (not DLYD_OSC and CLK(4)) or MACH_RST_3='1';
--RSTS(4) <= OSC and CLK(1);
--FLV(SETS,RSTS,CLK); -- AC1C6
-- The following process forms a ring counter
-- MACH_RST_3 forces the counter to 0001
-- If CLOCK_START is false, the counter stays at 0001
-- When CLOCK_START goes true, the counter cycles through
-- 0001 0001 0001 1001 1100 0110 0011 1001 1100 ....
-- When CLOCK_START subsequently goes false, the sequence continues
-- until reaching 0011, after which it stays at 0001
-- ... 1001 1100 0110 0011 0001 0001 0001 ...
-- The original counter used a level-triggered implementation, driven by
-- both levels of the OSC signal. Here it is easier to make it edge triggered
-- which requires a clock of twice the frequency, hence OSC2
process (OSC2, MACH_RST_3, CLOCK_START)
begin
if OSC2'event and OSC2='1' then
if OSC='0' then -- OSC Rising edge: +P1 (P4=1 & START) -P3 (P4=1) or -P1 +P3 (P2=1)
OSC <= '1';
if CLK(2)='1' or MACH_RST_3='1' then
CLK(1) <= '0';
elsif CLOCK_START='1' and CLK(4)='1' then
CLK(1) <= '1';
end if;
if CLK(4)='1' or MACH_RST_3='1' then
CLK(3) <= '0';
elsif CLK(2)='1' then
CLK(3) <= '1';
end if;
else -- OSC Falling edge: +P2 -P4 (P1=1) or -P2 +P4 (P3=1)
OSC <= '0';
if CLK(3)='1' or MACH_RST_3='1' then
CLK(2) <= '0';
elsif CLK(1)='1' then
CLK(2) <= '1';
end if;
if CLK(3)='1' or MACH_RST_3='1' then
CLK(4) <= '1';
elsif CLK(1)='1' then
CLK(4) <= '0';
end if;
end if;
end if;
end process;
OSC_T_LINEA <= OSC; -- AC1B6
OSC_T_LINED : FDCE port map(D=>OSC_T_LINEA,Q=>OSC_T_LINE,CE=>'1',C=>CLOCK_IN,CLR=>'0');
M_CONV_OSCD : FDCE port map(D=>N_OSC,Q=>M_CONV_OSC,CE=>'1',C=>CLOCK_IN,CLR=>'0'); -- AC1C6
M_DLYD_OSC <= not OSC; -- AC1C6
DLYN_OSC <= OSC; -- AC1C6
-- P1 <= CLK(1);
-- P2 <= CLK(2);
-- P3 <= CLK(3);
-- P4 <= CLK(4);
-- Delay the rising edge of each P pulse to ensure that the T pulses never overlap
P1DLY: entity DelayRisingEdgeX port map (D=>CLK(1),CLK=>CLOCK_IN,Q=>P1D);
P2DLY: entity DelayRisingEdgeX port map (D=>CLK(2),CLK=>CLOCK_IN,Q=>P2D);
P3DLY: entity DelayRisingEdgeX port map (D=>CLK(3),CLK=>CLOCK_IN,Q=>P3D);
P4DLY: entity DelayRisingEdgeX port map (D=>CLK(4),CLK=>CLOCK_IN,Q=>P4D);
T1A <= P4D and P1D;
T2A <= P1D and P2D;
T3A <= P2D and P3D;
T4A <= P3D and P4D;
T1D : FDCE port map(D=>T1A,Q=>T1,CE=>'1',C=>CLOCK_IN,CLR=>'0');
T2D : FDCE port map(D=>T2A,Q=>T2,CE=>'1',C=>CLOCK_IN,CLR=>'0');
T3D : FDCE port map(D=>T3A,Q=>T3,CE=>'1',C=>CLOCK_IN,CLR=>'0');
T4D : FDCE port map(D=>T4A,Q=>T4,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P1C : FDCE port map(D=>P1D,Q=>P1,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P2C : FDCE port map(D=>P2D,Q=>P2,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P3C : FDCE port map(D=>P3D,Q=>P3,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P4C : FDCE port map(D=>P4D,Q=>P4,CE=>'1',C=>CLOCK_IN,CLR=>'0');
CLOCK_ONA <= CLK(1) or CLK(2) or CLK(3);
CLOCK_OND : FDCE port map(D=>CLOCK_ONA,Q=>CLOCK_ON,CE=>'1',C=>CLOCK_IN,CLR=>'0');
CLOCK_OFFA <= not CLOCK_ONA;
CLOCK_OFFD : FDCE port map(D=>CLOCK_OFFA,Q=>CLOCK_OFF,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P_CONV_OSCA <= OSC and CLOCK_OFFA;
P_CONV_OSCD : FDCE port map(D=>P_CONV_OSCA,Q=>P_CONV_OSC,CE=>'1',C=>CLOCK_IN,CLR=>'0');
M_CONV_OSC_2A <= not(P_CONV_OSCA);
M_CONV_OSC_2D : FDCE port map(D=>M_CONV_OSC_2A,Q=>M_CONV_OSC_2,CE=>'1',C=>CLOCK_IN,CLR=>'0');
end FMD;
|
-- $Id: tb_tst_rlink_n2.vhd 437 2011-12-09 19:38:07Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_n2
-- Description: Configuration for tb_tst_rlink_n2 for tb_nexys2_fusp
--
-- Dependencies: sys_tst_rlink_n2
--
-- To test: sys_tst_rlink_n2
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
-- 2010-12-xx xxx - 0.29 12.1 M53d xc3s1200e u:???
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_rlink_n2 of tb_nexys2_fusp is
for sim
for all : nexys2_fusp_aif
use entity work.sys_tst_rlink_n2;
end for;
end for;
end tb_tst_rlink_n2;
|
-- $Id: tb_tst_rlink_n2.vhd 437 2011-12-09 19:38:07Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_n2
-- Description: Configuration for tb_tst_rlink_n2 for tb_nexys2_fusp
--
-- Dependencies: sys_tst_rlink_n2
--
-- To test: sys_tst_rlink_n2
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
-- 2010-12-xx xxx - 0.29 12.1 M53d xc3s1200e u:???
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_rlink_n2 of tb_nexys2_fusp is
for sim
for all : nexys2_fusp_aif
use entity work.sys_tst_rlink_n2;
end for;
end for;
end tb_tst_rlink_n2;
|
library std;
use std.textio.all;
entity count is
end entity count;
architecture tb of count is
begin
p_test : process is
variable v_line : line;
variable nlines : natural := 0;
begin
while not endfile(input) loop
readline(input, v_line);
nlines := nlines + 1;
end loop;
report natural'image (nlines);
wait;
end process;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use work.PhoenixPackage.all;
use work.HammingPack16.all;
entity SwitchControl is
generic(address : regmetadeflit := (others=>'0'));
port(
clock : in std_logic;
reset : in std_logic;
h : in regNport; -- solicitacoes de chaveamento
ack_h : out regNport; -- resposta para as solitacoes de chaveamento
data : in arrayNport_regflit; -- dado do buffer (contem o endereco destino)
c_ctrl : in std_logic; -- indica se foi lido ou criado de um pacote de controle pelo buffer
c_CodControle : in regflit; -- codigo de controle do pacote de controle (terceiro flit do pacote de controle)
c_BuffCtrl : in buffControl; -- linha correspondente a tabela de roteamento lido do pacote de controle que sera escrita na tabela
c_buffTabelaFalhas_in: in row_FaultTable_Nport_Ports;
c_ce : in std_logic; -- chip enable da tabela de roteamento. Indica que sera escrito na tabela de roteamento
c_ceTF_in : in regNport; -- ce (chip enable) para escrever/atualizar a tabela de falhas
c_error_dir: out regNport; -- indica qual direcao/porta de saida o pacote sera encaminhado
c_error_ArrayFind: out ArrayRouterControl; -- indica se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
c_tabelaFalhas : out row_FaultTable_Ports; -- tabela de falhas atualizada/final
c_strLinkTst : in regNport; -- (start link test) indica que houve um pacote de controle do tipo TEST_LINKS para testar os links
c_faultTableFDM : in regNPort; -- tabela de falhas gerado pelo teste de links
sender : in regNport;
free : out regNport; -- portas de saida que estao livres
mux_in : out arrayNport_reg3;
mux_out : out arrayNport_reg3;
row_FaultTablePorts_in: in row_FaultTable_Ports; -- linhas a serem escritas na tabela (do FFPM)
write_FaultTable: in regHamm_Nport); -- sinal para indicar escrita na tabela (do FPPM)
end SwitchControl;
architecture RoutingTable of SwitchControl is
type state is (S0,S1,S2,S3,S4,S5,S6,S7);
signal ES, PES: state;
-- sinais do arbitro
signal ask: std_logic := '0';
signal sel,prox: integer range 0 to (NPORT-1) := 0;
signal incoming: reg3 := (others=> '0');
signal header : regflit := (others=> '0');
-- sinais do controle
signal indice_dir: integer range 0 to (NPORT-1) := 0;
signal tx,ty: regquartoflit := (others=> '0');
signal auxfree: regNport := (others=> '0');
signal source: arrayNport_reg3 := (others=> (others=> '0'));
signal sender_ant: regNport := (others=> '0');
signal dir: std_logic_vector(NPORT-1 downto 0):= (others=> '0');
-- sinais de controle da tabela
signal find: RouterControl;
signal ceTable: std_logic := '0';
-- sinais de controle de atualizacao da tabela de falhas
signal c_ceTF : std_logic := '0';
signal c_buffTabelaFalhas : row_FaultTable_Ports := (others=>(others=>'0'));
--sinais da Tabela de Falhas
signal tabelaDeFalhas : row_FaultTable_Ports := (others=>(others=>'0'));
signal c_checked: regNPort:= (others=>'0');
signal c_checkedArray: arrayRegNport :=(others=>(others=>'0'));
signal dirBuff : std_logic_vector(NPORT-1 downto 0):= (others=> '0');
signal strLinkTstAll : std_logic := '0';
signal ant_c_ceTF_in: regNPort:= (others=>'0');
begin
ask <= '1' when (h(LOCAL)='1' or h(EAST)='1' or h(WEST)='1' or h(NORTH)='1' or h(SOUTH)='1') else '0';
incoming <= CONV_VECTOR(sel);
header <= data(CONV_INTEGER(incoming));
-- escolhe uma das portas que solicitou chaveamento
process(sel, h)
begin
case sel is
when LOCAL=>
if h(EAST)='1' then prox<=EAST;
elsif h(WEST)='1' then prox<=WEST;
elsif h(NORTH)='1' then prox<=NORTH;
elsif h(SOUTH)='1' then prox<=SOUTH;
else prox<=LOCAL; end if;
when EAST=>
if h(WEST)='1' then prox<=WEST;
elsif h(NORTH)='1' then prox<=NORTH;
elsif h(SOUTH)='1' then prox<=SOUTH;
elsif h(LOCAL)='1' then prox<=LOCAL;
else prox<=EAST; end if;
when WEST=>
if h(NORTH)='1' then prox<=NORTH;
elsif h(SOUTH)='1' then prox<=SOUTH;
elsif h(LOCAL)='1' then prox<=LOCAL;
elsif h(EAST)='1' then prox<=EAST;
else prox<=WEST; end if;
when NORTH=>
if h(SOUTH)='1' then prox<=SOUTH;
elsif h(LOCAL)='1' then prox<=LOCAL;
elsif h(EAST)='1' then prox<=EAST;
elsif h(WEST)='1' then prox<=WEST;
else prox<=NORTH; end if;
when SOUTH=>
if h(LOCAL)='1' then prox<=LOCAL;
elsif h(EAST)='1' then prox<=EAST;
elsif h(WEST)='1' then prox<=WEST;
elsif h(NORTH)='1' then prox<=NORTH;
else prox<=SOUTH; end if;
end case;
end process;
tx <= header((METADEFLIT - 1) downto QUARTOFLIT); -- coordenada X do destino
ty <= header((QUARTOFLIT - 1) downto 0); -- coordernada Y do destino
------------------------------------------------------------
--gravacao da tabela de falhas
------------------------------------------------------------
--registrador para tabela de falhas
process(reset,clock)
begin
if reset='1' then
tabelaDeFalhas <= (others=>(others=>'0'));
elsif clock'event and clock='0' then
ant_c_ceTF_in <= c_ceTF_in;
-- se receber um pacote de controle para escrever/atualizar a tabela, escreve na tabela conforme a tabela recebida no pacote
if c_ceTF='1' then
tabelaDeFalhas <= c_buffTabelaFalhas;
-- se tiver feito o teste dos links, atualiza a tabela de falha conforme o resultado do teste
elsif strLinkTstAll = '1' then
--tabelaDeFalhas <= c_faultTableFDM;
tabelaDeFalhas(EAST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(EAST) & '0';
tabelaDeFalhas(WEST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(WEST) & '0';
tabelaDeFalhas(NORTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(NORTH) & '0';
tabelaDeFalhas(SOUTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(SOUTH) & '0';
-- escrita na tabela de falhas pelo FPPM
elsif (write_FaultTable /= 0) then
-- escreve apenas se o sinal de escrit tiver ativo e se o sttus do link tiver uma severidade maior ou igual a contida na tabela
for i in 0 to HAMM_NPORT-1 loop
if (write_FaultTable(i) = '1' and row_FaultTablePorts_in(i)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) >= tabelaDeFalhas(i)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE)) then
tabelaDeFalhas(i) <= row_FaultTablePorts_in(i);
end if;
end loop;
end if;
end if;
end process;
-- '1' se em algum buffer houve o pedido de teste de link (por causa do pacote de controle do tipo TEST_LINKS)
strLinkTstAll <= c_strLinkTst(0) or c_strLinkTst(1) or c_strLinkTst(2) or c_strLinkTst(3) or c_strLinkTst(4);
-- "merge" das telas recebidas
process(c_ceTF_in)
variable achou: regHamm_Nport := (others=>'0');
begin
for i in 0 to NPORT-1 loop
if (ant_c_ceTF_in(i)='1' and c_ceTF_in(i)='0') then
achou := (others=>'0');
exit;
end if;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "10") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como tendencia de falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "01") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como sem falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "00") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
end process;
-- '1' se em algum buffer tiver habilita o ce para escrever/atualizar a tabela de falhas
c_ceTF <= ( c_ceTF_in(EAST) OR
c_ceTF_in(WEST) OR
c_ceTF_in(SOUTH) OR
c_ceTF_in(NORTH) OR
c_ceTF_in(LOCAL));
------------------------------------------------------------
process(clock,reset)
begin
c_error_ArrayFind <= (others=>invalidRegion);
c_error_ArrayFind(sel) <= find;
end process;
c_error_dir <= dir;
c_tabelafalhas <= tabelaDeFalhas;
RoutingMechanism : entity work.routingMechanism
generic map(address => address)
port map(
clock => clock,
reset => reset,
buffCtrl => c_BuffCtrl, -- linha correspondente a tabela de roteamento lido do pacote de controle que sera escrita na tabela
ctrl=> c_Ctrl, -- indica se foi lido ou criado de um pacote de controle pelo buffer
operacao => c_CodControle, -- codigo de controle do pacote de controle (terceiro flit do pacote de controle)
ceT => c_ce, -- chip enable da tabela de roteamento. Indica que sera escrito na tabela de roteamento
oe => ceTable, -- usado para solicitar direcao/porta destino para a tabela de roteamento
dest => header((METADEFLIT - 1) downto 0), -- primeiro flit/header do pacote (contem o destino do pacote)
inputPort => sel, -- porta de entrada selecionada pelo arbitro para ser chaveada
outputPort => dir, -- indica qual porta de saida o pacote sera encaminhado
find => find -- indica se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
);
process(reset,clock)
begin
if reset='1' then
ES<=S0;
elsif clock'event and clock='0' then
ES<=PES;
end if;
end process;
------------------------------------------------------------------------------------------------------
-- PARTE COMBINACIONAL PARA DEFINIR O PROXIMO ESTADO DA MAQUINA
--
-- SO -> O estado S0 eh o estado de inicializacao da maquina. Este estado somente eh
-- atingido quando o sinal reset eh ativado.
-- S1 -> O estado S1 eh o estado de espera por requisicao de chaveamento. Quando o
-- arbitro recebe uma ou mais requisicoes, o sinal ask eh ativado fazendo a
-- maquina avancar para o estado S2.
-- S2 -> No estado S2 a porta de entrada que solicitou chaveamento eh selecionada. Se
-- houver mais de uma, aquela com maior prioridade eh a selecionada. Se o destino
-- for o proprio roteador pula para o estado S4, caso contrario segue o fluxo
-- normal.
-- S3 -> Este estado eh muito parecido com o do algoritmo XY, a diferenca eh que ele
-- verifica o destino do pacote atraves de uma tabela e nao por calculos.
-- 4 3 2 1 0
-- dir -> | Local | South | North | West | East |
process(ES,ask,h,tx,ty,auxfree,dir,find)
begin
case ES is
when S0 => PES <= S1;
when S1 => if ask='1' then PES <= S2; else PES <= S1; end if;
when S2 => PES <= S3;
when S3 =>
if address = header((METADEFLIT - 1) downto 0) and auxfree(LOCAL)='1' then PES<=S4;
-- se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
elsif(find = validRegion)then
if (h(sel)='0') then -- se desistiu de chavear (por causa do descarte do pacote)
PES <= S1;
-- se a porta de sai eh EAST e se ela estiver livre
elsif (dir(EAST)='1' and auxfree(EAST)='1') then
indice_dir <= EAST ;
PES<=S5;
elsif (dir(WEST)='1' and auxfree(WEST)='1') then
indice_dir <= WEST;
PES<=S5;
elsif (dir(NORTH)='1' and auxfree(NORTH)='1' ) then
indice_dir <= NORTH;
PES<=S6;
elsif (dir(SOUTH)='1' and auxfree(SOUTH)='1' ) then
indice_dir <= SOUTH;
PES<=S6;
else PES<=S1;
end if;
elsif(find = portError)then
PES <= S1;
else
PES<=S3;
end if;
when S4 => PES<=S7;
when S5 => PES<=S7;
when S6 => PES<=S7;
when S7 => PES<=S1;
end case;
end process;
------------------------------------------------------------------------------------------------------
-- executa as acoes correspondente ao estado atual da maquina de estados
------------------------------------------------------------------------------------------------------
process(clock)
begin
if clock'event and clock='1' then
case ES is
-- Zera variaveis
when S0 =>
ceTable <= '0';
sel <= 0;
ack_h <= (others => '0');
auxfree <= (others=> '1');
sender_ant <= (others=> '0');
mux_out <= (others=>(others=>'0'));
source <= (others=>(others=>'0'));
-- Chegou um header
when S1=>
ceTable <= '0';
ack_h <= (others => '0');
-- Seleciona quem tera direito a requisitar roteamento
when S2=>
sel <= prox;
-- Aguarda resposta da Tabela
when S3 =>
if address /= header((METADEFLIT - 1) downto 0) then
ceTable <= '1';
end if;
-- Estabelece a conexao com a porta LOCAL
when S4 =>
source(CONV_INTEGER(incoming)) <= CONV_VECTOR(LOCAL); -- sinal para a crossbar
mux_out(LOCAL) <= incoming; -- sinal para crossbar
auxfree(LOCAL) <= '0'; -- conexao estabelecida, logo porta ocupado
ack_h(sel)<='1'; -- responde que houve chaveamento com sucesso
-- Estabelece a conexao com a porta EAST ou WEST
when S5 =>
source(CONV_INTEGER(incoming)) <= CONV_VECTOR(indice_dir);
mux_out(indice_dir) <= incoming;
auxfree(indice_dir) <= '0';
ack_h(sel)<='1';
-- Estabelece a conexao com a porta NORTH ou SOUTH
when S6 =>
source(CONV_INTEGER(incoming)) <= CONV_VECTOR(indice_dir);
mux_out(indice_dir) <= incoming;
auxfree(indice_dir) <= '0';
ack_h(sel)<='1';
when others =>
ack_h(sel)<='0';
ceTable <= '0';
end case;
sender_ant(LOCAL) <= sender(LOCAL);
sender_ant(EAST) <= sender(EAST);
sender_ant(WEST) <= sender(WEST);
sender_ant(NORTH) <= sender(NORTH);
sender_ant(SOUTH) <= sender(SOUTH);
-- se uma porta estava transmitindo dados e agora nao esta mais, entao a porta ficou livre
if sender(LOCAL)='0' and sender_ant(LOCAL)='1' then auxfree(CONV_INTEGER(source(LOCAL))) <='1'; end if;
if sender(EAST) ='0' and sender_ant(EAST)='1' then auxfree(CONV_INTEGER(source(EAST))) <='1'; end if;
if sender(WEST) ='0' and sender_ant(WEST)='1' then auxfree(CONV_INTEGER(source(WEST))) <='1'; end if;
if sender(NORTH)='0' and sender_ant(NORTH)='1' then auxfree(CONV_INTEGER(source(NORTH))) <='1'; end if;
if sender(SOUTH)='0' and sender_ant(SOUTH)='1' then auxfree(CONV_INTEGER(source(SOUTH))) <='1'; end if;
end if;
end process;
mux_in <= source;
free <= auxfree;
end RoutingTable; |
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"),
(name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
begin
proc_label : process
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
begin end process;
end architecture rtl;
architecture rtl of fifo is
constant avmm_master_null : avmm_master_t := (
(others => '0'),
(others => '0'),
'0',
'0'
);
begin end architecture rtl;
architecture rtl of fifo is
constant cons1 : t_type := (
1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(
G_GENERIC3
)
)
)
)
);
constant cons1 : t_type := (1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(G_GENERIC3))
))
);
constant cons1 : t_type := (1 => func1(G_GENERIC1, G_GENERIC2),
2 => func2(func3(func4(
func5(G_GENERIC3))
)));
constant cons1 : t_type :=
(
1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(
G_GENERIC3
)
)
)
)
);
begin end architecture rtl;
architecture rtl of fifo is
constant cons1 : t_type := '0';
constant cons2 : t_type := '0' and '1'
and '0' or '1';
constant cons2 : t_type := func1(G_GENERIC1, G_GENERIC_2,
func2(G_GENERIC3));
begin end architecture rtl;
|
entity tb_asgn04 is
end tb_asgn04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn04 is
signal s0 : std_logic;
signal s1 : std_logic;
signal r : std_logic_vector (2 downto 0);
begin
dut: entity work.asgn04
port map (s0 => s0, s1 => s1, r => r);
process
begin
s0 <= '0';
s1 <= '0';
wait for 1 ns;
assert r = "000" severity failure;
s0 <= '0';
s1 <= '1';
wait for 1 ns;
assert r = "000" severity failure;
s0 <= '1';
s1 <= '0';
wait for 1 ns;
assert r = "010" severity failure;
s0 <= '1';
s1 <= '1';
wait for 1 ns;
assert r = "001" severity failure;
wait;
end process;
end behav;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_sofeof_gen.vhd
-- Description: This entity manages
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_sofeof_gen is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
axis_tready : in std_logic ; --
axis_tvalid : in std_logic ; --
axis_tlast : in std_logic ; --
--
packet_sof : out std_logic ; --
packet_eof : out std_logic --
--
);
end axi_dma_sofeof_gen;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_sofeof_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal p_ready : std_logic := '0';
signal p_valid : std_logic := '0';
signal p_valid_d1 : std_logic := '0';
signal p_valid_re : std_logic := '0';
signal p_last : std_logic := '0';
signal p_last_d1 : std_logic := '0';
signal p_last_re : std_logic := '0';
signal s_ready : std_logic := '0';
signal s_valid : std_logic := '0';
signal s_valid_d1 : std_logic := '0';
signal s_valid_re : std_logic := '0';
signal s_last : std_logic := '0';
signal s_last_d1 : std_logic := '0';
signal s_last_re : std_logic := '0';
signal s_sof_d1_cdc_tig : std_logic := '0';
signal s_sof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s_sof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_sof_d2 : SIGNAL IS "true";
signal s_sof_d3 : std_logic := '0';
signal s_sof_re : std_logic := '0';
signal s_sof : std_logic := '0';
signal p_sof : std_logic := '0';
signal s_eof_d1_cdc_tig : std_logic := '0';
signal s_eof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s_eof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_eof_d2 : SIGNAL IS "true";
signal s_eof_d3 : std_logic := '0';
signal s_eof_re : std_logic := '0';
signal p_eof : std_logic := '0';
signal p_eof_d1_cdc_tig : std_logic := '0';
signal p_eof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_eof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_eof_d2 : SIGNAL IS "true";
signal p_eof_d3 : std_logic := '0';
signal p_eof_clr : std_logic := '0';
signal s_sof_generated : std_logic := '0';
signal sof_generated_fe : std_logic := '0';
signal s_eof_re_latch : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- pass internal version out
packet_sof <= s_sof_re;
packet_eof <= s_eof_re;
-- Generate for when primary clock is asynchronous
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
---------------------------------------------------------------------------
-- Generate Packet SOF
---------------------------------------------------------------------------
-- Register stream control in to isolate wrt clock
-- for timing closure
REG_STRM_IN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_valid <= '0';
p_last <= '0';
p_ready <= '0';
else
p_valid <= axis_tvalid;
p_last <= axis_tlast ;
p_ready <= axis_tready;
end if;
end if;
end process REG_STRM_IN;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_valid_d1 <= '0';
p_last_d1 <= '0';
p_last_re <= '0';
else
p_valid_d1 <= p_valid and p_ready;
p_last_d1 <= p_last and p_valid and p_ready;
-- register to aligne with setting of p_sof
p_last_re <= p_ready and p_valid and p_last and not p_last_d1;
end if;
end if;
end process REG_FOR_RE;
p_valid_re <= p_ready and p_valid and not p_valid_d1;
-- Sample and hold valid re to create sof
SOF_SMPL_N_HOLD : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- clear at end of packet
if(p_reset_n = '0' or p_eof_clr = '1')then
p_sof <= '0';
-- assert at beginning of packet hold to allow
-- clock crossing to slower secondary clk
elsif(p_valid_re = '1')then
p_sof <= '1';
end if;
end if;
end process SOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
SOF_REG2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_sof,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_sof_d2,
scndry_vect_out => open
);
SOF_REG2SCNDRY1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
-- s_sof_d1_cdc_tig <= '0';
-- s_sof_d2 <= '0';
s_sof_d3 <= '0';
else
-- s_sof_d1_cdc_tig <= p_sof;
-- s_sof_d2 <= s_sof_d1_cdc_tig;
s_sof_d3 <= s_sof_d2;
end if;
end if;
end process SOF_REG2SCNDRY1;
s_sof_re <= s_sof_d2 and not s_sof_d3;
---------------------------------------------------------------------------
-- Generate Packet EOF
---------------------------------------------------------------------------
-- Sample and hold valid re to create sof
EOF_SMPL_N_HOLD : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0' or p_eof_clr = '1')then
p_eof <= '0';
-- if p_last but p_sof not set then it means between pkt
-- gap was too small to catch new sof. therefor do not
-- generate eof
elsif(p_last_re = '1' and p_sof = '0')then
p_eof <= '0';
elsif(p_last_re = '1')then
p_eof <= '1';
end if;
end if;
end process EOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
-- CDC register has to be a pure flop
EOF_REG2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_eof,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_eof_d2,
scndry_vect_out => open
);
EOF_REG2SCNDRY1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
-- s_eof_d1_cdc_tig <= '0';
-- s_eof_d2 <= '0';
s_eof_d3 <= '0'; -- CR605883
else
-- s_eof_d1_cdc_tig <= p_eof;
-- s_eof_d2 <= s_eof_d1_cdc_tig;
s_eof_d3 <= s_eof_d2; -- CR605883
end if;
end if;
end process EOF_REG2SCNDRY1;
s_eof_re <= s_eof_d2 and not s_eof_d3;
EOF_latch : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_eof_re_latch <= '0';
elsif (s_eof_re = '1') then
s_eof_re_latch <= not s_eof_re_latch;
end if;
end if;
end process EOF_latch;
-- Register s_sof_re back into primary clock domain to use
-- as clear of p_sof.
EOF_REG2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_eof_re_latch,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_eof_d2,
scndry_vect_out => open
);
EOF_REG2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_eof_d1_cdc_tig <= '0';
-- p_eof_d2 <= '0';
p_eof_d3 <= '0';
else
-- p_eof_d1_cdc_tig <= s_eof_re_latch;
-- p_eof_d2 <= p_eof_d1_cdc_tig;
p_eof_d3 <= p_eof_d2;
end if;
end if;
end process EOF_REG2PRMRY1;
-- p_eof_clr <= p_eof_d2 and not p_eof_d3;-- CR565366
-- drive eof clear for minimum of 2 scndry clocks
-- to guarentee secondary capture. this allows
-- new valid assertions to not be missed in
-- creating next sof.
p_eof_clr <= p_eof_d2 xor p_eof_d3;
end generate GEN_FOR_ASYNC;
-- Generate for when primary clock is synchronous
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
---------------------------------------------------------------------------
-- Generate Packet EOF and SOF
---------------------------------------------------------------------------
-- Register stream control in to isolate wrt clock
-- for timing closure
REG_STRM_IN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_valid <= '0';
s_last <= '0';
s_ready <= '0';
else
s_valid <= axis_tvalid;
s_last <= axis_tlast ;
s_ready <= axis_tready;
end if;
end if;
end process REG_STRM_IN;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_valid_d1 <= '0';
s_last_d1 <= '0';
else
s_valid_d1 <= s_valid and s_ready;
s_last_d1 <= s_last and s_valid and s_ready;
end if;
end if;
end process REG_FOR_RE;
-- CR565366 investigating delay interurpt issue discovered
-- this coding issue.
-- s_valid_re <= s_ready and s_valid and not s_last_d1;
s_valid_re <= s_ready and s_valid and not s_valid_d1;
s_last_re <= s_ready and s_valid and s_last and not s_last_d1;
-- Sample and hold valid re to create sof
SOF_SMPL_N_HOLD : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(p_reset_n = '0' or s_eof_re = '1')then
s_sof_generated <= '0';
-- new
elsif((s_valid_re = '1')
or (sof_generated_fe = '1' and s_ready = '1' and s_valid = '1'))then
s_sof_generated <= '1';
end if;
end if;
end process SOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
SOF_REG2SCNDRY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_sof_d1_cdc_tig <= '0';
else
s_sof_d1_cdc_tig <= s_sof_generated;
end if;
end if;
end process SOF_REG2SCNDRY;
-- generate falling edge pulse on end of packet for use if
-- need to generate an immediate sof.
sof_generated_fe <= not s_sof_generated and s_sof_d1_cdc_tig;
-- generate SOF on rising edge of valid if not already in a packet OR...
s_sof_re <= '1' when (s_valid_re = '1' and s_sof_generated = '0')
or (sof_generated_fe = '1' -- If end of previous packet
and s_ready = '1' -- and ready asserted
and s_valid = '1') -- and valid asserted
else '0';
-- generate eof on rising edge of valid last assertion OR...
s_eof_re <= '1' when (s_last_re = '1')
or (sof_generated_fe = '1' -- If end of previous packet
and s_ready = '1' -- and ready asserted
and s_valid = '1' -- and valid asserted
and s_last = '1') -- and last asserted
else '0';
end generate GEN_FOR_SYNC;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_sofeof_gen.vhd
-- Description: This entity manages
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_sofeof_gen is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
axis_tready : in std_logic ; --
axis_tvalid : in std_logic ; --
axis_tlast : in std_logic ; --
--
packet_sof : out std_logic ; --
packet_eof : out std_logic --
--
);
end axi_dma_sofeof_gen;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_sofeof_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal p_ready : std_logic := '0';
signal p_valid : std_logic := '0';
signal p_valid_d1 : std_logic := '0';
signal p_valid_re : std_logic := '0';
signal p_last : std_logic := '0';
signal p_last_d1 : std_logic := '0';
signal p_last_re : std_logic := '0';
signal s_ready : std_logic := '0';
signal s_valid : std_logic := '0';
signal s_valid_d1 : std_logic := '0';
signal s_valid_re : std_logic := '0';
signal s_last : std_logic := '0';
signal s_last_d1 : std_logic := '0';
signal s_last_re : std_logic := '0';
signal s_sof_d1_cdc_tig : std_logic := '0';
signal s_sof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s_sof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_sof_d2 : SIGNAL IS "true";
signal s_sof_d3 : std_logic := '0';
signal s_sof_re : std_logic := '0';
signal s_sof : std_logic := '0';
signal p_sof : std_logic := '0';
signal s_eof_d1_cdc_tig : std_logic := '0';
signal s_eof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s_eof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_eof_d2 : SIGNAL IS "true";
signal s_eof_d3 : std_logic := '0';
signal s_eof_re : std_logic := '0';
signal p_eof : std_logic := '0';
signal p_eof_d1_cdc_tig : std_logic := '0';
signal p_eof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_eof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_eof_d2 : SIGNAL IS "true";
signal p_eof_d3 : std_logic := '0';
signal p_eof_clr : std_logic := '0';
signal s_sof_generated : std_logic := '0';
signal sof_generated_fe : std_logic := '0';
signal s_eof_re_latch : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- pass internal version out
packet_sof <= s_sof_re;
packet_eof <= s_eof_re;
-- Generate for when primary clock is asynchronous
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
---------------------------------------------------------------------------
-- Generate Packet SOF
---------------------------------------------------------------------------
-- Register stream control in to isolate wrt clock
-- for timing closure
REG_STRM_IN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_valid <= '0';
p_last <= '0';
p_ready <= '0';
else
p_valid <= axis_tvalid;
p_last <= axis_tlast ;
p_ready <= axis_tready;
end if;
end if;
end process REG_STRM_IN;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_valid_d1 <= '0';
p_last_d1 <= '0';
p_last_re <= '0';
else
p_valid_d1 <= p_valid and p_ready;
p_last_d1 <= p_last and p_valid and p_ready;
-- register to aligne with setting of p_sof
p_last_re <= p_ready and p_valid and p_last and not p_last_d1;
end if;
end if;
end process REG_FOR_RE;
p_valid_re <= p_ready and p_valid and not p_valid_d1;
-- Sample and hold valid re to create sof
SOF_SMPL_N_HOLD : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- clear at end of packet
if(p_reset_n = '0' or p_eof_clr = '1')then
p_sof <= '0';
-- assert at beginning of packet hold to allow
-- clock crossing to slower secondary clk
elsif(p_valid_re = '1')then
p_sof <= '1';
end if;
end if;
end process SOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
SOF_REG2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_sof,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_sof_d2,
scndry_vect_out => open
);
SOF_REG2SCNDRY1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
-- s_sof_d1_cdc_tig <= '0';
-- s_sof_d2 <= '0';
s_sof_d3 <= '0';
else
-- s_sof_d1_cdc_tig <= p_sof;
-- s_sof_d2 <= s_sof_d1_cdc_tig;
s_sof_d3 <= s_sof_d2;
end if;
end if;
end process SOF_REG2SCNDRY1;
s_sof_re <= s_sof_d2 and not s_sof_d3;
---------------------------------------------------------------------------
-- Generate Packet EOF
---------------------------------------------------------------------------
-- Sample and hold valid re to create sof
EOF_SMPL_N_HOLD : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0' or p_eof_clr = '1')then
p_eof <= '0';
-- if p_last but p_sof not set then it means between pkt
-- gap was too small to catch new sof. therefor do not
-- generate eof
elsif(p_last_re = '1' and p_sof = '0')then
p_eof <= '0';
elsif(p_last_re = '1')then
p_eof <= '1';
end if;
end if;
end process EOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
-- CDC register has to be a pure flop
EOF_REG2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_eof,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_eof_d2,
scndry_vect_out => open
);
EOF_REG2SCNDRY1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
-- s_eof_d1_cdc_tig <= '0';
-- s_eof_d2 <= '0';
s_eof_d3 <= '0'; -- CR605883
else
-- s_eof_d1_cdc_tig <= p_eof;
-- s_eof_d2 <= s_eof_d1_cdc_tig;
s_eof_d3 <= s_eof_d2; -- CR605883
end if;
end if;
end process EOF_REG2SCNDRY1;
s_eof_re <= s_eof_d2 and not s_eof_d3;
EOF_latch : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_eof_re_latch <= '0';
elsif (s_eof_re = '1') then
s_eof_re_latch <= not s_eof_re_latch;
end if;
end if;
end process EOF_latch;
-- Register s_sof_re back into primary clock domain to use
-- as clear of p_sof.
EOF_REG2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_eof_re_latch,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_eof_d2,
scndry_vect_out => open
);
EOF_REG2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_eof_d1_cdc_tig <= '0';
-- p_eof_d2 <= '0';
p_eof_d3 <= '0';
else
-- p_eof_d1_cdc_tig <= s_eof_re_latch;
-- p_eof_d2 <= p_eof_d1_cdc_tig;
p_eof_d3 <= p_eof_d2;
end if;
end if;
end process EOF_REG2PRMRY1;
-- p_eof_clr <= p_eof_d2 and not p_eof_d3;-- CR565366
-- drive eof clear for minimum of 2 scndry clocks
-- to guarentee secondary capture. this allows
-- new valid assertions to not be missed in
-- creating next sof.
p_eof_clr <= p_eof_d2 xor p_eof_d3;
end generate GEN_FOR_ASYNC;
-- Generate for when primary clock is synchronous
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
---------------------------------------------------------------------------
-- Generate Packet EOF and SOF
---------------------------------------------------------------------------
-- Register stream control in to isolate wrt clock
-- for timing closure
REG_STRM_IN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_valid <= '0';
s_last <= '0';
s_ready <= '0';
else
s_valid <= axis_tvalid;
s_last <= axis_tlast ;
s_ready <= axis_tready;
end if;
end if;
end process REG_STRM_IN;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_valid_d1 <= '0';
s_last_d1 <= '0';
else
s_valid_d1 <= s_valid and s_ready;
s_last_d1 <= s_last and s_valid and s_ready;
end if;
end if;
end process REG_FOR_RE;
-- CR565366 investigating delay interurpt issue discovered
-- this coding issue.
-- s_valid_re <= s_ready and s_valid and not s_last_d1;
s_valid_re <= s_ready and s_valid and not s_valid_d1;
s_last_re <= s_ready and s_valid and s_last and not s_last_d1;
-- Sample and hold valid re to create sof
SOF_SMPL_N_HOLD : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(p_reset_n = '0' or s_eof_re = '1')then
s_sof_generated <= '0';
-- new
elsif((s_valid_re = '1')
or (sof_generated_fe = '1' and s_ready = '1' and s_valid = '1'))then
s_sof_generated <= '1';
end if;
end if;
end process SOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
SOF_REG2SCNDRY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_sof_d1_cdc_tig <= '0';
else
s_sof_d1_cdc_tig <= s_sof_generated;
end if;
end if;
end process SOF_REG2SCNDRY;
-- generate falling edge pulse on end of packet for use if
-- need to generate an immediate sof.
sof_generated_fe <= not s_sof_generated and s_sof_d1_cdc_tig;
-- generate SOF on rising edge of valid if not already in a packet OR...
s_sof_re <= '1' when (s_valid_re = '1' and s_sof_generated = '0')
or (sof_generated_fe = '1' -- If end of previous packet
and s_ready = '1' -- and ready asserted
and s_valid = '1') -- and valid asserted
else '0';
-- generate eof on rising edge of valid last assertion OR...
s_eof_re <= '1' when (s_last_re = '1')
or (sof_generated_fe = '1' -- If end of previous packet
and s_ready = '1' -- and ready asserted
and s_valid = '1' -- and valid asserted
and s_last = '1') -- and last asserted
else '0';
end generate GEN_FOR_SYNC;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_sofeof_gen.vhd
-- Description: This entity manages
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_sofeof_gen is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
axis_tready : in std_logic ; --
axis_tvalid : in std_logic ; --
axis_tlast : in std_logic ; --
--
packet_sof : out std_logic ; --
packet_eof : out std_logic --
--
);
end axi_dma_sofeof_gen;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_sofeof_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal p_ready : std_logic := '0';
signal p_valid : std_logic := '0';
signal p_valid_d1 : std_logic := '0';
signal p_valid_re : std_logic := '0';
signal p_last : std_logic := '0';
signal p_last_d1 : std_logic := '0';
signal p_last_re : std_logic := '0';
signal s_ready : std_logic := '0';
signal s_valid : std_logic := '0';
signal s_valid_d1 : std_logic := '0';
signal s_valid_re : std_logic := '0';
signal s_last : std_logic := '0';
signal s_last_d1 : std_logic := '0';
signal s_last_re : std_logic := '0';
signal s_sof_d1_cdc_tig : std_logic := '0';
signal s_sof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s_sof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_sof_d2 : SIGNAL IS "true";
signal s_sof_d3 : std_logic := '0';
signal s_sof_re : std_logic := '0';
signal s_sof : std_logic := '0';
signal p_sof : std_logic := '0';
signal s_eof_d1_cdc_tig : std_logic := '0';
signal s_eof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s_eof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_eof_d2 : SIGNAL IS "true";
signal s_eof_d3 : std_logic := '0';
signal s_eof_re : std_logic := '0';
signal p_eof : std_logic := '0';
signal p_eof_d1_cdc_tig : std_logic := '0';
signal p_eof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_eof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_eof_d2 : SIGNAL IS "true";
signal p_eof_d3 : std_logic := '0';
signal p_eof_clr : std_logic := '0';
signal s_sof_generated : std_logic := '0';
signal sof_generated_fe : std_logic := '0';
signal s_eof_re_latch : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- pass internal version out
packet_sof <= s_sof_re;
packet_eof <= s_eof_re;
-- Generate for when primary clock is asynchronous
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
---------------------------------------------------------------------------
-- Generate Packet SOF
---------------------------------------------------------------------------
-- Register stream control in to isolate wrt clock
-- for timing closure
REG_STRM_IN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_valid <= '0';
p_last <= '0';
p_ready <= '0';
else
p_valid <= axis_tvalid;
p_last <= axis_tlast ;
p_ready <= axis_tready;
end if;
end if;
end process REG_STRM_IN;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_valid_d1 <= '0';
p_last_d1 <= '0';
p_last_re <= '0';
else
p_valid_d1 <= p_valid and p_ready;
p_last_d1 <= p_last and p_valid and p_ready;
-- register to aligne with setting of p_sof
p_last_re <= p_ready and p_valid and p_last and not p_last_d1;
end if;
end if;
end process REG_FOR_RE;
p_valid_re <= p_ready and p_valid and not p_valid_d1;
-- Sample and hold valid re to create sof
SOF_SMPL_N_HOLD : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- clear at end of packet
if(p_reset_n = '0' or p_eof_clr = '1')then
p_sof <= '0';
-- assert at beginning of packet hold to allow
-- clock crossing to slower secondary clk
elsif(p_valid_re = '1')then
p_sof <= '1';
end if;
end if;
end process SOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
SOF_REG2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_sof,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_sof_d2,
scndry_vect_out => open
);
SOF_REG2SCNDRY1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
-- s_sof_d1_cdc_tig <= '0';
-- s_sof_d2 <= '0';
s_sof_d3 <= '0';
else
-- s_sof_d1_cdc_tig <= p_sof;
-- s_sof_d2 <= s_sof_d1_cdc_tig;
s_sof_d3 <= s_sof_d2;
end if;
end if;
end process SOF_REG2SCNDRY1;
s_sof_re <= s_sof_d2 and not s_sof_d3;
---------------------------------------------------------------------------
-- Generate Packet EOF
---------------------------------------------------------------------------
-- Sample and hold valid re to create sof
EOF_SMPL_N_HOLD : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0' or p_eof_clr = '1')then
p_eof <= '0';
-- if p_last but p_sof not set then it means between pkt
-- gap was too small to catch new sof. therefor do not
-- generate eof
elsif(p_last_re = '1' and p_sof = '0')then
p_eof <= '0';
elsif(p_last_re = '1')then
p_eof <= '1';
end if;
end if;
end process EOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
-- CDC register has to be a pure flop
EOF_REG2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_eof,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_eof_d2,
scndry_vect_out => open
);
EOF_REG2SCNDRY1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
-- s_eof_d1_cdc_tig <= '0';
-- s_eof_d2 <= '0';
s_eof_d3 <= '0'; -- CR605883
else
-- s_eof_d1_cdc_tig <= p_eof;
-- s_eof_d2 <= s_eof_d1_cdc_tig;
s_eof_d3 <= s_eof_d2; -- CR605883
end if;
end if;
end process EOF_REG2SCNDRY1;
s_eof_re <= s_eof_d2 and not s_eof_d3;
EOF_latch : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_eof_re_latch <= '0';
elsif (s_eof_re = '1') then
s_eof_re_latch <= not s_eof_re_latch;
end if;
end if;
end process EOF_latch;
-- Register s_sof_re back into primary clock domain to use
-- as clear of p_sof.
EOF_REG2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_eof_re_latch,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_eof_d2,
scndry_vect_out => open
);
EOF_REG2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_eof_d1_cdc_tig <= '0';
-- p_eof_d2 <= '0';
p_eof_d3 <= '0';
else
-- p_eof_d1_cdc_tig <= s_eof_re_latch;
-- p_eof_d2 <= p_eof_d1_cdc_tig;
p_eof_d3 <= p_eof_d2;
end if;
end if;
end process EOF_REG2PRMRY1;
-- p_eof_clr <= p_eof_d2 and not p_eof_d3;-- CR565366
-- drive eof clear for minimum of 2 scndry clocks
-- to guarentee secondary capture. this allows
-- new valid assertions to not be missed in
-- creating next sof.
p_eof_clr <= p_eof_d2 xor p_eof_d3;
end generate GEN_FOR_ASYNC;
-- Generate for when primary clock is synchronous
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
---------------------------------------------------------------------------
-- Generate Packet EOF and SOF
---------------------------------------------------------------------------
-- Register stream control in to isolate wrt clock
-- for timing closure
REG_STRM_IN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_valid <= '0';
s_last <= '0';
s_ready <= '0';
else
s_valid <= axis_tvalid;
s_last <= axis_tlast ;
s_ready <= axis_tready;
end if;
end if;
end process REG_STRM_IN;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_valid_d1 <= '0';
s_last_d1 <= '0';
else
s_valid_d1 <= s_valid and s_ready;
s_last_d1 <= s_last and s_valid and s_ready;
end if;
end if;
end process REG_FOR_RE;
-- CR565366 investigating delay interurpt issue discovered
-- this coding issue.
-- s_valid_re <= s_ready and s_valid and not s_last_d1;
s_valid_re <= s_ready and s_valid and not s_valid_d1;
s_last_re <= s_ready and s_valid and s_last and not s_last_d1;
-- Sample and hold valid re to create sof
SOF_SMPL_N_HOLD : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(p_reset_n = '0' or s_eof_re = '1')then
s_sof_generated <= '0';
-- new
elsif((s_valid_re = '1')
or (sof_generated_fe = '1' and s_ready = '1' and s_valid = '1'))then
s_sof_generated <= '1';
end if;
end if;
end process SOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
SOF_REG2SCNDRY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_sof_d1_cdc_tig <= '0';
else
s_sof_d1_cdc_tig <= s_sof_generated;
end if;
end if;
end process SOF_REG2SCNDRY;
-- generate falling edge pulse on end of packet for use if
-- need to generate an immediate sof.
sof_generated_fe <= not s_sof_generated and s_sof_d1_cdc_tig;
-- generate SOF on rising edge of valid if not already in a packet OR...
s_sof_re <= '1' when (s_valid_re = '1' and s_sof_generated = '0')
or (sof_generated_fe = '1' -- If end of previous packet
and s_ready = '1' -- and ready asserted
and s_valid = '1') -- and valid asserted
else '0';
-- generate eof on rising edge of valid last assertion OR...
s_eof_re <= '1' when (s_last_re = '1')
or (sof_generated_fe = '1' -- If end of previous packet
and s_ready = '1' -- and ready asserted
and s_valid = '1' -- and valid asserted
and s_last = '1') -- and last asserted
else '0';
end generate GEN_FOR_SYNC;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_sofeof_gen.vhd
-- Description: This entity manages
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_sofeof_gen is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
axis_tready : in std_logic ; --
axis_tvalid : in std_logic ; --
axis_tlast : in std_logic ; --
--
packet_sof : out std_logic ; --
packet_eof : out std_logic --
--
);
end axi_dma_sofeof_gen;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_sofeof_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal p_ready : std_logic := '0';
signal p_valid : std_logic := '0';
signal p_valid_d1 : std_logic := '0';
signal p_valid_re : std_logic := '0';
signal p_last : std_logic := '0';
signal p_last_d1 : std_logic := '0';
signal p_last_re : std_logic := '0';
signal s_ready : std_logic := '0';
signal s_valid : std_logic := '0';
signal s_valid_d1 : std_logic := '0';
signal s_valid_re : std_logic := '0';
signal s_last : std_logic := '0';
signal s_last_d1 : std_logic := '0';
signal s_last_re : std_logic := '0';
signal s_sof_d1_cdc_tig : std_logic := '0';
signal s_sof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s_sof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_sof_d2 : SIGNAL IS "true";
signal s_sof_d3 : std_logic := '0';
signal s_sof_re : std_logic := '0';
signal s_sof : std_logic := '0';
signal p_sof : std_logic := '0';
signal s_eof_d1_cdc_tig : std_logic := '0';
signal s_eof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s_eof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_eof_d2 : SIGNAL IS "true";
signal s_eof_d3 : std_logic := '0';
signal s_eof_re : std_logic := '0';
signal p_eof : std_logic := '0';
signal p_eof_d1_cdc_tig : std_logic := '0';
signal p_eof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_eof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_eof_d2 : SIGNAL IS "true";
signal p_eof_d3 : std_logic := '0';
signal p_eof_clr : std_logic := '0';
signal s_sof_generated : std_logic := '0';
signal sof_generated_fe : std_logic := '0';
signal s_eof_re_latch : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- pass internal version out
packet_sof <= s_sof_re;
packet_eof <= s_eof_re;
-- Generate for when primary clock is asynchronous
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
---------------------------------------------------------------------------
-- Generate Packet SOF
---------------------------------------------------------------------------
-- Register stream control in to isolate wrt clock
-- for timing closure
REG_STRM_IN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_valid <= '0';
p_last <= '0';
p_ready <= '0';
else
p_valid <= axis_tvalid;
p_last <= axis_tlast ;
p_ready <= axis_tready;
end if;
end if;
end process REG_STRM_IN;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_valid_d1 <= '0';
p_last_d1 <= '0';
p_last_re <= '0';
else
p_valid_d1 <= p_valid and p_ready;
p_last_d1 <= p_last and p_valid and p_ready;
-- register to aligne with setting of p_sof
p_last_re <= p_ready and p_valid and p_last and not p_last_d1;
end if;
end if;
end process REG_FOR_RE;
p_valid_re <= p_ready and p_valid and not p_valid_d1;
-- Sample and hold valid re to create sof
SOF_SMPL_N_HOLD : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- clear at end of packet
if(p_reset_n = '0' or p_eof_clr = '1')then
p_sof <= '0';
-- assert at beginning of packet hold to allow
-- clock crossing to slower secondary clk
elsif(p_valid_re = '1')then
p_sof <= '1';
end if;
end if;
end process SOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
SOF_REG2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_sof,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_sof_d2,
scndry_vect_out => open
);
SOF_REG2SCNDRY1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
-- s_sof_d1_cdc_tig <= '0';
-- s_sof_d2 <= '0';
s_sof_d3 <= '0';
else
-- s_sof_d1_cdc_tig <= p_sof;
-- s_sof_d2 <= s_sof_d1_cdc_tig;
s_sof_d3 <= s_sof_d2;
end if;
end if;
end process SOF_REG2SCNDRY1;
s_sof_re <= s_sof_d2 and not s_sof_d3;
---------------------------------------------------------------------------
-- Generate Packet EOF
---------------------------------------------------------------------------
-- Sample and hold valid re to create sof
EOF_SMPL_N_HOLD : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0' or p_eof_clr = '1')then
p_eof <= '0';
-- if p_last but p_sof not set then it means between pkt
-- gap was too small to catch new sof. therefor do not
-- generate eof
elsif(p_last_re = '1' and p_sof = '0')then
p_eof <= '0';
elsif(p_last_re = '1')then
p_eof <= '1';
end if;
end if;
end process EOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
-- CDC register has to be a pure flop
EOF_REG2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_eof,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_eof_d2,
scndry_vect_out => open
);
EOF_REG2SCNDRY1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
-- s_eof_d1_cdc_tig <= '0';
-- s_eof_d2 <= '0';
s_eof_d3 <= '0'; -- CR605883
else
-- s_eof_d1_cdc_tig <= p_eof;
-- s_eof_d2 <= s_eof_d1_cdc_tig;
s_eof_d3 <= s_eof_d2; -- CR605883
end if;
end if;
end process EOF_REG2SCNDRY1;
s_eof_re <= s_eof_d2 and not s_eof_d3;
EOF_latch : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_eof_re_latch <= '0';
elsif (s_eof_re = '1') then
s_eof_re_latch <= not s_eof_re_latch;
end if;
end if;
end process EOF_latch;
-- Register s_sof_re back into primary clock domain to use
-- as clear of p_sof.
EOF_REG2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_eof_re_latch,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_eof_d2,
scndry_vect_out => open
);
EOF_REG2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_eof_d1_cdc_tig <= '0';
-- p_eof_d2 <= '0';
p_eof_d3 <= '0';
else
-- p_eof_d1_cdc_tig <= s_eof_re_latch;
-- p_eof_d2 <= p_eof_d1_cdc_tig;
p_eof_d3 <= p_eof_d2;
end if;
end if;
end process EOF_REG2PRMRY1;
-- p_eof_clr <= p_eof_d2 and not p_eof_d3;-- CR565366
-- drive eof clear for minimum of 2 scndry clocks
-- to guarentee secondary capture. this allows
-- new valid assertions to not be missed in
-- creating next sof.
p_eof_clr <= p_eof_d2 xor p_eof_d3;
end generate GEN_FOR_ASYNC;
-- Generate for when primary clock is synchronous
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
---------------------------------------------------------------------------
-- Generate Packet EOF and SOF
---------------------------------------------------------------------------
-- Register stream control in to isolate wrt clock
-- for timing closure
REG_STRM_IN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_valid <= '0';
s_last <= '0';
s_ready <= '0';
else
s_valid <= axis_tvalid;
s_last <= axis_tlast ;
s_ready <= axis_tready;
end if;
end if;
end process REG_STRM_IN;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_valid_d1 <= '0';
s_last_d1 <= '0';
else
s_valid_d1 <= s_valid and s_ready;
s_last_d1 <= s_last and s_valid and s_ready;
end if;
end if;
end process REG_FOR_RE;
-- CR565366 investigating delay interurpt issue discovered
-- this coding issue.
-- s_valid_re <= s_ready and s_valid and not s_last_d1;
s_valid_re <= s_ready and s_valid and not s_valid_d1;
s_last_re <= s_ready and s_valid and s_last and not s_last_d1;
-- Sample and hold valid re to create sof
SOF_SMPL_N_HOLD : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(p_reset_n = '0' or s_eof_re = '1')then
s_sof_generated <= '0';
-- new
elsif((s_valid_re = '1')
or (sof_generated_fe = '1' and s_ready = '1' and s_valid = '1'))then
s_sof_generated <= '1';
end if;
end if;
end process SOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
SOF_REG2SCNDRY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_sof_d1_cdc_tig <= '0';
else
s_sof_d1_cdc_tig <= s_sof_generated;
end if;
end if;
end process SOF_REG2SCNDRY;
-- generate falling edge pulse on end of packet for use if
-- need to generate an immediate sof.
sof_generated_fe <= not s_sof_generated and s_sof_d1_cdc_tig;
-- generate SOF on rising edge of valid if not already in a packet OR...
s_sof_re <= '1' when (s_valid_re = '1' and s_sof_generated = '0')
or (sof_generated_fe = '1' -- If end of previous packet
and s_ready = '1' -- and ready asserted
and s_valid = '1') -- and valid asserted
else '0';
-- generate eof on rising edge of valid last assertion OR...
s_eof_re <= '1' when (s_last_re = '1')
or (sof_generated_fe = '1' -- If end of previous packet
and s_ready = '1' -- and ready asserted
and s_valid = '1' -- and valid asserted
and s_last = '1') -- and last asserted
else '0';
end generate GEN_FOR_SYNC;
end implementation;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:20:40 10/16/2014
-- Design Name:
-- Module Name: D:/Documents/Xilinx Projects/multi_cycle_cpu/MIPS_ALU_tb.vhd
-- Project Name: multi_cycle_cpu
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: alu
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MIPS_ALU_tb IS
END MIPS_ALU_tb;
ARCHITECTURE behavior OF MIPS_ALU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu
PORT(
alu_ctrl : IN std_logic_vector(3 downto 0);
alu_src1 : IN std_logic_vector(31 downto 0);
alu_src2 : IN std_logic_vector(31 downto 0);
alu_zero : OUT std_logic;
alu_result : OUT std_logic_vector(31 downto 0);
alu_carry : OUT std_logic
);
END COMPONENT;
signal clock : std_logic;
--Inputs
signal alu_ctrl : std_logic_vector(3 downto 0) := (others => '0');
signal alu_src1 : std_logic_vector(31 downto 0) := (others => '0');
signal alu_src2 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal alu_zero : std_logic;
signal alu_result : std_logic_vector(31 downto 0);
signal alu_carry : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu PORT MAP (
alu_ctrl => alu_ctrl,
alu_src1 => alu_src1,
alu_src2 => alu_src2,
alu_zero => alu_zero,
alu_result => alu_result,
alu_carry => alu_carry
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clock_period*10;
-- insert stimulus here
--test add
alu_src1 <= X"f0f0f0f0";
alu_src2 <= X"0f0f0f0f";
alu_ctrl <= "0000";
wait for 10 ns;
assert alu_result = X"00000000" report "and failed" severity error;
-- test or
wait for 10 ns;
alu_src1 <= X"f0f0f0f0";
alu_src2 <= X"0f0f0f0f";
alu_ctrl <= "0001";
wait for 10 ns;
assert alu_result = X"ffffffff" report "or failed" severity error;
-- test add
wait for 10 ns;
alu_src1 <= std_logic_vector(to_signed(1234567,32));
alu_src2 <= std_logic_vector(to_signed(7654321,32));
alu_ctrl <= "0010";
wait for 10 ns;
assert alu_result = std_logic_vector(to_signed(8888888,32)) report "add failed" severity error;
-- test sub
wait for 10 ns;
alu_src1 <= std_logic_vector(to_signed(7777777,32));
alu_src2 <= std_logic_vector(to_signed(4444444,32));
alu_ctrl <= "0110";
wait for 10 ns;
assert alu_result = std_logic_vector(to_signed(3333333,32)) report "sub failed" severity error;
-- test sub2
wait for 10 ns;
alu_src1 <= std_logic_vector(to_signed(4444444,32));
alu_src2 <= std_logic_vector(to_signed(7777777,32));
alu_ctrl <= "0110";
wait for 10 ns;
assert alu_result = std_logic_vector(to_signed(-3333333,32)) report "sub2 failed" severity error;
-- test slt
wait for 10 ns;
alu_src1 <= std_logic_vector(to_signed(4444444,32));
alu_src2 <= std_logic_vector(to_signed(7777777,32));
alu_ctrl <= "0111";
wait for 10 ns;
assert alu_result = x"00000001" report "slt failed" severity error;
-- test nor
wait for 10 ns;
alu_src1 <= X"00000000";
alu_src2 <= X"00000000";
alu_ctrl <= "1100";
wait for 10 ns;
assert alu_result = x"ffffffff" report "nor failed" severity error;
wait;
end process;
END;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.net.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package ethernet_mac is
type eth_tx_in_type is record
start : std_ulogic;
valid : std_ulogic;
data : std_logic_vector(31 downto 0);
full_duplex : std_ulogic;
length : std_logic_vector(10 downto 0);
col : std_ulogic;
crs : std_ulogic;
read_ack : std_ulogic;
end record;
type eth_tx_out_type is record
status : std_logic_vector(1 downto 0);
done : std_ulogic;
restart : std_ulogic;
read : std_ulogic;
tx_er : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
end record;
type eth_rx_in_type is record
writeok : std_ulogic;
rxen : std_ulogic;
rx_dv : std_ulogic;
rx_er : std_ulogic;
rxd : std_logic_vector(3 downto 0);
done_ack : std_ulogic;
write_ack : std_ulogic;
end record;
type eth_rx_out_type is record
write : std_ulogic;
data : std_logic_vector(31 downto 0);
done : std_ulogic;
length : std_logic_vector(10 downto 0);
status : std_logic_vector(2 downto 0);
start : std_ulogic;
end record;
type eth_mdio_in_type is record
mdioi : std_ulogic;
write : std_ulogic;
read : std_ulogic;
mdiostart : std_ulogic;
regadr : std_logic_vector(4 downto 0);
phyadr : std_logic_vector(4 downto 0);
data : std_logic_vector(15 downto 0);
end record;
type eth_mdio_out_type is record
mdc : std_ulogic;
mdioo : std_ulogic;
mdioen : std_ulogic;
data : std_logic_vector(15 downto 0);
done : std_ulogic;
error : std_ulogic;
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
component eth_ahb_mst is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
end package;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_demo_tb
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library STD;
use std.env.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library bitvis_vip_sbi;
use bitvis_vip_sbi.sbi_bfm_pkg.all;
use work.irqc_pif_pkg.all;
-- Test case entity
entity irqc_demo_tb is
end entity;
-- Test case architecture
architecture func of irqc_demo_tb is
-- DSP interface and general control signals
signal clk : std_logic := '0';
signal arst : std_logic := '0';
-- CPU interface
signal sbi_if : t_sbi_if(addr(2 downto 0), wdata(7 downto 0), rdata(7 downto 0)) := init_sbi_if_signals(3, 8);
-- Interrupt related signals
signal irq_source : std_logic_vector(C_NUM_SOURCES-1 downto 0) := (others => '0');
signal irq2cpu : std_logic := '0';
signal irq2cpu_ack : std_logic := '0';
signal clock_ena : boolean := false;
constant C_CLK_PERIOD : time := 10 ns;
subtype t_irq_source is std_logic_vector(C_NUM_SOURCES-1 downto 0);
-- Trim (cut) a given vector to fit the number of irq sources (i.e. pot. reduce width)
function trim(
constant source : std_logic_vector;
constant num_bits : positive := C_NUM_SOURCES)
return t_irq_source is
variable v_result : std_logic_vector(source'length-1 downto 0) := source;
begin
return v_result(num_bits-1 downto 0);
end;
-- Fit a given vector to the number of irq sources by masking with zeros above irq width
function fit(
constant source : std_logic_vector;
constant num_bits : positive := C_NUM_SOURCES)
return std_logic_vector is
variable v_result : std_logic_vector(source'length-1 downto 0) := (others => '0');
variable v_source : std_logic_vector(source'length-1 downto 0) := source;
begin
v_result(num_bits-1 downto 0) := v_source(num_bits-1 downto 0);
return v_result;
end;
begin
-----------------------------------------------------------------------------
-- Instantiate DUT
-----------------------------------------------------------------------------
i_irqc: entity work.irqc
port map (
-- DSP interface and general control signals
clk => clk,
arst => arst,
-- CPU interface
cs => sbi_if.cs,
addr => sbi_if.addr,
wr => sbi_if.wena,
rd => sbi_if.rena,
din => sbi_if.wdata,
dout => sbi_if.rdata,
-- Interrupt related signals
irq_source => irq_source,
irq2cpu => irq2cpu,
irq2cpu_ack => irq2cpu_ack
);
sbi_if.ready <= '1'; -- always ready in the same clock cycle.
-----------------------------------------------------------------------------
-- Clock Generator
-----------------------------------------------------------------------------
clock_generator(clk, clock_ena, C_CLK_PERIOD, "IRQC TB clock");
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
-- Overloads for PIF BFMs for SBI (Simple Bus Interface)
procedure write(
constant addr_value : in natural;
constant data_value : in std_logic_vector;
constant msg : in string) is
begin
sbi_write(to_unsigned(addr_value, sbi_if.addr'length), data_value, msg,
clk, sbi_if, C_SCOPE);
end;
procedure check(
constant addr_value : in natural;
constant data_exp : in std_logic_vector;
constant alert_level : in t_alert_level;
constant msg : in string) is
begin
sbi_check(to_unsigned(addr_value, sbi_if.addr'length), data_exp, msg,
clk, sbi_if, alert_level, C_SCOPE);
end;
procedure set_inputs_passive(
dummy : t_void) is
begin
sbi_if.cs <= '0';
sbi_if.addr <= (others => '0');
sbi_if.wena <= '0';
sbi_if.rena <= '0';
sbi_if.wdata <= (others => '0');
irq_source <= (others => '0');
irq2cpu_ack <= '0';
log(ID_SEQUENCER_SUB, "All inputs set passive", C_SCOPE);
end;
variable v_time_stamp : time := 0 ns;
variable v_irq_mask : std_logic_vector(7 downto 0);
variable v_irq_mask_inv : std_logic_vector(7 downto 0);
begin
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
enable_log_msg(ALL_MESSAGES);
--disable_log_msg(ALL_MESSAGES);
--enable_log_msg(ID_LOG_HDR);
log(ID_LOG_HDR, "Start Simulation of TB for IRQC", C_SCOPE);
------------------------------------------------------------
set_inputs_passive(VOID);
clock_ena <= true; -- to start clock generator
gen_pulse(arst, 10 * C_CLK_PERIOD, "Pulsed reset-signal - active for 10T");
v_time_stamp := now; -- time from which irq2cpu should be stable off until triggered
check_value(C_NUM_SOURCES > 0, FAILURE, "Must be at least 1 interrupt source", C_SCOPE);
check_value(C_NUM_SOURCES <= 8, TB_WARNING, "This TB is only checking IRQC with up to 8 interrupt sources", C_SCOPE);
log(ID_LOG_HDR, "Check defaults on output ports", C_SCOPE);
------------------------------------------------------------
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must be default inactive", C_SCOPE);
check_value(sbi_if.rdata, x"00", ERROR, "Register data bus output must be default passive");
log(ID_LOG_HDR, "Check register defaults and access (write + read)", C_SCOPE);
------------------------------------------------------------
log("\nChecking Register defaults");
check(C_ADDR_IRR, x"00", ERROR, "IRR default");
check(C_ADDR_IER, x"00", ERROR, "IER default");
check(C_ADDR_IPR, x"00", ERROR, "IPR default");
check(C_ADDR_IRQ2CPU_ALLOWED, x"00", ERROR, "IRQ2CPU_ALLOWED default");
log("\nChecking Register Write/Read");
write(C_ADDR_IER, fit(x"55"), "IER");
check(C_ADDR_IER, fit(x"55"), ERROR, "IER pure readback");
write(C_ADDR_IER, fit(x"AA"), "IER");
check(C_ADDR_IER, fit(x"AA"), ERROR, "IER pure readback");
write(C_ADDR_IER, fit(x"00"), "IER");
check(C_ADDR_IER, fit(x"00"), ERROR, "IER pure readback");
log(ID_LOG_HDR, "Check register trigger/clear mechanism", C_SCOPE);
------------------------------------------------------------
write(C_ADDR_ITR, fit(x"AA"), "ITR : Set interrupts");
check(C_ADDR_IRR, fit(x"AA"), ERROR, "IRR");
write(C_ADDR_ITR, fit(x"55"), "ITR : Set more interrupts");
check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR");
write(C_ADDR_ICR, fit(x"71"), "ICR : Clear interrupts");
check(C_ADDR_IRR, fit(x"8E"), ERROR, "IRR");
write(C_ADDR_ICR, fit(x"85"), "ICR : Clear interrupts");
check(C_ADDR_IRR, fit(x"0A"), ERROR, "IRR");
write(C_ADDR_ITR, fit(x"55"), "ITR : Set more interrupts");
check(C_ADDR_IRR, fit(x"5F"), ERROR, "IRR");
write(C_ADDR_ICR, fit(x"5F"), "ICR : Clear interrupts");
check(C_ADDR_IRR, fit(x"00"), ERROR, "IRR");
log(ID_LOG_HDR, "Check interrupt sources, IER, IPR and irq2cpu", C_SCOPE);
------------------------------------------------------------
log("\nChecking interrupts and IRR");
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
gen_pulse(irq_source, trim(x"AA"), clk, 1, "Pulse irq_source 1T");
check(C_ADDR_IRR, fit(x"AA"), ERROR, "IRR after irq pulses");
gen_pulse(irq_source, trim(x"01"), clk, 1, "Add more interrupts");
check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR after irq pulses");
gen_pulse(irq_source, trim(x"A1"), clk, 1, "Repeat same interrupts");
check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR after irq pulses");
gen_pulse(irq_source, trim(x"54"), clk, 1, "Add remaining interrupts");
check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR after irq pulses");
write(C_ADDR_ICR, fit(x"AA"), "ICR : Clear half the interrupts");
gen_pulse(irq_source, trim(x"A0"), clk, 1, "Add more interrupts");
check(C_ADDR_IRR, fit(x"F5"), ERROR, "IRR after irq pulses");
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
check(C_ADDR_IRR, fit(x"00"), ERROR, "IRR after clearing all");
log("\nChecking IER, IPR and irq2cpu");
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
write(C_ADDR_IER, fit(x"55"), "IER : Enable some interrupts");
write(C_ADDR_ITR, fit(x"AA"), "ITR : Trigger non-enable interrupts");
check(C_ADDR_IPR, fit(x"00"), ERROR, "IPR should not be active");
check(C_ADDR_IRQ2CPU_ALLOWED, x"00", ERROR, "IRQ2CPU_ALLOWED should not be active");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Enable main interrupt to CPU");
check(C_ADDR_IRQ2CPU_ALLOWED, x"01", ERROR, "IRQ2CPU_ALLOWED should now be active");
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must still be inactive", C_SCOPE);
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu", C_SCOPE);
gen_pulse(irq_source, trim(x"01"), clk, 1, "Add a single enabled interrupt");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt expected immediately", C_SCOPE);
v_time_stamp := now; -- from time of stable active irq2cpu
check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR should now be active");
check(C_ADDR_IPR, fit(x"01"), ERROR, "IPR should now be active");
log("\nMore details checked in the autonomy section below");
check_value(irq2cpu, '1', ERROR, "Interrupt to CPU must still be active", C_SCOPE);
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu", C_SCOPE);
log(ID_LOG_HDR, "Check autonomy for all interrupts", C_SCOPE);
------------------------------------------------------------
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
write(C_ADDR_IER, fit(x"FF"), "IER : Disable all interrupts");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU");
for i in 0 to C_NUM_SOURCES-1 loop
log(" ");
log("- Checking irq_source(" & to_string(i) & ") and all corresponding functionality");
log("- - Check interrupt activation not affected by non related interrupts or registers");
v_time_stamp := now; -- from time of stable inactive irq2cpu
v_irq_mask := (others => '0');
v_irq_mask(i) := '1';
v_irq_mask_inv := (others => '1');
v_irq_mask_inv(i) := '0';
write(C_ADDR_IER, v_irq_mask, "IER : Enable selected interrupt");
gen_pulse(irq_source, trim(v_irq_mask_inv), clk, 1, "Pulse all non-enabled interrupts");
write(C_ADDR_ITR, v_irq_mask_inv, "ITR : Trigger all non-enabled interrupts");
check(C_ADDR_IRR, fit(v_irq_mask_inv), ERROR, "IRR not yet triggered");
check(C_ADDR_IPR, x"00", ERROR, "IPR not yet triggered");
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must still be inactive", C_SCOPE);
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu", C_SCOPE);
gen_pulse(irq_source, trim(v_irq_mask), clk, 1, "Pulse the enabled interrupt");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt expected immediately", C_SCOPE);
check(C_ADDR_IRR, fit(x"FF"), ERROR, "All IRR triggered");
check(C_ADDR_IPR, v_irq_mask, ERROR, "IPR triggered for selected");
log("\n- - Check interrupt deactivation not affected by non related interrupts or registers");
v_time_stamp := now; -- from time of stable active irq2cpu
write(C_ADDR_ICR, v_irq_mask_inv, "ICR : Clear all non-enabled interrupts");
write(C_ADDR_IER, fit(x"FF"), "IER : Enable all interrupts");
write(C_ADDR_IER, v_irq_mask, "IER : Disable non-selected interrupts");
gen_pulse(irq_source, trim(x"FF"), clk, 1, "Pulse all interrupts");
write(C_ADDR_ITR, x"FF", "ITR : Trigger all interrupts");
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu (='1')", C_SCOPE);
write(C_ADDR_IER, v_irq_mask_inv, "IER : Enable all interrupts but disable selected");
check_value(irq2cpu, '1', ERROR, "Interrupt to CPU still active", C_SCOPE);
check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR still active for all");
write(C_ADDR_ICR, v_irq_mask_inv, "ICR : Clear all non-enabled interrupts");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation expected immediately", C_SCOPE);
write(C_ADDR_IER, v_irq_mask, "IER : Re-enable selected interrupt");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt reactivation expected immediately", C_SCOPE);
check(C_ADDR_IPR, v_irq_mask, ERROR, "IPR still active for selected");
write(C_ADDR_ICR, v_irq_mask, "ICR : Clear selected interrupt");
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must go inactive", C_SCOPE);
check(C_ADDR_IRR, x"00", ERROR, "IRR all inactive");
check(C_ADDR_IPR, x"00", ERROR, "IPR all inactive");
write(C_ADDR_IER, x"00", "IER : Disable all interrupts");
end loop;
report_alert_counters(INTERMEDIATE); -- Report intermediate counters
log(ID_LOG_HDR, "Check irq acknowledge and re-enable", C_SCOPE);
------------------------------------------------------------
log("- Activate interrupt");
write(C_ADDR_ITR, v_irq_mask, "ICR : Set single upper interrupt");
write(C_ADDR_IER, v_irq_mask, "IER : Enable single upper interrupts");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt activation expected", C_SCOPE);
v_time_stamp := now; -- from time of stable active irq2cpu
log("\n- Try potential malfunction");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU again - should not affect anything");
write(C_ADDR_IRQ2CPU_ENA, x"00", "IRQ2CPU_ENA : Set to 0 - should not affect anything");
write(C_ADDR_IRQ2CPU_DISABLE, x"00", "IRQ2CPU_DISABLE : Set to 0 - should not affect anything");
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu (='1')", C_SCOPE);
log("\n- Acknowledge and deactivate interrupt");
gen_pulse(irq2cpu_ack, clk, 1, "Pulse irq2cpu_ack");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation expected", C_SCOPE);
v_time_stamp := now; -- from time of stable inactive irq2cpu
log("\n- Test for potential malfunction");
write(C_ADDR_IRQ2CPU_DISABLE, x"01", "IRQ2CPU_DISABLE : Disable interrupt to CPU again - should not affect anything");
write(C_ADDR_IRQ2CPU_DISABLE, x"00", "IRQ2CPU_DISABLE : Set to 0 - should not affect anything");
write(C_ADDR_IRQ2CPU_ENA, x"00", "IRQ2CPU_ENA : Set to 0 - should not affect anything");
write(C_ADDR_ITR, x"FF", "ICR : Trigger all interrupts");
write(C_ADDR_IER, x"FF", "IER : Enable all interrupts");
gen_pulse(irq_source, trim(x"FF"), clk, 1, "Pulse all interrupts");
gen_pulse(irq2cpu_ack, clk, 1, "Pulse irq2cpu_ack");
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu (='0')", C_SCOPE);
log("\n- Re-/de-activation");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Reactivate interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt reactivation expected", C_SCOPE);
write(C_ADDR_IRQ2CPU_DISABLE, x"01", "IRQ2CPU_DISABLE : Deactivate interrupt to CPU");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation expected", C_SCOPE);
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Reactivate interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt reactivation expected", C_SCOPE);
log(ID_LOG_HDR, "Check Reset", C_SCOPE);
------------------------------------------------------------
log("- Activate all interrupts");
write(C_ADDR_ITR, x"FF", "ICR : Set all interrupts");
write(C_ADDR_IER, x"FF", "IER : Enable all interrupts");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt activation expected", C_SCOPE);
gen_pulse(arst, clk, 1, "Pulse reset");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation", C_SCOPE);
check(C_ADDR_IER, x"00", ERROR, "IER all inactive");
check(C_ADDR_IRR, x"00", ERROR, "IRR all inactive");
check(C_ADDR_IPR, x"00", ERROR, "IPR all inactive");
--==================================================================================================
-- Ending the simulation
--------------------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- Finish the simulation
std.env.stop;
wait; -- to stop completely
end process p_main;
end func;
|
----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_ambilight IS
END test_ambilight;
ARCHITECTURE behavior OF test_ambilight IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ambilight
PORT(
vidclk : IN std_logic;
viddata_r : IN std_logic_vector(7 downto 0);
viddata_g : IN std_logic_vector(7 downto 0);
viddata_b : IN std_logic_vector(7 downto 0);
hblank : IN std_logic;
vblank : IN std_logic;
cfgclk : IN std_logic;
cfgwe : IN std_logic;
cfgaddr : IN std_logic_vector(13 downto 0);
cfgdatain : IN std_logic_vector(7 downto 0);
cfgdataout : OUT std_logic_vector(7 downto 0);
output : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal vidclk : std_logic := '0';
signal viddata_r : std_logic_vector(7 downto 0) := (others => '0');
signal viddata_g : std_logic_vector(7 downto 0) := (others => '0');
signal viddata_b : std_logic_vector(7 downto 0) := (others => '0');
signal hblank : std_logic := '0';
signal vblank : std_logic := '0';
signal cfgclk : std_logic := '0';
signal cfgwe : std_logic := '0';
signal cfgaddr : std_logic_vector(13 downto 0) := (others => '0');
signal cfgdatain : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal cfgdataout : std_logic_vector(7 downto 0);
signal output : std_logic_vector(7 downto 0);
-- Clock period definitions
constant vidclk_period : time := 10 ns;
constant cfgclk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ambilight PORT MAP (
vidclk => vidclk,
viddata_r => viddata_r,
viddata_g => viddata_g,
viddata_b => viddata_b,
hblank => hblank,
vblank => vblank,
cfgclk => cfgclk,
cfgwe => cfgwe,
cfgaddr => cfgaddr,
cfgdatain => cfgdatain,
cfgdataout => cfgdataout,
output => output
);
-- Clock process definitions
vidclk_process :process
begin
vidclk <= '0';
wait for vidclk_period/2;
vidclk <= '1';
wait for vidclk_period/2;
end process;
cfgclk_process :process
begin
cfgclk <= '0';
wait for cfgclk_period/2;
cfgclk <= '1';
wait for cfgclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for vidclk_period*10;
cfgaddr <= "00000000000000";
wait for cfgclk_period*2;
cfgdatain <= x"00";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgaddr <= "00000000000001";
wait for cfgclk_period*2;
cfgdatain <= x"07";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgaddr <= "00000000000010";
wait for cfgclk_period*2;
cfgdatain <= x"00";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgaddr <= "00000000000011";
wait for cfgclk_period*2;
cfgdatain <= x"07";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgaddr <= "00000000000100";
wait for cfgclk_period*2;
cfgdatain <= x"06";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgwe <= '0';
wait for cfgclk_period;
for field in 0 to 10 loop
-- vblank = hBlank = 1
hblank <= '1';
vblank <= '1';
for y in 0 to 20 loop
for x in 0 to 820 loop
viddata_r <= x"00";
viddata_g <= x"00";
viddata_b <= x"00";
wait for vidclk_period;
end loop;
end loop;
for y in 0 to 288 loop
-- vBlank = hBlank = 0
hblank <= '0';
vblank <= '0';
-- line of video, 720 pixels in total
for x in 0 to 720 loop
viddata_r <= x"aa";
viddata_g <= x"00";
viddata_b <= x"00";
wait for vidclk_period;
end loop;
-- hBlank = 1
hblank <= '1';
-- blank data
for x in 0 to 100 loop
viddata_r <= x"00";
viddata_g <= x"00";
viddata_b <= x"00";
wait for vidclk_period;
end loop;
end loop;
end loop;
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:29:10 09/04/2016
-- Design Name:
-- Module Name: memory_interface - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity memory_interface is
generic (
ram_adr_width : natural;
ram_size : natural;
wbs_adr_high : natural := 27;
RamFileName : string := "meminit.ram";
mode : string := "B";
Swapbytes : boolean := true -- SWAP Bytes in RAM word in low byte first order to use data2mem
-- UseBRAMPrimitives : boolean := TRUE
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
wbs_cyc_i: in std_logic;
wbs_stb_i: in std_logic;
wbs_we_i: in std_logic;
wbs_sel_i: in std_logic_vector(3 downto 0);
wbs_ack_o: out std_logic;
wbs_adr_i: in std_logic_vector(wbs_adr_high downto 2);
wbs_dat_i: in std_logic_vector(31 downto 0);
wbs_dat_o: out std_logic_vector(31 downto 0);
lli_re_i: in std_logic;
lli_adr_i: in std_logic_vector(29 downto 0);
lli_dat_o: out std_logic_vector(31 downto 0);
lli_busy_o: out std_logic
);
end memory_interface;
architecture Behavioral of memory_interface is
constant slave_adr_high : natural := 29;
-- Slaves
-- RAM
signal instr_ram_adr,data_ram_adr : std_logic_vector(ram_adr_width-1 downto 0);
signal ram_a_we: std_logic_vector(3 downto 0);
signal ack_read, ack_write : std_logic;
begin
instr_ram_adr <= lli_adr_i(ram_adr_width-1 downto 0);
data_ram_adr <= wbs_adr_i(ram_adr_width+1 downto 2);
lli_busy_o <= '0';
-- Wishbone ACK
process (clk_i) is
begin
if rising_edge(clk_i) then
ack_read<=wbs_cyc_i and wbs_stb_i and not wbs_we_i;
end if;
end process;
ack_write<=wbs_cyc_i and wbs_stb_i and wbs_we_i;
wbs_ack_o<=ack_read or ack_write;
-- RAM WREN Signals
gen_ram_a_we: for i in 3 downto 0 generate
ram_a_we(i)<='1' when wbs_cyc_i='1' and wbs_stb_i='1' and wbs_we_i='1' and wbs_sel_i(i)='1'
else '0';
end generate;
-- genericMainMemory: if not UseBRAMPrimitives generate
ram: entity work.MainMemory
generic map (
ADDR_WIDTH =>ram_adr_width,
SIZE => ram_size,
RamFileName => RamFileName,
mode => mode,
Swapbytes => Swapbytes
)
PORT MAP(
DBOut =>wbs_dat_o,
DBIn => wbs_dat_i,
AdrBus => data_ram_adr,
ENA => wbs_cyc_i,
WREN => ram_a_we,
CLK => clk_i,
CLKB =>clk_i ,
ENB =>lli_re_i ,
AdrBusB =>instr_ram_adr,
DBOutB => lli_dat_o
);
--end generate;
-- spartanMainMemory: if UseBRAMPrimitives generate
-- mem: entity work.MainMemorySpartan6
-- generic map (
-- NUMBANKS => 2
-- )
--
-- PORT MAP(
-- DBOut =>wbs_dat_o,
-- DBIn => wbs_dat_i,
-- AdrBus => data_ram_adr,
-- ENA => wbs_cyc_i,
-- WREN => ram_a_we,
-- CLK => clk_i,
-- CLKB =>clk_i ,
-- ENB =>lli_re_i ,
-- AdrBusB =>instr_ram_adr,
-- DBOutB => lli_dat_o
-- );
--
-- end generate;
--
end Behavioral;
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: compute_distance_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity compute_distance_top is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type;
point_2 : in data_type;
distance : out coord_type_ext;
point_1_out : out data_type;
point_2_out : out data_type;
rdy : out std_logic
);
end compute_distance_top;
architecture Behavioral of compute_distance_top is
constant LAT_DOT_PRODUCT : integer := MUL_CORE_LATENCY+2*integer(ceil(log2(real(D))));
constant LAT_SUB : integer := 2;
constant LATENCY : integer := LAT_DOT_PRODUCT+LAT_SUB;
type data_delay_type is array(0 to LATENCY-1) of data_type;
component addorsub
generic (
USE_DSP : boolean := true;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component dot_product
generic (
SCALE_MUL_RESULT : integer := 0
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type;
point_2 : in data_type;
result : out coord_type_ext;
rdy : out std_logic
);
end component;
signal tmp_diff : data_type;
signal tmp_sub_rdy : std_logic;
signal tmp_dot_product_rdy : std_logic;
signal tmp_dot_product_result : coord_type_ext;
signal data_delay_1 : data_delay_type;
signal data_delay_2 : data_delay_type;
begin
G1: for I in 0 to D-1 generate
G_FIRST: if I = 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH,
B_BITWIDTH => COORD_BITWIDTH,
RES_BITWIDTH => COORD_BITWIDTH
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
sub => '1',
a => point_1(I),
b => point_2(I),
res => tmp_diff(I),
rdy => tmp_sub_rdy
);
end generate G_FIRST;
G_OTHER: if I > 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH,
B_BITWIDTH => COORD_BITWIDTH,
RES_BITWIDTH => COORD_BITWIDTH
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
sub => '1',
a => point_1(I),
b => point_2(I),
res => tmp_diff(I),
rdy => open
);
end generate G_OTHER;
end generate G1;
dot_product_inst : dot_product
generic map (
SCALE_MUL_RESULT => MUL_FRACTIONAL_BITS
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_sub_rdy,
point_1 => tmp_diff,
point_2 => tmp_diff,
result => tmp_dot_product_result,
rdy => tmp_dot_product_rdy
);
-- feed point_2 from input of this unit to output
data_delay_proc : process(clk)
begin
if rising_edge(clk) then
data_delay_1(0) <= point_1;
data_delay_1(1 to LATENCY-1) <= data_delay_1(0 to LATENCY-2);
data_delay_2(0) <= point_2;
data_delay_2(1 to LATENCY-1) <= data_delay_2(0 to LATENCY-2);
end if;
end process data_delay_proc;
rdy <= tmp_dot_product_rdy;
distance <= tmp_dot_product_result;
point_1_out <= data_delay_1(LATENCY-1);
point_2_out <= data_delay_2(LATENCY-1);
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity Blinking is
generic (
FREQ : positive:=25e6;
SECS : positive:=1
);
port (
clk_i : in std_logic;
led_o : out std_logic
);
end entity Blinking;
architecture RTL of Blinking is
constant DIV : positive:=FREQ*SECS-1;
signal led : std_logic;
begin
blink:
process (clk_i)
variable cnt: natural range 0 to DIV:=0;
begin
if rising_edge(clk_i) then
if cnt=DIV then
cnt:=0;
led <= not(led);
else
cnt:=cnt+1;
end if;
end if;
end process blink;
led_o <= led;
end architecture RTL;
|
-------------------------------------------------------------------------------
-- Title : Input Capture Counter
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package input_capture_pkg is
component input_capture is
port (
value_p : out std_logic_vector(15 downto 0);
step_p : in std_logic;
dir_p : in std_logic;
clk_en_p : in std_logic;
clk : in std_logic);
end component input_capture;
end package input_capture_pkg;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity input_capture is
port (
value_p : out std_logic_vector(15 downto 0);
step_p : in std_logic; -- Encoder Step
dir_p : in std_logic; -- Encoder Direction
clk_en_p : in std_logic; -- Clock enable
clk : in std_logic
);
end entity input_capture;
architecture behavioral of input_capture is
type input_capture_type is record
dir : std_logic;
value : std_logic_vector(15 downto 0);
invalid : std_logic;
cnt : unsigned(15 downto 0); -- Counter value
end record;
signal r, rin : input_capture_type := (
dir => '0',
value => (others => '1'),
invalid => '1',
cnt => (others => '0')
);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(clk_en_p, dir_p, r, r.cnt, step_p)
variable v : input_capture_type;
begin
v := r;
if clk_en_p = '1' then
v.cnt := r.cnt + 1;
end if;
-- Check for overflows
if r.cnt = (r.cnt'range => '1') then
v.value := std_logic_vector(r.cnt);
v.invalid := '1';
end if;
-- Next value will bigger, preadjust the output value
if std_logic_vector(r.cnt) >= r.value then
v.value := std_logic_vector(r.cnt);
end if;
if step_p = '1' then
if v.dir = dir_p and r.invalid = '0' then
-- Step is in the same direction as the one before
-- => correct measurement
v.value := std_logic_vector(r.cnt);
else
-- Step in the other direction => invalid value
v.value := (others => '1');
end if;
v.dir := dir_p;
v.cnt := (others => '0');
v.invalid := '0';
end if;
rin <= v;
end process comb_proc;
value_p <= r.value;
end architecture behavioral;
|
-------------------------------------------------------------------------------
-- Title : Input Capture Counter
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package input_capture_pkg is
component input_capture is
port (
value_p : out std_logic_vector(15 downto 0);
step_p : in std_logic;
dir_p : in std_logic;
clk_en_p : in std_logic;
clk : in std_logic);
end component input_capture;
end package input_capture_pkg;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity input_capture is
port (
value_p : out std_logic_vector(15 downto 0);
step_p : in std_logic; -- Encoder Step
dir_p : in std_logic; -- Encoder Direction
clk_en_p : in std_logic; -- Clock enable
clk : in std_logic
);
end entity input_capture;
architecture behavioral of input_capture is
type input_capture_type is record
dir : std_logic;
value : std_logic_vector(15 downto 0);
invalid : std_logic;
cnt : unsigned(15 downto 0); -- Counter value
end record;
signal r, rin : input_capture_type := (
dir => '0',
value => (others => '1'),
invalid => '1',
cnt => (others => '0')
);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(clk_en_p, dir_p, r, r.cnt, step_p)
variable v : input_capture_type;
begin
v := r;
if clk_en_p = '1' then
v.cnt := r.cnt + 1;
end if;
-- Check for overflows
if r.cnt = (r.cnt'range => '1') then
v.value := std_logic_vector(r.cnt);
v.invalid := '1';
end if;
-- Next value will bigger, preadjust the output value
if std_logic_vector(r.cnt) >= r.value then
v.value := std_logic_vector(r.cnt);
end if;
if step_p = '1' then
if v.dir = dir_p and r.invalid = '0' then
-- Step is in the same direction as the one before
-- => correct measurement
v.value := std_logic_vector(r.cnt);
else
-- Step in the other direction => invalid value
v.value := (others => '1');
end if;
v.dir := dir_p;
v.cnt := (others => '0');
v.invalid := '0';
end if;
rin <= v;
end process comb_proc;
value_p <= r.value;
end architecture behavioral;
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is
signal sig1 : std_logic;
constant con1 : std_logic := '0';
file file1 : std_logic;
alias alias1 is name;
begin
end block BLOCK_LABEL;
end architecture RTL;
|
----------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. --
----------------------------------------------------------------------
-- You must compile the wrapper file block_ram_2kx16.vhd when simulating
-- the core, block_ram_2kx16. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "Coregen Users Guide".
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Express, Exemplar and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;
ENTITY block_ram_2kx16 IS
port (
addr: IN std_logic_VECTOR(10 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
sinit: IN std_logic;
we: IN std_logic);
END block_ram_2kx16;
ARCHITECTURE block_ram_2kx16_a OF block_ram_2kx16 IS
component wrapped_block_ram_2kx16
port (
addr: IN std_logic_VECTOR(10 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
sinit: IN std_logic;
we: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_block_ram_2kx16 use entity XilinxCoreLib.blkmemsp_v3_1(behavioral)
generic map(
c_reg_inputs => 0,
c_addr_width => 11,
c_has_sinit => 1,
c_has_rdy => 0,
c_width => 16,
c_has_en => 0,
c_mem_init_file => "mif_file_16_1",
c_depth => 2047,
c_has_nd => 0,
c_has_default_data => 1,
c_default_data => "0",
c_limit_data_pitch => 8,
c_pipe_stages => 0,
c_has_rfd => 0,
c_has_we => 1,
c_sinit_value => "0",
c_has_limit_data_pitch => 0,
c_enable_rlocs => 0,
c_has_din => 1,
c_write_mode => 0);
BEGIN
U0 : wrapped_block_ram_2kx16
port map (
addr => addr,
clk => clk,
din => din,
dout => dout,
sinit => sinit,
we => we);
END block_ram_2kx16_a;
-- synopsys translate_on
|
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
END case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
END case;
end process PROC_2;
PROC_3 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
END case;
end process PROC_3;
end architecture ARCH;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Thu Jan 27 08:21:01 2005
-- cmd: h:/work/mix_new/mix/mix_0.pl -strip -nodelta ../open.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-conf-c.vhd,v 1.2 2005/01/27 07:29:26 wig Exp $
-- $Date: 2005/01/27 07:29:26 $
-- $Log: inst_a_e-rtl-conf-c.vhd,v $
-- Revision 1.2 2005/01/27 07:29:26 wig
-- reworked %OPEN% setup and testcase
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.48 2005/01/26 14:01:45 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_a_e_rtl_conf / inst_a_e
--
configuration inst_a_e_rtl_conf of inst_a_e is
for rtl
-- Generated Configuration
end for;
end inst_a_e_rtl_conf;
--
-- End of Generated Configuration inst_a_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
architecture RTL of FIFO is
begin
IF_LABEL : if a = '1' generate
signal signal1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
elsif b = '0' generate
signal sig1 : std_logic;
constant constant1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
else generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable vars1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
-- Violations below
IF_LABEL : if a = '1' generate
signal signal1: std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
elsif b = '0' generate
signal sig1 : std_logic;
constant constant1: std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
else generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable vars1: std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
end;
--- Test nested generates
architecture nested of fifo is
begin
g_0 : if true generate
g_1 : if true generate
signal sig0 : bit;
signal sig00 : bit;
begin end generate g_1;
end generate g_0;
end architecture fifo;
|
entity bounds30 is
end entity;
architecture test of bounds30 is
signal s : integer := -1;
begin
main: process is
begin
wait for 1 ns;
assert 2 ** s = 0; -- Error, negative exponent
wait;
end process;
end architecture;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := inferred;
constant CFG_MEMTECH : integer := inferred;
constant CFG_PADTECH : integer := inferred;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := inferred;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 2;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0;
constant CFG_MAC : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_DSU : integer := 0;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#00007A#;
constant CFG_ETH_ENL : integer := 16#CC0001#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := inferred;
constant CFG_MEMTECH : integer := inferred;
constant CFG_PADTECH : integer := inferred;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := inferred;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 2;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0;
constant CFG_MAC : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_DSU : integer := 0;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#00007A#;
constant CFG_ETH_ENL : integer := 16#CC0001#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END system_axi_gpio_0_0;
ARCHITECTURE system_axi_gpio_0_0_arch OF system_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_gpio_0_0_arch : ARCHITECTURE IS "system_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_gpio_0_0_arch: ARCHITECTURE IS "system_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=20,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 20,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_0_0_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc740.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p04n02i00740pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
end c01s01b01x01p04n02i00740pkg;
use work.c01s01b01x01p04n02i00740pkg.all;
ENTITY c01s01b01x01p04n02i00740ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen10 : string := "shishir";
Cgen11 : bit_vector := B"0011";
Cgen12 : boolean_vector := (true,false);
Cgen13 : severity_level_vector := (note,error);
Cgne14 : integer_vector := (1,2,3,4);
Cgen15 : real_vector := (1.0,2.0,3.0,4.0);
Cgen16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
Cgen17 : natural_vector := (1,2,3,4);
Cgen18 : positive_vector := (1,2,3,4));
END c01s01b01x01p04n02i00740ent;
ARCHITECTURE c01s01b01x01p04n02i00740arch OF c01s01b01x01p04n02i00740ent IS
BEGIN
TESTING: PROCESS
variable Vgen1 : boolean := true;
variable Vgen2 : bit := '1';
variable Vgen3 : character := 's';
variable Vgen4 : severity_level := note;
variable Vgen5 : integer := 3;
variable Vgen6 : real := 3.0;
variable Vgen7 : time := 3 ns;
variable Vgen8 : natural := 1;
variable Vgen9 : positive := 1;
variable Vgen10 : string (one to seven):= "shishir";
variable Vgen11 : bit_vector(zero to three) := B"0011";
variable Vgen12 : boolean_vector(zero to one) := (true,false);
variable Vgen13 : severity_level_vector(zero to one) := (note,error);
variable Vgen14 : integer_vector(zero to three) := (1,2,3,4);
variable Vgen15 : real_vector(zero to three) := (1.0,2.0,3.0,4.0);
variable Vgen16 : time_vector(zero to three) := (1 ns, 2 ns, 3 ns, 4 ns);
variable Vgen17 : natural_vector(zero to three) := (1,2,3,4);
variable Vgen18 : positive_vector(zero to three) := (1,2,3,4);
BEGIN
assert Vgen1 = C1 report "Initializing variable with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing variable with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing variable with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing variable with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing variable with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing variable with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing variable with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing variable with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing variable with generic Vgen9 does not work" severity error;
assert Vgen10 = C10 report "Initializing variable with generic Vgen10 does not work" severity error;
assert Vgen11 = C11 report "Initializing variable with generic Vgen11 does not work" severity error;
assert Vgen12 = C12 report "Initializing variable with generic Vgen12 does not work" severity error;
assert Vgen13 = C13 report "Initializing variable with generic Vgen13 does not work" severity error;
assert Vgen14 = C14 report "Initializing variable with generic Vgen14 does not work" severity error;
assert Vgen15 = C15 report "Initializing variable with generic Vgen15 does not work" severity error;
assert Vgen16 = C16 report "Initializing variable with generic Vgen16 does not work" severity error;
assert Vgen17 = C17 report "Initializing variable with generic Vgen17 does not work" severity error;
assert Vgen18 = C18 report "Initializing variable with generic Vgen18 does not work" severity error;
assert NOT(
Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***PASSED TEST: c01s01b01x01p04n02i00740"
severity NOTE;
assert (
Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***FAILED TEST: c01s01b01x01p04n02i00740 - Initializing variable with generic does not work."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p04n02i00740arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc740.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p04n02i00740pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
end c01s01b01x01p04n02i00740pkg;
use work.c01s01b01x01p04n02i00740pkg.all;
ENTITY c01s01b01x01p04n02i00740ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen10 : string := "shishir";
Cgen11 : bit_vector := B"0011";
Cgen12 : boolean_vector := (true,false);
Cgen13 : severity_level_vector := (note,error);
Cgne14 : integer_vector := (1,2,3,4);
Cgen15 : real_vector := (1.0,2.0,3.0,4.0);
Cgen16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
Cgen17 : natural_vector := (1,2,3,4);
Cgen18 : positive_vector := (1,2,3,4));
END c01s01b01x01p04n02i00740ent;
ARCHITECTURE c01s01b01x01p04n02i00740arch OF c01s01b01x01p04n02i00740ent IS
BEGIN
TESTING: PROCESS
variable Vgen1 : boolean := true;
variable Vgen2 : bit := '1';
variable Vgen3 : character := 's';
variable Vgen4 : severity_level := note;
variable Vgen5 : integer := 3;
variable Vgen6 : real := 3.0;
variable Vgen7 : time := 3 ns;
variable Vgen8 : natural := 1;
variable Vgen9 : positive := 1;
variable Vgen10 : string (one to seven):= "shishir";
variable Vgen11 : bit_vector(zero to three) := B"0011";
variable Vgen12 : boolean_vector(zero to one) := (true,false);
variable Vgen13 : severity_level_vector(zero to one) := (note,error);
variable Vgen14 : integer_vector(zero to three) := (1,2,3,4);
variable Vgen15 : real_vector(zero to three) := (1.0,2.0,3.0,4.0);
variable Vgen16 : time_vector(zero to three) := (1 ns, 2 ns, 3 ns, 4 ns);
variable Vgen17 : natural_vector(zero to three) := (1,2,3,4);
variable Vgen18 : positive_vector(zero to three) := (1,2,3,4);
BEGIN
assert Vgen1 = C1 report "Initializing variable with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing variable with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing variable with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing variable with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing variable with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing variable with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing variable with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing variable with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing variable with generic Vgen9 does not work" severity error;
assert Vgen10 = C10 report "Initializing variable with generic Vgen10 does not work" severity error;
assert Vgen11 = C11 report "Initializing variable with generic Vgen11 does not work" severity error;
assert Vgen12 = C12 report "Initializing variable with generic Vgen12 does not work" severity error;
assert Vgen13 = C13 report "Initializing variable with generic Vgen13 does not work" severity error;
assert Vgen14 = C14 report "Initializing variable with generic Vgen14 does not work" severity error;
assert Vgen15 = C15 report "Initializing variable with generic Vgen15 does not work" severity error;
assert Vgen16 = C16 report "Initializing variable with generic Vgen16 does not work" severity error;
assert Vgen17 = C17 report "Initializing variable with generic Vgen17 does not work" severity error;
assert Vgen18 = C18 report "Initializing variable with generic Vgen18 does not work" severity error;
assert NOT(
Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***PASSED TEST: c01s01b01x01p04n02i00740"
severity NOTE;
assert (
Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***FAILED TEST: c01s01b01x01p04n02i00740 - Initializing variable with generic does not work."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p04n02i00740arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc740.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p04n02i00740pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
end c01s01b01x01p04n02i00740pkg;
use work.c01s01b01x01p04n02i00740pkg.all;
ENTITY c01s01b01x01p04n02i00740ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen10 : string := "shishir";
Cgen11 : bit_vector := B"0011";
Cgen12 : boolean_vector := (true,false);
Cgen13 : severity_level_vector := (note,error);
Cgne14 : integer_vector := (1,2,3,4);
Cgen15 : real_vector := (1.0,2.0,3.0,4.0);
Cgen16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
Cgen17 : natural_vector := (1,2,3,4);
Cgen18 : positive_vector := (1,2,3,4));
END c01s01b01x01p04n02i00740ent;
ARCHITECTURE c01s01b01x01p04n02i00740arch OF c01s01b01x01p04n02i00740ent IS
BEGIN
TESTING: PROCESS
variable Vgen1 : boolean := true;
variable Vgen2 : bit := '1';
variable Vgen3 : character := 's';
variable Vgen4 : severity_level := note;
variable Vgen5 : integer := 3;
variable Vgen6 : real := 3.0;
variable Vgen7 : time := 3 ns;
variable Vgen8 : natural := 1;
variable Vgen9 : positive := 1;
variable Vgen10 : string (one to seven):= "shishir";
variable Vgen11 : bit_vector(zero to three) := B"0011";
variable Vgen12 : boolean_vector(zero to one) := (true,false);
variable Vgen13 : severity_level_vector(zero to one) := (note,error);
variable Vgen14 : integer_vector(zero to three) := (1,2,3,4);
variable Vgen15 : real_vector(zero to three) := (1.0,2.0,3.0,4.0);
variable Vgen16 : time_vector(zero to three) := (1 ns, 2 ns, 3 ns, 4 ns);
variable Vgen17 : natural_vector(zero to three) := (1,2,3,4);
variable Vgen18 : positive_vector(zero to three) := (1,2,3,4);
BEGIN
assert Vgen1 = C1 report "Initializing variable with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing variable with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing variable with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing variable with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing variable with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing variable with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing variable with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing variable with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing variable with generic Vgen9 does not work" severity error;
assert Vgen10 = C10 report "Initializing variable with generic Vgen10 does not work" severity error;
assert Vgen11 = C11 report "Initializing variable with generic Vgen11 does not work" severity error;
assert Vgen12 = C12 report "Initializing variable with generic Vgen12 does not work" severity error;
assert Vgen13 = C13 report "Initializing variable with generic Vgen13 does not work" severity error;
assert Vgen14 = C14 report "Initializing variable with generic Vgen14 does not work" severity error;
assert Vgen15 = C15 report "Initializing variable with generic Vgen15 does not work" severity error;
assert Vgen16 = C16 report "Initializing variable with generic Vgen16 does not work" severity error;
assert Vgen17 = C17 report "Initializing variable with generic Vgen17 does not work" severity error;
assert Vgen18 = C18 report "Initializing variable with generic Vgen18 does not work" severity error;
assert NOT(
Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***PASSED TEST: c01s01b01x01p04n02i00740"
severity NOTE;
assert (
Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***FAILED TEST: c01s01b01x01p04n02i00740 - Initializing variable with generic does not work."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p04n02i00740arch;
|
entity crash is end;
architecture behav of crash is
constant data_width : natural := 8;
type data_type is record
data: bit_vector(data_width-1 downto 0);
enable: bit;
end record data_type;
type port_type is array(0 to 15) of data_type;
signal s : port_type;
begin
s(s'range).enable <= '0';
end behav;
|
entity crash is end;
architecture behav of crash is
constant data_width : natural := 8;
type data_type is record
data: bit_vector(data_width-1 downto 0);
enable: bit;
end record data_type;
type port_type is array(0 to 15) of data_type;
signal s : port_type;
begin
s(s'range).enable <= '0';
end behav;
|
entity crash is end;
architecture behav of crash is
constant data_width : natural := 8;
type data_type is record
data: bit_vector(data_width-1 downto 0);
enable: bit;
end record data_type;
type port_type is array(0 to 15) of data_type;
signal s : port_type;
begin
s(s'range).enable <= '0';
end behav;
|
--------------------------------------------------------------------------------
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/01/2012 Scott Larson
-- Initial Public Release
-- Version 2.0 06/20/2014 Scott Larson
-- Added ability to interface with different slaves in the same transaction
-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
-- Corrected timing of when ack_error signal clears
-- Version 2.1 10/21/2014 Scott Larson
-- Replaced gated clock with clock enable
-- Adjusted timing of SCL during start and stop conditions
-- Version 2.2 02/05/2015 Scott Larson
-- Corrected small SDA glitch introduced in version 2.1
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY i2c_master IS
GENERIC(
input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC); --serial clock output of i2c bus
END i2c_master;
ARCHITECTURE logic OF i2c_master IS
CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --data clock for sda
SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
BEGIN
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch <= '0';
count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
data_clk_prev <= data_clk; --store previous value of data clock
IF(count = divider*4-1) THEN --end of timing cycle
count := 0; --reset timer
ELSIF(stretch = '0') THEN --clock stretching from slave not detected
count := count + 1; --continue clock generation timing
END IF;
CASE count IS
WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '0';
WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '1';
WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
scl_clk <= '1'; --release scl
IF(scl = '0') THEN --detect if slave is stretching clock
stretch <= '1';
ELSE
stretch <= '0';
END IF;
data_clk <= '1';
WHEN OTHERS => --last 1/4 cycle of clocking
scl_clk <= '1';
data_clk <= '0';
END CASE;
END IF;
END PROCESS;
--state machine and writing to sda during scl low (data_clk rising edge)
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
ack_error <= '0'; --clear acknowledge error flag
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
ELSIF(clk'EVENT AND clk = '1') THEN
IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
CASE state IS
WHEN ready => --idle state
IF(ena = '1') THEN --transaction requested
busy <= '1'; --flag busy
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
state <= start; --go to start bit
ELSE --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
END IF;
WHEN start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
state <= command; --go to command
WHEN command => --address and command byte of transaction
IF(bit_cnt = 0) THEN --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
ELSE --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
state <= command; --continue with command
END IF;
WHEN slv_ack1 => --slave acknowledge bit (command)
IF(addr_rw(0) = '0') THEN --write command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
END IF;
WHEN wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack2; --go to slave acknowledge (write)
ELSE --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
state <= wr; --continue writing
END IF;
WHEN rd => --read byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --read byte receive finished
IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
sda_int <= '0'; --acknowledge the byte has been received
ELSE --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
END IF;
bit_cnt <= 7; --reset bit counter for "byte" states
data_rd <= data_rx; --output received data
state <= mstr_ack; --go to master acknowledge
ELSE --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
END IF;
WHEN slv_ack2 => --slave acknowledge bit (write)
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another write
sda_int <= data_wr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --continue transaction with a read or new slave
state <= start; --go to repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN mstr_ack => --master acknowledge bit after a read
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted and data received is available on bus
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another read
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
ELSE --continue transaction with a write or new slave
state <= start; --repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN stop => --stop bit of transaction
busy <= '0'; --unflag busy
state <= ready; --go to idle state
END CASE;
ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
CASE state IS
WHEN start =>
IF(scl_ena = '0') THEN --starting new transaction
scl_ena <= '1'; --enable scl output
ack_error <= '0'; --reset acknowledge error output
END IF;
WHEN slv_ack1 => --receiving slave acknowledge (command)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
WHEN slv_ack2 => --receiving slave acknowledge (write)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN stop =>
scl_ena <= '0'; --disable scl
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS;
--set sda output
WITH state SELECT
sda_ena_n <= data_clk_prev WHEN start, --generate start condition
NOT data_clk_prev WHEN stop, --generate stop condition
sda_int WHEN OTHERS; --set to internal sda signal
--set scl and sda outputs
scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
END logic;
|
-- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
entity clkgen is
port (
pciclk : out bit;
nicclk : out bit;
ethclk : out bit
);
end clkgen;
architecture V1 of clkgen is
--------------- Line speed configuration ---------------
--constant ethclk_period : time := 0.1 us; --Ethernet
--constant ethclk_period : time := 0.01 us; -- Fast Ethernet
constant ethclk_period : time := 0.001 us; -- Gigabit Ethernet
--constant ethclk_period : time := 0.0001 us; -- 10 Gigabit Ethernet
--constant ethclk_period : time := 0.00001 us; -- 100 Gigabit Ethernet
--------------- I/O-bus speed configuration ---------------
--constant pciclk_period : time := 0.03030303 us; -- PCI 33
--constant pciclk_period : time := 0.015151515 us; -- PCI-X 66
constant pciclk_period : time := 0.007518797 us; -- PCI-X 133
--constant pciclk_period : time := 0.003759398 us; -- PCI-X 266
--constant pciclk_period : time := 0.001876173 us; -- PCI-X 533
--constant freq : integer := 33; -- PCI Clock in MHz
--constant clk_period : time := 1/freq; -- Clock Period in microseconds
--constant eth_freq : time := 10; -- Ethernet Clock in MHz
constant pcitpw : time := pciclk_period/2; --Pulse width (0 and 1) of the PCI Clock
constant nicclk_period : time := pciclk_period/100; -- NIC Clock Period (this clock 100 times faster than IO-bus clock)
constant nictpw : time := nicclk_period/2; -- Pulse width (0 and 1) of the Memory Clock
constant ethtpw : time := ethclk_period/2; -- Pulse width (0 and 1) of the Ethernet Clock
begin
pci_clock_generator: process
begin
pciclk <= '0', '1' after pcitpw;
wait for pciclk_period;
end process pci_clock_generator;
nic_clock_generator: process
begin
nicclk <= '1', '0' after nictpw;
wait for nicclk_period;
end process nic_clock_generator;
eth_clock_generator: process
begin
ethclk <= '1', '0' after ethtpw;
wait for ethclk_period;
end process eth_clock_generator;
end V1;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CAM_Array is
Generic (CAM_WIDTH : integer := 8 ;
CAM_DEPTH : integer := 4 ) ;
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we_decoded_row_address : in STD_LOGIC_VECTOR(CAM_DEPTH-1 downto 0) ;
search_word : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
dont_care_mask : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
decoded_match_address : out STD_LOGIC_VECTOR (CAM_DEPTH-1 downto 0));
end CAM_Array;
architecture Behavioral of CAM_Array is
component CAM_Row is
Generic (CAM_WIDTH : integer := 8) ;
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
search_word : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
dont_care_mask : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
row_match : out STD_LOGIC);
end component ;
begin
GEN_REG:
for i in 0 to (CAM_DEPTH-1) generate
cam_array : cam_row
generic map
(
CAM_WIDTH => CAM_WIDTH
)
port map
(
clk => clk,
rst => rst,
we => we_decoded_row_address(i),
search_word => search_word,
dont_care_mask => dont_care_mask,
row_match => decoded_match_address(i)
);
end generate GEN_REG;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
ENTITY addsub IS
generic (
width : integer
);
port (
A: IN std_logic_VECTOR(width-1 downto 0);
B: IN std_logic_VECTOR(width-1 downto 0);
C_IN: IN std_logic;
C_EN: IN std_logic;
C_OUT: OUT std_logic;
sub: IN std_logic;
S: OUT std_logic_VECTOR(width-1 downto 0)
);
END addsub;
ARCHITECTURE behavior OF addsub IS
component ADDC is
generic (
width : integer
);
port(
opa: in std_logic_vector(width-1 downto 0);
opb: in std_logic_vector(width-1 downto 0);
ci: in std_logic;
sum: out std_logic_vector(width-1 downto 0);
co: out std_logic
);
end component;
signal B_int : std_logic_vector( width-1 downto 0 ):=(others=>'0');
signal ci,co : std_logic:='0';
begin
B_int<=B when sub='0' else (not B);
ci<=(C_In and C_EN) xor sub;
C_out<=co xor sub;
ADDC_a : ADDC
generic map (
width => width )
port map (
opa => A,
opb => B_int,
Ci => ci,
co => co,
sum => S
);
end behavior;
|
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity naChans is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_number : in sfixed (18 downto -13);
param_voltage_erev : in sfixed (2 downto -22);
exposure_current_i : out sfixed (-28 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
param_conductance_na_conductance : in sfixed (-22 downto -53);
exposure_conductance_na_g : out sfixed (-22 downto -53);
derivedvariable_conductance_na_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_na_g_in : in sfixed (-22 downto -53);
param_none_na_m_instances : in sfixed (18 downto -13);
exposure_none_na_m_fcond : out sfixed (18 downto -13);
exposure_none_na_m_q : out sfixed (18 downto -13);
statevariable_none_na_m_q_out : out sfixed (18 downto -13);
statevariable_none_na_m_q_in : in sfixed (18 downto -13);
derivedvariable_none_na_m_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_na_m_fcond_in : in sfixed (18 downto -13);
param_per_time_na_m_forwardRatem1_rate : in sfixed (18 downto -2);
param_voltage_na_m_forwardRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_na_m_forwardRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_m_forwardRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_m_forwardRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_forwardRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_forwardRatem1_r_in : in sfixed (18 downto -2);
param_per_time_na_m_reverseRatem1_rate : in sfixed (18 downto -2);
param_voltage_na_m_reverseRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_na_m_reverseRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_m_reverseRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_m_reverseRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_reverseRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_reverseRatem1_r_in : in sfixed (18 downto -2);
param_none_na_h_instances : in sfixed (18 downto -13);
exposure_none_na_h_fcond : out sfixed (18 downto -13);
exposure_none_na_h_q : out sfixed (18 downto -13);
statevariable_none_na_h_q_out : out sfixed (18 downto -13);
statevariable_none_na_h_q_in : in sfixed (18 downto -13);
derivedvariable_none_na_h_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_na_h_fcond_in : in sfixed (18 downto -13);
param_per_time_na_h_forwardRateh1_rate : in sfixed (18 downto -2);
param_voltage_na_h_forwardRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_na_h_forwardRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_h_forwardRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_h_forwardRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_forwardRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_forwardRateh1_r_in : in sfixed (18 downto -2);
param_per_time_na_h_reverseRateh1_rate : in sfixed (18 downto -2);
param_voltage_na_h_reverseRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_na_h_reverseRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_h_reverseRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_h_reverseRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_reverseRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_reverseRateh1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end naChans;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of naChans is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_conductance_channelg : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_channelg_next : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_geff : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_geff_next : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_current_i : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_i_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component na
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_conductance_conductance : in sfixed (-22 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
derivedvariable_conductance_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_g_in : in sfixed (-22 downto -53);
param_none_m_instances : in sfixed (18 downto -13);
exposure_none_m_fcond : out sfixed (18 downto -13);
exposure_none_m_q : out sfixed (18 downto -13);
statevariable_none_m_q_out : out sfixed (18 downto -13);
statevariable_none_m_q_in : in sfixed (18 downto -13);
derivedvariable_none_m_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_m_fcond_in : in sfixed (18 downto -13);
param_per_time_m_forwardRatem1_rate : in sfixed (18 downto -2);
param_voltage_m_forwardRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_m_forwardRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_m_forwardRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_m_forwardRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_m_forwardRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_m_forwardRatem1_r_in : in sfixed (18 downto -2);
param_per_time_m_reverseRatem1_rate : in sfixed (18 downto -2);
param_voltage_m_reverseRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_m_reverseRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_m_reverseRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_m_reverseRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_m_reverseRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_m_reverseRatem1_r_in : in sfixed (18 downto -2);
param_none_h_instances : in sfixed (18 downto -13);
exposure_none_h_fcond : out sfixed (18 downto -13);
exposure_none_h_q : out sfixed (18 downto -13);
statevariable_none_h_q_out : out sfixed (18 downto -13);
statevariable_none_h_q_in : in sfixed (18 downto -13);
derivedvariable_none_h_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_h_fcond_in : in sfixed (18 downto -13);
param_per_time_h_forwardRateh1_rate : in sfixed (18 downto -2);
param_voltage_h_forwardRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_h_forwardRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_h_forwardRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_h_forwardRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_h_forwardRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_h_forwardRateh1_r_in : in sfixed (18 downto -2);
param_per_time_h_reverseRateh1_rate : in sfixed (18 downto -2);
param_voltage_h_reverseRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_h_reverseRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_h_reverseRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_h_reverseRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_h_reverseRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_h_reverseRateh1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal na_Component_done : STD_LOGIC ; signal Exposure_conductance_na_g_internal : sfixed (-22 downto -53);
signal Exposure_none_na_m_fcond_internal : sfixed (18 downto -13);
signal Exposure_none_na_m_q_internal : sfixed (18 downto -13);
signal Exposure_per_time_na_m_forwardRatem1_r_internal : sfixed (18 downto -2);
signal Exposure_per_time_na_m_reverseRatem1_r_internal : sfixed (18 downto -2);
signal Exposure_none_na_h_fcond_internal : sfixed (18 downto -13);
signal Exposure_none_na_h_q_internal : sfixed (18 downto -13);
signal Exposure_per_time_na_h_forwardRateh1_r_internal : sfixed (18 downto -2);
signal Exposure_per_time_na_h_reverseRateh1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
na_uut : na
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => na_Component_done,
param_conductance_conductance => param_conductance_na_conductance,
requirement_voltage_v => requirement_voltage_v,
Exposure_conductance_g => Exposure_conductance_na_g_internal,
derivedvariable_conductance_g_out => derivedvariable_conductance_na_g_out,
derivedvariable_conductance_g_in => derivedvariable_conductance_na_g_in,
param_none_m_instances => param_none_na_m_instances,
Exposure_none_m_fcond => Exposure_none_na_m_fcond_internal,
Exposure_none_m_q => Exposure_none_na_m_q_internal,
statevariable_none_m_q_out => statevariable_none_na_m_q_out,
statevariable_none_m_q_in => statevariable_none_na_m_q_in,
derivedvariable_none_m_fcond_out => derivedvariable_none_na_m_fcond_out,
derivedvariable_none_m_fcond_in => derivedvariable_none_na_m_fcond_in,
param_per_time_m_forwardRatem1_rate => param_per_time_na_m_forwardRatem1_rate,
param_voltage_m_forwardRatem1_midpoint => param_voltage_na_m_forwardRatem1_midpoint,
param_voltage_m_forwardRatem1_scale => param_voltage_na_m_forwardRatem1_scale,
param_voltage_inv_m_forwardRatem1_scale_inv => param_voltage_inv_na_m_forwardRatem1_scale_inv,
Exposure_per_time_m_forwardRatem1_r => Exposure_per_time_na_m_forwardRatem1_r_internal,
derivedvariable_per_time_m_forwardRatem1_r_out => derivedvariable_per_time_na_m_forwardRatem1_r_out,
derivedvariable_per_time_m_forwardRatem1_r_in => derivedvariable_per_time_na_m_forwardRatem1_r_in,
param_per_time_m_reverseRatem1_rate => param_per_time_na_m_reverseRatem1_rate,
param_voltage_m_reverseRatem1_midpoint => param_voltage_na_m_reverseRatem1_midpoint,
param_voltage_m_reverseRatem1_scale => param_voltage_na_m_reverseRatem1_scale,
param_voltage_inv_m_reverseRatem1_scale_inv => param_voltage_inv_na_m_reverseRatem1_scale_inv,
Exposure_per_time_m_reverseRatem1_r => Exposure_per_time_na_m_reverseRatem1_r_internal,
derivedvariable_per_time_m_reverseRatem1_r_out => derivedvariable_per_time_na_m_reverseRatem1_r_out,
derivedvariable_per_time_m_reverseRatem1_r_in => derivedvariable_per_time_na_m_reverseRatem1_r_in,
param_none_h_instances => param_none_na_h_instances,
Exposure_none_h_fcond => Exposure_none_na_h_fcond_internal,
Exposure_none_h_q => Exposure_none_na_h_q_internal,
statevariable_none_h_q_out => statevariable_none_na_h_q_out,
statevariable_none_h_q_in => statevariable_none_na_h_q_in,
derivedvariable_none_h_fcond_out => derivedvariable_none_na_h_fcond_out,
derivedvariable_none_h_fcond_in => derivedvariable_none_na_h_fcond_in,
param_per_time_h_forwardRateh1_rate => param_per_time_na_h_forwardRateh1_rate,
param_voltage_h_forwardRateh1_midpoint => param_voltage_na_h_forwardRateh1_midpoint,
param_voltage_h_forwardRateh1_scale => param_voltage_na_h_forwardRateh1_scale,
param_voltage_inv_h_forwardRateh1_scale_inv => param_voltage_inv_na_h_forwardRateh1_scale_inv,
Exposure_per_time_h_forwardRateh1_r => Exposure_per_time_na_h_forwardRateh1_r_internal,
derivedvariable_per_time_h_forwardRateh1_r_out => derivedvariable_per_time_na_h_forwardRateh1_r_out,
derivedvariable_per_time_h_forwardRateh1_r_in => derivedvariable_per_time_na_h_forwardRateh1_r_in,
param_per_time_h_reverseRateh1_rate => param_per_time_na_h_reverseRateh1_rate,
param_voltage_h_reverseRateh1_midpoint => param_voltage_na_h_reverseRateh1_midpoint,
param_voltage_h_reverseRateh1_scale => param_voltage_na_h_reverseRateh1_scale,
param_voltage_inv_h_reverseRateh1_scale_inv => param_voltage_inv_na_h_reverseRateh1_scale_inv,
Exposure_per_time_h_reverseRateh1_r => Exposure_per_time_na_h_reverseRateh1_r_internal,
derivedvariable_per_time_h_reverseRateh1_r_out => derivedvariable_per_time_na_h_reverseRateh1_r_out,
derivedvariable_per_time_h_reverseRateh1_r_in => derivedvariable_per_time_na_h_reverseRateh1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_conductance_na_g <= Exposure_conductance_na_g_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_conductance_na_g_internal, derivedvariable_conductance_channelg_next , param_none_number, requirement_voltage_v , derivedvariable_conductance_geff_next , param_voltage_erev )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_conductance_na_g_internal, derivedvariable_conductance_channelg_next , param_none_number, requirement_voltage_v , derivedvariable_conductance_geff_next , param_voltage_erev )
begin
derivedvariable_conductance_channelg_next <= resize(( exposure_conductance_na_g_internal ),-22,-53);
derivedvariable_conductance_geff_next <= resize(( derivedvariable_conductance_channelg_next * param_none_number ),-22,-53);
derivedvariable_current_i_next <= resize(( derivedvariable_conductance_geff_next * ( param_voltage_erev - requirement_voltage_v ) ),-28,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_conductance_channelg <= derivedvariable_conductance_channelg_next;
derivedvariable_conductance_geff <= derivedvariable_conductance_geff_next;
derivedvariable_current_i <= derivedvariable_current_i_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_current_i <= derivedvariable_current_i_in;derivedvariable_current_i_out <= derivedvariable_current_i;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(na_component_done,CLK)
begin
if (na_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
end RTL;
|
entity sub is
port (
x : in bit;
y : out bit );
end entity;
architecture test of sub is
begin
y <= x after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity jcore1 is
end entity;
architecture test of jcore1 is
type rec is record
a, b : bit;
end record;
signal s : rec;
begin
sub_i: entity work.sub
port map ( s.a, s.b );
end architecture;
|
entity sub is
port (
x : in bit;
y : out bit );
end entity;
architecture test of sub is
begin
y <= x after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity jcore1 is
end entity;
architecture test of jcore1 is
type rec is record
a, b : bit;
end record;
signal s : rec;
begin
sub_i: entity work.sub
port map ( s.a, s.b );
end architecture;
|
entity sub is
port (
x : in bit;
y : out bit );
end entity;
architecture test of sub is
begin
y <= x after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity jcore1 is
end entity;
architecture test of jcore1 is
type rec is record
a, b : bit;
end record;
signal s : rec;
begin
sub_i: entity work.sub
port map ( s.a, s.b );
end architecture;
|
-- PROM/SRAM controller
constant CFG_SRCTRLFT : integer := CONFIG_SRCTRLFT;
constant CFG_SRCTRLFT_APBEN : integer := CONFIG_SRCTRLFT_APBEN;
constant CFG_SRCTRLFT_PROMWS : integer := CONFIG_SRCTRLFT_PROMWS;
constant CFG_SRCTRLFT_RAMWS : integer := CONFIG_SRCTRLFT_RAMWS;
constant CFG_SRCTRLFT_IOWS : integer := CONFIG_SRCTRLFT_IOWS;
constant CFG_SRCTRLFT_RMW : integer := CONFIG_SRCTRLFT_RMW;
constant CFG_SRCTRLFT_EDAC : integer := CONFIG_SRCTRLFT_EDAC;
constant CFG_SRCTRLFT_NETLIST : integer := CONFIG_SRCTRLFT_NETLIST;
constant CFG_SRCTRLFT_8BIT : Integer := CONFIG_SRCTRLFT_8BIT;
constant CFG_SRCTRLFT_SRBANKS : Integer := CFG_SR_CTRLFT_SRBANKS;
constant CFG_SRCTRLFT_BANKSZ : Integer := CFG_SR_CTRLFT_BANKSZ;
constant CFG_SRCTRLFT_ROMBANKS : Integer := CFG_SR_CTRLFT_ROMBANKS;
constant CFG_SRCTRLFT_ROMBANKSZ : Integer := CFG_SR_CTRLFT_ROMBANKSZ;
constant CFG_SRCTRLFT_ROMBANKSZDEF : Integer := CFG_SR_CTRLFT_ROMBANKSZDEF;
|
library verilog;
use verilog.vl_types.all;
entity finalproject_mm_interconnect_0_cmd_mux_001 is
port(
sink0_valid : in vl_logic;
sink0_data : in vl_logic_vector(104 downto 0);
sink0_channel : in vl_logic_vector(5 downto 0);
sink0_startofpacket: in vl_logic;
sink0_endofpacket: in vl_logic;
sink0_ready : out vl_logic;
sink1_valid : in vl_logic;
sink1_data : in vl_logic_vector(104 downto 0);
sink1_channel : in vl_logic_vector(5 downto 0);
sink1_startofpacket: in vl_logic;
sink1_endofpacket: in vl_logic;
sink1_ready : out vl_logic;
src_valid : out vl_logic;
src_data : out vl_logic_vector(104 downto 0);
src_channel : out vl_logic_vector(5 downto 0);
src_startofpacket: out vl_logic;
src_endofpacket : out vl_logic;
src_ready : in vl_logic;
clk : in vl_logic;
reset : in vl_logic
);
end finalproject_mm_interconnect_0_cmd_mux_001;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------------------------------------------------
entity lut_3inadd is
generic(
NUM_BITS: positive := 131
);
port (
I: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
B: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
C: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
D: out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0)
);
end;
---------------------------------------------------------------------------------------------
architecture behave of lut_3inadd is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
constant a : std_logic_vector(NUM_BITS-1 downto 0):= "11110100001000110110000100110100111011010110101011000100001010001000100000110001111111100111111111110001100001001010111000010111000";
begin
D(0) <= I(0) xor B(0) xor C(0) xor a(0);
D(1) <= I(1) xor B(1) xor C(1) xor a(1);
D(2) <= I(2) xor B(2) xor C(2) xor a(2);
D(3) <= I(3) xor B(3) xor C(3) xor a(3);
D(4) <= I(4) xor B(4) xor C(4) xor a(4);
D(5) <= I(5) xor B(5) xor C(5) xor a(5);
D(6) <= I(6) xor B(6) xor C(6) xor a(6);
D(7) <= I(7) xor B(7) xor C(7) xor a(7);
D(8) <= I(8) xor B(8) xor C(8) xor a(8);
D(9) <= I(9) xor B(9) xor C(9) xor a(9);
D(10) <= I(10) xor B(10) xor C(10) xor a(10);
D(11) <= I(11) xor B(11) xor C(11) xor a(11);
D(12) <= I(12) xor B(12) xor C(12) xor a(12);
D(13) <= I(13) xor B(13) xor C(13) xor a(13);
D(14) <= I(14) xor B(14) xor C(14) xor a(14);
D(15) <= I(15) xor B(15) xor C(15) xor a(15);
D(16) <= I(16) xor B(16) xor C(16) xor a(16);
D(17) <= I(17) xor B(17) xor C(17) xor a(17);
D(18) <= I(18) xor B(18) xor C(18) xor a(18);
D(19) <= I(19) xor B(19) xor C(19) xor a(19);
D(20) <= I(20) xor B(20) xor C(20) xor a(20);
D(21) <= I(21) xor B(21) xor C(21) xor a(21);
D(22) <= I(22) xor B(22) xor C(22) xor a(22);
D(23) <= I(23) xor B(23) xor C(23) xor a(23);
D(24) <= I(24) xor B(24) xor C(24) xor a(24);
D(25) <= I(25) xor B(25) xor C(25) xor a(25);
D(26) <= I(26) xor B(26) xor C(26) xor a(26);
D(27) <= I(27) xor B(27) xor C(27) xor a(27);
D(28) <= I(28) xor B(28) xor C(28) xor a(28);
D(29) <= I(29) xor B(29) xor C(29) xor a(29);
D(30) <= I(30) xor B(30) xor C(30) xor a(30);
D(31) <= I(31) xor B(31) xor C(31) xor a(31);
D(32) <= I(32) xor B(32) xor C(32) xor a(32);
D(33) <= I(33) xor B(33) xor C(33) xor a(33);
D(34) <= I(34) xor B(34) xor C(34) xor a(34);
D(35) <= I(35) xor B(35) xor C(35) xor a(35);
D(36) <= I(36) xor B(36) xor C(36) xor a(36);
D(37) <= I(37) xor B(37) xor C(37) xor a(37);
D(38) <= I(38) xor B(38) xor C(38) xor a(38);
D(39) <= I(39) xor B(39) xor C(39) xor a(39);
D(40) <= I(40) xor B(40) xor C(40) xor a(40);
D(41) <= I(41) xor B(41) xor C(41) xor a(41);
D(42) <= I(42) xor B(42) xor C(42) xor a(42);
D(43) <= I(43) xor B(43) xor C(43) xor a(43);
D(44) <= I(44) xor B(44) xor C(44) xor a(44);
D(45) <= I(45) xor B(45) xor C(45) xor a(45);
D(46) <= I(46) xor B(46) xor C(46) xor a(46);
D(47) <= I(47) xor B(47) xor C(47) xor a(47);
D(48) <= I(48) xor B(48) xor C(48) xor a(48);
D(49) <= I(49) xor B(49) xor C(49) xor a(49);
D(50) <= I(50) xor B(50) xor C(50) xor a(50);
D(51) <= I(51) xor B(51) xor C(51) xor a(51);
D(52) <= I(52) xor B(52) xor C(52) xor a(52);
D(53) <= I(53) xor B(53) xor C(53) xor a(53);
D(54) <= I(54) xor B(54) xor C(54) xor a(54);
D(55) <= I(55) xor B(55) xor C(55) xor a(55);
D(56) <= I(56) xor B(56) xor C(56) xor a(56);
D(57) <= I(57) xor B(57) xor C(57) xor a(57);
D(58) <= I(58) xor B(58) xor C(58) xor a(58);
D(59) <= I(59) xor B(59) xor C(59) xor a(59);
D(60) <= I(60) xor B(60) xor C(60) xor a(60);
D(61) <= I(61) xor B(61) xor C(61) xor a(61);
D(62) <= I(62) xor B(62) xor C(62) xor a(62);
D(63) <= I(63) xor B(63) xor C(63) xor a(63);
D(64) <= I(64) xor B(64) xor C(64) xor a(64);
D(65) <= I(65) xor B(65) xor C(65) xor a(65);
D(66) <= I(66) xor B(66) xor C(66) xor a(66);
D(67) <= I(67) xor B(67) xor C(67) xor a(67);
D(68) <= I(68) xor B(68) xor C(68) xor a(68);
D(69) <= I(69) xor B(69) xor C(69) xor a(69);
D(70) <= I(70) xor B(70) xor C(70) xor a(70);
D(71) <= I(71) xor B(71) xor C(71) xor a(71);
D(72) <= I(72) xor B(72) xor C(72) xor a(72);
D(73) <= I(73) xor B(73) xor C(73) xor a(73);
D(74) <= I(74) xor B(74) xor C(74) xor a(74);
D(75) <= I(75) xor B(75) xor C(75) xor a(75);
D(76) <= I(76) xor B(76) xor C(76) xor a(76);
D(77) <= I(77) xor B(77) xor C(77) xor a(77);
D(78) <= I(78) xor B(78) xor C(78) xor a(78);
D(79) <= I(79) xor B(79) xor C(79) xor a(79);
D(80) <= I(80) xor B(80) xor C(80) xor a(80);
D(81) <= I(81) xor B(81) xor C(81) xor a(81);
D(82) <= I(82) xor B(82) xor C(82) xor a(82);
D(83) <= I(83) xor B(83) xor C(83) xor a(83);
D(84) <= I(84) xor B(84) xor C(84) xor a(84);
D(85) <= I(85) xor B(85) xor C(85) xor a(85);
D(86) <= I(86) xor B(86) xor C(86) xor a(86);
D(87) <= I(87) xor B(87) xor C(87) xor a(87);
D(88) <= I(88) xor B(88) xor C(88) xor a(88);
D(89) <= I(89) xor B(89) xor C(89) xor a(89);
D(90) <= I(90) xor B(90) xor C(90) xor a(90);
D(91) <= I(91) xor B(91) xor C(91) xor a(91);
D(92) <= I(92) xor B(92) xor C(92) xor a(92);
D(93) <= I(93) xor B(93) xor C(93) xor a(93);
D(94) <= I(94) xor B(94) xor C(94) xor a(94);
D(95) <= I(95) xor B(95) xor C(95) xor a(95);
D(96) <= I(96) xor B(96) xor C(96) xor a(96);
D(97) <= I(97) xor B(97) xor C(97) xor a(97);
D(98) <= I(98) xor B(98) xor C(98) xor a(98);
D(99) <= I(99) xor B(99) xor C(99) xor a(99);
D(100) <= I(100) xor B(100) xor C(100) xor a(100);
D(101) <= I(101) xor B(101) xor C(101) xor a(101);
D(102) <= I(102) xor B(102) xor C(102) xor a(102);
D(103) <= I(103) xor B(103) xor C(103) xor a(103);
D(104) <= I(104) xor B(104) xor C(104) xor a(104);
D(105) <= I(105) xor B(105) xor C(105) xor a(105);
D(106) <= I(106) xor B(106) xor C(106) xor a(106);
D(107) <= I(107) xor B(107) xor C(107) xor a(107);
D(108) <= I(108) xor B(108) xor C(108) xor a(108);
D(109) <= I(109) xor B(109) xor C(109) xor a(109);
D(110) <= I(110) xor B(110) xor C(110) xor a(110);
D(111) <= I(111) xor B(111) xor C(111) xor a(111);
D(112) <= I(112) xor B(112) xor C(112) xor a(112);
D(113) <= I(113) xor B(113) xor C(113) xor a(113);
D(114) <= I(114) xor B(114) xor C(114) xor a(114);
D(115) <= I(115) xor B(115) xor C(115) xor a(115);
D(116) <= I(116) xor B(116) xor C(116) xor a(116);
D(117) <= I(117) xor B(117) xor C(117) xor a(117);
D(118) <= I(118) xor B(118) xor C(118) xor a(118);
D(119) <= I(119) xor B(119) xor C(119) xor a(119);
D(120) <= I(120) xor B(120) xor C(120) xor a(120);
D(121) <= I(121) xor B(121) xor C(121) xor a(121);
D(122) <= I(122) xor B(122) xor C(122) xor a(122);
D(123) <= I(123) xor B(123) xor C(123) xor a(123);
D(124) <= I(124) xor B(124) xor C(124) xor a(124);
D(125) <= I(125) xor B(125) xor C(125) xor a(125);
D(126) <= I(126) xor B(126) xor C(126) xor a(126);
D(127) <= I(127) xor B(127) xor C(127) xor a(127);
D(128) <= I(128) xor B(128) xor C(128) xor a(128);
D(129) <= I(129) xor B(129) xor C(129) xor a(129);
D(130) <= I(130) xor B(130) xor C(130) xor a(130);
end; |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
end if;
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
end if;
if a = '1' then
b <= '0';
elsif c = '1' and
d = '0' then
b <= '1';
end if;
end process;
end architecture RTL;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
USE ieee.numeric_std.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module generates the clocks needed for the I/O devices on *
-- * Altera's DE-series boards. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Clock_Signals IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
CLOCK_50 :IN STD_LOGIC;
reset :IN STD_LOGIC;
-- Bidirectionals
-- Outputs
VGA_CLK :BUFFER STD_LOGIC;
sys_clk :BUFFER STD_LOGIC;
sys_reset_n :BUFFER STD_LOGIC
);
END Video_System_Clock_Signals;
ARCHITECTURE Behaviour OF Video_System_Clock_Signals IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
CONSTANT SYS_CLK_MULT :INTEGER := 1;
CONSTANT SYS_CLK_DIV :INTEGER := 1;
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL sys_mem_clks :STD_LOGIC_VECTOR( 2 DOWNTO 0);
SIGNAL clk_locked :STD_LOGIC;
SIGNAL video_in_clk :STD_LOGIC;
SIGNAL SDRAM_CLK :STD_LOGIC;
-- Internal Registers
-- State Machine Registers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT altpll
GENERIC (
clk0_divide_by :INTEGER;
clk0_duty_cycle :INTEGER;
clk0_multiply_by :INTEGER;
clk0_phase_shift :STRING;
clk1_divide_by :INTEGER;
clk1_duty_cycle :INTEGER;
clk1_multiply_by :INTEGER;
clk1_phase_shift :STRING;
clk2_divide_by :INTEGER;
clk2_duty_cycle :INTEGER;
clk2_multiply_by :INTEGER;
clk2_phase_shift :STRING;
compensate_clock :STRING;
gate_lock_signal :STRING;
inclk0_input_frequency :INTEGER;
intended_device_family :STRING;
invalid_lock_multiplier :INTEGER;
lpm_type :STRING;
operation_mode :STRING;
pll_type :STRING;
port_activeclock :STRING;
port_areset :STRING;
port_clkbad0 :STRING;
port_clkbad1 :STRING;
port_clkloss :STRING;
port_clkswitch :STRING;
port_fbin :STRING;
port_inclk0 :STRING;
port_inclk1 :STRING;
port_locked :STRING;
port_pfdena :STRING;
port_pllena :STRING;
port_scanaclr :STRING;
port_scanclk :STRING;
port_scandata :STRING;
port_scandataout :STRING;
port_scandone :STRING;
port_scanread :STRING;
port_scanwrite :STRING;
port_clk0 :STRING;
port_clk1 :STRING;
port_clk2 :STRING;
port_clk3 :STRING;
port_clk4 :STRING;
port_clk5 :STRING;
port_clkena0 :STRING;
port_clkena1 :STRING;
port_clkena2 :STRING;
port_clkena3 :STRING;
port_clkena4 :STRING;
port_clkena5 :STRING;
port_enable0 :STRING;
port_enable1 :STRING;
port_extclk0 :STRING;
port_extclk1 :STRING;
port_extclk2 :STRING;
port_extclk3 :STRING;
port_extclkena0 :STRING;
port_extclkena1 :STRING;
port_extclkena2 :STRING;
port_extclkena3 :STRING;
port_sclkout0 :STRING;
port_sclkout1 :STRING;
valid_lock_multiplier :INTEGER
);
PORT (
-- Inputs
inclk :IN STD_LOGIC_VECTOR( 1 DOWNTO 0);
-- Outputs
clk :BUFFER STD_LOGIC_VECTOR( 2 DOWNTO 0);
locked :BUFFER STD_LOGIC
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
-- Internal Registers
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
sys_reset_n <= clk_locked;
sys_clk <= sys_mem_clks(0);
SDRAM_CLK <= sys_mem_clks(1);
VGA_CLK <= sys_mem_clks(2);
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
DE_Clock_Generator_System : altpll
GENERIC MAP (
clk0_divide_by => SYS_CLK_DIV,
clk0_duty_cycle => 50,
clk0_multiply_by => SYS_CLK_MULT,
clk0_phase_shift => "0",
clk1_divide_by => SYS_CLK_DIV,
clk1_duty_cycle => 50,
clk1_multiply_by => SYS_CLK_MULT,
clk1_phase_shift => "-3000",
clk2_divide_by => 2,
clk2_duty_cycle => 50,
clk2_multiply_by => 1,
clk2_phase_shift => "20000",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "FAST",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_enable0 => "PORT_UNUSED",
port_enable1 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
port_extclkena0 => "PORT_UNUSED",
port_extclkena1 => "PORT_UNUSED",
port_extclkena2 => "PORT_UNUSED",
port_extclkena3 => "PORT_UNUSED",
port_sclkout0 => "PORT_UNUSED",
port_sclkout1 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
-- Inputs
inclk => '0' & CLOCK_50,
-- Outputs
clk => sys_mem_clks,
locked => clk_locked
);
END Behaviour;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity find_first_set is
end entity find_first_set;
architecture test of find_first_set is
-- code from book
procedure find_first_set ( v : in bit_vector;
found : out boolean;
first_set_index : out natural ) is
begin
for index in v'range loop
if v(index) = '1' then
found := true;
first_set_index := index;
return;
end if;
end loop;
found := false;
end procedure find_first_set;
-- end code from book
begin
stimulus : process is
-- code from book (in text)
variable int_req : bit_vector (7 downto 0);
variable top_priority : natural;
variable int_pending : boolean;
-- . . .
-- end code from book
constant block_count : natural := 16;
-- code from book (in text)
variable free_block_map : bit_vector(0 to block_count-1);
variable first_free_block : natural;
variable free_block_found : boolean;
-- . . .
-- end code from book
begin
int_req := "00010000";
-- code from book (in text)
find_first_set ( int_req, int_pending, top_priority );
-- end code from book
free_block_map := (others => '0');
-- code from book (in text)
find_first_set ( free_block_map, free_block_found, first_free_block );
-- end code from book
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity find_first_set is
end entity find_first_set;
architecture test of find_first_set is
-- code from book
procedure find_first_set ( v : in bit_vector;
found : out boolean;
first_set_index : out natural ) is
begin
for index in v'range loop
if v(index) = '1' then
found := true;
first_set_index := index;
return;
end if;
end loop;
found := false;
end procedure find_first_set;
-- end code from book
begin
stimulus : process is
-- code from book (in text)
variable int_req : bit_vector (7 downto 0);
variable top_priority : natural;
variable int_pending : boolean;
-- . . .
-- end code from book
constant block_count : natural := 16;
-- code from book (in text)
variable free_block_map : bit_vector(0 to block_count-1);
variable first_free_block : natural;
variable free_block_found : boolean;
-- . . .
-- end code from book
begin
int_req := "00010000";
-- code from book (in text)
find_first_set ( int_req, int_pending, top_priority );
-- end code from book
free_block_map := (others => '0');
-- code from book (in text)
find_first_set ( free_block_map, free_block_found, first_free_block );
-- end code from book
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity find_first_set is
end entity find_first_set;
architecture test of find_first_set is
-- code from book
procedure find_first_set ( v : in bit_vector;
found : out boolean;
first_set_index : out natural ) is
begin
for index in v'range loop
if v(index) = '1' then
found := true;
first_set_index := index;
return;
end if;
end loop;
found := false;
end procedure find_first_set;
-- end code from book
begin
stimulus : process is
-- code from book (in text)
variable int_req : bit_vector (7 downto 0);
variable top_priority : natural;
variable int_pending : boolean;
-- . . .
-- end code from book
constant block_count : natural := 16;
-- code from book (in text)
variable free_block_map : bit_vector(0 to block_count-1);
variable first_free_block : natural;
variable free_block_found : boolean;
-- . . .
-- end code from book
begin
int_req := "00010000";
-- code from book (in text)
find_first_set ( int_req, int_pending, top_priority );
-- end code from book
free_block_map := (others => '0');
-- code from book (in text)
find_first_set ( free_block_map, free_block_found, first_free_block );
-- end code from book
wait;
end process stimulus;
end architecture test;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Chip toplevel design with minimal feature set
--
-- $Id: chip-minimal-a.vhd,v 1.7 2007-08-06 23:31:42 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture minimal of chip is
component spi_boot
generic (
width_bit_cnt_g : integer := 6;
width_img_cnt_g : integer := 2;
num_bits_per_img_g : integer := 18;
sd_init_g : integer := 0;
mmc_compat_clk_div_g : integer := 0;
width_mmc_clk_div_g : integer := 0;
reset_level_g : integer := 0
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_i : in std_logic_vector(31-width_img_cnt_g-num_bits_per_img_g
downto 0);
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
spi_en_outs_o : out std_logic;
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end component;
signal spi_clk_s : std_logic;
signal spi_cs_n_s : std_logic;
signal spi_data_out_s : std_logic;
signal spi_en_outs_s : std_logic;
constant width_img_cnt_c : integer := 2; -- 4 images
constant num_bits_per_img_c : integer := 18; -- 256 kByte per image
constant set_sel_width_c : integer := 31-width_img_cnt_c-num_bits_per_img_c;
signal set_sel_s : std_logic_vector(set_sel_width_c downto 0);
begin
set_sel_s <= (3 => not set_sel_n_i(3),
2 => not set_sel_n_i(2),
1 => not set_sel_n_i(1),
0 => not set_sel_n_i(0),
others => '0');
spi_boot_b : spi_boot
generic map (
width_bit_cnt_g => 6, -- 8 bytes per block
width_img_cnt_g => width_img_cnt_c,
num_bits_per_img_g => num_bits_per_img_c,
sd_init_g => 0, -- no SD specific initialization
mmc_compat_clk_div_g => 0, -- no MMC compatibility
width_mmc_clk_div_g => 0 -- no MMC compatibility
)
port map (
clk_i => clk_i,
reset_i => reset_i,
set_sel_i => set_sel_s,
spi_clk_o => spi_clk_s,
spi_cs_n_o => spi_cs_n_s,
spi_data_in_i => spi_data_in_i,
spi_data_out_o => spi_data_out_s,
spi_en_outs_o => spi_en_outs_s,
start_i => start_i,
mode_i => mode_i,
config_n_o => config_n_o,
detached_o => detached_o,
cfg_init_n_i => cfg_init_n_i,
cfg_done_i => cfg_done_i,
dat_done_i => dat_done_i,
cfg_clk_o => cfg_clk_o,
cfg_dat_o => cfg_dat_o
);
-----------------------------------------------------------------------------
-- Three state drivers for SPI outputs.
-----------------------------------------------------------------------------
spi_clk_o <= spi_clk_s
when spi_en_outs_s = '1' else
'Z';
spi_cs_n_o <= spi_cs_n_s
when spi_en_outs_s = '1' else
'Z';
spi_data_out_o <= spi_data_out_s
when spi_en_outs_s = '1' else
'Z';
end minimal;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2005/04/07 20:44:23 arniml
-- add new port detached_o
--
-- Revision 1.5 2005/03/09 19:48:34 arniml
-- invert level of set_sel input
--
-- Revision 1.4 2005/03/08 22:07:12 arniml
-- added set selection
--
-- Revision 1.3 2005/02/18 06:42:12 arniml
-- clarify wording for images
--
-- Revision 1.2 2005/02/16 18:54:39 arniml
-- added tri-state drivers for spi outputs
--
-- Revision 1.1 2005/02/08 20:41:31 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY dataMemory IS
PORT (
address : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
writeData : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
memRead : IN STD_LOGIC;
memWrite : IN STD_LOGIC;
readData : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END dataMemory;
ARCHITECTURE Behavioral OF dataMemory IS
TYPE RAM_16_x_32 IS ARRAY(0 TO 15) OF std_logic_vector(31 DOWNTO 0);
SIGNAL DM : RAM_16_x_32 := (
x"00000000", -- assume starts at 0x1000100000
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000"
);
BEGIN
PROCESS (memWrite, memRead) -- pulse on write
-- Note: 268500992 = 0x10010000
BEGIN
IF (memWrite = '1') THEN
DM((to_integer(unsigned(address)) - 268500992) / 4) <= writeData;
END IF;
IF (memRead = '1') THEN
readData <= DM((to_integer(unsigned(address)) - 268500992)/4);
END IF;
-- it gives, 0, 1, 2, 3, 4, ...
END PROCESS;
END Behavioral; |
------------------------------------------------------------------------------------------------------------------------
-- Global package
--
-- Copyright (C) 2012 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2012-02-07 zelenkaj Derived from global package
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Global is
constant cActivated : std_logic := '1';
constant cInactivated : std_logic := '0';
constant cnActivated : std_logic := '0';
constant cnInactivated : std_logic := '1';
function LogDualis(cNumber : natural) return natural;
end Global;
package body Global is
function LogDualis(cNumber : natural) return natural is
variable vClimbUp : natural := 1;
variable vResult : natural;
begin
while vClimbUp < cNumber loop
vClimbUp := vClimbUp * 2;
vResult := vResult+1;
end loop;
return vResult;
end LogDualis;
end Global; |
------------------------------------------------------------------------------------------------------------------------
-- Global package
--
-- Copyright (C) 2012 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2012-02-07 zelenkaj Derived from global package
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Global is
constant cActivated : std_logic := '1';
constant cInactivated : std_logic := '0';
constant cnActivated : std_logic := '0';
constant cnInactivated : std_logic := '1';
function LogDualis(cNumber : natural) return natural;
end Global;
package body Global is
function LogDualis(cNumber : natural) return natural is
variable vClimbUp : natural := 1;
variable vResult : natural;
begin
while vClimbUp < cNumber loop
vClimbUp := vClimbUp * 2;
vResult := vResult+1;
end loop;
return vResult;
end LogDualis;
end Global; |
------------------------------------------------------------------------------------------------------------------------
-- Global package
--
-- Copyright (C) 2012 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2012-02-07 zelenkaj Derived from global package
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Global is
constant cActivated : std_logic := '1';
constant cInactivated : std_logic := '0';
constant cnActivated : std_logic := '0';
constant cnInactivated : std_logic := '1';
function LogDualis(cNumber : natural) return natural;
end Global;
package body Global is
function LogDualis(cNumber : natural) return natural is
variable vClimbUp : natural := 1;
variable vResult : natural;
begin
while vClimbUp < cNumber loop
vClimbUp := vClimbUp * 2;
vResult := vResult+1;
end loop;
return vResult;
end LogDualis;
end Global; |
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