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------------------------------------------------------------------------------- -- MacAddrRAM - entity/architecture pair ------------------------------------------------------------------------------- -- *************************************************************************** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2010 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- *************************************************************************** -- ------------------------------------------------------------------------------- -- Filename : macaddram.vhd -- Version : v2.0 -- Description : Design file for the Ethernet Lite MAC. -- There is a rom used in the MII to store the MAC address -- -- Note that the two nibbles in each word of the MAC address -- are transposed in order to transmit to the network in the -- proper order.However, the generic value (MACAddr)of this -- ROM keeps the normal order. -- -- Representation of each word in this ROM (list with address order) -- -- Addr (3 downto 0) : netOrder(MACAddr(47 downto 32)) e.g.: 0xafec -- Addr (7 downto 4) : netOrder(MACAddr(31 downto 16)) e.g.: 0xedfa -- Addr (11 downto 8) : netOrder(MACAddr(15 downto 0)) e.g.: 0xacef -- Addr (15 downto 12) : netOrder(Filler) e.g.: 0x0000 -- -- Uses 4 LUTs (4 rom16x1), 0 register -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- axi_ethernetlite.vhd -- \ -- \-- axi_interface.vhd -- \-- xemac.vhd -- \ -- \-- mdio_if.vhd -- \-- emac_dpram.vhd -- \ \ -- \ \-- RAMB16_S4_S36 -- \ -- \ -- \-- emac.vhd -- \ -- \-- MacAddrRAM -- \-- receive.vhd -- \ rx_statemachine.vhd -- \ rx_intrfce.vhd -- \ async_fifo_fg.vhd -- \ crcgenrx.vhd -- \ -- \-- transmit.vhd -- crcgentx.vhd -- crcnibshiftreg -- tx_intrfce.vhd -- async_fifo_fg.vhd -- tx_statemachine.vhd -- deferral.vhd -- cntr5bit.vhd -- defer_state.vhd -- bocntr.vhd -- lfsr16.vhd -- msh_cnt.vhd -- ld_arith_reg.vhd -- ------------------------------------------------------------------------------- -- Author: PVK -- History: -- PVK 06/07/2010 First Version -- ^^^^^^ -- First version. -- ~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "Clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- -- library ieee; use ieee.STD_LOGIC_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ------------------------------------------------------------------------------- -- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0 -- component declarations ------------------------------------------------------------------------------- library axi_ethernetlite_v3_0; use axi_ethernetlite_v3_0.mac_pkg.all; ------------------------------------------------------------------------------- -- synopsys translate_off -- Library XilinxCoreLib; --library simprim; -- synopsys translate_on ------------------------------------------------------------------------------- -- Vcomponents from unisim library is used for FIFO instatiation -- function declarations ------------------------------------------------------------------------------- library unisim; use unisim.Vcomponents.all; ------------------------------------------------------------------------------- -- Definition of Generics: ------------------------------------------------------------------------------- -- -- MACAddr -- MAC Address -- Filler -- Filler ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Ports: -- -- Addr -- Address -- Dout -- Data output -- Din -- Data input -- We -- Write Enable -- Clk -- Clock ------------------------------------------------------------------------------- -- ENTITY ------------------------------------------------------------------------------- entity MacAddrRAM is generic (MACAddr : bit_vector(47 downto 0) := x"ffffffffffaa"; -- use the normal order Filler : bit_vector(15 downto 0) := x"0000"); port( Addr : in std_logic_vector (3 downto 0); Dout : out std_logic_vector (3 downto 0); Din : in std_logic_vector (3 downto 0); We : in std_logic; Clk : in std_logic ); end MacAddrRAM; architecture imp of MacAddrRAM is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- Constants used in this design are found in mac_pkg.vhd ------------------------------------------------------------------------------- -- Component Declarations ------------------------------------------------------------------------------- -- The following components are the building blocks of the EMAC --component ram16x4 -- generic( -- INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for Addr(3 downto 0) -- INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for Addr(7 downto 4) -- INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for Addr(11 downto 8) -- INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for Addr(15 downto 12) -- ); -- port( -- Addr : in std_logic_vector(3 downto 0); -- D : in std_logic_vector(3 downto 0); -- We : in std_logic; -- Clk : in std_logic; -- Q : out std_logic_vector(3 downto 0)); --end component; begin ram16x4i: entity axi_ethernetlite_v3_0.ram16x4 generic map (INIT_00 => netOrder(MACAddr(47 downto 32)), INIT_01 => netOrder(MACAddr(31 downto 16)), INIT_02 => netOrder(MACAddr(15 downto 0)), INIT_03 => netOrder(Filler) ) port map (Addr => Addr, D => Din, Q => Dout, We => We, Clk => Clk ); end imp;
------------------------------------------------------------------------------- -- MacAddrRAM - entity/architecture pair ------------------------------------------------------------------------------- -- *************************************************************************** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2010 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- *************************************************************************** -- ------------------------------------------------------------------------------- -- Filename : macaddram.vhd -- Version : v2.0 -- Description : Design file for the Ethernet Lite MAC. -- There is a rom used in the MII to store the MAC address -- -- Note that the two nibbles in each word of the MAC address -- are transposed in order to transmit to the network in the -- proper order.However, the generic value (MACAddr)of this -- ROM keeps the normal order. -- -- Representation of each word in this ROM (list with address order) -- -- Addr (3 downto 0) : netOrder(MACAddr(47 downto 32)) e.g.: 0xafec -- Addr (7 downto 4) : netOrder(MACAddr(31 downto 16)) e.g.: 0xedfa -- Addr (11 downto 8) : netOrder(MACAddr(15 downto 0)) e.g.: 0xacef -- Addr (15 downto 12) : netOrder(Filler) e.g.: 0x0000 -- -- Uses 4 LUTs (4 rom16x1), 0 register -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- axi_ethernetlite.vhd -- \ -- \-- axi_interface.vhd -- \-- xemac.vhd -- \ -- \-- mdio_if.vhd -- \-- emac_dpram.vhd -- \ \ -- \ \-- RAMB16_S4_S36 -- \ -- \ -- \-- emac.vhd -- \ -- \-- MacAddrRAM -- \-- receive.vhd -- \ rx_statemachine.vhd -- \ rx_intrfce.vhd -- \ async_fifo_fg.vhd -- \ crcgenrx.vhd -- \ -- \-- transmit.vhd -- crcgentx.vhd -- crcnibshiftreg -- tx_intrfce.vhd -- async_fifo_fg.vhd -- tx_statemachine.vhd -- deferral.vhd -- cntr5bit.vhd -- defer_state.vhd -- bocntr.vhd -- lfsr16.vhd -- msh_cnt.vhd -- ld_arith_reg.vhd -- ------------------------------------------------------------------------------- -- Author: PVK -- History: -- PVK 06/07/2010 First Version -- ^^^^^^ -- First version. -- ~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "Clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- -- library ieee; use ieee.STD_LOGIC_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ------------------------------------------------------------------------------- -- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0 -- component declarations ------------------------------------------------------------------------------- library axi_ethernetlite_v3_0; use axi_ethernetlite_v3_0.mac_pkg.all; ------------------------------------------------------------------------------- -- synopsys translate_off -- Library XilinxCoreLib; --library simprim; -- synopsys translate_on ------------------------------------------------------------------------------- -- Vcomponents from unisim library is used for FIFO instatiation -- function declarations ------------------------------------------------------------------------------- library unisim; use unisim.Vcomponents.all; ------------------------------------------------------------------------------- -- Definition of Generics: ------------------------------------------------------------------------------- -- -- MACAddr -- MAC Address -- Filler -- Filler ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Ports: -- -- Addr -- Address -- Dout -- Data output -- Din -- Data input -- We -- Write Enable -- Clk -- Clock ------------------------------------------------------------------------------- -- ENTITY ------------------------------------------------------------------------------- entity MacAddrRAM is generic (MACAddr : bit_vector(47 downto 0) := x"ffffffffffaa"; -- use the normal order Filler : bit_vector(15 downto 0) := x"0000"); port( Addr : in std_logic_vector (3 downto 0); Dout : out std_logic_vector (3 downto 0); Din : in std_logic_vector (3 downto 0); We : in std_logic; Clk : in std_logic ); end MacAddrRAM; architecture imp of MacAddrRAM is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- Constants used in this design are found in mac_pkg.vhd ------------------------------------------------------------------------------- -- Component Declarations ------------------------------------------------------------------------------- -- The following components are the building blocks of the EMAC --component ram16x4 -- generic( -- INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for Addr(3 downto 0) -- INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for Addr(7 downto 4) -- INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for Addr(11 downto 8) -- INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for Addr(15 downto 12) -- ); -- port( -- Addr : in std_logic_vector(3 downto 0); -- D : in std_logic_vector(3 downto 0); -- We : in std_logic; -- Clk : in std_logic; -- Q : out std_logic_vector(3 downto 0)); --end component; begin ram16x4i: entity axi_ethernetlite_v3_0.ram16x4 generic map (INIT_00 => netOrder(MACAddr(47 downto 32)), INIT_01 => netOrder(MACAddr(31 downto 16)), INIT_02 => netOrder(MACAddr(15 downto 0)), INIT_03 => netOrder(Filler) ) port map (Addr => Addr, D => Din, Q => Dout, We => We, Clk => Clk ); end imp;
------------------------------------------------------------------------------- -- MacAddrRAM - entity/architecture pair ------------------------------------------------------------------------------- -- *************************************************************************** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2010 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- *************************************************************************** -- ------------------------------------------------------------------------------- -- Filename : macaddram.vhd -- Version : v2.0 -- Description : Design file for the Ethernet Lite MAC. -- There is a rom used in the MII to store the MAC address -- -- Note that the two nibbles in each word of the MAC address -- are transposed in order to transmit to the network in the -- proper order.However, the generic value (MACAddr)of this -- ROM keeps the normal order. -- -- Representation of each word in this ROM (list with address order) -- -- Addr (3 downto 0) : netOrder(MACAddr(47 downto 32)) e.g.: 0xafec -- Addr (7 downto 4) : netOrder(MACAddr(31 downto 16)) e.g.: 0xedfa -- Addr (11 downto 8) : netOrder(MACAddr(15 downto 0)) e.g.: 0xacef -- Addr (15 downto 12) : netOrder(Filler) e.g.: 0x0000 -- -- Uses 4 LUTs (4 rom16x1), 0 register -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- axi_ethernetlite.vhd -- \ -- \-- axi_interface.vhd -- \-- xemac.vhd -- \ -- \-- mdio_if.vhd -- \-- emac_dpram.vhd -- \ \ -- \ \-- RAMB16_S4_S36 -- \ -- \ -- \-- emac.vhd -- \ -- \-- MacAddrRAM -- \-- receive.vhd -- \ rx_statemachine.vhd -- \ rx_intrfce.vhd -- \ async_fifo_fg.vhd -- \ crcgenrx.vhd -- \ -- \-- transmit.vhd -- crcgentx.vhd -- crcnibshiftreg -- tx_intrfce.vhd -- async_fifo_fg.vhd -- tx_statemachine.vhd -- deferral.vhd -- cntr5bit.vhd -- defer_state.vhd -- bocntr.vhd -- lfsr16.vhd -- msh_cnt.vhd -- ld_arith_reg.vhd -- ------------------------------------------------------------------------------- -- Author: PVK -- History: -- PVK 06/07/2010 First Version -- ^^^^^^ -- First version. -- ~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "Clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- -- library ieee; use ieee.STD_LOGIC_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ------------------------------------------------------------------------------- -- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0 -- component declarations ------------------------------------------------------------------------------- library axi_ethernetlite_v3_0; use axi_ethernetlite_v3_0.mac_pkg.all; ------------------------------------------------------------------------------- -- synopsys translate_off -- Library XilinxCoreLib; --library simprim; -- synopsys translate_on ------------------------------------------------------------------------------- -- Vcomponents from unisim library is used for FIFO instatiation -- function declarations ------------------------------------------------------------------------------- library unisim; use unisim.Vcomponents.all; ------------------------------------------------------------------------------- -- Definition of Generics: ------------------------------------------------------------------------------- -- -- MACAddr -- MAC Address -- Filler -- Filler ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Ports: -- -- Addr -- Address -- Dout -- Data output -- Din -- Data input -- We -- Write Enable -- Clk -- Clock ------------------------------------------------------------------------------- -- ENTITY ------------------------------------------------------------------------------- entity MacAddrRAM is generic (MACAddr : bit_vector(47 downto 0) := x"ffffffffffaa"; -- use the normal order Filler : bit_vector(15 downto 0) := x"0000"); port( Addr : in std_logic_vector (3 downto 0); Dout : out std_logic_vector (3 downto 0); Din : in std_logic_vector (3 downto 0); We : in std_logic; Clk : in std_logic ); end MacAddrRAM; architecture imp of MacAddrRAM is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- Constants used in this design are found in mac_pkg.vhd ------------------------------------------------------------------------------- -- Component Declarations ------------------------------------------------------------------------------- -- The following components are the building blocks of the EMAC --component ram16x4 -- generic( -- INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for Addr(3 downto 0) -- INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for Addr(7 downto 4) -- INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for Addr(11 downto 8) -- INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for Addr(15 downto 12) -- ); -- port( -- Addr : in std_logic_vector(3 downto 0); -- D : in std_logic_vector(3 downto 0); -- We : in std_logic; -- Clk : in std_logic; -- Q : out std_logic_vector(3 downto 0)); --end component; begin ram16x4i: entity axi_ethernetlite_v3_0.ram16x4 generic map (INIT_00 => netOrder(MACAddr(47 downto 32)), INIT_01 => netOrder(MACAddr(31 downto 16)), INIT_02 => netOrder(MACAddr(15 downto 0)), INIT_03 => netOrder(Filler) ) port map (Addr => Addr, D => Din, Q => Dout, We => We, Clk => Clk ); end imp;
------------------------------------------------------------------------------- -- MacAddrRAM - entity/architecture pair ------------------------------------------------------------------------------- -- *************************************************************************** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2010 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- *************************************************************************** -- ------------------------------------------------------------------------------- -- Filename : macaddram.vhd -- Version : v2.0 -- Description : Design file for the Ethernet Lite MAC. -- There is a rom used in the MII to store the MAC address -- -- Note that the two nibbles in each word of the MAC address -- are transposed in order to transmit to the network in the -- proper order.However, the generic value (MACAddr)of this -- ROM keeps the normal order. -- -- Representation of each word in this ROM (list with address order) -- -- Addr (3 downto 0) : netOrder(MACAddr(47 downto 32)) e.g.: 0xafec -- Addr (7 downto 4) : netOrder(MACAddr(31 downto 16)) e.g.: 0xedfa -- Addr (11 downto 8) : netOrder(MACAddr(15 downto 0)) e.g.: 0xacef -- Addr (15 downto 12) : netOrder(Filler) e.g.: 0x0000 -- -- Uses 4 LUTs (4 rom16x1), 0 register -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- axi_ethernetlite.vhd -- \ -- \-- axi_interface.vhd -- \-- xemac.vhd -- \ -- \-- mdio_if.vhd -- \-- emac_dpram.vhd -- \ \ -- \ \-- RAMB16_S4_S36 -- \ -- \ -- \-- emac.vhd -- \ -- \-- MacAddrRAM -- \-- receive.vhd -- \ rx_statemachine.vhd -- \ rx_intrfce.vhd -- \ async_fifo_fg.vhd -- \ crcgenrx.vhd -- \ -- \-- transmit.vhd -- crcgentx.vhd -- crcnibshiftreg -- tx_intrfce.vhd -- async_fifo_fg.vhd -- tx_statemachine.vhd -- deferral.vhd -- cntr5bit.vhd -- defer_state.vhd -- bocntr.vhd -- lfsr16.vhd -- msh_cnt.vhd -- ld_arith_reg.vhd -- ------------------------------------------------------------------------------- -- Author: PVK -- History: -- PVK 06/07/2010 First Version -- ^^^^^^ -- First version. -- ~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "Clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- -- library ieee; use ieee.STD_LOGIC_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ------------------------------------------------------------------------------- -- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0 -- component declarations ------------------------------------------------------------------------------- library axi_ethernetlite_v3_0; use axi_ethernetlite_v3_0.mac_pkg.all; ------------------------------------------------------------------------------- -- synopsys translate_off -- Library XilinxCoreLib; --library simprim; -- synopsys translate_on ------------------------------------------------------------------------------- -- Vcomponents from unisim library is used for FIFO instatiation -- function declarations ------------------------------------------------------------------------------- library unisim; use unisim.Vcomponents.all; ------------------------------------------------------------------------------- -- Definition of Generics: ------------------------------------------------------------------------------- -- -- MACAddr -- MAC Address -- Filler -- Filler ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Ports: -- -- Addr -- Address -- Dout -- Data output -- Din -- Data input -- We -- Write Enable -- Clk -- Clock ------------------------------------------------------------------------------- -- ENTITY ------------------------------------------------------------------------------- entity MacAddrRAM is generic (MACAddr : bit_vector(47 downto 0) := x"ffffffffffaa"; -- use the normal order Filler : bit_vector(15 downto 0) := x"0000"); port( Addr : in std_logic_vector (3 downto 0); Dout : out std_logic_vector (3 downto 0); Din : in std_logic_vector (3 downto 0); We : in std_logic; Clk : in std_logic ); end MacAddrRAM; architecture imp of MacAddrRAM is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- Constants used in this design are found in mac_pkg.vhd ------------------------------------------------------------------------------- -- Component Declarations ------------------------------------------------------------------------------- -- The following components are the building blocks of the EMAC --component ram16x4 -- generic( -- INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for Addr(3 downto 0) -- INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for Addr(7 downto 4) -- INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for Addr(11 downto 8) -- INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for Addr(15 downto 12) -- ); -- port( -- Addr : in std_logic_vector(3 downto 0); -- D : in std_logic_vector(3 downto 0); -- We : in std_logic; -- Clk : in std_logic; -- Q : out std_logic_vector(3 downto 0)); --end component; begin ram16x4i: entity axi_ethernetlite_v3_0.ram16x4 generic map (INIT_00 => netOrder(MACAddr(47 downto 32)), INIT_01 => netOrder(MACAddr(31 downto 16)), INIT_02 => netOrder(MACAddr(15 downto 0)), INIT_03 => netOrder(Filler) ) port map (Addr => Addr, D => Din, Q => Dout, We => We, Clk => Clk ); end imp;
--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_prod_data_lgth_calc | -- | --------------------------------------------------------------------------------------------------- -- File wf_prod_data_lgth_calc.vhd | -- | -- Description Calculation of the number of bytes, after the FSS and before the FCS, that have to| -- be transferred when a variable is produced (var_pres, var_identif, var_3, var_5) | -- As the following figure indicates, in detail, the unit adds-up: | -- o 1 byte RP_DAT.CTRL, | -- o 1 byte RP_DAT.Data.PDU_TYPE, | -- o 1 byte RP_DAT.Data.LGTH, | -- o 1-124 RP_DAT.Data.User_Data bytes according to the variable type: | -- - var_pres: 5 bytes | -- - var_pres: 8 bytes | -- - var_5 : 1 byte | -- - var_3 : 2-124 bytes defined by the "nanoFIP User Interface,General signal"| -- SLONE and the "nanoFIP WorldFIP Settings" input P3_LGTH, | -- o 1 byte RP_DAT.Data.nanoFIP_status, always for a var_5 | -- and for a var_3, if the "nanoFIP User | -- Interface General signal"NOSTAT is negated,| -- o 1 byte RP_DAT.Data.MPS_status, for a var_3 and a var_5 | -- | -- | -- Reminder: | -- | -- Produced RP_DAT frame structure : | -- ||--------------------- Data ---------------------|| | -- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ | -- |____FSS____|_CTRL_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__| | -- | -- |-----P3_LGTH-----| | -- | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 09/12/2010 | -- Version v0.02 | -- Depends on wf_engine_control | ---------------- | -- Last changes | -- 12/2010 v0.02 EG code cleaned-up+commented | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_prod_data_lgth_calc --================================================================================================= entity wf_prod_data_lgth_calc is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- nanoFIP WorldFIP Settings p3_lgth_i : in std_logic_vector (2 downto 0); -- produced var user-data length -- User Interface, General signals nostat_i : in std_logic; -- if negated, nFIP status is sent slone_i : in std_logic; -- stand-alone mode -- Signal from the wf_engine_control unit var_i : in t_var; -- variable type that is being treated -- OUTPUT -- Signal to the wf_engine_control and wf_production units prod_data_lgth_o : out std_logic_vector (7 downto 0)); end entity wf_prod_data_lgth_calc; --================================================================================================= -- architecture declaration --================================================================================================= architecture behavior of wf_prod_data_lgth_calc is signal s_prod_data_lgth, s_p3_lgth_decoded : unsigned (7 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Combinatorial process data_length_calcul: calculation of the amount of bytes, after the -- FSS and before the FCS, that have to be transferred when a variable is produced. In the case -- of the presence, the identification and the var5 variables, the data length is predefined in the -- WF_PACKAGE. In the case of a var3 the inputs SLONE, NOSTAT and P3_LGTH[] are accounted for the -- calculation. data_length_calcul: process (var_i, s_p3_lgth_decoded, slone_i, nostat_i, p3_lgth_i) begin s_p3_lgth_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i))); case var_i is -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when var_presence => -- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE) s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_lgth; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when var_identif => -- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE) s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_lgth; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when var_3 => -- data length calculation according to the operational mode (memory or stand-alone) -- in slone mode 2 bytes of user-data are produced (independently of P3_LGTH) -- to these there should be added: 1 byte CTRL -- 1 byte PDU_TYPE -- 1 byte LGTH -- 1 byte MPS status -- optionally 1 byte nFIP status -- in memory mode the signal "s_p3_lgth_decoded" indicates the amount of user-data; -- to these, there should be added 1 byte CTRL -- 1 byte PDU_TYPE -- 1 byte LGTH -- 1 byte MPS status -- optionally 1 byte nFIP status if slone_i = '1' then if nostat_i = '1' then -- 6 bytes (counting starts from 0!) s_prod_data_lgth <= to_unsigned(5, s_prod_data_lgth'length); else -- 7 bytes s_prod_data_lgth <= to_unsigned(6, s_prod_data_lgth'length); end if; else if nostat_i = '0' then s_prod_data_lgth <= s_p3_lgth_decoded + 4; else s_prod_data_lgth <= s_p3_lgth_decoded + 3; end if; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when var_5 => -- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE) s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_5_INDEX).array_lgth; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when others => s_prod_data_lgth <= (others => '0'); end case; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Registration of the output (coz of slack) Prod_Data_Lgth_Reg: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then prod_data_lgth_o <= (others =>'0'); else prod_data_lgth_o <= std_logic_vector (s_prod_data_lgth); end if; end if; end process; end architecture behavior; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------- -- -- The testbench for t48_core. -- -- $Id: tb-c.vhd,v 1.4 2006-06-21 01:04:05 arniml Exp $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- -- All rights reserved -- ------------------------------------------------------------------------------- configuration tb_behav_c0 of tb is for behav for rom_internal_2k : lpm_rom use configuration work.lpm_rom_c0; end for; for rom_external_2k : lpm_rom use configuration work.lpm_rom_c0; end for; for ram_256 : generic_ram_ena use configuration work.generic_ram_ena_rtl_c0; end for; for ext_ram_b : generic_ram_ena use configuration work.generic_ram_ena_rtl_c0; end for; for t48_core_b : t48_core use configuration work.t48_core_struct_c0; end for; for if_timing_b : if_timing use configuration work.if_timing_behav_c0; end for; end for; end tb_behav_c0; ------------------------------------------------------------------------------- -- File History: -- -- $Log: not supported by cvs2svn $ -- Revision 1.3 2004/05/21 11:22:44 arniml -- exchange syn_rom for lpm_rom -- -- Revision 1.2 2004/04/25 16:23:21 arniml -- added if_timing -- -- Revision 1.1 2004/03/24 21:42:10 arniml -- initial check-in -- -------------------------------------------------------------------------------
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2466.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s03b02x02p03n02i02466ent IS END c07s03b02x02p03n02i02466ent; ARCHITECTURE c07s03b02x02p03n02i02466arch OF c07s03b02x02p03n02i02466ent IS type UN_ARR is array (integer range <>) of character; subtype CON_ARR is UN_ARR( 1 to 5 ) ; signal S : CON_ARR := ('A','Z', others => 'C'); -- No_failure_here BEGIN TESTING: PROCESS BEGIN wait for 1 ns; assert NOT(S(1)='A' and S(2)='Z' and S(3)='C' and S(4)='C' and S(5)='C') report "***PASSED TEST: c07s03b02x02p03n02i02466" severity NOTE; assert (S(1)='A' and S(2)='Z' and S(3)='C' and S(4)='C' and S(5)='C') report "***FAILED TEST: c07s03b02x02p03n02i02466 - An array aggregate with an others choice may appear as the expression defining the initial value of the drivers of one or more signals in an initialization specification." severity ERROR; wait; END PROCESS TESTING; END c07s03b02x02p03n02i02466arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2466.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s03b02x02p03n02i02466ent IS END c07s03b02x02p03n02i02466ent; ARCHITECTURE c07s03b02x02p03n02i02466arch OF c07s03b02x02p03n02i02466ent IS type UN_ARR is array (integer range <>) of character; subtype CON_ARR is UN_ARR( 1 to 5 ) ; signal S : CON_ARR := ('A','Z', others => 'C'); -- No_failure_here BEGIN TESTING: PROCESS BEGIN wait for 1 ns; assert NOT(S(1)='A' and S(2)='Z' and S(3)='C' and S(4)='C' and S(5)='C') report "***PASSED TEST: c07s03b02x02p03n02i02466" severity NOTE; assert (S(1)='A' and S(2)='Z' and S(3)='C' and S(4)='C' and S(5)='C') report "***FAILED TEST: c07s03b02x02p03n02i02466 - An array aggregate with an others choice may appear as the expression defining the initial value of the drivers of one or more signals in an initialization specification." severity ERROR; wait; END PROCESS TESTING; END c07s03b02x02p03n02i02466arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2466.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s03b02x02p03n02i02466ent IS END c07s03b02x02p03n02i02466ent; ARCHITECTURE c07s03b02x02p03n02i02466arch OF c07s03b02x02p03n02i02466ent IS type UN_ARR is array (integer range <>) of character; subtype CON_ARR is UN_ARR( 1 to 5 ) ; signal S : CON_ARR := ('A','Z', others => 'C'); -- No_failure_here BEGIN TESTING: PROCESS BEGIN wait for 1 ns; assert NOT(S(1)='A' and S(2)='Z' and S(3)='C' and S(4)='C' and S(5)='C') report "***PASSED TEST: c07s03b02x02p03n02i02466" severity NOTE; assert (S(1)='A' and S(2)='Z' and S(3)='C' and S(4)='C' and S(5)='C') report "***FAILED TEST: c07s03b02x02p03n02i02466 - An array aggregate with an others choice may appear as the expression defining the initial value of the drivers of one or more signals in an initialization specification." severity ERROR; wait; END PROCESS TESTING; END c07s03b02x02p03n02i02466arch;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library std; use std.textio.all; library work; use work.all; use work.procedures.all; entity tb_serial is end tb_serial; architecture behav of tb_serial is signal rst : std_logic := '1'; signal clk : std_logic := '0'; signal rx : std_logic := '1'; signal tx : std_logic := '1'; signal ena : std_logic := '0'; signal wea : std_logic := '0'; signal dia : std_logic_vector(7 downto 0) := (others => '0'); signal doa : std_logic_vector(7 downto 0) := (others => '0'); signal busy : std_logic := '0'; begin process begin clk <= '1'; wait for 10 ns; clk <= '0'; wait for 10 ns; end process; process variable l : line; begin wait for 61 ns; rst <= '0'; wait for 20 ns; ena <= '1'; wea <= '1'; dia <= X"A1"; wait for 20 ns; dia <= X"A2"; wait for 20 ns; dia <= X"A3"; wait for 20 ns; wea <= '0'; wait for 300 us; assert false report "stop" severity failure; end process; aserial: entity work.serial port map( rst => rst, clk => clk, rx => rx, tx => tx, ena => ena, wea => wea, dia => dia, doa => doa, busy => busy ); rx <= tx; end behav;
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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block iQhNoP8QJ1+kTr3K1ulFnGXGJShy5Jff0AwqOXh+IFE5P69Uc53qVphYu8R52BLkC7tEaLSbbNWk YC1DFRJLXA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block QJGPslOZ4HGlcIUvdMcabcmjWYtY06vuMx1zfz9OpVbYgdasGwK6H4xSN59LFRI6qJyNoznQWgYO DL7eXZ4TuI5mAw0176hgjDTCgN2Ia0eTGF0Sl7jqVGmeZs2MramdL0pnQrxW0TCcY2DnzWIU58ur Oc0G3Q/a1VYyFtXGry0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; --single line ENTITY SimpleComentedUnit2 IS PORT( a : IN STD_LOGIC; b : OUT STD_LOGIC ); END ENTITY; ARCHITECTURE rtl OF SimpleComentedUnit2 IS BEGIN b <= a; END ARCHITECTURE;
library IEEE; use IEEE.STD_LOGIC_1164.all; entity NOR2Gate is port(inPort0 : in std_logic; inPort1 : in std_logic; outPort : out std_logic); end NOR2Gate; architecture Structural of NOR2Gate is signal s_orOut : std_logic; begin or_gate : entity work.OR2Gate(Behavioral) port map(inPort0 => inPort0, inPort1 => inPort1, outPort => s_orOut); not_gate : entity work.NotGate(Behavioral) port map(inPort => s_orOut, outPort => outPort); end Structural;
-------------------------------------------------------------------------------- -- Author: Elahe Jalalpour (el.jalalpour@gmail.com) -- -- Create Date: 27-08-2015 -- Module Name: ha.vhd -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity ha is port(a, b : in std_logic; s, c : out std_logic); end ha; architecture rtl of ha is begin s <= a xor b; c <= a and b; end rtl;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Oipr+gdcA2oQnv/OAgp4Pe6VmHsrTLHpu3iYXZykA9cAIC7qwhYt1YOyseO4j7gL7Bbl58/mMZEK QSmmruO6sA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block UkwE5x4ijx7qxaqaCQ/RrI8RB7Myn4KvRT+MnxD+8OYzNb5WmyJE+1+wjl2fSC4KMnGgu0hu1s5H NhYXbmvDhkmmKPWow3RC7VpQtc8v4+FqJxduDd6lE5hLPuyL/KSjThYHvWBxulgzHSk9ZKzM/pl7 d9tvpc76EWA+s04aBSk= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Oipr+gdcA2oQnv/OAgp4Pe6VmHsrTLHpu3iYXZykA9cAIC7qwhYt1YOyseO4j7gL7Bbl58/mMZEK QSmmruO6sA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block UkwE5x4ijx7qxaqaCQ/RrI8RB7Myn4KvRT+MnxD+8OYzNb5WmyJE+1+wjl2fSC4KMnGgu0hu1s5H NhYXbmvDhkmmKPWow3RC7VpQtc8v4+FqJxduDd6lE5hLPuyL/KSjThYHvWBxulgzHSk9ZKzM/pl7 d9tvpc76EWA+s04aBSk= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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Library IEEE; Use IEEE.std_logic_1164.All; Use IEEE.std_logic_arith.All; Use IEEE.std_logic_unsigned.All; Use Work.RC5_pkg.All; Entity rc5_Struct is Port ( clr : in std_logic; clk : in std_logic; enc : in std_logic; key_vld : in std_logic; key : in std_logic_vector (127 downto 0); data_vld : in std_logic; din : in std_logic_vector (63 downto 0); dout : out std_logic_vector (63 downto 0); data_rdy : out std_logic ); End rc5_Struct; --Architecture Architecture struct of rc5_Struct is --Key Expansion Module Component rc5_rnd_key Port ( clr : in std_logic; clk : in std_logic; key_vld : in std_logic; key_in : in Std_logic_vector (127 downto 0); skey : out rom; key_rdy : out std_logic ); End Component; --Encryption Module Component rc5_enc Port ( clr : in std_logic; clk : in std_logic; din : in std_logic_vector(63 downto 0); di_vld : in std_logic; key_rdy : in std_logic; skey : in rom; dout : out std_logic_vector(63 downto 0); do_rdy : out std_logic ); End Component; --Decryption Module Component rc5_dec Port ( clr : In std_logic; clk : In std_logic; din : In std_logic_vector(63 downto 0); din_vld : In std_logic; key_rdy : In std_logic; skey : In rom; dout : Out std_logic_vector(63 downto 0); dout_rdy : Out std_logic ); End Component; --Signals Signal skey : rom; Signal key_rdy : std_logic; Signal dout_enc : std_logic_vector (63 downto 0); Signal dout_dec : std_logic_vector (63 downto 0); Signal enc_rdy : std_logic; Signal dec_rdy : std_logic; Signal i_cnt : std_logic_vector (3 downto 0); Begin --Port Maps U1 : rc5_rnd_key Port Map (clr => clr, clk => clk, key_in => key, key_vld => key_vld, skey => skey, key_rdy => key_rdy); U2 : rc5_enc Port Map (clr => clr, clk => clk, din => din, di_vld => key_rdy, skey => skey, dout => dout_enc, do_rdy => enc_rdy, key_rdy => key_rdy); U3 : rc5_dec Port Map (clr => clr, clk => clk, din => din, din_vld => key_rdy, skey => skey, dout => dout_dec, dout_rdy => dec_rdy, key_rdy => key_rdy); --Select With enc select dout <= dout_enc when '1', dout_dec when others; With enc select data_rdy <= enc_rdy when '1', dec_rdy when others; --End structure End struct;
Library IEEE; Use IEEE.std_logic_1164.All; Use IEEE.std_logic_arith.All; Use IEEE.std_logic_unsigned.All; Use Work.RC5_pkg.All; Entity rc5_Struct is Port ( clr : in std_logic; clk : in std_logic; enc : in std_logic; key_vld : in std_logic; key : in std_logic_vector (127 downto 0); data_vld : in std_logic; din : in std_logic_vector (63 downto 0); dout : out std_logic_vector (63 downto 0); data_rdy : out std_logic ); End rc5_Struct; --Architecture Architecture struct of rc5_Struct is --Key Expansion Module Component rc5_rnd_key Port ( clr : in std_logic; clk : in std_logic; key_vld : in std_logic; key_in : in Std_logic_vector (127 downto 0); skey : out rom; key_rdy : out std_logic ); End Component; --Encryption Module Component rc5_enc Port ( clr : in std_logic; clk : in std_logic; din : in std_logic_vector(63 downto 0); di_vld : in std_logic; key_rdy : in std_logic; skey : in rom; dout : out std_logic_vector(63 downto 0); do_rdy : out std_logic ); End Component; --Decryption Module Component rc5_dec Port ( clr : In std_logic; clk : In std_logic; din : In std_logic_vector(63 downto 0); din_vld : In std_logic; key_rdy : In std_logic; skey : In rom; dout : Out std_logic_vector(63 downto 0); dout_rdy : Out std_logic ); End Component; --Signals Signal skey : rom; Signal key_rdy : std_logic; Signal dout_enc : std_logic_vector (63 downto 0); Signal dout_dec : std_logic_vector (63 downto 0); Signal enc_rdy : std_logic; Signal dec_rdy : std_logic; Signal i_cnt : std_logic_vector (3 downto 0); Begin --Port Maps U1 : rc5_rnd_key Port Map (clr => clr, clk => clk, key_in => key, key_vld => key_vld, skey => skey, key_rdy => key_rdy); U2 : rc5_enc Port Map (clr => clr, clk => clk, din => din, di_vld => key_rdy, skey => skey, dout => dout_enc, do_rdy => enc_rdy, key_rdy => key_rdy); U3 : rc5_dec Port Map (clr => clr, clk => clk, din => din, din_vld => key_rdy, skey => skey, dout => dout_dec, dout_rdy => dec_rdy, key_rdy => key_rdy); --Select With enc select dout <= dout_enc when '1', dout_dec when others; With enc select data_rdy <= enc_rdy when '1', dec_rdy when others; --End structure End struct;
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2014.3 (lin64) Build 1034051 Fri Oct 3 16:31:15 MDT 2014 -- Date : Sun Nov 2 20:42:29 2014 -- Host : ubuntu-imac running 64-bit Ubuntu 14.04.1 LTS -- Command : write_vhdl -force -mode funcsim -- /home/john/parallella-hw/fpga/projects/vivado_parallella_7010_headless/parallela_7010_headless/parallela_7010_headless.srcs/sources_1/ip/processing_system7_0/processing_system7_0_funcsim.vhdl -- Design : processing_system7_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity processing_system7_0_processing_system7_v5_5_processing_system7 is port ( CAN0_PHY_TX : out STD_LOGIC; CAN0_PHY_RX : in STD_LOGIC; CAN1_PHY_TX : out STD_LOGIC; CAN1_PHY_RX : in STD_LOGIC; ENET0_GMII_TX_EN : out STD_LOGIC; ENET0_GMII_TX_ER : out STD_LOGIC; ENET0_MDIO_MDC : out STD_LOGIC; ENET0_MDIO_O : out STD_LOGIC; ENET0_MDIO_T : out STD_LOGIC; ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET0_SOF_RX : out STD_LOGIC; ENET0_SOF_TX : out STD_LOGIC; ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET0_GMII_COL : in STD_LOGIC; ENET0_GMII_CRS : in STD_LOGIC; ENET0_GMII_RX_CLK : in STD_LOGIC; ENET0_GMII_RX_DV : in STD_LOGIC; ENET0_GMII_RX_ER : in STD_LOGIC; ENET0_GMII_TX_CLK : in STD_LOGIC; ENET0_MDIO_I : in STD_LOGIC; ENET0_EXT_INTIN : in STD_LOGIC; ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_TX_EN : out STD_LOGIC; ENET1_GMII_TX_ER : out STD_LOGIC; ENET1_MDIO_MDC : out STD_LOGIC; ENET1_MDIO_O : out STD_LOGIC; ENET1_MDIO_T : out STD_LOGIC; ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET1_SOF_RX : out STD_LOGIC; ENET1_SOF_TX : out STD_LOGIC; ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_COL : in STD_LOGIC; ENET1_GMII_CRS : in STD_LOGIC; ENET1_GMII_RX_CLK : in STD_LOGIC; ENET1_GMII_RX_DV : in STD_LOGIC; ENET1_GMII_RX_ER : in STD_LOGIC; ENET1_GMII_TX_CLK : in STD_LOGIC; ENET1_MDIO_I : in STD_LOGIC; ENET1_EXT_INTIN : in STD_LOGIC; ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); GPIO_I : in STD_LOGIC_VECTOR ( 47 downto 0 ); GPIO_O : out STD_LOGIC_VECTOR ( 47 downto 0 ); GPIO_T : out STD_LOGIC_VECTOR ( 47 downto 0 ); I2C0_SDA_I : in STD_LOGIC; I2C0_SDA_O : out STD_LOGIC; I2C0_SDA_T : out STD_LOGIC; I2C0_SCL_I : in STD_LOGIC; I2C0_SCL_O : out STD_LOGIC; I2C0_SCL_T : out STD_LOGIC; I2C1_SDA_I : in STD_LOGIC; I2C1_SDA_O : out STD_LOGIC; I2C1_SDA_T : out STD_LOGIC; I2C1_SCL_I : in STD_LOGIC; I2C1_SCL_O : out STD_LOGIC; I2C1_SCL_T : out STD_LOGIC; PJTAG_TCK : in STD_LOGIC; PJTAG_TMS : in STD_LOGIC; PJTAG_TDI : in STD_LOGIC; PJTAG_TDO : out STD_LOGIC; SDIO0_CLK : out STD_LOGIC; SDIO0_CLK_FB : in STD_LOGIC; SDIO0_CMD_O : out STD_LOGIC; SDIO0_CMD_I : in STD_LOGIC; SDIO0_CMD_T : out STD_LOGIC; SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_LED : out STD_LOGIC; SDIO0_CDN : in STD_LOGIC; SDIO0_WP : in STD_LOGIC; SDIO0_BUSPOW : out STD_LOGIC; SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SDIO1_CLK : out STD_LOGIC; SDIO1_CLK_FB : in STD_LOGIC; SDIO1_CMD_O : out STD_LOGIC; SDIO1_CMD_I : in STD_LOGIC; SDIO1_CMD_T : out STD_LOGIC; SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_LED : out STD_LOGIC; SDIO1_CDN : in STD_LOGIC; SDIO1_WP : in STD_LOGIC; SDIO1_BUSPOW : out STD_LOGIC; SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SPI0_SCLK_I : in STD_LOGIC; SPI0_SCLK_O : out STD_LOGIC; SPI0_SCLK_T : out STD_LOGIC; SPI0_MOSI_I : in STD_LOGIC; SPI0_MOSI_O : out STD_LOGIC; SPI0_MOSI_T : out STD_LOGIC; SPI0_MISO_I : in STD_LOGIC; SPI0_MISO_O : out STD_LOGIC; SPI0_MISO_T : out STD_LOGIC; SPI0_SS_I : in STD_LOGIC; SPI0_SS_O : out STD_LOGIC; SPI0_SS1_O : out STD_LOGIC; SPI0_SS2_O : out STD_LOGIC; SPI0_SS_T : out STD_LOGIC; SPI1_SCLK_I : in STD_LOGIC; SPI1_SCLK_O : out STD_LOGIC; SPI1_SCLK_T : out STD_LOGIC; SPI1_MOSI_I : in STD_LOGIC; SPI1_MOSI_O : out STD_LOGIC; SPI1_MOSI_T : out STD_LOGIC; SPI1_MISO_I : in STD_LOGIC; SPI1_MISO_O : out STD_LOGIC; SPI1_MISO_T : out STD_LOGIC; SPI1_SS_I : in STD_LOGIC; SPI1_SS_O : out STD_LOGIC; SPI1_SS1_O : out STD_LOGIC; SPI1_SS2_O : out STD_LOGIC; SPI1_SS_T : out STD_LOGIC; UART0_DTRN : out STD_LOGIC; UART0_RTSN : out STD_LOGIC; UART0_TX : out STD_LOGIC; UART0_CTSN : in STD_LOGIC; UART0_DCDN : in STD_LOGIC; UART0_DSRN : in STD_LOGIC; UART0_RIN : in STD_LOGIC; UART0_RX : in STD_LOGIC; UART1_DTRN : out STD_LOGIC; UART1_RTSN : out STD_LOGIC; UART1_TX : out STD_LOGIC; UART1_CTSN : in STD_LOGIC; UART1_DCDN : in STD_LOGIC; UART1_DSRN : in STD_LOGIC; UART1_RIN : in STD_LOGIC; UART1_RX : in STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; TTC0_CLK0_IN : in STD_LOGIC; TTC0_CLK1_IN : in STD_LOGIC; TTC0_CLK2_IN : in STD_LOGIC; TTC1_WAVE0_OUT : out STD_LOGIC; TTC1_WAVE1_OUT : out STD_LOGIC; TTC1_WAVE2_OUT : out STD_LOGIC; TTC1_CLK0_IN : in STD_LOGIC; TTC1_CLK1_IN : in STD_LOGIC; TTC1_CLK2_IN : in STD_LOGIC; WDT_CLK_IN : in STD_LOGIC; WDT_RST_OUT : out STD_LOGIC; TRACE_CLK : in STD_LOGIC; TRACE_CTL : out STD_LOGIC; TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 ); TRACE_CLK_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB1_VBUS_PWRSELECT : out STD_LOGIC; USB1_VBUS_PWRFAULT : in STD_LOGIC; SRAM_INTIN : in STD_LOGIC; M_AXI_GP0_ARESETN : out STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARESETN : out STD_LOGIC; M_AXI_GP1_ARVALID : out STD_LOGIC; M_AXI_GP1_AWVALID : out STD_LOGIC; M_AXI_GP1_BREADY : out STD_LOGIC; M_AXI_GP1_RREADY : out STD_LOGIC; M_AXI_GP1_WLAST : out STD_LOGIC; M_AXI_GP1_WVALID : out STD_LOGIC; M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ACLK : in STD_LOGIC; M_AXI_GP1_ARREADY : in STD_LOGIC; M_AXI_GP1_AWREADY : in STD_LOGIC; M_AXI_GP1_BVALID : in STD_LOGIC; M_AXI_GP1_RLAST : in STD_LOGIC; M_AXI_GP1_RVALID : in STD_LOGIC; M_AXI_GP1_WREADY : in STD_LOGIC; M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARESETN : out STD_LOGIC; S_AXI_GP0_ARREADY : out STD_LOGIC; S_AXI_GP0_AWREADY : out STD_LOGIC; S_AXI_GP0_BVALID : out STD_LOGIC; S_AXI_GP0_RLAST : out STD_LOGIC; S_AXI_GP0_RVALID : out STD_LOGIC; S_AXI_GP0_WREADY : out STD_LOGIC; S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_ACLK : in STD_LOGIC; S_AXI_GP0_ARVALID : in STD_LOGIC; S_AXI_GP0_AWVALID : in STD_LOGIC; S_AXI_GP0_BREADY : in STD_LOGIC; S_AXI_GP0_RREADY : in STD_LOGIC; S_AXI_GP0_WLAST : in STD_LOGIC; S_AXI_GP0_WVALID : in STD_LOGIC; S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ARESETN : out STD_LOGIC; S_AXI_GP1_ARREADY : out STD_LOGIC; S_AXI_GP1_AWREADY : out STD_LOGIC; S_AXI_GP1_BVALID : out STD_LOGIC; S_AXI_GP1_RLAST : out STD_LOGIC; S_AXI_GP1_RVALID : out STD_LOGIC; S_AXI_GP1_WREADY : out STD_LOGIC; S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ACLK : in STD_LOGIC; S_AXI_GP1_ARVALID : in STD_LOGIC; S_AXI_GP1_AWVALID : in STD_LOGIC; S_AXI_GP1_BREADY : in STD_LOGIC; S_AXI_GP1_RREADY : in STD_LOGIC; S_AXI_GP1_WLAST : in STD_LOGIC; S_AXI_GP1_WVALID : in STD_LOGIC; S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_ACP_ARESETN : out STD_LOGIC; S_AXI_ACP_ARREADY : out STD_LOGIC; S_AXI_ACP_AWREADY : out STD_LOGIC; S_AXI_ACP_BVALID : out STD_LOGIC; S_AXI_ACP_RLAST : out STD_LOGIC; S_AXI_ACP_RVALID : out STD_LOGIC; S_AXI_ACP_WREADY : out STD_LOGIC; S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_ACLK : in STD_LOGIC; S_AXI_ACP_ARVALID : in STD_LOGIC; S_AXI_ACP_AWVALID : in STD_LOGIC; S_AXI_ACP_BREADY : in STD_LOGIC; S_AXI_ACP_RREADY : in STD_LOGIC; S_AXI_ACP_WLAST : in STD_LOGIC; S_AXI_ACP_WVALID : in STD_LOGIC; S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_ARESETN : out STD_LOGIC; S_AXI_HP0_ARREADY : out STD_LOGIC; S_AXI_HP0_AWREADY : out STD_LOGIC; S_AXI_HP0_BVALID : out STD_LOGIC; S_AXI_HP0_RLAST : out STD_LOGIC; S_AXI_HP0_RVALID : out STD_LOGIC; S_AXI_HP0_WREADY : out STD_LOGIC; S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_ACLK : in STD_LOGIC; S_AXI_HP0_ARVALID : in STD_LOGIC; S_AXI_HP0_AWVALID : in STD_LOGIC; S_AXI_HP0_BREADY : in STD_LOGIC; S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_RREADY : in STD_LOGIC; S_AXI_HP0_WLAST : in STD_LOGIC; S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_WVALID : in STD_LOGIC; S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARESETN : out STD_LOGIC; S_AXI_HP1_ARREADY : out STD_LOGIC; S_AXI_HP1_AWREADY : out STD_LOGIC; S_AXI_HP1_BVALID : out STD_LOGIC; S_AXI_HP1_RLAST : out STD_LOGIC; S_AXI_HP1_RVALID : out STD_LOGIC; S_AXI_HP1_WREADY : out STD_LOGIC; S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_ACLK : in STD_LOGIC; S_AXI_HP1_ARVALID : in STD_LOGIC; S_AXI_HP1_AWVALID : in STD_LOGIC; S_AXI_HP1_BREADY : in STD_LOGIC; S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_RREADY : in STD_LOGIC; S_AXI_HP1_WLAST : in STD_LOGIC; S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_WVALID : in STD_LOGIC; S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_ARESETN : out STD_LOGIC; S_AXI_HP2_ARREADY : out STD_LOGIC; S_AXI_HP2_AWREADY : out STD_LOGIC; S_AXI_HP2_BVALID : out STD_LOGIC; S_AXI_HP2_RLAST : out STD_LOGIC; S_AXI_HP2_RVALID : out STD_LOGIC; S_AXI_HP2_WREADY : out STD_LOGIC; S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_ACLK : in STD_LOGIC; S_AXI_HP2_ARVALID : in STD_LOGIC; S_AXI_HP2_AWVALID : in STD_LOGIC; S_AXI_HP2_BREADY : in STD_LOGIC; S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_RREADY : in STD_LOGIC; S_AXI_HP2_WLAST : in STD_LOGIC; S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_WVALID : in STD_LOGIC; S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_ARESETN : out STD_LOGIC; S_AXI_HP3_ARREADY : out STD_LOGIC; S_AXI_HP3_AWREADY : out STD_LOGIC; S_AXI_HP3_BVALID : out STD_LOGIC; S_AXI_HP3_RLAST : out STD_LOGIC; S_AXI_HP3_RVALID : out STD_LOGIC; S_AXI_HP3_WREADY : out STD_LOGIC; S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_ACLK : in STD_LOGIC; S_AXI_HP3_ARVALID : in STD_LOGIC; S_AXI_HP3_AWVALID : in STD_LOGIC; S_AXI_HP3_BREADY : in STD_LOGIC; S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_RREADY : in STD_LOGIC; S_AXI_HP3_WLAST : in STD_LOGIC; S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_WVALID : in STD_LOGIC; S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); IRQ_P2F_DMAC_ABORT : out STD_LOGIC; IRQ_P2F_DMAC0 : out STD_LOGIC; IRQ_P2F_DMAC1 : out STD_LOGIC; IRQ_P2F_DMAC2 : out STD_LOGIC; IRQ_P2F_DMAC3 : out STD_LOGIC; IRQ_P2F_DMAC4 : out STD_LOGIC; IRQ_P2F_DMAC5 : out STD_LOGIC; IRQ_P2F_DMAC6 : out STD_LOGIC; IRQ_P2F_DMAC7 : out STD_LOGIC; IRQ_P2F_SMC : out STD_LOGIC; IRQ_P2F_QSPI : out STD_LOGIC; IRQ_P2F_CTI : out STD_LOGIC; IRQ_P2F_GPIO : out STD_LOGIC; IRQ_P2F_USB0 : out STD_LOGIC; IRQ_P2F_ENET0 : out STD_LOGIC; IRQ_P2F_ENET_WAKE0 : out STD_LOGIC; IRQ_P2F_SDIO0 : out STD_LOGIC; IRQ_P2F_I2C0 : out STD_LOGIC; IRQ_P2F_SPI0 : out STD_LOGIC; IRQ_P2F_UART0 : out STD_LOGIC; IRQ_P2F_CAN0 : out STD_LOGIC; IRQ_P2F_USB1 : out STD_LOGIC; IRQ_P2F_ENET1 : out STD_LOGIC; IRQ_P2F_ENET_WAKE1 : out STD_LOGIC; IRQ_P2F_SDIO1 : out STD_LOGIC; IRQ_P2F_I2C1 : out STD_LOGIC; IRQ_P2F_SPI1 : out STD_LOGIC; IRQ_P2F_UART1 : out STD_LOGIC; IRQ_P2F_CAN1 : out STD_LOGIC; IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 ); Core0_nFIQ : in STD_LOGIC; Core0_nIRQ : in STD_LOGIC; Core1_nFIQ : in STD_LOGIC; Core1_nIRQ : in STD_LOGIC; DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA0_DAVALID : out STD_LOGIC; DMA0_DRREADY : out STD_LOGIC; DMA0_RSTN : out STD_LOGIC; DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DAVALID : out STD_LOGIC; DMA1_DRREADY : out STD_LOGIC; DMA1_RSTN : out STD_LOGIC; DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DAVALID : out STD_LOGIC; DMA2_DRREADY : out STD_LOGIC; DMA2_RSTN : out STD_LOGIC; DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DAVALID : out STD_LOGIC; DMA3_DRREADY : out STD_LOGIC; DMA3_RSTN : out STD_LOGIC; DMA0_ACLK : in STD_LOGIC; DMA0_DAREADY : in STD_LOGIC; DMA0_DRLAST : in STD_LOGIC; DMA0_DRVALID : in STD_LOGIC; DMA1_ACLK : in STD_LOGIC; DMA1_DAREADY : in STD_LOGIC; DMA1_DRLAST : in STD_LOGIC; DMA1_DRVALID : in STD_LOGIC; DMA2_ACLK : in STD_LOGIC; DMA2_DAREADY : in STD_LOGIC; DMA2_DRLAST : in STD_LOGIC; DMA2_DRVALID : in STD_LOGIC; DMA3_ACLK : in STD_LOGIC; DMA3_DAREADY : in STD_LOGIC; DMA3_DRLAST : in STD_LOGIC; DMA3_DRVALID : in STD_LOGIC; DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); FCLK_CLK3 : out STD_LOGIC; FCLK_CLK2 : out STD_LOGIC; FCLK_CLK1 : out STD_LOGIC; FCLK_CLK0 : out STD_LOGIC; FCLK_CLKTRIG3_N : in STD_LOGIC; FCLK_CLKTRIG2_N : in STD_LOGIC; FCLK_CLKTRIG1_N : in STD_LOGIC; FCLK_CLKTRIG0_N : in STD_LOGIC; FCLK_RESET3_N : out STD_LOGIC; FCLK_RESET2_N : out STD_LOGIC; FCLK_RESET1_N : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMD_TRACEIN_VALID : in STD_LOGIC; FTMD_TRACEIN_CLK : in STD_LOGIC; FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 ); FTMT_F2P_TRIG_0 : in STD_LOGIC; FTMT_F2P_TRIGACK_0 : out STD_LOGIC; FTMT_F2P_TRIG_1 : in STD_LOGIC; FTMT_F2P_TRIGACK_1 : out STD_LOGIC; FTMT_F2P_TRIG_2 : in STD_LOGIC; FTMT_F2P_TRIGACK_2 : out STD_LOGIC; FTMT_F2P_TRIG_3 : in STD_LOGIC; FTMT_F2P_TRIGACK_3 : out STD_LOGIC; FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMT_P2F_TRIGACK_0 : in STD_LOGIC; FTMT_P2F_TRIG_0 : out STD_LOGIC; FTMT_P2F_TRIGACK_1 : in STD_LOGIC; FTMT_P2F_TRIG_1 : out STD_LOGIC; FTMT_P2F_TRIGACK_2 : in STD_LOGIC; FTMT_P2F_TRIG_2 : out STD_LOGIC; FTMT_P2F_TRIGACK_3 : in STD_LOGIC; FTMT_P2F_TRIG_3 : out STD_LOGIC; FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 ); FPGA_IDLE_N : in STD_LOGIC; EVENT_EVENTO : out STD_LOGIC; EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_EVENTI : in STD_LOGIC; DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 ); MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute POWER : string; attribute POWER of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1600.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP1} dataWidth={64} clockFreq={10} usageRate={0.5} /><AXI interface={M_AXI_GP1} dataWidth={32} clockFreq={10} usageRate={0.5} />/>"; attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=400, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=9, PCW_UIPARAM_DDR_CWL=9, PCW_UIPARAM_DDR_T_RCD=9, PCW_UIPARAM_DDR_T_RP=9, PCW_UIPARAM_DDR_T_RC=60, PCW_UIPARAM_DDR_T_RAS_MIN=40, PCW_UIPARAM_DDR_T_FAW=50, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.315, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.391, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.374, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.271, PCW_UIPARAM_DDR_BOARD_DELAY0=0.434, PCW_UIPARAM_DDR_BOARD_DELAY1=0.398, PCW_UIPARAM_DDR_BOARD_DELAY2=0.41, PCW_UIPARAM_DDR_BOARD_DELAY3=0.455, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=200.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=200.000000, PCW_FPGA3_PERIPHERAL_FREQMHZ=40.000000, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=48, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1600.000, PCW_USE_M_AXI_GP0=0, PCW_USE_M_AXI_GP1=1, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=1, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=10, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=32, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3 (Low Voltage), PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=Custom, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=1, PCW_SD1_SD1_IO=MIO 10 .. 15, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 8 .. 9, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=1, PCW_USB1_USB1_IO=MIO 40 .. 51, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=1, PCW_GPIO_MIO_GPIO_ENABLE=0, PCW_GPIO_EMIO_GPIO_ENABLE=1, PCW_GPIO_EMIO_GPIO_IO=48, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=1, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }"; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 3; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 32; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "true"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "false"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "false"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "true"; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 48; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 128; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 12; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 8; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION"; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 32; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 54; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "clg400"; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT"; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 2; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7"; end processing_system7_0_processing_system7_v5_5_processing_system7; architecture STRUCTURE of processing_system7_0_processing_system7_v5_5_processing_system7 is signal \<const0>\ : STD_LOGIC; signal ENET0_MDIO_T_n : STD_LOGIC; signal ENET1_MDIO_T_n : STD_LOGIC; signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 3 downto 0 ); signal I2C0_SCL_T_n : STD_LOGIC; signal I2C0_SDA_T_n : STD_LOGIC; signal I2C1_SCL_T_n : STD_LOGIC; signal I2C1_SDA_T_n : STD_LOGIC; signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal SDIO0_CMD_T_n : STD_LOGIC; signal SDIO1_CMD_T_n : STD_LOGIC; signal SPI0_MISO_T_n : STD_LOGIC; signal SPI0_MOSI_T_n : STD_LOGIC; signal SPI0_SCLK_T_n : STD_LOGIC; signal SPI0_SS_T_n : STD_LOGIC; signal SPI1_MISO_T_n : STD_LOGIC; signal SPI1_MOSI_T_n : STD_LOGIC; signal SPI1_SCLK_T_n : STD_LOGIC; signal SPI1_SS_T_n : STD_LOGIC; signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 ); signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal buffered_DDR_CAS_n : STD_LOGIC; signal buffered_DDR_CKE : STD_LOGIC; signal buffered_DDR_CS_n : STD_LOGIC; signal buffered_DDR_Clk : STD_LOGIC; signal buffered_DDR_Clk_n : STD_LOGIC; signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DRSTB : STD_LOGIC; signal buffered_DDR_ODT : STD_LOGIC; signal buffered_DDR_RAS_n : STD_LOGIC; signal buffered_DDR_VRN : STD_LOGIC; signal buffered_DDR_VRP : STD_LOGIC; signal buffered_DDR_WEB : STD_LOGIC; signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); signal buffered_PS_CLK : STD_LOGIC; signal buffered_PS_PORB : STD_LOGIC; signal buffered_PS_SRSTB : STD_LOGIC; signal n_1000_PS7_i : STD_LOGIC; signal n_701_PS7_i : STD_LOGIC; signal n_702_PS7_i : STD_LOGIC; signal n_703_PS7_i : STD_LOGIC; signal n_704_PS7_i : STD_LOGIC; signal n_953_PS7_i : STD_LOGIC; signal n_954_PS7_i : STD_LOGIC; signal n_955_PS7_i : STD_LOGIC; signal n_956_PS7_i : STD_LOGIC; signal n_957_PS7_i : STD_LOGIC; signal n_958_PS7_i : STD_LOGIC; signal n_959_PS7_i : STD_LOGIC; signal n_960_PS7_i : STD_LOGIC; signal n_961_PS7_i : STD_LOGIC; signal n_962_PS7_i : STD_LOGIC; signal n_963_PS7_i : STD_LOGIC; signal n_964_PS7_i : STD_LOGIC; signal n_965_PS7_i : STD_LOGIC; signal n_966_PS7_i : STD_LOGIC; signal n_967_PS7_i : STD_LOGIC; signal n_968_PS7_i : STD_LOGIC; signal n_969_PS7_i : STD_LOGIC; signal n_970_PS7_i : STD_LOGIC; signal n_971_PS7_i : STD_LOGIC; signal n_972_PS7_i : STD_LOGIC; signal n_973_PS7_i : STD_LOGIC; signal n_974_PS7_i : STD_LOGIC; signal n_975_PS7_i : STD_LOGIC; signal n_976_PS7_i : STD_LOGIC; signal n_977_PS7_i : STD_LOGIC; signal n_978_PS7_i : STD_LOGIC; signal n_979_PS7_i : STD_LOGIC; signal n_980_PS7_i : STD_LOGIC; signal n_981_PS7_i : STD_LOGIC; signal n_982_PS7_i : STD_LOGIC; signal n_983_PS7_i : STD_LOGIC; signal n_984_PS7_i : STD_LOGIC; signal n_985_PS7_i : STD_LOGIC; signal n_986_PS7_i : STD_LOGIC; signal n_987_PS7_i : STD_LOGIC; signal n_988_PS7_i : STD_LOGIC; signal n_989_PS7_i : STD_LOGIC; signal n_990_PS7_i : STD_LOGIC; signal n_991_PS7_i : STD_LOGIC; signal n_992_PS7_i : STD_LOGIC; signal n_993_PS7_i : STD_LOGIC; signal n_994_PS7_i : STD_LOGIC; signal n_995_PS7_i : STD_LOGIC; signal n_996_PS7_i : STD_LOGIC; signal n_997_PS7_i : STD_LOGIC; signal n_998_PS7_i : STD_LOGIC; signal n_999_PS7_i : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOGPIOO_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 48 ); signal NLW_PS7_i_EMIOGPIOTN_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 48 ); signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_PS7_i_SAXIHP0RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 32 ); attribute BOX_TYPE : string; attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS7_i : label is "PRIMITIVE"; attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE"; attribute BOX_TYPE of \buffer_fclk_clk_3.FCLK_CLK_3_BUFG\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; begin ENET0_GMII_TXD(7) <= \<const0>\; ENET0_GMII_TXD(6) <= \<const0>\; ENET0_GMII_TXD(5) <= \<const0>\; ENET0_GMII_TXD(4) <= \<const0>\; ENET0_GMII_TXD(3) <= \<const0>\; ENET0_GMII_TXD(2) <= \<const0>\; ENET0_GMII_TXD(1) <= \<const0>\; ENET0_GMII_TXD(0) <= \<const0>\; ENET0_GMII_TX_EN <= \<const0>\; ENET0_GMII_TX_ER <= \<const0>\; ENET1_GMII_TXD(7) <= \<const0>\; ENET1_GMII_TXD(6) <= \<const0>\; ENET1_GMII_TXD(5) <= \<const0>\; ENET1_GMII_TXD(4) <= \<const0>\; ENET1_GMII_TXD(3) <= \<const0>\; ENET1_GMII_TXD(2) <= \<const0>\; ENET1_GMII_TXD(1) <= \<const0>\; ENET1_GMII_TXD(0) <= \<const0>\; ENET1_GMII_TX_EN <= \<const0>\; ENET1_GMII_TX_ER <= \<const0>\; M_AXI_GP0_ARSIZE(2) <= \<const0>\; M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0); M_AXI_GP0_AWSIZE(2) <= \<const0>\; M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0); M_AXI_GP1_ARSIZE(2) <= \<const0>\; M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0); M_AXI_GP1_AWSIZE(2) <= \<const0>\; M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0); PJTAG_TDO <= \<const0>\; TRACE_CLK_OUT <= \<const0>\; TRACE_CTL <= \<const0>\; TRACE_DATA(1) <= \<const0>\; TRACE_DATA(0) <= \<const0>\; DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CAS_n, PAD => DDR_CAS_n ); DDR_CKE_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CKE, PAD => DDR_CKE ); DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CS_n, PAD => DDR_CS_n ); DDR_Clk_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk, PAD => DDR_Clk ); DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk_n, PAD => DDR_Clk_n ); DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DRSTB, PAD => DDR_DRSTB ); DDR_ODT_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_ODT, PAD => DDR_ODT ); DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_RAS_n, PAD => DDR_RAS_n ); DDR_VRN_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRN, PAD => DDR_VRN ); DDR_VRP_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRP, PAD => DDR_VRP ); DDR_WEB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_WEB, PAD => DDR_WEB ); ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET0_MDIO_T_n, O => ENET0_MDIO_T ); ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET1_MDIO_T_n, O => ENET1_MDIO_T ); GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_1000_PS7_i, O => GPIO_T(0) ); \GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_990_PS7_i, O => GPIO_T(10) ); \GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_989_PS7_i, O => GPIO_T(11) ); \GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_988_PS7_i, O => GPIO_T(12) ); \GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_987_PS7_i, O => GPIO_T(13) ); \GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_986_PS7_i, O => GPIO_T(14) ); \GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_985_PS7_i, O => GPIO_T(15) ); \GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_984_PS7_i, O => GPIO_T(16) ); \GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_983_PS7_i, O => GPIO_T(17) ); \GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_982_PS7_i, O => GPIO_T(18) ); \GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_981_PS7_i, O => GPIO_T(19) ); \GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_999_PS7_i, O => GPIO_T(1) ); \GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_980_PS7_i, O => GPIO_T(20) ); \GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_979_PS7_i, O => GPIO_T(21) ); \GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_978_PS7_i, O => GPIO_T(22) ); \GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_977_PS7_i, O => GPIO_T(23) ); \GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_976_PS7_i, O => GPIO_T(24) ); \GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_975_PS7_i, O => GPIO_T(25) ); \GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_974_PS7_i, O => GPIO_T(26) ); \GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_973_PS7_i, O => GPIO_T(27) ); \GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_972_PS7_i, O => GPIO_T(28) ); \GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_971_PS7_i, O => GPIO_T(29) ); \GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_998_PS7_i, O => GPIO_T(2) ); \GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_970_PS7_i, O => GPIO_T(30) ); \GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_969_PS7_i, O => GPIO_T(31) ); \GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_968_PS7_i, O => GPIO_T(32) ); \GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_967_PS7_i, O => GPIO_T(33) ); \GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_966_PS7_i, O => GPIO_T(34) ); \GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_965_PS7_i, O => GPIO_T(35) ); \GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_964_PS7_i, O => GPIO_T(36) ); \GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_963_PS7_i, O => GPIO_T(37) ); \GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_962_PS7_i, O => GPIO_T(38) ); \GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_961_PS7_i, O => GPIO_T(39) ); \GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_997_PS7_i, O => GPIO_T(3) ); \GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_960_PS7_i, O => GPIO_T(40) ); \GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_959_PS7_i, O => GPIO_T(41) ); \GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_958_PS7_i, O => GPIO_T(42) ); \GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_957_PS7_i, O => GPIO_T(43) ); \GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_956_PS7_i, O => GPIO_T(44) ); \GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_955_PS7_i, O => GPIO_T(45) ); \GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_954_PS7_i, O => GPIO_T(46) ); \GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_953_PS7_i, O => GPIO_T(47) ); \GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_996_PS7_i, O => GPIO_T(4) ); \GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_995_PS7_i, O => GPIO_T(5) ); \GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_994_PS7_i, O => GPIO_T(6) ); \GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_993_PS7_i, O => GPIO_T(7) ); \GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_992_PS7_i, O => GPIO_T(8) ); \GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_991_PS7_i, O => GPIO_T(9) ); I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SCL_T_n, O => I2C0_SCL_T ); I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SDA_T_n, O => I2C0_SDA_T ); I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SCL_T_n, O => I2C1_SCL_T ); I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SDA_T_n, O => I2C1_SDA_T ); PS7_i: unisim.vcomponents.PS7 port map ( DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0), DDRARB(3 downto 0) => DDR_ARB(3 downto 0), DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0), DDRCASB => buffered_DDR_CAS_n, DDRCKE => buffered_DDR_CKE, DDRCKN => buffered_DDR_Clk_n, DDRCKP => buffered_DDR_Clk, DDRCSB => buffered_DDR_CS_n, DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0), DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0), DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0), DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0), DDRDRSTB => buffered_DDR_DRSTB, DDRODT => buffered_DDR_ODT, DDRRASB => buffered_DDR_RAS_n, DDRVRN => buffered_DDR_VRN, DDRVRP => buffered_DDR_VRP, DDRWEB => buffered_DDR_WEB, DMA0ACLK => DMA0_ACLK, DMA0DAREADY => DMA0_DAREADY, DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0), DMA0DAVALID => DMA0_DAVALID, DMA0DRLAST => DMA0_DRLAST, DMA0DRREADY => DMA0_DRREADY, DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0), DMA0DRVALID => DMA0_DRVALID, DMA0RSTN => DMA0_RSTN, DMA1ACLK => DMA1_ACLK, DMA1DAREADY => DMA1_DAREADY, DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0), DMA1DAVALID => DMA1_DAVALID, DMA1DRLAST => DMA1_DRLAST, DMA1DRREADY => DMA1_DRREADY, DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0), DMA1DRVALID => DMA1_DRVALID, DMA1RSTN => DMA1_RSTN, DMA2ACLK => DMA2_ACLK, DMA2DAREADY => DMA2_DAREADY, DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0), DMA2DAVALID => DMA2_DAVALID, DMA2DRLAST => DMA2_DRLAST, DMA2DRREADY => DMA2_DRREADY, DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0), DMA2DRVALID => DMA2_DRVALID, DMA2RSTN => DMA2_RSTN, DMA3ACLK => DMA3_ACLK, DMA3DAREADY => DMA3_DAREADY, DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0), DMA3DAVALID => DMA3_DAVALID, DMA3DRLAST => DMA3_DRLAST, DMA3DRREADY => DMA3_DRREADY, DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0), DMA3DRVALID => DMA3_DRVALID, DMA3RSTN => DMA3_RSTN, EMIOCAN0PHYRX => CAN0_PHY_RX, EMIOCAN0PHYTX => CAN0_PHY_TX, EMIOCAN1PHYRX => CAN1_PHY_RX, EMIOCAN1PHYTX => CAN1_PHY_TX, EMIOENET0EXTINTIN => ENET0_EXT_INTIN, EMIOENET0GMIICOL => '0', EMIOENET0GMIICRS => '0', EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK, EMIOENET0GMIIRXD(7) => '0', EMIOENET0GMIIRXD(6) => '0', EMIOENET0GMIIRXD(5) => '0', EMIOENET0GMIIRXD(4) => '0', EMIOENET0GMIIRXD(3) => '0', EMIOENET0GMIIRXD(2) => '0', EMIOENET0GMIIRXD(1) => '0', EMIOENET0GMIIRXD(0) => '0', EMIOENET0GMIIRXDV => '0', EMIOENET0GMIIRXER => '0', EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK, EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0), EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED, EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED, EMIOENET0MDIOI => ENET0_MDIO_I, EMIOENET0MDIOMDC => ENET0_MDIO_MDC, EMIOENET0MDIOO => ENET0_MDIO_O, EMIOENET0MDIOTN => ENET0_MDIO_T_n, EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX, EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX, EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX, EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX, EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX, EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX, EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX, EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX, EMIOENET0SOFRX => ENET0_SOF_RX, EMIOENET0SOFTX => ENET0_SOF_TX, EMIOENET1EXTINTIN => ENET1_EXT_INTIN, EMIOENET1GMIICOL => '0', EMIOENET1GMIICRS => '0', EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK, EMIOENET1GMIIRXD(7) => '0', EMIOENET1GMIIRXD(6) => '0', EMIOENET1GMIIRXD(5) => '0', EMIOENET1GMIIRXD(4) => '0', EMIOENET1GMIIRXD(3) => '0', EMIOENET1GMIIRXD(2) => '0', EMIOENET1GMIIRXD(1) => '0', EMIOENET1GMIIRXD(0) => '0', EMIOENET1GMIIRXDV => '0', EMIOENET1GMIIRXER => '0', EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK, EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0), EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED, EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED, EMIOENET1MDIOI => ENET1_MDIO_I, EMIOENET1MDIOMDC => ENET1_MDIO_MDC, EMIOENET1MDIOO => ENET1_MDIO_O, EMIOENET1MDIOTN => ENET1_MDIO_T_n, EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX, EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX, EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX, EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX, EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX, EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX, EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX, EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX, EMIOENET1SOFRX => ENET1_SOF_RX, EMIOENET1SOFTX => ENET1_SOF_TX, EMIOGPIOI(63) => \<const0>\, EMIOGPIOI(62) => \<const0>\, EMIOGPIOI(61) => \<const0>\, EMIOGPIOI(60) => \<const0>\, EMIOGPIOI(59) => \<const0>\, EMIOGPIOI(58) => \<const0>\, EMIOGPIOI(57) => \<const0>\, EMIOGPIOI(56) => \<const0>\, EMIOGPIOI(55) => \<const0>\, EMIOGPIOI(54) => \<const0>\, EMIOGPIOI(53) => \<const0>\, EMIOGPIOI(52) => \<const0>\, EMIOGPIOI(51) => \<const0>\, EMIOGPIOI(50) => \<const0>\, EMIOGPIOI(49) => \<const0>\, EMIOGPIOI(48) => \<const0>\, EMIOGPIOI(47 downto 0) => GPIO_I(47 downto 0), EMIOGPIOO(63 downto 48) => NLW_PS7_i_EMIOGPIOO_UNCONNECTED(63 downto 48), EMIOGPIOO(47 downto 0) => GPIO_O(47 downto 0), EMIOGPIOTN(63 downto 48) => NLW_PS7_i_EMIOGPIOTN_UNCONNECTED(63 downto 48), EMIOGPIOTN(47) => n_953_PS7_i, EMIOGPIOTN(46) => n_954_PS7_i, EMIOGPIOTN(45) => n_955_PS7_i, EMIOGPIOTN(44) => n_956_PS7_i, EMIOGPIOTN(43) => n_957_PS7_i, EMIOGPIOTN(42) => n_958_PS7_i, EMIOGPIOTN(41) => n_959_PS7_i, EMIOGPIOTN(40) => n_960_PS7_i, EMIOGPIOTN(39) => n_961_PS7_i, EMIOGPIOTN(38) => n_962_PS7_i, EMIOGPIOTN(37) => n_963_PS7_i, EMIOGPIOTN(36) => n_964_PS7_i, EMIOGPIOTN(35) => n_965_PS7_i, EMIOGPIOTN(34) => n_966_PS7_i, EMIOGPIOTN(33) => n_967_PS7_i, EMIOGPIOTN(32) => n_968_PS7_i, EMIOGPIOTN(31) => n_969_PS7_i, EMIOGPIOTN(30) => n_970_PS7_i, EMIOGPIOTN(29) => n_971_PS7_i, EMIOGPIOTN(28) => n_972_PS7_i, EMIOGPIOTN(27) => n_973_PS7_i, EMIOGPIOTN(26) => n_974_PS7_i, EMIOGPIOTN(25) => n_975_PS7_i, EMIOGPIOTN(24) => n_976_PS7_i, EMIOGPIOTN(23) => n_977_PS7_i, EMIOGPIOTN(22) => n_978_PS7_i, EMIOGPIOTN(21) => n_979_PS7_i, EMIOGPIOTN(20) => n_980_PS7_i, EMIOGPIOTN(19) => n_981_PS7_i, EMIOGPIOTN(18) => n_982_PS7_i, EMIOGPIOTN(17) => n_983_PS7_i, EMIOGPIOTN(16) => n_984_PS7_i, EMIOGPIOTN(15) => n_985_PS7_i, EMIOGPIOTN(14) => n_986_PS7_i, EMIOGPIOTN(13) => n_987_PS7_i, EMIOGPIOTN(12) => n_988_PS7_i, EMIOGPIOTN(11) => n_989_PS7_i, EMIOGPIOTN(10) => n_990_PS7_i, EMIOGPIOTN(9) => n_991_PS7_i, EMIOGPIOTN(8) => n_992_PS7_i, EMIOGPIOTN(7) => n_993_PS7_i, EMIOGPIOTN(6) => n_994_PS7_i, EMIOGPIOTN(5) => n_995_PS7_i, EMIOGPIOTN(4) => n_996_PS7_i, EMIOGPIOTN(3) => n_997_PS7_i, EMIOGPIOTN(2) => n_998_PS7_i, EMIOGPIOTN(1) => n_999_PS7_i, EMIOGPIOTN(0) => n_1000_PS7_i, EMIOI2C0SCLI => I2C0_SCL_I, EMIOI2C0SCLO => I2C0_SCL_O, EMIOI2C0SCLTN => I2C0_SCL_T_n, EMIOI2C0SDAI => I2C0_SDA_I, EMIOI2C0SDAO => I2C0_SDA_O, EMIOI2C0SDATN => I2C0_SDA_T_n, EMIOI2C1SCLI => I2C1_SCL_I, EMIOI2C1SCLO => I2C1_SCL_O, EMIOI2C1SCLTN => I2C1_SCL_T_n, EMIOI2C1SDAI => I2C1_SDA_I, EMIOI2C1SDAO => I2C1_SDA_O, EMIOI2C1SDATN => I2C1_SDA_T_n, EMIOPJTAGTCK => PJTAG_TCK, EMIOPJTAGTDI => PJTAG_TDI, EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED, EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED, EMIOPJTAGTMS => PJTAG_TMS, EMIOSDIO0BUSPOW => SDIO0_BUSPOW, EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0), EMIOSDIO0CDN => SDIO0_CDN, EMIOSDIO0CLK => SDIO0_CLK, EMIOSDIO0CLKFB => SDIO0_CLK_FB, EMIOSDIO0CMDI => SDIO0_CMD_I, EMIOSDIO0CMDO => SDIO0_CMD_O, EMIOSDIO0CMDTN => SDIO0_CMD_T_n, EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0), EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0), EMIOSDIO0DATATN(3 downto 0) => p_0_in(3 downto 0), EMIOSDIO0LED => SDIO0_LED, EMIOSDIO0WP => SDIO0_WP, EMIOSDIO1BUSPOW => SDIO1_BUSPOW, EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0), EMIOSDIO1CDN => SDIO1_CDN, EMIOSDIO1CLK => SDIO1_CLK, EMIOSDIO1CLKFB => SDIO1_CLK_FB, EMIOSDIO1CMDI => SDIO1_CMD_I, EMIOSDIO1CMDO => SDIO1_CMD_O, EMIOSDIO1CMDTN => SDIO1_CMD_T_n, EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0), EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0), EMIOSDIO1DATATN(3) => n_701_PS7_i, EMIOSDIO1DATATN(2) => n_702_PS7_i, EMIOSDIO1DATATN(1) => n_703_PS7_i, EMIOSDIO1DATATN(0) => n_704_PS7_i, EMIOSDIO1LED => SDIO1_LED, EMIOSDIO1WP => SDIO1_WP, EMIOSPI0MI => SPI0_MISO_I, EMIOSPI0MO => SPI0_MOSI_O, EMIOSPI0MOTN => SPI0_MOSI_T_n, EMIOSPI0SCLKI => SPI0_SCLK_I, EMIOSPI0SCLKO => SPI0_SCLK_O, EMIOSPI0SCLKTN => SPI0_SCLK_T_n, EMIOSPI0SI => SPI0_MOSI_I, EMIOSPI0SO => SPI0_MISO_O, EMIOSPI0SSIN => SPI0_SS_I, EMIOSPI0SSNTN => SPI0_SS_T_n, EMIOSPI0SSON(2) => SPI0_SS2_O, EMIOSPI0SSON(1) => SPI0_SS1_O, EMIOSPI0SSON(0) => SPI0_SS_O, EMIOSPI0STN => SPI0_MISO_T_n, EMIOSPI1MI => SPI1_MISO_I, EMIOSPI1MO => SPI1_MOSI_O, EMIOSPI1MOTN => SPI1_MOSI_T_n, EMIOSPI1SCLKI => SPI1_SCLK_I, EMIOSPI1SCLKO => SPI1_SCLK_O, EMIOSPI1SCLKTN => SPI1_SCLK_T_n, EMIOSPI1SI => SPI1_MOSI_I, EMIOSPI1SO => SPI1_MISO_O, EMIOSPI1SSIN => SPI1_SS_I, EMIOSPI1SSNTN => SPI1_SS_T_n, EMIOSPI1SSON(2) => SPI1_SS2_O, EMIOSPI1SSON(1) => SPI1_SS1_O, EMIOSPI1SSON(0) => SPI1_SS_O, EMIOSPI1STN => SPI1_MISO_T_n, EMIOSRAMINTIN => SRAM_INTIN, EMIOTRACECLK => TRACE_CLK, EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED, EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0), EMIOTTC0CLKI(2) => TTC0_CLK2_IN, EMIOTTC0CLKI(1) => TTC0_CLK1_IN, EMIOTTC0CLKI(0) => TTC0_CLK0_IN, EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT, EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT, EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT, EMIOTTC1CLKI(2) => TTC1_CLK2_IN, EMIOTTC1CLKI(1) => TTC1_CLK1_IN, EMIOTTC1CLKI(0) => TTC1_CLK0_IN, EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT, EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT, EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT, EMIOUART0CTSN => UART0_CTSN, EMIOUART0DCDN => UART0_DCDN, EMIOUART0DSRN => UART0_DSRN, EMIOUART0DTRN => UART0_DTRN, EMIOUART0RIN => UART0_RIN, EMIOUART0RTSN => UART0_RTSN, EMIOUART0RX => UART0_RX, EMIOUART0TX => UART0_TX, EMIOUART1CTSN => UART1_CTSN, EMIOUART1DCDN => UART1_DCDN, EMIOUART1DSRN => UART1_DSRN, EMIOUART1DTRN => UART1_DTRN, EMIOUART1RIN => UART1_RIN, EMIOUART1RTSN => UART1_RTSN, EMIOUART1RX => UART1_RX, EMIOUART1TX => UART1_TX, EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT, EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT, EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0), EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT, EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT, EMIOWDTCLKI => WDT_CLK_IN, EMIOWDTRSTO => WDT_RST_OUT, EVENTEVENTI => EVENT_EVENTI, EVENTEVENTO => EVENT_EVENTO, EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0), EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0), FCLKCLK(3) => FCLK_CLK_unbuffered(3), FCLKCLK(2) => FCLK_CLK2, FCLKCLK(1) => FCLK_CLK1, FCLKCLK(0) => FCLK_CLK_unbuffered(0), FCLKCLKTRIGN(3) => \<const0>\, FCLKCLKTRIGN(2) => \<const0>\, FCLKCLKTRIGN(1) => \<const0>\, FCLKCLKTRIGN(0) => \<const0>\, FCLKRESETN(3) => FCLK_RESET3_N, FCLKRESETN(2) => FCLK_RESET2_N, FCLKRESETN(1) => FCLK_RESET1_N, FCLKRESETN(0) => FCLK_RESET0_N, FPGAIDLEN => FPGA_IDLE_N, FTMDTRACEINATID(3) => '0', FTMDTRACEINATID(2) => '0', FTMDTRACEINATID(1) => '0', FTMDTRACEINATID(0) => '0', FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK, FTMDTRACEINDATA(31) => '0', FTMDTRACEINDATA(30) => '0', FTMDTRACEINDATA(29) => '0', FTMDTRACEINDATA(28) => '0', FTMDTRACEINDATA(27) => '0', FTMDTRACEINDATA(26) => '0', FTMDTRACEINDATA(25) => '0', FTMDTRACEINDATA(24) => '0', FTMDTRACEINDATA(23) => '0', FTMDTRACEINDATA(22) => '0', FTMDTRACEINDATA(21) => '0', FTMDTRACEINDATA(20) => '0', FTMDTRACEINDATA(19) => '0', FTMDTRACEINDATA(18) => '0', FTMDTRACEINDATA(17) => '0', FTMDTRACEINDATA(16) => '0', FTMDTRACEINDATA(15) => '0', FTMDTRACEINDATA(14) => '0', FTMDTRACEINDATA(13) => '0', FTMDTRACEINDATA(12) => '0', FTMDTRACEINDATA(11) => '0', FTMDTRACEINDATA(10) => '0', FTMDTRACEINDATA(9) => '0', FTMDTRACEINDATA(8) => '0', FTMDTRACEINDATA(7) => '0', FTMDTRACEINDATA(6) => '0', FTMDTRACEINDATA(5) => '0', FTMDTRACEINDATA(4) => '0', FTMDTRACEINDATA(3) => '0', FTMDTRACEINDATA(2) => '0', FTMDTRACEINDATA(1) => '0', FTMDTRACEINDATA(0) => '0', FTMDTRACEINVALID => '0', FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0), FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3, FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2, FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1, FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0, FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3, FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2, FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1, FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0, FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0), FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3, FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2, FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1, FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0, FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3, FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2, FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1, FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0, IRQF2P(19) => Core1_nFIQ, IRQF2P(18) => Core0_nFIQ, IRQF2P(17) => Core1_nIRQ, IRQF2P(16) => Core0_nIRQ, IRQF2P(15) => \<const0>\, IRQF2P(14) => \<const0>\, IRQF2P(13) => \<const0>\, IRQF2P(12) => \<const0>\, IRQF2P(11) => \<const0>\, IRQF2P(10) => \<const0>\, IRQF2P(9) => \<const0>\, IRQF2P(8) => \<const0>\, IRQF2P(7) => \<const0>\, IRQF2P(6) => \<const0>\, IRQF2P(5) => \<const0>\, IRQF2P(4) => \<const0>\, IRQF2P(3) => \<const0>\, IRQF2P(2) => \<const0>\, IRQF2P(1) => \<const0>\, IRQF2P(0) => IRQ_F2P(0), IRQP2F(28) => IRQ_P2F_DMAC_ABORT, IRQP2F(27) => IRQ_P2F_DMAC7, IRQP2F(26) => IRQ_P2F_DMAC6, IRQP2F(25) => IRQ_P2F_DMAC5, IRQP2F(24) => IRQ_P2F_DMAC4, IRQP2F(23) => IRQ_P2F_DMAC3, IRQP2F(22) => IRQ_P2F_DMAC2, IRQP2F(21) => IRQ_P2F_DMAC1, IRQP2F(20) => IRQ_P2F_DMAC0, IRQP2F(19) => IRQ_P2F_SMC, IRQP2F(18) => IRQ_P2F_QSPI, IRQP2F(17) => IRQ_P2F_CTI, IRQP2F(16) => IRQ_P2F_GPIO, IRQP2F(15) => IRQ_P2F_USB0, IRQP2F(14) => IRQ_P2F_ENET0, IRQP2F(13) => IRQ_P2F_ENET_WAKE0, IRQP2F(12) => IRQ_P2F_SDIO0, IRQP2F(11) => IRQ_P2F_I2C0, IRQP2F(10) => IRQ_P2F_SPI0, IRQP2F(9) => IRQ_P2F_UART0, IRQP2F(8) => IRQ_P2F_CAN0, IRQP2F(7) => IRQ_P2F_USB1, IRQP2F(6) => IRQ_P2F_ENET1, IRQP2F(5) => IRQ_P2F_ENET_WAKE1, IRQP2F(4) => IRQ_P2F_SDIO1, IRQP2F(3) => IRQ_P2F_I2C1, IRQP2F(2) => IRQ_P2F_SPI1, IRQP2F(1) => IRQ_P2F_UART1, IRQP2F(0) => IRQ_P2F_CAN1, MAXIGP0ACLK => M_AXI_GP0_ACLK, MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0), MAXIGP0ARESETN => M_AXI_GP0_ARESETN, MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), MAXIGP0ARREADY => M_AXI_GP0_ARREADY, MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0), MAXIGP0ARVALID => M_AXI_GP0_ARVALID, MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0), MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), MAXIGP0AWREADY => M_AXI_GP0_AWREADY, MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0), MAXIGP0AWVALID => M_AXI_GP0_AWVALID, MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), MAXIGP0BREADY => M_AXI_GP0_BREADY, MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), MAXIGP0BVALID => M_AXI_GP0_BVALID, MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), MAXIGP0RLAST => M_AXI_GP0_RLAST, MAXIGP0RREADY => M_AXI_GP0_RREADY, MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), MAXIGP0RVALID => M_AXI_GP0_RVALID, MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), MAXIGP0WLAST => M_AXI_GP0_WLAST, MAXIGP0WREADY => M_AXI_GP0_WREADY, MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), MAXIGP0WVALID => M_AXI_GP0_WVALID, MAXIGP1ACLK => M_AXI_GP1_ACLK, MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0), MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0), MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0), MAXIGP1ARESETN => M_AXI_GP1_ARESETN, MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0), MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0), MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0), MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0), MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0), MAXIGP1ARREADY => M_AXI_GP1_ARREADY, MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0), MAXIGP1ARVALID => M_AXI_GP1_ARVALID, MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0), MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0), MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0), MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0), MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0), MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0), MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0), MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0), MAXIGP1AWREADY => M_AXI_GP1_AWREADY, MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0), MAXIGP1AWVALID => M_AXI_GP1_AWVALID, MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0), MAXIGP1BREADY => M_AXI_GP1_BREADY, MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0), MAXIGP1BVALID => M_AXI_GP1_BVALID, MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0), MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0), MAXIGP1RLAST => M_AXI_GP1_RLAST, MAXIGP1RREADY => M_AXI_GP1_RREADY, MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0), MAXIGP1RVALID => M_AXI_GP1_RVALID, MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0), MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0), MAXIGP1WLAST => M_AXI_GP1_WLAST, MAXIGP1WREADY => M_AXI_GP1_WREADY, MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0), MAXIGP1WVALID => M_AXI_GP1_WVALID, MIO(53 downto 0) => buffered_MIO(53 downto 0), PSCLK => buffered_PS_CLK, PSPORB => buffered_PS_PORB, PSSRSTB => buffered_PS_SRSTB, SAXIACPACLK => S_AXI_ACP_ACLK, SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0), SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0), SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0), SAXIACPARESETN => S_AXI_ACP_ARESETN, SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0), SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0), SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0), SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0), SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0), SAXIACPARREADY => S_AXI_ACP_ARREADY, SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0), SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0), SAXIACPARVALID => S_AXI_ACP_ARVALID, SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0), SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0), SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0), SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0), SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0), SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0), SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0), SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0), SAXIACPAWREADY => S_AXI_ACP_AWREADY, SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0), SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0), SAXIACPAWVALID => S_AXI_ACP_AWVALID, SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0), SAXIACPBREADY => S_AXI_ACP_BREADY, SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0), SAXIACPBVALID => S_AXI_ACP_BVALID, SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0), SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0), SAXIACPRLAST => S_AXI_ACP_RLAST, SAXIACPRREADY => S_AXI_ACP_RREADY, SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0), SAXIACPRVALID => S_AXI_ACP_RVALID, SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0), SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0), SAXIACPWLAST => S_AXI_ACP_WLAST, SAXIACPWREADY => S_AXI_ACP_WREADY, SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0), SAXIACPWVALID => S_AXI_ACP_WVALID, SAXIGP0ACLK => S_AXI_GP0_ACLK, SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0), SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0), SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0), SAXIGP0ARESETN => S_AXI_GP0_ARESETN, SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0), SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0), SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0), SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0), SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0), SAXIGP0ARREADY => S_AXI_GP0_ARREADY, SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0), SAXIGP0ARVALID => S_AXI_GP0_ARVALID, SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0), SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0), SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0), SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0), SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0), SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0), SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0), SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0), SAXIGP0AWREADY => S_AXI_GP0_AWREADY, SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0), SAXIGP0AWVALID => S_AXI_GP0_AWVALID, SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0), SAXIGP0BREADY => S_AXI_GP0_BREADY, SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0), SAXIGP0BVALID => S_AXI_GP0_BVALID, SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0), SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0), SAXIGP0RLAST => S_AXI_GP0_RLAST, SAXIGP0RREADY => S_AXI_GP0_RREADY, SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0), SAXIGP0RVALID => S_AXI_GP0_RVALID, SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0), SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0), SAXIGP0WLAST => S_AXI_GP0_WLAST, SAXIGP0WREADY => S_AXI_GP0_WREADY, SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0), SAXIGP0WVALID => S_AXI_GP0_WVALID, SAXIGP1ACLK => S_AXI_GP1_ACLK, SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0), SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0), SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0), SAXIGP1ARESETN => S_AXI_GP1_ARESETN, SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0), SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0), SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0), SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0), SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0), SAXIGP1ARREADY => S_AXI_GP1_ARREADY, SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0), SAXIGP1ARVALID => S_AXI_GP1_ARVALID, SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0), SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0), SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0), SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0), SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0), SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0), SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0), SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0), SAXIGP1AWREADY => S_AXI_GP1_AWREADY, SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0), SAXIGP1AWVALID => S_AXI_GP1_AWVALID, SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0), SAXIGP1BREADY => S_AXI_GP1_BREADY, SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0), SAXIGP1BVALID => S_AXI_GP1_BVALID, SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0), SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0), SAXIGP1RLAST => S_AXI_GP1_RLAST, SAXIGP1RREADY => S_AXI_GP1_RREADY, SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0), SAXIGP1RVALID => S_AXI_GP1_RVALID, SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0), SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0), SAXIGP1WLAST => S_AXI_GP1_WLAST, SAXIGP1WREADY => S_AXI_GP1_WREADY, SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0), SAXIGP1WVALID => S_AXI_GP1_WVALID, SAXIHP0ACLK => S_AXI_HP0_ACLK, SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0), SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0), SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0), SAXIHP0ARESETN => S_AXI_HP0_ARESETN, SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0), SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0), SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0), SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0), SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0), SAXIHP0ARREADY => S_AXI_HP0_ARREADY, SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0), SAXIHP0ARVALID => S_AXI_HP0_ARVALID, SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0), SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0), SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0), SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0), SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0), SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0), SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0), SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0), SAXIHP0AWREADY => S_AXI_HP0_AWREADY, SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0), SAXIHP0AWVALID => S_AXI_HP0_AWVALID, SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0), SAXIHP0BREADY => S_AXI_HP0_BREADY, SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0), SAXIHP0BVALID => S_AXI_HP0_BVALID, SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0), SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0), SAXIHP0RDATA(63 downto 32) => NLW_PS7_i_SAXIHP0RDATA_UNCONNECTED(63 downto 32), SAXIHP0RDATA(31 downto 0) => S_AXI_HP0_RDATA(31 downto 0), SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN, SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0), SAXIHP0RLAST => S_AXI_HP0_RLAST, SAXIHP0RREADY => S_AXI_HP0_RREADY, SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0), SAXIHP0RVALID => S_AXI_HP0_RVALID, SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0), SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0), SAXIHP0WDATA(63) => \<const0>\, SAXIHP0WDATA(62) => \<const0>\, SAXIHP0WDATA(61) => \<const0>\, SAXIHP0WDATA(60) => \<const0>\, SAXIHP0WDATA(59) => \<const0>\, SAXIHP0WDATA(58) => \<const0>\, SAXIHP0WDATA(57) => \<const0>\, SAXIHP0WDATA(56) => \<const0>\, SAXIHP0WDATA(55) => \<const0>\, SAXIHP0WDATA(54) => \<const0>\, SAXIHP0WDATA(53) => \<const0>\, SAXIHP0WDATA(52) => \<const0>\, SAXIHP0WDATA(51) => \<const0>\, SAXIHP0WDATA(50) => \<const0>\, SAXIHP0WDATA(49) => \<const0>\, SAXIHP0WDATA(48) => \<const0>\, SAXIHP0WDATA(47) => \<const0>\, SAXIHP0WDATA(46) => \<const0>\, SAXIHP0WDATA(45) => \<const0>\, SAXIHP0WDATA(44) => \<const0>\, SAXIHP0WDATA(43) => \<const0>\, SAXIHP0WDATA(42) => \<const0>\, SAXIHP0WDATA(41) => \<const0>\, SAXIHP0WDATA(40) => \<const0>\, SAXIHP0WDATA(39) => \<const0>\, SAXIHP0WDATA(38) => \<const0>\, SAXIHP0WDATA(37) => \<const0>\, SAXIHP0WDATA(36) => \<const0>\, SAXIHP0WDATA(35) => \<const0>\, SAXIHP0WDATA(34) => \<const0>\, SAXIHP0WDATA(33) => \<const0>\, SAXIHP0WDATA(32) => \<const0>\, SAXIHP0WDATA(31 downto 0) => S_AXI_HP0_WDATA(31 downto 0), SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0), SAXIHP0WLAST => S_AXI_HP0_WLAST, SAXIHP0WREADY => S_AXI_HP0_WREADY, SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN, SAXIHP0WSTRB(7) => \<const0>\, SAXIHP0WSTRB(6) => \<const0>\, SAXIHP0WSTRB(5) => \<const0>\, SAXIHP0WSTRB(4) => \<const0>\, SAXIHP0WSTRB(3 downto 0) => S_AXI_HP0_WSTRB(3 downto 0), SAXIHP0WVALID => S_AXI_HP0_WVALID, SAXIHP1ACLK => S_AXI_HP1_ACLK, SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0), SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0), SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0), SAXIHP1ARESETN => S_AXI_HP1_ARESETN, SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0), SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0), SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0), SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0), SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0), SAXIHP1ARREADY => S_AXI_HP1_ARREADY, SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0), SAXIHP1ARVALID => S_AXI_HP1_ARVALID, SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0), SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0), SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0), SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0), SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0), SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0), SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0), SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0), SAXIHP1AWREADY => S_AXI_HP1_AWREADY, SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0), SAXIHP1AWVALID => S_AXI_HP1_AWVALID, SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0), SAXIHP1BREADY => S_AXI_HP1_BREADY, SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0), SAXIHP1BVALID => S_AXI_HP1_BVALID, SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0), SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0), SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0), SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN, SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0), SAXIHP1RLAST => S_AXI_HP1_RLAST, SAXIHP1RREADY => S_AXI_HP1_RREADY, SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0), SAXIHP1RVALID => S_AXI_HP1_RVALID, SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0), SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0), SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0), SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0), SAXIHP1WLAST => S_AXI_HP1_WLAST, SAXIHP1WREADY => S_AXI_HP1_WREADY, SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN, SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0), SAXIHP1WVALID => S_AXI_HP1_WVALID, SAXIHP2ACLK => S_AXI_HP2_ACLK, SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0), SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0), SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0), SAXIHP2ARESETN => S_AXI_HP2_ARESETN, SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0), SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0), SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0), SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0), SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0), SAXIHP2ARREADY => S_AXI_HP2_ARREADY, SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0), SAXIHP2ARVALID => S_AXI_HP2_ARVALID, SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0), SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0), SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0), SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0), SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0), SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0), SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0), SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0), SAXIHP2AWREADY => S_AXI_HP2_AWREADY, SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0), SAXIHP2AWVALID => S_AXI_HP2_AWVALID, SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0), SAXIHP2BREADY => S_AXI_HP2_BREADY, SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0), SAXIHP2BVALID => S_AXI_HP2_BVALID, SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0), SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0), SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0), SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN, SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0), SAXIHP2RLAST => S_AXI_HP2_RLAST, SAXIHP2RREADY => S_AXI_HP2_RREADY, SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0), SAXIHP2RVALID => S_AXI_HP2_RVALID, SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0), SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0), SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0), SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0), SAXIHP2WLAST => S_AXI_HP2_WLAST, SAXIHP2WREADY => S_AXI_HP2_WREADY, SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN, SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0), SAXIHP2WVALID => S_AXI_HP2_WVALID, SAXIHP3ACLK => S_AXI_HP3_ACLK, SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0), SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0), SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0), SAXIHP3ARESETN => S_AXI_HP3_ARESETN, SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0), SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0), SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0), SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0), SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0), SAXIHP3ARREADY => S_AXI_HP3_ARREADY, SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0), SAXIHP3ARVALID => S_AXI_HP3_ARVALID, SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0), SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0), SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0), SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0), SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0), SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0), SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0), SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0), SAXIHP3AWREADY => S_AXI_HP3_AWREADY, SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0), SAXIHP3AWVALID => S_AXI_HP3_AWVALID, SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0), SAXIHP3BREADY => S_AXI_HP3_BREADY, SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0), SAXIHP3BVALID => S_AXI_HP3_BVALID, SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0), SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0), SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0), SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN, SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0), SAXIHP3RLAST => S_AXI_HP3_RLAST, SAXIHP3RREADY => S_AXI_HP3_RREADY, SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0), SAXIHP3RVALID => S_AXI_HP3_RVALID, SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0), SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0), SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0), SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0), SAXIHP3WLAST => S_AXI_HP3_WLAST, SAXIHP3WREADY => S_AXI_HP3_WREADY, SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN, SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0), SAXIHP3WVALID => S_AXI_HP3_WVALID ); PS_CLK_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_CLK, PAD => PS_CLK ); PS_PORB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_PORB, PAD => PS_PORB ); PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_SRSTB, PAD => PS_SRSTB ); SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_CMD_T_n, O => SDIO0_CMD_T ); \SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => p_0_in(0), O => SDIO0_DATA_T(0) ); \SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => p_0_in(1), O => SDIO0_DATA_T(1) ); \SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => p_0_in(2), O => SDIO0_DATA_T(2) ); \SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => p_0_in(3), O => SDIO0_DATA_T(3) ); SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_CMD_T_n, O => SDIO1_CMD_T ); \SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_704_PS7_i, O => SDIO1_DATA_T(0) ); \SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_703_PS7_i, O => SDIO1_DATA_T(1) ); \SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_702_PS7_i, O => SDIO1_DATA_T(2) ); \SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => n_701_PS7_i, O => SDIO1_DATA_T(3) ); SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MISO_T_n, O => SPI0_MISO_T ); SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MOSI_T_n, O => SPI0_MOSI_T ); SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SCLK_T_n, O => SPI0_SCLK_T ); SPI0_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SS_T_n, O => SPI0_SS_T ); SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MISO_T_n, O => SPI1_MISO_T ); SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MOSI_T_n, O => SPI1_MOSI_T ); SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SCLK_T_n, O => SPI1_SCLK_T ); SPI1_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SS_T_n, O => SPI1_SS_T ); \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG port map ( I => FCLK_CLK_unbuffered(0), O => FCLK_CLK0 ); \buffer_fclk_clk_3.FCLK_CLK_3_BUFG\: unisim.vcomponents.BUFG port map ( I => FCLK_CLK_unbuffered(3), O => FCLK_CLK3 ); \genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(0), PAD => MIO(0) ); \genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(10), PAD => MIO(10) ); \genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(11), PAD => MIO(11) ); \genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(12), PAD => MIO(12) ); \genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(13), PAD => MIO(13) ); \genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(14), PAD => MIO(14) ); \genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(15), PAD => MIO(15) ); \genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(16), PAD => MIO(16) ); \genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(17), PAD => MIO(17) ); \genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(18), PAD => MIO(18) ); \genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(19), PAD => MIO(19) ); \genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(1), PAD => MIO(1) ); \genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(20), PAD => MIO(20) ); \genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(21), PAD => MIO(21) ); \genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(22), PAD => MIO(22) ); \genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(23), PAD => MIO(23) ); \genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(24), PAD => MIO(24) ); \genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(25), PAD => MIO(25) ); \genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(26), PAD => MIO(26) ); \genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(27), PAD => MIO(27) ); \genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(28), PAD => MIO(28) ); \genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(29), PAD => MIO(29) ); \genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(2), PAD => MIO(2) ); \genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(30), PAD => MIO(30) ); \genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(31), PAD => MIO(31) ); \genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(32), PAD => MIO(32) ); \genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(33), PAD => MIO(33) ); \genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(34), PAD => MIO(34) ); \genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(35), PAD => MIO(35) ); \genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(36), PAD => MIO(36) ); \genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(37), PAD => MIO(37) ); \genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(38), PAD => MIO(38) ); \genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(39), PAD => MIO(39) ); \genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(3), PAD => MIO(3) ); \genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(40), PAD => MIO(40) ); \genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(41), PAD => MIO(41) ); \genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(42), PAD => MIO(42) ); \genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(43), PAD => MIO(43) ); \genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(44), PAD => MIO(44) ); \genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(45), PAD => MIO(45) ); \genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(46), PAD => MIO(46) ); \genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(47), PAD => MIO(47) ); \genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(48), PAD => MIO(48) ); \genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(49), PAD => MIO(49) ); \genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(4), PAD => MIO(4) ); \genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(50), PAD => MIO(50) ); \genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(51), PAD => MIO(51) ); \genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(52), PAD => MIO(52) ); \genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(53), PAD => MIO(53) ); \genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(5), PAD => MIO(5) ); \genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(6), PAD => MIO(6) ); \genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(7), PAD => MIO(7) ); \genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(8), PAD => MIO(8) ); \genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(9), PAD => MIO(9) ); \genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(0), PAD => DDR_BankAddr(0) ); \genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(1), PAD => DDR_BankAddr(1) ); \genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(2), PAD => DDR_BankAddr(2) ); \genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(0), PAD => DDR_Addr(0) ); \genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(10), PAD => DDR_Addr(10) ); \genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(11), PAD => DDR_Addr(11) ); \genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(12), PAD => DDR_Addr(12) ); \genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(13), PAD => DDR_Addr(13) ); \genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(14), PAD => DDR_Addr(14) ); \genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(1), PAD => DDR_Addr(1) ); \genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(2), PAD => DDR_Addr(2) ); \genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(3), PAD => DDR_Addr(3) ); \genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(4), PAD => DDR_Addr(4) ); \genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(5), PAD => DDR_Addr(5) ); \genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(6), PAD => DDR_Addr(6) ); \genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(7), PAD => DDR_Addr(7) ); \genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(8), PAD => DDR_Addr(8) ); \genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(9), PAD => DDR_Addr(9) ); \genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(0), PAD => DDR_DM(0) ); \genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(1), PAD => DDR_DM(1) ); \genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(2), PAD => DDR_DM(2) ); \genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(3), PAD => DDR_DM(3) ); \genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(0), PAD => DDR_DQ(0) ); \genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(10), PAD => DDR_DQ(10) ); \genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(11), PAD => DDR_DQ(11) ); \genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(12), PAD => DDR_DQ(12) ); \genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(13), PAD => DDR_DQ(13) ); \genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(14), PAD => DDR_DQ(14) ); \genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(15), PAD => DDR_DQ(15) ); \genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(16), PAD => DDR_DQ(16) ); \genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(17), PAD => DDR_DQ(17) ); \genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(18), PAD => DDR_DQ(18) ); \genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(19), PAD => DDR_DQ(19) ); \genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(1), PAD => DDR_DQ(1) ); \genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(20), PAD => DDR_DQ(20) ); \genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(21), PAD => DDR_DQ(21) ); \genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(22), PAD => DDR_DQ(22) ); \genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(23), PAD => DDR_DQ(23) ); \genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(24), PAD => DDR_DQ(24) ); \genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(25), PAD => DDR_DQ(25) ); \genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(26), PAD => DDR_DQ(26) ); \genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(27), PAD => DDR_DQ(27) ); \genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(28), PAD => DDR_DQ(28) ); \genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(29), PAD => DDR_DQ(29) ); \genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(2), PAD => DDR_DQ(2) ); \genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(30), PAD => DDR_DQ(30) ); \genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(31), PAD => DDR_DQ(31) ); \genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(3), PAD => DDR_DQ(3) ); \genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(4), PAD => DDR_DQ(4) ); \genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(5), PAD => DDR_DQ(5) ); \genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(6), PAD => DDR_DQ(6) ); \genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(7), PAD => DDR_DQ(7) ); \genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(8), PAD => DDR_DQ(8) ); \genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(9), PAD => DDR_DQ(9) ); \genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(0), PAD => DDR_DQS_n(0) ); \genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(1), PAD => DDR_DQS_n(1) ); \genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(2), PAD => DDR_DQS_n(2) ); \genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(3), PAD => DDR_DQS_n(3) ); \genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(0), PAD => DDR_DQS(0) ); \genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(1), PAD => DDR_DQS(1) ); \genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(2), PAD => DDR_DQS(2) ); \genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(3), PAD => DDR_DQS(3) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity processing_system7_0 is port ( ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET0_SOF_RX : out STD_LOGIC; ENET0_SOF_TX : out STD_LOGIC; GPIO_I : in STD_LOGIC_VECTOR ( 47 downto 0 ); GPIO_O : out STD_LOGIC_VECTOR ( 47 downto 0 ); GPIO_T : out STD_LOGIC_VECTOR ( 47 downto 0 ); I2C0_SDA_I : in STD_LOGIC; I2C0_SDA_O : out STD_LOGIC; I2C0_SDA_T : out STD_LOGIC; I2C0_SCL_I : in STD_LOGIC; I2C0_SCL_O : out STD_LOGIC; I2C0_SCL_T : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB1_VBUS_PWRSELECT : out STD_LOGIC; USB1_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP1_ARVALID : out STD_LOGIC; M_AXI_GP1_AWVALID : out STD_LOGIC; M_AXI_GP1_BREADY : out STD_LOGIC; M_AXI_GP1_RREADY : out STD_LOGIC; M_AXI_GP1_WLAST : out STD_LOGIC; M_AXI_GP1_WVALID : out STD_LOGIC; M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ACLK : in STD_LOGIC; M_AXI_GP1_ARREADY : in STD_LOGIC; M_AXI_GP1_AWREADY : in STD_LOGIC; M_AXI_GP1_BVALID : in STD_LOGIC; M_AXI_GP1_RLAST : in STD_LOGIC; M_AXI_GP1_RVALID : in STD_LOGIC; M_AXI_GP1_WREADY : in STD_LOGIC; M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_ARREADY : out STD_LOGIC; S_AXI_HP1_AWREADY : out STD_LOGIC; S_AXI_HP1_BVALID : out STD_LOGIC; S_AXI_HP1_RLAST : out STD_LOGIC; S_AXI_HP1_RVALID : out STD_LOGIC; S_AXI_HP1_WREADY : out STD_LOGIC; S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_ACLK : in STD_LOGIC; S_AXI_HP1_ARVALID : in STD_LOGIC; S_AXI_HP1_AWVALID : in STD_LOGIC; S_AXI_HP1_BREADY : in STD_LOGIC; S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_RREADY : in STD_LOGIC; S_AXI_HP1_WLAST : in STD_LOGIC; S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_WVALID : in STD_LOGIC; S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_CLK3 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of processing_system7_0 : entity is true; attribute X_CORE_INFO : string; attribute X_CORE_INFO of processing_system7_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2014.3"; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of processing_system7_0 : entity is "processing_system7_0,processing_system7_v5_5_processing_system7,{}"; attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of processing_system7_0 : entity is "processing_system7_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2014.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=0,x_ipLanguage=VERILOG,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=48,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=32,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=true,C_PACKAGE_NAME=clg400}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of processing_system7_0 : entity is "yes"; end processing_system7_0; architecture STRUCTURE of processing_system7_0 is signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute CORE_GENERATION_INFO of inst : label is "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=400, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=9, PCW_UIPARAM_DDR_CWL=9, PCW_UIPARAM_DDR_T_RCD=9, PCW_UIPARAM_DDR_T_RP=9, PCW_UIPARAM_DDR_T_RC=60, PCW_UIPARAM_DDR_T_RAS_MIN=40, PCW_UIPARAM_DDR_T_FAW=50, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.315, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.391, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.374, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.271, PCW_UIPARAM_DDR_BOARD_DELAY0=0.434, PCW_UIPARAM_DDR_BOARD_DELAY1=0.398, PCW_UIPARAM_DDR_BOARD_DELAY2=0.41, PCW_UIPARAM_DDR_BOARD_DELAY3=0.455, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=200.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=200.000000, PCW_FPGA3_PERIPHERAL_FREQMHZ=40.000000, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=48, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1600.000, PCW_USE_M_AXI_GP0=0, PCW_USE_M_AXI_GP1=1, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=1, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=10, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=32, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3 (Low Voltage), PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=Custom, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=1, PCW_SD1_SD1_IO=MIO 10 .. 15, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 8 .. 9, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=1, PCW_USB1_USB1_IO=MIO 40 .. 51, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=1, PCW_GPIO_MIO_GPIO_ENABLE=0, PCW_GPIO_EMIO_GPIO_ENABLE=1, PCW_GPIO_EMIO_GPIO_IO=48, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=1, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }"; attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of inst : label is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of inst : label is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of inst : label is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of inst : label is 48; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of inst : label is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of inst : label is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of inst : label is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of inst : label is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of inst : label is "true"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of inst : label is "false"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of inst : label is "false"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of inst : label is "true"; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of inst : label is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of inst : label is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of inst : label is "clg400"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of inst : label is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 32; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0; attribute POWER : string; attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1600.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP1} dataWidth={64} clockFreq={10} usageRate={0.5} /><AXI interface={M_AXI_GP1} dataWidth={32} clockFreq={10} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of inst : label is "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_RX"; begin inst: entity work.processing_system7_0_processing_system7_v5_5_processing_system7 port map ( CAN0_PHY_RX => '0', CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED, CAN1_PHY_RX => '0', CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED, Core0_nFIQ => '0', Core0_nIRQ => '0', Core1_nFIQ => '0', Core1_nIRQ => '0', DDR_ARB(3) => '0', DDR_ARB(2) => '0', DDR_ARB(1) => '0', DDR_ARB(0) => '0', DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0), DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0), DDR_CAS_n => DDR_CAS_n, DDR_CKE => DDR_CKE, DDR_CS_n => DDR_CS_n, DDR_Clk => DDR_Clk, DDR_Clk_n => DDR_Clk_n, DDR_DM(3 downto 0) => DDR_DM(3 downto 0), DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0), DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0), DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0), DDR_DRSTB => DDR_DRSTB, DDR_ODT => DDR_ODT, DDR_RAS_n => DDR_RAS_n, DDR_VRN => DDR_VRN, DDR_VRP => DDR_VRP, DDR_WEB => DDR_WEB, DMA0_ACLK => '0', DMA0_DAREADY => '0', DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0), DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED, DMA0_DRLAST => '0', DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED, DMA0_DRTYPE(1) => '0', DMA0_DRTYPE(0) => '0', DMA0_DRVALID => '0', DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED, DMA1_ACLK => '0', DMA1_DAREADY => '0', DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0), DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED, DMA1_DRLAST => '0', DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED, DMA1_DRTYPE(1) => '0', DMA1_DRTYPE(0) => '0', DMA1_DRVALID => '0', DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED, DMA2_ACLK => '0', DMA2_DAREADY => '0', DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0), DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED, DMA2_DRLAST => '0', DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED, DMA2_DRTYPE(1) => '0', DMA2_DRTYPE(0) => '0', DMA2_DRVALID => '0', DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED, DMA3_ACLK => '0', DMA3_DAREADY => '0', DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0), DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED, DMA3_DRLAST => '0', DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED, DMA3_DRTYPE(1) => '0', DMA3_DRTYPE(0) => '0', DMA3_DRVALID => '0', DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED, ENET0_EXT_INTIN => '0', ENET0_GMII_COL => '0', ENET0_GMII_CRS => '0', ENET0_GMII_RXD(7) => '0', ENET0_GMII_RXD(6) => '0', ENET0_GMII_RXD(5) => '0', ENET0_GMII_RXD(4) => '0', ENET0_GMII_RXD(3) => '0', ENET0_GMII_RXD(2) => '0', ENET0_GMII_RXD(1) => '0', ENET0_GMII_RXD(0) => '0', ENET0_GMII_RX_CLK => '0', ENET0_GMII_RX_DV => '0', ENET0_GMII_RX_ER => '0', ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0), ENET0_GMII_TX_CLK => '0', ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED, ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED, ENET0_MDIO_I => '0', ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED, ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED, ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED, ENET0_PTP_DELAY_REQ_RX => ENET0_PTP_DELAY_REQ_RX, ENET0_PTP_DELAY_REQ_TX => ENET0_PTP_DELAY_REQ_TX, ENET0_PTP_PDELAY_REQ_RX => ENET0_PTP_PDELAY_REQ_RX, ENET0_PTP_PDELAY_REQ_TX => ENET0_PTP_PDELAY_REQ_TX, ENET0_PTP_PDELAY_RESP_RX => ENET0_PTP_PDELAY_RESP_RX, ENET0_PTP_PDELAY_RESP_TX => ENET0_PTP_PDELAY_RESP_TX, ENET0_PTP_SYNC_FRAME_RX => ENET0_PTP_SYNC_FRAME_RX, ENET0_PTP_SYNC_FRAME_TX => ENET0_PTP_SYNC_FRAME_TX, ENET0_SOF_RX => ENET0_SOF_RX, ENET0_SOF_TX => ENET0_SOF_TX, ENET1_EXT_INTIN => '0', ENET1_GMII_COL => '0', ENET1_GMII_CRS => '0', ENET1_GMII_RXD(7) => '0', ENET1_GMII_RXD(6) => '0', ENET1_GMII_RXD(5) => '0', ENET1_GMII_RXD(4) => '0', ENET1_GMII_RXD(3) => '0', ENET1_GMII_RXD(2) => '0', ENET1_GMII_RXD(1) => '0', ENET1_GMII_RXD(0) => '0', ENET1_GMII_RX_CLK => '0', ENET1_GMII_RX_DV => '0', ENET1_GMII_RX_ER => '0', ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0), ENET1_GMII_TX_CLK => '0', ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED, ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED, ENET1_MDIO_I => '0', ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED, ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED, ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED, ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED, ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED, ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED, EVENT_EVENTI => '0', EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED, EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0), EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0), FCLK_CLK0 => FCLK_CLK0, FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED, FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED, FCLK_CLK3 => FCLK_CLK3, FCLK_CLKTRIG0_N => '0', FCLK_CLKTRIG1_N => '0', FCLK_CLKTRIG2_N => '0', FCLK_CLKTRIG3_N => '0', FCLK_RESET0_N => FCLK_RESET0_N, FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED, FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED, FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED, FPGA_IDLE_N => '0', FTMD_TRACEIN_ATID(3) => '0', FTMD_TRACEIN_ATID(2) => '0', FTMD_TRACEIN_ATID(1) => '0', FTMD_TRACEIN_ATID(0) => '0', FTMD_TRACEIN_CLK => '0', FTMD_TRACEIN_DATA(31) => '0', FTMD_TRACEIN_DATA(30) => '0', FTMD_TRACEIN_DATA(29) => '0', FTMD_TRACEIN_DATA(28) => '0', FTMD_TRACEIN_DATA(27) => '0', FTMD_TRACEIN_DATA(26) => '0', FTMD_TRACEIN_DATA(25) => '0', FTMD_TRACEIN_DATA(24) => '0', FTMD_TRACEIN_DATA(23) => '0', FTMD_TRACEIN_DATA(22) => '0', FTMD_TRACEIN_DATA(21) => '0', FTMD_TRACEIN_DATA(20) => '0', FTMD_TRACEIN_DATA(19) => '0', FTMD_TRACEIN_DATA(18) => '0', FTMD_TRACEIN_DATA(17) => '0', FTMD_TRACEIN_DATA(16) => '0', FTMD_TRACEIN_DATA(15) => '0', FTMD_TRACEIN_DATA(14) => '0', FTMD_TRACEIN_DATA(13) => '0', FTMD_TRACEIN_DATA(12) => '0', FTMD_TRACEIN_DATA(11) => '0', FTMD_TRACEIN_DATA(10) => '0', FTMD_TRACEIN_DATA(9) => '0', FTMD_TRACEIN_DATA(8) => '0', FTMD_TRACEIN_DATA(7) => '0', FTMD_TRACEIN_DATA(6) => '0', FTMD_TRACEIN_DATA(5) => '0', FTMD_TRACEIN_DATA(4) => '0', FTMD_TRACEIN_DATA(3) => '0', FTMD_TRACEIN_DATA(2) => '0', FTMD_TRACEIN_DATA(1) => '0', FTMD_TRACEIN_DATA(0) => '0', FTMD_TRACEIN_VALID => '0', FTMT_F2P_DEBUG(31) => '0', FTMT_F2P_DEBUG(30) => '0', FTMT_F2P_DEBUG(29) => '0', FTMT_F2P_DEBUG(28) => '0', FTMT_F2P_DEBUG(27) => '0', FTMT_F2P_DEBUG(26) => '0', FTMT_F2P_DEBUG(25) => '0', FTMT_F2P_DEBUG(24) => '0', FTMT_F2P_DEBUG(23) => '0', FTMT_F2P_DEBUG(22) => '0', FTMT_F2P_DEBUG(21) => '0', FTMT_F2P_DEBUG(20) => '0', FTMT_F2P_DEBUG(19) => '0', FTMT_F2P_DEBUG(18) => '0', FTMT_F2P_DEBUG(17) => '0', FTMT_F2P_DEBUG(16) => '0', FTMT_F2P_DEBUG(15) => '0', FTMT_F2P_DEBUG(14) => '0', FTMT_F2P_DEBUG(13) => '0', FTMT_F2P_DEBUG(12) => '0', FTMT_F2P_DEBUG(11) => '0', FTMT_F2P_DEBUG(10) => '0', FTMT_F2P_DEBUG(9) => '0', FTMT_F2P_DEBUG(8) => '0', FTMT_F2P_DEBUG(7) => '0', FTMT_F2P_DEBUG(6) => '0', FTMT_F2P_DEBUG(5) => '0', FTMT_F2P_DEBUG(4) => '0', FTMT_F2P_DEBUG(3) => '0', FTMT_F2P_DEBUG(2) => '0', FTMT_F2P_DEBUG(1) => '0', FTMT_F2P_DEBUG(0) => '0', FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED, FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED, FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED, FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED, FTMT_F2P_TRIG_0 => '0', FTMT_F2P_TRIG_1 => '0', FTMT_F2P_TRIG_2 => '0', FTMT_F2P_TRIG_3 => '0', FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0), FTMT_P2F_TRIGACK_0 => '0', FTMT_P2F_TRIGACK_1 => '0', FTMT_P2F_TRIGACK_2 => '0', FTMT_P2F_TRIGACK_3 => '0', FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED, FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED, FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED, FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED, GPIO_I(47 downto 0) => GPIO_I(47 downto 0), GPIO_O(47 downto 0) => GPIO_O(47 downto 0), GPIO_T(47 downto 0) => GPIO_T(47 downto 0), I2C0_SCL_I => I2C0_SCL_I, I2C0_SCL_O => I2C0_SCL_O, I2C0_SCL_T => I2C0_SCL_T, I2C0_SDA_I => I2C0_SDA_I, I2C0_SDA_O => I2C0_SDA_O, I2C0_SDA_T => I2C0_SDA_T, I2C1_SCL_I => '0', I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED, I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED, I2C1_SDA_I => '0', I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED, I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED, IRQ_F2P(0) => '0', IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED, IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED, IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED, IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED, IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED, IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED, IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED, IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED, IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED, IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED, IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED, IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED, IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED, IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED, IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED, IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED, IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED, IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED, IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED, IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED, IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED, IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED, IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED, IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED, IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED, IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED, IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED, IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED, IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED, MIO(53 downto 0) => MIO(53 downto 0), M_AXI_GP0_ACLK => '0', M_AXI_GP0_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0), M_AXI_GP0_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0), M_AXI_GP0_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0), M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED, M_AXI_GP0_ARID(11 downto 0) => NLW_inst_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0), M_AXI_GP0_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0), M_AXI_GP0_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0), M_AXI_GP0_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0), M_AXI_GP0_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0), M_AXI_GP0_ARREADY => '0', M_AXI_GP0_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0), M_AXI_GP0_ARVALID => NLW_inst_M_AXI_GP0_ARVALID_UNCONNECTED, M_AXI_GP0_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0), M_AXI_GP0_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0), M_AXI_GP0_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0), M_AXI_GP0_AWID(11 downto 0) => NLW_inst_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0), M_AXI_GP0_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0), M_AXI_GP0_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0), M_AXI_GP0_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0), M_AXI_GP0_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0), M_AXI_GP0_AWREADY => '0', M_AXI_GP0_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0), M_AXI_GP0_AWVALID => NLW_inst_M_AXI_GP0_AWVALID_UNCONNECTED, M_AXI_GP0_BID(11) => '0', M_AXI_GP0_BID(10) => '0', M_AXI_GP0_BID(9) => '0', M_AXI_GP0_BID(8) => '0', M_AXI_GP0_BID(7) => '0', M_AXI_GP0_BID(6) => '0', M_AXI_GP0_BID(5) => '0', M_AXI_GP0_BID(4) => '0', M_AXI_GP0_BID(3) => '0', M_AXI_GP0_BID(2) => '0', M_AXI_GP0_BID(1) => '0', M_AXI_GP0_BID(0) => '0', M_AXI_GP0_BREADY => NLW_inst_M_AXI_GP0_BREADY_UNCONNECTED, M_AXI_GP0_BRESP(1) => '0', M_AXI_GP0_BRESP(0) => '0', M_AXI_GP0_BVALID => '0', M_AXI_GP0_RDATA(31) => '0', M_AXI_GP0_RDATA(30) => '0', M_AXI_GP0_RDATA(29) => '0', M_AXI_GP0_RDATA(28) => '0', M_AXI_GP0_RDATA(27) => '0', M_AXI_GP0_RDATA(26) => '0', M_AXI_GP0_RDATA(25) => '0', M_AXI_GP0_RDATA(24) => '0', M_AXI_GP0_RDATA(23) => '0', M_AXI_GP0_RDATA(22) => '0', M_AXI_GP0_RDATA(21) => '0', M_AXI_GP0_RDATA(20) => '0', M_AXI_GP0_RDATA(19) => '0', M_AXI_GP0_RDATA(18) => '0', M_AXI_GP0_RDATA(17) => '0', M_AXI_GP0_RDATA(16) => '0', M_AXI_GP0_RDATA(15) => '0', M_AXI_GP0_RDATA(14) => '0', M_AXI_GP0_RDATA(13) => '0', M_AXI_GP0_RDATA(12) => '0', M_AXI_GP0_RDATA(11) => '0', M_AXI_GP0_RDATA(10) => '0', M_AXI_GP0_RDATA(9) => '0', M_AXI_GP0_RDATA(8) => '0', M_AXI_GP0_RDATA(7) => '0', M_AXI_GP0_RDATA(6) => '0', M_AXI_GP0_RDATA(5) => '0', M_AXI_GP0_RDATA(4) => '0', M_AXI_GP0_RDATA(3) => '0', M_AXI_GP0_RDATA(2) => '0', M_AXI_GP0_RDATA(1) => '0', M_AXI_GP0_RDATA(0) => '0', M_AXI_GP0_RID(11) => '0', M_AXI_GP0_RID(10) => '0', M_AXI_GP0_RID(9) => '0', M_AXI_GP0_RID(8) => '0', M_AXI_GP0_RID(7) => '0', M_AXI_GP0_RID(6) => '0', M_AXI_GP0_RID(5) => '0', M_AXI_GP0_RID(4) => '0', M_AXI_GP0_RID(3) => '0', M_AXI_GP0_RID(2) => '0', M_AXI_GP0_RID(1) => '0', M_AXI_GP0_RID(0) => '0', M_AXI_GP0_RLAST => '0', M_AXI_GP0_RREADY => NLW_inst_M_AXI_GP0_RREADY_UNCONNECTED, M_AXI_GP0_RRESP(1) => '0', M_AXI_GP0_RRESP(0) => '0', M_AXI_GP0_RVALID => '0', M_AXI_GP0_WDATA(31 downto 0) => NLW_inst_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0), M_AXI_GP0_WID(11 downto 0) => NLW_inst_M_AXI_GP0_WID_UNCONNECTED(11 downto 0), M_AXI_GP0_WLAST => NLW_inst_M_AXI_GP0_WLAST_UNCONNECTED, M_AXI_GP0_WREADY => '0', M_AXI_GP0_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0), M_AXI_GP0_WVALID => NLW_inst_M_AXI_GP0_WVALID_UNCONNECTED, M_AXI_GP1_ACLK => M_AXI_GP1_ACLK, M_AXI_GP1_ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0), M_AXI_GP1_ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0), M_AXI_GP1_ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0), M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED, M_AXI_GP1_ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0), M_AXI_GP1_ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0), M_AXI_GP1_ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0), M_AXI_GP1_ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0), M_AXI_GP1_ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0), M_AXI_GP1_ARREADY => M_AXI_GP1_ARREADY, M_AXI_GP1_ARSIZE(2 downto 0) => M_AXI_GP1_ARSIZE(2 downto 0), M_AXI_GP1_ARVALID => M_AXI_GP1_ARVALID, M_AXI_GP1_AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0), M_AXI_GP1_AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0), M_AXI_GP1_AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0), M_AXI_GP1_AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0), M_AXI_GP1_AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0), M_AXI_GP1_AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0), M_AXI_GP1_AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0), M_AXI_GP1_AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0), M_AXI_GP1_AWREADY => M_AXI_GP1_AWREADY, M_AXI_GP1_AWSIZE(2 downto 0) => M_AXI_GP1_AWSIZE(2 downto 0), M_AXI_GP1_AWVALID => M_AXI_GP1_AWVALID, M_AXI_GP1_BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0), M_AXI_GP1_BREADY => M_AXI_GP1_BREADY, M_AXI_GP1_BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0), M_AXI_GP1_BVALID => M_AXI_GP1_BVALID, M_AXI_GP1_RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0), M_AXI_GP1_RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0), M_AXI_GP1_RLAST => M_AXI_GP1_RLAST, M_AXI_GP1_RREADY => M_AXI_GP1_RREADY, M_AXI_GP1_RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0), M_AXI_GP1_RVALID => M_AXI_GP1_RVALID, M_AXI_GP1_WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0), M_AXI_GP1_WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0), M_AXI_GP1_WLAST => M_AXI_GP1_WLAST, M_AXI_GP1_WREADY => M_AXI_GP1_WREADY, M_AXI_GP1_WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0), M_AXI_GP1_WVALID => M_AXI_GP1_WVALID, PJTAG_TCK => '0', PJTAG_TDI => '0', PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED, PJTAG_TMS => '0', PS_CLK => PS_CLK, PS_PORB => PS_PORB, PS_SRSTB => PS_SRSTB, SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED, SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0), SDIO0_CDN => '0', SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED, SDIO0_CLK_FB => '0', SDIO0_CMD_I => '0', SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED, SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED, SDIO0_DATA_I(3) => '0', SDIO0_DATA_I(2) => '0', SDIO0_DATA_I(1) => '0', SDIO0_DATA_I(0) => '0', SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0), SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0), SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED, SDIO0_WP => '0', SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED, SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0), SDIO1_CDN => '0', SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED, SDIO1_CLK_FB => '0', SDIO1_CMD_I => '0', SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED, SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED, SDIO1_DATA_I(3) => '0', SDIO1_DATA_I(2) => '0', SDIO1_DATA_I(1) => '0', SDIO1_DATA_I(0) => '0', SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0), SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0), SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED, SDIO1_WP => '0', SPI0_MISO_I => '0', SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED, SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED, SPI0_MOSI_I => '0', SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED, SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED, SPI0_SCLK_I => '0', SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED, SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED, SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED, SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED, SPI0_SS_I => '0', SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED, SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED, SPI1_MISO_I => '0', SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED, SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED, SPI1_MOSI_I => '0', SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED, SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED, SPI1_SCLK_I => '0', SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED, SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED, SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED, SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED, SPI1_SS_I => '0', SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED, SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED, SRAM_INTIN => '0', S_AXI_ACP_ACLK => '0', S_AXI_ACP_ARADDR(31) => '0', S_AXI_ACP_ARADDR(30) => '0', S_AXI_ACP_ARADDR(29) => '0', S_AXI_ACP_ARADDR(28) => '0', S_AXI_ACP_ARADDR(27) => '0', S_AXI_ACP_ARADDR(26) => '0', S_AXI_ACP_ARADDR(25) => '0', S_AXI_ACP_ARADDR(24) => '0', S_AXI_ACP_ARADDR(23) => '0', S_AXI_ACP_ARADDR(22) => '0', S_AXI_ACP_ARADDR(21) => '0', S_AXI_ACP_ARADDR(20) => '0', S_AXI_ACP_ARADDR(19) => '0', S_AXI_ACP_ARADDR(18) => '0', S_AXI_ACP_ARADDR(17) => '0', S_AXI_ACP_ARADDR(16) => '0', S_AXI_ACP_ARADDR(15) => '0', S_AXI_ACP_ARADDR(14) => '0', S_AXI_ACP_ARADDR(13) => '0', S_AXI_ACP_ARADDR(12) => '0', S_AXI_ACP_ARADDR(11) => '0', S_AXI_ACP_ARADDR(10) => '0', S_AXI_ACP_ARADDR(9) => '0', S_AXI_ACP_ARADDR(8) => '0', S_AXI_ACP_ARADDR(7) => '0', S_AXI_ACP_ARADDR(6) => '0', S_AXI_ACP_ARADDR(5) => '0', S_AXI_ACP_ARADDR(4) => '0', S_AXI_ACP_ARADDR(3) => '0', S_AXI_ACP_ARADDR(2) => '0', S_AXI_ACP_ARADDR(1) => '0', S_AXI_ACP_ARADDR(0) => '0', S_AXI_ACP_ARBURST(1) => '0', S_AXI_ACP_ARBURST(0) => '0', S_AXI_ACP_ARCACHE(3) => '0', S_AXI_ACP_ARCACHE(2) => '0', S_AXI_ACP_ARCACHE(1) => '0', S_AXI_ACP_ARCACHE(0) => '0', S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED, S_AXI_ACP_ARID(2) => '0', S_AXI_ACP_ARID(1) => '0', S_AXI_ACP_ARID(0) => '0', S_AXI_ACP_ARLEN(3) => '0', S_AXI_ACP_ARLEN(2) => '0', S_AXI_ACP_ARLEN(1) => '0', S_AXI_ACP_ARLEN(0) => '0', S_AXI_ACP_ARLOCK(1) => '0', S_AXI_ACP_ARLOCK(0) => '0', S_AXI_ACP_ARPROT(2) => '0', S_AXI_ACP_ARPROT(1) => '0', S_AXI_ACP_ARPROT(0) => '0', S_AXI_ACP_ARQOS(3) => '0', S_AXI_ACP_ARQOS(2) => '0', S_AXI_ACP_ARQOS(1) => '0', S_AXI_ACP_ARQOS(0) => '0', S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED, S_AXI_ACP_ARSIZE(2) => '0', S_AXI_ACP_ARSIZE(1) => '0', S_AXI_ACP_ARSIZE(0) => '0', S_AXI_ACP_ARUSER(4) => '0', S_AXI_ACP_ARUSER(3) => '0', S_AXI_ACP_ARUSER(2) => '0', S_AXI_ACP_ARUSER(1) => '0', S_AXI_ACP_ARUSER(0) => '0', S_AXI_ACP_ARVALID => '0', S_AXI_ACP_AWADDR(31) => '0', S_AXI_ACP_AWADDR(30) => '0', S_AXI_ACP_AWADDR(29) => '0', S_AXI_ACP_AWADDR(28) => '0', S_AXI_ACP_AWADDR(27) => '0', S_AXI_ACP_AWADDR(26) => '0', S_AXI_ACP_AWADDR(25) => '0', S_AXI_ACP_AWADDR(24) => '0', S_AXI_ACP_AWADDR(23) => '0', S_AXI_ACP_AWADDR(22) => '0', S_AXI_ACP_AWADDR(21) => '0', S_AXI_ACP_AWADDR(20) => '0', S_AXI_ACP_AWADDR(19) => '0', S_AXI_ACP_AWADDR(18) => '0', S_AXI_ACP_AWADDR(17) => '0', S_AXI_ACP_AWADDR(16) => '0', S_AXI_ACP_AWADDR(15) => '0', S_AXI_ACP_AWADDR(14) => '0', S_AXI_ACP_AWADDR(13) => '0', S_AXI_ACP_AWADDR(12) => '0', S_AXI_ACP_AWADDR(11) => '0', S_AXI_ACP_AWADDR(10) => '0', S_AXI_ACP_AWADDR(9) => '0', S_AXI_ACP_AWADDR(8) => '0', S_AXI_ACP_AWADDR(7) => '0', S_AXI_ACP_AWADDR(6) => '0', S_AXI_ACP_AWADDR(5) => '0', S_AXI_ACP_AWADDR(4) => '0', S_AXI_ACP_AWADDR(3) => '0', S_AXI_ACP_AWADDR(2) => '0', S_AXI_ACP_AWADDR(1) => '0', S_AXI_ACP_AWADDR(0) => '0', S_AXI_ACP_AWBURST(1) => '0', S_AXI_ACP_AWBURST(0) => '0', S_AXI_ACP_AWCACHE(3) => '0', S_AXI_ACP_AWCACHE(2) => '0', S_AXI_ACP_AWCACHE(1) => '0', S_AXI_ACP_AWCACHE(0) => '0', S_AXI_ACP_AWID(2) => '0', S_AXI_ACP_AWID(1) => '0', S_AXI_ACP_AWID(0) => '0', S_AXI_ACP_AWLEN(3) => '0', S_AXI_ACP_AWLEN(2) => '0', S_AXI_ACP_AWLEN(1) => '0', S_AXI_ACP_AWLEN(0) => '0', S_AXI_ACP_AWLOCK(1) => '0', S_AXI_ACP_AWLOCK(0) => '0', S_AXI_ACP_AWPROT(2) => '0', S_AXI_ACP_AWPROT(1) => '0', S_AXI_ACP_AWPROT(0) => '0', S_AXI_ACP_AWQOS(3) => '0', S_AXI_ACP_AWQOS(2) => '0', S_AXI_ACP_AWQOS(1) => '0', S_AXI_ACP_AWQOS(0) => '0', S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED, S_AXI_ACP_AWSIZE(2) => '0', S_AXI_ACP_AWSIZE(1) => '0', S_AXI_ACP_AWSIZE(0) => '0', S_AXI_ACP_AWUSER(4) => '0', S_AXI_ACP_AWUSER(3) => '0', S_AXI_ACP_AWUSER(2) => '0', S_AXI_ACP_AWUSER(1) => '0', S_AXI_ACP_AWUSER(0) => '0', S_AXI_ACP_AWVALID => '0', S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0), S_AXI_ACP_BREADY => '0', S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED, S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0), S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0), S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED, S_AXI_ACP_RREADY => '0', S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED, S_AXI_ACP_WDATA(63) => '0', S_AXI_ACP_WDATA(62) => '0', S_AXI_ACP_WDATA(61) => '0', S_AXI_ACP_WDATA(60) => '0', S_AXI_ACP_WDATA(59) => '0', S_AXI_ACP_WDATA(58) => '0', S_AXI_ACP_WDATA(57) => '0', S_AXI_ACP_WDATA(56) => '0', S_AXI_ACP_WDATA(55) => '0', S_AXI_ACP_WDATA(54) => '0', S_AXI_ACP_WDATA(53) => '0', S_AXI_ACP_WDATA(52) => '0', S_AXI_ACP_WDATA(51) => '0', S_AXI_ACP_WDATA(50) => '0', S_AXI_ACP_WDATA(49) => '0', S_AXI_ACP_WDATA(48) => '0', S_AXI_ACP_WDATA(47) => '0', S_AXI_ACP_WDATA(46) => '0', S_AXI_ACP_WDATA(45) => '0', S_AXI_ACP_WDATA(44) => '0', S_AXI_ACP_WDATA(43) => '0', S_AXI_ACP_WDATA(42) => '0', S_AXI_ACP_WDATA(41) => '0', S_AXI_ACP_WDATA(40) => '0', S_AXI_ACP_WDATA(39) => '0', S_AXI_ACP_WDATA(38) => '0', S_AXI_ACP_WDATA(37) => '0', S_AXI_ACP_WDATA(36) => '0', S_AXI_ACP_WDATA(35) => '0', S_AXI_ACP_WDATA(34) => '0', S_AXI_ACP_WDATA(33) => '0', S_AXI_ACP_WDATA(32) => '0', S_AXI_ACP_WDATA(31) => '0', S_AXI_ACP_WDATA(30) => '0', S_AXI_ACP_WDATA(29) => '0', S_AXI_ACP_WDATA(28) => '0', S_AXI_ACP_WDATA(27) => '0', S_AXI_ACP_WDATA(26) => '0', S_AXI_ACP_WDATA(25) => '0', S_AXI_ACP_WDATA(24) => '0', S_AXI_ACP_WDATA(23) => '0', S_AXI_ACP_WDATA(22) => '0', S_AXI_ACP_WDATA(21) => '0', S_AXI_ACP_WDATA(20) => '0', S_AXI_ACP_WDATA(19) => '0', S_AXI_ACP_WDATA(18) => '0', S_AXI_ACP_WDATA(17) => '0', S_AXI_ACP_WDATA(16) => '0', S_AXI_ACP_WDATA(15) => '0', S_AXI_ACP_WDATA(14) => '0', S_AXI_ACP_WDATA(13) => '0', S_AXI_ACP_WDATA(12) => '0', S_AXI_ACP_WDATA(11) => '0', S_AXI_ACP_WDATA(10) => '0', S_AXI_ACP_WDATA(9) => '0', S_AXI_ACP_WDATA(8) => '0', S_AXI_ACP_WDATA(7) => '0', S_AXI_ACP_WDATA(6) => '0', S_AXI_ACP_WDATA(5) => '0', S_AXI_ACP_WDATA(4) => '0', S_AXI_ACP_WDATA(3) => '0', S_AXI_ACP_WDATA(2) => '0', S_AXI_ACP_WDATA(1) => '0', S_AXI_ACP_WDATA(0) => '0', S_AXI_ACP_WID(2) => '0', S_AXI_ACP_WID(1) => '0', S_AXI_ACP_WID(0) => '0', S_AXI_ACP_WLAST => '0', S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED, S_AXI_ACP_WSTRB(7) => '0', S_AXI_ACP_WSTRB(6) => '0', S_AXI_ACP_WSTRB(5) => '0', S_AXI_ACP_WSTRB(4) => '0', S_AXI_ACP_WSTRB(3) => '0', S_AXI_ACP_WSTRB(2) => '0', S_AXI_ACP_WSTRB(1) => '0', S_AXI_ACP_WSTRB(0) => '0', S_AXI_ACP_WVALID => '0', S_AXI_GP0_ACLK => '0', S_AXI_GP0_ARADDR(31) => '0', S_AXI_GP0_ARADDR(30) => '0', S_AXI_GP0_ARADDR(29) => '0', S_AXI_GP0_ARADDR(28) => '0', S_AXI_GP0_ARADDR(27) => '0', S_AXI_GP0_ARADDR(26) => '0', S_AXI_GP0_ARADDR(25) => '0', S_AXI_GP0_ARADDR(24) => '0', S_AXI_GP0_ARADDR(23) => '0', S_AXI_GP0_ARADDR(22) => '0', S_AXI_GP0_ARADDR(21) => '0', S_AXI_GP0_ARADDR(20) => '0', S_AXI_GP0_ARADDR(19) => '0', S_AXI_GP0_ARADDR(18) => '0', S_AXI_GP0_ARADDR(17) => '0', S_AXI_GP0_ARADDR(16) => '0', S_AXI_GP0_ARADDR(15) => '0', S_AXI_GP0_ARADDR(14) => '0', S_AXI_GP0_ARADDR(13) => '0', S_AXI_GP0_ARADDR(12) => '0', S_AXI_GP0_ARADDR(11) => '0', S_AXI_GP0_ARADDR(10) => '0', S_AXI_GP0_ARADDR(9) => '0', S_AXI_GP0_ARADDR(8) => '0', S_AXI_GP0_ARADDR(7) => '0', S_AXI_GP0_ARADDR(6) => '0', S_AXI_GP0_ARADDR(5) => '0', S_AXI_GP0_ARADDR(4) => '0', S_AXI_GP0_ARADDR(3) => '0', S_AXI_GP0_ARADDR(2) => '0', S_AXI_GP0_ARADDR(1) => '0', S_AXI_GP0_ARADDR(0) => '0', S_AXI_GP0_ARBURST(1) => '0', S_AXI_GP0_ARBURST(0) => '0', S_AXI_GP0_ARCACHE(3) => '0', S_AXI_GP0_ARCACHE(2) => '0', S_AXI_GP0_ARCACHE(1) => '0', S_AXI_GP0_ARCACHE(0) => '0', S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED, S_AXI_GP0_ARID(5) => '0', S_AXI_GP0_ARID(4) => '0', S_AXI_GP0_ARID(3) => '0', S_AXI_GP0_ARID(2) => '0', S_AXI_GP0_ARID(1) => '0', S_AXI_GP0_ARID(0) => '0', S_AXI_GP0_ARLEN(3) => '0', S_AXI_GP0_ARLEN(2) => '0', S_AXI_GP0_ARLEN(1) => '0', S_AXI_GP0_ARLEN(0) => '0', S_AXI_GP0_ARLOCK(1) => '0', S_AXI_GP0_ARLOCK(0) => '0', S_AXI_GP0_ARPROT(2) => '0', S_AXI_GP0_ARPROT(1) => '0', S_AXI_GP0_ARPROT(0) => '0', S_AXI_GP0_ARQOS(3) => '0', S_AXI_GP0_ARQOS(2) => '0', S_AXI_GP0_ARQOS(1) => '0', S_AXI_GP0_ARQOS(0) => '0', S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED, S_AXI_GP0_ARSIZE(2) => '0', S_AXI_GP0_ARSIZE(1) => '0', S_AXI_GP0_ARSIZE(0) => '0', S_AXI_GP0_ARVALID => '0', S_AXI_GP0_AWADDR(31) => '0', S_AXI_GP0_AWADDR(30) => '0', S_AXI_GP0_AWADDR(29) => '0', S_AXI_GP0_AWADDR(28) => '0', S_AXI_GP0_AWADDR(27) => '0', S_AXI_GP0_AWADDR(26) => '0', S_AXI_GP0_AWADDR(25) => '0', S_AXI_GP0_AWADDR(24) => '0', S_AXI_GP0_AWADDR(23) => '0', S_AXI_GP0_AWADDR(22) => '0', S_AXI_GP0_AWADDR(21) => '0', S_AXI_GP0_AWADDR(20) => '0', S_AXI_GP0_AWADDR(19) => '0', S_AXI_GP0_AWADDR(18) => '0', S_AXI_GP0_AWADDR(17) => '0', S_AXI_GP0_AWADDR(16) => '0', S_AXI_GP0_AWADDR(15) => '0', S_AXI_GP0_AWADDR(14) => '0', S_AXI_GP0_AWADDR(13) => '0', S_AXI_GP0_AWADDR(12) => '0', S_AXI_GP0_AWADDR(11) => '0', S_AXI_GP0_AWADDR(10) => '0', S_AXI_GP0_AWADDR(9) => '0', S_AXI_GP0_AWADDR(8) => '0', S_AXI_GP0_AWADDR(7) => '0', S_AXI_GP0_AWADDR(6) => '0', S_AXI_GP0_AWADDR(5) => '0', S_AXI_GP0_AWADDR(4) => '0', S_AXI_GP0_AWADDR(3) => '0', S_AXI_GP0_AWADDR(2) => '0', S_AXI_GP0_AWADDR(1) => '0', S_AXI_GP0_AWADDR(0) => '0', S_AXI_GP0_AWBURST(1) => '0', S_AXI_GP0_AWBURST(0) => '0', S_AXI_GP0_AWCACHE(3) => '0', S_AXI_GP0_AWCACHE(2) => '0', S_AXI_GP0_AWCACHE(1) => '0', S_AXI_GP0_AWCACHE(0) => '0', S_AXI_GP0_AWID(5) => '0', S_AXI_GP0_AWID(4) => '0', S_AXI_GP0_AWID(3) => '0', S_AXI_GP0_AWID(2) => '0', S_AXI_GP0_AWID(1) => '0', S_AXI_GP0_AWID(0) => '0', S_AXI_GP0_AWLEN(3) => '0', S_AXI_GP0_AWLEN(2) => '0', S_AXI_GP0_AWLEN(1) => '0', S_AXI_GP0_AWLEN(0) => '0', S_AXI_GP0_AWLOCK(1) => '0', S_AXI_GP0_AWLOCK(0) => '0', S_AXI_GP0_AWPROT(2) => '0', S_AXI_GP0_AWPROT(1) => '0', S_AXI_GP0_AWPROT(0) => '0', S_AXI_GP0_AWQOS(3) => '0', S_AXI_GP0_AWQOS(2) => '0', S_AXI_GP0_AWQOS(1) => '0', S_AXI_GP0_AWQOS(0) => '0', S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED, S_AXI_GP0_AWSIZE(2) => '0', S_AXI_GP0_AWSIZE(1) => '0', S_AXI_GP0_AWSIZE(0) => '0', S_AXI_GP0_AWVALID => '0', S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0), S_AXI_GP0_BREADY => '0', S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED, S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0), S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED, S_AXI_GP0_RREADY => '0', S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED, S_AXI_GP0_WDATA(31) => '0', S_AXI_GP0_WDATA(30) => '0', S_AXI_GP0_WDATA(29) => '0', S_AXI_GP0_WDATA(28) => '0', S_AXI_GP0_WDATA(27) => '0', S_AXI_GP0_WDATA(26) => '0', S_AXI_GP0_WDATA(25) => '0', S_AXI_GP0_WDATA(24) => '0', S_AXI_GP0_WDATA(23) => '0', S_AXI_GP0_WDATA(22) => '0', S_AXI_GP0_WDATA(21) => '0', S_AXI_GP0_WDATA(20) => '0', S_AXI_GP0_WDATA(19) => '0', S_AXI_GP0_WDATA(18) => '0', S_AXI_GP0_WDATA(17) => '0', S_AXI_GP0_WDATA(16) => '0', S_AXI_GP0_WDATA(15) => '0', S_AXI_GP0_WDATA(14) => '0', S_AXI_GP0_WDATA(13) => '0', S_AXI_GP0_WDATA(12) => '0', S_AXI_GP0_WDATA(11) => '0', S_AXI_GP0_WDATA(10) => '0', S_AXI_GP0_WDATA(9) => '0', S_AXI_GP0_WDATA(8) => '0', S_AXI_GP0_WDATA(7) => '0', S_AXI_GP0_WDATA(6) => '0', S_AXI_GP0_WDATA(5) => '0', S_AXI_GP0_WDATA(4) => '0', S_AXI_GP0_WDATA(3) => '0', S_AXI_GP0_WDATA(2) => '0', S_AXI_GP0_WDATA(1) => '0', S_AXI_GP0_WDATA(0) => '0', S_AXI_GP0_WID(5) => '0', S_AXI_GP0_WID(4) => '0', S_AXI_GP0_WID(3) => '0', S_AXI_GP0_WID(2) => '0', S_AXI_GP0_WID(1) => '0', S_AXI_GP0_WID(0) => '0', S_AXI_GP0_WLAST => '0', S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED, S_AXI_GP0_WSTRB(3) => '0', S_AXI_GP0_WSTRB(2) => '0', S_AXI_GP0_WSTRB(1) => '0', S_AXI_GP0_WSTRB(0) => '0', S_AXI_GP0_WVALID => '0', S_AXI_GP1_ACLK => '0', S_AXI_GP1_ARADDR(31) => '0', S_AXI_GP1_ARADDR(30) => '0', S_AXI_GP1_ARADDR(29) => '0', S_AXI_GP1_ARADDR(28) => '0', S_AXI_GP1_ARADDR(27) => '0', S_AXI_GP1_ARADDR(26) => '0', S_AXI_GP1_ARADDR(25) => '0', S_AXI_GP1_ARADDR(24) => '0', S_AXI_GP1_ARADDR(23) => '0', S_AXI_GP1_ARADDR(22) => '0', S_AXI_GP1_ARADDR(21) => '0', S_AXI_GP1_ARADDR(20) => '0', S_AXI_GP1_ARADDR(19) => '0', S_AXI_GP1_ARADDR(18) => '0', S_AXI_GP1_ARADDR(17) => '0', S_AXI_GP1_ARADDR(16) => '0', S_AXI_GP1_ARADDR(15) => '0', S_AXI_GP1_ARADDR(14) => '0', S_AXI_GP1_ARADDR(13) => '0', S_AXI_GP1_ARADDR(12) => '0', S_AXI_GP1_ARADDR(11) => '0', S_AXI_GP1_ARADDR(10) => '0', S_AXI_GP1_ARADDR(9) => '0', S_AXI_GP1_ARADDR(8) => '0', S_AXI_GP1_ARADDR(7) => '0', S_AXI_GP1_ARADDR(6) => '0', S_AXI_GP1_ARADDR(5) => '0', S_AXI_GP1_ARADDR(4) => '0', S_AXI_GP1_ARADDR(3) => '0', S_AXI_GP1_ARADDR(2) => '0', S_AXI_GP1_ARADDR(1) => '0', S_AXI_GP1_ARADDR(0) => '0', S_AXI_GP1_ARBURST(1) => '0', S_AXI_GP1_ARBURST(0) => '0', S_AXI_GP1_ARCACHE(3) => '0', S_AXI_GP1_ARCACHE(2) => '0', S_AXI_GP1_ARCACHE(1) => '0', S_AXI_GP1_ARCACHE(0) => '0', S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED, S_AXI_GP1_ARID(5) => '0', S_AXI_GP1_ARID(4) => '0', S_AXI_GP1_ARID(3) => '0', S_AXI_GP1_ARID(2) => '0', S_AXI_GP1_ARID(1) => '0', S_AXI_GP1_ARID(0) => '0', S_AXI_GP1_ARLEN(3) => '0', S_AXI_GP1_ARLEN(2) => '0', S_AXI_GP1_ARLEN(1) => '0', S_AXI_GP1_ARLEN(0) => '0', S_AXI_GP1_ARLOCK(1) => '0', S_AXI_GP1_ARLOCK(0) => '0', S_AXI_GP1_ARPROT(2) => '0', S_AXI_GP1_ARPROT(1) => '0', S_AXI_GP1_ARPROT(0) => '0', S_AXI_GP1_ARQOS(3) => '0', S_AXI_GP1_ARQOS(2) => '0', S_AXI_GP1_ARQOS(1) => '0', S_AXI_GP1_ARQOS(0) => '0', S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED, S_AXI_GP1_ARSIZE(2) => '0', S_AXI_GP1_ARSIZE(1) => '0', S_AXI_GP1_ARSIZE(0) => '0', S_AXI_GP1_ARVALID => '0', S_AXI_GP1_AWADDR(31) => '0', S_AXI_GP1_AWADDR(30) => '0', S_AXI_GP1_AWADDR(29) => '0', S_AXI_GP1_AWADDR(28) => '0', S_AXI_GP1_AWADDR(27) => '0', S_AXI_GP1_AWADDR(26) => '0', S_AXI_GP1_AWADDR(25) => '0', S_AXI_GP1_AWADDR(24) => '0', S_AXI_GP1_AWADDR(23) => '0', S_AXI_GP1_AWADDR(22) => '0', S_AXI_GP1_AWADDR(21) => '0', S_AXI_GP1_AWADDR(20) => '0', S_AXI_GP1_AWADDR(19) => '0', S_AXI_GP1_AWADDR(18) => '0', S_AXI_GP1_AWADDR(17) => '0', S_AXI_GP1_AWADDR(16) => '0', S_AXI_GP1_AWADDR(15) => '0', S_AXI_GP1_AWADDR(14) => '0', S_AXI_GP1_AWADDR(13) => '0', S_AXI_GP1_AWADDR(12) => '0', S_AXI_GP1_AWADDR(11) => '0', S_AXI_GP1_AWADDR(10) => '0', S_AXI_GP1_AWADDR(9) => '0', S_AXI_GP1_AWADDR(8) => '0', S_AXI_GP1_AWADDR(7) => '0', S_AXI_GP1_AWADDR(6) => '0', S_AXI_GP1_AWADDR(5) => '0', S_AXI_GP1_AWADDR(4) => '0', S_AXI_GP1_AWADDR(3) => '0', S_AXI_GP1_AWADDR(2) => '0', S_AXI_GP1_AWADDR(1) => '0', S_AXI_GP1_AWADDR(0) => '0', S_AXI_GP1_AWBURST(1) => '0', S_AXI_GP1_AWBURST(0) => '0', S_AXI_GP1_AWCACHE(3) => '0', S_AXI_GP1_AWCACHE(2) => '0', S_AXI_GP1_AWCACHE(1) => '0', S_AXI_GP1_AWCACHE(0) => '0', S_AXI_GP1_AWID(5) => '0', S_AXI_GP1_AWID(4) => '0', S_AXI_GP1_AWID(3) => '0', S_AXI_GP1_AWID(2) => '0', S_AXI_GP1_AWID(1) => '0', S_AXI_GP1_AWID(0) => '0', S_AXI_GP1_AWLEN(3) => '0', S_AXI_GP1_AWLEN(2) => '0', S_AXI_GP1_AWLEN(1) => '0', S_AXI_GP1_AWLEN(0) => '0', S_AXI_GP1_AWLOCK(1) => '0', S_AXI_GP1_AWLOCK(0) => '0', S_AXI_GP1_AWPROT(2) => '0', S_AXI_GP1_AWPROT(1) => '0', S_AXI_GP1_AWPROT(0) => '0', S_AXI_GP1_AWQOS(3) => '0', S_AXI_GP1_AWQOS(2) => '0', S_AXI_GP1_AWQOS(1) => '0', S_AXI_GP1_AWQOS(0) => '0', S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED, S_AXI_GP1_AWSIZE(2) => '0', S_AXI_GP1_AWSIZE(1) => '0', S_AXI_GP1_AWSIZE(0) => '0', S_AXI_GP1_AWVALID => '0', S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0), S_AXI_GP1_BREADY => '0', S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED, S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0), S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED, S_AXI_GP1_RREADY => '0', S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED, S_AXI_GP1_WDATA(31) => '0', S_AXI_GP1_WDATA(30) => '0', S_AXI_GP1_WDATA(29) => '0', S_AXI_GP1_WDATA(28) => '0', S_AXI_GP1_WDATA(27) => '0', S_AXI_GP1_WDATA(26) => '0', S_AXI_GP1_WDATA(25) => '0', S_AXI_GP1_WDATA(24) => '0', S_AXI_GP1_WDATA(23) => '0', S_AXI_GP1_WDATA(22) => '0', S_AXI_GP1_WDATA(21) => '0', S_AXI_GP1_WDATA(20) => '0', S_AXI_GP1_WDATA(19) => '0', S_AXI_GP1_WDATA(18) => '0', S_AXI_GP1_WDATA(17) => '0', S_AXI_GP1_WDATA(16) => '0', S_AXI_GP1_WDATA(15) => '0', S_AXI_GP1_WDATA(14) => '0', S_AXI_GP1_WDATA(13) => '0', S_AXI_GP1_WDATA(12) => '0', S_AXI_GP1_WDATA(11) => '0', S_AXI_GP1_WDATA(10) => '0', S_AXI_GP1_WDATA(9) => '0', S_AXI_GP1_WDATA(8) => '0', S_AXI_GP1_WDATA(7) => '0', S_AXI_GP1_WDATA(6) => '0', S_AXI_GP1_WDATA(5) => '0', S_AXI_GP1_WDATA(4) => '0', S_AXI_GP1_WDATA(3) => '0', S_AXI_GP1_WDATA(2) => '0', S_AXI_GP1_WDATA(1) => '0', S_AXI_GP1_WDATA(0) => '0', S_AXI_GP1_WID(5) => '0', S_AXI_GP1_WID(4) => '0', S_AXI_GP1_WID(3) => '0', S_AXI_GP1_WID(2) => '0', S_AXI_GP1_WID(1) => '0', S_AXI_GP1_WID(0) => '0', S_AXI_GP1_WLAST => '0', S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED, S_AXI_GP1_WSTRB(3) => '0', S_AXI_GP1_WSTRB(2) => '0', S_AXI_GP1_WSTRB(1) => '0', S_AXI_GP1_WSTRB(0) => '0', S_AXI_GP1_WVALID => '0', S_AXI_HP0_ACLK => '0', S_AXI_HP0_ARADDR(31) => '0', S_AXI_HP0_ARADDR(30) => '0', S_AXI_HP0_ARADDR(29) => '0', S_AXI_HP0_ARADDR(28) => '0', S_AXI_HP0_ARADDR(27) => '0', S_AXI_HP0_ARADDR(26) => '0', S_AXI_HP0_ARADDR(25) => '0', S_AXI_HP0_ARADDR(24) => '0', S_AXI_HP0_ARADDR(23) => '0', S_AXI_HP0_ARADDR(22) => '0', S_AXI_HP0_ARADDR(21) => '0', S_AXI_HP0_ARADDR(20) => '0', S_AXI_HP0_ARADDR(19) => '0', S_AXI_HP0_ARADDR(18) => '0', S_AXI_HP0_ARADDR(17) => '0', S_AXI_HP0_ARADDR(16) => '0', S_AXI_HP0_ARADDR(15) => '0', S_AXI_HP0_ARADDR(14) => '0', S_AXI_HP0_ARADDR(13) => '0', S_AXI_HP0_ARADDR(12) => '0', S_AXI_HP0_ARADDR(11) => '0', S_AXI_HP0_ARADDR(10) => '0', S_AXI_HP0_ARADDR(9) => '0', S_AXI_HP0_ARADDR(8) => '0', S_AXI_HP0_ARADDR(7) => '0', S_AXI_HP0_ARADDR(6) => '0', S_AXI_HP0_ARADDR(5) => '0', S_AXI_HP0_ARADDR(4) => '0', S_AXI_HP0_ARADDR(3) => '0', S_AXI_HP0_ARADDR(2) => '0', S_AXI_HP0_ARADDR(1) => '0', S_AXI_HP0_ARADDR(0) => '0', S_AXI_HP0_ARBURST(1) => '0', S_AXI_HP0_ARBURST(0) => '0', S_AXI_HP0_ARCACHE(3) => '0', S_AXI_HP0_ARCACHE(2) => '0', S_AXI_HP0_ARCACHE(1) => '0', S_AXI_HP0_ARCACHE(0) => '0', S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED, S_AXI_HP0_ARID(5) => '0', S_AXI_HP0_ARID(4) => '0', S_AXI_HP0_ARID(3) => '0', S_AXI_HP0_ARID(2) => '0', S_AXI_HP0_ARID(1) => '0', S_AXI_HP0_ARID(0) => '0', S_AXI_HP0_ARLEN(3) => '0', S_AXI_HP0_ARLEN(2) => '0', S_AXI_HP0_ARLEN(1) => '0', S_AXI_HP0_ARLEN(0) => '0', S_AXI_HP0_ARLOCK(1) => '0', S_AXI_HP0_ARLOCK(0) => '0', S_AXI_HP0_ARPROT(2) => '0', S_AXI_HP0_ARPROT(1) => '0', S_AXI_HP0_ARPROT(0) => '0', S_AXI_HP0_ARQOS(3) => '0', S_AXI_HP0_ARQOS(2) => '0', S_AXI_HP0_ARQOS(1) => '0', S_AXI_HP0_ARQOS(0) => '0', S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED, S_AXI_HP0_ARSIZE(2) => '0', S_AXI_HP0_ARSIZE(1) => '0', S_AXI_HP0_ARSIZE(0) => '0', S_AXI_HP0_ARVALID => '0', S_AXI_HP0_AWADDR(31) => '0', S_AXI_HP0_AWADDR(30) => '0', S_AXI_HP0_AWADDR(29) => '0', S_AXI_HP0_AWADDR(28) => '0', S_AXI_HP0_AWADDR(27) => '0', S_AXI_HP0_AWADDR(26) => '0', S_AXI_HP0_AWADDR(25) => '0', S_AXI_HP0_AWADDR(24) => '0', S_AXI_HP0_AWADDR(23) => '0', S_AXI_HP0_AWADDR(22) => '0', S_AXI_HP0_AWADDR(21) => '0', S_AXI_HP0_AWADDR(20) => '0', S_AXI_HP0_AWADDR(19) => '0', S_AXI_HP0_AWADDR(18) => '0', S_AXI_HP0_AWADDR(17) => '0', S_AXI_HP0_AWADDR(16) => '0', S_AXI_HP0_AWADDR(15) => '0', S_AXI_HP0_AWADDR(14) => '0', S_AXI_HP0_AWADDR(13) => '0', S_AXI_HP0_AWADDR(12) => '0', S_AXI_HP0_AWADDR(11) => '0', S_AXI_HP0_AWADDR(10) => '0', S_AXI_HP0_AWADDR(9) => '0', S_AXI_HP0_AWADDR(8) => '0', S_AXI_HP0_AWADDR(7) => '0', S_AXI_HP0_AWADDR(6) => '0', S_AXI_HP0_AWADDR(5) => '0', S_AXI_HP0_AWADDR(4) => '0', S_AXI_HP0_AWADDR(3) => '0', S_AXI_HP0_AWADDR(2) => '0', S_AXI_HP0_AWADDR(1) => '0', S_AXI_HP0_AWADDR(0) => '0', S_AXI_HP0_AWBURST(1) => '0', S_AXI_HP0_AWBURST(0) => '0', S_AXI_HP0_AWCACHE(3) => '0', S_AXI_HP0_AWCACHE(2) => '0', S_AXI_HP0_AWCACHE(1) => '0', S_AXI_HP0_AWCACHE(0) => '0', S_AXI_HP0_AWID(5) => '0', S_AXI_HP0_AWID(4) => '0', S_AXI_HP0_AWID(3) => '0', S_AXI_HP0_AWID(2) => '0', S_AXI_HP0_AWID(1) => '0', S_AXI_HP0_AWID(0) => '0', S_AXI_HP0_AWLEN(3) => '0', S_AXI_HP0_AWLEN(2) => '0', S_AXI_HP0_AWLEN(1) => '0', S_AXI_HP0_AWLEN(0) => '0', S_AXI_HP0_AWLOCK(1) => '0', S_AXI_HP0_AWLOCK(0) => '0', S_AXI_HP0_AWPROT(2) => '0', S_AXI_HP0_AWPROT(1) => '0', S_AXI_HP0_AWPROT(0) => '0', S_AXI_HP0_AWQOS(3) => '0', S_AXI_HP0_AWQOS(2) => '0', S_AXI_HP0_AWQOS(1) => '0', S_AXI_HP0_AWQOS(0) => '0', S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED, S_AXI_HP0_AWSIZE(2) => '0', S_AXI_HP0_AWSIZE(1) => '0', S_AXI_HP0_AWSIZE(0) => '0', S_AXI_HP0_AWVALID => '0', S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0), S_AXI_HP0_BREADY => '0', S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED, S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_RDATA(31 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(31 downto 0), S_AXI_HP0_RDISSUECAP1_EN => '0', S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0), S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED, S_AXI_HP0_RREADY => '0', S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED, S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_WDATA(31) => '0', S_AXI_HP0_WDATA(30) => '0', S_AXI_HP0_WDATA(29) => '0', S_AXI_HP0_WDATA(28) => '0', S_AXI_HP0_WDATA(27) => '0', S_AXI_HP0_WDATA(26) => '0', S_AXI_HP0_WDATA(25) => '0', S_AXI_HP0_WDATA(24) => '0', S_AXI_HP0_WDATA(23) => '0', S_AXI_HP0_WDATA(22) => '0', S_AXI_HP0_WDATA(21) => '0', S_AXI_HP0_WDATA(20) => '0', S_AXI_HP0_WDATA(19) => '0', S_AXI_HP0_WDATA(18) => '0', S_AXI_HP0_WDATA(17) => '0', S_AXI_HP0_WDATA(16) => '0', S_AXI_HP0_WDATA(15) => '0', S_AXI_HP0_WDATA(14) => '0', S_AXI_HP0_WDATA(13) => '0', S_AXI_HP0_WDATA(12) => '0', S_AXI_HP0_WDATA(11) => '0', S_AXI_HP0_WDATA(10) => '0', S_AXI_HP0_WDATA(9) => '0', S_AXI_HP0_WDATA(8) => '0', S_AXI_HP0_WDATA(7) => '0', S_AXI_HP0_WDATA(6) => '0', S_AXI_HP0_WDATA(5) => '0', S_AXI_HP0_WDATA(4) => '0', S_AXI_HP0_WDATA(3) => '0', S_AXI_HP0_WDATA(2) => '0', S_AXI_HP0_WDATA(1) => '0', S_AXI_HP0_WDATA(0) => '0', S_AXI_HP0_WID(5) => '0', S_AXI_HP0_WID(4) => '0', S_AXI_HP0_WID(3) => '0', S_AXI_HP0_WID(2) => '0', S_AXI_HP0_WID(1) => '0', S_AXI_HP0_WID(0) => '0', S_AXI_HP0_WLAST => '0', S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED, S_AXI_HP0_WRISSUECAP1_EN => '0', S_AXI_HP0_WSTRB(3) => '0', S_AXI_HP0_WSTRB(2) => '0', S_AXI_HP0_WSTRB(1) => '0', S_AXI_HP0_WSTRB(0) => '0', S_AXI_HP0_WVALID => '0', S_AXI_HP1_ACLK => S_AXI_HP1_ACLK, S_AXI_HP1_ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0), S_AXI_HP1_ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0), S_AXI_HP1_ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0), S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED, S_AXI_HP1_ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0), S_AXI_HP1_ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0), S_AXI_HP1_ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0), S_AXI_HP1_ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0), S_AXI_HP1_ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0), S_AXI_HP1_ARREADY => S_AXI_HP1_ARREADY, S_AXI_HP1_ARSIZE(2 downto 0) => S_AXI_HP1_ARSIZE(2 downto 0), S_AXI_HP1_ARVALID => S_AXI_HP1_ARVALID, S_AXI_HP1_AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0), S_AXI_HP1_AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0), S_AXI_HP1_AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0), S_AXI_HP1_AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0), S_AXI_HP1_AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0), S_AXI_HP1_AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0), S_AXI_HP1_AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0), S_AXI_HP1_AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0), S_AXI_HP1_AWREADY => S_AXI_HP1_AWREADY, S_AXI_HP1_AWSIZE(2 downto 0) => S_AXI_HP1_AWSIZE(2 downto 0), S_AXI_HP1_AWVALID => S_AXI_HP1_AWVALID, S_AXI_HP1_BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0), S_AXI_HP1_BREADY => S_AXI_HP1_BREADY, S_AXI_HP1_BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0), S_AXI_HP1_BVALID => S_AXI_HP1_BVALID, S_AXI_HP1_RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0), S_AXI_HP1_RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0), S_AXI_HP1_RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0), S_AXI_HP1_RDISSUECAP1_EN => S_AXI_HP1_RDISSUECAP1_EN, S_AXI_HP1_RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0), S_AXI_HP1_RLAST => S_AXI_HP1_RLAST, S_AXI_HP1_RREADY => S_AXI_HP1_RREADY, S_AXI_HP1_RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0), S_AXI_HP1_RVALID => S_AXI_HP1_RVALID, S_AXI_HP1_WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0), S_AXI_HP1_WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0), S_AXI_HP1_WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0), S_AXI_HP1_WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0), S_AXI_HP1_WLAST => S_AXI_HP1_WLAST, S_AXI_HP1_WREADY => S_AXI_HP1_WREADY, S_AXI_HP1_WRISSUECAP1_EN => S_AXI_HP1_WRISSUECAP1_EN, S_AXI_HP1_WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0), S_AXI_HP1_WVALID => S_AXI_HP1_WVALID, S_AXI_HP2_ACLK => '0', S_AXI_HP2_ARADDR(31) => '0', S_AXI_HP2_ARADDR(30) => '0', S_AXI_HP2_ARADDR(29) => '0', S_AXI_HP2_ARADDR(28) => '0', S_AXI_HP2_ARADDR(27) => '0', S_AXI_HP2_ARADDR(26) => '0', S_AXI_HP2_ARADDR(25) => '0', S_AXI_HP2_ARADDR(24) => '0', S_AXI_HP2_ARADDR(23) => '0', S_AXI_HP2_ARADDR(22) => '0', S_AXI_HP2_ARADDR(21) => '0', S_AXI_HP2_ARADDR(20) => '0', S_AXI_HP2_ARADDR(19) => '0', S_AXI_HP2_ARADDR(18) => '0', S_AXI_HP2_ARADDR(17) => '0', S_AXI_HP2_ARADDR(16) => '0', S_AXI_HP2_ARADDR(15) => '0', S_AXI_HP2_ARADDR(14) => '0', S_AXI_HP2_ARADDR(13) => '0', S_AXI_HP2_ARADDR(12) => '0', S_AXI_HP2_ARADDR(11) => '0', S_AXI_HP2_ARADDR(10) => '0', S_AXI_HP2_ARADDR(9) => '0', S_AXI_HP2_ARADDR(8) => '0', S_AXI_HP2_ARADDR(7) => '0', S_AXI_HP2_ARADDR(6) => '0', S_AXI_HP2_ARADDR(5) => '0', S_AXI_HP2_ARADDR(4) => '0', S_AXI_HP2_ARADDR(3) => '0', S_AXI_HP2_ARADDR(2) => '0', S_AXI_HP2_ARADDR(1) => '0', S_AXI_HP2_ARADDR(0) => '0', S_AXI_HP2_ARBURST(1) => '0', S_AXI_HP2_ARBURST(0) => '0', S_AXI_HP2_ARCACHE(3) => '0', S_AXI_HP2_ARCACHE(2) => '0', S_AXI_HP2_ARCACHE(1) => '0', S_AXI_HP2_ARCACHE(0) => '0', S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED, S_AXI_HP2_ARID(5) => '0', S_AXI_HP2_ARID(4) => '0', S_AXI_HP2_ARID(3) => '0', S_AXI_HP2_ARID(2) => '0', S_AXI_HP2_ARID(1) => '0', S_AXI_HP2_ARID(0) => '0', S_AXI_HP2_ARLEN(3) => '0', S_AXI_HP2_ARLEN(2) => '0', S_AXI_HP2_ARLEN(1) => '0', S_AXI_HP2_ARLEN(0) => '0', S_AXI_HP2_ARLOCK(1) => '0', S_AXI_HP2_ARLOCK(0) => '0', S_AXI_HP2_ARPROT(2) => '0', S_AXI_HP2_ARPROT(1) => '0', S_AXI_HP2_ARPROT(0) => '0', S_AXI_HP2_ARQOS(3) => '0', S_AXI_HP2_ARQOS(2) => '0', S_AXI_HP2_ARQOS(1) => '0', S_AXI_HP2_ARQOS(0) => '0', S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED, S_AXI_HP2_ARSIZE(2) => '0', S_AXI_HP2_ARSIZE(1) => '0', S_AXI_HP2_ARSIZE(0) => '0', S_AXI_HP2_ARVALID => '0', S_AXI_HP2_AWADDR(31) => '0', S_AXI_HP2_AWADDR(30) => '0', S_AXI_HP2_AWADDR(29) => '0', S_AXI_HP2_AWADDR(28) => '0', S_AXI_HP2_AWADDR(27) => '0', S_AXI_HP2_AWADDR(26) => '0', S_AXI_HP2_AWADDR(25) => '0', S_AXI_HP2_AWADDR(24) => '0', S_AXI_HP2_AWADDR(23) => '0', S_AXI_HP2_AWADDR(22) => '0', S_AXI_HP2_AWADDR(21) => '0', S_AXI_HP2_AWADDR(20) => '0', S_AXI_HP2_AWADDR(19) => '0', S_AXI_HP2_AWADDR(18) => '0', S_AXI_HP2_AWADDR(17) => '0', S_AXI_HP2_AWADDR(16) => '0', S_AXI_HP2_AWADDR(15) => '0', S_AXI_HP2_AWADDR(14) => '0', S_AXI_HP2_AWADDR(13) => '0', S_AXI_HP2_AWADDR(12) => '0', S_AXI_HP2_AWADDR(11) => '0', S_AXI_HP2_AWADDR(10) => '0', S_AXI_HP2_AWADDR(9) => '0', S_AXI_HP2_AWADDR(8) => '0', S_AXI_HP2_AWADDR(7) => '0', S_AXI_HP2_AWADDR(6) => '0', S_AXI_HP2_AWADDR(5) => '0', S_AXI_HP2_AWADDR(4) => '0', S_AXI_HP2_AWADDR(3) => '0', S_AXI_HP2_AWADDR(2) => '0', S_AXI_HP2_AWADDR(1) => '0', S_AXI_HP2_AWADDR(0) => '0', S_AXI_HP2_AWBURST(1) => '0', S_AXI_HP2_AWBURST(0) => '0', S_AXI_HP2_AWCACHE(3) => '0', S_AXI_HP2_AWCACHE(2) => '0', S_AXI_HP2_AWCACHE(1) => '0', S_AXI_HP2_AWCACHE(0) => '0', S_AXI_HP2_AWID(5) => '0', S_AXI_HP2_AWID(4) => '0', S_AXI_HP2_AWID(3) => '0', S_AXI_HP2_AWID(2) => '0', S_AXI_HP2_AWID(1) => '0', S_AXI_HP2_AWID(0) => '0', S_AXI_HP2_AWLEN(3) => '0', S_AXI_HP2_AWLEN(2) => '0', S_AXI_HP2_AWLEN(1) => '0', S_AXI_HP2_AWLEN(0) => '0', S_AXI_HP2_AWLOCK(1) => '0', S_AXI_HP2_AWLOCK(0) => '0', S_AXI_HP2_AWPROT(2) => '0', S_AXI_HP2_AWPROT(1) => '0', S_AXI_HP2_AWPROT(0) => '0', S_AXI_HP2_AWQOS(3) => '0', S_AXI_HP2_AWQOS(2) => '0', S_AXI_HP2_AWQOS(1) => '0', S_AXI_HP2_AWQOS(0) => '0', S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED, S_AXI_HP2_AWSIZE(2) => '0', S_AXI_HP2_AWSIZE(1) => '0', S_AXI_HP2_AWSIZE(0) => '0', S_AXI_HP2_AWVALID => '0', S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0), S_AXI_HP2_BREADY => '0', S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED, S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP2_RDISSUECAP1_EN => '0', S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0), S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED, S_AXI_HP2_RREADY => '0', S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED, S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_WDATA(63) => '0', S_AXI_HP2_WDATA(62) => '0', S_AXI_HP2_WDATA(61) => '0', S_AXI_HP2_WDATA(60) => '0', S_AXI_HP2_WDATA(59) => '0', S_AXI_HP2_WDATA(58) => '0', S_AXI_HP2_WDATA(57) => '0', S_AXI_HP2_WDATA(56) => '0', S_AXI_HP2_WDATA(55) => '0', S_AXI_HP2_WDATA(54) => '0', S_AXI_HP2_WDATA(53) => '0', S_AXI_HP2_WDATA(52) => '0', S_AXI_HP2_WDATA(51) => '0', S_AXI_HP2_WDATA(50) => '0', S_AXI_HP2_WDATA(49) => '0', S_AXI_HP2_WDATA(48) => '0', S_AXI_HP2_WDATA(47) => '0', S_AXI_HP2_WDATA(46) => '0', S_AXI_HP2_WDATA(45) => '0', S_AXI_HP2_WDATA(44) => '0', S_AXI_HP2_WDATA(43) => '0', S_AXI_HP2_WDATA(42) => '0', S_AXI_HP2_WDATA(41) => '0', S_AXI_HP2_WDATA(40) => '0', S_AXI_HP2_WDATA(39) => '0', S_AXI_HP2_WDATA(38) => '0', S_AXI_HP2_WDATA(37) => '0', S_AXI_HP2_WDATA(36) => '0', S_AXI_HP2_WDATA(35) => '0', S_AXI_HP2_WDATA(34) => '0', S_AXI_HP2_WDATA(33) => '0', S_AXI_HP2_WDATA(32) => '0', S_AXI_HP2_WDATA(31) => '0', S_AXI_HP2_WDATA(30) => '0', S_AXI_HP2_WDATA(29) => '0', S_AXI_HP2_WDATA(28) => '0', S_AXI_HP2_WDATA(27) => '0', S_AXI_HP2_WDATA(26) => '0', S_AXI_HP2_WDATA(25) => '0', S_AXI_HP2_WDATA(24) => '0', S_AXI_HP2_WDATA(23) => '0', S_AXI_HP2_WDATA(22) => '0', S_AXI_HP2_WDATA(21) => '0', S_AXI_HP2_WDATA(20) => '0', S_AXI_HP2_WDATA(19) => '0', S_AXI_HP2_WDATA(18) => '0', S_AXI_HP2_WDATA(17) => '0', S_AXI_HP2_WDATA(16) => '0', S_AXI_HP2_WDATA(15) => '0', S_AXI_HP2_WDATA(14) => '0', S_AXI_HP2_WDATA(13) => '0', S_AXI_HP2_WDATA(12) => '0', S_AXI_HP2_WDATA(11) => '0', S_AXI_HP2_WDATA(10) => '0', S_AXI_HP2_WDATA(9) => '0', S_AXI_HP2_WDATA(8) => '0', S_AXI_HP2_WDATA(7) => '0', S_AXI_HP2_WDATA(6) => '0', S_AXI_HP2_WDATA(5) => '0', S_AXI_HP2_WDATA(4) => '0', S_AXI_HP2_WDATA(3) => '0', S_AXI_HP2_WDATA(2) => '0', S_AXI_HP2_WDATA(1) => '0', S_AXI_HP2_WDATA(0) => '0', S_AXI_HP2_WID(5) => '0', S_AXI_HP2_WID(4) => '0', S_AXI_HP2_WID(3) => '0', S_AXI_HP2_WID(2) => '0', S_AXI_HP2_WID(1) => '0', S_AXI_HP2_WID(0) => '0', S_AXI_HP2_WLAST => '0', S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED, S_AXI_HP2_WRISSUECAP1_EN => '0', S_AXI_HP2_WSTRB(7) => '0', S_AXI_HP2_WSTRB(6) => '0', S_AXI_HP2_WSTRB(5) => '0', S_AXI_HP2_WSTRB(4) => '0', S_AXI_HP2_WSTRB(3) => '0', S_AXI_HP2_WSTRB(2) => '0', S_AXI_HP2_WSTRB(1) => '0', S_AXI_HP2_WSTRB(0) => '0', S_AXI_HP2_WVALID => '0', S_AXI_HP3_ACLK => '0', S_AXI_HP3_ARADDR(31) => '0', S_AXI_HP3_ARADDR(30) => '0', S_AXI_HP3_ARADDR(29) => '0', S_AXI_HP3_ARADDR(28) => '0', S_AXI_HP3_ARADDR(27) => '0', S_AXI_HP3_ARADDR(26) => '0', S_AXI_HP3_ARADDR(25) => '0', S_AXI_HP3_ARADDR(24) => '0', S_AXI_HP3_ARADDR(23) => '0', S_AXI_HP3_ARADDR(22) => '0', S_AXI_HP3_ARADDR(21) => '0', S_AXI_HP3_ARADDR(20) => '0', S_AXI_HP3_ARADDR(19) => '0', S_AXI_HP3_ARADDR(18) => '0', S_AXI_HP3_ARADDR(17) => '0', S_AXI_HP3_ARADDR(16) => '0', S_AXI_HP3_ARADDR(15) => '0', S_AXI_HP3_ARADDR(14) => '0', S_AXI_HP3_ARADDR(13) => '0', S_AXI_HP3_ARADDR(12) => '0', S_AXI_HP3_ARADDR(11) => '0', S_AXI_HP3_ARADDR(10) => '0', S_AXI_HP3_ARADDR(9) => '0', S_AXI_HP3_ARADDR(8) => '0', S_AXI_HP3_ARADDR(7) => '0', S_AXI_HP3_ARADDR(6) => '0', S_AXI_HP3_ARADDR(5) => '0', S_AXI_HP3_ARADDR(4) => '0', S_AXI_HP3_ARADDR(3) => '0', S_AXI_HP3_ARADDR(2) => '0', S_AXI_HP3_ARADDR(1) => '0', S_AXI_HP3_ARADDR(0) => '0', S_AXI_HP3_ARBURST(1) => '0', S_AXI_HP3_ARBURST(0) => '0', S_AXI_HP3_ARCACHE(3) => '0', S_AXI_HP3_ARCACHE(2) => '0', S_AXI_HP3_ARCACHE(1) => '0', S_AXI_HP3_ARCACHE(0) => '0', S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED, S_AXI_HP3_ARID(5) => '0', S_AXI_HP3_ARID(4) => '0', S_AXI_HP3_ARID(3) => '0', S_AXI_HP3_ARID(2) => '0', S_AXI_HP3_ARID(1) => '0', S_AXI_HP3_ARID(0) => '0', S_AXI_HP3_ARLEN(3) => '0', S_AXI_HP3_ARLEN(2) => '0', S_AXI_HP3_ARLEN(1) => '0', S_AXI_HP3_ARLEN(0) => '0', S_AXI_HP3_ARLOCK(1) => '0', S_AXI_HP3_ARLOCK(0) => '0', S_AXI_HP3_ARPROT(2) => '0', S_AXI_HP3_ARPROT(1) => '0', S_AXI_HP3_ARPROT(0) => '0', S_AXI_HP3_ARQOS(3) => '0', S_AXI_HP3_ARQOS(2) => '0', S_AXI_HP3_ARQOS(1) => '0', S_AXI_HP3_ARQOS(0) => '0', S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED, S_AXI_HP3_ARSIZE(2) => '0', S_AXI_HP3_ARSIZE(1) => '0', S_AXI_HP3_ARSIZE(0) => '0', S_AXI_HP3_ARVALID => '0', S_AXI_HP3_AWADDR(31) => '0', S_AXI_HP3_AWADDR(30) => '0', S_AXI_HP3_AWADDR(29) => '0', S_AXI_HP3_AWADDR(28) => '0', S_AXI_HP3_AWADDR(27) => '0', S_AXI_HP3_AWADDR(26) => '0', S_AXI_HP3_AWADDR(25) => '0', S_AXI_HP3_AWADDR(24) => '0', S_AXI_HP3_AWADDR(23) => '0', S_AXI_HP3_AWADDR(22) => '0', S_AXI_HP3_AWADDR(21) => '0', S_AXI_HP3_AWADDR(20) => '0', S_AXI_HP3_AWADDR(19) => '0', S_AXI_HP3_AWADDR(18) => '0', S_AXI_HP3_AWADDR(17) => '0', S_AXI_HP3_AWADDR(16) => '0', S_AXI_HP3_AWADDR(15) => '0', S_AXI_HP3_AWADDR(14) => '0', S_AXI_HP3_AWADDR(13) => '0', S_AXI_HP3_AWADDR(12) => '0', S_AXI_HP3_AWADDR(11) => '0', S_AXI_HP3_AWADDR(10) => '0', S_AXI_HP3_AWADDR(9) => '0', S_AXI_HP3_AWADDR(8) => '0', S_AXI_HP3_AWADDR(7) => '0', S_AXI_HP3_AWADDR(6) => '0', S_AXI_HP3_AWADDR(5) => '0', S_AXI_HP3_AWADDR(4) => '0', S_AXI_HP3_AWADDR(3) => '0', S_AXI_HP3_AWADDR(2) => '0', S_AXI_HP3_AWADDR(1) => '0', S_AXI_HP3_AWADDR(0) => '0', S_AXI_HP3_AWBURST(1) => '0', S_AXI_HP3_AWBURST(0) => '0', S_AXI_HP3_AWCACHE(3) => '0', S_AXI_HP3_AWCACHE(2) => '0', S_AXI_HP3_AWCACHE(1) => '0', S_AXI_HP3_AWCACHE(0) => '0', S_AXI_HP3_AWID(5) => '0', S_AXI_HP3_AWID(4) => '0', S_AXI_HP3_AWID(3) => '0', S_AXI_HP3_AWID(2) => '0', S_AXI_HP3_AWID(1) => '0', S_AXI_HP3_AWID(0) => '0', S_AXI_HP3_AWLEN(3) => '0', S_AXI_HP3_AWLEN(2) => '0', S_AXI_HP3_AWLEN(1) => '0', S_AXI_HP3_AWLEN(0) => '0', S_AXI_HP3_AWLOCK(1) => '0', S_AXI_HP3_AWLOCK(0) => '0', S_AXI_HP3_AWPROT(2) => '0', S_AXI_HP3_AWPROT(1) => '0', S_AXI_HP3_AWPROT(0) => '0', S_AXI_HP3_AWQOS(3) => '0', S_AXI_HP3_AWQOS(2) => '0', S_AXI_HP3_AWQOS(1) => '0', S_AXI_HP3_AWQOS(0) => '0', S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED, S_AXI_HP3_AWSIZE(2) => '0', S_AXI_HP3_AWSIZE(1) => '0', S_AXI_HP3_AWSIZE(0) => '0', S_AXI_HP3_AWVALID => '0', S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0), S_AXI_HP3_BREADY => '0', S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED, S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP3_RDISSUECAP1_EN => '0', S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0), S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED, S_AXI_HP3_RREADY => '0', S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED, S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_WDATA(63) => '0', S_AXI_HP3_WDATA(62) => '0', S_AXI_HP3_WDATA(61) => '0', S_AXI_HP3_WDATA(60) => '0', S_AXI_HP3_WDATA(59) => '0', S_AXI_HP3_WDATA(58) => '0', S_AXI_HP3_WDATA(57) => '0', S_AXI_HP3_WDATA(56) => '0', S_AXI_HP3_WDATA(55) => '0', S_AXI_HP3_WDATA(54) => '0', S_AXI_HP3_WDATA(53) => '0', S_AXI_HP3_WDATA(52) => '0', S_AXI_HP3_WDATA(51) => '0', S_AXI_HP3_WDATA(50) => '0', S_AXI_HP3_WDATA(49) => '0', S_AXI_HP3_WDATA(48) => '0', S_AXI_HP3_WDATA(47) => '0', S_AXI_HP3_WDATA(46) => '0', S_AXI_HP3_WDATA(45) => '0', S_AXI_HP3_WDATA(44) => '0', S_AXI_HP3_WDATA(43) => '0', S_AXI_HP3_WDATA(42) => '0', S_AXI_HP3_WDATA(41) => '0', S_AXI_HP3_WDATA(40) => '0', S_AXI_HP3_WDATA(39) => '0', S_AXI_HP3_WDATA(38) => '0', S_AXI_HP3_WDATA(37) => '0', S_AXI_HP3_WDATA(36) => '0', S_AXI_HP3_WDATA(35) => '0', S_AXI_HP3_WDATA(34) => '0', S_AXI_HP3_WDATA(33) => '0', S_AXI_HP3_WDATA(32) => '0', S_AXI_HP3_WDATA(31) => '0', S_AXI_HP3_WDATA(30) => '0', S_AXI_HP3_WDATA(29) => '0', S_AXI_HP3_WDATA(28) => '0', S_AXI_HP3_WDATA(27) => '0', S_AXI_HP3_WDATA(26) => '0', S_AXI_HP3_WDATA(25) => '0', S_AXI_HP3_WDATA(24) => '0', S_AXI_HP3_WDATA(23) => '0', S_AXI_HP3_WDATA(22) => '0', S_AXI_HP3_WDATA(21) => '0', S_AXI_HP3_WDATA(20) => '0', S_AXI_HP3_WDATA(19) => '0', S_AXI_HP3_WDATA(18) => '0', S_AXI_HP3_WDATA(17) => '0', S_AXI_HP3_WDATA(16) => '0', S_AXI_HP3_WDATA(15) => '0', S_AXI_HP3_WDATA(14) => '0', S_AXI_HP3_WDATA(13) => '0', S_AXI_HP3_WDATA(12) => '0', S_AXI_HP3_WDATA(11) => '0', S_AXI_HP3_WDATA(10) => '0', S_AXI_HP3_WDATA(9) => '0', S_AXI_HP3_WDATA(8) => '0', S_AXI_HP3_WDATA(7) => '0', S_AXI_HP3_WDATA(6) => '0', S_AXI_HP3_WDATA(5) => '0', S_AXI_HP3_WDATA(4) => '0', S_AXI_HP3_WDATA(3) => '0', S_AXI_HP3_WDATA(2) => '0', S_AXI_HP3_WDATA(1) => '0', S_AXI_HP3_WDATA(0) => '0', S_AXI_HP3_WID(5) => '0', S_AXI_HP3_WID(4) => '0', S_AXI_HP3_WID(3) => '0', S_AXI_HP3_WID(2) => '0', S_AXI_HP3_WID(1) => '0', S_AXI_HP3_WID(0) => '0', S_AXI_HP3_WLAST => '0', S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED, S_AXI_HP3_WRISSUECAP1_EN => '0', S_AXI_HP3_WSTRB(7) => '0', S_AXI_HP3_WSTRB(6) => '0', S_AXI_HP3_WSTRB(5) => '0', S_AXI_HP3_WSTRB(4) => '0', S_AXI_HP3_WSTRB(3) => '0', S_AXI_HP3_WSTRB(2) => '0', S_AXI_HP3_WSTRB(1) => '0', S_AXI_HP3_WSTRB(0) => '0', S_AXI_HP3_WVALID => '0', TRACE_CLK => '0', TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED, TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED, TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0), TTC0_CLK0_IN => '0', TTC0_CLK1_IN => '0', TTC0_CLK2_IN => '0', TTC0_WAVE0_OUT => NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED, TTC0_WAVE1_OUT => NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED, TTC0_WAVE2_OUT => NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED, TTC1_CLK0_IN => '0', TTC1_CLK1_IN => '0', TTC1_CLK2_IN => '0', TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED, TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED, TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED, UART0_CTSN => '0', UART0_DCDN => '0', UART0_DSRN => '0', UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED, UART0_RIN => '0', UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED, UART0_RX => '1', UART0_TX => NLW_inst_UART0_TX_UNCONNECTED, UART1_CTSN => '0', UART1_DCDN => '0', UART1_DSRN => '0', UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED, UART1_RIN => '0', UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED, UART1_RX => '1', UART1_TX => NLW_inst_UART1_TX_UNCONNECTED, USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT, USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT, USB1_PORT_INDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0), USB1_VBUS_PWRFAULT => USB1_VBUS_PWRFAULT, USB1_VBUS_PWRSELECT => USB1_VBUS_PWRSELECT, WDT_CLK_IN => '0', WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED ); end STRUCTURE;
-- megafunction wizard: %RAM: 2-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: RAM_5.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 14.0.0 Build 200 06/17/2014 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2014 Altera Corporation. All rights reserved. --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, the Altera Quartus II License Agreement, --the Altera MegaCore Function License Agreement, or other --applicable license agreement, including, without limitation, --that your use is for the sole purpose of programming logic --devices manufactured by Altera and sold by Altera or its --authorized distributors. Please refer to the applicable --agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; ENTITY RAM_5 IS PORT ( aclr : IN STD_LOGIC := '0'; address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0); clock : IN STD_LOGIC := '1'; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC := '0'; wren_b : IN STD_LOGIC := '0'; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); END RAM_5; ARCHITECTURE SYN OF ram_5 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); BEGIN q_a <= sub_wire0(31 DOWNTO 0); q_b <= sub_wire1(31 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_reg_b => "CLOCK0", clock_enable_input_a => "BYPASS", clock_enable_input_b => "BYPASS", clock_enable_output_a => "BYPASS", clock_enable_output_b => "BYPASS", indata_reg_b => "CLOCK0", init_file => "RAM_5.mif", intended_device_family => "Cyclone IV E", lpm_type => "altsyncram", numwords_a => 1024, numwords_b => 1024, operation_mode => "BIDIR_DUAL_PORT", outdata_aclr_a => "CLEAR0", outdata_aclr_b => "CLEAR0", outdata_reg_a => "UNREGISTERED", outdata_reg_b => "UNREGISTERED", power_up_uninitialized => "FALSE", read_during_write_mode_mixed_ports => "OLD_DATA", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", widthad_a => 10, widthad_b => 10, width_a => 32, width_b => 32, width_byteena_a => 1, width_byteena_b => 1, wrcontrol_wraddress_reg_b => "CLOCK0" ) PORT MAP ( aclr0 => aclr, address_a => address_a, address_b => address_b, clock0 => clock, data_a => data_a, data_b => data_b, wren_a => wren_a, wren_b => wren_b, q_a => sub_wire0, q_b => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" -- Retrieval info: PRIVATE: CLRdata NUMERIC "0" -- Retrieval info: PRIVATE: CLRq NUMERIC "1" -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRrren NUMERIC "0" -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRwren NUMERIC "0" -- Retrieval info: PRIVATE: Clock NUMERIC "0" -- Retrieval info: PRIVATE: Clock_A NUMERIC "0" -- Retrieval info: PRIVATE: Clock_B NUMERIC "0" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768" -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "RAM_5.mif" -- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1" -- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" -- Retrieval info: PRIVATE: REGdata NUMERIC "1" -- Retrieval info: PRIVATE: REGq NUMERIC "0" -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" -- Retrieval info: PRIVATE: REGrren NUMERIC "0" -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" -- Retrieval info: PRIVATE: REGwren NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" -- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" -- Retrieval info: PRIVATE: VarWidth NUMERIC "0" -- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" -- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: enable NUMERIC "0" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" -- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" -- Retrieval info: CONSTANT: INIT_FILE STRING "RAM_5.mif" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" -- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0" -- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" -- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" -- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" -- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" -- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]" -- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]" -- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]" -- Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]" -- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]" -- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" -- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" -- Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0 -- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0 -- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0 -- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 -- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 -- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0 -- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_5.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_5.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_5.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_5.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_5_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
library ieee; use ieee.std_logic_1164.all; entity sr_latch_testbench is end sr_latch_testbench; architecture behavioral of sr_latch_testbench IS component sr_latch port ( s : in std_logic; r : in std_logic; q_n : inout std_logic; q : inout std_logic); end component; signal q, q_n : std_logic := '0'; signal input : std_logic_vector(1 downto 0); begin input <= -- a,b "10", "11" AFTER 5 ns, "01" AFTER 10 ns, "11" AFTER 15 ns, "10" AFTER 20 ns, "11" AFTER 25 ns, "00" AFTER 30 ns; uut: sr_latch port map (input(1), input(0), q_n, q); end behavioral;
-- Copyright (C) 1991-2011 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. -- Quartus II 11.0 Build 157 04/27/2011 library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; package hardcopyiii_atom_pack is function str_to_bin (lut_mask : string ) return std_logic_vector; function product(list : std_logic_vector) return std_logic ; function alt_conv_integer(arg : in std_logic_vector) return integer; -- default generic values CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns); CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns); CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns); CONSTANT DefSetupHoldCnst : TIME := 0 ns; CONSTANT DefPulseWdthCnst : TIME := 0 ns; -- default control options -- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent; -- change default delay type to Transport : for spr 68748 CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport; CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE; CONSTANT DefGlitchXOn : BOOLEAN := FALSE; CONSTANT DefMsgOnChecks : BOOLEAN := TRUE; CONSTANT DefXOnChecks : BOOLEAN := TRUE; -- output strength mapping -- UX01ZWHL- CONSTANT PullUp : VitalOutputMapType := "UX01HX01X"; CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X"; CONSTANT PullDown : VitalOutputMapType := "UX01LX01X"; -- primitive result strength mapping CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' ); CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' ); CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) -- Declare array types for CAM_SLICE TYPE hardcopyiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0); function int2str( value : integer ) return string; function map_x_to_0 (value : std_logic) return std_logic; function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME; function int2bit (arg : boolean) return std_logic; function int2bit (arg : integer) return std_logic; function bin2int (s : std_logic_vector) return integer; function bin2int (s : std_logic) return integer; function int2bin (arg : integer; size : integer) return std_logic_vector; function int2bin (arg : boolean; size : integer) return std_logic_vector; function calc_sum_len( widtha : integer; widthb : integer) return integer; end hardcopyiii_atom_pack; library IEEE; use IEEE.std_logic_1164.all; package body hardcopyiii_atom_pack is type masklength is array (4 downto 1) of std_logic_vector(3 downto 0); function str_to_bin (lut_mask : string) return std_logic_vector is variable slice : masklength := (OTHERS => "0000"); variable mask : std_logic_vector(15 downto 0); begin for i in 1 to lut_mask'length loop case lut_mask(i) is when '0' => slice(i) := "0000"; when '1' => slice(i) := "0001"; when '2' => slice(i) := "0010"; when '3' => slice(i) := "0011"; when '4' => slice(i) := "0100"; when '5' => slice(i) := "0101"; when '6' => slice(i) := "0110"; when '7' => slice(i) := "0111"; when '8' => slice(i) := "1000"; when '9' => slice(i) := "1001"; when 'a' => slice(i) := "1010"; when 'A' => slice(i) := "1010"; when 'b' => slice(i) := "1011"; when 'B' => slice(i) := "1011"; when 'c' => slice(i) := "1100"; when 'C' => slice(i) := "1100"; when 'd' => slice(i) := "1101"; when 'D' => slice(i) := "1101"; when 'e' => slice(i) := "1110"; when 'E' => slice(i) := "1110"; when others => slice(i) := "1111"; end case; end loop; mask := (slice(1) & slice(2) & slice(3) & slice(4)); return (mask); end str_to_bin; function product (list: std_logic_vector) return std_logic is begin for i in 0 to 31 loop if list(i) = '0' then return ('0'); end if; end loop; return ('1'); end product; function alt_conv_integer(arg : in std_logic_vector) return integer is variable result : integer; begin result := 0; for i in arg'range loop if arg(i) = '1' then result := result + 2**i; end if; end loop; return result; end alt_conv_integer; function int2str( value : integer ) return string is variable ivalue,index : integer; variable digit : integer; variable line_no: string(8 downto 1) := " "; begin ivalue := value; index := 1; if (ivalue = 0) then line_no := " 0"; end if; while (ivalue > 0) loop digit := ivalue MOD 10; ivalue := ivalue/10; case digit is when 0 => line_no(index) := '0'; when 1 => line_no(index) := '1'; when 2 => line_no(index) := '2'; when 3 => line_no(index) := '3'; when 4 => line_no(index) := '4'; when 5 => line_no(index) := '5'; when 6 => line_no(index) := '6'; when 7 => line_no(index) := '7'; when 8 => line_no(index) := '8'; when 9 => line_no(index) := '9'; when others => ASSERT FALSE REPORT "Illegal number!" SEVERITY ERROR; end case; index := index + 1; end loop; return line_no; end; function map_x_to_0 (value : std_logic) return std_logic is begin if (Is_X (value) = TRUE) then return '0'; else return value; end if; end; function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS variable Temp : TIME; variable TransitionTime : TIME := TIME'HIGH; variable PathDelay : TIME := TIME'HIGH; begin for i IN Paths'RANGE loop next when not Paths(i).PathCondition; next when Paths(i).InputChangeTime > TransitionTime; Temp := Paths(i).PathDelay(tr01); if Paths(i).InputChangeTime < TransitionTime then PathDelay := Temp; else if Temp < PathDelay then PathDelay := Temp; end if; end if; TransitionTime := Paths(i).InputChangeTime; end loop; return PathDelay; end; function int2bit (arg : integer) return std_logic is variable int_val : integer := arg; variable result : std_logic; begin if (int_val = 0) then result := '0'; else result := '1'; end if; return result; end int2bit; function int2bit (arg : boolean) return std_logic is variable int_val : boolean := arg; variable result : std_logic; begin if (int_val ) then result := '1'; else result := '0'; end if; return result; end int2bit; function bin2int (s : std_logic_vector) return integer is constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s; variable result : integer := 0; begin for i in temp'range loop if (temp(i) = '1') then result := result + (2**i); end if; end loop; return(result); end bin2int; function bin2int (s : std_logic) return integer is constant temp : std_logic := s; variable result : integer := 0; begin if (temp = '1') then result := 1; else result := 0; end if; return(result); end bin2int; function int2bin (arg : integer; size : integer) return std_logic_vector is variable int_val : integer := arg; variable result : std_logic_vector(size-1 downto 0); begin for i in 0 to result'left loop if ((int_val mod 2) = 0) then result(i) := '0'; else result(i) := '1'; end if; int_val := int_val/2; end loop; return result; end int2bin; function int2bin (arg : boolean; size : integer) return std_logic_vector is variable result : std_logic_vector(size-1 downto 0); begin if(arg)then result := (OTHERS => '1'); else result := (OTHERS => '0'); end if; return result; end int2bin; function calc_sum_len( widtha : integer; widthb : integer) return integer is variable result: integer; begin if(widtha >= widthb) then result := widtha + 1; else result := widthb + 1; end if; return result; end calc_sum_len; end hardcopyiii_atom_pack; Library ieee; use ieee.std_logic_1164.all; Package hardcopyiii_pllpack is procedure find_simple_integer_fraction( numerator : in integer; denominator : in integer; max_denom : in integer; fraction_num : out integer; fraction_div : out integer); procedure find_m_and_n_4_manual_phase ( inclock_period : in integer; vco_phase_shift_step : in integer; clk0_mult: in integer; clk1_mult: in integer; clk2_mult: in integer; clk3_mult: in integer; clk4_mult: in integer; clk5_mult: in integer; clk6_mult: in integer; clk7_mult: in integer; clk8_mult: in integer; clk9_mult: in integer; clk0_div : in integer; clk1_div : in integer; clk2_div : in integer; clk3_div : in integer; clk4_div : in integer; clk5_div : in integer; clk6_div : in integer; clk7_div : in integer; clk8_div : in integer; clk9_div : in integer; clk0_used : in string; clk1_used : in string; clk2_used : in string; clk3_used : in string; clk4_used : in string; clk5_used : in string; clk6_used : in string; clk7_used : in string; clk8_used : in string; clk9_used : in string; m : out integer; n : out integer ); function gcd (X: integer; Y: integer) return integer; function count_digit (X: integer) return integer; function scale_num (X: integer; Y: integer) return integer; function lcm (A1: integer; A2: integer; A3: integer; A4: integer; A5: integer; A6: integer; A7: integer; A8: integer; A9: integer; A10: integer; P: integer) return integer; function output_counter_value (clk_divide: integer; clk_mult : integer ; M: integer; N: integer ) return integer; function counter_mode (duty_cycle: integer; output_counter_value: integer) return string; function counter_high (output_counter_value: integer := 1; duty_cycle: integer) return integer; function counter_low (output_counter_value: integer; duty_cycle: integer) return integer; function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer; t5: integer; t6: integer; t7: integer; t8: integer; t9: integer; t10: integer) return integer; function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer; t5: integer; t6: integer; t7: integer; t8: integer; t9: integer; t10: integer) return integer; function counter_time_delay ( clk_time_delay: integer; m_time_delay: integer; n_time_delay: integer) return integer; function get_phase_degree (phase_shift: integer; clk_period: integer) return integer; function counter_initial (tap_phase: integer; m: integer; n: integer) return integer; function counter_ph (tap_phase: integer; m : integer; n: integer) return integer; function ph_adjust (tap_phase: integer; ph_base : integer) return integer; function translate_string (mode : string) return string; function str2int (s : string) return integer; function dqs_str2int (s : string) return integer; end hardcopyiii_pllpack; package body hardcopyiii_pllpack is -- finds the closest integer fraction of a given pair of numerator and denominator. procedure find_simple_integer_fraction( numerator : in integer; denominator : in integer; max_denom : in integer; fraction_num : out integer; fraction_div : out integer) is constant MAX_ITER : integer := 20; type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer; variable quotient_array : INT_ARRAY; variable int_loop_iter : integer; variable int_quot : integer; variable m_value : integer; variable d_value : integer; variable old_m_value : integer; variable swap : integer; variable loop_iter : integer; variable num : integer; variable den : integer; variable i_max_iter : integer; begin loop_iter := 0; if (numerator = 0) then num := 1; else num := numerator; end if; if (denominator = 0) then den := 1; else den := denominator; end if; i_max_iter := max_iter; while (loop_iter < i_max_iter) loop int_quot := num / den; quotient_array(loop_iter) := int_quot; num := num - (den*int_quot); loop_iter := loop_iter+1; if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then -- calculate the numerator and denominator if there is a restriction on the -- max denom value or if the loop is ending m_value := 0; d_value := 1; -- get the rounded value at this stage for the remaining fraction if (den /= 0) then m_value := (2*num/den); end if; -- calculate the fraction numerator and denominator at this stage for int_loop_iter in (loop_iter-1) downto 0 loop if (m_value = 0) then m_value := quotient_array(int_loop_iter); d_value := 1; else old_m_value := m_value; m_value := (quotient_array(int_loop_iter)*m_value) + d_value; d_value := old_m_value; end if; end loop; -- if the denominator is less than the maximum denom_value or if there is no restriction save it if ((d_value <= max_denom) or (max_denom = -1)) then if ((m_value = 0) or (d_value = 0)) then fraction_num := numerator; fraction_div := denominator; else fraction_num := m_value; fraction_div := d_value; end if; end if; -- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round) if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then i_max_iter := loop_iter; end if; end if; -- swap the numerator and denominator for the next round swap := den; den := num; num := swap; end loop; end find_simple_integer_fraction; -- find the M and N values for Manual phase based on the following 5 criterias: -- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz -- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz -- 3. M is less than 512 -- 4. N is less than 512 -- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps -- of the desired vco-phase-shift-step procedure find_m_and_n_4_manual_phase ( inclock_period : in integer; vco_phase_shift_step : in integer; clk0_mult: in integer; clk1_mult: in integer; clk2_mult: in integer; clk3_mult: in integer; clk4_mult: in integer; clk5_mult: in integer; clk6_mult: in integer; clk7_mult: in integer; clk8_mult: in integer; clk9_mult: in integer; clk0_div : in integer; clk1_div : in integer; clk2_div : in integer; clk3_div : in integer; clk4_div : in integer; clk5_div : in integer; clk6_div : in integer; clk7_div : in integer; clk8_div : in integer; clk9_div : in integer; clk0_used : in string; clk1_used : in string; clk2_used : in string; clk3_used : in string; clk4_used : in string; clk5_used : in string; clk6_used : in string; clk7_used : in string; clk8_used : in string; clk9_used : in string; m : out integer; n : out integer ) is constant MAX_M : integer := 511; constant MAX_N : integer := 511; constant MAX_PFD : integer := 720; constant MIN_PFD : integer := 5; constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz) constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz) constant MAX_OFFSET : real := 0.004; variable vco_period : integer; variable pfd_freq : integer; variable vco_freq : integer; variable vco_ps_step_value : integer; variable i_m : integer; variable i_n : integer; variable i_pre_m : integer; variable i_pre_n : integer; variable closest_vco_step_value : integer; variable i_max_iter : integer; variable loop_iter : integer; variable clk0_div_factor_real : real; variable clk1_div_factor_real : real; variable clk2_div_factor_real : real; variable clk3_div_factor_real : real; variable clk4_div_factor_real : real; variable clk5_div_factor_real : real; variable clk6_div_factor_real : real; variable clk7_div_factor_real : real; variable clk8_div_factor_real : real; variable clk9_div_factor_real : real; variable clk0_div_factor_int : integer; variable clk1_div_factor_int : integer; variable clk2_div_factor_int : integer; variable clk3_div_factor_int : integer; variable clk4_div_factor_int : integer; variable clk5_div_factor_int : integer; variable clk6_div_factor_int : integer; variable clk7_div_factor_int : integer; variable clk8_div_factor_int : integer; variable clk9_div_factor_int : integer; begin vco_period := vco_phase_shift_step * 8; i_pre_m := 0; i_pre_n := 0; closest_vco_step_value := 0; LOOP_1 : for i_n_out in 1 to MAX_N loop for i_m_out in 1 to MAX_M loop clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out); clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out); clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out); clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out); clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out); clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out); clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out); clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out); clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out); clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out); clk0_div_factor_int := integer(clk0_div_factor_real); clk1_div_factor_int := integer(clk1_div_factor_real); clk2_div_factor_int := integer(clk2_div_factor_real); clk3_div_factor_int := integer(clk3_div_factor_real); clk4_div_factor_int := integer(clk4_div_factor_real); clk5_div_factor_int := integer(clk5_div_factor_real); clk6_div_factor_int := integer(clk6_div_factor_real); clk7_div_factor_int := integer(clk7_div_factor_real); clk8_div_factor_int := integer(clk8_div_factor_real); clk9_div_factor_int := integer(clk9_div_factor_real); if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and ((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and ((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and ((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and ((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and ((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and ((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and ((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and ((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and ((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) ) then if ((i_m_out /= 0) and (i_n_out /= 0)) then pfd_freq := 1000000 / (inclock_period * i_n_out); vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out); vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out); if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and (vco_freq >= min_vco) and (vco_freq <= max_vco) ) then if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2) then i_pre_m := i_m_out; i_pre_n := i_n_out; exit LOOP_1; else if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step))) then i_pre_m := i_m_out; i_pre_n := i_n_out; closest_vco_step_value := vco_ps_step_value; end if; end if; end if; end if; end if; end loop; end loop; if ((i_pre_m /= 0) and (i_pre_n /= 0)) then find_simple_integer_fraction(i_pre_m, i_pre_n, MAX_N, m, n); else n := 1; m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult, clk4_mult, clk5_mult, clk6_mult, clk7_mult, clk8_mult, clk9_mult, inclock_period); end if; end find_m_and_n_4_manual_phase; -- find the greatest common denominator of X and Y function gcd (X: integer; Y: integer) return integer is variable L, S, R, G : integer := 1; begin if (X < Y) then -- find which is smaller. S := X; L := Y; else S := Y; L := X; end if; R := S; while ( R > 1) loop S := L; L := R; R := S rem L; -- divide bigger number by smaller. -- remainder becomes smaller number. end loop; if (R = 0) then -- if evenly divisible then L is gcd else it is 1. G := L; else G := R; end if; return G; end gcd; -- count the number of digits in the given integer function count_digit (X: integer) return integer is variable count, result: integer := 0; begin result := X; while (result /= 0) loop result := (result / 10); count := count + 1; end loop; return count; end count_digit; -- reduce the given huge number to Y significant digits function scale_num (X: integer; Y: integer) return integer is variable count : integer := 0; variable lc, fac_ten, result: integer := 1; begin count := count_digit(X); for lc in 1 to (count-Y) loop fac_ten := fac_ten * 10; end loop; result := (X / fac_ten); return result; end scale_num; -- find the least common multiple of A1 to A10 function lcm (A1: integer; A2: integer; A3: integer; A4: integer; A5: integer; A6: integer; A7: integer; A8: integer; A9: integer; A10: integer; P: integer) return integer is variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1; begin M1 := (A1 * A2)/gcd(A1, A2); M2 := (M1 * A3)/gcd(M1, A3); M3 := (M2 * A4)/gcd(M2, A4); M4 := (M3 * A5)/gcd(M3, A5); M5 := (M4 * A6)/gcd(M4, A6); M6 := (M5 * A7)/gcd(M5, A7); M7 := (M6 * A8)/gcd(M6, A8); M8 := (M7 * A9)/gcd(M7, A9); M9 := (M8 * A10)/gcd(M8, A10); if (M9 < 3) then R := 10; elsif (M9 = 3) then R := 9; elsif ((M9 <= 10) and (M9 > 3)) then R := 4 * M9; elsif (M9 > 1000) then R := scale_num(M9,3); else R := M9 ; end if; return R; end lcm; -- find the factor of division of the output clock frequency compared to the VCO function output_counter_value (clk_divide: integer; clk_mult: integer ; M: integer; N: integer ) return integer is variable r_real : real := 1.0; variable r: integer := 1; begin r_real := real(clk_divide * M)/ real(clk_mult * N); r := integer(r_real); return R; end output_counter_value; -- find the mode of each PLL counter - bypass, even or odd function counter_mode (duty_cycle: integer; output_counter_value: integer) return string is variable R: string (1 to 6) := " "; variable counter_value: integer := 1; begin counter_value := (2*duty_cycle*output_counter_value)/100; if output_counter_value = 1 then R := "bypass"; elsif (counter_value REM 2) = 0 then R := " even"; else R := " odd"; end if; return R; end counter_mode; -- find the number of VCO clock cycles to hold the output clock high function counter_high (output_counter_value: integer := 1; duty_cycle: integer) return integer is variable R: integer := 1; variable half_cycle_high : integer := 1; begin half_cycle_high := (duty_cycle * output_counter_value *2)/100 ; if (half_cycle_high REM 2 = 0) then R := half_cycle_high/2 ; else R := (half_cycle_high/2) + 1; end if; return R; end; -- find the number of VCO clock cycles to hold the output clock low function counter_low (output_counter_value: integer; duty_cycle: integer) return integer is variable R, R1: integer := 1; variable half_cycle_high : integer := 1; begin half_cycle_high := (duty_cycle * output_counter_value*2)/100 ; if (half_cycle_high REM 2 = 0) then R1 := half_cycle_high/2 ; else R1 := (half_cycle_high/2) + 1; end if; R := output_counter_value - R1; if (R = 0) then R := 1; end if; return R; end; -- find the smallest time delay amongst t1 to t10 function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer; t5: integer; t6: integer; t7: integer; t8: integer; t9: integer; t10: integer) return integer is variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0; begin if (t1 < t2) then m1 := t1; else m1 := t2; end if; if (m1 < t3) then m2 := m1; else m2 := t3; end if; if (m2 < t4) then m3 := m2; else m3 := t4; end if; if (m3 < t5) then m4 := m3; else m4 := t5; end if; if (m4 < t6) then m5 := m4; else m5 := t6; end if; if (m5 < t7) then m6 := m5; else m6 := t7; end if; if (m6 < t8) then m7 := m6; else m7 := t8; end if; if (m7 < t9) then m8 := m7; else m8 := t9; end if; if (m8 < t10) then m9 := m8; else m9 := t10; end if; if (m9 > 0) then return m9; else return 0; end if; end; -- find the numerically largest negative number, and return its absolute value function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer; t5: integer; t6: integer; t7: integer; t8: integer; t9: integer; t10: integer) return integer is variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0; begin if (t1 < t2) then m1 := t1; else m1 := t2; end if; if (m1 < t3) then m2 := m1; else m2 := t3; end if; if (m2 < t4) then m3 := m2; else m3 := t4; end if; if (m3 < t5) then m4 := m3; else m4 := t5; end if; if (m4 < t6) then m5 := m4; else m5 := t6; end if; if (m5 < t7) then m6 := m5; else m6 := t7; end if; if (m6 < t8) then m7 := m6; else m7 := t8; end if; if (m7 < t9) then m8 := m7; else m8 := t9; end if; if (m8 < t10) then m9 := m8; else m9 := t10; end if; if (m9 < 0) then return (0 - m9); else return 0; end if; end; -- adjust the phase (tap_phase) with the largest negative number (ph_base) function ph_adjust (tap_phase: integer; ph_base : integer) return integer is begin return (tap_phase + ph_base); end; -- find the time delay for each PLL counter function counter_time_delay (clk_time_delay: integer; m_time_delay: integer; n_time_delay: integer) return integer is variable R: integer := 0; begin R := clk_time_delay + m_time_delay - n_time_delay; return R; end; -- calculate the given phase shift (in ps) in terms of degrees function get_phase_degree (phase_shift: integer; clk_period: integer) return integer is variable result: integer := 0; begin result := ( phase_shift * 360 ) / clk_period; -- to round up the calculation result if (result > 0) then result := result + 1; elsif (result < 0) then result := result - 1; else result := 0; end if; return result; end; -- find the number of VCO clock cycles to wait initially before the first rising -- edge of the output clock function counter_initial (tap_phase: integer; m: integer; n: integer) return integer is variable R: integer; variable R1: real; begin R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6; -- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99. -- This checking will ensure that the rounding up is done. if (R1 >= 0.5) and (R1 <= 1.0) then R1 := 1.0; end if; R := integer(R1); return R; end; -- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is variable R: integer := 0; begin -- 0.5 is added for proper rounding of the tap_phase. R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8; return R; end; -- convert given string to length 6 by padding with spaces function translate_string (mode : string) return string is variable new_mode : string (1 to 6) := " "; begin if (mode = "bypass") then new_mode := "bypass"; elsif (mode = "even") then new_mode := " even"; elsif (mode = "odd") then new_mode := " odd"; end if; return new_mode; end; function str2int (s : string) return integer is variable len : integer := s'length; variable newdigit : integer := 0; variable sign : integer := 1; variable digit : integer := 0; begin for i in 1 to len loop case s(i) is when '-' => if i = 1 then sign := -1; else ASSERT FALSE REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR; end if; when '0' => digit := 0; when '1' => digit := 1; when '2' => digit := 2; when '3' => digit := 3; when '4' => digit := 4; when '5' => digit := 5; when '6' => digit := 6; when '7' => digit := 7; when '8' => digit := 8; when '9' => digit := 9; when others => ASSERT FALSE REPORT "Illegal Character "& s(i) & "in string parameter! " SEVERITY ERROR; end case; newdigit := newdigit * 10 + digit; end loop; return (sign*newdigit); end; function dqs_str2int (s : string) return integer is variable len : integer := s'length; variable newdigit : integer := 0; variable sign : integer := 1; variable digit : integer := 0; variable err : boolean := false; begin for i in 1 to len loop case s(i) is when '-' => if i = 1 then sign := -1; else ASSERT FALSE REPORT "Illegal Character "& s(i) & " in string parameter! " SEVERITY ERROR; err := true; end if; when '0' => digit := 0; when '1' => digit := 1; when '2' => digit := 2; when '3' => digit := 3; when '4' => digit := 4; when '5' => digit := 5; when '6' => digit := 6; when '7' => digit := 7; when '8' => digit := 8; when '9' => digit := 9; when others => -- set error flag err := true; end case; if (err) then err := false; else newdigit := newdigit * 10 + digit; end if; end loop; return (sign*newdigit); end; end hardcopyiii_pllpack; -- -- -- DFFE Model -- -- LIBRARY IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; entity hardcopyiii_dffe is generic( TimingChecksOn: Boolean := True; XOn: Boolean := DefGlitchXOn; MsgOn: Boolean := DefGlitchMsgOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; InstancePath: STRING := "*"; tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01; tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01; tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01; tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01; tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst; tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst; thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tipd_D : VitalDelayType01 := DefPropDelay01; tipd_CLRN : VitalDelayType01 := DefPropDelay01; tipd_PRN : VitalDelayType01 := DefPropDelay01; tipd_CLK : VitalDelayType01 := DefPropDelay01; tipd_ENA : VitalDelayType01 := DefPropDelay01); port( Q : out STD_LOGIC := '0'; D : in STD_LOGIC; CLRN : in STD_LOGIC; PRN : in STD_LOGIC; CLK : in STD_LOGIC; ENA : in STD_LOGIC); attribute VITAL_LEVEL0 of hardcopyiii_dffe : entity is TRUE; end hardcopyiii_dffe; -- architecture body -- architecture behave of hardcopyiii_dffe is attribute VITAL_LEVEL0 of behave : architecture is TRUE; signal D_ipd : STD_ULOGIC := 'U'; signal CLRN_ipd : STD_ULOGIC := 'U'; signal PRN_ipd : STD_ULOGIC := 'U'; signal CLK_ipd : STD_ULOGIC := 'U'; signal ENA_ipd : STD_ULOGIC := 'U'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN); VitalWireDelay (PRN_ipd, PRN, tipd_PRN); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (ENA_ipd, ENA, tipd_ENA); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd) -- timing check results VARIABLE Tviol_D_CLK : STD_ULOGIC := '0'; VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0'; VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit; VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7); VARIABLE D_delayed : STD_ULOGIC := 'U'; VARIABLE CLK_delayed : STD_ULOGIC := 'U'; VARIABLE ENA_delayed : STD_ULOGIC := 'U'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0'); -- output glitch detection variables VARIABLE Q_VitalGlitchData : VitalGlitchDataType; CONSTANT dffe_Q_tab : VitalStateTableType := ( ( L, L, x, x, x, x, x, x, x, L ), ( L, H, L, H, H, x, x, H, x, H ), ( L, H, L, H, x, L, x, H, x, H ), ( L, H, L, x, H, H, x, H, x, H ), ( L, H, H, x, x, x, H, x, x, S ), ( L, H, x, x, x, x, L, x, x, H ), ( L, H, x, x, x, x, H, L, x, S ), ( L, x, L, L, L, x, H, H, x, L ), ( L, x, L, L, x, L, H, H, x, L ), ( L, x, L, x, L, H, H, H, x, L ), ( L, x, x, x, x, x, x, x, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK, TimingData => TimingData_D_CLK, TestSignal => D_ipd, TestSignalName => "D", RefSignal => CLK_ipd, RefSignalName => "CLK", SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1', RefTransition => '/', HeaderMsg => InstancePath & "/DFFE", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_ENA_CLK, TimingData => TimingData_ENA_CLK, TestSignal => ENA_ipd, TestSignalName => "ENA", RefSignal => CLK_ipd, RefSignalName => "CLK", SetupHigh => tsetup_ENA_CLK_noedge_posedge, SetupLow => tsetup_ENA_CLK_noedge_posedge, HoldHigh => thold_ENA_CLK_noedge_posedge, HoldLow => thold_ENA_CLK_noedge_posedge, CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1', RefTransition => '/', HeaderMsg => InstancePath & "/DFFE", XOn => XOnChecks, MsgOn => MsgOnChecks ); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK or Tviol_ENA_CLK; VitalStateTable( StateTable => dffe_Q_tab, DataIn => ( Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd), Result => Results, NumStates => 1, PreviousDataIn => PrevData_Q); D_delayed := D_ipd; CLK_delayed := CLK_ipd; ENA_delayed := ENA_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, OutSignalName => "Q", OutTemp => Results(1), Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE), 1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)), GlitchData => Q_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; end behave; -- -- -- hardcopyiii_mux21 Model -- -- LIBRARY IEEE; use ieee.std_logic_1164.all; use IEEE.VITAL_Timing.all; use work.hardcopyiii_atom_pack.all; entity hardcopyiii_mux21 is generic( TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; InstancePath: STRING := "*"; tpd_A_MO : VitalDelayType01 := DefPropDelay01; tpd_B_MO : VitalDelayType01 := DefPropDelay01; tpd_S_MO : VitalDelayType01 := DefPropDelay01; tipd_A : VitalDelayType01 := DefPropDelay01; tipd_B : VitalDelayType01 := DefPropDelay01; tipd_S : VitalDelayType01 := DefPropDelay01); port ( A : in std_logic := '0'; B : in std_logic := '0'; S : in std_logic := '0'; MO : out std_logic); attribute VITAL_LEVEL0 of hardcopyiii_mux21 : entity is TRUE; end hardcopyiii_mux21; architecture AltVITAL of hardcopyiii_mux21 is attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE; signal A_ipd, B_ipd, S_ipd : std_logic; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd) -- output glitch detection variables VARIABLE MO_GlitchData : VitalGlitchDataType; variable tmp_MO : std_logic; begin ------------------------- -- Functionality Section ------------------------- if (S_ipd = '1') then tmp_MO := B_ipd; else tmp_MO := A_ipd; end if; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => MO, OutSignalName => "MO", OutTemp => tmp_MO, Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE), 1 => (B_ipd'last_event, tpd_B_MO, TRUE), 2 => (S_ipd'last_event, tpd_S_MO, TRUE)), GlitchData => MO_GlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; end AltVITAL; -- -- -- hardcopyiii_mux41 Model -- -- LIBRARY IEEE; use ieee.std_logic_1164.all; use IEEE.VITAL_Timing.all; use work.hardcopyiii_atom_pack.all; entity hardcopyiii_mux41 is generic( TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; InstancePath: STRING := "*"; tpd_IN0_MO : VitalDelayType01 := DefPropDelay01; tpd_IN1_MO : VitalDelayType01 := DefPropDelay01; tpd_IN2_MO : VitalDelayType01 := DefPropDelay01; tpd_IN3_MO : VitalDelayType01 := DefPropDelay01; tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); tipd_IN0 : VitalDelayType01 := DefPropDelay01; tipd_IN1 : VitalDelayType01 := DefPropDelay01; tipd_IN2 : VitalDelayType01 := DefPropDelay01; tipd_IN3 : VitalDelayType01 := DefPropDelay01; tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01) ); port ( IN0 : in std_logic := '0'; IN1 : in std_logic := '0'; IN2 : in std_logic := '0'; IN3 : in std_logic := '0'; S : in std_logic_vector(1 downto 0) := (OTHERS => '0'); MO : out std_logic ); attribute VITAL_LEVEL0 of hardcopyiii_mux41 : entity is TRUE; end hardcopyiii_mux41; architecture AltVITAL of hardcopyiii_mux41 is attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE; signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic; signal S_ipd : std_logic_vector(1 downto 0); begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (IN0_ipd, IN0, tipd_IN0); VitalWireDelay (IN1_ipd, IN1, tipd_IN1); VitalWireDelay (IN2_ipd, IN2, tipd_IN2); VitalWireDelay (IN3_ipd, IN3, tipd_IN3); VitalWireDelay (S_ipd(0), S(0), tipd_S(0)); VitalWireDelay (S_ipd(1), S(1), tipd_S(1)); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1)) -- output glitch detection variables VARIABLE MO_GlitchData : VitalGlitchDataType; variable tmp_MO : std_logic; begin ------------------------- -- Functionality Section ------------------------- if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then tmp_MO := IN3_ipd; elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then tmp_MO := IN2_ipd; elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then tmp_MO := IN1_ipd; else tmp_MO := IN0_ipd; end if; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => MO, OutSignalName => "MO", OutTemp => tmp_MO, Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE), 1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE), 2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE), 3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE), 4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE), 5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)), GlitchData => MO_GlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; end AltVITAL; -- -- -- hardcopyiii_and1 Model -- -- LIBRARY IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; use work.hardcopyiii_atom_pack.all; -- entity declaration -- entity hardcopyiii_and1 is generic( TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; InstancePath: STRING := "*"; tpd_IN1_Y : VitalDelayType01 := DefPropDelay01; tipd_IN1 : VitalDelayType01 := DefPropDelay01); port( Y : out STD_LOGIC; IN1 : in STD_LOGIC); attribute VITAL_LEVEL0 of hardcopyiii_and1 : entity is TRUE; end hardcopyiii_and1; -- architecture body -- architecture AltVITAL of hardcopyiii_and1 is attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE; SIGNAL IN1_ipd : STD_ULOGIC := 'U'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (IN1_ipd, IN1, tipd_IN1); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (IN1_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_ULOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := TO_X01(IN1_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)), GlitchData => Y_GlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; end AltVITAL; --------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_lcell_comb -- -- Description : HARDCOPYIII LCELL_COMB VHDL simulation model -- -- --------------------------------------------------------------------- LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; entity hardcopyiii_lcell_comb is generic ( lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1'); shared_arith : string := "off"; extended_lut : string := "off"; dont_touch : string := "off"; lpm_type : string := "hardcopyiii_lcell_comb"; TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; InstancePath: STRING := "*"; tpd_dataa_combout : VitalDelayType01 := DefPropDelay01; tpd_datab_combout : VitalDelayType01 := DefPropDelay01; tpd_datac_combout : VitalDelayType01 := DefPropDelay01; tpd_datad_combout : VitalDelayType01 := DefPropDelay01; tpd_datae_combout : VitalDelayType01 := DefPropDelay01; tpd_dataf_combout : VitalDelayType01 := DefPropDelay01; tpd_datag_combout : VitalDelayType01 := DefPropDelay01; tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01; tpd_datab_sumout : VitalDelayType01 := DefPropDelay01; tpd_datac_sumout : VitalDelayType01 := DefPropDelay01; tpd_datad_sumout : VitalDelayType01 := DefPropDelay01; tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01; tpd_cin_sumout : VitalDelayType01 := DefPropDelay01; tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01; tpd_dataa_cout : VitalDelayType01 := DefPropDelay01; tpd_datab_cout : VitalDelayType01 := DefPropDelay01; tpd_datac_cout : VitalDelayType01 := DefPropDelay01; tpd_datad_cout : VitalDelayType01 := DefPropDelay01; tpd_dataf_cout : VitalDelayType01 := DefPropDelay01; tpd_cin_cout : VitalDelayType01 := DefPropDelay01; tpd_sharein_cout : VitalDelayType01 := DefPropDelay01; tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01; tpd_datab_shareout : VitalDelayType01 := DefPropDelay01; tpd_datac_shareout : VitalDelayType01 := DefPropDelay01; tpd_datad_shareout : VitalDelayType01 := DefPropDelay01; tipd_dataa : VitalDelayType01 := DefPropDelay01; tipd_datab : VitalDelayType01 := DefPropDelay01; tipd_datac : VitalDelayType01 := DefPropDelay01; tipd_datad : VitalDelayType01 := DefPropDelay01; tipd_datae : VitalDelayType01 := DefPropDelay01; tipd_dataf : VitalDelayType01 := DefPropDelay01; tipd_datag : VitalDelayType01 := DefPropDelay01; tipd_cin : VitalDelayType01 := DefPropDelay01; tipd_sharein : VitalDelayType01 := DefPropDelay01 ); port ( dataa : in std_logic := '0'; datab : in std_logic := '0'; datac : in std_logic := '0'; datad : in std_logic := '0'; datae : in std_logic := '0'; dataf : in std_logic := '0'; datag : in std_logic := '0'; cin : in std_logic := '0'; sharein : in std_logic := '0'; combout : out std_logic; sumout : out std_logic; cout : out std_logic; shareout : out std_logic ); attribute VITAL_LEVEL0 of hardcopyiii_lcell_comb : entity is TRUE; end hardcopyiii_lcell_comb; architecture vital_lcell_comb of hardcopyiii_lcell_comb is attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE; signal dataa_ipd : std_logic; signal datab_ipd : std_logic; signal datac_ipd : std_logic; signal datad_ipd : std_logic; signal datae_ipd : std_logic; signal dataf_ipd : std_logic; signal datag_ipd : std_logic; signal cin_ipd : std_logic; signal sharein_ipd : std_logic; signal f2_input3 : std_logic; -- sub masks signal f0_mask : std_logic_vector(15 downto 0); signal f1_mask : std_logic_vector(15 downto 0); signal f2_mask : std_logic_vector(15 downto 0); signal f3_mask : std_logic_vector(15 downto 0); begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (dataa_ipd, dataa, tipd_dataa); VitalWireDelay (datab_ipd, datab, tipd_datab); VitalWireDelay (datac_ipd, datac, tipd_datac); VitalWireDelay (datad_ipd, datad, tipd_datad); VitalWireDelay (datae_ipd, datae, tipd_datae); VitalWireDelay (dataf_ipd, dataf, tipd_dataf); VitalWireDelay (datag_ipd, datag, tipd_datag); VitalWireDelay (cin_ipd, cin, tipd_cin); VitalWireDelay (sharein_ipd, sharein, tipd_sharein); end block; f0_mask <= lut_mask(15 downto 0); f1_mask <= lut_mask(31 downto 16); f2_mask <= lut_mask(47 downto 32); f3_mask <= lut_mask(63 downto 48); f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd; VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd, datae_ipd, dataf_ipd, f2_input3, cin_ipd, sharein_ipd) variable combout_VitalGlitchData : VitalGlitchDataType; variable sumout_VitalGlitchData : VitalGlitchDataType; variable cout_VitalGlitchData : VitalGlitchDataType; variable shareout_VitalGlitchData : VitalGlitchDataType; -- sub lut outputs variable f0_out : std_logic; variable f1_out : std_logic; variable f2_out : std_logic; variable f3_out : std_logic; -- muxed output variable g0_out : std_logic; variable g1_out : std_logic; -- internal variables variable f2_f : std_logic; variable adder_input2 : std_logic; -- output variables variable combout_tmp : std_logic; variable sumout_tmp : std_logic; variable cout_tmp : std_logic; -- temp variable for NCVHDL variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1'); begin lut_mask_var := lut_mask; ------------------------ -- Timing Check Section ------------------------ f0_out := VitalMUX(data => f0_mask, dselect => (datad_ipd, datac_ipd, datab_ipd, dataa_ipd)); f1_out := VitalMUX(data => f1_mask, dselect => (datad_ipd, f2_input3, datab_ipd, dataa_ipd)); f2_out := VitalMUX(data => f2_mask, dselect => (datad_ipd, datac_ipd, datab_ipd, dataa_ipd)); f3_out := VitalMUX(data => f3_mask, dselect => (datad_ipd, f2_input3, datab_ipd, dataa_ipd)); -- combout if (extended_lut = "on") then if (datae_ipd = '0') then g0_out := f0_out; g1_out := f2_out; elsif (datae_ipd = '1') then g0_out := f1_out; g1_out := f3_out; else g0_out := 'X'; g1_out := 'X'; end if; if (dataf_ipd = '0') then combout_tmp := g0_out; elsif ((dataf_ipd = '1') or (g0_out = g1_out))then combout_tmp := g1_out; else combout_tmp := 'X'; end if; else combout_tmp := VitalMUX(data => lut_mask_var, dselect => (dataf_ipd, datae_ipd, datad_ipd, datac_ipd, datab_ipd, dataa_ipd)); end if; -- sumout and cout f2_f := VitalMUX(data => f2_mask, dselect => (dataf_ipd, datac_ipd, datab_ipd, dataa_ipd)); if (shared_arith = "on") then adder_input2 := sharein_ipd; else adder_input2 := NOT f2_f; end if; sumout_tmp := cin_ipd XOR f0_out XOR adder_input2; cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR (f0_out AND adder_input2); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => combout, OutSignalName => "COMBOUT", OutTemp => combout_tmp, Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE), 1 => (datab_ipd'last_event, tpd_datab_combout, TRUE), 2 => (datac_ipd'last_event, tpd_datac_combout, TRUE), 3 => (datad_ipd'last_event, tpd_datad_combout, TRUE), 4 => (datae_ipd'last_event, tpd_datae_combout, TRUE), 5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE), 6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)), GlitchData => combout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => sumout, OutSignalName => "SUMOUT", OutTemp => sumout_tmp, Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE), 1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE), 2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE), 3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE), 4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE), 5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE), 6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)), GlitchData => sumout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => cout, OutSignalName => "COUT", OutTemp => cout_tmp, Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE), 1 => (datab_ipd'last_event, tpd_datab_cout, TRUE), 2 => (datac_ipd'last_event, tpd_datac_cout, TRUE), 3 => (datad_ipd'last_event, tpd_datad_cout, TRUE), 4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE), 5 => (cin_ipd'last_event, tpd_cin_cout, TRUE), 6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)), GlitchData => cout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => shareout, OutSignalName => "SHAREOUT", OutTemp => f2_out, Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE), 1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE), 2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE), 3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)), GlitchData => shareout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; end vital_lcell_comb; --------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_routing_wire -- -- Description : HARDCOPYIII Routing Wire VHDL simulation model -- -- --------------------------------------------------------------------- LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_routing_wire is generic ( MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; tpd_datain_dataout : VitalDelayType01 := DefPropDelay01; tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01; tipd_datain : VitalDelayType01 := DefPropDelay01 ); PORT ( datain : in std_logic; dataout : out std_logic ); attribute VITAL_LEVEL0 of hardcopyiii_routing_wire : entity is TRUE; end hardcopyiii_routing_wire; ARCHITECTURE behave of hardcopyiii_routing_wire is attribute VITAL_LEVEL0 of behave : architecture is TRUE; signal datain_ipd : std_logic; signal datainglitch_inert : std_logic; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (datain_ipd, datain, tipd_datain); end block; VITAL: process(datain_ipd, datainglitch_inert) variable datain_inert_VitalGlitchData : VitalGlitchDataType; variable dataout_VitalGlitchData : VitalGlitchDataType; begin ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => datainglitch_inert, OutSignalName => "datainglitch_inert", OutTemp => datain_ipd, Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)), GlitchData => datain_inert_VitalGlitchData, Mode => VitalInertial, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => dataout, OutSignalName => "dataout", OutTemp => datainglitch_inert, Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; end behave; --///////////////////////////////////////////////////////////////////////////// -- -- Module Name : hardcopyiii_lvds_tx_reg -- -- Description : Simulation model for a simple DFF. -- This is used for registering the enable inputs. -- No timing, powers upto 0. -- --///////////////////////////////////////////////////////////////////////////// LIBRARY IEEE, std; USE ieee.std_logic_1164.all; --USE ieee.std_logic_unsigned.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_lvds_tx_reg is GENERIC ( MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; TimingChecksOn : Boolean := True; InstancePath : String := "*"; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_ena : VitalDelayType01 := DefpropDelay01; tipd_d : VitalDelayType01 := DefpropDelay01; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01 ); PORT ( q : OUT std_logic; clk : IN std_logic; ena : IN std_logic; d : IN std_logic; clrn : IN std_logic; prn : IN std_logic ); attribute VITAL_LEVEL0 of hardcopyiii_lvds_tx_reg : ENTITY is TRUE; END hardcopyiii_lvds_tx_reg; ARCHITECTURE vital_hardcopyiii_lvds_tx_reg of hardcopyiii_lvds_tx_reg is attribute VITAL_LEVEL0 of vital_hardcopyiii_lvds_tx_reg : architecture is TRUE; -- INTERNAL SIGNALS signal clk_ipd : std_logic; signal d_ipd : std_logic; signal ena_ipd : std_logic; begin ---------------------- -- INPUT PATH DELAYs ---------------------- WireDelay : block begin VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (ena_ipd, ena, tipd_ena); VitalWireDelay (d_ipd, d, tipd_d); end block; process (clk_ipd, clrn, prn) variable q_tmp : std_logic := '0'; variable q_VitalGlitchData : VitalGlitchDataType; variable Tviol_d_clk : std_ulogic := '0'; variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_d_clk, TimingData => TimingData_d_clk, TestSignal => d_ipd, TestSignalName => "d", RefSignal => clk_ipd, RefSignalName => "clk", SetupHigh => tsetup_d_clk_noedge_posedge, SetupLow => tsetup_d_clk_noedge_posedge, HoldHigh => thold_d_clk_noedge_posedge, HoldLow => thold_d_clk_noedge_posedge, CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1', RefTransition => '/', HeaderMsg => InstancePath & "/hardcopyiii_lvds_tx_reg", XOn => XOnChecks, MsgOn => MsgOnChecks ); end if; if (prn = '0') then q_tmp := '1'; elsif (clrn = '0') then q_tmp := '0'; elsif (clk_ipd'event and clk_ipd = '1') then if (ena_ipd = '1') then q_tmp := d_ipd; end if; end if; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => q, OutSignalName => "Q", OutTemp => q_tmp, Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)), GlitchData => q_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; end vital_hardcopyiii_lvds_tx_reg; --//////////////////////////////////////////////////////////////////////////// -- -- Entity name : hardcopyiii_lvds_tx_parallel_register -- -- Description : Register for the 10 data input channels of the HARDCOPYIII -- LVDS Tx -- --//////////////////////////////////////////////////////////////////////////// LIBRARY IEEE, std; USE IEEE.std_logic_1164.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE work.hardcopyiii_atom_pack.all; USE std.textio.all; ENTITY hardcopyiii_lvds_tx_parallel_register is GENERIC ( channel_width : integer := 10; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_enable : VitalDelayType01 := DefpropDelay01; tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01) ); PORT ( clk : in std_logic; enable : in std_logic; datain : in std_logic_vector(channel_width - 1 downto 0); devclrn : in std_logic := '1'; devpor : in std_logic := '1'; dataout : out std_logic_vector(channel_width - 1 downto 0) ); END hardcopyiii_lvds_tx_parallel_register; ARCHITECTURE vital_tx_reg of hardcopyiii_lvds_tx_parallel_register is signal clk_ipd : std_logic; signal enable_ipd : std_logic; signal datain_ipd : std_logic_vector(channel_width - 1 downto 0); begin ---------------------- -- INPUT PATH DELAYs ---------------------- WireDelay : block begin VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (enable_ipd, enable, tipd_enable); loopbits : FOR i in datain'RANGE GENERATE VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i)); END GENERATE; end block; VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn) variable Tviol_datain_clk : std_ulogic := '0'; variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit; variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0); variable i : integer := 0; variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0); variable CQDelay : TIME := 0 ns; begin if (now = 0 ns) then dataout_tmp := (OTHERS => '0'); end if; ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_datain_clk, TimingData => TimingData_datain_clk, TestSignal => datain_ipd, TestSignalName => "DATAIN", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_datain_clk_noedge_posedge, SetupLow => tsetup_datain_clk_noedge_posedge, HoldHigh => thold_datain_clk_noedge_posedge, HoldLow => thold_datain_clk_noedge_posedge, RefTransition => '/', HeaderMsg => InstancePath & "/hardcopyiii_lvds_tx_parallel_register", XOn => XOn, MsgOn => MsgOnChecks ); end if; if ((devpor = '0') or (devclrn = '0')) then dataout_tmp := (OTHERS => '0'); else if (clk_ipd'event and clk_ipd = '1') then if (enable_ipd = '1') then dataout_tmp := datain_ipd; end if; end if; end if; ---------------------- -- Path Delay Section ---------------------- CQDelay := SelectDelay( (1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE)) ); dataout <= TRANSPORT dataout_tmp AFTER CQDelay; end process; end vital_tx_reg; --//////////////////////////////////////////////////////////////////////////// -- -- Entity name : hardcopyiii_lvds_tx_out_block -- -- Description : Negative-edge triggered register on the Tx output. -- Also, optionally generates an identical/inverted output clock -- --//////////////////////////////////////////////////////////////////////////// LIBRARY IEEE, std; USE IEEE.std_logic_1164.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE work.hardcopyiii_atom_pack.all; USE std.textio.all; ENTITY hardcopyiii_lvds_tx_out_block is GENERIC ( bypass_serializer : String := "false"; invert_clock : String := "false"; use_falling_clock_edge : String := "false"; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tpd_datain_dataout : VitalDelayType01 := DefPropDelay01; tpd_clk_dataout : VitalDelayType01 := DefPropDelay01; tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_datain : VitalDelayType01 := DefpropDelay01 ); PORT ( clk : in std_logic; datain : in std_logic; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; dataout : out std_logic ); END hardcopyiii_lvds_tx_out_block; ARCHITECTURE vital_tx_out_block of hardcopyiii_lvds_tx_out_block is signal clk_ipd : std_logic; signal datain_ipd : std_logic; signal inv_clk : integer; begin ---------------------- -- INPUT PATH DELAYs ---------------------- WireDelay : block begin VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (datain_ipd, datain, tipd_datain); end block; VITAL: process (clk_ipd, datain_ipd, devpor, devclrn) variable dataout_VitalGlitchData : VitalGlitchDataType; variable dataout_tmp : std_logic; begin if (now = 0 ns) then dataout_tmp := '0'; else if (bypass_serializer = "false") then if (use_falling_clock_edge = "false") then dataout_tmp := datain_ipd; end if; if (clk_ipd'event and clk_ipd = '0') then if (use_falling_clock_edge = "true") then dataout_tmp := datain_ipd; end if; end if; else if (invert_clock = "false") then dataout_tmp := clk_ipd; else dataout_tmp := NOT (clk_ipd); end if; if (invert_clock = "false") then inv_clk <= 0; else inv_clk <= 1; end if; end if; end if; ---------------------- -- Path Delay Section ---------------------- if (bypass_serializer = "false") then VitalPathDelay01 ( OutSignal => dataout, OutSignalName => "DATAOUT", OutTemp => dataout_tmp, Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE), 1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end if; if (bypass_serializer = "true") then VitalPathDelay01 ( OutSignal => dataout, OutSignalName => "DATAOUT", OutTemp => dataout_tmp, Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end if; end process; end vital_tx_out_block; --//////////////////////////////////////////////////////////////////////////// -- -- Entity name : hardcopyiii_lvds_transmitter -- -- Description : Timing simulation model for the HARDCOPYIII LVDS Tx WYSIWYG. -- It instantiates the following sub-modules : -- 1) primitive DFFE -- 2) HARDCOPYIII_lvds_tx_parallel_register and -- 3) HARDCOPYIII_lvds_tx_out_block -- --//////////////////////////////////////////////////////////////////////////// LIBRARY IEEE, std; USE IEEE.std_logic_1164.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE work.hardcopyiii_atom_pack.all; USE std.textio.all; USE work.hardcopyiii_lvds_tx_parallel_register; USE work.hardcopyiii_lvds_tx_out_block; USE work.hardcopyiii_lvds_tx_reg; ENTITY hardcopyiii_lvds_transmitter is GENERIC ( channel_width : integer := 10; bypass_serializer : String := "false"; invert_clock : String := "false"; use_falling_clock_edge : String := "false"; use_serial_data_input : String := "false"; use_post_dpa_serial_data_input : String := "false"; is_used_as_outclk : String := "false"; -- HARDCOPYIII tx_output_path_delay_engineering_bits : Integer := -1; -- HARDCOPYIII enable_dpaclk_to_lvdsout : string := "off"; -- HARDCOPYIII preemphasis_setting : integer := 0; vod_setting : integer := 0; differential_drive : integer := 0; lpm_type : string := "hardcopyiii_lvds_transmitter"; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01; tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01; tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01; tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;-- HARDCOPYIII tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01; tipd_clk0 : VitalDelayType01 := DefpropDelay01; tipd_enable0 : VitalDelayType01 := DefpropDelay01; tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01); tipd_serialdatain : VitalDelayType01 := DefpropDelay01; tipd_dpaclkin : VitalDelayType01 := DefpropDelay01; -- HARDCOPYIII tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01 ); PORT ( clk0 : in std_logic; enable0 : in std_logic := '0'; datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0'); serialdatain : in std_logic := '0'; postdpaserialdatain : in std_logic := '0'; dpaclkin : in std_logic := '0';-- HARDCOPYIII devclrn : in std_logic := '1'; devpor : in std_logic := '1'; dataout : out std_logic; serialfdbkout : out std_logic ); end hardcopyiii_lvds_transmitter; ARCHITECTURE vital_transmitter_atom of hardcopyiii_lvds_transmitter is signal clk0_ipd : std_logic; signal serialdatain_ipd : std_logic; signal postdpaserialdatain_ipd : std_logic; signal dpaclkin_ipd : std_logic;-- HARDCOPYIII signal input_data : std_logic_vector(channel_width - 1 downto 0); signal txload0 : std_logic; signal shift_out : std_logic; signal clk0_dly0 : std_logic; signal clk0_dly1 : std_logic; signal clk0_dly2 : std_logic; signal datain_dly : std_logic_vector(channel_width - 1 downto 0); signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0); signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0); signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0); signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0); signal vcc : std_logic := '1'; signal tmp_dataout : std_logic; COMPONENT hardcopyiii_lvds_tx_parallel_register GENERIC ( channel_width : integer := 10; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_enable : VitalDelayType01 := DefpropDelay01; tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01) ); PORT ( clk : in std_logic; enable : in std_logic; datain : in std_logic_vector(channel_width - 1 downto 0); devclrn : in std_logic := '1'; devpor : in std_logic := '1'; dataout : out std_logic_vector(channel_width - 1 downto 0) ); END COMPONENT; COMPONENT hardcopyiii_lvds_tx_out_block GENERIC ( bypass_serializer : String := "false"; invert_clock : String := "false"; use_falling_clock_edge : String := "false"; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tpd_datain_dataout : VitalDelayType01 := DefPropDelay01; tpd_clk_dataout : VitalDelayType01 := DefPropDelay01; tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_datain : VitalDelayType01 := DefpropDelay01 ); PORT ( clk : in std_logic; datain : in std_logic; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; dataout : out std_logic ); END COMPONENT; COMPONENT hardcopyiii_lvds_tx_reg GENERIC (TimingChecksOn : Boolean := true; InstancePath : STRING := "*"; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tipd_d : VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01 ); PORT ( q : out STD_LOGIC := '0'; d : in STD_LOGIC := '1'; clrn : in STD_LOGIC := '1'; prn : in STD_LOGIC := '1'; clk : in STD_LOGIC := '0'; ena : in STD_LOGIC := '1' ); END COMPONENT; begin ---------------------- -- INPUT PATH DELAYs ---------------------- WireDelay : block begin VitalWireDelay (clk0_ipd, clk0, tipd_clk0); VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain); VitalWireDelay (dpaclkin_ipd, dpaclkin, tipd_dpaclkin);-- HARDCOPYIII VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain); end block; txload0_reg: hardcopyiii_lvds_tx_reg PORT MAP (d => enable0, clrn => vcc, prn => vcc, ena => vcc, clk => clk0_dly2, q => txload0 ); input_reg: hardcopyiii_lvds_tx_parallel_register GENERIC MAP ( channel_width => channel_width) PORT MAP ( clk => txload0, enable => vcc, datain => datain_dly, dataout => input_data, devclrn => devclrn, devpor => devpor ); output_module: hardcopyiii_lvds_tx_out_block GENERIC MAP ( bypass_serializer => bypass_serializer, use_falling_clock_edge => use_falling_clock_edge, invert_clock => invert_clock) PORT MAP ( clk => clk0_dly2, datain => shift_out, dataout => tmp_dataout, devclrn => devclrn, devpor => devpor ); clk_delay: process (clk0_ipd, datain) begin clk0_dly0 <= clk0_ipd; datain_dly1 <= datain; end process; clk_delay1: process (clk0_dly0, datain_dly1) begin clk0_dly1 <= clk0_dly0; datain_dly2 <= datain_dly1; end process; clk_delay2: process (clk0_dly1, datain_dly2) begin clk0_dly2 <= clk0_dly1; datain_dly3 <= datain_dly2; end process; data_delay: process (datain_dly3) begin datain_dly4 <= datain_dly3; end process; data_delay1: process (datain_dly4) begin datain_dly <= datain_dly4; end process; VITAL: process (clk0_ipd, devclrn, devpor) variable dataout_VitalGlitchData : VitalGlitchDataType; variable i : integer := 0; variable shift_data : std_logic_vector(channel_width-1 downto 0); begin if (now = 0 ns) then shift_data := (OTHERS => '0'); end if; if ((devpor = '0') or (devclrn = '0')) then shift_data := (OTHERS => '0'); else if (bypass_serializer = "false") then if (clk0_ipd'event and clk0_ipd = '1') then if (txload0 = '1') then shift_data := input_data; end if; shift_out <= shift_data(channel_width - 1); for i in channel_width-1 downto 1 loop shift_data(i) := shift_data(i - 1); end loop; end if; end if; end if; end process; process (serialdatain_ipd, postdpaserialdatain_ipd, dpaclkin_ipd, -- HARDCOPYIII tmp_dataout ) variable dataout_tmp : std_logic := '0'; variable dataout_VitalGlitchData : VitalGlitchDataType; begin if (serialdatain_ipd'event and use_serial_data_input = "true") then dataout_tmp := serialdatain_ipd; elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then dataout_tmp := postdpaserialdatain_ipd; elsif (dpaclkin_ipd'event and enable_dpaclk_to_lvdsout = "on") then-- HARDCOPYIII dataout_tmp := dpaclkin_ipd;-- HARDCOPYIII else dataout_tmp := tmp_dataout; end if; ---------------------- -- Path Delay Section ---------------------- if (use_serial_data_input = "true") then VitalPathDelay01 ( OutSignal => dataout, OutSignalName => "DATAOUT", OutTemp => dataout_tmp, Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); elsif (use_post_dpa_serial_data_input = "true") then VitalPathDelay01 ( OutSignal => dataout, OutSignalName => "DATAOUT", OutTemp => dataout_tmp, Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); elsif (enable_dpaclk_to_lvdsout = "on") then -- HARDCOPYIII VitalPathDelay01 ( -- HARDCOPYIII OutSignal => dataout, -- HARDCOPYIII OutSignalName => "DATAOUT", -- HARDCOPYIII OutTemp => dataout_tmp, -- HARDCOPYIII Paths => (0 => (dpaclkin_ipd'last_event, tpd_dpaclkin_dataout, TRUE)), -- HARDCOPYIII GlitchData => dataout_VitalGlitchData, -- HARDCOPYIII Mode => DefGlitchMode, -- HARDCOPYIII XOn => XOn, -- HARDCOPYIII MsgOn => MsgOn ); -- HARDCOPYIII else VitalPathDelay01 ( OutSignal => dataout, OutSignalName => "DATAOUT", OutTemp => dataout_tmp, Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end if; end process; end vital_transmitter_atom; ---------------------------------------------------------------------------- -- Module Name : hardcopyiii_ram_register -- Description : Register module for RAM inputs/outputs ---------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_ram_register IS GENERIC ( width : INTEGER := 1; preset : STD_LOGIC := '0'; tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01); tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; tipd_stall : VitalDelayType01 := DefPropDelay01; tipd_aclr : VitalDelayType01 := DefPropDelay01; tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst ); PORT ( d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0); clk : IN STD_LOGIC; ena : IN STD_LOGIC; stall : IN STD_LOGIC; aclr : IN STD_LOGIC; devclrn : IN STD_LOGIC; devpor : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0); aclrout : OUT STD_LOGIC ); END hardcopyiii_ram_register; ARCHITECTURE reg_arch OF hardcopyiii_ram_register IS SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0); SIGNAL clk_ipd : STD_LOGIC; SIGNAL ena_ipd : STD_LOGIC; SIGNAL aclr_ipd : STD_LOGIC; SIGNAL stall_ipd : STD_LOGIC; BEGIN WireDelay : BLOCK BEGIN loopbits : FOR i in d'RANGE GENERATE VitalWireDelay (d_ipd(i), d(i), tipd_d(i)); END GENERATE; VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (aclr_ipd, aclr, tipd_aclr); VitalWireDelay (ena_ipd, ena, tipd_ena); VitalWireDelay (stall_ipd, stall, tipd_stall); END BLOCK; PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor) VARIABLE Tviol_clk_ena : STD_ULOGIC := '0'; VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0'; VARIABLE Tviol_data_clk : STD_ULOGIC := '0'; VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit; VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit; VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit; VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_ena : STD_ULOGIC := '0'; VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0); VARIABLE CQDelay : TIME := 0 ns; VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset); BEGIN IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN q_reg := (OTHERS => preset); ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN q_reg := d_ipd; END IF; -- Timing checks VitalSetupHoldCheck ( Violation => Tviol_clk_ena, TimingData => TimingData_clk_ena, TestSignal => ena_ipd, TestSignalName => "ena", RefSignal => clk_ipd, RefSignalName => "clk", SetupHigh => tsetup_ena_clk_noedge_posedge, SetupLow => tsetup_ena_clk_noedge_posedge, HoldHigh => thold_ena_clk_noedge_posedge, HoldLow => thold_ena_clk_noedge_posedge, CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1', RefTransition => '/', HeaderMsg => "/RAM Register VitalSetupHoldCheck", XOn => DefXOnChecks, MsgOn => DefMsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_clk_ena, TimingData => TimingData_clk_stall, TestSignal => stall_ipd, TestSignalName => "stall", RefSignal => clk_ipd, RefSignalName => "clk", SetupHigh => tsetup_stall_clk_noedge_posedge, SetupLow => tsetup_stall_clk_noedge_posedge, HoldHigh => thold_stall_clk_noedge_posedge, HoldLow => thold_stall_clk_noedge_posedge, CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1', RefTransition => '/', HeaderMsg => "/RAM Register VitalSetupHoldCheck", XOn => DefXOnChecks, MsgOn => DefMsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_clk_aclr, TimingData => TimingData_clk_aclr, TestSignal => aclr_ipd, TestSignalName => "aclr", RefSignal => clk_ipd, RefSignalName => "clk", SetupHigh => tsetup_aclr_clk_noedge_posedge, SetupLow => tsetup_aclr_clk_noedge_posedge, HoldHigh => thold_aclr_clk_noedge_posedge, HoldLow => thold_aclr_clk_noedge_posedge, CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1', RefTransition => '/', HeaderMsg => "/RAM Register VitalSetupHoldCheck", XOn => DefXOnChecks, MsgOn => DefMsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_data_clk, TimingData => TimingData_data_clk, TestSignal => d_ipd, TestSignalName => "data", RefSignal => clk_ipd, RefSignalName => "clk", SetupHigh => tsetup_d_clk_noedge_posedge, SetupLow => tsetup_d_clk_noedge_posedge, HoldHigh => thold_d_clk_noedge_posedge, HoldLow => thold_d_clk_noedge_posedge, CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1', RefTransition => '/', HeaderMsg => "/RAM Register VitalSetupHoldCheck", XOn => DefXOnChecks, MsgOn => DefMsgOnChecks ); VitalPeriodPulseCheck ( Violation => Tviol_ena, PeriodData => PeriodData_ena, TestSignal => ena_ipd, TestSignalName => "ena", PulseWidthHigh => tpw_ena_posedge, HeaderMsg => "/RAM Register VitalPeriodPulseCheck", XOn => DefXOnChecks, MsgOn => DefMsgOnChecks ); -- Path Delay Selection CQDelay := SelectDelay ( Paths => ( (0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE), 1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE)) ) ); q <= TRANSPORT q_reg AFTER CQDelay; END PROCESS; aclrout <= aclr_ipd; END reg_arch; ---------------------------------------------------------------------------- -- Module Name : hardcopyiii_ram_pulse_generator -- Description : Generate pulse to initiate memory read/write operations ---------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_ram_pulse_generator IS GENERIC ( tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns); tipd_ena : VitalDelayType01 := DefPropDelay01; tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01 ); PORT ( clk,ena : IN STD_LOGIC; delaywrite : IN STD_LOGIC := '0'; pulse,cycle : OUT STD_LOGIC ); ATTRIBUTE VITAL_Level0 OF hardcopyiii_ram_pulse_generator:ENTITY IS TRUE; END hardcopyiii_ram_pulse_generator; ARCHITECTURE pgen_arch OF hardcopyiii_ram_pulse_generator IS SIGNAL clk_ipd,ena_ipd : STD_LOGIC; SIGNAL state : STD_LOGIC; ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE; BEGIN WireDelay : BLOCK BEGIN VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (ena_ipd, ena, tipd_ena); END BLOCK; PROCESS (clk_ipd,state) BEGIN IF (state = '1' AND state'EVENT) THEN state <= '0'; ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN IF (delaywrite = '1') THEN state <= '1' AFTER 1 NS; -- delayed write ELSE state <= '1'; END IF; END IF; END PROCESS; PathDelay : PROCESS VARIABLE pulse_VitalGlitchData : VitalGlitchDataType; BEGIN WAIT UNTIL state'EVENT; VitalPathDelay01 ( OutSignal => pulse, OutSignalName => "pulse", OutTemp => state, Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)), GlitchData => pulse_VitalGlitchData, Mode => DefGlitchMode, XOn => DefXOnChecks, MsgOn => DefMsgOnChecks ); END PROCESS; cycle <= clk_ipd; END pgen_arch; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE work.hardcopyiii_atom_pack.all; USE work.hardcopyiii_ram_register; USE work.hardcopyiii_ram_pulse_generator; ENTITY hardcopyiii_ram_block IS GENERIC ( -- -------- GLOBAL PARAMETERS --------- operation_mode : STRING := "single_port"; mixed_port_feed_through_mode : STRING := "dont_care"; ram_block_type : STRING := "auto"; logical_ram_name : STRING := "ram_name"; init_file : STRING := "init_file.hex"; init_file_layout : STRING := "none"; enable_ecc : STRING := "false"; width_eccstatus : INTEGER := 3; data_interleave_width_in_bits : INTEGER := 1; data_interleave_offset_in_bits : INTEGER := 1; port_a_logical_ram_depth : INTEGER := 0; port_a_logical_ram_width : INTEGER := 0; port_a_first_address : INTEGER := 0; port_a_last_address : INTEGER := 0; port_a_first_bit_number : INTEGER := 0; port_a_address_clear : STRING := "none"; port_a_data_out_clear : STRING := "none"; port_a_data_in_clock : STRING := "clock0"; port_a_address_clock : STRING := "clock0"; port_a_write_enable_clock : STRING := "clock0"; port_a_read_enable_clock : STRING := "clock0"; port_a_byte_enable_clock : STRING := "clock0"; port_a_data_out_clock : STRING := "none"; port_a_data_width : INTEGER := 1; port_a_address_width : INTEGER := 1; port_a_byte_enable_mask_width : INTEGER := 1; port_b_logical_ram_depth : INTEGER := 0; port_b_logical_ram_width : INTEGER := 0; port_b_first_address : INTEGER := 0; port_b_last_address : INTEGER := 0; port_b_first_bit_number : INTEGER := 0; port_b_address_clear : STRING := "none"; port_b_data_out_clear : STRING := "none"; port_b_data_in_clock : STRING := "clock1"; port_b_address_clock : STRING := "clock1"; port_b_write_enable_clock: STRING := "clock1"; port_b_read_enable_clock: STRING := "clock1"; port_b_byte_enable_clock : STRING := "clock1"; port_b_data_out_clock : STRING := "none"; port_b_data_width : INTEGER := 1; port_b_address_width : INTEGER := 1; port_b_byte_enable_mask_width : INTEGER := 1; port_a_read_during_write_mode : STRING := "new_data_no_nbe_read"; port_b_read_during_write_mode : STRING := "new_data_no_nbe_read"; power_up_uninitialized : STRING := "false"; port_b_byte_size : INTEGER := 0; port_a_byte_size : INTEGER := 0; lpm_type : string := "hardcopyiii_ram_block"; lpm_hint : string := "true"; clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none clk0_output_clock_enable : STRING := "none"; -- ena0,none clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none clk1_output_clock_enable : STRING := "none"; -- ena1,none clock_duty_cycle_dependence : STRING := "On"; mem_init0 : BIT_VECTOR := X"0"; mem_init1 : BIT_VECTOR := X"0"; mem_init2 : BIT_VECTOR := X"0"; mem_init3 : BIT_VECTOR := X"0"; mem_init4 : BIT_VECTOR := X"0"; mem_init5 : BIT_VECTOR := X"0"; mem_init6 : BIT_VECTOR := X"0"; mem_init7 : BIT_VECTOR := X"0"; mem_init8 : BIT_VECTOR := X"0"; mem_init9 : BIT_VECTOR := X"0"; mem_init10 : BIT_VECTOR := X"0"; mem_init11 : BIT_VECTOR := X"0"; mem_init12 : BIT_VECTOR := X"0"; mem_init13 : BIT_VECTOR := X"0"; mem_init14 : BIT_VECTOR := X"0"; mem_init15 : BIT_VECTOR := X"0"; mem_init16 : BIT_VECTOR := X"0"; mem_init17 : BIT_VECTOR := X"0"; mem_init18 : BIT_VECTOR := X"0"; mem_init19 : BIT_VECTOR := X"0"; mem_init20 : BIT_VECTOR := X"0"; mem_init21 : BIT_VECTOR := X"0"; mem_init22 : BIT_VECTOR := X"0"; mem_init23 : BIT_VECTOR := X"0"; mem_init24 : BIT_VECTOR := X"0"; mem_init25 : BIT_VECTOR := X"0"; mem_init26 : BIT_VECTOR := X"0"; mem_init27 : BIT_VECTOR := X"0"; mem_init28 : BIT_VECTOR := X"0"; mem_init29 : BIT_VECTOR := X"0"; mem_init30 : BIT_VECTOR := X"0"; mem_init31 : BIT_VECTOR := X"0"; mem_init32 : BIT_VECTOR := X"0"; mem_init33 : BIT_VECTOR := X"0"; mem_init34 : BIT_VECTOR := X"0"; mem_init35 : BIT_VECTOR := X"0"; mem_init36 : BIT_VECTOR := X"0"; mem_init37 : BIT_VECTOR := X"0"; mem_init38 : BIT_VECTOR := X"0"; mem_init39 : BIT_VECTOR := X"0"; mem_init40 : BIT_VECTOR := X"0"; mem_init41 : BIT_VECTOR := X"0"; mem_init42 : BIT_VECTOR := X"0"; mem_init43 : BIT_VECTOR := X"0"; mem_init44 : BIT_VECTOR := X"0"; mem_init45 : BIT_VECTOR := X"0"; mem_init46 : BIT_VECTOR := X"0"; mem_init47 : BIT_VECTOR := X"0"; mem_init48 : BIT_VECTOR := X"0"; mem_init49 : BIT_VECTOR := X"0"; mem_init50 : BIT_VECTOR := X"0"; mem_init51 : BIT_VECTOR := X"0"; mem_init52 : BIT_VECTOR := X"0"; mem_init53 : BIT_VECTOR := X"0"; mem_init54 : BIT_VECTOR := X"0"; mem_init55 : BIT_VECTOR := X"0"; mem_init56 : BIT_VECTOR := X"0"; mem_init57 : BIT_VECTOR := X"0"; mem_init58 : BIT_VECTOR := X"0"; mem_init59 : BIT_VECTOR := X"0"; mem_init60 : BIT_VECTOR := X"0"; mem_init61 : BIT_VECTOR := X"0"; mem_init62 : BIT_VECTOR := X"0"; mem_init63 : BIT_VECTOR := X"0"; mem_init64 : BIT_VECTOR := X"0"; mem_init65 : BIT_VECTOR := X"0"; mem_init66 : BIT_VECTOR := X"0"; mem_init67 : BIT_VECTOR := X"0"; mem_init68 : BIT_VECTOR := X"0"; mem_init69 : BIT_VECTOR := X"0"; mem_init70 : BIT_VECTOR := X"0"; mem_init71 : BIT_VECTOR := X"0"; connectivity_checking : string := "off" ); -- -------- PORT DECLARATIONS --------- PORT ( portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0'); portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0'); portawe : IN STD_LOGIC := '0'; portare : IN STD_LOGIC := '1'; portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0'); portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0'); portbwe : IN STD_LOGIC := '0'; portbre : IN STD_LOGIC := '1'; clk0 : IN STD_LOGIC := '0'; clk1 : IN STD_LOGIC := '0'; ena0 : IN STD_LOGIC := '1'; ena1 : IN STD_LOGIC := '1'; ena2 : IN STD_LOGIC := '1'; ena3 : IN STD_LOGIC := '1'; clr0 : IN STD_LOGIC := '0'; clr1 : IN STD_LOGIC := '0'; portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); devclrn : IN STD_LOGIC := '1'; devpor : IN STD_LOGIC := '1'; portaaddrstall : IN STD_LOGIC := '0'; portbaddrstall : IN STD_LOGIC := '0'; eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0'); dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000"; portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) ); END hardcopyiii_ram_block; ARCHITECTURE block_arch OF hardcopyiii_ram_block IS COMPONENT hardcopyiii_ram_pulse_generator PORT ( clk : IN STD_LOGIC; ena : IN STD_LOGIC; delaywrite : IN STD_LOGIC := '0'; pulse : OUT STD_LOGIC; cycle : OUT STD_LOGIC ); END COMPONENT; COMPONENT hardcopyiii_ram_register GENERIC ( preset : STD_LOGIC := '0'; width : integer := 1 ); PORT ( d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0); clk : IN STD_LOGIC; aclr : IN STD_LOGIC; devclrn : IN STD_LOGIC; devpor : IN STD_LOGIC; ena : IN STD_LOGIC; stall : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0); aclrout : OUT STD_LOGIC ); END COMPONENT; FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS VARIABLE c: INTEGER; BEGIN IF (condition) THEN c := a; ELSE c := b; END IF; RETURN c; END; SUBTYPE port_type IS BOOLEAN; CONSTANT primary : port_type := TRUE; CONSTANT secondary : port_type := FALSE; CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width); CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a; CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom"); CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port"); CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port"); CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port"); CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1) AND (port_a_data_width /= port_b_data_width); CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1, cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width)))); CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width); CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width); CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width); CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width); CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width; CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width; CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED"); CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED"); CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0'); CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0'); CONSTANT ram_type : BOOLEAN := FALSE; TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC; CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0'); -- Hardware write modes CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR operation_mode = "bidir_dual_port") AND (port_b_address_clock = "clock1"); CONSTANT both_new_data_same_port : BOOLEAN := ( ((port_a_read_during_write_mode = "new_data_no_nbe_read") OR (port_a_read_during_write_mode = "dont_care")) AND ((port_b_read_during_write_mode = "new_data_no_nbe_read") OR (port_b_read_during_write_mode = "dont_care")) ); SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1); SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1); SIGNAL delay_write_pulse_a : STD_LOGIC ; SIGNAL delay_write_pulse_b : STD_LOGIC ; CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read"); CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read"); CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data"); CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data"); SIGNAL read_before_write_a : BOOLEAN; SIGNAL read_before_write_b : BOOLEAN; -- -------- internal signals --------- -- clock / clock enable SIGNAL clk_a_in,clk_b_in : STD_LOGIC; SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC; SIGNAL clk_a_out,clk_b_out : STD_LOGIC; SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC; SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC; SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC; SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC; SIGNAL clk_a_core : STD_LOGIC; SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC; SIGNAL clk_b_core : STD_LOGIC; SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0); -- asynch clear TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN; TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC; SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC; SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC; SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC; SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type; SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type; SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC; SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC; SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC; SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC; SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC; SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC; SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC; SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type; SIGNAL clear_asserted_during_write : clear_vec_type; -- port A registers SIGNAL we_a_reg : STD_LOGIC; SIGNAL re_a_reg : STD_LOGIC; SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type; SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type; SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0); SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0); -- port B registers SIGNAL we_b_reg, re_b_reg : STD_LOGIC; SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type; SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0); SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0); SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0); SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0); SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0); -- pulses TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC; SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec; SIGNAL rw_pulse : pulse_vec; SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC; SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC; SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC; SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC; -- registered address SIGNAL addr_prime_reg,addr_sec_reg : INTEGER; -- input/output SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0); -- overlapping location write SIGNAL dual_write : BOOLEAN; -- byte enable mask write TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN; SIGNAL be_mask_write : be_mask_write_vec; -- memory core SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0); SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0); TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type; TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type; SIGNAL mem : mem_type; SIGNAL init_mem : BOOLEAN := FALSE; CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X'))); CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X')); CONSTANT col_x : mem_col_type := (OTHERS => 'X'); SIGNAL mem_data : mem_row_type; SIGNAL old_mem_data : mem_row_type; SIGNAL mem_unit_data : mem_col_type; -- latches TYPE read_latch_rec IS RECORD prime : mem_row_type; sec : mem_col_type; END RECORD; SIGNAL read_latch : read_latch_rec; -- (row,column) coordinates SIGNAL row_sec,col_sec : INTEGER; -- byte enable TYPE mask_type IS (normal,inverse); TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type; TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type; TYPE mask_rec IS RECORD prime : mask_prime_type; sec : mask_sec_type; END RECORD; SIGNAL mask_vector : mask_rec; SIGNAL mask_vector_common : mem_col_type; FUNCTION get_mask( b_ena : IN STD_LOGIC_VECTOR; mode : port_type; CONSTANT b_ena_width ,byte_size: INTEGER ) RETURN mask_rec IS VARIABLE l : INTEGER; VARIABLE mask : mask_rec := ( (normal => (OTHERS => '0'),inverse => (OTHERS => 'X')), (normal => (OTHERS => '0'),inverse => (OTHERS => 'X')) ); BEGIN FOR l in 0 TO b_ena_width - 1 LOOP IF (b_ena(l) = '0') THEN IF (mode = primary) THEN mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X'); mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0'); ELSE mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X'); mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0'); END IF; ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN IF (mode = primary) THEN mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X'); ELSE mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X'); END IF; END IF; END LOOP; RETURN mask; END get_mask; -- port active for read/write SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type; SIGNAL active_a_in,active_b_in : STD_LOGIC; SIGNAL active_write_a : BOOLEAN; SIGNAL active_write_b : BOOLEAN; SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC; SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC; SIGNAL active_a_core, active_b_core : BOOLEAN; SIGNAL wire_vcc : STD_LOGIC := '1'; SIGNAL wire_gnd : STD_LOGIC := '0'; BEGIN -- memory initialization init_mem <= TRUE; -- hardware write modes hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR (port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE " FW" WHEN (dual_clock OR ( mixed_port_feed_through_mode = "dont_care" AND both_new_data_same_port )) ELSE " DW"; hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR (port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE " FW" WHEN (dual_clock OR ( mixed_port_feed_through_mode = "dont_care" AND both_new_data_same_port )) ELSE " DW"; delay_write_pulse_a <= '0' WHEN (mode_is_dp AND mixed_port_feed_through_mode = "dont_care") ELSE '1' WHEN (hw_write_mode_a /= " FW") ELSE '0'; delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ; read_before_write_a <= (hw_write_mode_a = "R+W"); read_before_write_b <= (hw_write_mode_b = "R+W"); -- -------- core logic --------------- clk_a_in <= clk0; clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in; clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in; clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in; clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1; clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1; clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1; clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE clk1; clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE clk1; clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1; addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0; addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1; datain_a_clr_in <= '0'; datain_b_clr_in <= '0'; dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1; dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1; byteena_a_clr_in <= '0'; byteena_b_clr_in <= '0'; we_a_clr_in <= '0'; re_a_clr_in <= '0'; we_b_clr_in <= '0'; re_b_clr_in <= '0'; active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE ena2; active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE ena2; be_mask_write(primary_port_is_a) <= be_mask_write_a; be_mask_write(primary_port_is_b) <= be_mask_write_b; active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE ena2; active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE ena3; active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1; active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE ena2; active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE ena3; active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1; active_write_a <= (byteena_a_reg /= bytes_a_disabled); active_write_b <= (byteena_b_reg /= bytes_b_disabled); -- Store core clock enable value for delayed write -- port A core active active_a_core_in_vec(0) <= active_a_core_in; active_core_port_a : hardcopyiii_ram_register GENERIC MAP ( width => 1 ) PORT MAP ( d => active_a_core_in_vec, clk => clk_a_in, aclr => wire_gnd, devclrn => wire_vcc,devpor => wire_vcc, ena => wire_vcc, stall => wire_gnd, q => active_a_core_out ); active_a_core <= (active_a_core_out(0) = '1'); -- port B core active active_b_core_in_vec(0) <= active_b_core_in; active_core_port_b : hardcopyiii_ram_register GENERIC MAP ( width => 1 ) PORT MAP ( d => active_b_core_in_vec, clk => clk_b_in, aclr => wire_gnd, devclrn => wire_vcc,devpor => wire_vcc, ena => wire_vcc, stall => wire_gnd, q => active_b_core_out ); active_b_core <= (active_b_core_out(0) = '1'); -- ------ A input registers -- write enable we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe; we_a_register : hardcopyiii_ram_register GENERIC MAP ( width => 1 ) PORT MAP ( d => we_a_reg_in, clk => clk_a_wena, aclr => we_a_clr_in, devclrn => devclrn, devpor => devpor, stall => wire_gnd, ena => active_a_core_in, q => we_a_reg_out, aclrout => we_a_clr ); we_a_reg <= we_a_reg_out(0); -- read enable re_a_reg_in(0) <= portare; re_a_register : hardcopyiii_ram_register GENERIC MAP ( width => 1 ) PORT MAP ( d => re_a_reg_in, clk => clk_a_rena, aclr => re_a_clr_in, devclrn => devclrn, devpor => devpor, stall => wire_gnd, ena => active_a_core_in, q => re_a_reg_out, aclrout => re_a_clr ); re_a_reg <= re_a_reg_out(0); -- address addr_a_register : hardcopyiii_ram_register GENERIC MAP ( width => port_a_address_width ) PORT MAP ( d => portaaddr, clk => clk_a_in, aclr => addr_a_clr_in, devclrn => devclrn, devpor => devpor, stall => portaaddrstall, ena => active_a_in, q => addr_a_reg, aclrout => addr_a_clr ); -- data datain_a_register : hardcopyiii_ram_register GENERIC MAP ( width => port_a_data_width ) PORT MAP ( d => portadatain, clk => clk_a_in, aclr => datain_a_clr_in, devclrn => devclrn, devpor => devpor, stall => wire_gnd, ena => active_a_in, q => datain_a_reg, aclrout => datain_a_clr ); -- byte enable byteena_a_register : hardcopyiii_ram_register GENERIC MAP ( width => port_a_byte_enable_mask_width, preset => '1' ) PORT MAP ( d => portabyteenamasks, clk => clk_a_byteena, aclr => byteena_a_clr_in, devclrn => devclrn, devpor => devpor, stall => wire_gnd, ena => active_a_in, q => byteena_a_reg, aclrout => byteena_a_clr ); -- ------ B input registers -- read enable re_b_reg_in(0) <= portbre; re_b_register : hardcopyiii_ram_register GENERIC MAP ( width => 1 ) PORT MAP ( d => re_b_reg_in, clk => clk_b_in, aclr => re_b_clr_in, devclrn => devclrn, devpor => devpor, stall => wire_gnd, ena => active_b_core_in, q => re_b_reg_out, aclrout => re_b_clr ); re_b_reg <= re_b_reg_out(0); -- write enable we_b_reg_in(0) <= portbwe; we_b_register : hardcopyiii_ram_register GENERIC MAP ( width => 1 ) PORT MAP ( d => we_b_reg_in, clk => clk_b_in, aclr => we_b_clr_in, devclrn => devclrn, devpor => devpor, stall => wire_gnd, ena => active_b_core_in, q => we_b_reg_out, aclrout => we_b_clr ); we_b_reg <= we_b_reg_out(0); -- address addr_b_register : hardcopyiii_ram_register GENERIC MAP ( width => port_b_address_width ) PORT MAP ( d => portbaddr, clk => clk_b_in, aclr => addr_b_clr_in, devclrn => devclrn, devpor => devpor, stall => portbaddrstall, ena => active_b_in, q => addr_b_reg, aclrout => addr_b_clr ); -- data datain_b_register : hardcopyiii_ram_register GENERIC MAP ( width => port_b_data_width ) PORT MAP ( d => portbdatain, clk => clk_b_in, aclr => datain_b_clr_in, devclrn => devclrn, devpor => devpor, stall => wire_gnd, ena => active_b_in, q => datain_b_reg, aclrout => datain_b_clr ); -- byte enable byteena_b_register : hardcopyiii_ram_register GENERIC MAP ( width => port_b_byte_enable_mask_width, preset => '1' ) PORT MAP ( d => portbbyteenamasks, clk => clk_b_byteena, aclr => byteena_b_clr_in, devclrn => devclrn, devpor => devpor, stall => wire_gnd, ena => active_b_in, q => byteena_b_reg, aclrout => byteena_b_clr ); datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg; addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg); datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg; addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg); -- Write pulse generation wpgen_a_clk <= clk_a_in; wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0'; wpgen_a : hardcopyiii_ram_pulse_generator PORT MAP ( clk => wpgen_a_clk, ena => wpgen_a_clkena, delaywrite => delay_write_pulse_a, pulse => write_pulse(primary_port_is_a), cycle => write_cycle_a ); wpgen_b_clk <= clk_b_in; wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0'; wpgen_b : hardcopyiii_ram_pulse_generator PORT MAP ( clk => wpgen_b_clk, ena => wpgen_b_clkena, delaywrite => delay_write_pulse_b, pulse => write_pulse(primary_port_is_b), cycle => write_cycle_b ); -- Read pulse generation rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0')) ELSE '0'; rpgen_a : hardcopyiii_ram_pulse_generator PORT MAP ( clk => clk_a_in, ena => rpgen_a_clkena, cycle => clk_a_core, pulse => read_pulse(primary_port_is_a) ); rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0')) ELSE '0'; rpgen_b : hardcopyiii_ram_pulse_generator PORT MAP ( clk => clk_b_in, ena => rpgen_b_clkena, cycle => clk_b_core, pulse => read_pulse(primary_port_is_b) ); -- Read-during-Write pulse generation rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a) ELSE '0'; rwpgen_a : hardcopyiii_ram_pulse_generator PORT MAP ( clk => clk_a_in, ena => rwpgen_a_clkena, pulse => rw_pulse(primary_port_is_a) ); rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b) ELSE '0'; rwpgen_b : hardcopyiii_ram_pulse_generator PORT MAP ( clk => clk_b_in, ena => rwpgen_b_clkena, pulse => rw_pulse(primary_port_is_b) ); -- Create internal masks for byte enable processing mask_create : PROCESS (byteena_a_reg,byteena_b_reg) VARIABLE mask : mask_rec; BEGIN IF (byteena_a_reg'EVENT) THEN mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a); IF (primary_port_is_a) THEN mask_vector.prime <= mask.prime; ELSE mask_vector.sec <= mask.sec; END IF; END IF; IF (byteena_b_reg'EVENT) THEN mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b); IF (primary_port_is_b) THEN mask_vector.prime <= mask.prime; ELSE mask_vector.sec <= mask.sec; END IF; END IF; END PROCESS mask_create; -- (row,col) coordinates row_sec <= addr_sec_reg / num_cols; col_sec <= addr_sec_reg mod num_cols; mem_rw : PROCESS (init_mem, write_pulse,read_pulse,read_pulse_feedthru, rw_pulse, mem_invalidate,mem_invalidate_loc,read_latch_invalidate) -- mem init TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN; VARIABLE addr_range_init,row,col,index : INTEGER; VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0); VARIABLE mem_init : bit_vector(mem_init71'length + mem_init70'length + mem_init69'length + mem_init68'length + mem_init67'length + mem_init66'length + mem_init65'length + mem_init64'length + mem_init63'length + mem_init62'length + mem_init61'length + mem_init60'length + mem_init59'length + mem_init58'length + mem_init57'length + mem_init56'length + mem_init55'length + mem_init54'length + mem_init53'length + mem_init52'length + mem_init51'length + mem_init50'length + mem_init49'length + mem_init48'length + mem_init47'length + mem_init46'length + mem_init45'length + mem_init44'length + mem_init43'length + mem_init42'length + mem_init41'length + mem_init40'length + mem_init39'length + mem_init38'length + mem_init37'length + mem_init36'length + mem_init35'length + mem_init34'length + mem_init33'length + mem_init32'length + mem_init31'length + mem_init30'length + mem_init29'length + mem_init28'length + mem_init27'length + mem_init26'length + mem_init25'length + mem_init24'length + mem_init23'length + mem_init22'length + mem_init21'length + mem_init20'length + mem_init19'length + mem_init18'length + mem_init17'length + mem_init16'length + mem_init15'length + mem_init14'length + mem_init13'length + mem_init12'length + mem_init11'length + mem_init10'length + mem_init9'length + mem_init8'length + mem_init7'length + mem_init6'length + mem_init5'length + mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length + mem_init0'length - 1 DOWNTO 0); VARIABLE mem_val : mem_type; -- read/write VARIABLE mem_data_p : mem_row_type; VARIABLE old_mem_data_p : mem_row_type; VARIABLE row_prime,col_prime : INTEGER; VARIABLE access_same_location : BOOLEAN; VARIABLE read_during_write : rw_type; BEGIN read_during_write := (FALSE,FALSE); -- Memory initialization IF (init_mem'EVENT) THEN -- Initialize output latches to 0 IF (primary_port_is_a) THEN dataout_prime <= (OTHERS => '0'); IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF; ELSE dataout_sec <= (OTHERS => '0'); IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF; END IF; IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN mem_val := (OTHERS => (OTHERS => (OTHERS => '0'))); END IF; IF (primary_port_is_a) THEN addr_range_init := port_a_last_address - port_a_first_address + 1; ELSE addr_range_init := port_b_last_address - port_b_first_address + 1; END IF; IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN mem_init := mem_init71 & mem_init70 & mem_init69 & mem_init68 & mem_init67 & mem_init66 & mem_init65 & mem_init64 & mem_init63 & mem_init62 & mem_init61 & mem_init60 & mem_init59 & mem_init58 & mem_init57 & mem_init56 & mem_init55 & mem_init54 & mem_init53 & mem_init52 & mem_init51 & mem_init50 & mem_init49 & mem_init48 & mem_init47 & mem_init46 & mem_init45 & mem_init44 & mem_init43 & mem_init42 & mem_init41 & mem_init40 & mem_init39 & mem_init38 & mem_init37 & mem_init36 & mem_init35 & mem_init34 & mem_init33 & mem_init32 & mem_init31 & mem_init30 & mem_init29 & mem_init28 & mem_init27 & mem_init26 & mem_init25 & mem_init24 & mem_init23 & mem_init22 & mem_init21 & mem_init20 & mem_init19 & mem_init18 & mem_init17 & mem_init16 & mem_init15 & mem_init14 & mem_init13 & mem_init12 & mem_init11 & mem_init10 & mem_init9 & mem_init8 & mem_init7 & mem_init6 & mem_init5 & mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0; mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0); FOR row IN 0 TO addr_range_init - 1 LOOP FOR col IN 0 to num_cols - 1 LOOP index := row * data_width; mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO index + col*data_unit_width); END LOOP; END LOOP; END IF; mem <= mem_val; END IF; access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec); -- Read before Write stage 1 : read data from memory -- Read before Write stage 2 : send data to output IF (rw_pulse(primary)'EVENT) THEN IF (rw_pulse(primary) = '1') THEN read_latch.prime <= mem(addr_prime_reg); ELSE IF (be_mask_write(primary)) THEN FOR i IN 0 TO data_width - 1 LOOP IF (mask_vector.prime(normal)(i) = 'X') THEN row_prime := i / data_unit_width; col_prime := i mod data_unit_width; dataout_prime(i) <= read_latch.prime(row_prime)(col_prime); END IF; END LOOP; ELSE FOR i IN 0 TO data_width - 1 LOOP row_prime := i / data_unit_width; col_prime := i mod data_unit_width; dataout_prime(i) <= read_latch.prime(row_prime)(col_prime); END LOOP; END IF; END IF; END IF; IF (rw_pulse(secondary)'EVENT) THEN IF (rw_pulse(secondary) = '1') THEN read_latch.sec <= mem(row_sec)(col_sec); ELSE IF (be_mask_write(secondary)) THEN FOR i IN 0 TO data_unit_width - 1 LOOP IF (mask_vector.sec(normal)(i) = 'X') THEN dataout_sec(i) <= read_latch.sec(i); END IF; END LOOP; ELSE dataout_sec <= read_latch.sec; END IF; END IF; END IF; -- Write stage 1 : X to buffer -- Write stage 2 : actual data to memory IF (write_pulse(primary)'EVENT) THEN IF (write_pulse(primary) = '1') THEN old_mem_data_p := mem(addr_prime_reg); mem_data_p := mem(addr_prime_reg); FOR i IN 0 TO num_cols - 1 LOOP mem_data_p(i) := mem_data_p(i) XOR mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width); END LOOP; read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1'); IF (read_during_write(secondary)) THEN read_latch.sec <= old_mem_data_p(col_sec); ELSE mem_data <= mem_data_p; END IF; ELSIF (clear_asserted_during_write(primary) /= '1') THEN FOR i IN 0 TO data_width - 1 LOOP IF (mask_vector.prime(normal)(i) = '0') THEN mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i); ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X'; END IF; END LOOP; END IF; END IF; IF (write_pulse(secondary)'EVENT) THEN IF (write_pulse(secondary) = '1') THEN read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1'); IF (read_during_write(primary)) THEN read_latch.prime <= mem(addr_prime_reg); read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse); ELSE mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse); END IF; IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN mask_vector_common <= mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND mask_vector.sec(inverse); dual_write <= TRUE; END IF; ELSIF (clear_asserted_during_write(secondary) /= '1') THEN FOR i IN 0 TO data_unit_width - 1 LOOP IF (mask_vector.sec(normal)(i) = '0') THEN mem(row_sec)(col_sec)(i) <= datain_sec_reg(i); ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN mem(row_sec)(col_sec)(i) <= 'X'; END IF; END LOOP; END IF; END IF; -- Simultaneous write IF (dual_write AND write_pulse = "00") THEN mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common; dual_write <= FALSE; END IF; -- Read stage 1 : read data -- Read stage 2 : send data to output IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN IF (read_pulse(primary) = '1') THEN read_latch.prime <= mem(addr_prime_reg); IF (access_same_location AND write_pulse(secondary) = '1') THEN read_latch.prime(col_sec) <= mem_unit_data; END IF; ELSE FOR i IN 0 TO data_width - 1 LOOP row_prime := i / data_unit_width; col_prime := i mod data_unit_width; dataout_prime(i) <= read_latch.prime(row_prime)(col_prime); END LOOP; END IF; END IF; IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN IF (read_pulse(secondary) = '1') THEN IF (access_same_location AND write_pulse(primary) = '1') THEN read_latch.sec <= mem_data(col_sec); ELSE read_latch.sec <= mem(row_sec)(col_sec); END IF; ELSE dataout_sec <= read_latch.sec; END IF; END IF; -- Same port feed thru IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN IF (be_mask_write(primary)) THEN FOR i IN 0 TO data_width - 1 LOOP IF (mask_vector.prime(normal)(i) = '0') THEN dataout_prime(i) <= datain_prime_reg(i); END IF; END LOOP; ELSE dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal); END IF; END IF; IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN IF (be_mask_write(secondary)) THEN FOR i IN 0 TO data_unit_width - 1 LOOP IF (mask_vector.sec(normal)(i) = '0') THEN dataout_sec(i) <= datain_sec_reg(i); END IF; END LOOP; ELSE dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal); END IF; END IF; -- Async clear IF (mem_invalidate'EVENT) THEN IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN mem <= mem_x; END IF; END IF; IF (mem_invalidate_loc'EVENT) THEN IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF; IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF; END IF; IF (read_latch_invalidate'EVENT) THEN IF (read_latch_invalidate(primary)) THEN read_latch.prime <= row_x; END IF; IF (read_latch_invalidate(secondary)) THEN read_latch.sec <= col_x; END IF; END IF; END PROCESS mem_rw; -- Same port feed through ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1')) ELSE '0'; ftpgen_a : hardcopyiii_ram_pulse_generator PORT MAP ( clk => clk_a_in, ena => ftpgen_a_clkena, pulse => read_pulse_feedthru(primary_port_is_a) ); ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1')) ELSE '0'; ftpgen_b : hardcopyiii_ram_pulse_generator PORT MAP ( clk => clk_b_in, ena => ftpgen_b_clkena, pulse => read_pulse_feedthru(primary_port_is_b) ); -- Asynch clear events clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr) BEGIN IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a); IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns; ELSIF (active_a_core AND re_a_reg = '1') THEN read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns; END IF; END IF; IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a); IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns; read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns; END IF; END IF; END PROCESS clear_a; clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr) BEGIN IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b); IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns; ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1') THEN read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns; END IF; END IF; IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b); IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns; read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns; END IF; END IF; END PROCESS clear_b; -- Clear mux registers (Latch Clear) -- Port A output register clear dataout_a_clr_reg_in(0) <= dataout_a_clr; aclr_a_mux_register : hardcopyiii_ram_register GENERIC MAP ( width => 1 ) PORT MAP ( d => dataout_a_clr_reg_in, clk => clk_a_core, aclr => wire_gnd, devclrn => devclrn, devpor => devpor, stall => wire_gnd, ena => wire_vcc, q => dataout_a_clr_reg_out ); dataout_a_clr_reg <= dataout_a_clr_reg_out(0); -- Port B output register clear dataout_b_clr_reg_in(0) <= dataout_b_clr; aclr_b_mux_register : hardcopyiii_ram_register GENERIC MAP ( width => 1 ) PORT MAP ( d => dataout_b_clr_reg_in, clk => clk_b_core, aclr => wire_gnd, devclrn => devclrn, devpor => devpor, stall => wire_gnd, ena => wire_vcc, q => dataout_b_clr_reg_out ); dataout_b_clr_reg <= dataout_b_clr_reg_out(0); -- ------ Output registers clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0; clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1; clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1; clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1; dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec; dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE dataout_prime WHEN primary_port_is_b ELSE dataout_sec; dataout_a_register : hardcopyiii_ram_register GENERIC MAP ( width => port_a_data_width ) PORT MAP ( d => dataout_a, clk => clk_a_out, aclr => dataout_a_clr, devclrn => devclrn, devpor => devpor, stall => wire_gnd, ena => clkena_a_out, q => dataout_a_reg ); dataout_b_register : hardcopyiii_ram_register GENERIC MAP ( width => port_b_data_width ) PORT MAP ( d => dataout_b, clk => clk_b_out, aclr => dataout_b_clr, devclrn => devclrn, devpor => devpor, stall => wire_gnd, ena => clkena_b_out, q => dataout_b_reg ); portadataout <= dataout_a_reg WHEN (out_a_is_reg) ELSE (OTHERS => '0') WHEN ((dataout_a_clr = '1') OR (dataout_a_clr_reg = '1')) ELSE dataout_a; portbdataout <= dataout_b_reg WHEN (out_b_is_reg) ELSE (OTHERS => '0') WHEN ((dataout_b_clr = '1') OR (dataout_b_clr_reg = '1')) ELSE dataout_b; eccstatus <= (OTHERS => '0'); dftout <= (OTHERS => '0'); END block_arch; --------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_ff -- -- Description : HARDCOPYIII FF VHDL simulation model -- -- --------------------------------------------------------------------- LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; use work.hardcopyiii_and1; entity hardcopyiii_ff is generic ( power_up : string := "low"; x_on_violation : string := "on"; lpm_type : string := "hardcopyiii_ff"; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_asdata_q: VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_d : VitalDelayType01 := DefPropDelay01; tipd_asdata : VitalDelayType01 := DefPropDelay01; tipd_sclr : VitalDelayType01 := DefPropDelay01; tipd_sload : VitalDelayType01 := DefPropDelay01; tipd_clrn : VitalDelayType01 := DefPropDelay01; tipd_aload : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; InstancePath: STRING := "*" ); port ( d : in std_logic := '0'; clk : in std_logic := '0'; clrn : in std_logic := '1'; aload : in std_logic := '0'; sclr : in std_logic := '0'; sload : in std_logic := '0'; ena : in std_logic := '1'; asdata : in std_logic := '0'; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; q : out std_logic ); attribute VITAL_LEVEL0 of hardcopyiii_ff : entity is TRUE; end hardcopyiii_ff; architecture vital_lcell_ff of hardcopyiii_ff is attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE; signal clk_ipd : std_logic; signal d_ipd : std_logic; signal d_dly : std_logic; signal asdata_ipd : std_logic; signal asdata_dly : std_logic; signal asdata_dly1 : std_logic; signal sclr_ipd : std_logic; signal sload_ipd : std_logic; signal clrn_ipd : std_logic; signal aload_ipd : std_logic; signal ena_ipd : std_logic; component hardcopyiii_and1 generic (XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; tpd_IN1_Y : VitalDelayType01 := DefPropDelay01; tipd_IN1 : VitalDelayType01 := DefPropDelay01 ); port (Y : out STD_LOGIC; IN1 : in STD_LOGIC ); end component; begin ddelaybuffer: hardcopyiii_and1 port map(IN1 => d_ipd, Y => d_dly); asdatadelaybuffer: hardcopyiii_and1 port map(IN1 => asdata_ipd, Y => asdata_dly); asdatadelaybuffer1: hardcopyiii_and1 port map(IN1 => asdata_dly, Y => asdata_dly1); --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (d_ipd, d, tipd_d); VitalWireDelay (asdata_ipd, asdata, tipd_asdata); VitalWireDelay (sclr_ipd, sclr, tipd_sclr); VitalWireDelay (sload_ipd, sload, tipd_sload); VitalWireDelay (clrn_ipd, clrn, tipd_clrn); VitalWireDelay (aload_ipd, aload, tipd_aload); VitalWireDelay (ena_ipd, ena, tipd_ena); end block; VITALtiming : process (clk_ipd, d_dly, asdata_dly1, sclr_ipd, sload_ipd, clrn_ipd, aload_ipd, ena_ipd, devclrn, devpor) variable Tviol_d_clk : std_ulogic := '0'; variable Tviol_asdata_clk : std_ulogic := '0'; variable Tviol_sclr_clk : std_ulogic := '0'; variable Tviol_sload_clk : std_ulogic := '0'; variable Tviol_ena_clk : std_ulogic := '0'; variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit; variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit; variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit; variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit; variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit; variable q_VitalGlitchData : VitalGlitchDataType; variable iq : std_logic := '0'; variable idata: std_logic := '0'; -- variables for 'X' generation variable violation : std_logic := '0'; begin if (now = 0 ns) then if (power_up = "low") then iq := '0'; elsif (power_up = "high") then iq := '1'; end if; end if; ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_d_clk, TimingData => TimingData_d_clk, TestSignal => d, TestSignalName => "DATAIN", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_d_clk_noedge_posedge, SetupLow => tsetup_d_clk_noedge_posedge, HoldHigh => thold_d_clk_noedge_posedge, HoldLow => thold_d_clk_noedge_posedge, CheckEnabled => TO_X01((NOT clrn_ipd) OR (sload_ipd) OR (sclr_ipd) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1', RefTransition => '/', HeaderMsg => InstancePath & "/LCELL_FF", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_asdata_clk, TimingData => TimingData_asdata_clk, TestSignal => asdata_ipd, TestSignalName => "ASDATA", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_asdata_clk_noedge_posedge, SetupLow => tsetup_asdata_clk_noedge_posedge, HoldHigh => thold_asdata_clk_noedge_posedge, HoldLow => thold_asdata_clk_noedge_posedge, CheckEnabled => TO_X01((NOT clrn_ipd) OR (NOT sload_ipd) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1', RefTransition => '/', HeaderMsg => InstancePath & "/LCELL_FF", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_sclr_clk, TimingData => TimingData_sclr_clk, TestSignal => sclr_ipd, TestSignalName => "SCLR", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_sclr_clk_noedge_posedge, SetupLow => tsetup_sclr_clk_noedge_posedge, HoldHigh => thold_sclr_clk_noedge_posedge, HoldLow => thold_sclr_clk_noedge_posedge, CheckEnabled => TO_X01((NOT clrn_ipd) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1', RefTransition => '/', HeaderMsg => InstancePath & "/LCELL_FF", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_sload_clk, TimingData => TimingData_sload_clk, TestSignal => sload_ipd, TestSignalName => "SLOAD", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_sload_clk_noedge_posedge, SetupLow => tsetup_sload_clk_noedge_posedge, HoldHigh => thold_sload_clk_noedge_posedge, HoldLow => thold_sload_clk_noedge_posedge, CheckEnabled => TO_X01((NOT clrn_ipd) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1', RefTransition => '/', HeaderMsg => InstancePath & "/LCELL_FF", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_ena_clk, TimingData => TimingData_ena_clk, TestSignal => ena_ipd, TestSignalName => "ENA", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_ena_clk_noedge_posedge, SetupLow => tsetup_ena_clk_noedge_posedge, HoldHigh => thold_ena_clk_noedge_posedge, HoldLow => thold_ena_clk_noedge_posedge, CheckEnabled => TO_X01((NOT clrn_ipd) OR (NOT devpor) OR (NOT devclrn) ) /= '1', RefTransition => '/', HeaderMsg => InstancePath & "/LCELL_FF", XOn => XOnChecks, MsgOn => MsgOnChecks ); end if; violation := Tviol_d_clk or Tviol_asdata_clk or Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk; if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then iq := '0'; elsif (aload_ipd = '1') then iq := asdata_dly1; elsif (violation = 'X' and x_on_violation = "on") then iq := 'X'; elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then if (ena_ipd = '1') then if (sclr_ipd = '1') then iq := '0'; elsif (sload_ipd = '1') then iq := asdata_dly1; else iq := d_dly; end if; end if; end if; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => q, OutSignalName => "Q", OutTemp => iq, Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE), 1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE), 2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE), 3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)), GlitchData => q_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; end vital_lcell_ff; --///////////////////////////////////////////////////////////////////////////// -- -- VHDL Simulation Model for HARDCOPYIII CLKSELECT Atom -- --///////////////////////////////////////////////////////////////////////////// -- -- -- HARDCOPYIII_CLKSELECT Model -- -- LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; entity hardcopyiii_clkselect is generic ( lpm_type : STRING := "hardcopyiii_clkselect"; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : STRING := "*"; tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01) ); port ( inclk : in std_logic_vector(3 downto 0) := "0000"; clkselect : in std_logic_vector(1 downto 0) := "00"; outclk : out std_logic ); attribute VITAL_LEVEL0 of hardcopyiii_clkselect : entity is TRUE; end hardcopyiii_clkselect; architecture vital_clkselect of hardcopyiii_clkselect is attribute VITAL_LEVEL0 of vital_clkselect : architecture is TRUE; signal inclk_ipd : std_logic_vector(3 downto 0); signal clkselect_ipd : std_logic_vector(1 downto 0); signal clkmux_out : std_logic; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0)); VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1)); VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2)); VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3)); VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0)); VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1)); end block; process(inclk_ipd, clkselect_ipd) variable outclk_VitalGlitchData : VitalGlitchDataType; variable tmp : std_logic; begin if (clkselect_ipd = "11") then tmp := inclk_ipd(3); elsif (clkselect_ipd = "10") then tmp := inclk_ipd(2); elsif (clkselect_ipd = "01") then tmp := inclk_ipd(1); else tmp := inclk_ipd(0); end if; clkmux_out <= tmp; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => outclk, OutSignalName => "OUTCLOCK", OutTemp => tmp, Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE), 1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE), 2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE), 3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE), 4 => (clkselect_ipd(0)'last_event, tpd_clkselect_outclk(0), TRUE), 5 => (clkselect_ipd(1)'last_event, tpd_clkselect_outclk(1), TRUE)), GlitchData => outclk_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; end vital_clkselect; --///////////////////////////////////////////////////////////////////////////// -- -- hardcopyiii_and2 Model -- Description : Simulation model for a simple two input AND gate. -- --///////////////////////////////////////////////////////////////////////////// LIBRARY IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; use work.hardcopyiii_atom_pack.all; -- entity declaration -- entity hardcopyiii_and2 is generic( TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; InstancePath: STRING := "*"; tpd_IN1_Y : VitalDelayType01 := DefPropDelay01; tpd_IN2_Y : VitalDelayType01 := DefPropDelay01; tipd_IN1 : VitalDelayType01 := DefPropDelay01; tipd_IN2 : VitalDelayType01 := DefPropDelay01); port( Y : out STD_LOGIC; IN1 : in STD_LOGIC; IN2 : in STD_LOGIC); attribute VITAL_LEVEL0 of hardcopyiii_and2 : entity is TRUE; end hardcopyiii_and2; -- architecture body -- architecture AltVITAL of hardcopyiii_and2 is attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE; SIGNAL IN1_ipd : STD_ULOGIC := 'U'; SIGNAL IN2_ipd : STD_ULOGIC := 'U'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (IN1_ipd, IN1, tipd_IN1); VitalWireDelay (IN2_ipd, IN2, tipd_IN2); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (IN1_ipd, IN2_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_ULOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := TO_X01(IN1_ipd) AND TO_X01(IN2_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, OutSignalName => "Y", OutTemp => Y_zd, Paths => ( 0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE), 1 => (IN2_ipd'last_event, tpd_IN2_Y, TRUE)), GlitchData => Y_GlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; end AltVITAL; --///////////////////////////////////////////////////////////////////////////// -- -- Entity Name : hardcopyiii_ena_reg -- -- Description : Simulation model for a simple DFF. -- This is used for the gated clock generation -- Powers upto 1. -- --///////////////////////////////////////////////////////////////////////////// LIBRARY IEEE; USE IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_ena_reg is generic ( TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : STRING := "*"; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tipd_d : VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01 ); PORT ( clk : in std_logic; ena : in std_logic := '1'; d : in std_logic; clrn : in std_logic := '1'; prn : in std_logic := '1'; q : out std_logic ); attribute VITAL_LEVEL0 of hardcopyiii_ena_reg : entity is TRUE; end hardcopyiii_ena_reg; ARCHITECTURE behave of hardcopyiii_ena_reg is attribute VITAL_LEVEL0 of behave : architecture is TRUE; signal d_ipd : std_logic; signal clk_ipd : std_logic; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (d_ipd, d, tipd_d); VitalWireDelay (clk_ipd, clk, tipd_clk); end block; VITALtiming : process (clk_ipd, prn, clrn) variable Tviol_d_clk : std_ulogic := '0'; variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit; variable q_VitalGlitchData : VitalGlitchDataType; variable q_reg : std_logic := '1'; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_d_clk, TimingData => TimingData_d_clk, TestSignal => d, TestSignalName => "D", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_d_clk_noedge_posedge, SetupLow => tsetup_d_clk_noedge_posedge, HoldHigh => thold_d_clk_noedge_posedge, HoldLow => thold_d_clk_noedge_posedge, CheckEnabled => TO_X01((clrn) OR (NOT ena)) /= '1', RefTransition => '/', HeaderMsg => InstancePath & "/hardcopyiii_ena_reg", XOn => XOnChecks, MsgOn => MsgOnChecks ); end if; if (prn = '0') then q_reg := '1'; elsif (clrn = '0') then q_reg := '0'; elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then q_reg := d_ipd; end if; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => q, OutSignalName => "Q", OutTemp => q_reg, Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)), GlitchData => q_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; end behave; --///////////////////////////////////////////////////////////////////////////// -- -- VHDL Simulation Model for HARDCOPYIII CLKCTRL Atom -- --///////////////////////////////////////////////////////////////////////////// -- -- -- HARDCOPYIII_CLKENA Model -- -- LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; use work.hardcopyiii_ena_reg; use work.hardcopyiii_and2; entity hardcopyiii_clkena is generic ( clock_type : STRING := "Auto"; lpm_type : STRING := "hardcopyiii_clkena"; ena_register_mode : STRING := "Falling Edge"; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : STRING := "*"; tipd_inclk : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01 ); port ( inclk : in std_logic := '0'; ena : in std_logic := '1'; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; enaout : out std_logic; outclk : out std_logic ); attribute VITAL_LEVEL0 of hardcopyiii_clkena : entity is TRUE; end hardcopyiii_clkena; architecture vital_clkena of hardcopyiii_clkena is attribute VITAL_LEVEL0 of vital_clkena : architecture is TRUE; component hardcopyiii_and2 generic( TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; InstancePath: STRING := "*"; tpd_IN1_Y : VitalDelayType01 := DefPropDelay01; tpd_IN2_Y : VitalDelayType01 := DefPropDelay01; tipd_IN1 : VitalDelayType01 := DefPropDelay01; tipd_IN2 : VitalDelayType01 := DefPropDelay01); port( Y : out STD_LOGIC; IN1 : in STD_LOGIC; IN2 : in STD_LOGIC); end component; component hardcopyiii_ena_reg generic ( TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : STRING := "*"; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tipd_d : VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01 ); PORT ( clk : in std_logic; ena : in std_logic := '1'; d : in std_logic; clrn : in std_logic := '1'; prn : in std_logic := '1'; q : out std_logic ); end component; signal inclk_ipd : std_logic; signal inclk_inv : std_logic; signal ena_ipd : std_logic; signal cereg_clr : std_logic; signal cereg1_out : std_logic; signal cereg2_out : std_logic; signal ena_out : std_logic; signal vcc : std_logic := '1'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (ena_ipd, ena, tipd_ena); VitalWireDelay (inclk_ipd, inclk, tipd_inclk); end block; inclk_inv <= NOT inclk_ipd; extena_reg1 : hardcopyiii_ena_reg port map ( clk => inclk_inv, ena => vcc, d => ena_ipd, clrn => vcc, prn => devpor, q => cereg1_out ); extena_reg2 : hardcopyiii_ena_reg port map ( clk => inclk_inv, ena => vcc, d => cereg1_out, clrn => vcc, prn => devpor, q => cereg2_out ); ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out; outclk_and : hardcopyiii_and2 port map ( IN1 => inclk_ipd, IN2 => ena_out, Y => outclk ); enaout_and : hardcopyiii_and2 port map ( IN1 => vcc, IN2 => ena_out, Y => enaout ); end vital_clkena; ---------------------------------------------------------------------------- -- Entity Name : hardcopyiii_hram_pulse_generator -- Description : Generate pulse to initiate memory read/write operations ---------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; USE work.hardcopyiii_atom_pack.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; ENTITY hardcopyiii_hram_pulse_generator IS GENERIC ( tipd_clk : VitalDelayType01 := (1 ps,1 ps); tipd_ena : VitalDelayType01 := DefPropDelay01; tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01 ); PORT ( clk,ena : IN STD_LOGIC; pulse,cycle : OUT STD_LOGIC ); ATTRIBUTE VITAL_Level0 OF hardcopyiii_hram_pulse_generator:ENTITY IS TRUE; END hardcopyiii_hram_pulse_generator; ARCHITECTURE pgen_arch OF hardcopyiii_hram_pulse_generator IS SIGNAL clk_ipd,ena_ipd : STD_LOGIC; SIGNAL state : STD_LOGIC; ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE; BEGIN WireDelay : BLOCK BEGIN VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (ena_ipd, ena, tipd_ena); END BLOCK; PROCESS (clk_ipd,state) BEGIN IF (state = '1' AND state'EVENT) THEN state <= '0'; ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN state <= '1'; END IF; END PROCESS; PathDelay : PROCESS VARIABLE pulse_VitalGlitchData : VitalGlitchDataType; BEGIN WAIT UNTIL state'EVENT; VitalPathDelay01 ( OutSignal => pulse, OutSignalName => "pulse", OutTemp => state, Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)), GlitchData => pulse_VitalGlitchData, Mode => DefGlitchMode, XOn => DefXOnChecks, MsgOn => DefMsgOnChecks ); END PROCESS; cycle <= clk_ipd; END pgen_arch; ---------------------------------------------------------------------------- -- Entity Name : hardcopyiii_hram -- Description : HRAM VHDL Simulation Model ---------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; USE work.hardcopyiii_atom_pack.all; USE work.hardcopyiii_hram_pulse_generator; USE work.hardcopyiii_ram_register; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; ENTITY hardcopyiii_hram IS GENERIC ( -- generic control parameters -- MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; tipd_ena0 : VitalDelayType01 := DefpropDelay01; tipd_clk1 : VitalDelayType01 := DefpropDelay01; tipd_devclrn : VitalDelayType01 := DefpropDelay01; tipd_clr0 : VitalDelayType01 := DefpropDelay01; tipd_clk0 : VitalDelayType01 := DefpropDelay01; tipd_portabyteenamasks :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); tipd_portadatain :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01); tipd_clr1 : VitalDelayType01 := DefpropDelay01; tipd_devpor : VitalDelayType01 := DefpropDelay01; tipd_ena1 : VitalDelayType01 := DefpropDelay01; tipd_ena2 : VitalDelayType01 := DefpropDelay01; tipd_portaaddr :VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01); tipd_portbaddr :VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01); tipd_ena3 : VitalDelayType01 := DefpropDelay01; tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01; -- -------- GLOBAL PARAMETERS --------- logical_ram_name : STRING := "hram"; logical_ram_depth : INTEGER := 0; logical_ram_width : INTEGER := 0; first_address : INTEGER := 0; last_address : INTEGER := 0; first_bit_number : INTEGER := 0; init_file : STRING := "NONE"; data_width : INTEGER := 20; address_width : INTEGER := 6; byte_enable_mask_width : INTEGER := 1; byte_size : INTEGER := 1; port_b_address_clock : STRING := "none"; port_b_address_clear : STRING := "none"; port_b_data_out_clock : STRING := "none"; port_b_data_out_clear : STRING := "none"; lpm_type : STRING := "hardcopyiii_hram"; lpm_hint : STRING := "true"; mem_init0 : BIT_VECTOR := X"0"; mixed_port_feed_through_mode : STRING := "dont_care" ); PORT ( -- -------- PORT DECLARATIONS --------- portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (others => '0'); portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0'); portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (others => '1'); portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0'); clk0 : IN STD_LOGIC := '0'; clk1 : IN STD_LOGIC := '0'; ena0 : IN STD_LOGIC := '1'; ena1 : IN STD_LOGIC := '1'; ena2 : IN STD_LOGIC := '1'; ena3 : IN STD_LOGIC := '1'; clr0 : IN STD_LOGIC := '0'; clr1 : IN STD_LOGIC := '0'; devclrn : IN STD_LOGIC := '1'; devpor : IN STD_LOGIC := '1'; portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) ); END hardcopyiii_hram; ARCHITECTURE trans OF hardcopyiii_hram IS CONSTANT port_byte_size : INTEGER := (data_width / byte_enable_mask_width) + (data_width rem byte_enable_mask_width); CONSTANT num_rows : INTEGER := 2**address_width; CONSTANT num_cols : INTEGER := 1; signal ena0_ipd :STD_LOGIC; signal clk1_ipd :STD_LOGIC; signal devclrn_ipd :STD_LOGIC; signal clr0_ipd :STD_LOGIC; signal clk0_ipd :STD_LOGIC; signal portabyteenamasks_ipd :STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0); signal portadatain_ipd :STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); signal clr1_ipd :STD_LOGIC; signal devpor_ipd :STD_LOGIC; signal ena1_ipd :STD_LOGIC; signal ena2_ipd :STD_LOGIC; signal portaaddr_ipd :STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0); signal portbaddr_ipd :STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0); signal ena3_ipd :STD_LOGIC; COMPONENT hardcopyiii_hram_pulse_generator PORT ( clk : IN STD_LOGIC; ena : IN STD_LOGIC; pulse : OUT STD_LOGIC; cycle : OUT STD_LOGIC ); END COMPONENT; COMPONENT hardcopyiii_ram_register GENERIC ( preset : STD_LOGIC := '0'; width : integer := 1 ); PORT ( d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0); clk : IN STD_LOGIC; aclr : IN STD_LOGIC; devclrn : IN STD_LOGIC; devpor : IN STD_LOGIC; ena : IN STD_LOGIC; stall : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0); aclrout : OUT STD_LOGIC ); END COMPONENT; TYPE type_xhdl0 IS ARRAY (num_rows - 1 DOWNTO 0) OF STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); SIGNAL ena0_reg : STD_LOGIC := '0' ; SIGNAL ena1_reg : STD_LOGIC := '0' ; SIGNAL ena2_reg : STD_LOGIC := '0' ; SIGNAL ena3_reg : STD_LOGIC := '0' ; SIGNAL viol_notifier : STD_LOGIC; SIGNAL reset : STD_LOGIC; -- -------- INTERNAL signals --------- -- clock / clock enable SIGNAL clk_a_in : STD_LOGIC; SIGNAL clk_b_in : STD_LOGIC; SIGNAL clk_b_out : STD_LOGIC; -- asynch clear SIGNAL addr_b_clr_in : STD_LOGIC; SIGNAL dataout_b_clr_in : STD_LOGIC; SIGNAL dataout_b_clr : STD_LOGIC; SIGNAL addr_b_clr : STD_LOGIC; SIGNAL addr_a_clr : STD_LOGIC; SIGNAL datain_a_clr : STD_LOGIC; SIGNAL byteena_a_clr : STD_LOGIC; -- port A registers SIGNAL addr_a_reg : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0); SIGNAL datain_a_reg : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0); -- port B registers SIGNAL addr_b_reg : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0); SIGNAL dataout_b : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); SIGNAL portbdataout_tmp : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); -- placeholders for read/written data SIGNAL read_data_latch : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); SIGNAL mem_data : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); -- pulses for A/B ports (no read pulse) SIGNAL write_pulse : STD_LOGIC; SIGNAL write_cycle : STD_LOGIC; -- memory core SIGNAL mem : type_xhdl0; -- byte enable SIGNAL mask_vector : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); SIGNAL mask_vector_int : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); -- memory initialization SIGNAL init_mem : BOOLEAN := FALSE; -- port active for read/write SIGNAL active_a : STD_LOGIC; SIGNAL active_a_in : STD_LOGIC; SIGNAL active_write_a : STD_LOGIC; -- X-HDL generated signals SIGNAL xhdl1 : STD_LOGIC; BEGIN ------------------------ -- Wire Delay Block -- ------------------------ WireDelay : BLOCK BEGIN VitalWireDelay (clk1_ipd,clk1, tipd_clk1); VitalWireDelay (ena0_ipd,ena0, tipd_ena0); bits_portadatain : FOR i in portadatain'RANGE GENERATE VitalWireDelay (portadatain_ipd(i),portadatain(i), tipd_portadatain(i)); END GENERATE; bits_portabyteenamasks : FOR i in portabyteenamasks'RANGE GENERATE VitalWireDelay (portabyteenamasks_ipd(i),portabyteenamasks(i), tipd_portabyteenamasks(i)); END GENERATE; VitalWireDelay (clk0_ipd,clk0, tipd_clk0); VitalWireDelay (clr0_ipd,clr0, tipd_clr0); VitalWireDelay (devclrn_ipd,devclrn, tipd_devclrn); VitalWireDelay (clr1_ipd,clr1, tipd_clr1); VitalWireDelay (ena1_ipd,ena1, tipd_ena1); VitalWireDelay (devpor_ipd,devpor, tipd_devpor); bits_portaaddr : FOR i in portaaddr'RANGE GENERATE VitalWireDelay (portaaddr_ipd(i),portaaddr(i), tipd_portaaddr(i)); END GENERATE; VitalWireDelay (ena2_ipd,ena2, tipd_ena2); bits_portbaddr : FOR i in portbaddr'RANGE GENERATE VitalWireDelay (portbaddr_ipd(i),portbaddr(i), tipd_portbaddr(i)); END GENERATE; VitalWireDelay (ena3_ipd,ena3, tipd_ena3); END BLOCK; ------------------------ -- Functionality Section -- ------------------------ reset <= ena0_reg; init_mem <= TRUE; clk_a_in <= clk0_ipd; clk_b_in <= clk0_ipd WHEN (port_b_address_clock = ("clock0")) ELSE clk1_ipd WHEN (port_b_address_clock = ("clock1")) ELSE '0'; clk_b_out <= clk1_ipd WHEN (port_b_data_out_clock = ("clock1")) ELSE '0'; PROCESS (clk_a_in) BEGIN IF (clk_a_in'EVENT AND clk_a_in = '1') THEN ena0_reg <= ena0_ipd; END IF; END PROCESS; PROCESS (clk_b_out) BEGIN IF (clk_b_out'EVENT AND clk_b_out = '1') THEN ena1_reg <= ena1_ipd; END IF; END PROCESS; PROCESS (clk_a_in) BEGIN IF (clk_a_in'EVENT AND clk_a_in = '1') THEN ena2_reg <= ena2_ipd; END IF; END PROCESS; PROCESS (clk_b_in) BEGIN IF (clk_b_in'EVENT AND clk_b_in = '1') THEN ena3_reg <= ena3_ipd; END IF; END PROCESS; addr_b_clr_in <= clr0_ipd WHEN (port_b_address_clear = ("clear0")) ELSE '0'; dataout_b_clr_in <= clr1_ipd WHEN (port_b_data_out_clear = ("clear1")) ELSE '0'; -- Port A registers -- address register addr_a_register : hardcopyiii_ram_register GENERIC MAP ( width => address_width ) PORT MAP ( d => portaaddr_ipd, clk => clk_a_in, aclr => '0', devclrn =>devclrn_ipd, devpor =>devpor_ipd, ena => ena2, stall => '0', q => addr_a_reg, aclrout => addr_a_clr ); -- data register datain_a_register : hardcopyiii_ram_register GENERIC MAP ( width => data_width ) PORT MAP ( d => portadatain_ipd, clk => clk_a_in, aclr => '0', devclrn =>devclrn_ipd, devpor =>devpor_ipd, ena => ena2, stall => '0', q => datain_a_reg, aclrout => datain_a_clr ); -- byte enable register byteena_a_register : hardcopyiii_ram_register GENERIC MAP ( width => byte_enable_mask_width ) PORT MAP ( d => portabyteenamasks_ipd, clk => clk_a_in, aclr => '0', devclrn =>devclrn_ipd, devpor =>devpor_ipd, ena => ena2, stall => '0', q => byteena_a_reg, aclrout => byteena_a_clr ); -- Port B registers -- address register addr_b_register : hardcopyiii_ram_register GENERIC MAP ( width => address_width ) PORT MAP ( d => portbaddr_ipd, clk => clk_b_in, aclr => addr_b_clr_in, devclrn =>devclrn_ipd, devpor =>devpor_ipd, ena => ena3, stall => '0', q => addr_b_reg, aclrout => addr_b_clr ); -- data register data_b_register : hardcopyiii_ram_register GENERIC MAP ( width => data_width ) PORT MAP ( d => dataout_b, clk => clk_b_out, aclr => dataout_b_clr_in, devclrn =>devclrn_ipd, devpor =>devpor_ipd, ena => ena1, stall => '0', q => dataout_b_reg, aclrout => dataout_b_clr ); -- Write pulse generation xhdl1 <= NOT(clk_a_in); wpgen_a : hardcopyiii_hram_pulse_generator PORT MAP ( clk => xhdl1, ena => ena0_reg, pulse => write_pulse, cycle => write_cycle ); -- Read pulse generation -- -- none -- -- Create internal masks for byte enable processing PROCESS (byteena_a_reg) BEGIN FOR i IN 0 TO data_width-1 LOOP IF (byteena_a_reg(i / port_byte_size) = '1') THEN mask_vector(i) <= '0'; ELSE mask_vector(i) <= 'X'; END IF; IF (byteena_a_reg(i / port_byte_size) = '0') THEN mask_vector_int(i) <= '0'; ELSE mask_vector_int(i) <= 'X'; END IF; END LOOP; END PROCESS; PROCESS (init_mem, write_pulse) VARIABLE addr_range_init,index : INTEGER; VARIABLE mem_init_std : STD_LOGIC_VECTOR((last_address - first_address + 1)*data_width - 1 DOWNTO 0); VARIABLE mem_init : bit_vector(mem_init0'length - 1 DOWNTO 0); VARIABLE mem_val : type_xhdl0; VARIABLE mem_data_p : STD_LOGIC_VECTOR(data_width-1 downto 0); BEGIN -- powerup output to 0 IF (init_mem'EVENT) THEN -- Initialize output to 0 mem_val := (OTHERS => (OTHERS => '0')); IF (init_file /= "NONE" AND init_file /= "none") THEN addr_range_init := last_address - first_address + 1; mem_init := mem_init0; mem_init_std := to_stdlogicvector(mem_init)((last_address - first_address + 1)*data_width - 1 DOWNTO 0); FOR row IN 0 TO addr_range_init - 1 LOOP index := row * data_width; mem_val(row) := mem_init_std(index + data_width -1 DOWNTO index ); END LOOP; END IF; mem <= mem_val; END IF; -- Write stage 1 : X to memory -- Write stage 2 : actual data to memory IF (write_pulse'EVENT) THEN IF (write_pulse = '1') THEN mem_data_p := mem(bin2int(addr_a_reg)); FOR i IN 0 TO data_width - 1 LOOP mem_data_p(i) := mem_data_p(i) XOR mask_vector_int(i); END LOOP; mem(bin2int(addr_a_reg)) <= mem_data_p; ELSIF (write_pulse = '0') THEN mem_data_p := mem(bin2int(addr_a_reg)); FOR i IN 0 TO data_width - 1 LOOP IF (mask_vector(i) = '0') THEN mem(bin2int(addr_a_reg))(i) <= datain_a_reg(i); mem_data_p(i) := datain_a_reg(i); ELSIF (mask_vector_int(i) = 'X') THEN mem(bin2int(addr_a_reg))(i) <= 'X'; mem_data_p(i) := 'X'; END IF; END LOOP; END IF; END IF; END PROCESS; -- Read stage : asynchronous continuous read dataout_b <= mem(bin2int(portbaddr_ipd)) WHEN (port_b_address_clock = ("none")) ELSE mem(bin2int(addr_b_reg)); portbdataout_tmp <= dataout_b_reg WHEN (port_b_data_out_clock = ("clock1")) ELSE dataout_b; --portbdataout <= portbdataout_tmp; ------------------------ -- Path Delay Section -- ------------------------ PathDelay_portbdataout : BLOCK BEGIN portbdataout_GEN : FOR i IN portbdataout'RANGE GENERATE PROCESS(portbdataout_tmp) variable portbdataout_VitalGlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => portbdataout(i), OutSignalName => "portbdataout", OutTemp => portbdataout_tmp(i), Paths => ( 0 => (portbaddr_ipd'last_event, tpd_portbaddr_portbdataout, TRUE)), GlitchData => portbdataout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); END PROCESS; END GENERATE; END BLOCK; END trans; --------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_io_ibuf -- -- Description : HARDCOPYIII IO Ibuf VHDL simulation model -- -- --------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_io_ibuf IS GENERIC ( tipd_i : VitalDelayType01 := DefPropDelay01; tipd_ibar : VitalDelayType01 := DefPropDelay01; tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01; tpd_i_o : VitalDelayType01 := DefPropDelay01; tpd_ibar_o : VitalDelayType01 := DefPropDelay01; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; differential_mode : string := "false"; bus_hold : string := "false"; simulate_z_as : string := "Z"; lpm_type : string := "hardcopyiii_io_ibuf" ); PORT ( i : IN std_logic := '0'; ibar : IN std_logic := '0'; dynamicterminationcontrol : IN std_logic := '0'; o : OUT std_logic ); END hardcopyiii_io_ibuf; ARCHITECTURE arch OF hardcopyiii_io_ibuf IS SIGNAL i_ipd : std_logic := '0'; SIGNAL ibar_ipd : std_logic := '0'; SIGNAL o_tmp : std_logic; SIGNAL out_tmp : std_logic; SIGNAL prev_value : std_logic := '0'; BEGIN WireDelay : block begin VitalWireDelay (i_ipd, i, tipd_i); VitalWireDelay (ibar_ipd, ibar, tipd_ibar); end block; PROCESS(i_ipd, ibar_ipd) BEGIN IF (differential_mode = "false") THEN IF (i_ipd = '1') THEN o_tmp <= '1'; prev_value <= '1'; ELSIF (i_ipd = '0') THEN o_tmp <= '0'; prev_value <= '0'; ELSE o_tmp <= i_ipd; END IF; ELSE IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then o_tmp <= '0'; ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then o_tmp <= '1'; ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then o_tmp <= 'X'; ELSE o_tmp <= 'X'; END IF; END IF; END PROCESS; out_tmp <= prev_value when (bus_hold = "true") else 'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else 'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else '1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else '0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else o_tmp; ---------------------- -- Path Delay Section ---------------------- PROCESS( out_tmp) variable output_VitalGlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => o, OutSignalName => "o", OutTemp => out_tmp, Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE), 1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)), GlitchData => output_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); END PROCESS; END arch; --------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_io_obuf -- -- Description : HARDCOPYIII IO Obuf VHDL simulation model -- -- --------------------------------------------------------------------- LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_io_obuf IS GENERIC ( tipd_i : VitalDelayType01 := DefPropDelay01; tipd_oe : VitalDelayType01 := DefPropDelay01; tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01; tipd_seriesterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01); tipd_parallelterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01 ); tpd_i_o : VitalDelayType01 := DefPropDelay01; tpd_oe_o : VitalDelayType01 := DefPropDelay01; tpd_i_obar : VitalDelayType01 := DefPropDelay01; tpd_oe_obar : VitalDelayType01 := DefPropDelay01; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; open_drain_output : string := "false"; shift_series_termination_control : string := "false"; sim_dynamic_termination_control_is_connected : string := "false"; bus_hold : string := "false"; lpm_type : string := "hardcopyiii_io_obuf" ); PORT ( i : IN std_logic := '0'; oe : IN std_logic := '1'; dynamicterminationcontrol : IN std_logic := '0'; seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0'); parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0'); devoe : IN std_logic := '1'; o : OUT std_logic; obar : OUT std_logic ); END hardcopyiii_io_obuf; ARCHITECTURE arch OF hardcopyiii_io_obuf IS --INTERNAL Signals SIGNAL i_ipd : std_logic := '0'; SIGNAL oe_ipd : std_logic := '0'; SIGNAL dynamicterminationcontrol_ipd : std_logic := '0'; SIGNAL out_tmp : std_logic := 'Z'; SIGNAL out_tmp_bar : std_logic; SIGNAL prev_value : std_logic := '0'; SIGNAL o_tmp : std_logic; SIGNAL obar_tmp : std_logic; SIGNAL o_tmp1 : std_logic; SIGNAL obar_tmp1 : std_logic; SIGNAL seriesterminationcontrol_ipd : std_logic_vector(13 DOWNTO 0) := (others => '0'); SIGNAL parallelterminationcontrol_ipd : std_logic_vector(13 DOWNTO 0) := (others => '0'); BEGIN WireDelay : block begin VitalWireDelay (i_ipd, i, tipd_i); VitalWireDelay (oe_ipd, oe, tipd_oe); VitalWireDelay (dynamicterminationcontrol_ipd, dynamicterminationcontrol, tipd_dynamicterminationcontrol); g1 :for i in seriesterminationcontrol'range generate VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i)); end generate; g2 :for i in parallelterminationcontrol'range generate VitalWireDelay (parallelterminationcontrol_ipd(i), parallelterminationcontrol(i), tipd_parallelterminationcontrol(i)); end generate; end block; PROCESS( i_ipd, oe_ipd) BEGIN IF (oe_ipd = '1') THEN IF (open_drain_output = "true") THEN IF (i_ipd = '0') THEN out_tmp <= '0'; out_tmp_bar <= '1'; prev_value <= '0'; ELSE out_tmp <= 'Z'; out_tmp_bar <= 'Z'; END IF; ELSE IF (i_ipd = '0') THEN out_tmp <= '0'; out_tmp_bar <= '1'; prev_value <= '0'; ELSE IF (i_ipd = '1') THEN out_tmp <= '1'; out_tmp_bar <= '0'; prev_value <= '1'; ELSE out_tmp <= i_ipd; out_tmp_bar <= i_ipd; END IF; END IF; END IF; ELSE IF (oe_ipd = '0') THEN out_tmp <= 'Z'; out_tmp_bar <= 'Z'; ELSE out_tmp <= 'X'; out_tmp_bar <= 'X'; END IF; END IF; END PROCESS; o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp; obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar; o_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1') and (sim_dynamic_termination_control_is_connected = "true")) else o_tmp1 WHEN (devoe = '1') ELSE 'Z'; obar_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1')and (sim_dynamic_termination_control_is_connected = "true")) else obar_tmp1 WHEN (devoe = '1') ELSE 'Z'; --------------------- -- Path Delay Section ---------------------- PROCESS( o_tmp,obar_tmp) variable o_VitalGlitchData : VitalGlitchDataType; variable obar_VitalGlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => o, OutSignalName => "o", OutTemp => o_tmp, Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE), 1 => (oe_ipd'last_event, tpd_oe_o, TRUE)), GlitchData => o_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => obar, OutSignalName => "obar", OutTemp => obar_tmp, Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE), 1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)), GlitchData => obar_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); END PROCESS; END arch; ----------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_ddio_in -- -- Description : HARDCOPYIII DDIO_IN VHDL simulation model -- -- --------------------------------------------------------------------- LIBRARY IEEE; LIBRARY altera; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use altera.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_ddio_in IS generic( tipd_datain : VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_clkn : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; tipd_areset : VitalDelayType01 := DefPropDelay01; tipd_sreset : VitalDelayType01 := DefPropDelay01; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; power_up : string := "low"; async_mode : string := "none"; sync_mode : string := "none"; use_clkn : string := "false"; lpm_type : string := "hardcopyiii_ddio_in" ); PORT ( datain : IN std_logic := '0'; clk : IN std_logic := '0'; clkn : IN std_logic := '0'; ena : IN std_logic := '1'; areset : IN std_logic := '0'; sreset : IN std_logic := '0'; regoutlo : OUT std_logic; regouthi : OUT std_logic; dfflo : OUT std_logic; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1' ); END hardcopyiii_ddio_in; ARCHITECTURE arch OF hardcopyiii_ddio_in IS component dffeas generic ( power_up : string := "DONT_CARE"; is_wysiwyg : string := "false"; x_on_violation : string := "on"; lpm_type : string := "DFFEAS"; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01; tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_asdata_q: VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_d : VitalDelayType01 := DefPropDelay01; tipd_asdata : VitalDelayType01 := DefPropDelay01; tipd_sclr : VitalDelayType01 := DefPropDelay01; tipd_sload : VitalDelayType01 := DefPropDelay01; tipd_clrn : VitalDelayType01 := DefPropDelay01; tipd_prn : VitalDelayType01 := DefPropDelay01; tipd_aload : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; InstancePath: STRING := "*" ); port ( d : in std_logic := '0'; clk : in std_logic := '0'; ena : in std_logic := '1'; clrn : in std_logic := '1'; prn : in std_logic := '1'; aload : in std_logic := '0'; asdata : in std_logic := '1'; sclr : in std_logic := '0'; sload : in std_logic := '0'; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; q : out std_logic ); end component; --Internal Signals SIGNAL datain_ipd : std_logic := '0'; SIGNAL clk_ipd : std_logic := '0'; SIGNAL clkn_ipd : std_logic := '0'; SIGNAL ena_ipd : std_logic := '0'; SIGNAL areset_ipd : std_logic := '0'; SIGNAL sreset_ipd : std_logic := '0'; SIGNAL ddioreg_aclr : std_logic; SIGNAL ddioreg_prn : std_logic; SIGNAL ddioreg_adatasdata : std_logic; SIGNAL ddioreg_sclr : std_logic; SIGNAL ddioreg_sload : std_logic; SIGNAL ddioreg_clk : std_logic; SIGNAL dfflo_tmp : std_logic; SIGNAL regout_tmp_hi : std_logic; SIGNAL regout_tmp_lo : std_logic; SIGNAL regouthi_tmp : std_logic; SIGNAL regoutlo_tmp : std_logic; BEGIN WireDelay : block begin VitalWireDelay (datain_ipd, datain, tipd_datain); VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (clkn_ipd, clkn, tipd_clkn); VitalWireDelay (ena_ipd, ena, tipd_ena); VitalWireDelay (areset_ipd, areset, tipd_areset); VitalWireDelay (sreset_ipd, sreset, tipd_sreset); end block; ddioreg_clk <= NOT clk_ipd WHEN (use_clkn = "false") ELSE clkn_ipd; --Decode the control values for the DDIO registers PROCESS BEGIN WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT; IF (async_mode = "clear") THEN ddioreg_aclr <= NOT areset_ipd; ddioreg_prn <= '1'; ELSIF (async_mode = "preset") THEN ddioreg_aclr <= '1'; ddioreg_prn <= NOT areset_ipd; ELSE ddioreg_aclr <= '1'; ddioreg_prn <= '1'; END IF; IF (sync_mode = "clear") THEN ddioreg_adatasdata <= '0'; ddioreg_sclr <= sreset_ipd; ddioreg_sload <= '0'; ELSIF (sync_mode = "preset") THEN ddioreg_adatasdata <= '1'; ddioreg_sclr <= '0'; ddioreg_sload <= sreset_ipd; ELSE ddioreg_adatasdata <= '0'; ddioreg_sclr <= '0'; ddioreg_sload <= '0'; END IF; END PROCESS; --DDIO High Register ddioreg_hi : dffeas GENERIC MAP ( power_up => power_up ) PORT MAP ( d => datain_ipd, clk => clk_ipd, clrn => ddioreg_aclr, prn => ddioreg_prn, sclr => ddioreg_sclr, sload => ddioreg_sload, asdata => ddioreg_adatasdata, ena => ena_ipd, q => regout_tmp_hi, devpor => devpor, devclrn => devclrn ); --DDIO Low Register ddioreg_lo : dffeas GENERIC MAP ( power_up => power_up ) PORT MAP ( d => datain_ipd, clk => ddioreg_clk, clrn => ddioreg_aclr, prn => ddioreg_prn, sclr => ddioreg_sclr, sload => ddioreg_sload, asdata => ddioreg_adatasdata, ena => ena_ipd, q => dfflo_tmp, devpor => devpor, devclrn => devclrn ); ddioreg_lo1 : dffeas GENERIC MAP ( power_up => power_up ) PORT MAP ( d => dfflo_tmp, clk => clk_ipd, clrn => ddioreg_aclr, prn => ddioreg_prn, sclr => ddioreg_sclr, sload => ddioreg_sload, asdata => ddioreg_adatasdata, ena => ena_ipd, q => regout_tmp_lo, devpor => devpor, devclrn => devclrn ); regouthi <= regout_tmp_hi ; regoutlo <= regout_tmp_lo ; dfflo <= dfflo_tmp ; END arch; --------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_ddio_oe -- -- Description : HARDCOPYIII DDIO_OE VHDL simulation model -- -- --------------------------------------------------------------------- LIBRARY IEEE; LIBRARY altera; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use altera.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_ddio_oe IS generic( tipd_oe : VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; tipd_areset : VitalDelayType01 := DefPropDelay01; tipd_sreset : VitalDelayType01 := DefPropDelay01; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; power_up : string := "low"; async_mode : string := "none"; sync_mode : string := "none"; lpm_type : string := "hardcopyiii_ddio_oe" ); PORT ( oe : IN std_logic := '1'; clk : IN std_logic := '0'; ena : IN std_logic := '1'; areset : IN std_logic := '0'; sreset : IN std_logic := '0'; dataout : OUT std_logic; dfflo : OUT std_logic; dffhi : OUT std_logic; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1' ); END hardcopyiii_ddio_oe; ARCHITECTURE arch OF hardcopyiii_ddio_oe IS component hardcopyiii_mux21 generic( TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; InstancePath: STRING := "*"; tpd_A_MO : VitalDelayType01 := DefPropDelay01; tpd_B_MO : VitalDelayType01 := DefPropDelay01; tpd_S_MO : VitalDelayType01 := DefPropDelay01; tipd_A : VitalDelayType01 := DefPropDelay01; tipd_B : VitalDelayType01 := DefPropDelay01; tipd_S : VitalDelayType01 := DefPropDelay01 ); port ( A : in std_logic := '0'; B : in std_logic := '0'; S : in std_logic := '0'; MO : out std_logic ); end component; component dffeas generic ( power_up : string := "DONT_CARE"; is_wysiwyg : string := "false"; x_on_violation : string := "on"; lpm_type : string := "DFFEAS"; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01; tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_asdata_q: VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_d : VitalDelayType01 := DefPropDelay01; tipd_asdata : VitalDelayType01 := DefPropDelay01; tipd_sclr : VitalDelayType01 := DefPropDelay01; tipd_sload : VitalDelayType01 := DefPropDelay01; tipd_clrn : VitalDelayType01 := DefPropDelay01; tipd_prn : VitalDelayType01 := DefPropDelay01; tipd_aload : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; InstancePath: STRING := "*" ); port ( d : in std_logic := '0'; clk : in std_logic := '0'; ena : in std_logic := '1'; clrn : in std_logic := '1'; prn : in std_logic := '1'; aload : in std_logic := '0'; asdata : in std_logic := '1'; sclr : in std_logic := '0'; sload : in std_logic := '0'; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; q : out std_logic ); end component; --Internal Signals SIGNAL oe_ipd : std_logic := '0'; SIGNAL clk_ipd : std_logic := '0'; SIGNAL ena_ipd : std_logic := '0'; SIGNAL areset_ipd : std_logic := '0'; SIGNAL sreset_ipd : std_logic := '0'; SIGNAL ddioreg_aclr : std_logic; SIGNAL ddioreg_prn : std_logic; SIGNAL ddioreg_adatasdata : std_logic; SIGNAL ddioreg_sclr : std_logic; SIGNAL ddioreg_sload : std_logic; SIGNAL dfflo_tmp : std_logic; SIGNAL dffhi_tmp : std_logic; signal nclk : std_logic; signal dataout_tmp : std_logic; BEGIN WireDelay : block begin VitalWireDelay (oe_ipd, oe, tipd_oe); VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (ena_ipd, ena, tipd_ena); VitalWireDelay (areset_ipd, areset, tipd_areset); VitalWireDelay (sreset_ipd, sreset, tipd_sreset); end block; nclk <= NOT clk_ipd; PROCESS BEGIN WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT; IF (async_mode = "clear") THEN ddioreg_aclr <= NOT areset_ipd; ddioreg_prn <= '1'; ELSIF (async_mode = "preset") THEN ddioreg_aclr <= '1'; ddioreg_prn <= NOT areset_ipd; ELSE ddioreg_aclr <= '1'; ddioreg_prn <= '1'; END IF; IF (sync_mode = "clear") THEN ddioreg_adatasdata <= '0'; ddioreg_sclr <= sreset_ipd; ddioreg_sload <= '0'; ELSIF (sync_mode = "preset") THEN ddioreg_adatasdata <= '1'; ddioreg_sclr <= '0'; ddioreg_sload <= sreset_ipd; ELSE ddioreg_adatasdata <= '0'; ddioreg_sclr <= '0'; ddioreg_sload <= '0'; END IF; END PROCESS; ddioreg_hi : dffeas GENERIC MAP ( power_up => power_up ) PORT MAP ( d => oe_ipd, clk => clk_ipd, clrn => ddioreg_aclr, prn => ddioreg_prn, sclr => ddioreg_sclr, sload => ddioreg_sload, asdata => ddioreg_adatasdata, ena => ena_ipd, q => dffhi_tmp, devpor => devpor, devclrn => devclrn ); --DDIO Low Register ddioreg_lo : dffeas GENERIC MAP ( power_up => power_up ) PORT MAP ( d => dffhi_tmp, clk => nclk, clrn => ddioreg_aclr, prn => ddioreg_prn, sclr => ddioreg_sclr, sload => ddioreg_sload, asdata => ddioreg_adatasdata, ena => ena_ipd, q => dfflo_tmp, devpor => devpor, devclrn => devclrn ); --registered output or_gate : hardcopyiii_mux21 port map ( A => dffhi_tmp, B => dfflo_tmp, S => dfflo_tmp, MO => dataout ); dfflo <= dfflo_tmp ; dffhi <= dffhi_tmp ; END arch; --------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_ddio_out -- -- Description : HARDCOPYIII DDIO_OUT VHDL simulation model -- -- --------------------------------------------------------------------- LIBRARY IEEE; LIBRARY altera; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use altera.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_ddio_out IS generic( tipd_datainlo : VitalDelayType01 := DefPropDelay01; tipd_datainhi : VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_clkhi : VitalDelayType01 := DefPropDelay01; tipd_clklo : VitalDelayType01 := DefPropDelay01; tipd_muxsel : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; tipd_areset : VitalDelayType01 := DefPropDelay01; tipd_sreset : VitalDelayType01 := DefPropDelay01; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; power_up : string := "low"; async_mode : string := "none"; sync_mode : string := "none"; half_rate_mode : string := "false"; use_new_clocking_model : string := "false"; lpm_type : string := "hardcopyiii_ddio_out" ); PORT ( datainlo : IN std_logic := '0'; datainhi : IN std_logic := '0'; clk : IN std_logic := '0'; clkhi : IN std_logic := '0'; clklo : IN std_logic := '0'; muxsel : IN std_logic := '0'; ena : IN std_logic := '1'; areset : IN std_logic := '0'; sreset : IN std_logic := '0'; dataout : OUT std_logic; dfflo : OUT std_logic; dffhi : OUT std_logic_vector(1 downto 0) ; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1' ); END hardcopyiii_ddio_out; ARCHITECTURE arch OF hardcopyiii_ddio_out IS component hardcopyiii_mux21 generic( TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; InstancePath: STRING := "*"; tpd_A_MO : VitalDelayType01 := DefPropDelay01; tpd_B_MO : VitalDelayType01 := DefPropDelay01; tpd_S_MO : VitalDelayType01 := DefPropDelay01; tipd_A : VitalDelayType01 := DefPropDelay01; tipd_B : VitalDelayType01 := DefPropDelay01; tipd_S : VitalDelayType01 := DefPropDelay01 ); port ( A : in std_logic := '0'; B : in std_logic := '0'; S : in std_logic := '0'; MO : out std_logic ); end component; component dffeas generic ( power_up : string := "DONT_CARE"; is_wysiwyg : string := "false"; x_on_violation : string := "on"; lpm_type : string := "DFFEAS"; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01; tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_asdata_q: VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_d : VitalDelayType01 := DefPropDelay01; tipd_asdata : VitalDelayType01 := DefPropDelay01; tipd_sclr : VitalDelayType01 := DefPropDelay01; tipd_sload : VitalDelayType01 := DefPropDelay01; tipd_clrn : VitalDelayType01 := DefPropDelay01; tipd_prn : VitalDelayType01 := DefPropDelay01; tipd_aload : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; InstancePath: STRING := "*" ); port ( d : in std_logic := '0'; clk : in std_logic := '0'; ena : in std_logic := '1'; clrn : in std_logic := '1'; prn : in std_logic := '1'; aload : in std_logic := '0'; asdata : in std_logic := '1'; sclr : in std_logic := '0'; sload : in std_logic := '0'; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; q : out std_logic ); end component; --Internal Signals SIGNAL datainlo_ipd : std_logic := '0'; SIGNAL datainhi_ipd : std_logic := '0'; SIGNAL clk_ipd : std_logic := '0'; SIGNAL clkhi_ipd : std_logic := '0'; SIGNAL clklo_ipd : std_logic := '0'; SIGNAL muxsel_ipd : std_logic := '0'; SIGNAL ena_ipd : std_logic := '0'; SIGNAL areset_ipd : std_logic := '0'; SIGNAL sreset_ipd : std_logic := '0'; SIGNAL ddioreg_aclr : std_logic; SIGNAL ddioreg_prn : std_logic; SIGNAL ddioreg_adatasdata : std_logic; SIGNAL ddioreg_sclr : std_logic; SIGNAL ddioreg_sload : std_logic; SIGNAL dfflo_tmp : std_logic; SIGNAL dffhi_tmp : std_logic; SIGNAL dataout_tmp : std_logic; Signal mux_sel : std_logic; Signal mux_hi : std_logic; Signal dffhi1_tmp : std_logic; Signal sel_mux_hi_in : std_logic; signal nclk : std_logic; signal clk1 : std_logic; signal clk_hi : std_logic; signal clk_lo : std_logic; signal clk_hr : std_logic; signal muxsel1 : std_logic; signal muxsel2: std_logic; signal clk2 : std_logic; signal muxsel_tmp: std_logic; signal sel_mux_lo_in : std_logic; signal datainlo_tmp : std_logic; signal datainhi_tmp : std_logic; BEGIN WireDelay : block begin VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo); VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi); VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi); VitalWireDelay (clklo_ipd, clklo, tipd_clklo); VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel); VitalWireDelay (ena_ipd, ena, tipd_ena); VitalWireDelay (areset_ipd, areset, tipd_areset); VitalWireDelay (sreset_ipd, sreset, tipd_sreset); end block; nclk <= NOT clk_ipd; PROCESS BEGIN WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT; IF (async_mode = "clear") THEN ddioreg_aclr <= NOT areset_ipd; ddioreg_prn <= '1'; ELSIF (async_mode = "preset") THEN ddioreg_aclr <= '1'; ddioreg_prn <= NOT areset_ipd; ELSE ddioreg_aclr <= '1'; ddioreg_prn <= '1'; END IF; IF (sync_mode = "clear") THEN ddioreg_adatasdata <= '0'; ddioreg_sclr <= sreset_ipd; ddioreg_sload <= '0'; ELSIF (sync_mode = "preset") THEN ddioreg_adatasdata <= '1'; ddioreg_sclr <= '0'; ddioreg_sload <= sreset_ipd; ELSE ddioreg_adatasdata <= '0'; ddioreg_sclr <= '0'; ddioreg_sload <= '0'; END IF; END PROCESS; process(clk_ipd) begin clk1 <= clk_ipd; end process; process(muxsel_ipd) begin muxsel1 <= muxsel_ipd; end process; --DDIO HIGH Register clk_hi <= clkhi_ipd when(use_new_clocking_model = "true") else clk_ipd; datainhi_tmp <= datainhi; ddioreg_hi : dffeas GENERIC MAP ( power_up => power_up ) PORT MAP ( d => datainhi_tmp, clk => clk_hi, clrn => ddioreg_aclr, prn => ddioreg_prn, sclr => ddioreg_sclr, sload => ddioreg_sload, asdata => ddioreg_adatasdata, ena => ena_ipd, q => dffhi_tmp, devpor => devpor, devclrn => devclrn ); --DDIO Low Register clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd; datainlo_tmp <= datainlo; ddioreg_lo : dffeas GENERIC MAP ( power_up => power_up ) PORT MAP ( d => datainlo_tmp, clk => clk_lo, clrn => ddioreg_aclr, prn => ddioreg_prn, sclr => ddioreg_sclr, sload => ddioreg_sload, asdata => ddioreg_adatasdata, ena => ena_ipd, q => dfflo_tmp, devpor => devpor, devclrn => devclrn ); clk_hr <= NOT clkhi_ipd when(use_new_clocking_model = "true") else NOT clk_ipd; ddioreg_hi1 : dffeas GENERIC MAP ( power_up => power_up ) PORT MAP ( d => dffhi_tmp, clk => clk_hr, clrn => ddioreg_aclr, prn => ddioreg_prn, sclr => ddioreg_sclr, sload => ddioreg_sload, asdata => ddioreg_adatasdata, ena => ena_ipd, q => dffhi1_tmp, devpor => devpor, devclrn => devclrn ); muxsel2 <= muxsel1; clk2 <= clk1; mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2; muxsel_tmp <= mux_sel; sel_mux_lo_in <= dfflo_tmp; sel_mux_hi_in <= dffhi1_tmp when(half_rate_mode = "true") else dffhi_tmp; sel_mux : hardcopyiii_mux21 port map ( A => sel_mux_lo_in, B => sel_mux_hi_in, S => muxsel_tmp, MO => dataout ); dfflo <= dfflo_tmp; dffhi(0) <= dffhi_tmp; dffhi(1) <= dffhi1_tmp; END arch; -- -------------------------------------------------------------------- -- Module Name: hardcopyiii_rt_sm -- Description: Parallel Termination State Machine -- -------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; ENTITY hardcopyiii_rt_sm IS PORT ( rup : IN std_logic; rdn : IN std_logic; clk : IN std_logic; clken : IN std_logic; clr : IN std_logic; rtena : IN std_logic; rscaldone : IN std_logic; rtoffsetp : OUT std_logic_vector(3 DOWNTO 0); rtoffsetn : OUT std_logic_vector(3 DOWNTO 0); caldone : OUT std_logic; sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0); sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0)); END hardcopyiii_rt_sm; ARCHITECTURE hardcopyiii_rt_sm_rtl OF hardcopyiii_rt_sm IS CONSTANT HARDCOPYIII_RTOCT_WAIT : std_logic_vector(4 DOWNTO 0) := "00000"; CONSTANT RUP_VREF_M_RDN_VER_M : std_logic_vector(4 DOWNTO 0) := "00001"; CONSTANT RUP_VREF_L_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00010"; CONSTANT RUP_VREF_H_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00011"; CONSTANT RUP_VREF_L_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00100"; CONSTANT RUP_VREF_H_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00101"; CONSTANT HARDCOPYIII_RTOCT_INC_PN : std_logic_vector(4 DOWNTO 0) := "01000"; CONSTANT HARDCOPYIII_RTOCT_DEC_PN : std_logic_vector(4 DOWNTO 0) := "01001"; CONSTANT HARDCOPYIII_RTOCT_INC_P : std_logic_vector(4 DOWNTO 0) := "01010"; CONSTANT HARDCOPYIII_RTOCT_DEC_P : std_logic_vector(4 DOWNTO 0) := "01011"; CONSTANT HARDCOPYIII_RTOCT_INC_N : std_logic_vector(4 DOWNTO 0) := "01100"; CONSTANT HARDCOPYIII_RTOCT_DEC_N : std_logic_vector(4 DOWNTO 0) := "01101"; CONSTANT HARDCOPYIII_RTOCT_SWITCH_REG: std_logic_vector(4 DOWNTO 0) := "10001"; CONSTANT HARDCOPYIII_RTOCT_DONE : std_logic_vector(4 DOWNTO 0) := "11111"; -- interface SIGNAL nclr : std_logic := '1'; -- for synthesis SIGNAL rtcalclk : std_logic; SIGNAL caldone_sig : std_logic := '0'; -- sm SIGNAL current_state : std_logic_vector(4 DOWNTO 0) := "00000"; SIGNAL next_state : std_logic_vector(4 DOWNTO 0) := "00000"; SIGNAL sel_rup_vref_h_d : std_logic := '0'; SIGNAL sel_rup_vref_h : std_logic := '0'; SIGNAL sel_rup_vref_m_d : std_logic := '1'; SIGNAL sel_rup_vref_m : std_logic := '1'; SIGNAL sel_rup_vref_l_d : std_logic := '0'; SIGNAL sel_rup_vref_l : std_logic := '0'; SIGNAL sel_rdn_vref_h_d : std_logic := '0'; SIGNAL sel_rdn_vref_h : std_logic := '0'; SIGNAL sel_rdn_vref_m_d : std_logic := '1'; SIGNAL sel_rdn_vref_m : std_logic := '1'; SIGNAL sel_rdn_vref_l_d : std_logic := '0'; SIGNAL sel_rdn_vref_l : std_logic := '0'; SIGNAL switch_region_d : std_logic := '0'; SIGNAL switch_region : std_logic := '0'; SIGNAL cmpup : std_logic := '0'; SIGNAL cmpdn : std_logic := '0'; SIGNAL rt_sm_done_d : std_logic := '0'; SIGNAL rt_sm_done : std_logic := '0'; -- cnt SIGNAL p_cnt_d : std_logic_vector(2 DOWNTO 0) := "000"; SIGNAL p_cnt : std_logic_vector(2 DOWNTO 0) := "000"; SIGNAL n_cnt_d : std_logic_vector(2 DOWNTO 0) := "000"; SIGNAL n_cnt : std_logic_vector(2 DOWNTO 0) := "000"; SIGNAL p_cnt_sub_d : std_logic := '0'; SIGNAL p_cnt_sub : std_logic := '0'; SIGNAL n_cnt_sub_d : std_logic := '0'; SIGNAL n_cnt_sub : std_logic := '0'; BEGIN -- primary output - MSB is sign bit rtoffsetp <= p_cnt_sub & p_cnt ; rtoffsetn <= n_cnt_sub & n_cnt ; caldone <= caldone_sig; caldone_sig <= rt_sm_done WHEN (rtena = '1') ELSE '1'; sel_rup_vref <= sel_rup_vref_h & sel_rup_vref_m & sel_rup_vref_l ; sel_rdn_vref <= sel_rdn_vref_h & sel_rdn_vref_m & sel_rdn_vref_l ; -- input interface nclr <= NOT clr ; rtcalclk <= ((rscaldone AND clken) AND (NOT caldone_sig)) AND clk ; -- latch registers - rising on everything except cmpup and cmpdn -- cmpup/dn PROCESS BEGIN WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '0') OR (nclr'EVENT AND nclr = '0'); IF (nclr = '0') THEN cmpup <= '0'; cmpdn <= '0'; ELSE cmpup <= rup; cmpdn <= rdn; END IF; END PROCESS; -- other regisers PROCESS BEGIN WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '1') OR (clr'EVENT AND clr = '1'); IF (clr = '1') THEN current_state <= HARDCOPYIII_RTOCT_WAIT; switch_region <= '0'; rt_sm_done <= '0'; p_cnt <= "000"; p_cnt_sub <= '0'; n_cnt <= "000"; n_cnt_sub <= '0'; sel_rup_vref_h <= '0'; sel_rup_vref_m <= '1'; sel_rup_vref_l <= '0'; sel_rdn_vref_h <= '0'; sel_rdn_vref_m <= '1'; sel_rdn_vref_l <= '0'; ELSE current_state <= next_state; switch_region <= switch_region_d; rt_sm_done <= rt_sm_done_d; p_cnt <= p_cnt_d; p_cnt_sub <= p_cnt_sub_d; n_cnt <= n_cnt_d; n_cnt_sub <= n_cnt_sub_d; sel_rup_vref_h <= sel_rup_vref_h_d; sel_rup_vref_m <= sel_rup_vref_m_d; sel_rup_vref_l <= sel_rup_vref_l_d; sel_rdn_vref_h <= sel_rdn_vref_h_d; sel_rdn_vref_m <= sel_rdn_vref_m_d; sel_rdn_vref_l <= sel_rdn_vref_l_d; END IF; END PROCESS; -- state machine PROCESS(current_state, rtena, cmpup, cmpdn, p_cnt, n_cnt, switch_region) variable p_cnt_d_var, n_cnt_d_var : std_logic_vector(2 DOWNTO 0); variable p_cnt_sub_d_var, n_cnt_sub_d_var : std_logic; BEGIN p_cnt_d_var := p_cnt; n_cnt_d_var := n_cnt; p_cnt_sub_d_var := '0'; n_cnt_sub_d_var := '0'; CASE current_state IS WHEN HARDCOPYIII_RTOCT_WAIT => IF (rtena = '0') THEN next_state <= HARDCOPYIII_RTOCT_WAIT; ELSE next_state <= RUP_VREF_M_RDN_VER_M; sel_rup_vref_h_d <= '0'; sel_rup_vref_m_d <= '1'; sel_rup_vref_l_d <= '0'; sel_rdn_vref_h_d <= '0'; sel_rdn_vref_m_d <= '1'; sel_rdn_vref_l_d <= '0'; END IF; WHEN RUP_VREF_M_RDN_VER_M => IF (cmpup = '0' AND cmpdn = '0') THEN next_state <= RUP_VREF_L_RDN_VER_L; sel_rup_vref_h_d <= '0'; sel_rup_vref_m_d <= '0'; sel_rup_vref_l_d <= '1'; sel_rdn_vref_h_d <= '0'; sel_rdn_vref_m_d <= '0'; sel_rdn_vref_l_d <= '1'; ELSE IF (cmpup = '1' AND cmpdn = '1') THEN next_state <= RUP_VREF_H_RDN_VER_H; sel_rup_vref_h_d <= '1'; sel_rup_vref_m_d <= '0'; sel_rup_vref_l_d <= '0'; sel_rdn_vref_h_d <= '1'; sel_rdn_vref_m_d <= '0'; sel_rdn_vref_l_d <= '0'; ELSE IF (cmpup = '1' AND cmpdn = '0') THEN next_state <= HARDCOPYIII_RTOCT_INC_PN; p_cnt_d_var := p_cnt_d_var + 1; p_cnt_sub_d_var := '0'; n_cnt_d_var := n_cnt_d_var + 1; n_cnt_sub_d_var := '0'; ELSE IF (cmpup = '0' AND cmpdn = '1') THEN next_state <= HARDCOPYIII_RTOCT_DEC_PN; p_cnt_d_var := p_cnt_d_var + 1; p_cnt_sub_d_var := '1'; n_cnt_d_var := n_cnt_d_var + 1; n_cnt_sub_d_var := '1'; END IF; END IF; END IF; END IF; WHEN RUP_VREF_L_RDN_VER_L => IF (cmpup = '1' AND cmpdn = '1') THEN next_state <= HARDCOPYIII_RTOCT_DONE; ELSE IF (cmpup = '0') THEN next_state <= HARDCOPYIII_RTOCT_DEC_N; n_cnt_d_var := n_cnt_d_var + 1; n_cnt_sub_d_var := '1'; ELSE IF (cmpup = '1' AND cmpdn = '0') THEN next_state <= HARDCOPYIII_RTOCT_INC_P; p_cnt_d_var := p_cnt_d_var + 1; p_cnt_sub_d_var := '0'; END IF; END IF; END IF; WHEN RUP_VREF_H_RDN_VER_H => IF (cmpup = '0' AND cmpdn = '0') THEN next_state <= HARDCOPYIII_RTOCT_DONE; ELSE IF (cmpup = '1') THEN next_state <= HARDCOPYIII_RTOCT_INC_N; n_cnt_d_var := n_cnt_d_var + 1; n_cnt_sub_d_var := '0'; ELSE IF (cmpup = '0' AND cmpdn = '1') THEN next_state <= HARDCOPYIII_RTOCT_DEC_P; p_cnt_d_var := p_cnt_d_var + 1; p_cnt_sub_d_var := '1'; END IF; END IF; END IF; WHEN RUP_VREF_L_RDN_VER_H => IF (cmpup = '1' AND cmpdn = '0') THEN next_state <= HARDCOPYIII_RTOCT_DONE; ELSE IF (cmpup = '1' AND switch_region = '1') THEN next_state <= HARDCOPYIII_RTOCT_DEC_P; p_cnt_d_var := p_cnt_d_var + 1; p_cnt_sub_d_var := '1'; ELSE IF (cmpup = '0' AND switch_region = '1') THEN next_state <= HARDCOPYIII_RTOCT_DEC_N; n_cnt_d_var := n_cnt_d_var + 1; n_cnt_sub_d_var := '1'; ELSE IF ((switch_region = '0') AND (cmpup = '0' OR cmpdn = '1')) THEN next_state <= HARDCOPYIII_RTOCT_SWITCH_REG; switch_region_d <= '1'; END IF; END IF; END IF; END IF; WHEN RUP_VREF_H_RDN_VER_L => IF (cmpup = '0' AND cmpdn = '1') THEN next_state <= HARDCOPYIII_RTOCT_DONE; ELSE IF (cmpup = '1' AND switch_region = '1') THEN next_state <= HARDCOPYIII_RTOCT_INC_N; n_cnt_d_var := n_cnt_d_var + 1; n_cnt_sub_d_var := '0'; ELSE IF (cmpup = '0' AND switch_region = '1') THEN next_state <= HARDCOPYIII_RTOCT_INC_P; p_cnt_d_var := p_cnt_d_var + 1; p_cnt_sub_d_var := '0'; ELSE IF ((switch_region = '0') AND (cmpup = '1' OR cmpdn = '0')) THEN next_state <= HARDCOPYIII_RTOCT_SWITCH_REG; switch_region_d <= '1'; END IF; END IF; END IF; END IF; WHEN HARDCOPYIII_RTOCT_INC_PN => IF (cmpup = '1' AND cmpdn = '0') THEN next_state <= HARDCOPYIII_RTOCT_INC_PN; p_cnt_d_var := p_cnt_d_var + 1; p_cnt_sub_d_var := '0'; n_cnt_d_var := n_cnt_d_var + 1; n_cnt_sub_d_var := '0'; ELSE IF (cmpup = '0' AND cmpdn = '0') THEN next_state <= RUP_VREF_L_RDN_VER_L; sel_rup_vref_h_d <= '0'; sel_rup_vref_m_d <= '0'; sel_rup_vref_l_d <= '1'; sel_rdn_vref_h_d <= '0'; sel_rdn_vref_m_d <= '0'; sel_rdn_vref_l_d <= '1'; ELSE IF (cmpup = '1' AND cmpdn = '1') THEN next_state <= RUP_VREF_H_RDN_VER_H; sel_rup_vref_h_d <= '1'; sel_rup_vref_m_d <= '0'; sel_rup_vref_l_d <= '0'; sel_rdn_vref_h_d <= '1'; sel_rdn_vref_m_d <= '0'; sel_rdn_vref_l_d <= '0'; ELSE IF (cmpup = '0' AND cmpdn = '1') THEN next_state <= RUP_VREF_L_RDN_VER_H; sel_rup_vref_h_d <= '0'; sel_rup_vref_m_d <= '0'; sel_rup_vref_l_d <= '1'; sel_rdn_vref_h_d <= '1'; sel_rdn_vref_m_d <= '0'; sel_rdn_vref_l_d <= '0'; END IF; END IF; END IF; END IF; WHEN HARDCOPYIII_RTOCT_DEC_PN => IF (cmpup = '0' AND cmpdn = '1') THEN next_state <= HARDCOPYIII_RTOCT_DEC_PN; p_cnt_d_var := p_cnt_d_var + 1; p_cnt_sub_d_var := '1'; n_cnt_d_var := n_cnt_d_var + 1; n_cnt_sub_d_var := '1'; ELSE IF (cmpup = '0' AND cmpdn = '0') THEN next_state <= RUP_VREF_L_RDN_VER_L; sel_rup_vref_h_d <= '0'; sel_rup_vref_m_d <= '0'; sel_rup_vref_l_d <= '1'; sel_rdn_vref_h_d <= '0'; sel_rdn_vref_m_d <= '0'; sel_rdn_vref_l_d <= '1'; ELSE IF (cmpup = '1' AND cmpdn = '1') THEN next_state <= RUP_VREF_H_RDN_VER_H; sel_rup_vref_h_d <= '1'; sel_rup_vref_m_d <= '0'; sel_rup_vref_l_d <= '0'; sel_rdn_vref_h_d <= '1'; sel_rdn_vref_m_d <= '0'; sel_rdn_vref_l_d <= '0'; ELSE IF (cmpup = '1' AND cmpdn = '0') THEN next_state <= RUP_VREF_H_RDN_VER_L; sel_rup_vref_h_d <= '1'; sel_rup_vref_m_d <= '0'; sel_rup_vref_l_d <= '0'; sel_rdn_vref_h_d <= '0'; sel_rdn_vref_m_d <= '0'; sel_rdn_vref_l_d <= '1'; END IF; END IF; END IF; END IF; ----------------- same action begin WHEN HARDCOPYIII_RTOCT_INC_P => IF (switch_region = '1') THEN next_state <= HARDCOPYIII_RTOCT_DONE; ELSE IF (switch_region = '0') THEN next_state <= RUP_VREF_M_RDN_VER_M; sel_rup_vref_h_d <= '0'; sel_rup_vref_m_d <= '1'; sel_rup_vref_l_d <= '0'; sel_rdn_vref_h_d <= '0'; sel_rdn_vref_m_d <= '1'; sel_rdn_vref_l_d <= '0'; END IF; END IF; WHEN HARDCOPYIII_RTOCT_DEC_P => IF (switch_region = '1') THEN next_state <= HARDCOPYIII_RTOCT_DONE; ELSE IF (switch_region = '0') THEN next_state <= RUP_VREF_M_RDN_VER_M; sel_rup_vref_h_d <= '0'; sel_rup_vref_m_d <= '1'; sel_rup_vref_l_d <= '0'; sel_rdn_vref_h_d <= '0'; sel_rdn_vref_m_d <= '1'; sel_rdn_vref_l_d <= '0'; END IF; END IF; WHEN HARDCOPYIII_RTOCT_INC_N => IF (switch_region = '1') THEN next_state <= HARDCOPYIII_RTOCT_DONE; ELSE IF (switch_region = '0') THEN next_state <= RUP_VREF_M_RDN_VER_M; sel_rup_vref_h_d <= '0'; sel_rup_vref_m_d <= '1'; sel_rup_vref_l_d <= '0'; sel_rdn_vref_h_d <= '0'; sel_rdn_vref_m_d <= '1'; sel_rdn_vref_l_d <= '0'; END IF; END IF; WHEN HARDCOPYIII_RTOCT_DEC_N => IF (switch_region = '1') THEN next_state <= HARDCOPYIII_RTOCT_DONE; ELSE IF (switch_region = '0') THEN next_state <= RUP_VREF_M_RDN_VER_M; sel_rup_vref_h_d <= '0'; sel_rup_vref_m_d <= '1'; sel_rup_vref_l_d <= '0'; sel_rdn_vref_h_d <= '0'; sel_rdn_vref_m_d <= '1'; sel_rdn_vref_l_d <= '0'; END IF; END IF; ----------------- same action end WHEN HARDCOPYIII_RTOCT_SWITCH_REG => next_state <= RUP_VREF_M_RDN_VER_M; sel_rup_vref_h_d <= '0'; sel_rup_vref_m_d <= '1'; sel_rup_vref_l_d <= '0'; sel_rdn_vref_h_d <= '0'; sel_rdn_vref_m_d <= '1'; sel_rdn_vref_l_d <= '0'; WHEN HARDCOPYIII_RTOCT_DONE => next_state <= HARDCOPYIII_RTOCT_DONE; rt_sm_done_d <= '1'; WHEN OTHERS => next_state <= HARDCOPYIII_RTOCT_WAIT; END CASE; -- case(current_state) -- schedule the outputs p_cnt_d <= p_cnt_d_var; n_cnt_d <= n_cnt_d_var; p_cnt_sub_d <= p_cnt_sub_d_var; n_cnt_sub_d <= n_cnt_sub_d_var; END PROCESS; END hardcopyiii_rt_sm_rtl; ------------------------------------------------------------------------------- -- Module Name: hardcopyiii_termination_aux_clock_div -- Description: auxilary clock divider module ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY hardcopyiii_termination_aux_clock_div IS GENERIC ( clk_divide_by : INTEGER := 1; extra_latency : INTEGER := 0 ); PORT ( clk : IN STD_LOGIC; reset : IN STD_LOGIC := '0'; clkout : OUT STD_LOGIC ); END hardcopyiii_termination_aux_clock_div; ARCHITECTURE oct_clock_div_arch OF hardcopyiii_termination_aux_clock_div IS SIGNAL clk_edges : INTEGER := -1; SIGNAL div_n_register : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0) := (OTHERS => '0'); BEGIN PROCESS(clk,reset) VARIABLE div_n : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0) := (OTHERS => '0'); VARIABLE m : INTEGER := 0; VARIABLE running_clk_edge : INTEGER := -1; BEGIN running_clk_edge := clk_edges; IF (reset = '1') THEN clk_edges <= -1; m := 0; div_n := (OTHERS => '0'); ELSE IF (clk'EVENT) THEN IF (running_clk_edge = -1) THEN m := 0; div_n(0) := clk; IF (clk = '1') THEN running_clk_edge := 0; END IF; ELSIF (running_clk_edge mod clk_divide_by = 0) THEN div_n(0) := NOT div_n(0); END IF; IF (running_clk_edge >= 0 OR clk = '1') THEN clk_edges <= (running_clk_edge + 1) mod (2 * clk_divide_by); END IF; END IF; END IF; m := 0; div_n_register(m) <= div_n(m); WHILE (m < 2 * extra_latency) LOOP div_n_register(m+1) <= div_n_register(m); m := m + 1; END LOOP; END PROCESS; clkout <= div_n_register(2 * extra_latency); END oct_clock_div_arch; ------------------------------------------------------------------------------- -- -- Module Name : hardcopyiii_termination -- -- Description : HARDCOPYIII Termination Atom -- Verilog simulation model -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; USE IEEE.VITAL_Timing.ALL; USE IEEE.VITAL_Primitives.ALL; use work.hardcopyiii_atom_pack.all; USE WORK.hardcopyiii_termination_aux_clock_div; USE WORK.hardcopyiii_rt_sm; ENTITY hardcopyiii_termination IS GENERIC ( runtime_control : STRING := "false"; allow_serial_data_from_core : STRING := "false"; power_down : STRING := "true"; enable_parallel_termination : STRING := "false"; test_mode : STRING := "false"; enable_calclk_divider : STRING := "false"; -- replaced by below clock_divider_enable : STRING := "false"; enable_pwrupmode_enser_for_usrmode : STRING := "false"; bypass_enser_logic : STRING := "false"; bypass_rt_calclk : STRING := "false"; enable_rt_scan_mode : STRING := "false"; enable_loopback : STRING := "false"; force_rtcalen_for_pllbiasen : STRING := "false"; enable_rt_sm_loopback : STRING := "false"; select_vrefl_values : integer := 0; select_vrefh_values : integer := 0; divide_intosc_by : integer := 2; use_usrmode_clear_for_configmode : STRING := "false"; tipd_rup : VitalDelayType01 := DefpropDelay01; tipd_rdn : VitalDelayType01 := DefpropDelay01; tipd_terminationclock : VitalDelayType01 := DefpropDelay01; tipd_terminationclear : VitalDelayType01 := DefpropDelay01; tipd_terminationenable : VitalDelayType01 := DefpropDelay01; tipd_serializerenable : VitalDelayType01 := DefpropDelay01; tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01; tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01); lpm_type : STRING := "hardcopyiii_termination"); PORT ( rup : IN std_logic := '0'; rdn : IN std_logic := '0'; terminationclock : IN std_logic := '0'; terminationclear : IN std_logic := '0'; terminationenable : IN std_logic := '1'; serializerenable : IN std_logic := '0'; terminationcontrolin : IN std_logic := '0'; scanin : IN std_logic := '0'; scanen : IN std_logic := '0'; otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0'); devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; incrup : OUT std_logic; incrdn : OUT std_logic; serializerenableout : OUT std_logic; terminationcontrol : OUT std_logic; terminationcontrolprobe : OUT std_logic; scanout : OUT std_logic; shiftregisterprobe : OUT std_logic); END hardcopyiii_termination; ARCHITECTURE hardcopyiii_oct_arch OF hardcopyiii_termination IS COMPONENT hardcopyiii_termination_aux_clock_div GENERIC ( clk_divide_by : INTEGER := 1; extra_latency : INTEGER := 0 ); PORT ( clk : IN STD_LOGIC; reset : IN STD_LOGIC := '0'; clkout : OUT STD_LOGIC ); END COMPONENT; COMPONENT hardcopyiii_rt_sm PORT ( rup : IN std_logic; rdn : IN std_logic; clk : IN std_logic; clken : IN std_logic; clr : IN std_logic; rtena : IN std_logic; rscaldone : IN std_logic; rtoffsetp : OUT std_logic_vector(3 DOWNTO 0); rtoffsetn : OUT std_logic_vector(3 DOWNTO 0); caldone : OUT std_logic; sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0); sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0) ); END COMPONENT; -- HW outputs SIGNAL compout_rup_core : std_logic; SIGNAL compout_rdn_core : std_logic; SIGNAL ser_data_io : std_logic; SIGNAL ser_data_core : std_logic; -- HW inputs SIGNAL usr_clk : std_logic; SIGNAL cal_clk : std_logic; SIGNAL rscal_clk : std_logic; SIGNAL cal_clken : std_logic; SIGNAL cal_nclr : std_logic; -- legality check on enser SIGNAL enser_checked : std_logic := '0'; -- Shift Register SIGNAL sreg_bit_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL sreg_bit_out_tmp0 : std_logic := '0'; SIGNAL sreg_vshift_bit_tmp : std_logic := '0'; SIGNAL sreg_vshift_bit_out : std_logic := '0'; SIGNAL sreg_rscaldone_prev : std_logic := '0'; SIGNAL sreg_rscaldone_prev1 : std_logic := '0'; SIGNAL sregn_rscaldone_out : std_logic := '0'; SIGNAL sreg_bit6_prev : std_logic := '1'; -- nreg before SA-ADC SIGNAL regn_rup_in : std_logic; SIGNAL regn_rdn_in : std_logic; SIGNAL regn_compout_rup : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL regn_compout_rdn : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0'); -- SA-ADC SIGNAL sa_octcaln_out : std_logic_vector(6 DOWNTO 0); -- RUP - NMOS SIGNAL sa_octcalp_out : std_logic_vector(6 DOWNTO 0); -- RDN - PMOS SIGNAL sa_octcaln_in : std_logic_vector(6 DOWNTO 0); SIGNAL sa_octcalp_in : std_logic_vector(6 DOWNTO 0); -- ENSER SIGNAL enser_out : std_logic; SIGNAL enser_gen_out : std_logic; SIGNAL enser_cnt : INTEGER := 0; -- RT State Machine SIGNAL rtsm_rup_in : std_logic; SIGNAL rtsm_rdn_in : std_logic; SIGNAL rtsm_rtena_in : std_logic; SIGNAL rtsm_rscaldone_in : std_logic; SIGNAL rtsm_caldone_out : std_logic; SIGNAL rtsm_rtoffsetp_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL rtsm_rtoffsetn_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL rtsm_sel_rup_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0'); SIGNAL rtsm_sel_rdn_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0'); -- RT Adder/Sub SIGNAL rtas_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0); SIGNAL rtas_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0); SIGNAL rtas_rtoffsetp_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL rtas_rtoffsetn_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL rtas_rs_rpcdp_out : std_logic_vector(6 DOWNTO 0); SIGNAL rtas_rs_rpcdn_out : std_logic_vector(6 DOWNTO 0); SIGNAL rtas_rt_rpcdp_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL rtas_rt_rpcdn_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0'); -- P2S SIGNAL p2s_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0); SIGNAL p2s_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0); SIGNAL p2s_rt_rpcdp_in : std_logic_vector(6 DOWNTO 0); SIGNAL p2s_rt_rpcdn_in : std_logic_vector(6 DOWNTO 0); SIGNAL p2s_enser_in : std_logic; SIGNAL p2s_clk_in : std_logic; SIGNAL p2s_ser_data_out : std_logic; SIGNAL p2s_parallel_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0'); SIGNAL p2s_serial_reg : std_logic := '0'; SIGNAL p2s_index : integer := 27; -- used to set SA outputs SIGNAL temp_xhdl10 : std_logic; SIGNAL temp_xhdl12 : std_logic; SIGNAL temp_xhdl14 : std_logic; SIGNAL temp_xhdl16 : std_logic; SIGNAL temp_xhdl18 : std_logic; SIGNAL temp_xhdl20 : std_logic; SIGNAL temp_xhdl22 : std_logic; SIGNAL temp_xhdl24 : std_logic; SIGNAL temp_xhdl26 : std_logic; SIGNAL temp_xhdl28 : std_logic; SIGNAL temp_xhdl30 : std_logic; SIGNAL temp_xhdl32 : std_logic; SIGNAL temp_xhdl34 : std_logic; SIGNAL temp_xhdl36 : std_logic; SIGNAL MY_GND : std_logic := '0'; -- timing SIGNAL rup_ipd : std_logic; SIGNAL rdn_ipd : std_logic; SIGNAL terminationclock_ipd : std_logic; SIGNAL terminationclear_ipd : std_logic; SIGNAL terminationenable_ipd : std_logic; SIGNAL serializerenable_ipd : std_logic; SIGNAL terminationcontrolin_ipd : std_logic; SIGNAL otherserializerenable_ipd : std_logic_vector(8 DOWNTO 0); BEGIN -- primary outputs incrup <= terminationenable_ipd WHEN (enable_loopback = "true") ELSE compout_rup_core; incrdn <= terminationclear_ipd WHEN (enable_loopback = "true") ELSE compout_rdn_core; terminationcontrol <= ser_data_io; terminationcontrolprobe <= serializerenable_ipd WHEN (enable_loopback = "true") ELSE ser_data_core; shiftregisterprobe <= terminationclock_ipd WHEN (enable_loopback = "true") ELSE sreg_vshift_bit_out; serializerenableout <= serializerenable; compout_rup_core <= rup ; compout_rdn_core <= rdn ; ser_data_io <= terminationcontrolin WHEN (allow_serial_data_from_core = "true") ELSE p2s_ser_data_out; ser_data_core <= p2s_ser_data_out ; -- primary inputs usr_clk <= terminationclock ; cal_nclr <= '1' WHEN (terminationclear = '1') ELSE '0'; cal_clken <= '1' WHEN (terminationenable = '1' AND serializerenable = '1') ELSE '0'; -- divide by 100 clock m_gen_calclk : hardcopyiii_termination_aux_clock_div GENERIC MAP ( clk_divide_by => 100, extra_latency => 0) PORT MAP ( clk => usr_clk, reset => MY_GND, clkout => cal_clk); rscal_clk <= cal_clk AND (NOT sregn_rscaldone_out) ; -- legality check on enser PROCESS BEGIN WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1'); IF (serializerenable = '1' AND cal_clken = '0') THEN IF (otherserializerenable(0) = '1' OR otherserializerenable(1) = '1' OR otherserializerenable(2) = '1' OR otherserializerenable(3) = '1' OR otherserializerenable(4) = '1' OR otherserializerenable(5) = '1' OR otherserializerenable(6) = '1' OR otherserializerenable(7) = '1' OR otherserializerenable(8) = '1') THEN IF (enser_checked = '0') THEN assert false report "serializizerable and some bits of otherserializerenable are asserted at data transfer time" severity warning; enser_checked <= '1'; END IF; ELSE enser_checked <= '0'; -- for another check END IF; ELSE enser_checked <= '0'; -- for another check END IF; END PROCESS; -- SHIFT regiter PROCESS BEGIN WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '1') OR (cal_nclr'EVENT AND cal_nclr = '1'); IF (cal_nclr = '1') THEN sreg_bit6_prev <= '1'; sreg_bit_out <= "0000000"; sreg_vshift_bit_out <= '0'; sreg_vshift_bit_tmp <= '0'; sreg_bit_out_tmp0 <= '0'; sreg_rscaldone_prev <= '0'; sreg_rscaldone_prev1 <= '0'; ELSE IF (cal_clken = '1') THEN sreg_bit_out(6) <= sreg_bit6_prev; sreg_bit_out(5) <= sreg_bit_out(6); sreg_bit_out(4) <= sreg_bit_out(5); sreg_bit_out(3) <= sreg_bit_out(4); sreg_bit_out(2) <= sreg_bit_out(3); sreg_bit_out(1) <= sreg_bit_out(2); sreg_bit_out_tmp0 <= sreg_bit_out(1); sreg_vshift_bit_tmp <= sreg_bit_out_tmp0; sreg_bit_out(0) <= sreg_bit_out(1) OR sreg_vshift_bit_tmp; sreg_vshift_bit_out <= sreg_bit_out_tmp0 OR sreg_vshift_bit_tmp; sreg_bit6_prev <= '0'; END IF; END IF; -- might falling outside of 10 cycles IF (sreg_vshift_bit_tmp = '1') THEN sreg_rscaldone_prev <= '1'; END IF; sreg_rscaldone_prev1 <= sreg_rscaldone_prev; END PROCESS; PROCESS BEGIN WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '0') OR (cal_nclr'EVENT AND cal_nclr = '1'); IF (cal_nclr = '1') THEN sregn_rscaldone_out <= '0'; ELSE -- if (cal_clken == 1'b1) - outside of 10 cycles IF (sreg_rscaldone_prev1 = '1' AND sregn_rscaldone_out = '0') THEN sregn_rscaldone_out <= '1'; END IF; END IF; END PROCESS; -- nreg and SA-ADC: -- -- RDN_vol < ref_voltage < RUP_voltage -- after reset, ref_voltage=VCCN/2; after ref_voltage_shift, ref_voltage=neighbor(VCCN/2) -- at 0 code, RUP=VCCN so voltage_compare_out for RUP = 0 -- RDN=GND so voltage compare out for RDN = 0 regn_rup_in <= rup ; regn_rdn_in <= rdn ; PROCESS BEGIN WAIT UNTIL (cal_nclr'EVENT AND cal_nclr = '1') OR (rscal_clk'EVENT AND rscal_clk = '0'); IF (cal_nclr = '1') THEN regn_compout_rup <= "0000000"; regn_compout_rdn <= "0000000"; ELSE -- rup IF (sreg_bit_out(0) = '1') THEN regn_compout_rup(0) <= regn_rup_in; END IF; IF (sreg_bit_out(1) = '1') THEN regn_compout_rup(1) <= regn_rup_in; END IF; IF (sreg_bit_out(2) = '1') THEN regn_compout_rup(2) <= regn_rup_in; END IF; IF (sreg_bit_out(3) = '1') THEN regn_compout_rup(3) <= regn_rup_in; END IF; IF (sreg_bit_out(4) = '1') THEN regn_compout_rup(4) <= regn_rup_in; END IF; IF (sreg_bit_out(5) = '1') THEN regn_compout_rup(5) <= regn_rup_in; END IF; IF (sreg_bit_out(6) = '1') THEN regn_compout_rup(6) <= regn_rup_in; END IF; -- rdn IF (sreg_bit_out(0) = '1') THEN regn_compout_rdn(0) <= regn_rdn_in; END IF; IF (sreg_bit_out(1) = '1') THEN regn_compout_rdn(1) <= regn_rdn_in; END IF; IF (sreg_bit_out(2) = '1') THEN regn_compout_rdn(2) <= regn_rdn_in; END IF; IF (sreg_bit_out(3) = '1') THEN regn_compout_rdn(3) <= regn_rdn_in; END IF; IF (sreg_bit_out(4) = '1') THEN regn_compout_rdn(4) <= regn_rdn_in; END IF; IF (sreg_bit_out(5) = '1') THEN regn_compout_rdn(5) <= regn_rdn_in; END IF; IF (sreg_bit_out(6) = '1') THEN regn_compout_rdn(6) <= regn_rdn_in; END IF; END IF; END PROCESS; sa_octcaln_in <= sreg_bit_out ; sa_octcalp_in <= sreg_bit_out ; -- RUP - octcaln_in == 1 = (pin_voltage < ref_voltage): clear the bit setting temp_xhdl10 <= '1' WHEN (sa_octcaln_in(0) = '1') ELSE sa_octcaln_out(0); sa_octcaln_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(0) = '1') ELSE temp_xhdl10; temp_xhdl12 <= '1' WHEN (sa_octcaln_in(1) = '1') ELSE sa_octcaln_out(1); sa_octcaln_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(1) = '1') ELSE temp_xhdl12; temp_xhdl14 <= '1' WHEN (sa_octcaln_in(2) = '1') ELSE sa_octcaln_out(2); sa_octcaln_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(2) = '1') ELSE temp_xhdl14; temp_xhdl16 <= '1' WHEN (sa_octcaln_in(3) = '1') ELSE sa_octcaln_out(3); sa_octcaln_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(3) = '1') ELSE temp_xhdl16; temp_xhdl18 <= '1' WHEN (sa_octcaln_in(4) = '1') ELSE sa_octcaln_out(4); sa_octcaln_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(4) = '1') ELSE temp_xhdl18; temp_xhdl20 <= '1' WHEN (sa_octcaln_in(5) = '1') ELSE sa_octcaln_out(5); sa_octcaln_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(5) = '1') ELSE temp_xhdl20; temp_xhdl22 <= '1' WHEN (sa_octcaln_in(6) = '1') ELSE sa_octcaln_out(6); sa_octcaln_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(6) = '1') ELSE temp_xhdl22; temp_xhdl24 <= '1' WHEN (sa_octcalp_in(0) = '1') ELSE sa_octcalp_out(0); sa_octcalp_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(0) = '1') ELSE temp_xhdl24; temp_xhdl26 <= '1' WHEN (sa_octcalp_in(1) = '1') ELSE sa_octcalp_out(1); sa_octcalp_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(1) = '1') ELSE temp_xhdl26; temp_xhdl28 <= '1' WHEN (sa_octcalp_in(2) = '1') ELSE sa_octcalp_out(2); sa_octcalp_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(2) = '1') ELSE temp_xhdl28; temp_xhdl30 <= '1' WHEN (sa_octcalp_in(3) = '1') ELSE sa_octcalp_out(3); sa_octcalp_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(3) = '1') ELSE temp_xhdl30; temp_xhdl32 <= '1' WHEN (sa_octcalp_in(4) = '1') ELSE sa_octcalp_out(4); sa_octcalp_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(4) = '1') ELSE temp_xhdl32; temp_xhdl34 <= '1' WHEN (sa_octcalp_in(5) = '1') ELSE sa_octcalp_out(5); sa_octcalp_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(5) = '1') ELSE temp_xhdl34; temp_xhdl36 <= '1' WHEN (sa_octcalp_in(6) = '1') ELSE sa_octcalp_out(6); sa_octcalp_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(6) = '1') ELSE temp_xhdl36; -- ENSER enser_out <= serializerenable WHEN (runtime_control = "true" OR bypass_enser_logic = "true") ELSE enser_gen_out; enser_gen_out <= '1' WHEN (enser_cnt > 0 AND enser_cnt < 31) ELSE '0'; PROCESS BEGIN WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1') OR (sregn_rscaldone_out'EVENT AND sregn_rscaldone_out = '1'); IF (sregn_rscaldone_out = '0') THEN enser_cnt <= 0; ELSE IF (enser_cnt < 63) THEN enser_cnt <= enser_cnt + 1; END IF; END IF; END PROCESS; -- RT SM rtsm_rup_in <= rup ; rtsm_rdn_in <= rdn ; rtsm_rtena_in <= '1' WHEN (enable_parallel_termination = "true") ELSE '0'; rtsm_rscaldone_in <= sregn_rscaldone_out ; m_rt_sm : hardcopyiii_rt_sm PORT MAP ( rup => rtsm_rup_in, rdn => rtsm_rdn_in, clk => cal_clk, clken => cal_clken, clr => cal_nclr, rtena => rtsm_rtena_in, rscaldone => rtsm_rscaldone_in, rtoffsetp => rtsm_rtoffsetp_out, rtoffsetn => rtsm_rtoffsetn_out, caldone => rtsm_caldone_out, sel_rup_vref => rtsm_sel_rup_vref_out, sel_rdn_vref => rtsm_sel_rdn_vref_out ); -- RT Adder/Sub rtas_rs_rpcdp_in <= sa_octcalp_out ; rtas_rs_rpcdn_in <= sa_octcaln_out ; rtas_rtoffsetp_in <= "0000" & rtsm_rtoffsetp_out(2 DOWNTO 0); rtas_rtoffsetn_in <="0000" & rtsm_rtoffsetn_out(2 DOWNTO 0); rtas_rs_rpcdp_out <= rtas_rs_rpcdp_in ; rtas_rs_rpcdn_out <= rtas_rs_rpcdn_in ; rtas_rt_rpcdn_out <= (rtas_rs_rpcdn_in + rtas_rtoffsetn_in) WHEN (rtsm_rtoffsetn_out(3) = '0') ELSE (rtas_rs_rpcdn_in - rtas_rtoffsetn_in); rtas_rt_rpcdp_out <= (rtas_rs_rpcdp_in + rtas_rtoffsetp_in) WHEN (rtsm_rtoffsetp_out(3) = '0') ELSE (rtas_rs_rpcdp_in - rtas_rtoffsetp_in); -- P2S p2s_rs_rpcdp_in <= rtas_rs_rpcdp_out ; p2s_rs_rpcdn_in <= rtas_rs_rpcdn_out ; p2s_rt_rpcdp_in <= rtas_rt_rpcdp_out; p2s_rt_rpcdn_in <= rtas_rt_rpcdn_out; p2s_enser_in <= enser_out ; p2s_clk_in <= usr_clk ; p2s_ser_data_out <= p2s_serial_reg ; -- load - clken PROCESS BEGIN WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1'); IF (cal_nclr = '1') THEN p2s_parallel_reg <= "0000000000000000000000000000"; ELSE IF (cal_clken = '1') THEN p2s_parallel_reg <= p2s_rs_rpcdp_in & p2s_rs_rpcdn_in & p2s_rt_rpcdp_in & p2s_rt_rpcdn_in; END IF; END IF; END PROCESS; -- shift - enser PROCESS BEGIN WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1'); IF (cal_nclr = '1') THEN p2s_serial_reg <= '0'; p2s_index <= 27; ELSE IF (p2s_enser_in = '1' AND cal_clken = '0') THEN p2s_serial_reg <= p2s_parallel_reg(p2s_index); IF (p2s_index > 0) THEN p2s_index <= p2s_index - 1; END IF; END IF; END IF; END PROCESS; -------------------- -- INPUT PATH DELAYS -------------------- WireDelay : block begin VitalWireDelay (rup_ipd, rup, tipd_rup); VitalWireDelay (rdn_ipd, rdn, tipd_rdn); VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock); VitalWireDelay (terminationclear_ipd, terminationclear, tipd_terminationclear); VitalWireDelay (terminationenable_ipd, terminationenable, tipd_terminationenable); VitalWireDelay (serializerenable_ipd, serializerenable, tipd_serializerenable); VitalWireDelay (terminationcontrolin_ipd, terminationcontrolin, tipd_terminationcontrolin); VitalWireDelay (otherserializerenable_ipd(0), otherserializerenable(0), tipd_otherserializerenable(0)); VitalWireDelay (otherserializerenable_ipd(1), otherserializerenable(1), tipd_otherserializerenable(1)); VitalWireDelay (otherserializerenable_ipd(2), otherserializerenable(2), tipd_otherserializerenable(2)); VitalWireDelay (otherserializerenable_ipd(3), otherserializerenable(3), tipd_otherserializerenable(3)); VitalWireDelay (otherserializerenable_ipd(4), otherserializerenable(4), tipd_otherserializerenable(4)); VitalWireDelay (otherserializerenable_ipd(5), otherserializerenable(5), tipd_otherserializerenable(5)); VitalWireDelay (otherserializerenable_ipd(6), otherserializerenable(6), tipd_otherserializerenable(6)); VitalWireDelay (otherserializerenable_ipd(7), otherserializerenable(7), tipd_otherserializerenable(7)); VitalWireDelay (otherserializerenable_ipd(8), otherserializerenable(8), tipd_otherserializerenable(8)); end block; END hardcopyiii_oct_arch; ------------------------------------------------------------------------------- -- -- Module Name : hardcopyiii_termination_logic -- -- Description : HARDCOPYIII Termination Logic Atom -- Verilog simulation model -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_Timing.ALL; USE IEEE.VITAL_Primitives.ALL; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_termination_logic IS GENERIC ( tipd_serialloadenable : VitalDelayType01 := DefpropDelay01; tipd_terminationclock : VitalDelayType01 := DefpropDelay01; tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01; tipd_terminationdata : VitalDelayType01 := DefpropDelay01; test_mode : string := "false"; lpm_type : string := "hardcopyiii_termination_logic"); PORT ( serialloadenable : IN std_logic := '0'; terminationclock : IN std_logic := '0'; parallelloadenable : IN std_logic := '0'; terminationdata : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0); parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0)); END hardcopyiii_termination_logic; ARCHITECTURE hardcopyiii_oct_logic_arch OF hardcopyiii_termination_logic IS CONSTANT xhdl_timescale : time := 1 ps; SIGNAL usr_clk : std_logic; SIGNAL rs_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0'); SIGNAL rt_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0'); SIGNAL hold_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0'); SIGNAL shift_index : integer := 27; -- timing SIGNAL serialloadenable_ipd : std_logic; SIGNAL terminationclock_ipd : std_logic; SIGNAL parallelloadenable_ipd : std_logic; SIGNAL terminationdata_ipd : std_logic; BEGIN seriesterminationcontrol <= rs_reg; parallelterminationcontrol <= rt_reg; usr_clk <= terminationclock AFTER 11 * xhdl_timescale; PROCESS BEGIN WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1'); IF (serialloadenable = '0') THEN shift_index <= 27; ELSE hold_reg(shift_index) <= terminationdata; IF (shift_index > 0) THEN shift_index <= shift_index - 1; END IF; END IF; END PROCESS; PROCESS BEGIN WAIT UNTIL (parallelloadenable'EVENT AND parallelloadenable = '1'); IF (parallelloadenable = '1') THEN rs_reg <= hold_reg(27 DOWNTO 14); rt_reg <= hold_reg(13 DOWNTO 0); END IF; END PROCESS; -------------------- -- INPUT PATH DELAYS -------------------- WireDelay : block begin VitalWireDelay (serialloadenable_ipd, serialloadenable, tipd_serialloadenable); VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock); VitalWireDelay (parallelloadenable_ipd, parallelloadenable, tipd_parallelloadenable); VitalWireDelay (terminationdata_ipd, terminationdata, tipd_terminationdata); end block; END hardcopyiii_oct_logic_arch; ------------------------------------------------------------------------------- -- utilities common for ddr ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; package hardcopyiii_atom_ddr_pack is function dll_unsigned2bin (in_int : integer) return std_logic_vector; end hardcopyiii_atom_ddr_pack; library IEEE; use IEEE.std_logic_1164.all; package body hardcopyiii_atom_ddr_pack is -- truncate input integer to get 6 LSB bits function dll_unsigned2bin (in_int : integer) return std_logic_vector is variable tmp_int, i : integer; variable tmp_bit : integer; variable result : std_logic_vector(5 downto 0) := "000000"; begin tmp_int := in_int; for i in 0 to 5 loop tmp_bit := tmp_int MOD 2; if (tmp_bit = 1) then result(i) := '1'; else result(i) := '0'; end if; tmp_int := tmp_int/2; end loop; return result; end dll_unsigned2bin; end hardcopyiii_atom_ddr_pack; ------------------------------------------------------------------------------- -- auxilary module for ddr ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ENTITY hardcopyiii_dll_gray_encoder IS GENERIC ( width : integer := 6 ); PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0'); gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END hardcopyiii_dll_gray_encoder; ARCHITECTURE hardcopyiii_dll_gray_encoder_arch OF hardcopyiii_dll_gray_encoder IS SIGNAL greg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0'); BEGIN gout <= greg; PROCESS(mbin) VARIABLE i : INTEGER := 0; BEGIN greg(width-1) <= mbin(width-1); IF (width > 1) THEN i := width - 2; WHILE (i >= 0) LOOP greg(i) <= mbin(i+1) XOR mbin(i); i := i - 1; END LOOP; END IF; END PROCESS; END hardcopyiii_dll_gray_encoder_arch; ------------------------------------------------------------------------------- -- auxilary module for ddr ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ENTITY hardcopyiii_dll_gray_decoder IS GENERIC ( width : integer := 6 ); PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0'); bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END hardcopyiii_dll_gray_decoder; ARCHITECTURE hardcopyiii_dll_gray_decoder_arch OF hardcopyiii_dll_gray_decoder IS SIGNAL breg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0'); BEGIN bout <= breg; PROCESS(gin) VARIABLE i : INTEGER := 0; VARIABLE bvar : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0'); BEGIN bvar(width-1) := gin(width-1); IF (width > 1) THEN i := width - 2; WHILE (i >= 0) LOOP bvar(i) := bvar(i+1) XOR gin(i); i := i - 1; END LOOP; END IF; breg <= bvar; END PROCESS; END hardcopyiii_dll_gray_decoder_arch; ------------------------------------------------------------------------------- -- Module Name: hardcopyiii_ddr_delay_chain_s -- Description: auxilary module - delay chain-setting ------------------------------------------------------------------------------- Library ieee; use ieee.std_logic_1164.all; use work.hardcopyiii_atom_pack.all; use work.hardcopyiii_dll_gray_decoder; ENTITY hardcopyiii_ddr_delay_chain_s IS GENERIC ( use_phasectrlin : string := "true"; phase_setting : integer := 0; delay_buffer_mode : string := "high"; sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; phasectrlin_limit : integer := 7 ); PORT ( clk : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0'); phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); delayed_clkout : OUT std_logic ); END hardcopyiii_ddr_delay_chain_s; ARCHITECTURE hardcopyiii_ddr_delay_chain_s_arch OF hardcopyiii_ddr_delay_chain_s IS COMPONENT hardcopyiii_dll_gray_decoder GENERIC ( width : integer := 6 ); PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0'); bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; SIGNAL clk_delay : INTEGER := 0; SIGNAL delayed_clk : STD_LOGIC := '0'; SIGNAL delayctrl_bin : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0'); SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0'); SIGNAL phasectrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); BEGIN delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0'; delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0'; delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0'; delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0'; delayctrlin_in(4) <= '1' WHEN (delayctrlin(4) = '1') ELSE '0'; delayctrlin_in(5) <= '1' WHEN (delayctrlin(5) = '1') ELSE '0'; phasectrlin_in(0) <= '1' WHEN (phasectrlin(0) = '1') ELSE '0'; phasectrlin_in(1) <= '1' WHEN (phasectrlin(1) = '1') ELSE '0'; phasectrlin_in(2) <= '1' WHEN (phasectrlin(2) = '1') ELSE '0'; phasectrlin_in(3) <= '1' WHEN (phasectrlin(3) = '1') ELSE '0'; -- decoder mdr_delayctrl_in_dec : hardcopyiii_dll_gray_decoder GENERIC MAP (width => 6) PORT MAP (gin => delayctrlin_in, bout => delayctrl_bin); PROCESS(delayctrl_bin, phasectrlin_in) variable sim_intrinsic_delay : INTEGER := 0; variable acell_delay : INTEGER := 0; variable delay_chain_len : INTEGER := 0; BEGIN IF (delay_buffer_mode = "low") THEN sim_intrinsic_delay := sim_low_buffer_intrinsic_delay; ELSE sim_intrinsic_delay := sim_high_buffer_intrinsic_delay; END IF; -- cell acell_delay := sim_intrinsic_delay + alt_conv_integer(delayctrl_bin) * sim_buffer_delay_increment; -- no of cells IF (use_phasectrlin = "false") THEN delay_chain_len := phase_setting; ELSIF (alt_conv_integer(phasectrlin_in) > phasectrlin_limit) THEN delay_chain_len := 0; ELSE delay_chain_len := alt_conv_integer(phasectrlin_in); END IF; -- total delay - added extra 1 ps for resolving racing clk_delay <= delay_chain_len * acell_delay + 1; IF ((use_phasectrlin = "true") AND (alt_conv_integer(phasectrlin_in) > phasectrlin_limit)) THEN assert false report "Warning: DDR phasesetting has invalid phasectrlin setting" severity warning; END IF; END PROCESS; -- generating delays delayed_clk <= transport clk after (clk_delay * 1 ps); delayed_clkout <= delayed_clk; END hardcopyiii_ddr_delay_chain_s_arch; ------------------------------------------------------------------------------- -- based on dffeas ------------------------------------------------------------------------------- Library ieee; use ieee.std_logic_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; entity hardcopyiii_ddr_io_reg is generic( power_up : string := "DONT_CARE"; is_wysiwyg : string := "false"; x_on_violation : string := "on"; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01; tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_asdata_q: VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_d : VitalDelayType01 := DefPropDelay01; tipd_asdata : VitalDelayType01 := DefPropDelay01; tipd_sclr : VitalDelayType01 := DefPropDelay01; tipd_sload : VitalDelayType01 := DefPropDelay01; tipd_clrn : VitalDelayType01 := DefPropDelay01; tipd_prn : VitalDelayType01 := DefPropDelay01; tipd_aload : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; InstancePath: STRING := "*" ); port( d : in std_logic := '0'; clk : in std_logic := '0'; ena : in std_logic := '1'; clrn : in std_logic := '1'; prn : in std_logic := '1'; aload : in std_logic := '0'; asdata : in std_logic := '1'; sclr : in std_logic := '0'; sload : in std_logic := '0'; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; q : out std_logic ); attribute VITAL_LEVEL0 of hardcopyiii_ddr_io_reg : entity is TRUE; end hardcopyiii_ddr_io_reg; architecture vital_hardcopyiii_ddr_io_reg of hardcopyiii_ddr_io_reg is attribute VITAL_LEVEL0 of vital_hardcopyiii_ddr_io_reg : architecture is TRUE; signal clk_ipd : std_logic; signal d_ipd : std_logic; signal d_dly : std_logic; signal asdata_ipd : std_logic; signal asdata_dly : std_logic; signal asdata_dly1 : std_logic; signal sclr_ipd : std_logic; signal sload_ipd : std_logic; signal clrn_ipd : std_logic; signal prn_ipd : std_logic; signal aload_ipd : std_logic; signal ena_ipd : std_logic; begin d_dly <= d_ipd; asdata_dly <= asdata_ipd; asdata_dly1 <= asdata_dly; --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (d_ipd, d, tipd_d); VitalWireDelay (asdata_ipd, asdata, tipd_asdata); VitalWireDelay (sclr_ipd, sclr, tipd_sclr); VitalWireDelay (sload_ipd, sload, tipd_sload); VitalWireDelay (clrn_ipd, clrn, tipd_clrn); VitalWireDelay (prn_ipd, prn, tipd_prn); VitalWireDelay (aload_ipd, aload, tipd_aload); VitalWireDelay (ena_ipd, ena, tipd_ena); end block; VITALtiming : process ( clk_ipd, d_dly, asdata_dly1, sclr_ipd, sload_ipd, clrn_ipd, prn_ipd, aload_ipd, ena_ipd, devclrn, devpor) variable Tviol_d_clk : std_ulogic := '0'; variable Tviol_asdata_clk : std_ulogic := '0'; variable Tviol_sclr_clk : std_ulogic := '0'; variable Tviol_sload_clk : std_ulogic := '0'; variable Tviol_ena_clk : std_ulogic := '0'; variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit; variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit; variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit; variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit; variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit; variable q_VitalGlitchData : VitalGlitchDataType; variable iq : std_logic := '0'; variable idata: std_logic := '0'; -- variables for 'X' generation variable violation : std_logic := '0'; begin if (now = 0 ns) then if ((power_up = "low") or (power_up = "DONT_CARE")) then iq := '0'; elsif (power_up = "high") then iq := '1'; else iq := '0'; end if; end if; ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_d_clk, TimingData => TimingData_d_clk, TestSignal => d, TestSignalName => "DATAIN", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_d_clk_noedge_posedge, SetupLow => tsetup_d_clk_noedge_posedge, HoldHigh => thold_d_clk_noedge_posedge, HoldLow => thold_d_clk_noedge_posedge, CheckEnabled => TO_X01( (NOT clrn_ipd) OR (NOT prn_ipd) OR (sload_ipd) OR (sclr_ipd) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1', RefTransition => '/', HeaderMsg => InstancePath & "/hardcopyiii_ddr_io_reg", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_asdata_clk, TimingData => TimingData_asdata_clk, TestSignal => asdata_ipd, TestSignalName => "ASDATA", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_asdata_clk_noedge_posedge, SetupLow => tsetup_asdata_clk_noedge_posedge, HoldHigh => thold_asdata_clk_noedge_posedge, HoldLow => thold_asdata_clk_noedge_posedge, CheckEnabled => TO_X01( (NOT clrn_ipd) OR (NOT prn_ipd) OR (NOT sload_ipd) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1', RefTransition => '/', HeaderMsg => InstancePath & "/hardcopyiii_ddr_io_reg", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_sclr_clk, TimingData => TimingData_sclr_clk, TestSignal => sclr_ipd, TestSignalName => "SCLR", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_sclr_clk_noedge_posedge, SetupLow => tsetup_sclr_clk_noedge_posedge, HoldHigh => thold_sclr_clk_noedge_posedge, HoldLow => thold_sclr_clk_noedge_posedge, CheckEnabled => TO_X01( (NOT clrn_ipd) OR (NOT prn_ipd) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1', RefTransition => '/', HeaderMsg => InstancePath & "/hardcopyiii_ddr_io_reg", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_sload_clk, TimingData => TimingData_sload_clk, TestSignal => sload_ipd, TestSignalName => "SLOAD", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_sload_clk_noedge_posedge, SetupLow => tsetup_sload_clk_noedge_posedge, HoldHigh => thold_sload_clk_noedge_posedge, HoldLow => thold_sload_clk_noedge_posedge, CheckEnabled => TO_X01( (NOT clrn_ipd) OR (NOT prn_ipd) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1', RefTransition => '/', HeaderMsg => InstancePath & "/hardcopyiii_ddr_io_reg", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_ena_clk, TimingData => TimingData_ena_clk, TestSignal => ena_ipd, TestSignalName => "ENA", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_ena_clk_noedge_posedge, SetupLow => tsetup_ena_clk_noedge_posedge, HoldHigh => thold_ena_clk_noedge_posedge, HoldLow => thold_ena_clk_noedge_posedge, CheckEnabled => TO_X01( (NOT clrn_ipd) OR (NOT prn_ipd) OR (NOT devpor) OR (NOT devclrn) ) /= '1', RefTransition => '/', HeaderMsg => InstancePath & "/hardcopyiii_ddr_io_reg", XOn => XOnChecks, MsgOn => MsgOnChecks ); end if; violation := Tviol_d_clk or Tviol_asdata_clk or Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk; if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then iq := '0'; elsif (prn_ipd = '0') then iq := '1'; elsif (aload_ipd = '1') then iq := asdata_dly1; elsif (violation = 'X' and x_on_violation = "on") then iq := 'X'; elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then if (ena_ipd = '1') then if (sclr_ipd = '1') then iq := '0'; elsif (sload_ipd = '1') then iq := asdata_dly1; else iq := d_dly; end if; end if; end if; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => q, OutSignalName => "Q", OutTemp => iq, Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_negedge, TRUE), 1 => (prn_ipd'last_event, tpd_prn_q_negedge, TRUE), 2 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE), 3 => (asdata_ipd'last_event, tpd_asdata_q, TRUE), 4 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)), GlitchData => q_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; end vital_hardcopyiii_ddr_io_reg; ------------------------------------------------------------------------------- -- -- Entity Name : HARDCOPYIII_dll -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; use work.hardcopyiii_pllpack.all; use work.hardcopyiii_atom_ddr_pack.all; use work.hardcopyiii_dll_gray_encoder; ENTITY hardcopyiii_dll is GENERIC ( input_frequency : string := "0 ps"; delay_buffer_mode : string := "low"; delay_chain_length : integer := 12; delayctrlout_mode : string := "normal"; jitter_reduction : string := "false"; use_upndnin : string := "false"; use_upndninclkena : string := "false"; dual_phase_comparators : string := "true"; sim_valid_lock : integer := 16; sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; static_delay_ctrl : integer := 0; lpm_type : string := "hardcopyiii_dll"; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_aload : VitalDelayType01 := DefpropDelay01; tipd_upndnin : VitalDelayType01 := DefpropDelay01; tipd_upndninclkena : VitalDelayType01 := DefpropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01; tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01) ); PORT ( clk : IN std_logic := '0'; aload : IN std_logic := '0'; upndnin : IN std_logic := '1'; upndninclkena : IN std_logic := '1'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '0'; delayctrlout : OUT std_logic_vector(5 DOWNTO 0); dqsupdate : OUT std_logic; offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0); offsetdelayctrlclkout : OUT std_logic; upndnout : OUT std_logic ); END hardcopyiii_dll; ARCHITECTURE vital_hcxdll of hardcopyiii_dll is COMPONENT hardcopyiii_dll_gray_encoder GENERIC ( width : integer := 6 ); PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0'); gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; signal clk_in : std_logic := '0'; signal aload_in_buf : std_logic := '0'; signal upndn_in : std_logic := '0'; signal upndninclkena_in : std_logic := '1'; signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000"; signal offsetdelayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000"; signal upndn_out : std_logic := '0'; signal dqsupdate_out : std_logic := '0'; signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01"; signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00"; signal para_static_delay_ctrl : integer := 0; signal para_jitter_reduction : std_logic := '0'; signal para_use_upndnin : std_logic := '0'; signal para_use_upndninclkena : std_logic := '1'; -- INTERNAL NETS AND VARIABLES -- for functionality - by modules signal sim_buffer_intrinsic_delay : INTEGER := 0; -- two reg on the de-assertion of dll SIGNAL aload_in : std_logic := '0'; SIGNAL aload_reg1 : std_logic := '1'; SIGNAL aload_reg2 : std_logic := '1'; -- delay and offset control out resolver signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000"; signal dr_delayctrl_int : std_logic_vector (5 DOWNTO 0) := "000000"; signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000"; signal dr_dllcount_in : std_logic_vector (5 DOWNTO 0) := "000000"; signal dr_clk8_in : std_logic := '0'; signal dr_aload_in : std_logic := '0'; signal dr_reg_dllcount : std_logic_vector (5 DOWNTO 0) := "000000"; signal para_static_delay_ctrl_gray : std_logic_vector (5 DOWNTO 0) := "000000"; -- delay chain setting counter signal dc_dllcount_out_gray : std_logic_vector (5 DOWNTO 0) := "000000"; signal dc_dllcount_out_vec : std_logic_vector (5 DOWNTO 0) := "000000"; signal dc_dllcount_out : integer := 0; signal dc_dqsupdate_out : std_logic := '0'; signal dc_upndn_in : std_logic := '1'; signal dc_aload_in : std_logic := '0'; signal dc_upndnclkena_in : std_logic := '1'; signal dc_clk8_in : std_logic := '0'; signal dc_clk1_in : std_logic := '0'; signal dc_dlltolock_in : std_logic := '0'; signal dc_reg_dllcount : integer := 0; signal dc_reg_dlltolock_pulse : std_logic := '0'; -- jitter reduction counter signal jc_upndn_out : std_logic := '0'; signal jc_upndnclkena_out : std_logic := '1'; signal jc_clk8_in : std_logic := '0'; signal jc_upndn_in : std_logic := '1'; signal jc_aload_in : std_logic := '0'; signal jc_clkena_in : std_logic := '1'; -- new in hardcopyiii signal jc_count : integer := 8; signal jc_reg_upndn : std_logic := '0'; signal jc_reg_upndnclkena : std_logic := '0'; -- phase comparator signal pc_lock : std_logic := '0'; -- new in hardcopyiii signal pc_upndn_out : std_logic := '1'; signal pc_dllcount_in : integer := 0; signal pc_clk1_in : std_logic := '0'; signal pc_clk8_in : std_logic := '0'; signal pc_aload_in : std_logic := '0'; signal pc_reg_upndn : std_logic := '1'; signal pc_delay : integer := 0; signal pc_lock_reg : std_logic := '0'; -- new in hardcopyiii signal pc_comp_range : integer := 0; -- new in hardcopyiii -- clock generator signal cg_clk_in : std_logic := '0'; signal cg_aload_in : std_logic := '0'; signal cg_clk1_out : std_logic := '0'; signal cg_clk8a_out : std_logic := '0'; signal cg_clk8b_out : std_logic := '0'; -- por: 000 signal cg_reg_1 : std_logic := '0'; signal cg_rega_2 : std_logic := '0'; signal cg_rega_3 : std_logic := '0'; -- por: 010 signal cg_regb_2 : std_logic := '1'; signal cg_regb_3 : std_logic := '0'; -- for violation checks signal dll_to_lock : std_logic := '0'; signal input_period : integer := 10000; signal clk_in_last_value : std_logic := 'X'; begin -- paramters input_period <= dqs_str2int(input_frequency); para_static_delay_ctrl <= static_delay_ctrl; para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0'; para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0'; para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0'; para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10"; para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "test" ELSE "10" WHEN delayctrlout_mode="normal" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00"; sim_buffer_intrinsic_delay <= sim_low_buffer_intrinsic_delay WHEN (delay_buffer_mode = "low") ELSE sim_high_buffer_intrinsic_delay; -- violation check block process (clk_in) variable got_first_rising_edge : std_logic := '0'; variable got_first_falling_edge : std_logic := '0'; variable per_violation : std_logic := '0'; variable duty_violation : std_logic := '0'; variable sent_per_violation : std_logic := '0'; variable sent_duty_violation : std_logic := '0'; variable clk_in_last_rising_edge : time := 0 ps; variable clk_in_last_falling_edge : time := 0 ps; variable input_period_ps : time := 10000 ps; variable duty_cycle : time := 5000 ps; variable clk_in_period : time := 10000 ps; variable clk_in_duty_cycle : time := 5000 ps; variable clk_per_tolerance : time := 2 ps; variable half_cycles_to_lock : integer := 1; variable init : boolean := true; begin if (init) then input_period_ps := dqs_str2int(input_frequency) * 1 ps; if (input_period_ps = 0 ps) then assert false report "Need to specify ps scale in simulation command" severity error; end if; duty_cycle := input_period_ps/2; clk_per_tolerance := 2 ps; half_cycles_to_lock := 0; init := false; end if; if (clk_in'event and clk_in = '1') then -- rising edge if (got_first_rising_edge = '0') then got_first_rising_edge := '1'; else -- subsequent rising -- check for clock period and duty cycle violation clk_in_period := now - clk_in_last_rising_edge; clk_in_duty_cycle := now - clk_in_last_falling_edge; if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then per_violation := '1'; if (sent_per_violation /= '1') then sent_per_violation := '1'; assert false report "Input clock frequency violation." severity warning; end if; elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then duty_violation := '1'; if (sent_duty_violation /= '1') then sent_duty_violation := '1'; assert false report "Input clock duty cycle violation." severity warning; end if; else if (per_violation = '1') then sent_per_violation := '0'; assert false report "Input clock frequency now matches specified clock frequency." severity warning; end if; per_violation := '0'; duty_violation := '0'; end if; end if; if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then half_cycles_to_lock := half_cycles_to_lock + 1; if (half_cycles_to_lock >= sim_valid_lock) then dll_to_lock <= '1'; assert false report "DLL to lock to incoming clock" severity note; end if; end if; clk_in_last_rising_edge := now; elsif (clk_in'event and clk_in = '0') then -- falling edge got_first_falling_edge := '1'; if (got_first_rising_edge = '1') then -- duty cycle check clk_in_duty_cycle := now - clk_in_last_rising_edge; if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then duty_violation := '1'; if (sent_duty_violation /= '1') then sent_duty_violation := '1'; assert false report "Input clock duty cycle violation." severity warning; end if; else duty_violation := '0'; end if; if (dll_to_lock = '0' and duty_violation = '0') then half_cycles_to_lock := half_cycles_to_lock + 1; end if; end if; clk_in_last_falling_edge := now; elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then -- switches from 1, 0 to X half_cycles_to_lock := 0; got_first_rising_edge := '0'; got_first_falling_edge := '0'; if (dll_to_lock = '1') then dll_to_lock <= '0'; assert false report "Illegal value detected on input clock. DLL will lose lock." severity warning; else assert false report "Illegal value detected on input clock." severity warning; end if; end if; clk_in_last_value <= clk_in; end process ; -- violation check -- outputs delayctrl_out <= dr_delayctrl_out; offsetdelayctrl_out <= dr_offsetctrl_out; offsetdelayctrlclkout <= dr_clk8_in; dqsupdate_out <= cg_clk8a_out; upndn_out <= pc_upndn_out; -- two registers on aload path -------------------------------------------- aload_in <= (aload_in_buf OR aload_reg2); process(clk_in) begin if (clk_in = '0' and clk_in'event) then aload_reg2 <= aload_reg1; aload_reg1 <= aload_in_buf; end if; end process; -- Delay and offset ctrl out resolver ------------------------------------- -------- convert calculations into integer -- inputs dr_clk8_in <= not cg_clk8b_out; dr_dllcount_in <= dc_dllcount_out_gray; dr_aload_in <= aload_in; mdll_count_enc : hardcopyiii_dll_gray_encoder GENERIC MAP (width => 6) PORT MAP (mbin => dc_dllcount_out_vec, gout => dc_dllcount_out_gray); dc_dllcount_out_vec <= dll_unsigned2bin(dc_dllcount_out); -- outputs dr_delayctrl_out <= dr_reg_dllcount; dr_offsetctrl_out <= dr_delayctrl_int; -- assumed para_static_delay_ctrl is gray-coded para_static_delay_ctrl_gray <= dll_unsigned2bin(para_static_delay_ctrl); dr_delayctrl_int <= para_static_delay_ctrl_gray WHEN (delayctrlout_mode = "static") ELSE dr_dllcount_in; -- model process(dr_clk8_in, dr_aload_in) begin if (dr_aload_in = '1' and dr_aload_in'event) then dr_reg_dllcount <= "000000"; elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then dr_reg_dllcount <= dr_delayctrl_int; end if; end process; -- Delay Setting Control Counter ------------------------------------------ --inputs dc_dlltolock_in <= dll_to_lock; dc_aload_in <= aload_in; dc_clk1_in <= cg_clk1_out; dc_clk8_in <= not cg_clk8b_out; dc_upndnclkena_in <= upndninclkena WHEN (para_use_upndninclkena = '1') ELSE jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE (not pc_lock) WHEN (dual_phase_comparators = "true") ELSE '1'; dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE pc_upndn_out; -- outputs dc_dllcount_out <= dc_reg_dllcount; -- needs to turn into gray counter -- dll counter logic process(dc_clk8_in, dc_aload_in, dc_dlltolock_in) variable dc_var_dllcount : integer := 64; variable init : boolean := true; begin if (init) then if (delay_buffer_mode = "low") then dc_var_dllcount := 32; else dc_var_dllcount := 16; end if; init := false; end if; if (dc_aload_in = '1' and dc_aload_in'event) then if (delay_buffer_mode = "low") then dc_var_dllcount := 32; else dc_var_dllcount := 16; end if; elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and dc_upndnclkena_in = '1' and para_use_upndnin = '0') then dc_var_dllcount := sim_valid_lockcount; dc_reg_dlltolock_pulse <= '1'; elsif (dc_aload_in /= '1' and dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk if (dc_upndn_in = '1') then if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or (para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then dc_var_dllcount := dc_var_dllcount + 1; end if; elsif (dc_upndn_in = '0') then if (dc_var_dllcount > 0) then dc_var_dllcount := dc_var_dllcount - 1; end if; end if; end if; -- rising clock -- schedule signal dc_reg_dllcount dc_reg_dllcount <= dc_var_dllcount; end process; -- Jitter reduction counter ----------------------------------------------- -- inputs jc_clk8_in <= not cg_clk8b_out; jc_upndn_in <= pc_upndn_out; jc_aload_in <= aload_in; -- new in hardcopyiii jc_clkena_in <= '1' WHEN (dual_phase_comparators = "false") ELSE (not pc_lock); -- outputs jc_upndn_out <= jc_reg_upndn; jc_upndnclkena_out <= jc_reg_upndnclkena; -- Model process (jc_clk8_in, jc_aload_in) begin if (jc_aload_in = '1' and jc_aload_in'event) then jc_count <= 8; elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then if (jc_clkena_in = '1') then if (jc_count = 12) then jc_reg_upndn <= '1'; jc_reg_upndnclkena <= '1'; jc_count <= 8; elsif (jc_count = 4) then jc_reg_upndn <= '0'; jc_reg_upndnclkena <= '1'; jc_count <= 8; else -- increment/decrement counter jc_reg_upndnclkena <= '0'; if (jc_upndn_in = '1') then jc_count <= jc_count + 1; elsif (jc_upndn_in = '0') then jc_count <= jc_count - 1; end if; end if; else -- not clkena jc_reg_upndnclkena <= '0'; end if; end if; end process; -- Phase comparator ------------------------------------------------------- -- inputs pc_clk1_in <= cg_clk1_out; pc_clk8_in <= cg_clk8b_out; -- positive pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation pc_aload_in <= aload_in; -- outputs pc_upndn_out <= pc_reg_upndn; pc_lock <= pc_lock_reg; -- parameter used -- sim_loop_intrinsic_delay, sim_loop_delay_increment pc_comp_range <= (3*delay_chain_length*sim_buffer_delay_increment)/2; -- Model process (pc_clk8_in, pc_aload_in) variable pc_var_delay : integer := 0; begin if (pc_aload_in = '1' and pc_aload_in'event) then pc_var_delay := 0; elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then pc_var_delay := delay_chain_length * (sim_buffer_intrinsic_delay + sim_buffer_delay_increment * pc_dllcount_in); pc_delay <= pc_var_delay; if (dual_phase_comparators = "false") then if (pc_var_delay > input_period) then pc_reg_upndn <= '0'; else pc_reg_upndn <= '1'; end if; else -- use dual phase if (pc_var_delay < (input_period - pc_comp_range/2)) then pc_reg_upndn <= '1'; pc_lock_reg <= '0'; elsif (pc_var_delay <= (input_period + pc_comp_range/2)) then pc_reg_upndn <= '0'; pc_lock_reg <= '1'; else pc_reg_upndn <= '0'; pc_lock_reg <= '0'; end if; end if; end if; end process; -- Clock Generator ------------------------------------------------------- -- inputs cg_clk_in <= clk_in; cg_aload_in <= aload_in; -- outputs cg_clk8a_out <= cg_rega_3; cg_clk8b_out <= cg_regb_3; cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in; -- Model process(cg_clk1_out, cg_aload_in) begin if (cg_aload_in = '1' and cg_aload_in'event) then cg_reg_1 <= '0'; elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then cg_reg_1 <= not cg_reg_1; end if; end process; process(cg_reg_1, cg_aload_in) begin if (cg_aload_in = '1' and cg_aload_in'event) then cg_rega_2 <= '0'; cg_regb_2 <= '1'; elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then cg_rega_2 <= not cg_rega_2; cg_regb_2 <= not cg_regb_2; end if; end process; process (cg_rega_2, cg_aload_in) begin if (cg_aload_in = '1' and cg_aload_in'event) then cg_rega_3 <= '0'; elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then cg_rega_3 <= not cg_rega_3; end if; end process; process (cg_regb_2, cg_aload_in) begin if (cg_aload_in = '1' and cg_aload_in'event) then cg_regb_3 <= '0'; elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then cg_regb_3 <= not cg_regb_3; end if; end process; -------------------- -- INPUT PATH DELAYS -------------------- WireDelay : block begin VitalWireDelay (clk_in, clk, tipd_clk); VitalWireDelay (aload_in_buf, aload, tipd_aload); VitalWireDelay (upndn_in, upndnin, tipd_upndnin); VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena); end block; ------------------------ -- Timing Check Section ------------------------ VITALtiming : process (clk_in, upndn_in, upndninclkena_in, delayctrl_out, offsetdelayctrl_out, dqsupdate_out, upndn_out) variable Tviol_upndnin_clk : std_ulogic := '0'; variable Tviol_upndninclkena_clk : std_ulogic := '0'; variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit; variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit; variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0); variable upndnout_VitalGlitchData : VitalGlitchDataType; begin if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_upndnin_clk, TimingData => TimingData_upndnin_clk, TestSignal => upndn_in, TestSignalName => "UPNDNIN", RefSignal => clk_in, RefSignalName => "CLK", SetupHigh => tsetup_upndnin_clk_noedge_posedge, SetupLow => tsetup_upndnin_clk_noedge_posedge, HoldHigh => thold_upndnin_clk_noedge_posedge, HoldLow => thold_upndnin_clk_noedge_posedge, RefTransition => '/', HeaderMsg => InstancePath & "/HARDCOPYIII_DLL", XOn => XOn, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_upndninclkena_clk, TimingData => TimingData_upndninclkena_clk, TestSignal => upndninclkena_in, TestSignalName => "UPNDNINCLKENA", RefSignal => clk_in, RefSignalName => "CLK", SetupHigh => tsetup_upndninclkena_clk_noedge_posedge, SetupLow => tsetup_upndninclkena_clk_noedge_posedge, HoldHigh => thold_upndninclkena_clk_noedge_posedge, HoldLow => thold_upndninclkena_clk_noedge_posedge, RefTransition => '/', HeaderMsg => InstancePath & "/HARDCOPYIII_DLL", XOn => XOn, MsgOn => MsgOnChecks ); end if; ---------------------- -- Path Delay Section ---------------------- offsetdelayctrlout <= offsetdelayctrl_out; dqsupdate <= dqsupdate_out; VitalPathDelay01 ( OutSignal => upndnout, OutSignalName => "UPNDNOUT", OutTemp => upndn_out, Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)), GlitchData => upndnout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => delayctrlout(0), OutSignalName => "DELAYCTRLOUT", OutTemp => delayctrl_out(0), Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE)), GlitchData => delayctrlout_VitalGlitchDataArray(0), Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => delayctrlout(1), OutSignalName => "DELAYCTRLOUT", OutTemp => delayctrl_out(1), Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(1), TRUE)), GlitchData => delayctrlout_VitalGlitchDataArray(1), Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => delayctrlout(2), OutSignalName => "DELAYCTRLOUT", OutTemp => delayctrl_out(2), Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(2), TRUE)), GlitchData => delayctrlout_VitalGlitchDataArray(2), Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => delayctrlout(3), OutSignalName => "DELAYCTRLOUT", OutTemp => delayctrl_out(3), Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(3), TRUE)), GlitchData => delayctrlout_VitalGlitchDataArray(3), Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => delayctrlout(4), OutSignalName => "DELAYCTRLOUT", OutTemp => delayctrl_out(4), Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(4), TRUE)), GlitchData => delayctrlout_VitalGlitchDataArray(4), Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => delayctrlout(5), OutSignalName => "DELAYCTRLOUT", OutTemp => delayctrl_out(5), Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(5), TRUE)), GlitchData => delayctrlout_VitalGlitchDataArray(5), Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; -- vital timing end vital_hcxdll; ------------------------------------------------------------------------------- -- -- Entity Name : HARDCOPYIII_dll_offset_ctrl -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; USE work.hardcopyiii_pllpack.all; use work.hardcopyiii_atom_ddr_pack.all; use work.hardcopyiii_dll_gray_encoder; use work.hardcopyiii_dll_gray_decoder; ENTITY hardcopyiii_dll_offset_ctrl is GENERIC ( use_offset : string := "false"; static_offset : string := "0"; delay_buffer_mode : string := "low"; lpm_type : string := "hardcopyiii_dll_offset_ctrl"; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_aload : VitalDelayType01 := DefpropDelay01; tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_addnsub : VitalDelayType01 := DefpropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst); thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst); tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01) ); PORT ( clk : IN std_logic := '0'; aload : IN std_logic := '0'; offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000"; offset : IN std_logic_vector(5 DOWNTO 0) := "000000"; addnsub : IN std_logic := '1'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '0'; offsettestout : OUT std_logic_vector(5 DOWNTO 0); offsetctrlout : OUT std_logic_vector(5 DOWNTO 0) ); END hardcopyiii_dll_offset_ctrl; ARCHITECTURE vital_hcxoffset of hardcopyiii_dll_offset_ctrl is COMPONENT hardcopyiii_dll_gray_encoder GENERIC ( width : integer := 6 ); PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0'); gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; COMPONENT hardcopyiii_dll_gray_decoder GENERIC ( width : integer := 6 ); PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0'); bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; signal clk_in : std_logic := '0'; signal aload_in : std_logic := '0'; signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000"; signal offsetdelayctrlin_in : std_logic_vector(5 DOWNTO 0) := "000000"; signal addnsub_in : std_logic := '0'; signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000"; signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01"; signal para_use_offset : std_logic := '0'; signal para_static_offset : integer := 0; signal para_static_offset_pos : integer := 0; -- INTERNAL NETS AND VARIABLES -- for functionality - by modules -- two reg on the de-assertion of aload SIGNAL aload_reg1 : std_logic := '1'; SIGNAL aload_reg2 : std_logic := '1'; -- delay and offset control out resolver signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000"; signal dr_offsettest_out : std_logic_vector (5 DOWNTO 0) := "000000"; signal dr_offsetctrl_out_gray : std_logic_vector (5 DOWNTO 0) := "000000"; signal dr_addnsub_in : std_logic := '1'; signal dr_clk8_in : std_logic := '0'; signal dr_aload_in : std_logic := '0'; signal dr_offset_in_gray : std_logic_vector (5 DOWNTO 0) := "000000"; signal dr_delayctrl_in_gray : std_logic_vector (5 DOWNTO 0) := "000000"; signal para_static_offset_vec_pos : std_logic_vector (5 DOWNTO 0) := "000000"; signal para_static_offset_gray : std_logic_vector (5 DOWNTO 0) := "000000"; -- signed in 2's complement -- docoder signal dr_delayctrl_in_bin : std_logic_vector (5 DOWNTO 0) := "000000"; signal dr_offset_in_bin : std_logic_vector (5 DOWNTO 0) := "000000"; signal dr_offset_in_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check signal para_static_offset_bin : std_logic_vector (5 DOWNTO 0) := "000000"; signal para_static_offset_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check signal dr_reg_offset : std_logic_vector (5 DOWNTO 0) := "000000"; begin -- paramters para_delay_buffer_mode <= "01" WHEN delay_buffer_mode = "low" ELSE "00"; para_use_offset <= '1' WHEN use_offset = "true" ELSE '0'; para_static_offset <= dqs_str2int(static_offset); -- signed int para_static_offset_pos <= para_static_offset WHEN (para_static_offset > 0) ELSE (-1)*para_static_offset; -- outputs offsetctrl_out <= dr_offsetctrl_out_gray; offsettestout <= dr_offsettest_out; -- two registers on aload path -------------------------------------------- -- it should be user clock to DLL, not the /8 clock of offsetctrl process(clk_in) begin if (clk_in = '0' and clk_in'event) then aload_reg2 <= aload_reg1; aload_reg1 <= aload_in; end if; end process; -- Delay and offset ctrl out resolver ------------------------------------- -- inputs dr_clk8_in <= clk_in; dr_addnsub_in <= addnsub_in; dr_aload_in <= aload_in; -- aload_in | aload_reg2; dr_delayctrl_in_gray <= offsetdelayctrlin_in; dr_offset_in_gray <= offset_in; para_static_offset_vec_pos <= dll_unsigned2bin(para_static_offset_pos); para_static_offset_gray <= ("111111" - para_static_offset_vec_pos + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_vec_pos; -- outputs dr_offsetctrl_out <= dr_reg_offset; moffsetctrl_out_enc : hardcopyiii_dll_gray_encoder GENERIC MAP (width => 6) PORT MAP (mbin => dr_reg_offset, gout => dr_offsetctrl_out_gray); dr_offsettest_out <= para_static_offset_gray WHEN (use_offset = "false") ELSE offset_in; -- model -- decoders mdr_delayctrl_in_dec : hardcopyiii_dll_gray_decoder GENERIC MAP (width => 6) PORT MAP (gin => dr_delayctrl_in_gray, bout => dr_delayctrl_in_bin); mdr_offset_in_dec : hardcopyiii_dll_gray_decoder GENERIC MAP (width => 6) PORT MAP (gin => dr_offset_in_gray, bout => dr_offset_in_bin); mpara_static_offset_dec : hardcopyiii_dll_gray_decoder GENERIC MAP (width => 6) PORT MAP (gin => para_static_offset_gray, bout => para_static_offset_bin); -- get postive value of decoded offset for over/underflow check para_static_offset_bin_pos <= ("111111" - para_static_offset_bin + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_bin; dr_offset_in_bin_pos <= ("111111" - dr_offset_in_bin + "000001") WHEN ((use_offset = "true") AND (addnsub_in = '0')) ELSE dr_offset_in_bin; -- generating dr_reg_offset process(dr_clk8_in, dr_aload_in) begin if (dr_aload_in = '1' and dr_aload_in'event) then dr_reg_offset <= "000000"; elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then if (use_offset = "true") then if (dr_addnsub_in = '1') then if (dr_delayctrl_in_bin < "111111" - dr_offset_in_bin) then dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin; else dr_reg_offset <= "111111"; end if; elsif (dr_addnsub_in = '0') then if (dr_delayctrl_in_bin > dr_offset_in_bin_pos) then dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin; -- same as - *_pos else dr_reg_offset <= "000000"; end if; end if; else if (para_static_offset >= 0) then -- do not use a + b < "11111" as it does not check overflow if ((para_static_offset_bin < "111111") AND (dr_delayctrl_in_bin < "111111" - para_static_offset_bin )) then dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin; else dr_reg_offset <= "111111"; end if; else if ((para_static_offset_bin_pos < "111111") AND (dr_delayctrl_in_bin > para_static_offset_bin_pos)) then dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin; -- same as - *_pos else dr_reg_offset <= "000000"; end if; end if; end if; end if; -- rising clock end process ; -- generating dr_reg_offset -------------------- -- INPUT PATH DELAYS -------------------- WireDelay : block begin VitalWireDelay (clk_in, clk, tipd_clk); VitalWireDelay (aload_in, aload, tipd_aload); VitalWireDelay (addnsub_in, addnsub, tipd_addnsub); VitalWireDelay (offset_in(0), offset(0), tipd_offset(0)); VitalWireDelay (offset_in(1), offset(1), tipd_offset(1)); VitalWireDelay (offset_in(2), offset(2), tipd_offset(2)); VitalWireDelay (offset_in(3), offset(3), tipd_offset(3)); VitalWireDelay (offset_in(4), offset(4), tipd_offset(4)); VitalWireDelay (offset_in(5), offset(5), tipd_offset(5)); VitalWireDelay (offsetdelayctrlin_in(0), offsetdelayctrlin(0), tipd_offsetdelayctrlin(0)); VitalWireDelay (offsetdelayctrlin_in(1), offsetdelayctrlin(1), tipd_offsetdelayctrlin(1)); VitalWireDelay (offsetdelayctrlin_in(2), offsetdelayctrlin(2), tipd_offsetdelayctrlin(2)); VitalWireDelay (offsetdelayctrlin_in(3), offsetdelayctrlin(3), tipd_offsetdelayctrlin(3)); VitalWireDelay (offsetdelayctrlin_in(4), offsetdelayctrlin(4), tipd_offsetdelayctrlin(4)); VitalWireDelay (offsetdelayctrlin_in(5), offsetdelayctrlin(5), tipd_offsetdelayctrlin(5)); end block; ------------------------ -- Timing Check Section ------------------------ VITALtiming : process (clk_in, offset_in, addnsub_in, offsetctrl_out) variable Tviol_offset_clk : std_ulogic := '0'; variable Tviol_addnsub_clk : std_ulogic := '0'; variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit; variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit; variable offsetctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0); begin if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_offset_clk, TimingData => TimingData_offset_clk, TestSignal => offset_in, TestSignalName => "OFFSET", RefSignal => clk_in, RefSignalName => "CLK", SetupHigh => tsetup_offset_clk_noedge_posedge(0), SetupLow => tsetup_offset_clk_noedge_posedge(0), HoldHigh => thold_offset_clk_noedge_posedge(0), HoldLow => thold_offset_clk_noedge_posedge(0), RefTransition => '/', HeaderMsg => InstancePath & "/HARDCOPYIII_OFFSETCTRL", XOn => XOn, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_addnsub_clk, TimingData => TimingData_addnsub_clk, TestSignal => addnsub_in, TestSignalName => "ADDNSUB", RefSignal => clk_in, RefSignalName => "CLK", SetupHigh => tsetup_addnsub_clk_noedge_posedge, SetupLow => tsetup_addnsub_clk_noedge_posedge, HoldHigh => thold_addnsub_clk_noedge_posedge, HoldLow => thold_addnsub_clk_noedge_posedge, RefTransition => '/', HeaderMsg => InstancePath & "/HARDCOPYIII_OFFSETCTRL", XOn => XOn, MsgOn => MsgOnChecks ); end if; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => offsetctrlout(0), OutSignalName => "offsetctrlOUT", OutTemp => offsetctrl_out(0), Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(0), TRUE)), GlitchData => offsetctrlout_VitalGlitchDataArray(0), Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => offsetctrlout(1), OutSignalName => "offsetctrlOUT", OutTemp => offsetctrl_out(1), Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(1), TRUE)), GlitchData => offsetctrlout_VitalGlitchDataArray(1), Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => offsetctrlout(2), OutSignalName => "offsetctrlOUT", OutTemp => offsetctrl_out(2), Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(2), TRUE)), GlitchData => offsetctrlout_VitalGlitchDataArray(2), Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => offsetctrlout(3), OutSignalName => "offsetctrlOUT", OutTemp => offsetctrl_out(3), Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(3), TRUE)), GlitchData => offsetctrlout_VitalGlitchDataArray(3), Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => offsetctrlout(4), OutSignalName => "offsetctrlOUT", OutTemp => offsetctrl_out(4), Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(4), TRUE)), GlitchData => offsetctrlout_VitalGlitchDataArray(4), Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => offsetctrlout(5), OutSignalName => "offsetctrlOUT", OutTemp => offsetctrl_out(5), Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(5), TRUE)), GlitchData => offsetctrlout_VitalGlitchDataArray(5), Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; -- vital timing end vital_hcxoffset; ------------------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_dqs_delay_chain -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; use work.hardcopyiii_dll_gray_decoder; ENTITY hardcopyiii_dqs_delay_chain IS GENERIC ( dqs_input_frequency : string := "unused" ; use_phasectrlin : string := "false"; phase_setting : integer := 0; delay_buffer_mode : string := "low"; dqs_phase_shift : integer := 0; dqs_offsetctrl_enable : string := "false"; dqs_ctrl_latches_enable : string := "false"; -- DFT added in WYS 1.33 test_enable : string := "false"; test_select : integer := 0; -- SIM only sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; lpm_type : string := "hardcopyiii_dqs_delay_chain"; tipd_dqsin : VitalDelayType01 := DefpropDelay01; tipd_aload : VitalDelayType01 := DefpropDelay01; tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01; tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01); tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01; tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst); thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst); tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst); thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst); TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( dqsin : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0'); offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0'); dqsupdateen : IN std_logic := '1'; phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0'); devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dqsbusout : OUT std_logic; dffin : OUT std_logic ); END; ARCHITECTURE hardcopyiii_dqs_delay_chain_arch OF hardcopyiii_dqs_delay_chain IS -- component section COMPONENT hardcopyiii_dll_gray_decoder GENERIC ( width : integer := 6 ); PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0'); bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; -- signal section SIGNAL delayctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0'); SIGNAL offsetctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0'); -- offsetctrl after "dqs_offsetctrl_enable" mux SIGNAL offsetctrl_mux : std_logic_vector(5 downto 0) := (OTHERS => '0'); -- reged outputs of delay count SIGNAL delayctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1'); SIGNAL offsetctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1'); -- delay count after latch enable mux SIGNAL delayctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0'); SIGNAL offsetctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0'); -- timing outputs SIGNAL tmp_dqsbusout : STD_LOGIC := '0'; SIGNAL dqs_delay : INTEGER := 0; -- timing inputs SIGNAL dqsin_in : std_logic := '0'; SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0'); SIGNAL offsetctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0'); SIGNAL dqsupdateen_in : std_logic := '1'; SIGNAL phasectrlin_in : std_logic_vector(2 downto 0) := (OTHERS => '0'); SIGNAL test_bus : std_logic_vector(12 downto 0); SIGNAL test_lpbk : std_logic; SIGNAL tmp_dqsin : std_logic; BEGIN PROCESS(dqsupdateen_in) BEGIN IF (dqsupdateen_in = '1') THEN delayctrl_reg <= delayctrlin_in; offsetctrl_reg <= offsetctrl_mux; END IF; END PROCESS; offsetctrl_mux <= offsetctrlin_in WHEN (dqs_offsetctrl_enable = "true") ELSE delayctrlin_in; -- mux after reg delayctrl_reg_mux <= delayctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE delayctrlin_in; offsetctrl_reg_mux <= offsetctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE offsetctrl_mux; mdelayctrlin_dec : hardcopyiii_dll_gray_decoder GENERIC MAP (width => 6) PORT MAP (gin => delayctrl_reg_mux, bout => delayctrl_bin); moffsetctrlin_dec : hardcopyiii_dll_gray_decoder GENERIC MAP (width => 6) PORT MAP (gin => offsetctrl_reg_mux, bout => offsetctrl_bin); PROCESS (delayctrl_bin, offsetctrl_bin, phasectrlin_in) variable sim_intrinsic_delay : INTEGER := 0; variable tmp_delayctrl : std_logic_vector(5 downto 0) := (OTHERS => '0'); variable tmp_offsetctrl : std_logic_vector(5 downto 0) := (OTHERS => '0'); variable acell_delay : INTEGER := 0; variable aoffsetcell_delay : INTEGER := 0; variable delay_chain_len : INTEGER := 0; BEGIN IF (delay_buffer_mode = "low") THEN sim_intrinsic_delay := sim_low_buffer_intrinsic_delay; ELSE sim_intrinsic_delay := sim_high_buffer_intrinsic_delay; END IF; IF (delay_buffer_mode = "high" AND delayctrl_bin(5) = '1') THEN tmp_delayctrl := "011111"; ELSE tmp_delayctrl := delayctrl_bin; END IF; IF (delay_buffer_mode = "high" AND offsetctrl_bin(5) = '1') THEN tmp_offsetctrl := "011111"; ELSE tmp_offsetctrl := offsetctrl_bin; END IF; -- cell acell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_delayctrl) * sim_buffer_delay_increment; IF (dqs_offsetctrl_enable = "true") THEN aoffsetcell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_offsetctrl)*sim_buffer_delay_increment; ELSE aoffsetcell_delay := acell_delay; END IF; -- no of cells IF (use_phasectrlin = "false") THEN delay_chain_len := phase_setting; ELSIF (phasectrlin_in(2) = '1') THEN delay_chain_len := 0; ELSE delay_chain_len := alt_conv_integer(phasectrlin_in) + 1; END IF; -- total delay IF (delay_chain_len = 0) THEN dqs_delay <= 0; ELSE dqs_delay <= (delay_chain_len - 1)*acell_delay + aoffsetcell_delay; END IF; END PROCESS; -- generating delays -- test bus loopback test_bus <= (not dqsupdateen_in) & offsetctrl_reg_mux & delayctrl_reg_mux; test_lpbk <= test_bus(test_select) WHEN ((0 <= test_select) AND (test_select <= 12)) ELSE 'Z'; tmp_dqsin <= (test_lpbk AND dqsin) WHEN (test_enable = "true") ELSE dqsin_in; tmp_dqsbusout <= transport tmp_dqsin after (dqs_delay * 1 ps); -------------------- -- INPUT PATH DELAYS -------------------- WireDelay : block begin VitalWireDelay (dqsin_in, dqsin, tipd_dqsin); loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i)); END GENERATE; loopbits_offsetctrlin : FOR i in offsetctrlin'RANGE GENERATE VitalWireDelay (offsetctrlin_in(i), offsetctrlin(i), tipd_offsetctrlin(i)); END GENERATE; VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen); loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i)); END GENERATE; end block; ----------------------------------- -- Timing Check Section ----------------------------------- VITAL_timing_check: PROCESS (dqsupdateen_in,offsetctrlin_in,delayctrlin_in) variable Tviol_dqsupdateen_offsetctrlin : std_ulogic := '0'; variable TimingData_dqsupdateen_offsetctrlin : VitalTimingDataType := VitalTimingDataInit; variable Tviol_dqsupdateen_delayctrlin : std_ulogic := '0'; variable TimingData_dqsupdateen_delayctrlin : VitalTimingDataType := VitalTimingDataInit; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( Violation => Tviol_dqsupdateen_offsetctrlin, TimingData => TimingData_dqsupdateen_offsetctrlin, TestSignal => offsetctrlin_in, TestSignalName => "offsetctrlin", RefSignal => dqsupdateen_in, RefSignalName => "dqsupdateen", SetupHigh => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0), SetupLow => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0), HoldHigh => thold_offsetctrlin_dqsupdateen_noedge_posedge(0), HoldLow => thold_offsetctrlin_dqsupdateen_noedge_posedge(0), RefTransition => '/', HeaderMsg => InstancePath & "/HARDCOPYIII_DQS_DELAY_CHAIN", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_dqsupdateen_delayctrlin, TimingData => TimingData_dqsupdateen_delayctrlin, TestSignal => delayctrlin_in, TestSignalName => "delayctrlin", RefSignal => dqsupdateen_in, RefSignalName => "dqsupdateen", SetupHigh => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0), SetupLow => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0), HoldHigh => thold_delayctrlin_dqsupdateen_noedge_posedge(0), HoldLow => thold_delayctrlin_dqsupdateen_noedge_posedge(0), RefTransition => '/', HeaderMsg => InstancePath & "/HARDCOPYIII_DQS_DELAY_CHAIN", XOn => XOnChecks, MsgOn => MsgOnChecks ); END IF; END PROCESS; -- timing check -------------------------------------- -- Path Delay Section -------------------------------------- VITAL_path_delays: PROCESS (tmp_dqsbusout) variable dqsbusout_VitalGlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => dqsbusout, OutSignalName => "dqsbusout", OutTemp => tmp_dqsbusout, Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE)), GlitchData => dqsbusout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); END PROCESS; -- Path Delays END hardcopyiii_dqs_delay_chain_arch; ------------------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_dqs_enable -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_dqs_enable IS GENERIC ( lpm_type : string := "hardcopyiii_dqs_enable"; tipd_dqsin : VitalDelayType01 := DefpropDelay01; tipd_dqsenable : VitalDelayType01 := DefpropDelay01; tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01; tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( dqsin : IN std_logic := '0'; dqsenable : IN std_logic := '1'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dqsbusout : OUT std_logic ); END; ARCHITECTURE hardcopyiii_dqs_enable_arch OF hardcopyiii_dqs_enable IS -- component section -- signal section SIGNAL ena_reg : STD_LOGIC := '1'; -- timing output SIGNAL tmp_dqsbusout : std_logic := '0'; -- timing input SIGNAL dqsin_in : std_logic := '0'; SIGNAL dqsenable_in : std_logic := '1'; BEGIN tmp_dqsbusout <= ena_reg AND dqsin_in; PROCESS(tmp_dqsbusout, dqsenable_in) BEGIN IF (dqsenable_in = '1') THEN ena_reg <= '1'; ELSIF (tmp_dqsbusout'event AND tmp_dqsbusout = '0') THEN ena_reg <= '0'; END IF; END PROCESS; -------------------- -- INPUT PATH DELAYS -------------------- WireDelay : block begin VitalWireDelay (dqsin_in, dqsin, tipd_dqsin); VitalWireDelay (dqsenable_in, dqsenable, tipd_dqsenable); end block; -------------------------------------- -- Path Delay Section -------------------------------------- VITAL_path_delays: PROCESS (tmp_dqsbusout) variable dqsbusout_VitalGlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => dqsbusout, OutSignalName => "dqsbusout", OutTemp => tmp_dqsbusout, Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE), 1 => (dqsenable_in'last_event, tpd_dqsenable_dqsbusout, TRUE)), GlitchData => dqsbusout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); END PROCESS; -- Path Delays END hardcopyiii_dqs_enable_arch; ------------------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_dqs_enable_ctrl -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; use work.hardcopyiii_ddr_io_reg; use work.hardcopyiii_ddr_delay_chain_s; ENTITY hardcopyiii_dqs_enable_ctrl IS GENERIC ( use_phasectrlin : string := "true"; phase_setting : integer := 0; delay_buffer_mode : string := "high"; level_dqs_enable : string := "false"; delay_dqs_enable_by_half_cycle : string := "false"; add_phase_transfer_reg : string := "false"; invert_phase : string := "false"; sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; lpm_type : string := "hardcopyiii_dqs_enable_ctrl"; tipd_dqsenablein : VitalDelayType01 := DefpropDelay01; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01; tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( dqsenablein : IN std_logic := '1'; clk : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0'); phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0'); enaphasetransferreg : IN std_logic := '0'; phaseinvertctrl : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dqsenableout : OUT std_logic; dffin : OUT std_logic; dffextenddqsenable : OUT std_logic ); END; ARCHITECTURE hardcopyiii_dqs_enable_ctrl_arch OF hardcopyiii_dqs_enable_ctrl IS -- component section COMPONENT hardcopyiii_ddr_delay_chain_s GENERIC ( use_phasectrlin : string := "true"; phase_setting : integer := 0; delay_buffer_mode : string := "high"; sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; phasectrlin_limit : integer := 7 ); PORT ( clk : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0'); phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); delayed_clkout : OUT std_logic ); END COMPONENT; component hardcopyiii_ddr_io_reg generic ( power_up : string := "DONT_CARE"; is_wysiwyg : string := "false"; x_on_violation : string := "on"; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_asdata_q: VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_d : VitalDelayType01 := DefPropDelay01; tipd_asdata : VitalDelayType01 := DefPropDelay01; tipd_sclr : VitalDelayType01 := DefPropDelay01; tipd_sload : VitalDelayType01 := DefPropDelay01; tipd_clrn : VitalDelayType01 := DefPropDelay01; tipd_prn : VitalDelayType01 := DefPropDelay01; tipd_aload : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; InstancePath: STRING := "*" ); port ( d : in std_logic := '0'; clk : in std_logic := '0'; ena : in std_logic := '1'; clrn : in std_logic := '1'; prn : in std_logic := '1'; aload : in std_logic := '0'; asdata : in std_logic := '0'; sclr : in std_logic := '0'; sload : in std_logic := '0'; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; q : out std_logic ); end component; -- int signals SIGNAL phasectrl_clkout : std_logic := '0'; SIGNAL delayed_clk : std_logic := '0'; SIGNAL dqsenablein_reg_q : std_logic := '0'; SIGNAL dqsenablein_level_ena : std_logic := '0'; -- transfer delay SIGNAL dqsenablein_reg_dly : std_logic := '0'; SIGNAL phasetransferdelay_mux_out : std_logic := '0'; SIGNAL dqsenable_delayed_regp : std_logic := '0'; SIGNAL dqsenable_delayed_regn : std_logic := '0'; SIGNAL m_vcc : std_logic := '1'; SIGNAL m_gnd : std_logic := '0'; SIGNAL not_clk_in : std_logic := '1'; SIGNAL not_delayed_clk : std_logic := '1'; -- timing output SIGNAL tmp_dqsenableout : std_logic := '1'; -- timing input SIGNAL dqsenablein_in : std_logic := '1'; SIGNAL clk_in : std_logic := '0'; SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0'); SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0'); SIGNAL enaphasetransferreg_in : std_logic := '0'; SIGNAL phaseinvertctrl_in : std_logic := '0'; BEGIN -- delay chain m_delay_chain : hardcopyiii_ddr_delay_chain_s GENERIC MAP ( phase_setting => phase_setting, use_phasectrlin => use_phasectrlin, delay_buffer_mode => delay_buffer_mode, sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay, sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay, sim_buffer_delay_increment => sim_buffer_delay_increment ) PORT MAP( clk => clk_in, delayctrlin => delayctrlin_in, phasectrlin => phasectrlin_in, delayed_clkout => phasectrl_clkout ); delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE phasectrl_clkout WHEN (invert_phase = "false") ELSE (not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE phasectrl_clkout; not_clk_in <= not clk_in; not_delayed_clk <= not delayed_clk; dqsenablein_reg : hardcopyiii_ddr_io_reg PORT MAP( d => dqsenablein_in, clk => clk_in, ena => m_vcc, clrn => m_vcc, prn => m_vcc, aload => m_gnd, asdata => m_gnd, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => dqsenablein_reg_q ); dqsenable_transfer_reg : hardcopyiii_ddr_io_reg PORT MAP ( d => dqsenablein_reg_q, clk => not_delayed_clk, ena => m_vcc, clrn => m_vcc, prn => m_vcc, aload => m_gnd, asdata => m_gnd, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => dqsenablein_reg_dly ); -- add phase transfer mux phasetransferdelay_mux_out <= dqsenablein_reg_dly WHEN (add_phase_transfer_reg = "true") ELSE dqsenablein_reg_q WHEN (add_phase_transfer_reg = "false") ELSE dqsenablein_reg_dly WHEN (enaphasetransferreg_in = '1') ELSE dqsenablein_reg_q; dqsenablein_level_ena <= phasetransferdelay_mux_out WHEN (level_dqs_enable = "true") ELSE dqsenablein_in; dqsenableout_reg : hardcopyiii_ddr_io_reg PORT MAP( d => dqsenablein_level_ena, clk => delayed_clk, ena => m_vcc, clrn => m_vcc, prn => m_vcc, aload => m_gnd, asdata => m_gnd, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => dqsenable_delayed_regp ); dqsenableout_extend_reg : hardcopyiii_ddr_io_reg PORT MAP( d => dqsenable_delayed_regp, clk => not_delayed_clk, ena => m_vcc, clrn => m_vcc, prn => m_vcc, aload => m_gnd, asdata => m_gnd, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => dqsenable_delayed_regn ); tmp_dqsenableout <= dqsenable_delayed_regp WHEN (delay_dqs_enable_by_half_cycle = "false") ELSE (dqsenable_delayed_regp AND dqsenable_delayed_regn); dqsenableout <= tmp_dqsenableout; -------------------- -- INPUT PATH DELAYS -------------------- WireDelay : block begin VitalWireDelay (dqsenablein_in, dqsenablein, tipd_dqsenablein); VitalWireDelay (clk_in, clk, tipd_clk); loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i)); END GENERATE; loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i)); END GENERATE; VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg); VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl); end block; END hardcopyiii_dqs_enable_ctrl_arch; ------------------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_delay_chain -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_delay_chain IS GENERIC ( sim_delayctrlin_rising_delay_0 : integer := 0; sim_delayctrlin_rising_delay_1 : integer := 50; sim_delayctrlin_rising_delay_2 : integer := 100; sim_delayctrlin_rising_delay_3 : integer := 150; sim_delayctrlin_rising_delay_4 : integer := 200; sim_delayctrlin_rising_delay_5 : integer := 250; sim_delayctrlin_rising_delay_6 : integer := 300; sim_delayctrlin_rising_delay_7 : integer := 350; sim_delayctrlin_rising_delay_8 : integer := 400; sim_delayctrlin_rising_delay_9 : integer := 450; sim_delayctrlin_rising_delay_10 : integer := 500; sim_delayctrlin_rising_delay_11 : integer := 550; sim_delayctrlin_rising_delay_12 : integer := 600; sim_delayctrlin_rising_delay_13 : integer := 650; sim_delayctrlin_rising_delay_14 : integer := 700; sim_delayctrlin_rising_delay_15 : integer := 750; sim_delayctrlin_falling_delay_0 : integer := 0; sim_delayctrlin_falling_delay_1 : integer := 50; sim_delayctrlin_falling_delay_2 : integer := 100; sim_delayctrlin_falling_delay_3 : integer := 150; sim_delayctrlin_falling_delay_4 : integer := 200; sim_delayctrlin_falling_delay_5 : integer := 250; sim_delayctrlin_falling_delay_6 : integer := 300; sim_delayctrlin_falling_delay_7 : integer := 350; sim_delayctrlin_falling_delay_8 : integer := 400; sim_delayctrlin_falling_delay_9 : integer := 450; sim_delayctrlin_falling_delay_10 : integer := 500; sim_delayctrlin_falling_delay_11 : integer := 550; sim_delayctrlin_falling_delay_12 : integer := 600; sim_delayctrlin_falling_delay_13 : integer := 650; sim_delayctrlin_falling_delay_14 : integer := 700; sim_delayctrlin_falling_delay_15 : integer := 750; use_delayctrlin : string := "true"; delay_setting : integer := 0; -- new in STRATIXIV ww30.2008 sim_finedelayctrlin_falling_delay_0 : integer := 0; sim_finedelayctrlin_falling_delay_1 : integer := 25; sim_finedelayctrlin_rising_delay_0 : integer := 0; sim_finedelayctrlin_rising_delay_1 : integer := 25; use_finedelayctrlin : string := "false"; lpm_type : string := "hardcopyiii_delay_chain"; tipd_datain : VitalDelayType01 := DefpropDelay01; tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); tpd_datain_dataout : VitalDelayType01 := DefPropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( datain : IN std_logic := '0'; delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0'); finedelayctrlin : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dataout : OUT std_logic ); END; ARCHITECTURE hardcopyiii_delay_chain_arch OF hardcopyiii_delay_chain IS -- type def type delay_chain_int_vec is array (natural range <>) of integer; -- component section -- signal section SIGNAL rising_dly : INTEGER := 0; SIGNAL falling_dly : INTEGER := 0; SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); SIGNAL finedelayctrlin_in : STD_LOGIC := '0'; -- timing inputs SIGNAL tmp_dataout : std_logic := '0'; -- timing inputs SIGNAL datain_in : std_logic := '0'; BEGIN -- filtering X/U etc. delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0'; delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0'; delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0'; delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0'; finedelayctrlin_in <= '1' WHEN (finedelayctrlin = '1') ELSE '0'; -- generate dynamic delay table and dynamic delay process(delayctrlin_in, finedelayctrlin_in) variable init : boolean := true; variable dly_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0); variable dly_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0); variable finedly_table_rising : delay_chain_int_vec(1 downto 0) := (OTHERS => 0); variable finedly_table_falling : delay_chain_int_vec(1 downto 0) := (OTHERS => 0); variable dly_setting : integer := 0; variable finedly_setting : integer := 0; begin if (init) then dly_table_rising(0) := sim_delayctrlin_rising_delay_0; dly_table_rising(1) := sim_delayctrlin_rising_delay_1; dly_table_rising(2) := sim_delayctrlin_rising_delay_2; dly_table_rising(3) := sim_delayctrlin_rising_delay_3; dly_table_rising(4) := sim_delayctrlin_rising_delay_4; dly_table_rising(5) := sim_delayctrlin_rising_delay_5; dly_table_rising(6) := sim_delayctrlin_rising_delay_6; dly_table_rising(7) := sim_delayctrlin_rising_delay_7; dly_table_rising(8) := sim_delayctrlin_rising_delay_8; dly_table_rising(9) := sim_delayctrlin_rising_delay_9; dly_table_rising(10) := sim_delayctrlin_rising_delay_10; dly_table_rising(11) := sim_delayctrlin_rising_delay_11; dly_table_rising(12) := sim_delayctrlin_rising_delay_12; dly_table_rising(13) := sim_delayctrlin_rising_delay_13; dly_table_rising(14) := sim_delayctrlin_rising_delay_14; dly_table_rising(15) := sim_delayctrlin_rising_delay_15; dly_table_falling(0) := sim_delayctrlin_falling_delay_0; dly_table_falling(1) := sim_delayctrlin_falling_delay_1; dly_table_falling(2) := sim_delayctrlin_falling_delay_2; dly_table_falling(3) := sim_delayctrlin_falling_delay_3; dly_table_falling(4) := sim_delayctrlin_falling_delay_4; dly_table_falling(5) := sim_delayctrlin_falling_delay_5; dly_table_falling(6) := sim_delayctrlin_falling_delay_6; dly_table_falling(7) := sim_delayctrlin_falling_delay_7; dly_table_falling(8) := sim_delayctrlin_falling_delay_8; dly_table_falling(9) := sim_delayctrlin_falling_delay_9; dly_table_falling(10) := sim_delayctrlin_falling_delay_10; dly_table_falling(11) := sim_delayctrlin_falling_delay_11; dly_table_falling(12) := sim_delayctrlin_falling_delay_12; dly_table_falling(13) := sim_delayctrlin_falling_delay_13; dly_table_falling(14) := sim_delayctrlin_falling_delay_14; dly_table_falling(15) := sim_delayctrlin_falling_delay_15; finedly_table_rising(0) := sim_finedelayctrlin_rising_delay_0; finedly_table_rising(1) := sim_finedelayctrlin_rising_delay_1; finedly_table_falling(0) := sim_finedelayctrlin_falling_delay_0; finedly_table_falling(1) := sim_finedelayctrlin_falling_delay_1; init := false; end if; IF (use_delayctrlin = "false") THEN dly_setting := delay_setting; ELSE dly_setting := alt_conv_integer(delayctrlin_in); END IF; IF (finedelayctrlin_in = '1') THEN finedly_setting := 1; ELSE finedly_setting := 0; END IF; IF (use_finedelayctrlin = "true") THEN rising_dly <= dly_table_rising(dly_setting) + finedly_table_rising(finedly_setting); falling_dly <= dly_table_falling(dly_setting) + finedly_table_falling(finedly_setting); ELSE rising_dly <= dly_table_rising(dly_setting); falling_dly <= dly_table_falling(dly_setting); END IF; end process; -- generating dynamic delays PROCESS(datain_in) BEGIN if (datain_in = '0') then tmp_dataout <= transport datain_in after (falling_dly * 1 ps); else tmp_dataout <= transport datain_in after (rising_dly * 1 ps); end if; END PROCESS; ---------------------------------- -- Path Delay Section ---------------------------------- VITAL: process(tmp_dataout) variable dataout_VitalGlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => dataout, OutSignalName => "dataout", OutTemp => tmp_dataout, Paths => (0 => (datain_in'last_event, tpd_datain_dataout, TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; -------------------- -- INPUT PATH DELAYS -------------------- WireDelay : block begin VitalWireDelay (datain_in, datain, tipd_datain); end block; END hardcopyiii_delay_chain_arch; ------------------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_io_clock_divider -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; use work.hardcopyiii_ddr_delay_chain_s; ENTITY hardcopyiii_io_clock_divider IS GENERIC ( use_phasectrlin : string := "true"; phase_setting : integer := 0; delay_buffer_mode : string := "high"; use_masterin : string := "false"; invert_phase : string := "false"; sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; lpm_type : string := "hardcopyiii_io_clock_divider"; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_phaseselect : VitalDelayType01 := DefpropDelay01; tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01; tipd_masterin : VitalDelayType01 := DefpropDelay01; tpd_clk_clkout : VitalDelayType01 := DefPropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( clk : IN std_logic := '0'; phaseselect : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0'); phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0'); phaseinvertctrl : IN std_logic := '0'; masterin : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; clkout : OUT std_logic; slaveout : OUT std_logic ); END; ARCHITECTURE hardcopyiii_io_clock_divider_arch OF hardcopyiii_io_clock_divider IS -- component section COMPONENT hardcopyiii_ddr_delay_chain_s GENERIC ( use_phasectrlin : string := "true"; phase_setting : integer := 0; delay_buffer_mode : string := "high"; sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; phasectrlin_limit : integer := 7 ); PORT ( clk : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0'); phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); delayed_clkout : OUT std_logic ); END COMPONENT; -- int signals SIGNAL phasectrl_clkout : STD_LOGIC := '0'; SIGNAL delayed_clk : STD_LOGIC := '0'; SIGNAL divided_clk_in : STD_LOGIC := '0'; SIGNAL divided_clk : STD_LOGIC := '0'; -- timing outputs SIGNAL tmp_clkout : STD_LOGIC := '0'; -- timing inputs SIGNAL clk_in : std_logic := '0'; SIGNAL phaseselect_in : std_logic := '0'; SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0'); SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0'); SIGNAL phaseinvertctrl_in : std_logic := '0'; SIGNAL masterin_in : std_logic := '0'; BEGIN -- delay chain m_delay_chain : hardcopyiii_ddr_delay_chain_s GENERIC MAP ( phase_setting => phase_setting, use_phasectrlin => use_phasectrlin, delay_buffer_mode => delay_buffer_mode, sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay, sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay, sim_buffer_delay_increment => sim_buffer_delay_increment ) PORT MAP( clk => clk_in, delayctrlin => delayctrlin_in, phasectrlin => phasectrlin_in, delayed_clkout => phasectrl_clkout ); delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE phasectrl_clkout WHEN (invert_phase = "false") ELSE (not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE phasectrl_clkout; divided_clk_in <= masterin_in WHEN (use_masterin = "true") ELSE divided_clk; PROCESS (delayed_clk) BEGIN if (delayed_clk = '1') then divided_clk <= not divided_clk_in; end if; END PROCESS; tmp_clkout <= (not divided_clk) WHEN (phaseselect_in = '1') ELSE divided_clk; slaveout <= divided_clk; ---------------------------------- -- Path Delay Section ---------------------------------- VITAL: process(tmp_clkout) variable clkout_VitalGlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => clkout, OutSignalName => "clkout", OutTemp => tmp_clkout, Paths => (0 => (clk_in'last_event, tpd_clk_clkout, TRUE)), GlitchData => clkout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; -------------------- -- INPUT PATH DELAYS -------------------- WireDelay : block begin VitalWireDelay (clk_in, clk, tipd_clk); VitalWireDelay (phaseselect_in, phaseselect, tipd_phaseselect); loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i)); END GENERATE; loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i)); END GENERATE; VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl); VitalWireDelay (masterin_in, masterin, tipd_masterin); end block; END hardcopyiii_io_clock_divider_arch; ------------------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_output_phase_alignment -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; use work.hardcopyiii_ddr_io_reg; use work.hardcopyiii_ddr_delay_chain_s; ENTITY hardcopyiii_output_phase_alignment IS GENERIC ( operation_mode : string := "ddio_out"; use_phasectrlin : string := "true"; phase_setting : integer := 0; delay_buffer_mode : string := "high"; power_up : string := "low"; async_mode : string := "none"; sync_mode : string := "none"; add_output_cycle_delay : string := "false"; use_delayed_clock : string := "false"; add_phase_transfer_reg : string := "false"; use_phasectrl_clock : string := "true"; use_primary_clock : string := "true"; invert_phase : string := "false"; bypass_input_register : string := "false"; phase_setting_for_delayed_clock : integer := 2; sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; -- new in STRATIXIV: ww30.2008 duty_cycle_delay_mode : string := "none"; sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ; sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ; sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ; sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ; sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ; sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ; sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ; sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ; sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ; sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ; sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ; sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ; sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ; sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ; sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ; sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ; sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ; sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ; sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ; sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ; sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ; sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ; sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ; sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ; sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ; sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ; sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ; sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ; sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ; sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ; sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ; sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ; lpm_type : string := "hardcopyiii_output_phase_alignment"; tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); tipd_areset : VitalDelayType01 := DefpropDelay01; tipd_sreset : VitalDelayType01 := DefpropDelay01; tipd_clkena : VitalDelayType01 := DefpropDelay01; tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01; tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01; tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0'); clk : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0'); phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0'); areset : IN std_logic := '0'; sreset : IN std_logic := '0'; clkena : IN std_logic := '1'; enaoutputcycledelay : IN std_logic := '0'; enaphasetransferreg : IN std_logic := '0'; phaseinvertctrl : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008 dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0'); dataout : OUT std_logic; dffin : OUT std_logic_vector(1 downto 0); dff1t : OUT std_logic_vector(1 downto 0); dffddiodataout : OUT std_logic ); END; ARCHITECTURE hardcopyiii_output_phase_alignment_arch OF hardcopyiii_output_phase_alignment IS -- type def type delay_chain_int_vec is array (natural range <>) of integer; -- component section COMPONENT hardcopyiii_ddr_delay_chain_s GENERIC ( use_phasectrlin : string := "true"; phase_setting : integer := 0; delay_buffer_mode : string := "high"; sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; phasectrlin_limit : integer := 7 ); PORT ( clk : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0'); phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); delayed_clkout : OUT std_logic ); END COMPONENT; component hardcopyiii_ddr_io_reg generic ( power_up : string := "DONT_CARE"; is_wysiwyg : string := "false"; x_on_violation : string := "on"; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_asdata_q: VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_d : VitalDelayType01 := DefPropDelay01; tipd_asdata : VitalDelayType01 := DefPropDelay01; tipd_sclr : VitalDelayType01 := DefPropDelay01; tipd_sload : VitalDelayType01 := DefPropDelay01; tipd_clrn : VitalDelayType01 := DefPropDelay01; tipd_prn : VitalDelayType01 := DefPropDelay01; tipd_aload : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; InstancePath: STRING := "*" ); port ( d : in std_logic := '0'; clk : in std_logic := '0'; ena : in std_logic := '1'; clrn : in std_logic := '1'; prn : in std_logic := '1'; aload : in std_logic := '0'; asdata : in std_logic := '0'; sclr : in std_logic := '0'; sload : in std_logic := '0'; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; q : out std_logic ); end component; -- int signals on clock paths SIGNAL clk_in_delayed: STD_LOGIC := '0'; SIGNAL clk_in_mux: STD_LOGIC := '0'; SIGNAL phasectrl_clkout: STD_LOGIC := '0'; SIGNAL phaseinvertctrl_out: STD_LOGIC := '0'; SIGNAL m_vcc: STD_LOGIC := '1'; SIGNAL m_gnd: STD_LOGIC := '0'; -- IO registers -- common SIGNAL adatasdata_in_r : STD_LOGIC := '0'; -- sync reset - common for transfer and output reg SIGNAL sclr_in_r : STD_LOGIC := '0'; SIGNAL sload_in_r : STD_LOGIC := '0'; SIGNAL sclr_in : STD_LOGIC := '0'; SIGNAL sload_in : STD_LOGIC := '0'; SIGNAL adatasdata_in : STD_LOGIC := '0'; SIGNAL clrn_in_r : STD_LOGIC := '1'; -- async reset - common for all registers SIGNAL prn_in_r : STD_LOGIC := '1'; SIGNAL datain_q: STD_LOGIC := '0'; SIGNAL ddio_datain_q: STD_LOGIC := '0'; SIGNAL cycledelay_q: STD_LOGIC := '0'; SIGNAL ddio_cycledelay_q: STD_LOGIC := '0'; SIGNAL cycledelay_mux_out: STD_LOGIC := '0'; SIGNAL ddio_cycledelay_mux_out: STD_LOGIC := '0'; SIGNAL bypass_input_reg_mux_out : STD_LOGIC := '0'; SIGNAL ddio_bypass_input_reg_mux_out : STD_LOGIC := '0'; SIGNAL not_clk_in_mux: STD_LOGIC := '0'; SIGNAL ddio_out_clk_mux: STD_LOGIC := '0'; SIGNAL ddio_out_lo_q: STD_LOGIC := '0'; SIGNAL ddio_out_hi_q: STD_LOGIC := '0'; -- transfer delay now by negative clk SIGNAL transfer_q: STD_LOGIC := '0'; SIGNAL ddio_transfer_q: STD_LOGIC := '0'; -- Duty Cycle Delay SIGNAL dcd_in : STD_LOGIC := '0'; SIGNAL dcd_out : STD_LOGIC := '0'; SIGNAL dcd_both : STD_LOGIC := '0'; SIGNAL dcd_both_gnd : STD_LOGIC := '0'; SIGNAL dcd_both_vcc : STD_LOGIC := '0'; SIGNAL dcd_fallnrise : STD_LOGIC := '0'; SIGNAL dcd_fallnrise_gnd : STD_LOGIC := '0'; SIGNAL dcd_fallnrise_vcc : STD_LOGIC := '0'; SIGNAL dcd_rising_dly : INTEGER := 0; SIGNAL dcd_falling_dly : INTEGER := 0; SIGNAL dlyclk_clk: STD_LOGIC := '0'; SIGNAL dlyclk_d: STD_LOGIC := '0'; SIGNAL dlyclk_q: STD_LOGIC := '0'; SIGNAL ddio_dlyclk_d: STD_LOGIC := '0'; SIGNAL ddio_dlyclk_q: STD_LOGIC := '0'; SIGNAL dlyclk_clkena_in: STD_LOGIC := '0'; -- shared SIGNAL dlyclk_extended_q: STD_LOGIC := '0'; SIGNAL dlyclk_extended_clk: STD_LOGIC := '0'; SIGNAL normal_dataout: STD_LOGIC := '0'; SIGNAL extended_dataout: STD_LOGIC := '0'; SIGNAL ddio_dataout: STD_LOGIC := '0'; SIGNAL tmp_dataout: STD_LOGIC := '0'; -- timing inputs SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0'); SIGNAL clk_in : std_logic := '0'; SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0'); SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0'); SIGNAL areset_in : std_logic := '0'; SIGNAL sreset_in : std_logic := '0'; SIGNAL clkena_in : std_logic := '1'; SIGNAL enaoutputcycledelay_in : std_logic := '0'; SIGNAL enaphasetransferreg_in : std_logic := '0'; SIGNAL phaseinvertctrl_in : std_logic := '0'; SIGNAL delaymode_in: std_logic := '0'; SIGNAL dutycycledelayctrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0'); BEGIN -- filtering X/U etc. delaymode_in <= '1' WHEN (delaymode = '1') ELSE '0'; dutycycledelayctrlin_in(0) <= '1' WHEN (dutycycledelayctrlin(0) = '1') ELSE '0'; dutycycledelayctrlin_in(1) <= '1' WHEN (dutycycledelayctrlin(1) = '1') ELSE '0'; dutycycledelayctrlin_in(2) <= '1' WHEN (dutycycledelayctrlin(2) = '1') ELSE '0'; dutycycledelayctrlin_in(3) <= '1' WHEN (dutycycledelayctrlin(3) = '1') ELSE '0'; -- delay chain for clk_in delay m_clk_in_delay_chain : hardcopyiii_ddr_delay_chain_s GENERIC MAP ( phase_setting => phase_setting_for_delayed_clock, use_phasectrlin => "false", delay_buffer_mode => delay_buffer_mode, sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay, sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay, sim_buffer_delay_increment => sim_buffer_delay_increment ) PORT MAP( clk => clk_in, delayctrlin => delayctrlin_in, phasectrlin => phasectrlin_in, delayed_clkout => clk_in_delayed ); -- clock source for datain and cycle delay registers clk_in_mux <= clk_in_delayed WHEN (use_delayed_clock = "true") ELSE clk_in; -- delay chain for phase control m_delay_chain : hardcopyiii_ddr_delay_chain_s GENERIC MAP ( phase_setting => phase_setting, use_phasectrlin => use_phasectrlin, delay_buffer_mode => delay_buffer_mode, sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay, sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay, phasectrlin_limit => 10, sim_buffer_delay_increment => sim_buffer_delay_increment ) PORT MAP( clk => clk_in, delayctrlin => delayctrlin_in, phasectrlin => phasectrlin_in, delayed_clkout => phasectrl_clkout ); -- primary outputs normal_dataout <= dlyclk_q; extended_dataout <= dlyclk_q OR dlyclk_extended_q; -- oe port is active low ddio_dataout <= ddio_out_hi_q WHEN (ddio_out_clk_mux = '1') ELSE ddio_out_lo_q; tmp_dataout <= ddio_dataout WHEN (operation_mode = "ddio_out") ELSE extended_dataout WHEN (operation_mode = "extended_oe" OR operation_mode = "extended_rtena") ELSE normal_dataout WHEN (operation_mode = "output" OR operation_mode = "oe" OR operation_mode = "rtena") ELSE 'Z'; dataout <= tmp_dataout; ddio_out_clk_mux <= dlyclk_clk after 1 ps; -- symbolic T4 to remove glitch on data_h ddio_out_lo_q <= dlyclk_q after 2 ps; -- symbolic 2 T4 to remove glitch on data_l ddio_out_hi_q <= ddio_dlyclk_q; -- resolve reset modes PROCESS(areset_in) BEGIN IF (async_mode = "clear") THEN clrn_in_r <= not areset_in; prn_in_r <= '1'; ELSIF (async_mode = "preset") THEN prn_in_r <= not areset_in; clrn_in_r <= '1'; END IF; END PROCESS; PROCESS(sreset_in) BEGIN IF (sync_mode = "clear") THEN sclr_in_r <= sreset_in; adatasdata_in_r <= '0'; sload_in_r <= '0'; ELSIF (sync_mode = "preset") THEN sload_in_r <= sreset_in; adatasdata_in_r <= '1'; sclr_in_r <= '0'; END IF; END PROCESS; sclr_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sclr_in_r; sload_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sload_in_r; adatasdata_in <= adatasdata_in_r; dlyclk_clkena_in <= '1' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE clkena_in; -- Datain Register datain_reg : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => datain_in(0), clk => clk_in_mux, ena => m_vcc, clrn => clrn_in_r, prn => prn_in_r, aload => m_gnd, asdata => adatasdata_in, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => datain_q ); -- DDIO Datain Register ddio_datain_reg : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => datain_in(1), clk => clk_in_mux, ena => m_vcc, clrn => clrn_in_r, prn => prn_in_r, aload => m_gnd, asdata => adatasdata_in, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => ddio_datain_q ); -- Cycle Delay Register cycledelay_reg : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => datain_q, clk => clk_in_mux, ena => m_vcc, clrn => clrn_in_r, prn => prn_in_r, aload => m_gnd, asdata => adatasdata_in, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => cycledelay_q ); -- DDIO Cycle Delay Register ddio_cycledelay_reg : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => ddio_datain_q, clk => clk_in_mux, ena => m_vcc, clrn => clrn_in_r, prn => prn_in_r, aload => m_gnd, asdata => adatasdata_in, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => ddio_cycledelay_q ); -- enaoutputcycledelay data path mux cycledelay_mux_out <= cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE datain_q WHEN (add_output_cycle_delay = "false") ELSE cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE datain_q; -- input register bypass mux bypass_input_reg_mux_out <= datain_in(0) WHEN (bypass_input_register = "true") ELSE cycledelay_mux_out; --assign #300 transfer_q = cycledelay_mux_out; -- transfer delay is implemented with negative register in rev1.26 transferdelay_reg : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => bypass_input_reg_mux_out, clk => not_clk_in_mux, ena => m_vcc, clrn => clrn_in_r, prn => prn_in_r, aload => m_gnd, asdata => adatasdata_in, sclr => sclr_in, sload => sload_in, devclrn => devclrn, devpor => devpor, q => transfer_q ); -- add phase transfer data path mux dlyclk_d <= transfer_q WHEN (add_phase_transfer_reg = "true") ELSE bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE bypass_input_reg_mux_out; -- clock mux for the output register phaseinvertctrl_out <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE phasectrl_clkout WHEN (invert_phase = "false") ELSE (not phasectrl_clkout) WHEN (phaseinvertctrl_in = m_vcc) ELSE phasectrl_clkout; -- Duty Cycle Delay dcd_in <= phaseinvertctrl_out WHEN (use_phasectrl_clock = "true") ELSE clk_in_mux; PROCESS(dutycycledelayctrlin_in) variable init : boolean := true; variable dcd_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0); variable dcd_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0); variable dcd_dly_setting : integer := 0; begin if (init) then dcd_table_rising(0) := sim_dutycycledelayctrlin_rising_delay_0; dcd_table_rising(1) := sim_dutycycledelayctrlin_rising_delay_1; dcd_table_rising(2) := sim_dutycycledelayctrlin_rising_delay_2; dcd_table_rising(3) := sim_dutycycledelayctrlin_rising_delay_3; dcd_table_rising(4) := sim_dutycycledelayctrlin_rising_delay_4; dcd_table_rising(5) := sim_dutycycledelayctrlin_rising_delay_5; dcd_table_rising(6) := sim_dutycycledelayctrlin_rising_delay_6; dcd_table_rising(7) := sim_dutycycledelayctrlin_rising_delay_7; dcd_table_rising(8) := sim_dutycycledelayctrlin_rising_delay_8; dcd_table_rising(9) := sim_dutycycledelayctrlin_rising_delay_9; dcd_table_rising(10) := sim_dutycycledelayctrlin_rising_delay_10; dcd_table_rising(11) := sim_dutycycledelayctrlin_rising_delay_11; dcd_table_rising(12) := sim_dutycycledelayctrlin_rising_delay_12; dcd_table_rising(13) := sim_dutycycledelayctrlin_rising_delay_13; dcd_table_rising(14) := sim_dutycycledelayctrlin_rising_delay_14; dcd_table_rising(15) := sim_dutycycledelayctrlin_rising_delay_15; dcd_table_falling(0) := sim_dutycycledelayctrlin_falling_delay_0; dcd_table_falling(1) := sim_dutycycledelayctrlin_falling_delay_1; dcd_table_falling(2) := sim_dutycycledelayctrlin_falling_delay_2; dcd_table_falling(3) := sim_dutycycledelayctrlin_falling_delay_3; dcd_table_falling(4) := sim_dutycycledelayctrlin_falling_delay_4; dcd_table_falling(5) := sim_dutycycledelayctrlin_falling_delay_5; dcd_table_falling(6) := sim_dutycycledelayctrlin_falling_delay_6; dcd_table_falling(7) := sim_dutycycledelayctrlin_falling_delay_7; dcd_table_falling(8) := sim_dutycycledelayctrlin_falling_delay_8; dcd_table_falling(9) := sim_dutycycledelayctrlin_falling_delay_9; dcd_table_falling(10) := sim_dutycycledelayctrlin_falling_delay_10; dcd_table_falling(11) := sim_dutycycledelayctrlin_falling_delay_11; dcd_table_falling(12) := sim_dutycycledelayctrlin_falling_delay_12; dcd_table_falling(13) := sim_dutycycledelayctrlin_falling_delay_13; dcd_table_falling(14) := sim_dutycycledelayctrlin_falling_delay_14; dcd_table_falling(15) := sim_dutycycledelayctrlin_falling_delay_15; init := false; end if; dcd_dly_setting := alt_conv_integer(dutycycledelayctrlin_in); dcd_rising_dly <= dcd_table_rising(dcd_dly_setting); dcd_falling_dly <= dcd_table_falling(dcd_dly_setting); end process; -- generating dynamic delays PROCESS(dcd_in) BEGIN dcd_both_gnd <= dcd_in; if (dcd_in = '0') then dcd_both_vcc <= transport dcd_in after (dcd_falling_dly * 1 ps); else dcd_both_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps); end if; END PROCESS; PROCESS(dcd_in) BEGIN if (dcd_in = '0') then dcd_fallnrise_gnd <= transport dcd_in after (dcd_falling_dly * 1 ps); else dcd_fallnrise_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps); end if; END PROCESS; dcd_both <= dcd_both_vcc WHEN (delaymode_in = '1') ELSE dcd_both_gnd; dcd_fallnrise <= dcd_fallnrise_vcc WHEN (delaymode_in = '1') ELSE dcd_fallnrise_gnd; dlyclk_clk <= dcd_both WHEN (duty_cycle_delay_mode = "both") ELSE dcd_fallnrise WHEN (duty_cycle_delay_mode = "fallnrise") ELSE dcd_in; -- Output Register clocked by phasectrl_clk dlyclk_reg : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => dlyclk_d, clk => dlyclk_clk, ena => dlyclk_clkena_in, clrn => clrn_in_r, prn => prn_in_r, aload => m_gnd, asdata => adatasdata_in, sclr => sclr_in, sload => sload_in, devclrn => devclrn, devpor => devpor, q => dlyclk_q ); -- enaoutputcycledelay data path mux ddio_cycledelay_mux_out <= ddio_cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE ddio_datain_q WHEN (add_output_cycle_delay = "false") ELSE ddio_cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE ddio_datain_q; -- input register bypass mux ddio_bypass_input_reg_mux_out <= datain_in(1) WHEN (bypass_input_register = "true") ELSE ddio_cycledelay_mux_out; --assign #300 ddio_transfer_q = ddio_cycledelay_mux_out; -- transfer delay is implemented with negative register in rev1.26 not_clk_in_mux <= not clk_in_mux; ddio_transferdelay_reg : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => ddio_bypass_input_reg_mux_out, clk => not_clk_in_mux, ena => m_vcc, clrn => clrn_in_r, prn => prn_in_r, aload => m_gnd, asdata => adatasdata_in, sclr => sclr_in, sload => sload_in, devclrn => devclrn, devpor => devpor, q => ddio_transfer_q ); -- add phase transfer data path mux ddio_dlyclk_d <= ddio_transfer_q WHEN (add_phase_transfer_reg = "true") ELSE ddio_bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE ddio_transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE ddio_bypass_input_reg_mux_out; -- Output Register clocked by phasectrl_clk ddio_dlyclk_reg : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => ddio_dlyclk_d, clk => dlyclk_clk, ena => dlyclk_clkena_in, clrn => clrn_in_r, prn => prn_in_r, aload => m_gnd, asdata => adatasdata_in, sclr => sclr_in, sload => sload_in, devclrn => devclrn, devpor => devpor, q => ddio_dlyclk_q ); -- Extension Register dlyclk_extended_clk <= not dlyclk_clk; dlyclk_extended_reg : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => dlyclk_q, clk => dlyclk_extended_clk, ena => dlyclk_clkena_in, clrn => clrn_in_r, prn => prn_in_r, aload => m_gnd, asdata => adatasdata_in, sclr => sclr_in, sload => sload_in, devclrn => devclrn, devpor => devpor, q => dlyclk_extended_q ); -------------------- -- INPUT PATH DELAYS -------------------- WireDelay : block begin loopbits_datain : FOR i in datain'RANGE GENERATE VitalWireDelay (datain_in(i), datain(i), tipd_datain(i)); END GENERATE; VitalWireDelay (clk_in, clk, tipd_clk); loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i)); END GENERATE; loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i)); END GENERATE; VitalWireDelay (areset_in, areset, tipd_areset); VitalWireDelay (sreset_in, sreset, tipd_sreset); VitalWireDelay (clkena_in, clkena, tipd_clkena); VitalWireDelay (enaoutputcycledelay_in, enaoutputcycledelay, tipd_enaoutputcycledelay); VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg); VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl); end block; END hardcopyiii_output_phase_alignment_arch; ------------------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_input_phase_alignment -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; use work.hardcopyiii_ddr_io_reg; use work.hardcopyiii_ddr_delay_chain_s; ENTITY hardcopyiii_input_phase_alignment IS GENERIC ( use_phasectrlin : string := "true"; phase_setting : integer := 0; delay_buffer_mode : string := "high"; power_up : string := "low"; async_mode : string := "none"; add_input_cycle_delay : string := "false"; bypass_output_register : string := "false"; add_phase_transfer_reg : string := "false"; invert_phase : string := "false"; sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; lpm_type : string := "hardcopyiii_input_phase_alignment"; tipd_datain : VitalDelayType01 := DefpropDelay01; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); tipd_areset : VitalDelayType01 := DefpropDelay01; tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01; tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01; tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( datain : IN std_logic := '0'; clk : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0'); phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0'); areset : IN std_logic := '0'; enainputcycledelay : IN std_logic := '0'; enaphasetransferreg : IN std_logic := '0'; phaseinvertctrl : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dataout : OUT std_logic; dffin : OUT std_logic; dff1t : OUT std_logic ); END; ARCHITECTURE hardcopyiii_input_phase_alignment_arch OF hardcopyiii_input_phase_alignment IS -- component section COMPONENT hardcopyiii_ddr_delay_chain_s GENERIC ( use_phasectrlin : string := "true"; phase_setting : integer := 0; delay_buffer_mode : string := "high"; sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; phasectrlin_limit : integer := 7 ); PORT ( clk : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0'); phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); delayed_clkout : OUT std_logic ); END COMPONENT; component hardcopyiii_ddr_io_reg generic ( power_up : string := "DONT_CARE"; is_wysiwyg : string := "false"; x_on_violation : string := "on"; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_asdata_q: VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_d : VitalDelayType01 := DefPropDelay01; tipd_asdata : VitalDelayType01 := DefPropDelay01; tipd_sclr : VitalDelayType01 := DefPropDelay01; tipd_sload : VitalDelayType01 := DefPropDelay01; tipd_clrn : VitalDelayType01 := DefPropDelay01; tipd_prn : VitalDelayType01 := DefPropDelay01; tipd_aload : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; InstancePath: STRING := "*" ); port ( d : in std_logic := '0'; clk : in std_logic := '0'; ena : in std_logic := '1'; clrn : in std_logic := '1'; prn : in std_logic := '1'; aload : in std_logic := '0'; asdata : in std_logic := '0'; sclr : in std_logic := '0'; sload : in std_logic := '0'; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; q : out std_logic ); end component; -- int signals SIGNAL phasectrl_clkout : STD_LOGIC := '0'; SIGNAL delayed_clk : STD_LOGIC := '0'; SIGNAL not_delayed_clk : STD_LOGIC := '1'; SIGNAL m_vcc: STD_LOGIC := '1'; SIGNAL m_gnd: STD_LOGIC := '0'; -- IO registers -- common SIGNAL adatasdata_in_r : STD_LOGIC := '0'; SIGNAL aload_in_r : STD_LOGIC := '0'; SIGNAL datain_q : STD_LOGIC := '0'; SIGNAL cycledelay_q : STD_LOGIC := '0'; SIGNAL cycledelay_mux_out : STD_LOGIC := '0'; SIGNAL cycledelay_mux_out_dly : STD_LOGIC := '0'; SIGNAL dlyclk_d : STD_LOGIC := '0'; SIGNAL dlyclk_q : STD_LOGIC := '0'; SIGNAL tmp_dataout : STD_LOGIC := '0'; -- timing inputs SIGNAL datain_in : std_logic := '0'; SIGNAL clk_in : std_logic := '0'; SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0'); SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0'); SIGNAL areset_in : std_logic := '0'; SIGNAL enainputcycledelay_in : std_logic := '0'; SIGNAL enaphasetransferreg_in : std_logic := '0'; SIGNAL phaseinvertctrl_in : std_logic := '0'; BEGIN m_clk_in_delay_chain : hardcopyiii_ddr_delay_chain_s GENERIC MAP ( phase_setting => phase_setting, use_phasectrlin => use_phasectrlin, delay_buffer_mode => delay_buffer_mode, sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay, sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay, sim_buffer_delay_increment => sim_buffer_delay_increment ) PORT MAP( clk => clk_in, delayctrlin => delayctrlin_in, phasectrlin => phasectrlin_in, delayed_clkout => phasectrl_clkout ); delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE phasectrl_clkout WHEN (invert_phase = "false") ELSE (not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE phasectrl_clkout; -- primary output dataout <= tmp_dataout; tmp_dataout <= dlyclk_d WHEN (bypass_output_register = "true") ELSE dlyclk_q; -- add phase transfer data path mux dlyclk_d <= cycledelay_mux_out_dly WHEN (add_phase_transfer_reg = "true") ELSE cycledelay_mux_out WHEN (add_phase_transfer_reg = "false") ELSE cycledelay_mux_out_dly WHEN (enaphasetransferreg_in = '1') ELSE cycledelay_mux_out; -- enaoutputcycledelay data path mux cycledelay_mux_out <= cycledelay_q WHEN (add_input_cycle_delay = "true") ELSE datain_q WHEN (add_input_cycle_delay = "false") ELSE cycledelay_q WHEN (enainputcycledelay_in = '1') ELSE datain_q; -- resolve reset modes PROCESS (areset_in) BEGIN if (async_mode = "clear") then aload_in_r <= areset_in; adatasdata_in_r <= '0'; elsif (async_mode = "preset") then aload_in_r <= areset_in; adatasdata_in_r <= '1'; else -- async_mode = "none" adatasdata_in_r <= 'Z'; end if; END PROCESS; -- Datain Register datain_reg : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => datain_in, clk => delayed_clk, ena => m_vcc, clrn => m_vcc, prn => m_vcc, aload => aload_in_r, asdata => adatasdata_in_r, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => datain_q ); -- Cycle Delay Register cycledelay_reg : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => datain_q, clk => delayed_clk, ena => m_vcc, clrn => m_vcc, prn => m_vcc, aload => aload_in_r, asdata => adatasdata_in_r, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => cycledelay_q ); -- assign #300 cycledelay_mux_out_dly = cycledelay_mux_out; replaced by neg reg -- Transfer Register - clocked by negative edge not_delayed_clk <= not delayed_clk; transfer_reg : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => cycledelay_mux_out, clk => not_delayed_clk, -- ~delayed_clk ena => m_vcc, clrn => m_vcc, prn => m_vcc, aload => aload_in_r, asdata => adatasdata_in_r, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => cycledelay_mux_out_dly ); -- Register clocked by actually by clk_in dlyclk_reg : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => dlyclk_d, clk => clk_in, ena => m_vcc, clrn => m_vcc, prn => m_vcc, aload => aload_in_r, asdata => adatasdata_in_r, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => dlyclk_q ); -------------------- -- INPUT PATH DELAYS -------------------- WireDelay : block begin VitalWireDelay (datain_in, datain, tipd_datain); VitalWireDelay (clk_in, clk, tipd_clk); loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i)); END GENERATE; loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i)); END GENERATE; VitalWireDelay (areset_in, areset, tipd_areset); VitalWireDelay (enainputcycledelay_in, enainputcycledelay, tipd_enainputcycledelay); VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg); VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl); end block; END hardcopyiii_input_phase_alignment_arch; ------------------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_half_rate_input -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; use work.hardcopyiii_ddr_io_reg; ENTITY hardcopyiii_half_rate_input IS GENERIC ( power_up : string := "low"; async_mode : string := "none"; use_dataoutbypass : string := "false"; lpm_type : string := "hardcopyiii_half_rate_input"; tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); tipd_directin : VitalDelayType01 := DefpropDelay01; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_areset : VitalDelayType01 := DefpropDelay01; tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0'); directin : IN std_logic := '0'; clk : IN std_logic := '0'; areset : IN std_logic := '0'; dataoutbypass: IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dataout : OUT std_logic_vector(3 downto 0); dffin : OUT std_logic ); END; ARCHITECTURE hardcopyiii_half_rate_input_arch OF hardcopyiii_half_rate_input IS -- component section component hardcopyiii_ddr_io_reg generic ( power_up : string := "DONT_CARE"; is_wysiwyg : string := "false"; x_on_violation : string := "on"; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_asdata_q: VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_d : VitalDelayType01 := DefPropDelay01; tipd_asdata : VitalDelayType01 := DefPropDelay01; tipd_sclr : VitalDelayType01 := DefPropDelay01; tipd_sload : VitalDelayType01 := DefPropDelay01; tipd_clrn : VitalDelayType01 := DefPropDelay01; tipd_prn : VitalDelayType01 := DefPropDelay01; tipd_aload : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; InstancePath: STRING := "*" ); port ( d : in std_logic := '0'; clk : in std_logic := '0'; ena : in std_logic := '1'; clrn : in std_logic := '1'; prn : in std_logic := '1'; aload : in std_logic := '0'; asdata : in std_logic := '0'; sclr : in std_logic := '0'; sload : in std_logic := '0'; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; q : out std_logic ); end component; SIGNAL m_vcc: STD_LOGIC := '1'; SIGNAL m_gnd: STD_LOGIC := '0'; -- IO SIGNAListers -- common SIGNAL neg_clk_in : STD_LOGIC := '0'; SIGNAL adatasdata_in_r : STD_LOGIC := '0'; SIGNAL aload_in_r : STD_LOGIC := '0'; -- low_bank = {1, 0} - capturing datain at falling edge then sending at falling rise -- high_bank = {3, 2} - output of SIGNALister datain at rising SIGNAL high_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0'); SIGNAL low_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0'); SIGNAL low_bank_low : STD_LOGIC := '0'; SIGNAL low_bank_high : STD_LOGIC := '0'; SIGNAL high_bank_low : STD_LOGIC := '0'; SIGNAL high_bank_high: STD_LOGIC := '0'; SIGNAL dataout_reg_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0'); SIGNAL tmp_dataout : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); -- delayed version to ensure 1 latency as expected in functional sim SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0'); -- timing inputs SIGNAL datain_ipd : std_logic_vector(1 downto 0) := (OTHERS => '0'); SIGNAL directin_in : std_logic := '0'; SIGNAL clk_in : std_logic := '0'; SIGNAL areset_in : std_logic := '0'; SIGNAL dataoutbypass_in: std_logic := '0'; BEGIN -- primary input datain_in <= transport datain_ipd after 2 ps; -- primary output dataout <= tmp_dataout; tmp_dataout(3) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_high; tmp_dataout(2) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_low; tmp_dataout(1) <= low_bank(1); tmp_dataout(0) <= low_bank(0); low_bank <= low_bank_high & low_bank_low; high_bank <= high_bank_high & high_bank_low; -- resolve reset modes PROCESS(areset_in) BEGIN if (async_mode = "clear") then aload_in_r <= areset_in; adatasdata_in_r <= '0'; elsif (async_mode = "preset") then aload_in_r <= areset_in; adatasdata_in_r <= '1'; else -- async_mode = "none" adatasdata_in_r <= 'Z'; end if; END PROCESS; neg_clk_in <= not clk_in; -- datain_1 - H reg1_h : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => datain_in(1), clk => clk_in, ena => m_vcc, clrn => m_vcc, prn => m_vcc, aload => aload_in_r, asdata => adatasdata_in_r, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => high_bank_high ); -- datain_0 - H reg0_h : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => datain_in(0), clk => clk_in, ena => m_vcc, clrn => m_vcc, prn => m_vcc, aload => aload_in_r, asdata => adatasdata_in_r, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => high_bank_low ); -- datain_1 - L (n) reg1_l_n : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => datain_in(1), clk => neg_clk_in, ena => m_vcc, clrn => m_vcc, prn => m_vcc, aload => aload_in_r, asdata => adatasdata_in_r, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => dataout_reg_n(1) ); -- datain_1 - L reg1_l : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => dataout_reg_n(1), clk => clk_in, ena => m_vcc, clrn => m_vcc, prn => m_vcc, aload => aload_in_r, asdata => adatasdata_in_r, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => low_bank_high ); -- datain_0 - L (n) reg0_l_n : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => datain_in(0), clk => neg_clk_in, ena => m_vcc, clrn => m_vcc, prn => m_vcc, aload => aload_in_r, asdata => adatasdata_in_r, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => dataout_reg_n(0) ); -- datain_0 - L reg0_l : hardcopyiii_ddr_io_reg GENERIC MAP (power_up => power_up) PORT MAP( d => dataout_reg_n(0), clk => clk_in, ena => m_vcc, clrn => m_vcc, prn => m_vcc, aload => aload_in_r, asdata => adatasdata_in_r, sclr => m_gnd, sload => m_gnd, devclrn => devclrn, devpor => devpor, q => low_bank_low ); -------------------- -- INPUT PATH DELAYS -------------------- WireDelay : block begin loopbits_datain : FOR i in datain'RANGE GENERATE VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i)); END GENERATE; VitalWireDelay (directin_in, directin, tipd_directin); VitalWireDelay (clk_in, clk, tipd_clk); VitalWireDelay (areset_in, areset, tipd_areset); VitalWireDelay (dataoutbypass_in, dataoutbypass, tipd_dataoutbypass); end block; END hardcopyiii_half_rate_input_arch; ------------------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_io_config -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_io_config IS GENERIC ( enhanced_mode : string := "false"; lpm_type : string := "hardcopyiii_io_config"; tipd_datain : VitalDelayType01 := DefpropDelay01; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_ena : VitalDelayType01 := DefpropDelay01; tipd_update : VitalDelayType01 := DefpropDelay01; tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( datain : IN std_logic := '0'; clk : IN std_logic := '0'; ena : IN std_logic := '1'; update : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; -- new STRATIXIV: ww30.2008 dutycycledelaymode : OUT std_logic; dutycycledelaysettings : OUT std_logic_vector(3 downto 0); outputfinedelaysetting1 : OUT std_logic; outputfinedelaysetting2 : OUT std_logic; outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0); outputonlyfinedelaysetting2 : OUT std_logic; padtoinputregisterfinedelaysetting : OUT std_logic; padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0); outputdelaysetting1 : OUT std_logic_vector(3 downto 0); outputdelaysetting2 : OUT std_logic_vector(2 downto 0); dataout : OUT std_logic ); END; ARCHITECTURE hardcopyiii_io_config_arch OF hardcopyiii_io_config IS -- component section SIGNAL shift_reg : std_logic_vector(10 downto 0) := (OTHERS => '0'); SIGNAL output_reg : std_logic_vector(10 downto 0) := (OTHERS => '0'); SIGNAL tmp_output : std_logic_vector(10 downto 0) := (OTHERS => '0'); SIGNAL enhance_shift_reg : std_logic_vector(22 downto 0) := (OTHERS => '0'); SIGNAL enhance_output_reg : std_logic_vector(22 downto 0) := (OTHERS => '0'); SIGNAL enhance_tmp_output : std_logic_vector(22 downto 0) := (OTHERS => '0'); -- timing outputs SIGNAL tmp_dataout : std_logic := '0'; -- timing inputs SIGNAL datain_in : std_logic := '0'; SIGNAL clk_in : std_logic := '0'; SIGNAL ena_in : std_logic := '0'; SIGNAL update_in : std_logic := '0'; BEGIN -- primary outputs tmp_dataout <= enhance_shift_reg(22) WHEN (enhanced_mode = "true") ELSE shift_reg(10); -- bit order changed in wys revision 1.32 outputdelaysetting1 <= tmp_output(3 DOWNTO 0); outputdelaysetting2 <= tmp_output(6 DOWNTO 4); padtoinputregisterdelaysetting <= tmp_output(10 DOWNTO 7); -- padtoinputregisterdelaysetting <= tmp_output(3 DOWNTO 0); -- outputdelaysetting1 <= tmp_output(7 DOWNTO 4); -- outputdelaysetting2 <= tmp_output(10 DOWNTO 8); tmp_output <= output_reg; outputdelaysetting1 <= enhance_tmp_output(3 DOWNTO 0) WHEN (enhanced_mode = "true") ELSE tmp_output(3 DOWNTO 0); outputdelaysetting2 <= enhance_tmp_output(6 DOWNTO 4) WHEN (enhanced_mode = "true") ELSE tmp_output(6 DOWNTO 4); padtoinputregisterdelaysetting <= enhance_tmp_output(10 DOWNTO 7) WHEN (enhanced_mode = "true") ELSE tmp_output(10 DOWNTO 7); outputfinedelaysetting1 <= enhance_tmp_output(11) WHEN (enhanced_mode = "true") ELSE '0'; outputfinedelaysetting2 <= enhance_tmp_output(12) WHEN (enhanced_mode = "true") ELSE '0'; padtoinputregisterfinedelaysetting <= enhance_tmp_output(13) WHEN (enhanced_mode = "true") ELSE '0'; outputonlyfinedelaysetting2 <= enhance_tmp_output(14) WHEN (enhanced_mode = "true") ELSE '0'; outputonlydelaysetting2 <= enhance_tmp_output(17 DOWNTO 15) WHEN (enhanced_mode = "true") ELSE "000"; dutycycledelaymode <= enhance_tmp_output(18) WHEN (enhanced_mode = "true") ELSE '0'; dutycycledelaysettings <= enhance_tmp_output(22 DOWNTO 19) WHEN (enhanced_mode = "true") ELSE "0000"; tmp_output <= output_reg; enhance_tmp_output <= enhance_output_reg; PROCESS(clk_in) BEGIN if (clk_in = '1' AND ena_in = '1') then shift_reg(0) <= datain_in; shift_reg(10 DOWNTO 1) <= shift_reg(9 DOWNTO 0); enhance_shift_reg(0) <= datain_in; enhance_shift_reg(22 DOWNTO 1) <= enhance_shift_reg(21 DOWNTO 0); end if; END PROCESS; PROCESS(clk_in) BEGIN if (clk_in = '1' AND update_in = '1') then output_reg <= shift_reg; enhance_output_reg <= enhance_shift_reg; end if; END PROCESS; -------------------- -- INPUT PATH DELAYS -------------------- WireDelay : block begin VitalWireDelay (datain_in, datain, tipd_datain); VitalWireDelay (clk_in, clk, tipd_clk); VitalWireDelay (ena_in, ena, tipd_ena); VitalWireDelay (update_in, update, tipd_update); end block; ----------------------------------- -- Timing Check Section ----------------------------------- VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in) variable Tviol_clk_datain : std_ulogic := '0'; variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit; variable Tviol_clk_ena : std_ulogic := '0'; variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit; variable Tviol_clk_update : std_ulogic := '0'; variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( Violation => Tviol_clk_datain, TimingData => TimingData_clk_datain, TestSignal => datain_in, TestSignalName => "Datain", RefSignal => clk_in, RefSignalName => "clk", SetupHigh => tsetup_datain_clk_noedge_posedge, SetupLow => tsetup_datain_clk_noedge_posedge, HoldHigh => thold_datain_clk_noedge_posedge, HoldLow => thold_datain_clk_noedge_posedge, RefTransition => '/', HeaderMsg => InstancePath & "/HARDCOPYIII_IO_CONFIG", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_clk_ena, TimingData => TimingData_clk_ena, TestSignal => ena_in, TestSignalName => "Ena", RefSignal => clk_in, RefSignalName => "clk", SetupHigh => tsetup_datain_clk_noedge_posedge, SetupLow => tsetup_datain_clk_noedge_posedge, HoldHigh => thold_datain_clk_noedge_posedge, HoldLow => thold_datain_clk_noedge_posedge, RefTransition => '/', HeaderMsg => InstancePath & "/HARDCOPYIII_IO_CONFIG", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_clk_update, TimingData => TimingData_clk_update, TestSignal => update_in, TestSignalName => "Update", RefSignal => clk_in, RefSignalName => "clk", SetupHigh => tsetup_datain_clk_noedge_posedge, SetupLow => tsetup_datain_clk_noedge_posedge, HoldHigh => thold_datain_clk_noedge_posedge, HoldLow => thold_datain_clk_noedge_posedge, RefTransition => '/', HeaderMsg => InstancePath & "/HARDCOPYIII_IO_CONFIG", XOn => XOnChecks, MsgOn => MsgOnChecks ); END IF; END PROCESS; -- timing check -------------------------------------- -- Path Delay Section -------------------------------------- VITAL_path_delays: PROCESS (tmp_dataout) variable dataout_VitalGlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => dataout, OutSignalName => "Dataout", OutTemp => tmp_dataout, Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); END PROCESS; -- Path Delays END hardcopyiii_io_config_arch; ------------------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_dqs_config -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_dqs_config IS GENERIC ( enhanced_mode : string := "false"; lpm_type : string := "hardcopyiii_dqs_config"; tipd_datain : VitalDelayType01 := DefpropDelay01; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_ena : VitalDelayType01 := DefpropDelay01; tipd_update : VitalDelayType01 := DefpropDelay01; tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( datain : IN std_logic := '0'; clk : IN std_logic := '0'; ena : IN std_logic := '0'; update : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0); dqsinputphasesetting : OUT std_logic_vector(2 downto 0); dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0); dqsoutputphasesetting : OUT std_logic_vector(3 downto 0); dqoutputphasesetting : OUT std_logic_vector(3 downto 0); resyncinputphasesetting : OUT std_logic_vector(3 downto 0); dividerphasesetting : OUT std_logic; enaoctcycledelaysetting : OUT std_logic; enainputcycledelaysetting : OUT std_logic; enaoutputcycledelaysetting: OUT std_logic; dqsenabledelaysetting : OUT std_logic_vector(2 downto 0); octdelaysetting1 : OUT std_logic_vector(3 downto 0); octdelaysetting2 : OUT std_logic_vector(2 downto 0); enadataoutbypass : OUT std_logic; enadqsenablephasetransferreg : OUT std_logic; enaoctphasetransferreg : OUT std_logic; enaoutputphasetransferreg : OUT std_logic; enainputphasetransferreg : OUT std_logic; resyncinputphaseinvert : OUT std_logic; dqsenablectrlphaseinvert : OUT std_logic; dqoutputphaseinvert : OUT std_logic; dqsoutputphaseinvert : OUT std_logic; dataout : OUT std_logic ); END; ARCHITECTURE hardcopyiii_dqs_config_arch OF hardcopyiii_dqs_config IS -- component section SIGNAL shift_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0'); SIGNAL output_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0'); SIGNAL tmp_output : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0'); -- timing outputs SIGNAL tmp_dataout : std_logic := '0'; -- timing inputs SIGNAL datain_in : std_logic := '0'; SIGNAL clk_in : std_logic := '0'; SIGNAL ena_in : std_logic := '0'; SIGNAL update_in : std_logic := '0'; BEGIN -- primary outputs tmp_dataout <= shift_reg(47) WHEN (enhanced_mode = "true")ELSE shift_reg(45); dqsbusoutdelaysetting <= tmp_output(3 DOWNTO 0); dqsinputphasesetting <= tmp_output(6 DOWNTO 4); dqsenablectrlphasesetting <= tmp_output(10 DOWNTO 7); dqsoutputphasesetting <= tmp_output(14 DOWNTO 11); dqoutputphasesetting <= tmp_output(18 DOWNTO 15); resyncinputphasesetting <= tmp_output(22 DOWNTO 19); dividerphasesetting <= tmp_output(23); enaoctcycledelaysetting <= tmp_output(24); enainputcycledelaysetting <= tmp_output(25); enaoutputcycledelaysetting<= tmp_output(26); dqsenabledelaysetting <= tmp_output(29 DOWNTO 27); octdelaysetting1 <= tmp_output(33 DOWNTO 30); octdelaysetting2 <= tmp_output(36 DOWNTO 34); enadataoutbypass <= tmp_output(37); enadqsenablephasetransferreg <= tmp_output(38); -- new in 1.23 enaoctphasetransferreg <= tmp_output(39); -- new in 1.23 enaoutputphasetransferreg <= tmp_output(40); -- new in 1.23 enainputphasetransferreg <= tmp_output(41); -- new in 1.23 resyncinputphaseinvert <= tmp_output(42); -- new in 1.26 dqsenablectrlphaseinvert <= tmp_output(43); -- new in 1.26 dqoutputphaseinvert <= tmp_output(44); -- new in 1.26 dqsoutputphaseinvert <= tmp_output(45); -- new in 1.26 -- new in STRATIXIV: ww30.2008 dqsbusoutfinedelaysetting <= tmp_output(46) WHEN (enhanced_mode = "true") ELSE '0'; dqsenablefinedelaysetting <= tmp_output(47) WHEN (enhanced_mode = "true") ELSE '0'; tmp_output <= output_reg; PROCESS(clk_in) begin if (clk_in = '1' AND ena_in = '1') then shift_reg(0) <= datain_in; shift_reg(47 DOWNTO 1) <= shift_reg(46 DOWNTO 0); end if; end process; PROCESS(clk_in) begin if (clk_in = '1' AND update_in = '1') then output_reg <= shift_reg; end if; end process; -------------------- -- INPUT PATH DELAYS -------------------- WireDelay : block begin VitalWireDelay (datain_in, datain, tipd_datain); VitalWireDelay (clk_in, clk, tipd_clk); VitalWireDelay (ena_in, ena, tipd_ena); VitalWireDelay (update_in, update, tipd_update); end block; ----------------------------------- -- Timing Check Section ----------------------------------- VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in) variable Tviol_clk_datain : std_ulogic := '0'; variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit; variable Tviol_clk_ena : std_ulogic := '0'; variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit; variable Tviol_clk_update : std_ulogic := '0'; variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( Violation => Tviol_clk_datain, TimingData => TimingData_clk_datain, TestSignal => datain_in, TestSignalName => "Datain", RefSignal => clk_in, RefSignalName => "clk", SetupHigh => tsetup_datain_clk_noedge_posedge, SetupLow => tsetup_datain_clk_noedge_posedge, HoldHigh => thold_datain_clk_noedge_posedge, HoldLow => thold_datain_clk_noedge_posedge, RefTransition => '/', HeaderMsg => InstancePath & "/HARDCOPYIII_IO_CONFIG", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_clk_ena, TimingData => TimingData_clk_ena, TestSignal => ena_in, TestSignalName => "Ena", RefSignal => clk_in, RefSignalName => "clk", SetupHigh => tsetup_datain_clk_noedge_posedge, SetupLow => tsetup_datain_clk_noedge_posedge, HoldHigh => thold_datain_clk_noedge_posedge, HoldLow => thold_datain_clk_noedge_posedge, RefTransition => '/', HeaderMsg => InstancePath & "/HARDCOPYIII_IO_CONFIG", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_clk_update, TimingData => TimingData_clk_update, TestSignal => update_in, TestSignalName => "Update", RefSignal => clk_in, RefSignalName => "clk", SetupHigh => tsetup_datain_clk_noedge_posedge, SetupLow => tsetup_datain_clk_noedge_posedge, HoldHigh => thold_datain_clk_noedge_posedge, HoldLow => thold_datain_clk_noedge_posedge, RefTransition => '/', HeaderMsg => InstancePath & "/HARDCOPYIII_IO_CONFIG", XOn => XOnChecks, MsgOn => MsgOnChecks ); END IF; END PROCESS; -- timing check -------------------------------------- -- Path Delay Section -------------------------------------- VITAL_path_delays: PROCESS (tmp_dataout) variable dataout_VitalGlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => dataout, OutSignalName => "Dataout", OutTemp => tmp_dataout, Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); END PROCESS; -- Path Delays END hardcopyiii_dqs_config_arch; ------------------------------------------------------------------------------- -- Module Name: hardcopyiii_mac_bit_register -- -- Description: HARDCOPYIII MAC single bit register -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_mac_bit_register IS GENERIC ( tipd_datain : VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_sload : VitalDelayType01 := DefPropDelay01; tipd_aclr : VitalDelayType01 := DefPropDelay01; tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01; tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01; tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks ); PORT ( datain : IN std_logic := '0'; clk : IN std_logic := '0'; aclr : IN std_logic := '0'; sload : IN std_logic := '0'; bypass_register : IN std_logic := '0'; dataout : OUT std_logic ); END hardcopyiii_mac_bit_register; ARCHITECTURE arch OF hardcopyiii_mac_bit_register IS SIGNAL datain_ipd : std_logic := '0'; SIGNAL clk_ipd : std_logic := '0'; SIGNAL aclr_ipd : std_logic := '0'; SIGNAL sload_ipd : std_logic := '1'; SIGNAL dataout_tmp : std_logic := '0'; SIGNAL dataout_reg : std_logic := '0'; BEGIN WireDelay : block begin VitalWireDelay (datain_ipd, datain, tipd_datain); VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (aclr_ipd, aclr, tipd_aclr); VitalWireDelay (sload_ipd, sload, tipd_sload); end block; PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd) variable Tviol_datain_clk : std_ulogic := '0'; variable Tviol_sload_clk : std_ulogic := '0'; variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit; variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit; variable q_VitalGlitchData : VitalGlitchDataType; VARIABLE CQDelay : TIME := 0 ns; BEGIN IF (aclr_ipd = '1') THEN dataout_reg <= '0'; ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN IF (sload_ipd = '1') THEN dataout_reg <= datain_ipd; ELSE dataout_reg <= dataout_reg; END IF; END IF; VitalSetupHoldCheck ( Violation => Tviol_datain_clk, TimingData => TimingData_datain_clk, TestSignal => datain, TestSignalName => "DATAIN", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_datain_clk_noedge_posedge, SetupLow => tsetup_datain_clk_noedge_posedge, HoldHigh => thold_datain_clk_noedge_posedge, HoldLow => thold_datain_clk_noedge_posedge, CheckEnabled => TO_X01((NOT aclr_ipd) OR (sload_ipd)) /= '1', RefTransition => '/', HeaderMsg => "/MAC Register VitalSetupHoldCheck", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_sload_clk, TimingData => TimingData_sload_clk, TestSignal => sload_ipd, TestSignalName => "SLOAD", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_sload_clk_noedge_posedge, SetupLow => tsetup_sload_clk_noedge_posedge, HoldHigh => thold_sload_clk_noedge_posedge, HoldLow => thold_sload_clk_noedge_posedge, CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1', RefTransition => '/', HeaderMsg => "/MAC Register VitalSetupHoldCheck", XOn => XOnChecks, MsgOn => MsgOnChecks ); END PROCESS; dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg; PROCESS(dataout_tmp) variable dataout_VitalGlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => dataout, OutSignalName => "dataout", OutTemp => dataout_tmp, Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE), 1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, XOn => TRUE, MsgOn => TRUE ); END PROCESS; END arch; ------------------------------------------------------------------------------- -- Module Name: hardcopyiii_mac_register -- -- Description: HARDCOPYIII MAC variable width register -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_mac_register IS GENERIC ( data_width : integer := 18; tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01); tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_sload : VitalDelayType01 := DefPropDelay01; tipd_aclr : VitalDelayType01 := DefPropDelay01; tpd_aclr_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01); tpd_clk_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01); tsetup_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst); thold_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst); tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks ); PORT ( datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0'); clk : IN std_logic := '0'; aclr : IN std_logic := '0'; sload : IN std_logic := '0'; bypass_register : IN std_logic := '0'; dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0) ); END hardcopyiii_mac_register; ARCHITECTURE arch OF hardcopyiii_mac_register IS SIGNAL datain_ipd : std_logic_vector(data_width -1 downto 0) := (others => '0'); SIGNAL clk_ipd : std_logic := '0'; SIGNAL aclr_ipd : std_logic := '0'; SIGNAL sload_ipd : std_logic := '1'; SIGNAL dataout_tmp : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0'); SIGNAL dataout_reg : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0'); BEGIN WireDelay : block begin g1 :for i in datain'range generate VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i)); end generate; VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (aclr_ipd, aclr, tipd_aclr); VitalWireDelay (sload_ipd, sload, tipd_sload); end block; PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd) BEGIN IF (aclr_ipd = '1') THEN dataout_reg <= (OTHERS => '0'); ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN IF (sload_ipd = '1') THEN dataout_reg <= datain_ipd; ELSE dataout_reg <= dataout_reg; END IF; END IF; END process; sh: block begin g0 : for i in datain'range generate process(datain_ipd(i),clk_ipd,sload_ipd) variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(71 downto 0); variable Tviol_sload_clk : std_ulogic := '0'; variable Tviol_datain_clk : std_ulogic := '0'; variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit; variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit; begin VitalSetupHoldCheck ( Violation => Tviol_datain_clk, TimingData => TimingData_datain_clk, TestSignal => datain_ipd(i), TestSignalName => "DATAIN(i)", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_datain_clk_noedge_posedge(i), SetupLow => tsetup_datain_clk_noedge_posedge(i), HoldHigh => thold_datain_clk_noedge_posedge(i), HoldLow => thold_datain_clk_noedge_posedge(i), CheckEnabled => TO_X01((NOT aclr_ipd) OR (sload_ipd)) /= '1', RefTransition => '/', HeaderMsg => "/MAC_REG", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_sload_clk, TimingData => TimingData_sload_clk, TestSignal => sload_ipd, TestSignalName => "SLOAD", RefSignal => clk_ipd, RefSignalName => "CLK", SetupHigh => tsetup_sload_clk_noedge_posedge, SetupLow => tsetup_sload_clk_noedge_posedge, HoldHigh => thold_sload_clk_noedge_posedge, HoldLow => thold_sload_clk_noedge_posedge, CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1', RefTransition => '/', HeaderMsg => "/MAC_REG", XOn => XOnChecks, MsgOn => MsgOnChecks ); END PROCESS; end generate g0; end block; dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg; PathDelay : block begin g1 : for i in dataout'range generate PROCESS (dataout_tmp(i)) variable dataout_VitalGlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => dataout(i), OutSignalName => "dataout", OutTemp => dataout_tmp(i), Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE), 1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, XOn => TRUE, MsgOn => TRUE ); end process; end generate; end block; END arch; ------------------------------------------------------------------------------- -- Module Name: hardcopyiii_mac_multiplier -- -- Description: HARDCOPYIII MAC signed multiplier -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_mac_multiplier IS GENERIC ( dataa_width : integer := 18; datab_width : integer := 18; tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01); tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01); tipd_signa : VitalDelayType01 := DefPropDelay01; tipd_signb : VitalDelayType01 := DefPropDelay01; tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01); tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01); tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01); tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01); XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn ); PORT ( dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0'); datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0'); signa : IN std_logic := '0'; signb : IN std_logic := '0'; dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0) ); END hardcopyiii_mac_multiplier; ARCHITECTURE arch OF hardcopyiii_mac_multiplier IS constant dataout_width : integer := dataa_width + datab_width; SIGNAL product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0'); SIGNAL abs_product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0'); SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0'); SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0'); SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0'); SIGNAL product_sign : std_logic := '0'; SIGNAL dataa_sign : std_logic := '0'; SIGNAL datab_sign : std_logic := '0'; SIGNAL dataa_ipd : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0'); SIGNAL datab_ipd : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0'); SIGNAL signa_ipd : std_logic := '0'; SIGNAL signb_ipd : std_logic := '0'; BEGIN WireDelay : block begin g1 :for i in dataa'range generate VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i)); end generate; g2 :for i in datab'range generate VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i)); end generate; VitalWireDelay (signa_ipd, signa, tipd_signa); VitalWireDelay (signb_ipd, signb, tipd_signb); end block; dataa_sign <= dataa_ipd(dataa_width - 1) AND signa_ipd ; datab_sign <= datab_ipd(datab_width - 1) AND signb_ipd ; product_sign <= dataa_sign XOR datab_sign ; abs_a <= (NOT dataa_ipd + '1') WHEN dataa_sign = '1' ELSE dataa_ipd; abs_b <= (NOT datab_ipd + '1') WHEN datab_sign = '1' ELSE datab_ipd; abs_product <= abs_a * abs_b ; dataout_tmp <= (NOT abs_product + 1) WHEN product_sign = '1' ELSE abs_product; PathDelay : block begin do : for i in dataout'range generate process(dataout_tmp(i)) VARIABLE dataout_VitalGlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => dataout(i), OutSignalName => "dataout", OutTemp => dataout_tmp(i), Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE), 1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE), 2 => (signa'last_event, tpd_signa_dataout(i), TRUE), 3 => (signb'last_event, tpd_signb_dataout(i), TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, MsgOn => FALSE, XOn => TRUE ); end process; end generate do; end block; END arch; ---------------------------------------------------------------------------------- -- Module Name: hardcopyiii_mac_mult_atom -- -- Description: Simulation model for hardcopyiii mac mult atom. -- -- This model instantiates the following components. -- -- 1.hardcopyiii_mac_bit_register. -- -- 2.hardcopyiii_mac_register. -- -- 3.hardcopyiii_mac_multiplier. -- ---------------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_mac_mult IS GENERIC ( dataa_width : integer := 18; datab_width : integer := 18; dataa_clock : string := "none"; datab_clock : string := "none"; signa_clock : string := "none"; signb_clock : string := "none"; scanouta_clock : string := "none"; dataa_clear : string := "none"; datab_clear : string := "none"; signa_clear : string := "none"; signb_clear : string := "none"; scanouta_clear : string := "none"; signa_internally_grounded : string := "false"; signb_internally_grounded : string := "false"; lpm_type : string := "hardcopyiii_mac_mult" ); PORT ( dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1'); datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1'); signa : IN std_logic := '1'; signb : IN std_logic := '1'; clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0'); aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0'); ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1'); dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0); scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0); devclrn : IN std_logic := '1'; devpor : IN std_logic := '1' ); END hardcopyiii_mac_mult; ARCHITECTURE arch OF hardcopyiii_mac_mult IS constant dataout_width : integer := dataa_width + datab_width; COMPONENT hardcopyiii_mac_bit_register PORT ( datain : IN std_logic := '0'; clk : IN std_logic := '0'; aclr : IN std_logic := '0'; sload : IN std_logic := '0'; bypass_register : IN std_logic := '0'; dataout : OUT std_logic ); END COMPONENT; COMPONENT hardcopyiii_mac_register GENERIC ( data_width : integer := 18 ); PORT ( datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0'); clk : IN std_logic := '0'; aclr : IN std_logic := '0'; sload : IN std_logic := '0'; bypass_register : IN std_logic := '0'; dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0) ); END COMPONENT; COMPONENT hardcopyiii_mac_multiplier GENERIC ( dataa_width : integer := 18; datab_width : integer := 18 ); PORT ( dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0'); datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0'); signa : IN std_logic := '0'; signb : IN std_logic := '0'; dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0) ); END COMPONENT; --Internal signals to instantiate the dataa input register unit SIGNAL dataa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL dataa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL dataa_clk : std_logic := '0'; SIGNAL dataa_aclr : std_logic := '0'; SIGNAL dataa_sload : std_logic := '0'; SIGNAL dataa_bypass_register : std_logic := '0'; SIGNAL dataa_in_reg : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0'); SIGNAL dataa_in : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0'); --Internal signals to instantiate the datab input register unit SIGNAL datab_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL datab_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL datab_clk : std_logic := '0'; SIGNAL datab_aclr : std_logic := '0'; SIGNAL datab_sload : std_logic := '0'; SIGNAL datab_bypass_register : std_logic := '0'; SIGNAL datab_in_reg : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0'); SIGNAL datab_in : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0'); --Internal signals to instantiate the signa input register unit SIGNAL signa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL signa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL signa_clk : std_logic := '0'; SIGNAL signa_aclr : std_logic := '0'; SIGNAL signa_sload : std_logic := '0'; SIGNAL signa_bypass_register : std_logic := '0'; SIGNAL signa_in_reg : std_logic := '0'; SIGNAL signa_in : std_logic := '0'; --Internal signbls to instantiate the signb input register unit SIGNAL signb_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL signb_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL signb_clk : std_logic := '0'; SIGNAL signb_aclr : std_logic := '0'; SIGNAL signb_sload : std_logic := '0'; SIGNAL signb_bypass_register : std_logic := '0'; SIGNAL signb_in_reg : std_logic := '0'; SIGNAL signb_in : std_logic := '0'; --Internal scanoutals to instantiate the scanouta input register unit SIGNAL scanouta_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL scanouta_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL scanouta_clk : std_logic := '0'; SIGNAL scanouta_aclr : std_logic := '0'; SIGNAL scanouta_sload : std_logic := '0'; SIGNAL scanouta_bypass_register : std_logic := '0'; SIGNAL scanouta_tmp : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0'); --Internal Signals to instantiate the mac multiplier SIGNAL signa_mult : std_logic := '0'; SIGNAL signb_mult : std_logic := '0'; SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0'); BEGIN --Instantiate the dataa input Register dataa_clk_value <= "0000" WHEN ((dataa_clock = "0") or (dataa_clock = "none")) ELSE "0001" WHEN (dataa_clock = "1") ELSE "0010" WHEN (dataa_clock = "2") ELSE "0011" WHEN (dataa_clock = "3") ELSE "0000" ; dataa_aclr_value <= "0000" WHEN ((dataa_clear = "0") or (dataa_clear = "none")) ELSE "0001" WHEN (dataa_clear = "1") ELSE "0010" WHEN (dataa_clear = "2") ELSE "0011" WHEN (dataa_clear = "3") ELSE "0000" ; dataa_clk <= '1' WHEN clk(conv_integer(dataa_clk_value)) = '1' ELSE '0'; dataa_aclr <= '1' WHEN (aclr(conv_integer(dataa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0'; dataa_sload <= '1' WHEN ena(conv_integer(dataa_clk_value)) = '1' ELSE '0'; dataa_bypass_register <= '1' WHEN (dataa_clock = "none") ELSE '0'; dataa_in <= dataa; dataa_input_register : hardcopyiii_mac_register GENERIC MAP ( data_width => dataa_width ) PORT MAP ( datain => dataa_in, clk => dataa_clk, aclr => dataa_aclr, sload => dataa_sload, bypass_register => dataa_bypass_register, dataout => dataa_in_reg ); --Instantiate the datab input Register datab_clk_value <= "0000" WHEN ((datab_clock = "0") or (datab_clock = "none")) ELSE "0001" WHEN (datab_clock = "1") ELSE "0010" WHEN (datab_clock = "2") ELSE "0011" WHEN (datab_clock = "3") ELSE "0000" ; datab_aclr_value <= "0000" WHEN ((datab_clear = "0") or (datab_clear = "none")) ELSE "0001" WHEN (datab_clear = "1") ELSE "0010" WHEN (datab_clear = "2") ELSE "0011" WHEN (datab_clear = "3") ELSE "0000" ; datab_clk <= '1' WHEN clk(conv_integer(datab_clk_value)) = '1' ELSE '0'; datab_aclr <= '1' WHEN (aclr(conv_integer(datab_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0'; datab_sload <= '1' WHEN ena(conv_integer(datab_clk_value)) = '1' ELSE '0'; datab_bypass_register <= '1' WHEN (datab_clock = "none") ELSE '0'; datab_in <= datab; datab_input_register : hardcopyiii_mac_register GENERIC MAP ( data_width => datab_width ) PORT MAP ( datain => datab_in, clk => datab_clk, aclr => datab_aclr, sload => datab_sload, bypass_register => datab_bypass_register, dataout => datab_in_reg ); --Instantiate the signa input Register signa_clk_value <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none")) ELSE "0001" WHEN (signa_clock = "1") ELSE "0010" WHEN (signa_clock = "2") ELSE "0011" WHEN (signa_clock = "3") ELSE "0000" ; signa_aclr_value <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none")) ELSE "0001" WHEN (signa_clear = "1") ELSE "0010" WHEN (signa_clear = "2") ELSE "0011" WHEN (signa_clear = "3") ELSE "0000" ; signa_clk <= '1' WHEN clk(conv_integer(signa_clk_value)) = '1' ELSE '0'; signa_aclr <= '1' WHEN (aclr(conv_integer(signa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0'; signa_sload <= '1' WHEN ena(conv_integer(signa_clk_value)) = '1' ELSE '0'; signa_bypass_register <= '1' WHEN (signa_clock = "none") ELSE '0'; signa_in <= signa; signa_input_register : hardcopyiii_mac_bit_register PORT MAP ( datain => signa_in, clk => signa_clk, aclr => signa_aclr, sload => signa_sload, bypass_register => signa_bypass_register, dataout => signa_in_reg ); --Instantiate the signb input Register signb_clk_value <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none")) ELSE "0001" WHEN (signb_clock = "1") ELSE "0010" WHEN (signb_clock = "2") ELSE "0011" WHEN (signb_clock = "3") ELSE "0000" ; signb_aclr_value <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none")) ELSE "0001" WHEN (signb_clear = "1") ELSE "0010" WHEN (signb_clear = "2") ELSE "0011" WHEN (signb_clear = "3") ELSE "0000" ; signb_clk <= '1' WHEN clk(conv_integer(signb_clk_value)) = '1' ELSE '0'; signb_aclr <= '1' WHEN (aclr(conv_integer(signb_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0'; signb_sload <= '1' WHEN ena(conv_integer(signb_clk_value)) = '1' ELSE '0'; signb_bypass_register <= '1' WHEN (signb_clock = "none") ELSE '0'; signb_in <= signb; signb_input_register : hardcopyiii_mac_bit_register PORT MAP ( datain => signb_in, clk => signb_clk, aclr => signb_aclr, sload => signb_sload, bypass_register => signb_bypass_register, dataout => signb_in_reg ); --Instantiate the scanouta input Register scanouta_clk_value <= "0000" WHEN ((scanouta_clock = "0") or (scanouta_clock = "none")) ELSE "0001" WHEN (scanouta_clock = "1") ELSE "0010" WHEN (scanouta_clock = "2") ELSE "0011" WHEN (scanouta_clock = "3") ELSE "0000" ; scanouta_aclr_value <= "0000" WHEN ((scanouta_clear = "0") or (scanouta_clear = "none")) ELSE "0001" WHEN (scanouta_clear = "1") ELSE "0010" WHEN (scanouta_clear = "2") ELSE "0011" WHEN (scanouta_clear = "3") ELSE "0000" ; scanouta_clk <= '1' WHEN clk(conv_integer(scanouta_clk_value)) = '1' ELSE '0'; scanouta_aclr <= '1' WHEN (aclr(conv_integer(scanouta_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0'; scanouta_sload <= '1' WHEN ena(conv_integer(scanouta_clk_value)) = '1' ELSE '0'; scanouta_bypass_register <= '1' WHEN (scanouta_clock = "none") ELSE '0'; scanouta_input_register : hardcopyiii_mac_register GENERIC MAP ( data_width => dataa_width ) PORT MAP ( datain => dataa_in_reg, clk => scanouta_clk, aclr => scanouta_aclr, sload => scanouta_sload, bypass_register => scanouta_bypass_register, dataout => scanouta ); --Instantiate mac_multiplier block signa_mult <= '0' WHEN (signa_internally_grounded = "true") ELSE signa_in_reg; signb_mult <= '0' WHEN (signb_internally_grounded = "true") ELSE signb_in_reg; mac_multiplier : hardcopyiii_mac_multiplier GENERIC MAP ( dataa_width => dataa_width, datab_width => datab_width ) PORT MAP ( dataa => dataa_in_reg, datab => datab_in_reg, signa => signa_mult, signb => signb_mult, dataout => dataout ); END arch; -------------------------------------------------------------------------------------------------- -- Module Name: hardcopyiii_fsa_isse -- -- Description: HARDCOPYIII first stage adder input selection and sign extension block. -- -------------------------------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_fsa_isse IS GENERIC ( dataa_width : integer := 36; datab_width : integer := 36; datac_width : integer := 36; datad_width : integer := 36; chainin_width : integer := 44; multa_signa_internally_grounded : string := "false"; multa_signb_internally_grounded : string := "false"; multb_signa_internally_grounded : string := "false"; multb_signb_internally_grounded : string := "false"; multc_signa_internally_grounded : string := "false"; multc_signb_internally_grounded : string := "false"; multd_signa_internally_grounded : string := "false"; multd_signb_internally_grounded : string := "false"; operation_mode : string := "output_only" ); PORT ( dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0); datab : IN std_logic_vector(datab_width - 1 DOWNTO 0); datac : IN std_logic_vector(datac_width - 1 DOWNTO 0); datad : IN std_logic_vector(datad_width - 1 DOWNTO 0); chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0); signa : IN std_logic := '0'; signb : IN std_logic := '0'; dataa_out : OUT std_logic_vector(71 DOWNTO 0); datab_out : OUT std_logic_vector(71 DOWNTO 0); datac_out : OUT std_logic_vector(71 DOWNTO 0); datad_out : OUT std_logic_vector(71 DOWNTO 0); chainin_out : OUT std_logic_vector(71 DOWNTO 0); operation : OUT std_logic_vector(3 DOWNTO 0) ); END hardcopyiii_fsa_isse; ARCHITECTURE arch OF hardcopyiii_fsa_isse IS signal dataa_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); signal datab_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); signal datac_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); signal datad_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); signal chainin_out_tmp: std_logic_vector(71 DOWNTO 0) := (others => '0'); signal sign :std_logic := '0'; BEGIN operation <= "0000" WHEN (operation_mode = "output_only") ELSE "0001" WHEN (operation_mode = "one_level_adder") ELSE "0010" WHEN (operation_mode = "loopback") ELSE "0011" WHEN (operation_mode = "accumulator") ELSE "0100" WHEN (operation_mode = "accumulator_chain_out") ELSE "0101" WHEN (operation_mode = "two_level_adder") ELSE "0110" WHEN (operation_mode = "two_level_adder_chain_out") ELSE "0111" WHEN (operation_mode = "36_bit_multiply") ELSE "1000" WHEN (operation_mode = "shift") ELSE "1001" WHEN (operation_mode = "double") ELSE "0000"; sign <= signa or signb; PROCESS( dataa,datab,datac,datad,chainin,signa,signb) variable active_signb : std_logic := '0'; variable active_signc : std_logic := '0'; variable active_signd : std_logic := '0'; variable read_new_param : std_logic := '0'; variable datab_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); variable datac_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); variable datad_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); variable datab_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); variable datac_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); variable datad_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); BEGIN IF ( multa_signa_internally_grounded = "false" AND multa_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "false" AND multb_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "false" AND multc_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "false" AND multd_signb_internally_grounded = "false") THEN read_new_param := '0' ; ELSE read_new_param := '1' ; END IF; IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN if (multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "true") then active_signb := signb; elsif(multb_signb_internally_grounded = "true" AND multb_signa_internally_grounded = "false" ) then active_signb := signa; elsif(multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "false") then active_signb := sign; else active_signb := '0'; end if; ELSE active_signb := sign; END IF; IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN if (multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "true") then active_signc := signb; elsif(multc_signb_internally_grounded = "true" AND multc_signa_internally_grounded = "false" ) then active_signc := signa; elsif(multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "false") then active_signc := sign; else active_signc := '0'; end if; ELSE active_signc := sign; END IF; IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN if (multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "true") then active_signd := signb; elsif(multd_signb_internally_grounded = "true" AND multd_signa_internally_grounded = "false" ) then active_signd := signa; elsif(multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "false") then active_signd := sign; else active_signd := '0'; end if; ELSE active_signd := sign; END IF; IF (dataa(dataa_width - 1) = '1' AND sign = '1') THEN dataa_out_tmp <= sxt(dataa(dataa_width - 1 DOWNTO 0), 72); ELSE dataa_out_tmp <= ext(dataa(dataa_width - 1 DOWNTO 0), 72); END IF; IF (datab(datab_width - 1) = '1' AND active_signb = '1') THEN datab_out_tim_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72); ELSE datab_out_tim_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72); END IF; IF (datac(datac_width - 1) = '1' AND active_signc = '1') THEN datac_out_tim_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72); ELSE datac_out_tim_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72); END IF; IF (datad(datad_width - 1) = '1' AND active_signd = '1') THEN datad_out_tim_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72); ELSE datad_out_tim_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72); END IF; IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN IF(datab(datab_width - 1) = '1' AND signb = '1') THEN datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72); ELSE datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72); END IF; ELSIF(operation_mode = "double") THEN IF(datab(datab_width - 1) = '1' AND signa = '1') THEN datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72); ELSE datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72); END IF; ELSE IF (datab(datab_width - 1) = '1' AND sign = '1') THEN datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72); ELSE datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72); END IF; END IF; IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN IF (datac(datac_width - 1) = '1' AND signa = '1') THEN datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72); ELSE datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72); END IF; ELSE IF (datac(datac_width - 1) = '1' AND sign = '1') THEN datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72); ELSE datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72); END IF; END IF; IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72); ELSIF(operation_mode = "double")THEN IF (datad(datad_width - 1) = '1' AND signa = '1') THEN datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72); ELSE datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72); END IF; ELSE IF (datad(datad_width - 1) = '1' AND sign = '1') THEN datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72); ELSE datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72); END IF; END IF; IF (chainin(chainin_width - 1) = '1') THEN chainin_out_tmp <= sxt(chainin(chainin_width - 1 DOWNTO 0), 72); ELSE chainin_out_tmp <= ext(chainin(chainin_width - 1 DOWNTO 0), 72); END IF; IF(read_new_param = '1') THEN datab_out_tmp <= datab_out_tim_tmp; datac_out_tmp <= datac_out_tim_tmp; datad_out_tmp <= datad_out_tim_tmp; ELSE datab_out_tmp <= datab_out_fun_tmp; datac_out_tmp <= datac_out_fun_tmp; datad_out_tmp <= datad_out_fun_tmp; END IF; END process; dataa_out <= dataa_out_tmp; datab_out <= datab_out_tmp; datac_out <= datac_out_tmp; datad_out <= datad_out_tmp; chainin_out <= chainin_out_tmp; END arch; -------------------------------------------------------------------------------------------------- -- Module Name: hardcopyiii_first_stage_add_sub -- -- Description: HARDCOPYIII First Stage Adder Subtractor Unit -- -------------------------------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_first_stage_add_sub IS GENERIC ( dataa_width : integer := 36; datab_width : integer := 36; fsa_mode : string := "add"; tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01); tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01); tipd_sign : VitalDelayType01 :=DefPropDelay01; tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01); tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01); tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01); XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn ); PORT ( dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); sign : IN std_logic := '0'; operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0'); dataout : OUT std_logic_vector(71 DOWNTO 0) ); END hardcopyiii_first_stage_add_sub; ARCHITECTURE arch OF hardcopyiii_first_stage_add_sub IS SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL sign_a : std_logic := '0'; SIGNAL sign_b : std_logic := '0'; SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL sign_ipd : std_logic := '0'; BEGIN WireDelay : block begin g1 :for i in dataa'range generate VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i)); end generate; g2 :for i in datab'range generate VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i)); end generate; VitalWireDelay (sign_ipd, sign, tipd_sign); end block; PROCESS BEGIN WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR operation'EVENT; IF ((operation = "0111") OR (operation = "1000")or (operation = "1001")) THEN --36 std_logic multiply, shift and add dataout_tmp <= dataa_ipd(53 DOWNTO 36) & dataa_ipd(35 DOWNTO 0) & "000000000000000000" + datab_ipd; ELSE IF(fsa_mode = "add")THEN IF (sign_ipd = '1') THEN dataout_tmp <= signed(dataa_ipd) + signed(datab_ipd); ELSE dataout_tmp <= unsigned(dataa_ipd) + unsigned(datab_ipd); END IF; ELSE IF (sign_ipd = '1') THEN dataout_tmp <= signed(dataa_ipd) - signed(datab_ipd); ELSE dataout_tmp <= unsigned(dataa_ipd) - unsigned(datab_ipd); END IF; END IF; END IF; END process ; PathDelay : block begin do1 : for i in dataout'range generate process(dataout_tmp(i)) VARIABLE dataout_VitalGlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => dataout(i), OutSignalName => "dataout", OutTemp => dataout_tmp(i), Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE), 1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE), 2 => (sign'last_event, tpd_sign_dataout(i), TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, MsgOn => FALSE, XOn => TRUE ); end process; end generate do1; end block; END arch; -------------------------------------------------------------------------------------------------- -- Module Name: hardcopyiii_second_stage_add_accum -- -- Description: HARDCOPYIII Second stage Adder and Accumulator/Decimator Unit -- -------------------------------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_second_stage_add_accum IS GENERIC ( dataa_width : integer := 36; datab_width : integer := 36; ssa_mode : string := "add"; tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01); tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01); tipd_accumin : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01); tipd_sign : VitalDelayType01 :=DefPropDelay01; tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01); tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01); tpd_accumin_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01); tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01); tpd_dataa_overflow : VitalDelayType01 := DefPropDelay01; tpd_datab_overflow : VitalDelayType01 := DefPropDelay01; tpd_accumin_overflow : VitalDelayType01 := DefPropDelay01; tpd_sign_overflow : VitalDelayType01 := DefPropDelay01; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn ); PORT ( dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); sign : IN std_logic := '0'; operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0'); dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'); overflow : OUT std_logic ); END hardcopyiii_second_stage_add_accum; ARCHITECTURE arch OF hardcopyiii_second_stage_add_accum IS constant accum_width : integer := dataa_width + 7; SIGNAL dataout_temp : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL dataa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL datab_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL accum_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL overflow_tmp : std_logic := '0'; SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL accumin_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL sign_ipd : std_logic := '0'; SIGNAL signb_ipd : std_logic := '0'; BEGIN WireDelay : block begin g1 :for i in dataa'range generate VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i)); end generate; g2 :for i in datab'range generate VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i)); end generate; g3 :for i in accumin'range generate VitalWireDelay (accumin_ipd(i), accumin(i), tipd_accumin(i)); end generate; VitalWireDelay (sign_ipd, sign, tipd_sign); end block; PROCESS Variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); BEGIN WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR accumin_ipd'EVENT OR operation'EVENT; IF (operation = "0011" OR operation = "0100") THEN --Accumultor or Accumulator chainout IF(ssa_mode = "add")THEN IF (sign_ipd = '1') THEN dataout_tmp := signed(sxt(accumin_ipd(accum_width-1 downto 0),72)) + signed(sxt(dataa_ipd(accum_width-1 downto 0),72)) + signed(sxt(datab_ipd(accum_width-1 downto 0),72)); ELSE dataout_tmp := unsigned(ext(accumin_ipd(accum_width-1 downto 0),72)) + unsigned(ext(dataa_ipd(accum_width-1 downto 0),72)) + unsigned(ext(datab_ipd(accum_width-1 downto 0),72)); END IF; ELSE IF (sign_ipd = '1') THEN dataout_tmp := signed(accumin_ipd) - signed(dataa_ipd)- signed(datab_ipd); ELSE dataout_tmp := unsigned(accumin_ipd) - unsigned(dataa_ipd)- unsigned(datab_ipd); END IF; END IF; IF(sign_ipd = '1')THEN overflow_tmp <= dataout_tmp(accum_width) xor dataout_tmp(accum_width -1); ELSE IF(ssa_mode = "add")THEN overflow_tmp <= dataout_tmp(accum_width); ELSE overflow_tmp <= 'X'; END IF; END IF; ELSIF (operation = "0101" OR operation = "0110") THEN -- two level adder or two level with chainout overflow_tmp <= '0'; IF (sign_ipd = '1') THEN dataout_tmp := signed(dataa_ipd) + signed(datab_ipd); ELSE dataout_tmp := unsigned(dataa_ipd) + unsigned(datab_ipd); END IF; ELSIF ((operation = "0111") OR (operation = "1000")) THEN --36 std_logic multiply; shift and add dataout_tmp(71 DOWNTO 0) := dataa_ipd(53 DOWNTO 0) & "000000000000000000" + datab_ipd; overflow_tmp <= '0'; ELSIF ((operation = "1001")) THEN --double mode dataout_tmp(71 DOWNTO 0) := dataa_ipd + datab_ipd; overflow_tmp <= '0'; END IF; dataout_temp <= dataout_tmp; END PROCESS; PathDelay : block begin do1 : for i in dataout'range generate process(dataout_temp(i)) VARIABLE dataout_VitalGlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => dataout(i), OutSignalName => "dataout", OutTemp => dataout_temp(i), Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE), 1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE), 2 => (accumin_ipd'last_event, tpd_accumin_dataout(i), TRUE), 3 => (sign'last_event, tpd_sign_dataout(i), TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, MsgOn => FALSE, XOn => TRUE ); end process; end generate do1; process(overflow_tmp) VARIABLE overflow_VitalGlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => overflow, OutSignalName => "overflow", OutTemp => overflow_tmp, paths => (0 => (dataa_ipd'last_event, tpd_dataa_overflow, TRUE), 1 => (datab_ipd'last_event, tpd_datab_overflow, TRUE), 2 => (accumin_ipd'last_event, tpd_accumin_overflow, TRUE), 3 => (sign'last_event, tpd_sign_overflow, TRUE)), GlitchData => overflow_VitalGlitchData, Mode => DefGlitchMode, XOn => TRUE, MsgOn => TRUE ); end process; end block; END arch; -------------------------------------------------------------------------------------------------- -- Module Name: hardcopyiii_round_block -- -- Description: HARDCOPYIII round block -- -------------------------------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_round_block IS GENERIC ( round_mode : string := "nearest_integer"; round_width : integer := 15; operation_mode : string := "output_only" ); PORT ( datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); round : IN std_logic := '0'; datain_width : IN std_logic_vector(7 DOWNTO 0):= (others => '0'); dataout : OUT std_logic_vector(71 DOWNTO 0) ); END hardcopyiii_round_block; ARCHITECTURE arch OF hardcopyiii_round_block IS signal out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); BEGIN dataout <= out_tmp ; PROCESS(datain,round,datain_width) variable i : integer ; variable j : integer ; variable sign : std_logic ; variable result_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); variable dataout_value : std_logic_vector(71 DOWNTO 0) := (others => '0'); BEGIN if(round = '0')then dataout_value := datain; else dataout_value := datain; j := 0; sign := '0'; IF( conv_integer(datain_width) > round_width) THEN for i in ((conv_integer(datain_width)) - round_width) to (conv_integer(datain_width) -1) loop result_tmp(j) := datain(i); j := j + 1; END LOOP; for i in 0 to (conv_integer(datain_width) - round_width -2) loop sign := sign or datain(i); dataout_value(i) := 'X'; END LOOP; dataout_value((conv_integer(datain_width)) - round_width -1) := 'X'; IF (datain(conv_integer(datain_width) - round_width -1) = '0') THEN -- fractional < 0.5 dataout_tmp := result_tmp; ELSE IF ((datain(conv_integer(datain_width) - round_width -1) = '1') AND (sign = '1')) THEN --fractional > 0.5 dataout_tmp := result_tmp + '1'; ELSE IF (round_mode = "nearest_even") THEN --unbiased rounding IF(result_tmp(0) = '1') THEN --check for odd integer dataout_tmp := result_tmp + '1' ; ELSE dataout_tmp := result_tmp; END IF; ELSE --biased rounding dataout_tmp := result_tmp + '1'; END IF; END IF; END IF; j := conv_integer(datain_width) - round_width; FOR i IN 0 to (round_width -1)LOOP dataout_value(j) := dataout_tmp(i); j := j + 1; END LOOP; ELSE dataout_value := datain; END IF; end if; out_tmp <= dataout_value; END PROCESS; END arch; -------------------------------------------------------------------------------------------------- -- Module Name: hardcopyiii_saturate_block -- -- Description: HARDCOPYIII saturation block -- -------------------------------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_saturate_block IS GENERIC ( dataa_width : integer := 36; datab_width : integer := 36; saturate_width : integer := 15; round_width : integer := 15; saturate_mode : string := " asymmetric"; operation_mode : string := "output_only" ); PORT ( datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); saturate : IN std_logic := '0'; round : IN std_logic := '0'; signa : IN std_logic := '0'; signb : IN std_logic := '0'; datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0'); dataout : OUT std_logic_vector(71 DOWNTO 0):= (others => '0'); saturation_overflow : OUT std_logic ); END hardcopyiii_saturate_block; ARCHITECTURE arch OF hardcopyiii_saturate_block IS constant accum_width : integer := dataa_width + 8; SIGNAL saturation_overflow_tmp : std_logic := '0'; signal msb : std_logic := '0'; signal sign : std_logic := '0'; signal min : std_logic_vector(71 downto 0):=(others => '1'); signal max : std_logic_vector(71 downto 0):=(others => '0'); signal dataout_tmp : std_logic_vector(71 DOWNTO 0):= (others => '0'); SIGNAL i : integer; BEGIN sign <= signa OR signb ; msb <= datain(accum_width) when ((operation_mode = "accumulator") or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out")) ELSE datain(dataa_width +1) when(operation_mode = "two_level_adder") ELSE datain(dataa_width) when((operation_mode = "one_level_adder")or (operation_mode = "loopback")) ELSE datain(dataa_width -1); dataout <= dataout_tmp ; saturation_overflow <= saturation_overflow_tmp ; PROCESS(datain,datain_width,round,saturate,sign,msb) variable saturation_temp : std_logic := '0'; variable sign_tmp : std_logic := '1'; variable data_tmp : std_logic := '0'; BEGIN IF (saturate = '0') THEN dataout_tmp <= datain; saturation_overflow_tmp <= '0'; ELSE saturation_temp := '0'; data_tmp := '0'; sign_tmp := '1'; IF (round = '1') THEN for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP min(i) <= 'X'; max(i) <= 'X'; END LOOP; END IF; IF (saturate_mode = "symmetric") THEN for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP IF (round = '1') THEN max(i) <= 'X'; min(i) <= 'X'; ELSE max(i) <= '1'; min(i) <= '0'; END IF; END LOOP; for i in (conv_integer(datain_width) - round_width) to (conv_integer(datain_width) - saturate_width -1) LOOP data_tmp := data_tmp or datain(i); max(i) <= '1'; min(i) <= '0'; END LOOP; IF (round = '1') THEN min(conv_integer(datain_width) - round_width) <= '1'; ELSE min(0) <= '1'; END IF; END IF; IF (saturate_mode = "asymmetric") THEN for i in 0 to (conv_integer(datain_width) - saturate_width -1) LOOP max(i) <= '1'; min(i) <= '0'; END LOOP; END IF; if((saturate_width = 1))then IF (msb /= datain(conv_integer(datain_width)-1)) THEN saturation_temp := '1'; ELSE sign_tmp := sign_tmp and datain(conv_integer(datain_width)-1); END IF; else for i in (conv_integer(datain_width) - saturate_width) to (conv_integer(datain_width)-1) LOOP sign_tmp := sign_tmp and datain(i); IF (datain(conv_integer(datain_width)-1) /= datain(i)) THEN saturation_temp := '1'; end if; END LOOP; end if; -- Trigger the saturation overflow for data=-2^n in case of symmetric saturation. if((sign_tmp ='1') and (data_tmp = '0') and (saturate_mode = "symmetric")) then saturation_temp := '1'; end if; saturation_overflow_tmp <= saturation_temp; IF (saturation_temp = '1') THEN IF ((operation_mode = "output_only")or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out")) THEN IF (msb = '1') THEN dataout_tmp <= min; ELSE dataout_tmp <= max; END IF; ELSE IF (sign = '1') THEN IF (msb = '1') THEN dataout_tmp <= min; ELSE dataout_tmp <= max; END IF; ELSE dataout_tmp <= (others => 'X'); END IF; END IF; ELSE dataout_tmp <= datain; END IF; END IF; END PROCESS; END arch; -------------------------------------------------------------------------------------------------- -- Module Name: hardcopyiii_round_saturate_block -- -- Description: HARDCOPYIII round and saturation Unit. -- -- This unit instantiated the following components. -- -- 1.hardcopyiii_round_block. -- -- 2.hardcopyiii_saturate_block. -- -------------------------------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_round_saturate_block IS GENERIC ( dataa_width : integer := 36; datab_width : integer := 36; saturate_width : integer := 15; round_width : integer := 15; saturate_mode : string := " asymmetric"; round_mode : string := "nearest_integer"; operation_mode : string := "output_only" ; tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01); tipd_round : VitalDelayType01 :=DefPropDelay01; tipd_saturate : VitalDelayType01 :=DefPropDelay01; tipd_signa : VitalDelayType01 :=DefPropDelay01; tipd_signb : VitalDelayType01 :=DefPropDelay01; tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01); tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01); tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01); tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01); tpd_signb_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01); tpd_datain_saturationoverflow : VitalDelayType01 := DefPropDelay01; tpd_round_saturationoverflow : VitalDelayType01 := DefPropDelay01; tpd_saturate_saturationoverflow : VitalDelayType01 := DefPropDelay01; tpd_signa_saturationoverflow : VitalDelayType01 := DefPropDelay01; tpd_signb_saturationoverflow : VitalDelayType01 := DefPropDelay01; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn ); PORT ( datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); round : IN std_logic := '0'; saturate : IN std_logic := '0'; signa : IN std_logic := '0'; signb : IN std_logic := '0'; datain_width : IN std_logic_vector(7 DOWNTO 0); dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'); saturationoverflow : OUT std_logic ); END hardcopyiii_round_saturate_block; ARCHITECTURE arch OF hardcopyiii_round_saturate_block IS COMPONENT hardcopyiii_round_block GENERIC ( round_mode : string := "nearest_integer"; round_width : integer := 15; operation_mode : string := "output_only" ); PORT ( datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); round : IN std_logic := '0'; datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0'); dataout : OUT std_logic_vector(71 DOWNTO 0) ); END COMPONENT; COMPONENT hardcopyiii_saturate_block GENERIC ( dataa_width : integer := 36; datab_width : integer := 36; saturate_mode : string := " asymmetric"; saturate_width : integer := 15; round_width : integer := 15; operation_mode : string := "output_only" ); PORT ( datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); saturate : IN std_logic := '0'; round : IN std_logic := '0'; signa : IN std_logic := '0'; signb : IN std_logic := '0'; datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0'); dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'); saturation_overflow : OUT std_logic ); END COMPONENT; SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL saturate_in : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL signa_ipd : std_logic := '0'; SIGNAL signb_ipd : std_logic := '0'; SIGNAL round_ipd : std_logic := '0'; SIGNAL saturate_ipd : std_logic := '0'; SIGNAL saturationoverflow_tmp : std_logic := '0'; BEGIN WireDelay : block begin g1 :for i in datain'range generate VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i)); end generate; VitalWireDelay (signa_ipd, signa, tipd_signa); VitalWireDelay (signb_ipd, signb, tipd_signb); VitalWireDelay (round_ipd, round, tipd_round); VitalWireDelay (saturate_ipd, saturate, tipd_saturate); end block; round_unit : hardcopyiii_round_block GENERIC MAP ( operation_mode => operation_mode, round_width => round_width, round_mode => round_mode ) PORT MAP ( datain => datain_ipd, round => round_ipd, datain_width => datain_width, dataout => dataout_round ); saturate_unit : hardcopyiii_saturate_block GENERIC MAP ( dataa_width => dataa_width, datab_width => datab_width, operation_mode => operation_mode, saturate_mode => saturate_mode, saturate_width =>saturate_width, round_width =>round_width ) PORT MAP ( datain => dataout_round, saturate => saturate_ipd, round => round_ipd, signa => signa_ipd, signb => signb_ipd, datain_width => datain_width, dataout => dataout_saturate, saturation_overflow => saturationoverflow_tmp ); PathDelay : block begin do1 : for i in dataout'range generate process(dataout_saturate(i)) VARIABLE dataout_VitalGlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => dataout(i), OutSignalName => "dataout", OutTemp => dataout_saturate(i), Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE), 1 => (round_ipd'last_event, tpd_round_dataout(i), TRUE), 2 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE), 3 => (signa'last_event, tpd_signa_dataout(i), TRUE), 4 => (signb'last_event, tpd_signb_dataout(i), TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, MsgOn => FALSE, XOn => TRUE ); end process; end generate do1; process(saturationoverflow_tmp) VARIABLE saturationoverflow_VitalGlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => saturationoverflow, OutSignalName => "saturationoverflow", OutTemp => saturationoverflow_tmp, Paths => (0 => (datain_ipd'last_event, tpd_datain_saturationoverflow, TRUE), 1 => (round_ipd'last_event, tpd_round_saturationoverflow, TRUE), 2 => (saturate_ipd'last_event, tpd_saturate_saturationoverflow, TRUE), 3 => (signa'last_event, tpd_signa_saturationoverflow, TRUE), 4 => (signb'last_event, tpd_signb_saturationoverflow, TRUE)), GlitchData => saturationoverflow_VitalGlitchData, Mode => DefGlitchMode, XOn => TRUE, MsgOn => TRUE ); end process; end block; END arch; -------------------------------------------------------------------------------------------------- -- Module Name: hardcopyiii_rotate_shift_block -- -- Description: HARDCOPYIII roate and shift Unit. -- -------------------------------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE ieee.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_rotate_shift_block IS GENERIC ( dataa_width : integer := 32; datab_width : integer := 32; tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01); tipd_rotate : VitalDelayType01 :=DefPropDelay01; tipd_shiftright : VitalDelayType01 :=DefPropDelay01; tipd_signa : VitalDelayType01 :=DefPropDelay01; tipd_signb : VitalDelayType01 :=DefPropDelay01; tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01); tpd_rotate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01); tpd_shiftright_dataout: VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01); tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01); XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn ); PORT ( datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); rotate : IN std_logic := '0'; shiftright : IN std_logic := '0'; signa : IN std_logic := '0'; signb : IN std_logic := '0'; dataout : OUT std_logic_vector(71 DOWNTO 0) ); END hardcopyiii_rotate_shift_block; ARCHITECTURE arch OF hardcopyiii_rotate_shift_block IS signal dataout_tmp : std_logic_vector(71 downto 0) := (others => '0'); SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL signa_ipd : std_logic := '0'; SIGNAL signb_ipd : std_logic := '0'; SIGNAL rotate_ipd : std_logic := '0'; SIGNAL shiftright_ipd : std_logic := '0'; SIGNAL sign : std_logic; BEGIN WireDelay : block begin g1 :for i in datain'range generate VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i)); end generate; VitalWireDelay (signa_ipd, signa, tipd_signa); VitalWireDelay (signb_ipd, signa, tipd_signa); VitalWireDelay (rotate_ipd, rotate, tipd_rotate); VitalWireDelay (shiftright_ipd, shiftright, tipd_shiftright); end block; PROCESS BEGIN WAIT UNTIL datain_ipd'EVENT OR rotate_ipd'EVENT OR shiftright_ipd'EVENT; sign <= signa_ipd xor signb_ipd; dataout_tmp <= datain; IF ((rotate_ipd = '0') AND (shiftright_ipd = '0')) THEN dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8); ELSIF ((rotate_ipd = '0') AND (shiftright_ipd = '1')) THEN --shift right dataout_tmp(39 downto 8) <= datain_ipd(71 downto 40); ELSIF((rotate_ipd = '1') AND (shiftright_ipd = '0')) THEN dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8) OR datain_ipd(71 downto 40); ELSE dataout_tmp <= datain_ipd; END IF; END PROCESS; PathDelay : block begin do1 : for i in dataout'range generate process(dataout_tmp(i)) VARIABLE dataout_VitalGlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => dataout(i), OutSignalName => "dataout", OutTemp => dataout_tmp(i), Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE), 1 => (rotate_ipd'last_event, tpd_rotate_dataout(i), TRUE), 2 => (shiftright_ipd'last_event, tpd_shiftright_dataout(i), TRUE), 3 => (signa'last_event, tpd_signa_dataout(i), TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, MsgOn => FALSE, XOn => TRUE ); end process; end generate do1; end block; END arch; -------------------------------------------------------------------------------------------------- -- Module Name: hardcopyiii_carry_chain_adder -- -- Description: HARDCOPYIII carry Chain Adder -- -------------------------------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_carry_chain_adder IS GENERIC( tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01); tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01); tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01); tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01); XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn ); PORT ( dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); dataout : OUT STD_LOGIC_vector(71 DOWNTO 0) ); END hardcopyiii_carry_chain_adder; ARCHITECTURE arch OF hardcopyiii_carry_chain_adder IS SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); BEGIN WireDelay : block begin g1 :for i in dataa'range generate VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i)); end generate; g2 :for i in datab'range generate VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i)); end generate; end block; dataout_tmp <= (dataa_ipd(71 downto 45) & dataa_ipd(43) & dataa_ipd(43 downto 0)) + (datab_ipd(71 downto 45) & datab_ipd(43) & datab_ipd(43 downto 0)) ; PathDelay : block begin do1 : for i in dataout'range generate process(dataout_tmp(i)) VARIABLE dataout_VitalGlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => dataout(i), OutSignalName => "dataout", OutTemp => dataout_tmp(i), Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE), 1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, MsgOn => FALSE, XOn => TRUE ); end process; end generate do1; end block; END arch; ---------------------------------------------------------------------------------- -- Module Name: hardcopyiii_mac_out_atom -- -- Description: Simulation model for hardcopyiii mac out atom -- -- This model instantiates the following components -- -- 1.hardcopyiii_mac_bit_register -- -- 2.hardcopyiii_mac_register -- -- 3.hardcopyiii_fsa_isse -- -- 4.hardcopyiii_first_stage_add_sub -- -- 5.hardcopyiii_second_stage_add_accum -- -- 6.hardcopyiii_round_saturate_block -- -- 7.hardcopyiii_rotate_shift_block -- -- 8.hardcopyiii_carry_chain_adder -- ---------------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; ENTITY hardcopyiii_mac_out IS GENERIC ( operation_mode : string := "output_only"; dataa_width : integer := 1; datab_width : integer := 1; datac_width : integer := 1; datad_width : integer := 1; chainin_width : integer := 1; round_width : integer := 15; round_chain_out_width : integer := 15; saturate_width : integer := 15; saturate_chain_out_width : integer := 15; first_adder0_clock : string := "none"; first_adder0_clear : string := "none"; first_adder1_clock : string := "none"; first_adder1_clear : string := "none"; second_adder_clock : string := "none"; second_adder_clear : string := "none"; output_clock : string := "none"; output_clear : string := "none"; signa_clock : string := "none"; signa_clear : string := "none"; signb_clock : string := "none"; signb_clear : string := "none"; round_clock : string := "none"; round_clear : string := "none"; roundchainout_clock : string := "none"; roundchainout_clear : string := "none"; saturate_clock : string := "none"; saturate_clear : string := "none"; saturatechainout_clock : string := "none"; saturatechainout_clear : string := "none"; zeroacc_clock : string := "none"; zeroacc_clear : string := "none"; zeroloopback_clock : string := "none"; zeroloopback_clear : string := "none"; rotate_clock : string := "none"; rotate_clear : string := "none"; shiftright_clock : string := "none"; shiftright_clear : string := "none"; signa_pipeline_clock : string := "none"; signa_pipeline_clear : string := "none"; signb_pipeline_clock : string := "none"; signb_pipeline_clear : string := "none"; round_pipeline_clock : string := "none"; round_pipeline_clear : string := "none"; roundchainout_pipeline_clock : string := "none"; roundchainout_pipeline_clear : string := "none"; saturate_pipeline_clock : string := "none"; saturate_pipeline_clear : string := "none"; saturatechainout_pipeline_clock: string := "none"; saturatechainout_pipeline_clear: string := "none"; zeroacc_pipeline_clock : string := "none"; zeroacc_pipeline_clear : string := "none"; zeroloopback_pipeline_clock : string := "none"; zeroloopback_pipeline_clear : string := "none"; rotate_pipeline_clock : string := "none"; rotate_pipeline_clear : string := "none"; shiftright_pipeline_clock : string := "none"; shiftright_pipeline_clear : string := "none"; roundchainout_output_clock : string := "none"; roundchainout_output_clear : string := "none"; saturatechainout_output_clock : string := "none"; saturatechainout_output_clear : string := "none"; zerochainout_output_clock : string := "none"; zerochainout_output_clear : string := "none"; zeroloopback_output_clock : string := "none"; zeroloopback_output_clear : string := "none"; rotate_output_clock : string := "none"; rotate_output_clear : string := "none"; shiftright_output_clock : string := "none"; shiftright_output_clear : string := "none"; first_adder0_mode : string := "add"; first_adder1_mode : string := "add"; acc_adder_operation : string := "add"; round_mode : string := "nearest_integer"; round_chain_out_mode : string := "nearest_integer"; saturate_mode : string := "asymmetric"; saturate_chain_out_mode : string := "asymmetric"; multa_signa_internally_grounded : string := "false"; multa_signb_internally_grounded : string := "false"; multb_signa_internally_grounded : string := "false"; multb_signb_internally_grounded : string := "false"; multc_signa_internally_grounded : string := "false"; multc_signb_internally_grounded : string := "false"; multd_signa_internally_grounded : string := "false"; multd_signb_internally_grounded : string := "false"; lpm_type : string := "hardcopyiii_mac_out"; dataout_width : integer:=72 ); PORT ( dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1'); datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1'); datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1'); datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1'); signa : IN std_logic := '1'; signb : IN std_logic := '1'; chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0'); round : IN std_logic := '0'; saturate : IN std_logic := '0'; zeroacc : IN std_logic := '0'; roundchainout : IN std_logic := '0'; saturatechainout : IN std_logic := '0'; zerochainout : IN std_logic := '0'; zeroloopback : IN std_logic := '0'; rotate : IN std_logic := '0'; shiftright : IN std_logic := '0'; clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0'); ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1'); aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0'); loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0'); dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'); overflow : OUT std_logic := '0'; saturatechainoutoverflow: OUT std_logic := '0'; dftout : OUT std_logic := '0'; devpor : IN std_logic := '1'; devclrn : IN std_logic := '1' ); END hardcopyiii_mac_out; ARCHITECTURE arch OF hardcopyiii_mac_out IS COMPONENT hardcopyiii_mac_bit_register PORT ( datain : IN std_logic := '0'; clk : IN std_logic := '0'; aclr : IN std_logic := '0'; sload : IN std_logic := '0'; bypass_register : IN std_logic := '0'; dataout : OUT std_logic ); END COMPONENT; COMPONENT hardcopyiii_mac_register GENERIC ( data_width : integer := 18 ); PORT ( datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0'); clk : IN std_logic := '0'; aclr : IN std_logic := '0'; sload : IN std_logic := '0'; bypass_register : IN std_logic := '0'; dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0) ); END COMPONENT; COMPONENT hardcopyiii_fsa_isse GENERIC ( datab_width : integer := 36; dataa_width : integer := 36; chainin_width : integer := 44; operation_mode : string := "output_only"; datad_width : integer := 36; multa_signa_internally_grounded : string := "false"; multa_signb_internally_grounded : string := "false"; multb_signa_internally_grounded : string := "false"; multb_signb_internally_grounded : string := "false"; multc_signa_internally_grounded : string := "false"; multc_signb_internally_grounded : string := "false"; multd_signa_internally_grounded : string := "false"; multd_signb_internally_grounded : string := "false"; datac_width : integer := 36 ); PORT ( dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0'); datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0'); datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '0'); datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '0'); chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0'); signa : IN std_logic := '0'; signb : IN std_logic := '0'; dataa_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'); datab_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'); datac_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'); datad_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'); chainin_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'); operation : OUT std_logic_vector(3 DOWNTO 0) ); END COMPONENT; COMPONENT hardcopyiii_first_stage_add_sub GENERIC ( dataa_width : integer := 36; datab_width : integer := 36; fsa_mode : string := "add" ); PORT ( dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); sign : IN std_logic := '0'; operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0'); dataout : OUT std_logic_vector(71 DOWNTO 0) ); END COMPONENT; COMPONENT hardcopyiii_second_stage_add_accum GENERIC ( dataa_width : integer := 36; datab_width : integer := 36; ssa_mode : string := "add" ); PORT ( dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); sign : IN std_logic := '0'; operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0'); dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'); overflow : OUT std_logic ); END COMPONENT; COMPONENT hardcopyiii_round_saturate_block GENERIC ( datab_width : integer := 36; dataa_width : integer := 36; saturate_mode : string := " asymmetric"; saturate_width : integer := 15; round_width : integer := 15; operation_mode : string := "output_only"; round_mode : string := "nearest_integer" ); PORT ( datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); round : IN std_logic := '0'; saturate : IN std_logic := '0'; signa : IN std_logic := '0'; signb : IN std_logic := '0'; datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0'); dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'); saturationoverflow : OUT std_logic ); END COMPONENT; COMPONENT hardcopyiii_rotate_shift_block GENERIC ( datab_width : integer := 32; dataa_width : integer := 32 ); PORT ( datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); rotate : IN std_logic := '0'; shiftright : IN std_logic := '0'; signa : IN std_logic := '0'; signb : IN std_logic := '0'; dataout : OUT std_logic_vector(71 DOWNTO 0) ); END COMPONENT; COMPONENT hardcopyiii_carry_chain_adder PORT ( dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0'); dataout : OUT std_logic_vector(71 DOWNTO 0) ); END COMPONENT; --signals for zeroloopback input register SIGNAL zeroloopback_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL zeroloopback_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL zeroloopback_clk_ir : std_logic := '0'; SIGNAL zeroloopback_aclr_ir : std_logic := '0'; SIGNAL zeroloopback_sload_ir : std_logic := '0'; SIGNAL zeroloopback_bypass_register_ir : std_logic := '0'; SIGNAL zeroloopback_in_reg : std_logic := '0'; SIGNAL zeroloopback_in : std_logic := '0'; --signals for zeroacc input register SIGNAL zeroacc_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL zeroacc_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL zeroacc_clk_ir : std_logic := '0'; SIGNAL zeroacc_aclr_ir : std_logic := '0'; SIGNAL zeroacc_sload_ir : std_logic := '0'; SIGNAL zeroacc_bypass_register_ir : std_logic := '0'; SIGNAL zeroacc_in_reg : std_logic := '0'; SIGNAL zeroacc_in : std_logic := '0'; --Signals for signa input register SIGNAL signa_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL signa_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL signa_clk_ir : std_logic := '0'; SIGNAL signa_aclr_ir : std_logic := '0'; SIGNAL signa_sload_ir : std_logic := '0'; SIGNAL signa_bypass_register_ir : std_logic := '0'; SIGNAL signa_in_reg : std_logic := '0'; SIGNAL signa_in : std_logic := '0'; --signals for signb input register SIGNAL signb_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL signb_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL signb_clk_ir : std_logic := '0'; SIGNAL signb_aclr_ir : std_logic := '0'; SIGNAL signb_sload_ir : std_logic := '0'; SIGNAL signb_bypass_register_ir : std_logic := '0'; SIGNAL signb_in_reg : std_logic := '0'; SIGNAL signb_in : std_logic := '0'; --signals for rotate input register SIGNAL rotate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL rotate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL rotate_clk_ir : std_logic := '0'; SIGNAL rotate_aclr_ir : std_logic := '0'; SIGNAL rotate_sload_ir : std_logic := '0'; SIGNAL rotate_bypass_register_ir: std_logic := '0'; SIGNAL rotate_in_reg : std_logic := '0'; SIGNAL rotate_in : std_logic := '0'; --signals for shiftright input register SIGNAL shiftright_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL shiftright_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL shiftright_clk_ir : std_logic := '0'; SIGNAL shiftright_aclr_ir : std_logic := '0'; SIGNAL shiftright_sload_ir : std_logic := '0'; SIGNAL shiftright_bypass_register_ir : std_logic := '0'; SIGNAL shiftright_in_reg : std_logic := '0'; SIGNAL shiftright_in : std_logic := '0'; --signals for round input register SIGNAL round_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL round_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL round_clk_ir : std_logic := '0'; SIGNAL round_aclr_ir : std_logic := '0'; SIGNAL round_sload_ir : std_logic := '0'; SIGNAL round_bypass_register_ir : std_logic := '0'; SIGNAL round_in_reg : std_logic := '0'; SIGNAL round_in : std_logic := '0'; --signals for saturate input register SIGNAL saturate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL saturate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL saturate_clk_ir : std_logic := '0'; SIGNAL saturate_aclr_ir : std_logic := '0'; SIGNAL saturate_sload_ir : std_logic := '0'; SIGNAL saturate_bypass_register_ir : std_logic := '0'; SIGNAL saturate_in_reg : std_logic := '0'; SIGNAL saturate_in : std_logic := '0'; --signals for roundchainout input register SIGNAL roundchainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL roundchainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL roundchainout_clk_ir : std_logic := '0'; SIGNAL roundchainout_aclr_ir : std_logic := '0'; SIGNAL roundchainout_sload_ir : std_logic := '0'; SIGNAL roundchainout_bypass_register_ir: std_logic := '0'; SIGNAL roundchainout_in_reg : std_logic := '0'; SIGNAL roundchainout_in : std_logic := '0'; --signals for saturatechainout input register SIGNAL saturatechainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL saturatechainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL saturatechainout_clk_ir : std_logic := '0'; SIGNAL saturatechainout_aclr_ir : std_logic := '0'; SIGNAL saturatechainout_sload_ir: std_logic := '0'; SIGNAL saturatechainout_bypass_register_ir: std_logic := '0'; SIGNAL saturatechainout_in_reg : std_logic := '0'; SIGNAL saturatechainout_in : std_logic := '0'; --signals for fsa_input_interface SIGNAL dataa_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL datab_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL datac_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL datad_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL chainin_coa_in : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0'); --Signals for First Stage Adder units SIGNAL dataout_fsa0 : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL fsa_pip_datain1 : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL dataout_fsa1 : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL overflow_fsa0 : std_logic := '0'; SIGNAL overflow_fsa1 : std_logic := '0'; --signals for zeroloopback pipeline register SIGNAL zeroloopback_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL zeroloopback_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL zeroloopback_clk_pip : std_logic := '0'; SIGNAL zeroloopback_aclr_pip : std_logic := '0'; SIGNAL zeroloopback_sload_pip : std_logic := '0'; SIGNAL zeroloopback_bypass_register_pip: std_logic := '0'; SIGNAL zeroloopback_pip_reg : std_logic := '0'; --signals for zeroacc pipeline register SIGNAL zeroacc_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL zeroacc_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL zeroacc_clk_pip : std_logic := '0'; SIGNAL zeroacc_aclr_pip : std_logic := '0'; SIGNAL zeroacc_sload_pip : std_logic := '0'; SIGNAL zeroacc_bypass_register_pip : std_logic := '0'; SIGNAL zeroacc_pip_reg : std_logic := '0'; --Signals for signa pipeline register SIGNAL signa_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL signa_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL signa_clk_pip : std_logic := '0'; SIGNAL signa_aclr_pip : std_logic := '0'; SIGNAL signa_sload_pip : std_logic := '0'; SIGNAL signa_bypass_register_pip: std_logic := '0'; SIGNAL signa_pip_reg : std_logic := '0'; --signals for signb pipeline register SIGNAL signb_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL signb_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL signb_clk_pip : std_logic := '0'; SIGNAL signb_aclr_pip : std_logic := '0'; SIGNAL signb_sload_pip : std_logic := '0'; SIGNAL signb_bypass_register_pip: std_logic := '0'; SIGNAL signb_pip_reg : std_logic := '0'; --signals for rotate pipeline register SIGNAL rotate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL rotate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL rotate_clk_pip : std_logic := '0'; SIGNAL rotate_aclr_pip : std_logic := '0'; SIGNAL rotate_sload_pip : std_logic := '0'; SIGNAL rotate_bypass_register_pip : std_logic := '0'; SIGNAL rotate_pip_reg : std_logic := '0'; --signals for shiftright pipeline register SIGNAL shiftright_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL shiftright_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL shiftright_clk_pip : std_logic := '0'; SIGNAL shiftright_aclr_pip : std_logic := '0'; SIGNAL shiftright_sload_pip : std_logic := '0'; SIGNAL shiftright_bypass_register_pip : std_logic := '0'; SIGNAL shiftright_pip_reg : std_logic := '0'; --signals for round pipeline register SIGNAL round_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL round_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL round_clk_pip : std_logic := '0'; SIGNAL round_aclr_pip : std_logic := '0'; SIGNAL round_sload_pip : std_logic := '0'; SIGNAL round_bypass_register_pip: std_logic := '0'; SIGNAL round_pip_reg : std_logic := '0'; --signals for saturate pipeline register SIGNAL saturate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL saturate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL saturate_clk_pip : std_logic := '0'; SIGNAL saturate_aclr_pip : std_logic := '0'; SIGNAL saturate_sload_pip : std_logic := '0'; SIGNAL saturate_bypass_register_pip : std_logic := '0'; SIGNAL saturate_pip_reg : std_logic := '0'; --signals for roundchainout pipeline register SIGNAL roundchainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL roundchainout_aclrval_pip: std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL roundchainout_clk_pip : std_logic := '0'; SIGNAL roundchainout_aclr_pip : std_logic := '0'; SIGNAL roundchainout_sload_pip : std_logic := '0'; SIGNAL roundchainout_bypass_register_pip: std_logic := '0'; SIGNAL roundchainout_pip_reg : std_logic := '0'; --signals for saturatechainout pipeline register SIGNAL saturatechainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL saturatechainout_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL saturatechainout_clk_pip : std_logic := '0'; SIGNAL saturatechainout_aclr_pip: std_logic := '0'; SIGNAL saturatechainout_sload_pip : std_logic := '0'; SIGNAL saturatechainout_bypass_register_pip: std_logic := '0'; SIGNAL saturatechainout_pip_reg : std_logic := '0'; --signals for fsa0 pipeline register SIGNAL fsa0_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL fsa0_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL fsa0_clk_pip : std_logic := '0'; SIGNAL fsa0_aclr_pip : std_logic := '0'; SIGNAL fsa0_sload_pip : std_logic := '0'; SIGNAL fsa0_bypass_register_pip : std_logic := '0'; SIGNAL fsa0_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0'); --signals for fsa1 pipeline register SIGNAL fsa1_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL fsa1_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL fsa1_clk_pip : std_logic := '0'; SIGNAL fsa1_aclr_pip : std_logic := '0'; SIGNAL fsa1_sload_pip : std_logic := '0'; SIGNAL fsa1_bypass_register_pip : std_logic := '0'; SIGNAL fsa1_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0'); --Signals for second stage adder SIGNAL ssa_accum_in : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL ssa_sign : std_logic := '0'; SIGNAL ssa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL ssa_overflow : std_logic := '0'; --Signals for RS block SIGNAL rs_datain : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL rs_dataout_of : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL rs_dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL rs_saturation_overflow : std_logic := '0'; SIGNAL ssa_datain_width : std_logic_vector(7 DOWNTO 0); SIGNAL ssa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0'); --signals for zeroloopback output register SIGNAL zeroloopback_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL zeroloopback_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL zeroloopback_clk_or : std_logic := '0'; SIGNAL zeroloopback_aclr_or : std_logic := '0'; SIGNAL zeroloopback_sload_or : std_logic := '0'; SIGNAL zeroloopback_bypass_register_or : std_logic := '0'; SIGNAL zeroloopback_out_reg : std_logic := '0'; --signals for zerochainout output register SIGNAL zerochainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL zerochainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL zerochainout_clk_or : std_logic := '0'; SIGNAL zerochainout_aclr_or : std_logic := '0'; SIGNAL zerochainout_sload_or : std_logic := '0'; SIGNAL zerochainout_bypass_register_or : std_logic := '0'; SIGNAL zerochainout_out_reg : std_logic := '0'; --Signals for saturation_overflow output register SIGNAL rs_saturation_overflow_in : std_logic := '0'; SIGNAL saturation_overflow_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL saturation_overflow_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL saturation_overflow_clk_or : std_logic := '0'; SIGNAL saturation_overflow_aclr_or : std_logic := '0'; SIGNAL saturation_overflow_sload_or : std_logic := '0'; SIGNAL saturation_overflow_bypass_register_or: std_logic := '0'; SIGNAL saturation_overflow_out_reg : std_logic := '0'; --signals for rs_dataout output register SIGNAL rs_dataout_in : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL rs_dataout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL rs_dataout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL rs_dataout_clkval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL rs_dataout_aclrval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL rs_dataout_clkval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL rs_dataout_aclrval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL rs_dataout_clk_or : std_logic := '0'; SIGNAL rs_dataout_aclr_or : std_logic := '0'; SIGNAL rs_dataout_sload_or : std_logic := '0'; SIGNAL rs_dataout_bypass_register_or_co : std_logic := '0'; SIGNAL rs_dataout_bypass_register_or_o : std_logic := '0'; SIGNAL rs_dataout_bypass_register_or : std_logic := '0'; SIGNAL rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL rs_saturation_overflow_out_reg : std_logic := '0'; --signals for rotate output register SIGNAL rotate_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL rotate_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL rotate_clk_or : std_logic := '0'; SIGNAL rotate_aclr_or : std_logic := '0'; SIGNAL rotate_sload_or : std_logic := '0'; SIGNAL rotate_bypass_register_or: std_logic := '0'; SIGNAL rotate_out_reg : std_logic := '0'; --signals for shiftright output register SIGNAL shiftright_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL shiftright_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL shiftright_clk_or : std_logic := '0'; SIGNAL shiftright_aclr_or : std_logic := '0'; SIGNAL shiftright_sload_or : std_logic := '0'; SIGNAL shiftright_bypass_register_or : std_logic := '0'; SIGNAL shiftright_out_reg : std_logic := '0'; --signals for roundchainout output register SIGNAL roundchainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL roundchainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL roundchainout_clk_or : std_logic := '0'; SIGNAL roundchainout_aclr_or : std_logic := '0'; SIGNAL roundchainout_sload_or : std_logic := '0'; SIGNAL roundchainout_bypass_register_or: std_logic := '0'; SIGNAL roundchainout_out_reg : std_logic := '0'; --signals for saturatechainout output register SIGNAL saturatechainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL saturatechainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL saturatechainout_clk_or : std_logic := '0'; SIGNAL saturatechainout_aclr_or : std_logic := '0'; SIGNAL saturatechainout_sload_or: std_logic := '0'; SIGNAL saturatechainout_bypass_register_or: std_logic := '0'; SIGNAL saturatechainout_out_reg : std_logic := '0'; --Signals for chainout Adder RS Block SIGNAL coa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL coa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL coa_rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL coa_rs_saturation_overflow : std_logic := '0'; --signals for control signals for COA output register SIGNAL coa_reg_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL coa_reg_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL coa_reg_clk_or : std_logic := '0'; SIGNAL coa_reg_aclr_or : std_logic := '0'; SIGNAL coa_reg_sload_or : std_logic := '0'; SIGNAL coa_reg_bypass_register_or : std_logic := '0'; SIGNAL coa_reg_out_reg : std_logic := '0'; SIGNAL coa_rs_saturation_overflow_out_reg: std_logic := '0'; SIGNAL coa_rs_saturationchainout_overflow_out_reg: std_logic := '0'; SIGNAL coa_rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL dataout_shift_rot : std_logic_vector(71 DOWNTO 0):= (others => '0'); SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL loopbackout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL saturation_overflow_tmp : std_logic := '0'; SIGNAL saturationchainout_overflow_tmp : std_logic := '0'; SIGNAL rs_dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0'); SIGNAL sign : std_logic := '0'; BEGIN process(rs_dataout, rs_saturation_overflow, saturate_pip_reg) variable rs_tmp : std_logic_vector(71 downto 0):= (others => '0'); begin rs_tmp := rs_dataout; if (((operation_mode = "output_only")or (operation_mode = "one_level_adder") or(operation_mode = "loopback")) and (dataa_width > 1) and (saturate_pip_reg = '1'))then rs_tmp(dataa_width -1) := rs_saturation_overflow ; end if; rs_dataout_of <= rs_tmp; end process; --Instantiate the zeroloopback input Register zeroloopback_clkval_ir <= "0000" WHEN ((zeroloopback_clock = "0") or (zeroloopback_clock = "none")) ELSE "0001" WHEN (zeroloopback_clock = "1") ELSE "0010" WHEN (zeroloopback_clock = "2") ELSE "0011" WHEN (zeroloopback_clock = "3") ELSE "0000" ; zeroloopback_aclrval_ir <= "0000" WHEN ((zeroloopback_clear = "0") or (zeroloopback_clear = "none")) ELSE "0001" WHEN (zeroloopback_clear = "1") ELSE "0010" WHEN (zeroloopback_clear = "2") ELSE "0011" WHEN (zeroloopback_clear = "3") ELSE "0000" ; zeroloopback_clk_ir <= '1' WHEN clk(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0'; zeroloopback_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; zeroloopback_sload_ir <= '1' WHEN ena(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0'; zeroloopback_bypass_register_ir <= '1' WHEN (zeroloopback_clock = "none") ELSE '0'; zeroloopback_in <= zeroloopback; zeroloopback_input_register : hardcopyiii_mac_bit_register PORT MAP ( datain => zeroloopback_in, clk => zeroloopback_clk_ir, aclr => zeroloopback_aclr_ir, sload => zeroloopback_sload_ir, bypass_register => zeroloopback_bypass_register_ir, dataout => zeroloopback_in_reg ); --Instantiate the zeroacc input Register zeroacc_clkval_ir <= "0000" WHEN ((zeroacc_clock = "0") or (zeroacc_clock = "none")) ELSE "0001" WHEN (zeroacc_clock = "1") ELSE "0010" WHEN (zeroacc_clock = "2") ELSE "0011" WHEN (zeroacc_clock = "3") ELSE "0000" ; zeroacc_aclrval_ir <= "0000" WHEN ((zeroacc_clear = "0") or (zeroacc_clear = "none")) ELSE "0001" WHEN (zeroacc_clear = "1") ELSE "0010" WHEN (zeroacc_clear = "2") ELSE "0011" WHEN (zeroacc_clear = "3") ELSE "0000" ; zeroacc_clk_ir <= '1' WHEN clk(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0'; zeroacc_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; zeroacc_sload_ir <= '1' WHEN ena(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0'; zeroacc_bypass_register_ir <= '1' WHEN (zeroacc_clock = "none") ELSE '0'; zeroacc_in <= zeroacc; zeroacc_input_register : hardcopyiii_mac_bit_register PORT MAP ( datain => zeroacc_in, clk => zeroacc_clk_ir, aclr => zeroacc_aclr_ir, sload => zeroacc_sload_ir, bypass_register => zeroacc_bypass_register_ir, dataout => zeroacc_in_reg ); --Instantiate the signa input Register signa_clkval_ir <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none")) ELSE "0001" WHEN (signa_clock = "1") ELSE "0010" WHEN (signa_clock = "2") ELSE "0011" WHEN (signa_clock = "3") ELSE "0000" ; signa_aclrval_ir <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none")) ELSE "0001" WHEN (signa_clear = "1") ELSE "0010" WHEN (signa_clear = "2") ELSE "0011" WHEN (signa_clear = "3") ELSE "0000" ; signa_clk_ir <= '1' WHEN clk(conv_integer(signa_clkval_ir)) = '1' ELSE '0'; signa_aclr_ir <= '1' WHEN (aclr(conv_integer(signa_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; signa_sload_ir <= '1' WHEN ena(conv_integer(signa_clkval_ir)) = '1' ELSE '0'; signa_bypass_register_ir <= '1' WHEN (signa_clock = "none") ELSE '0'; signa_in <= signa; signa_input_register : hardcopyiii_mac_bit_register PORT MAP ( datain => signa_in, clk => signa_clk_ir, aclr => signa_aclr_ir, sload => signa_sload_ir, bypass_register => signa_bypass_register_ir, dataout => signa_in_reg ); --Instantiate the signb input Register signb_clkval_ir <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none")) ELSE "0001" WHEN (signb_clock = "1") ELSE "0010" WHEN (signb_clock = "2") ELSE "0011" WHEN (signb_clock = "3") ELSE "0000" ; signb_aclrval_ir <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none")) ELSE "0001" WHEN (signb_clear = "1") ELSE "0010" WHEN (signb_clear = "2") ELSE "0011" WHEN (signb_clear = "3") ELSE "0000" ; signb_clk_ir <= '1' WHEN clk(conv_integer(signb_clkval_ir)) = '1' ELSE '0'; signb_aclr_ir <= '1' WHEN (aclr(conv_integer(signb_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; signb_sload_ir <= '1' WHEN ena(conv_integer(signb_clkval_ir)) = '1' ELSE '0'; signb_bypass_register_ir <= '1' WHEN (signb_clock = "none") ELSE '0'; signb_in <= signb; signb_input_register : hardcopyiii_mac_bit_register PORT MAP ( datain => signb_in, clk => signb_clk_ir, aclr => signb_aclr_ir, sload => signb_sload_ir, bypass_register => signb_bypass_register_ir, dataout => signb_in_reg ); --Instantiate the rotate input Register rotate_clkval_ir <= "0000" WHEN ((rotate_clock = "0") or (rotate_clock = "none")) ELSE "0001" WHEN (rotate_clock = "1") ELSE "0010" WHEN (rotate_clock = "2") ELSE "0011" WHEN (rotate_clock = "3") ELSE "0000" ; rotate_aclrval_ir <= "0000" WHEN ((rotate_clear = "0") or (rotate_clear = "none")) ELSE "0001" WHEN (rotate_clear = "1") ELSE "0010" WHEN (rotate_clear = "2") ELSE "0011" WHEN (rotate_clear = "3") ELSE "0000" ; rotate_clk_ir <= '1' WHEN clk(conv_integer(rotate_clkval_ir)) = '1' ELSE '0'; rotate_aclr_ir <= '1' WHEN (aclr(conv_integer(rotate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; rotate_sload_ir <= '1' WHEN ena(conv_integer(rotate_clkval_ir)) = '1' ELSE '0'; rotate_bypass_register_ir <= '1' WHEN (rotate_clock = "none") ELSE '0'; rotate_in <= rotate; rotate_input_register : hardcopyiii_mac_bit_register PORT MAP ( datain => rotate_in, clk => rotate_clk_ir, aclr => rotate_aclr_ir, sload => rotate_sload_ir, bypass_register => rotate_bypass_register_ir, dataout => rotate_in_reg ); --Instantiate the shiftright input Register shiftright_clkval_ir <= "0000" WHEN ((shiftright_clock = "0") or (shiftright_clock = "none")) ELSE "0001" WHEN (shiftright_clock = "1") ELSE "0010" WHEN (shiftright_clock = "2") ELSE "0011" WHEN (shiftright_clock = "3") ELSE "0000" ; shiftright_aclrval_ir <= "0000" WHEN ((shiftright_clear = "0") or (shiftright_clear = "none")) ELSE "0001" WHEN (shiftright_clear = "1") ELSE "0010" WHEN (shiftright_clear = "2") ELSE "0011" WHEN (shiftright_clear = "3") ELSE "0000" ; shiftright_clk_ir <= '1' WHEN clk(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0'; shiftright_aclr_ir <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ; shiftright_sload_ir <= '1' WHEN ena(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0'; shiftright_bypass_register_ir <= '1' WHEN (shiftright_clock = "none") ELSE '0'; shiftright_in <= shiftright; shiftright_input_register : hardcopyiii_mac_bit_register PORT MAP ( datain => shiftright_in, clk => shiftright_clk_ir, aclr => shiftright_aclr_ir, sload => shiftright_sload_ir, bypass_register => shiftright_bypass_register_ir, dataout => shiftright_in_reg ); --Instantiate the round input Register round_clkval_ir <= "0000" WHEN ((round_clock = "0") or (round_clock = "none")) ELSE "0001" WHEN (round_clock = "1") ELSE "0010" WHEN (round_clock = "2") ELSE "0011" WHEN (round_clock = "3") ELSE "0000" ; round_aclrval_ir <= "0000" WHEN ((round_clear = "0") or (round_clear = "none")) ELSE "0001" WHEN (round_clear = "1") ELSE "0010" WHEN (round_clear = "2") ELSE "0011" WHEN (round_clear = "3") ELSE "0000" ; round_clk_ir <= '1' WHEN clk(conv_integer(round_clkval_ir)) = '1' ELSE '0'; round_aclr_ir <= '1' WHEN (aclr(conv_integer(round_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; round_sload_ir <= '1' WHEN ena(conv_integer(round_clkval_ir)) = '1' ELSE '0'; round_bypass_register_ir <= '1' WHEN (round_clock = "none") ELSE '0'; round_in <= round; round_input_register : hardcopyiii_mac_bit_register PORT MAP ( datain => round_in, clk => round_clk_ir, aclr => round_aclr_ir, sload => round_sload_ir, bypass_register => round_bypass_register_ir, dataout => round_in_reg ); --Instantiate the saturate input Register saturate_clkval_ir <= "0000" WHEN ((saturate_clock = "0") or (saturate_clock = "none")) ELSE "0001" WHEN (saturate_clock = "1") ELSE "0010" WHEN (saturate_clock = "2") ELSE "0011" WHEN (saturate_clock = "3") ELSE "0000" ; saturate_aclrval_ir <= "0000" WHEN ((saturate_clear = "0") or (saturate_clear = "none")) ELSE "0001" WHEN (saturate_clear = "1") ELSE "0010" WHEN (saturate_clear = "2") ELSE "0011" WHEN (saturate_clear = "3") ELSE "0000" ; saturate_clk_ir <= '1' WHEN clk(conv_integer(saturate_clkval_ir)) = '1' ELSE '0'; saturate_aclr_ir <= '1' WHEN (aclr(conv_integer(saturate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; saturate_sload_ir <= '1' WHEN ena(conv_integer(saturate_clkval_ir)) = '1' ELSE '0'; saturate_bypass_register_ir <= '1' WHEN (saturate_clock = "none") ELSE '0'; saturate_in <= saturate; saturate_input_register : hardcopyiii_mac_bit_register PORT MAP ( datain => saturate_in, clk => saturate_clk_ir, aclr => saturate_aclr_ir, sload => saturate_sload_ir, bypass_register => saturate_bypass_register_ir, dataout => saturate_in_reg ); --Instantiate the roundchainout input Register roundchainout_clkval_ir <= "0000" WHEN ((roundchainout_clock = "0") or (roundchainout_clock = "none")) ELSE "0001" WHEN (roundchainout_clock = "1") ELSE "0010" WHEN (roundchainout_clock = "2") ELSE "0011" WHEN (roundchainout_clock = "3") ELSE "0000" ; roundchainout_aclrval_ir <= "0000" WHEN ((roundchainout_clear = "0") or (roundchainout_clear = "none")) ELSE "0001" WHEN (roundchainout_clear = "1") ELSE "0010" WHEN (roundchainout_clear = "2") ELSE "0011" WHEN (roundchainout_clear = "3") ELSE "0000" ; roundchainout_clk_ir <= '1' WHEN clk(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0'; roundchainout_aclr_ir <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; roundchainout_sload_ir <= '1' WHEN ena(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0'; roundchainout_bypass_register_ir <= '1' WHEN (roundchainout_clock = "none") ELSE '0'; roundchainout_in <= roundchainout; roundchainout_input_register : hardcopyiii_mac_bit_register PORT MAP ( datain => roundchainout_in, clk => roundchainout_clk_ir, aclr => roundchainout_aclr_ir, sload => roundchainout_sload_ir, bypass_register => roundchainout_bypass_register_ir, dataout => roundchainout_in_reg ); --Instantiate the saturatechainout input Register saturatechainout_clkval_ir <= "0000" WHEN ((saturatechainout_clock = "0") or (saturatechainout_clock = "none")) ELSE "0001" WHEN (saturatechainout_clock = "1") ELSE "0010" WHEN (saturatechainout_clock = "2") ELSE "0011" WHEN (saturatechainout_clock = "3") ELSE "0000" ; saturatechainout_aclrval_ir <= "0000" WHEN ((saturatechainout_clear = "0") or (saturatechainout_clear = "none")) ELSE "0001" WHEN (saturatechainout_clear = "1") ELSE "0010" WHEN (saturatechainout_clear = "2") ELSE "0011" WHEN (saturatechainout_clear = "3") ELSE "0000" ; saturatechainout_clk_ir <= '1' WHEN clk(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0'; saturatechainout_aclr_ir <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; saturatechainout_sload_ir <= '1' WHEN ena(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0'; saturatechainout_bypass_register_ir <= '1' WHEN (saturatechainout_clock = "none") ELSE '0'; saturatechainout_in <= saturatechainout; saturatechainout_input_register : hardcopyiii_mac_bit_register PORT MAP ( datain => saturatechainout_in, clk => saturatechainout_clk_ir, aclr => saturatechainout_aclr_ir, sload => saturatechainout_sload_ir, bypass_register => saturatechainout_bypass_register_ir, dataout => saturatechainout_in_reg ); --Instantiate the First level adder interface and sign extension block sign <= signa_in_reg OR signb_in_reg ; fsa_interface : hardcopyiii_fsa_isse GENERIC MAP ( chainin_width => chainin_width, dataa_width => dataa_width, datab_width => datab_width, datac_width => datac_width, datad_width => datad_width, operation_mode => operation_mode, multa_signa_internally_grounded => multa_signa_internally_grounded, multa_signb_internally_grounded => multa_signb_internally_grounded, multb_signa_internally_grounded => multb_signa_internally_grounded, multb_signb_internally_grounded => multb_signb_internally_grounded, multc_signa_internally_grounded => multc_signa_internally_grounded, multc_signb_internally_grounded => multc_signb_internally_grounded, multd_signa_internally_grounded => multd_signa_internally_grounded, multd_signb_internally_grounded => multd_signb_internally_grounded ) PORT MAP ( dataa => dataa, datab => datab, datac => datac, datad => datad, chainin => chainin, signa => signa_in_reg, signb => signb_in_reg, dataa_out => dataa_fsa_in, datab_out => datab_fsa_in, datac_out => datac_fsa_in, datad_out => datad_fsa_in, chainin_out => chainin_coa_in, operation => operation ); --Instantiate First Stage Adder/Subtractor Unit0 fsaunit0 : hardcopyiii_first_stage_add_sub GENERIC MAP ( dataa_width => dataa_width, datab_width => datab_width, fsa_mode => first_adder0_mode ) PORT MAP ( dataa => dataa_fsa_in, datab => datab_fsa_in, sign => sign, operation => operation, dataout => dataout_fsa0 ); --Instantiate First Stage Adder/Subtractor Unit1 fsaunit1 : hardcopyiii_first_stage_add_sub GENERIC MAP ( dataa_width => datac_width, datab_width => datad_width, fsa_mode => first_adder1_mode ) PORT MAP ( dataa => datac_fsa_in, datab => datad_fsa_in, sign => sign, operation => operation, dataout => dataout_fsa1 ); --Instantiate the zeroloopback pipeline Register zeroloopback_clkval_pip <= "0000" WHEN ((zeroloopback_pipeline_clock = "0") or (zeroloopback_pipeline_clock = "none")) ELSE "0001" WHEN (zeroloopback_pipeline_clock = "1") ELSE "0010" WHEN (zeroloopback_pipeline_clock = "2") ELSE "0011" WHEN (zeroloopback_pipeline_clock = "3") ELSE "0000" ; zeroloopback_aclrval_pip <= "0000" WHEN ((zeroloopback_pipeline_clear = "0") or (zeroloopback_pipeline_clear = "none")) ELSE "0001" WHEN (zeroloopback_pipeline_clear = "1") ELSE "0010" WHEN (zeroloopback_pipeline_clear = "2") ELSE "0011" WHEN (zeroloopback_pipeline_clear = "3") ELSE "0000" ; zeroloopback_clk_pip <= '1' WHEN clk(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0'; zeroloopback_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; zeroloopback_sload_pip <= '1' WHEN ena(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0'; zeroloopback_bypass_register_pip <= '1' WHEN (zeroloopback_pipeline_clock = "none") ELSE '0'; zeroloopback_pipeline_register : hardcopyiii_mac_bit_register PORT MAP ( datain => zeroloopback_in_reg, clk => zeroloopback_clk_pip, aclr => zeroloopback_aclr_pip, sload => zeroloopback_sload_pip, bypass_register => zeroloopback_bypass_register_pip, dataout => zeroloopback_pip_reg ); --Instantiate the zeroacc pipeline Register zeroacc_clkval_pip <= "0000" WHEN ((zeroacc_pipeline_clock = "0") or (zeroacc_pipeline_clock = "none")) ELSE "0001" WHEN (zeroacc_pipeline_clock = "1") ELSE "0010" WHEN (zeroacc_pipeline_clock = "2") ELSE "0011" WHEN (zeroacc_pipeline_clock = "3") ELSE "0000" ; zeroacc_aclrval_pip <= "0000" WHEN ((zeroacc_pipeline_clear = "0") or (zeroacc_pipeline_clear = "none")) ELSE "0001" WHEN (zeroacc_pipeline_clear = "1") ELSE "0010" WHEN (zeroacc_pipeline_clear = "2") ELSE "0011" WHEN (zeroacc_pipeline_clear = "3") ELSE "0000" ; zeroacc_clk_pip <= '1' WHEN clk(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0'; zeroacc_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; zeroacc_sload_pip <= '1' WHEN ena(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0'; zeroacc_bypass_register_pip <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0'; zeroacc_pipeline_register : hardcopyiii_mac_bit_register PORT MAP ( datain => zeroacc_in_reg, clk => zeroacc_clk_pip, aclr => zeroacc_aclr_pip, sload => zeroacc_sload_pip, bypass_register => zeroacc_bypass_register_pip, dataout => zeroacc_pip_reg ); --Instantiate the signa pipeline Register signa_clkval_pip <= "0000" WHEN ((signa_pipeline_clock = "0") or (signa_pipeline_clock = "none")) ELSE "0001" WHEN (signa_pipeline_clock = "1") ELSE "0010" WHEN (signa_pipeline_clock = "2") ELSE "0011" WHEN (signa_pipeline_clock = "3") ELSE "0000" ; signa_aclrval_pip <= "0000" WHEN ((signa_pipeline_clear = "0") or (signa_pipeline_clear = "none")) ELSE "0001" WHEN (signa_pipeline_clear = "1") ELSE "0010" WHEN (signa_pipeline_clear = "2") ELSE "0011" WHEN (signa_pipeline_clear = "3") ELSE "0000" ; signa_clk_pip <= '1' WHEN clk(conv_integer(signa_clkval_pip)) = '1' ELSE '0'; signa_aclr_pip <= '1' WHEN (aclr(conv_integer(signa_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; signa_sload_pip <= '1' WHEN ena(conv_integer(signa_clkval_pip)) = '1' ELSE '0'; signa_bypass_register_pip <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0'; signa_pipeline_register : hardcopyiii_mac_bit_register PORT MAP ( datain => signa_in_reg, clk => signa_clk_pip, aclr => signa_aclr_pip, sload => signa_sload_pip, bypass_register => signa_bypass_register_pip, dataout => signa_pip_reg ); --Instantiate the signb pipeline Register signb_clkval_pip <= "0000" WHEN ((signb_pipeline_clock = "0") or (signb_pipeline_clock = "none")) ELSE "0001" WHEN (signb_pipeline_clock = "1") ELSE "0010" WHEN (signb_pipeline_clock = "2") ELSE "0011" WHEN (signb_pipeline_clock = "3") ELSE "0000" ; signb_aclrval_pip <= "0000" WHEN ((signb_pipeline_clear = "0") or (signb_pipeline_clear = "none")) ELSE "0001" WHEN (signb_pipeline_clear = "1") ELSE "0010" WHEN (signb_pipeline_clear = "2") ELSE "0011" WHEN (signb_pipeline_clear = "3") ELSE "0000" ; signb_clk_pip <= '1' WHEN clk(conv_integer(signb_clkval_pip)) = '1' ELSE '0'; signb_aclr_pip <= '1' WHEN (aclr(conv_integer(signb_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; signb_sload_pip <= '1' WHEN ena(conv_integer(signb_clkval_pip)) = '1' ELSE '0'; signb_bypass_register_pip <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0'; signb_pipeline_register : hardcopyiii_mac_bit_register PORT MAP ( datain => signb_in_reg, clk => signb_clk_pip, aclr => signb_aclr_pip, sload => signb_sload_pip, bypass_register => signb_bypass_register_pip, dataout => signb_pip_reg ); --Instantiate the rotate pipeline Register rotate_clkval_pip <= "0000" WHEN ((rotate_pipeline_clock = "0") or (rotate_pipeline_clock = "none")) ELSE "0001" WHEN (rotate_pipeline_clock = "1") ELSE "0010" WHEN (rotate_pipeline_clock = "2") ELSE "0011" WHEN (rotate_pipeline_clock = "3") ELSE "0000" ; rotate_aclrval_pip <= "0000" WHEN ((rotate_pipeline_clear = "0") or (rotate_pipeline_clear = "none")) ELSE "0001" WHEN (rotate_pipeline_clear = "1") ELSE "0010" WHEN (rotate_pipeline_clear = "2") ELSE "0011" WHEN (rotate_pipeline_clear = "3") ELSE "0000" ; rotate_clk_pip <= '1' WHEN clk(conv_integer(rotate_clkval_pip)) = '1' ELSE '0'; rotate_aclr_pip <= '1' WHEN (aclr(conv_integer(rotate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; rotate_sload_pip <= '1' WHEN ena(conv_integer(rotate_clkval_pip)) = '1' ELSE '0'; rotate_bypass_register_pip <= '1' WHEN (rotate_pipeline_clock = "none") ELSE '0'; rotate_pipeline_register : hardcopyiii_mac_bit_register PORT MAP ( datain => rotate_in_reg, clk => rotate_clk_pip, aclr => rotate_aclr_pip, sload => rotate_sload_pip, bypass_register => rotate_bypass_register_pip, dataout => rotate_pip_reg ); --Instantiate the shiftright pipeline Register shiftright_clkval_pip <= "0000" WHEN ((shiftright_pipeline_clock = "0") or (shiftright_pipeline_clock = "none")) ELSE "0001" WHEN (shiftright_pipeline_clock = "1") ELSE "0010" WHEN (shiftright_pipeline_clock = "2") ELSE "0011" WHEN (shiftright_pipeline_clock = "3") ELSE "0000" ; shiftright_aclrval_pip <= "0000" WHEN ((shiftright_pipeline_clear = "0") or (shiftright_pipeline_clear = "none")) ELSE "0001" WHEN (shiftright_pipeline_clear = "1") ELSE "0010" WHEN (shiftright_pipeline_clear = "2") ELSE "0011" WHEN (shiftright_pipeline_clear = "3") ELSE "0000" ; shiftright_clk_pip <= '1' WHEN clk(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0'; shiftright_aclr_pip <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; shiftright_sload_pip <= '1' WHEN ena(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0'; shiftright_bypass_register_pip <= '1' WHEN (shiftright_pipeline_clock = "none") ELSE '0'; shiftright_pipeline_register : hardcopyiii_mac_bit_register PORT MAP ( datain => shiftright_in_reg, clk => shiftright_clk_pip, aclr => shiftright_aclr_pip, sload => shiftright_sload_pip, bypass_register => shiftright_bypass_register_pip, dataout => shiftright_pip_reg ); --Instantiate the round pipeline Register round_clkval_pip <= "0000" WHEN ((round_pipeline_clock = "0") or (round_pipeline_clock = "none")) ELSE "0001" WHEN (round_pipeline_clock = "1") ELSE "0010" WHEN (round_pipeline_clock = "2") ELSE "0011" WHEN (round_pipeline_clock = "3") ELSE "0000" ; round_aclrval_pip <= "0000" WHEN ((round_pipeline_clear = "0") or (round_pipeline_clear = "none")) ELSE "0001" WHEN (round_pipeline_clear = "1") ELSE "0010" WHEN (round_pipeline_clear = "2") ELSE "0011" WHEN (round_pipeline_clear = "3") ELSE "0000" ; round_clk_pip <= '1' WHEN clk(conv_integer(round_clkval_pip)) = '1' ELSE '0'; round_aclr_pip <= '1' WHEN (aclr(conv_integer(round_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; round_sload_pip <= '1' WHEN ena(conv_integer(round_clkval_pip)) = '1' ELSE '0'; round_bypass_register_pip <= '1' WHEN (round_pipeline_clock = "none") ELSE '0'; round_pipeline_register : hardcopyiii_mac_bit_register PORT MAP ( datain => round_in_reg, clk => round_clk_pip, aclr => round_aclr_pip, sload => round_sload_pip, bypass_register => round_bypass_register_pip, dataout => round_pip_reg ); --Instantiate the saturate pipeline Register saturate_clkval_pip <= "0000" WHEN ((saturate_pipeline_clock = "0") or (saturate_pipeline_clock = "none")) ELSE "0001" WHEN (saturate_pipeline_clock = "1") ELSE "0010" WHEN (saturate_pipeline_clock = "2") ELSE "0011" WHEN (saturate_pipeline_clock = "3") ELSE "0000" ; saturate_aclrval_pip <= "0000" WHEN ((saturate_pipeline_clear = "0") or (saturate_pipeline_clear = "none")) ELSE "0001" WHEN (saturate_pipeline_clear = "1") ELSE "0010" WHEN (saturate_pipeline_clear = "2") ELSE "0011" WHEN (saturate_pipeline_clear = "3") ELSE "0000" ; saturate_clk_pip <= '1' WHEN clk(conv_integer(saturate_clkval_pip)) = '1' ELSE '0'; saturate_aclr_pip <= '1' WHEN (aclr(conv_integer(saturate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; saturate_sload_pip <= '1' WHEN ena(conv_integer(saturate_clkval_pip)) = '1' ELSE '0'; saturate_bypass_register_pip <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0'; saturate_pipeline_register : hardcopyiii_mac_bit_register PORT MAP ( datain => saturate_in_reg, clk => saturate_clk_pip, aclr => saturate_aclr_pip, sload => saturate_sload_pip, bypass_register => saturate_bypass_register_pip, dataout => saturate_pip_reg ); --Instantiate the roundchainout pipeline Register roundchainout_clkval_pip <= "0000" WHEN ((roundchainout_pipeline_clock = "0") or (roundchainout_pipeline_clock = "none")) ELSE "0001" WHEN (roundchainout_pipeline_clock = "1") ELSE "0010" WHEN (roundchainout_pipeline_clock = "2") ELSE "0011" WHEN (roundchainout_pipeline_clock = "3") ELSE "0000" ; roundchainout_aclrval_pip <= "0000" WHEN ((roundchainout_pipeline_clear = "0") or (roundchainout_pipeline_clear = "none")) ELSE "0001" WHEN (roundchainout_pipeline_clear = "1") ELSE "0010" WHEN (roundchainout_pipeline_clear = "2") ELSE "0011" WHEN (roundchainout_pipeline_clear = "3") ELSE "0000" ; roundchainout_clk_pip <= '1' WHEN clk(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0'; roundchainout_aclr_pip <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; roundchainout_sload_pip <= '1' WHEN ena(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0'; roundchainout_bypass_register_pip <= '1' WHEN (roundchainout_pipeline_clock = "none") ELSE '0'; roundchainout_pipeline_register : hardcopyiii_mac_bit_register PORT MAP ( datain => roundchainout_in_reg, clk => roundchainout_clk_pip, aclr => roundchainout_aclr_pip, sload => roundchainout_sload_pip, bypass_register => roundchainout_bypass_register_pip, dataout => roundchainout_pip_reg ); --Instantiate the saturatechainout pipeline Register saturatechainout_clkval_pip <= "0000" WHEN ((saturatechainout_pipeline_clock = "0") or (saturatechainout_pipeline_clock = "none")) ELSE "0001" WHEN (saturatechainout_pipeline_clock = "1") ELSE "0010" WHEN (saturatechainout_pipeline_clock = "2") ELSE "0011" WHEN (saturatechainout_pipeline_clock = "3") ELSE "0000" ; saturatechainout_aclrval_pip <= "0000" WHEN ((saturatechainout_pipeline_clear = "0") or (saturatechainout_pipeline_clear = "none")) ELSE "0001" WHEN (saturatechainout_pipeline_clear = "1") ELSE "0010" WHEN (saturatechainout_pipeline_clear = "2") ELSE "0011" WHEN (saturatechainout_pipeline_clear = "3") ELSE "0000" ; saturatechainout_clk_pip <= '1' WHEN clk(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0'; saturatechainout_aclr_pip <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; saturatechainout_sload_pip <= '1' WHEN ena(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0'; saturatechainout_bypass_register_pip <= '1' WHEN (saturatechainout_pipeline_clock = "none") ELSE '0'; saturatechainout_pipeline_register : hardcopyiii_mac_bit_register PORT MAP ( datain => saturatechainout_in_reg, clk => saturatechainout_clk_pip, aclr => saturatechainout_aclr_pip, sload => saturatechainout_sload_pip, bypass_register => saturatechainout_bypass_register_pip, dataout => saturatechainout_pip_reg ); -- Instantiate fsa0 dataout pipline register fsa_pip_datain1 <= dataa_fsa_in WHEN (operation_mode = "output_only") ELSE dataout_fsa0; fsa0_clkval_pip <= "0000" WHEN ((first_adder0_clock = "0") or (first_adder0_clock = "none")) ELSE "0001" WHEN (first_adder0_clock = "1") ELSE "0010" WHEN (first_adder0_clock = "2") ELSE "0011" WHEN (first_adder0_clock = "3") ELSE "0000" ; fsa0_aclrval_pip <= "0000" WHEN ((first_adder0_clear = "0") or (first_adder0_clear = "none")) ELSE "0001" WHEN (first_adder0_clear = "1") ELSE "0010" WHEN (first_adder0_clear = "2") ELSE "0011" WHEN (first_adder0_clear = "3") ELSE "0000" ; fsa0_clk_pip <= '1' WHEN clk(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0'; fsa0_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa0_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; fsa0_sload_pip <= '1' WHEN ena(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0'; fsa0_bypass_register_pip <= '1' WHEN (first_adder0_clock = "none") ELSE '0'; fsa0_pipeline_register : hardcopyiii_mac_register GENERIC MAP ( data_width => 72 ) PORT MAP ( datain => fsa_pip_datain1, clk => fsa0_clk_pip, aclr => fsa0_aclr_pip, sload => fsa0_sload_pip, bypass_register => fsa0_bypass_register_pip, dataout => fsa0_pip_reg ); -- Instantiate fsa1 dataout pipline register fsa1_clkval_pip <= "0000" WHEN ((first_adder1_clock = "0") or (first_adder1_clock = "none")) ELSE "0001" WHEN (first_adder1_clock = "1") ELSE "0010" WHEN (first_adder1_clock = "2") ELSE "0011" WHEN (first_adder1_clock = "3") ELSE "0000" ; fsa1_aclrval_pip <= "0000" WHEN ((first_adder1_clear = "0") or (first_adder1_clear = "none")) ELSE "0001" WHEN (first_adder1_clear = "1") ELSE "0010" WHEN (first_adder1_clear = "2") ELSE "0011" WHEN (first_adder1_clear = "3") ELSE "0000" ; fsa1_clk_pip <= '1' WHEN clk(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0'; fsa1_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa1_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; fsa1_sload_pip <= '1' WHEN ena(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0'; fsa1_bypass_register_pip <= '1' WHEN (first_adder1_clock = "none") ELSE '0'; fsa1_pipeline_register : hardcopyiii_mac_register GENERIC MAP ( data_width => 72 ) PORT MAP ( datain => dataout_fsa1, clk => fsa1_clk_pip, aclr => fsa1_aclr_pip, sload => fsa1_sload_pip, bypass_register => fsa1_bypass_register_pip, dataout => fsa1_pip_reg ); --Instantiate the second level adder/accumulator block ssa_accum_in <= rs_dataout_out_reg WHEN (NOT zeroacc_pip_reg) = '1' ELSE (others => '0'); ssa_sign <= signa_pip_reg OR signb_pip_reg ; ssa_unit : hardcopyiii_second_stage_add_accum GENERIC MAP ( dataa_width => dataa_width + 1, datab_width => datac_width + 1, ssa_mode => acc_adder_operation ) PORT MAP ( dataa => fsa0_pip_reg, datab => fsa1_pip_reg, accumin => ssa_accum_in, sign => ssa_sign, operation => operation, dataout => ssa_dataout, overflow => ssa_overflow ); -- Instantiate round and saturation block rs_datain <= fsa0_pip_reg when ((operation_mode = "output_only") or (operation_mode = "one_level_adder")or(operation_mode = "loopback")) ELSE ssa_dataout ; ssa_datain_width <= CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "accumulator") or(operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out")) ELSE CONV_STD_LOGIC_VECTOR(dataa_width +2,8) when(operation_mode = "two_level_adder") ELSE CONV_STD_LOGIC_VECTOR(dataa_width + datab_width,8) when ((operation_mode = "shift" ) or (operation_mode = "36_bit_multiply" )) ELSE CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "double" )) ELSE CONV_STD_LOGIC_VECTOR(dataa_width,8); rs_block : hardcopyiii_round_saturate_block GENERIC MAP ( dataa_width => dataa_width, datab_width => datab_width, operation_mode => operation_mode, round_mode => round_mode, saturate_mode => saturate_mode, saturate_width => saturate_width, round_width => round_width ) PORT MAP ( datain => rs_datain, round => round_pip_reg, saturate => saturate_pip_reg, signa => signa_pip_reg, signb => signb_pip_reg, datain_width => ssa_datain_width, dataout => rs_dataout, saturationoverflow => rs_saturation_overflow ); --Instantiate the zeroloopback output Register zeroloopback_clkval_or <= "0000" WHEN ((zeroloopback_output_clock = "0") or (zeroloopback_output_clock = "none")) ELSE "0001" WHEN (zeroloopback_output_clock = "1") ELSE "0010" WHEN (zeroloopback_output_clock = "2") ELSE "0011" WHEN (zeroloopback_output_clock = "3") ELSE "0000" ; zeroloopback_aclrval_or <= "0000" WHEN ((zeroloopback_output_clear = "0") or (zeroloopback_output_clear = "none")) ELSE "0001" WHEN (zeroloopback_output_clear = "1") ELSE "0010" WHEN (zeroloopback_output_clear = "2") ELSE "0011" WHEN (zeroloopback_output_clear = "3") ELSE "0000" ; zeroloopback_clk_or <= '1' WHEN clk(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0'; zeroloopback_aclr_or <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; zeroloopback_sload_or <= '1' WHEN ena(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0'; zeroloopback_bypass_register_or <= '1' WHEN (zeroloopback_output_clock = "none") ELSE '0'; zeroloopback_output_register : hardcopyiii_mac_bit_register PORT MAP ( datain => zeroloopback_pip_reg, clk => zeroloopback_clk_or, aclr => zeroloopback_aclr_or, sload => zeroloopback_sload_or, bypass_register => zeroloopback_bypass_register_or, dataout => zeroloopback_out_reg ); --Instantiate the zerochainout output Register zerochainout_clkval_or <= "0000" WHEN ((zerochainout_output_clock = "0") or (zerochainout_output_clock = "none")) ELSE "0001" WHEN (zerochainout_output_clock = "1") ELSE "0010" WHEN (zerochainout_output_clock = "2") ELSE "0011" WHEN (zerochainout_output_clock = "3") ELSE "0000" ; zerochainout_aclrval_or <= "0000" WHEN ((zerochainout_output_clear = "0") or (zerochainout_output_clear = "none")) ELSE "0001" WHEN (zerochainout_output_clear = "1") ELSE "0010" WHEN (zerochainout_output_clear = "2") ELSE "0011" WHEN (zerochainout_output_clear = "3") ELSE "0000" ; zerochainout_clk_or <= '1' WHEN clk(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0'; zerochainout_aclr_or <= '1' WHEN (aclr(conv_integer(zerochainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; zerochainout_sload_or <= '1' WHEN ena(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0'; zerochainout_bypass_register_or <= '1' WHEN (zerochainout_output_clock = "none") ELSE '0'; zerochainout_output_register : hardcopyiii_mac_bit_register PORT MAP ( datain => zerochainout, clk => zerochainout_clk_or, aclr => zerochainout_aclr_or, sload => zerochainout_sload_or, bypass_register => zerochainout_bypass_register_or, dataout => zerochainout_out_reg ); -- Instantiate Round_Saturate dataout output register rs_dataout_clkval_or_co <= "0000" WHEN ((second_adder_clock = "0") or (second_adder_clock = "none")) ELSE "0001" WHEN (second_adder_clock = "1") ELSE "0010" WHEN (second_adder_clock = "2") ELSE "0011" WHEN (second_adder_clock = "3") ELSE "0000" ; rs_dataout_aclrval_or_co <= "0000" WHEN ((second_adder_clear = "0") or (second_adder_clear = "none")) ELSE "0001" WHEN (second_adder_clear = "1") ELSE "0010" WHEN (second_adder_clear = "2") ELSE "0011" WHEN (second_adder_clear = "3") ELSE "0000" ; rs_dataout_clkval_or_o <= "0000" WHEN ((output_clock = "0") or (output_clock = "none")) ELSE "0001" WHEN (output_clock = "1") ELSE "0010" WHEN (output_clock = "2") ELSE "0011" WHEN (output_clock = "3") ELSE "0000" ; rs_dataout_aclrval_or_o <= "0000" WHEN ((output_clear = "0") or (output_clear = "none")) ELSE "0001" WHEN (output_clear = "1") ELSE "0010" WHEN (output_clear = "2") ELSE "0011" WHEN (output_clear = "3") ELSE "0000" ; rs_dataout_aclrval_or <= rs_dataout_aclrval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" )) ELSE rs_dataout_aclrval_or_o; rs_dataout_clkval_or <= rs_dataout_clkval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" )) ELSE rs_dataout_clkval_or_o; rs_dataout_bypass_register_or_co <= '1' WHEN (second_adder_clock = "none") ELSE '0'; rs_dataout_bypass_register_or_o <= '1' WHEN (output_clock = "none") ELSE '0'; rs_dataout_clk_or <= '1' WHEN clk(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0'; rs_dataout_aclr_or <= '1' WHEN (aclr(conv_integer(rs_dataout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; rs_dataout_sload_or <= '1' WHEN ena(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0'; rs_dataout_bypass_register_or <= rs_dataout_bypass_register_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" )) ELSE rs_dataout_bypass_register_or_o; rs_dataout_in <= ssa_dataout WHEN ((operation_mode = "36_bit_multiply") OR (operation_mode = "shift")) ELSE rs_dataout_of; rs_dataout_output_register : hardcopyiii_mac_register GENERIC MAP ( data_width => 72 ) PORT MAP ( datain => rs_dataout_in, clk => rs_dataout_clk_or, aclr => rs_dataout_aclr_or, sload => rs_dataout_sload_or, bypass_register => rs_dataout_bypass_register_or, dataout => rs_dataout_out_reg ); -- Instantiate Round_Saturate saturation_overflow output register rs_saturation_overflow_in <= rs_saturation_overflow WHEN (saturate_pip_reg = '1') ELSE ssa_overflow; rs_saturation_overflow_output_register : hardcopyiii_mac_bit_register PORT MAP ( datain => rs_saturation_overflow_in, clk => rs_dataout_clk_or, aclr => rs_dataout_aclr_or, sload => rs_dataout_sload_or, bypass_register => rs_dataout_bypass_register_or, dataout => rs_saturation_overflow_out_reg ); --Instantiate the rotate output Register rotate_clkval_or <= "0000" WHEN ((rotate_output_clock = "0") or (rotate_output_clock = "none")) ELSE "0001" WHEN (rotate_output_clock = "1") ELSE "0010" WHEN (rotate_output_clock = "2") ELSE "0011" WHEN (rotate_output_clock = "3") ELSE "0000" ; rotate_aclrval_or <= "0000" WHEN ((rotate_output_clear = "0") or (rotate_output_clear = "none")) ELSE "0001" WHEN (rotate_output_clear = "1") ELSE "0010" WHEN (rotate_output_clear = "2") ELSE "0011" WHEN (rotate_output_clear = "3") ELSE "0000" ; rotate_clk_or <= '1' WHEN clk(conv_integer(rotate_clkval_or)) = '1' ELSE '0'; rotate_aclr_or <= '1' WHEN (aclr(conv_integer(rotate_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; rotate_sload_or <= '1' WHEN ena(conv_integer(rotate_clkval_or)) = '1' ELSE '0'; rotate_bypass_register_or <= '1' WHEN (rotate_output_clock = "none") ELSE '0'; rotate_output_register : hardcopyiii_mac_bit_register PORT MAP ( datain => rotate_pip_reg, clk => rotate_clk_or, aclr => rotate_aclr_or, sload => rotate_sload_or, bypass_register => rotate_bypass_register_or, dataout => rotate_out_reg ); --Instantiate the shiftright output Register shiftright_output_register : hardcopyiii_mac_bit_register PORT MAP ( datain => shiftright_pip_reg, clk => shiftright_clk_or, aclr => shiftright_aclr_or, sload => shiftright_sload_or, bypass_register => shiftright_bypass_register_or, dataout => shiftright_out_reg ); shiftright_clkval_or <= "0000" WHEN ((shiftright_output_clock = "0") or (shiftright_output_clock = "none")) ELSE "0001" WHEN (shiftright_output_clock = "1") ELSE "0010" WHEN (shiftright_output_clock = "2") ELSE "0011" WHEN (shiftright_output_clock = "3") ELSE "0000" ; shiftright_aclrval_or <= "0000" WHEN ((shiftright_output_clear = "0") or (shiftright_output_clear = "none")) ELSE "0001" WHEN (shiftright_output_clear = "1") ELSE "0010" WHEN (shiftright_output_clear = "2") ELSE "0011" WHEN (shiftright_output_clear = "3") ELSE "0000" ; shiftright_clk_or <= '1' WHEN clk(conv_integer(shiftright_clkval_or)) = '1' ELSE '0'; shiftright_aclr_or <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; shiftright_sload_or <= '1' WHEN ena(conv_integer(shiftright_clkval_or)) = '1' ELSE '0'; shiftright_bypass_register_or <= '1' WHEN (shiftright_output_clock = "none") ELSE '0'; --Instantiate the roundchainout output Register roundchainout_clkval_or <= "0000" WHEN ((roundchainout_output_clock = "0") or (roundchainout_output_clock = "none")) ELSE "0001" WHEN (roundchainout_output_clock = "1") ELSE "0010" WHEN (roundchainout_output_clock = "2") ELSE "0011" WHEN (roundchainout_output_clock = "3") ELSE "0000" ; roundchainout_aclrval_or <= "0000" WHEN ((roundchainout_output_clear = "0") or (roundchainout_output_clear = "none")) ELSE "0001" WHEN (roundchainout_output_clear = "1") ELSE "0010" WHEN (roundchainout_output_clear = "2") ELSE "0011" WHEN (roundchainout_output_clear = "3") ELSE "0000" ; roundchainout_clk_or <= '1' WHEN clk(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0'; roundchainout_aclr_or <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; roundchainout_sload_or <= '1' WHEN ena(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0'; roundchainout_bypass_register_or <= '1' WHEN (roundchainout_output_clock = "none") ELSE '0'; roundchainout_output_register : hardcopyiii_mac_bit_register PORT MAP ( datain => roundchainout_pip_reg, clk => roundchainout_clk_or, aclr => roundchainout_aclr_or, sload => roundchainout_sload_or, bypass_register => roundchainout_bypass_register_or, dataout => roundchainout_out_reg ); --Instantiate the saturatechainout output Register saturatechainout_clkval_or <= "0000" WHEN ((saturatechainout_output_clock = "0") or (saturatechainout_output_clock = "none")) ELSE "0001" WHEN (saturatechainout_output_clock = "1") ELSE "0010" WHEN (saturatechainout_output_clock = "2") ELSE "0011" WHEN (saturatechainout_output_clock = "3") ELSE "0000" ; saturatechainout_aclrval_or <= "0000" WHEN ((saturatechainout_output_clear = "0") or (saturatechainout_output_clear = "none")) ELSE "0001" WHEN (saturatechainout_output_clear = "1") ELSE "0010" WHEN (saturatechainout_output_clear = "2") ELSE "0011" WHEN (saturatechainout_output_clear = "3") ELSE "0000" ; saturatechainout_clk_or <= '1' WHEN clk(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0'; saturatechainout_aclr_or <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; saturatechainout_sload_or <= '1' WHEN ena(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0'; saturatechainout_bypass_register_or <= '1' WHEN (saturatechainout_output_clock = "none") ELSE '0'; saturatechainout_output_register : hardcopyiii_mac_bit_register PORT MAP ( datain => saturatechainout_pip_reg, clk => saturatechainout_clk_or, aclr => saturatechainout_aclr_or, sload => saturatechainout_sload_or, bypass_register => saturatechainout_bypass_register_or, dataout => saturatechainout_out_reg ); --Instantiate the Carry chainout Adder chainout_adder : hardcopyiii_carry_chain_adder PORT MAP ( dataa => rs_dataout_out_reg, datab => chainin_coa_in, dataout => coa_dataout ); --Instantiate the carry chainout adder RS Block coa_rs_block : hardcopyiii_round_saturate_block GENERIC MAP ( dataa_width => dataa_width, datab_width => datab_width, operation_mode => operation_mode, round_mode => round_chain_out_mode, saturate_mode => saturate_chain_out_mode, saturate_width => saturate_chain_out_width, round_width => round_chain_out_width ) PORT MAP ( datain => coa_dataout, round => roundchainout_out_reg, saturate => saturatechainout_out_reg, signa => signa_pip_reg, signb => signb_pip_reg, datain_width => ssa_datain_width, dataout => coa_rs_dataout, saturationoverflow => coa_rs_saturation_overflow ); --Instantiate the rs_saturation_overflow output register (after COA) coa_reg_clkval_or <= "0000" WHEN ((output_clock = "0") or (output_clock = "none")) ELSE "0001" WHEN (output_clock = "1") ELSE "0010" WHEN (output_clock = "2") ELSE "0011" WHEN (output_clock = "3") ELSE "0000" ; coa_reg_aclrval_or <= "0000" WHEN ((output_clear = "0") or (output_clear = "none")) ELSE "0001" WHEN (output_clear = "1") ELSE "0010" WHEN (output_clear = "2") ELSE "0011" WHEN (output_clear = "3") ELSE "0000" ; coa_reg_clk_or <= '1' WHEN clk(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0'; coa_reg_aclr_or <= '1' WHEN (aclr(conv_integer(coa_reg_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0'; coa_reg_sload_or <= '1' WHEN ena(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0'; coa_reg_bypass_register_or <= '1' WHEN (output_clock = "none") ELSE '0'; coa_rs_saturation_overflow_register : hardcopyiii_mac_bit_register PORT MAP ( datain => rs_saturation_overflow_out_reg, clk => coa_reg_clk_or, aclr => coa_reg_aclr_or, sload => coa_reg_sload_or, bypass_register => '1', dataout => coa_rs_saturation_overflow_out_reg ); --Instantiate the rs_saturationchainout_overflow output register coa_rs_saturationchainout_overflow_register : hardcopyiii_mac_bit_register PORT MAP ( datain => coa_rs_saturation_overflow, clk => coa_reg_clk_or, aclr => coa_reg_aclr_or, sload => coa_reg_sload_or, bypass_register => coa_reg_bypass_register_or, dataout => coa_rs_saturationchainout_overflow_out_reg ); -- Instantiate the coa_rs_dataout output register coa_rs_dataout_register : hardcopyiii_mac_register GENERIC MAP ( data_width => 72 ) PORT MAP ( datain => coa_rs_dataout, clk => coa_reg_clk_or, aclr => coa_reg_aclr_or, sload => coa_reg_sload_or, bypass_register => coa_reg_bypass_register_or, dataout => coa_rs_dataout_out_reg ); --Instantiate the shift/Rotate Unit shift_rot_unit : hardcopyiii_rotate_shift_block GENERIC MAP ( dataa_width => dataa_width, datab_width => datab_width ) PORT MAP ( datain => rs_dataout_out_reg, rotate => rotate_out_reg, shiftright => shiftright_out_reg, signa => signa_pip_reg, signb => signb_pip_reg, dataout => dataout_shift_rot ); --Assign the dataout depENDing on the mode of operation dataout_tmp <= coa_rs_dataout_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out")) ELSE dataout_shift_rot when (operation_mode = "shift") ELSE rs_dataout_out_reg; --Assign the loopbackout for loopback mode loopbackout_tmp <= rs_dataout_out_reg when((operation_mode = "loopback") and (zeroloopback_out_reg = '0')) ELSE (others => '0'); --Assign the saturation overflow output saturation_overflow_tmp <= rs_saturation_overflow_out_reg when((operation_mode = "accumulator") or(operation_mode = "two_level_adder")) ELSE coa_rs_saturation_overflow_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out")) ELSE '0'; --Assign the saturationchainout overflow output saturationchainout_overflow_tmp <= coa_rs_saturationchainout_overflow_out_reg when((operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out")) ELSE '0'; dataout <= (others => '0') WHEN (((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out")) and (zerochainout_out_reg = '1')) ELSE dataout_tmp; loopbackout <= loopbackout_tmp(35 downto 18); overflow <= saturation_overflow_tmp; saturatechainoutoverflow <= saturationchainout_overflow_tmp; END arch; ---------------------------------------------------------------------------- -- Module Name : hardcopyiii_io_pad -- Description : Simulation model for hardcopyiii IO pad ---------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; ENTITY hardcopyiii_io_pad IS GENERIC ( lpm_type : string := "hardcopyiii_io_pad"); PORT ( --INPUT PORTS padin : IN std_logic := '0'; -- Input Pad --OUTPUT PORTS padout : OUT std_logic); -- Output Pad END hardcopyiii_io_pad; ARCHITECTURE arch OF hardcopyiii_io_pad IS BEGIN padout <= padin; END arch; --/////////////////////////////////////////////////////////////////////////// -- -- Entity Name : hardcopyiii_mn_cntr -- -- Description : Timing simulation model for the M and N counter. This is a -- common model for the input counter and the loop feedback -- counter of the HARDCOPYIII PLL. -- --/////////////////////////////////////////////////////////////////////////// LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_unsigned.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; ENTITY hardcopyiii_mn_cntr is PORT( clk : IN std_logic; reset : IN std_logic := '0'; cout : OUT std_logic; initial_value : IN integer := 1; modulus : IN integer := 1; time_delay : IN integer := 0 ); END hardcopyiii_mn_cntr; ARCHITECTURE behave of hardcopyiii_mn_cntr is begin process (clk, reset) variable count : integer := 1; variable first_rising_edge : boolean := true; variable tmp_cout : std_logic; begin if (reset = '1') then count := 1; tmp_cout := '0'; first_rising_edge := true; elsif (clk'event) then if (clk = '1' and first_rising_edge) then first_rising_edge := false; tmp_cout := clk; elsif (not first_rising_edge) then if (count < modulus) then count := count + 1; else count := 1; tmp_cout := not tmp_cout; end if; end if; end if; cout <= transport tmp_cout after time_delay * 1 ps; end process; end behave; --///////////////////////////////////////////////////////////////////////////// -- -- Entity Name : hardcopyiii_scale_cntr -- -- Description : Timing simulation model for the output scale-down counters. -- This is a common model for the C0, C1, C2, C3, C4 and C5 -- output counters of the HARDCOPYIII PLL. -- --///////////////////////////////////////////////////////////////////////////// LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; ENTITY hardcopyiii_scale_cntr is PORT( clk : IN std_logic; reset : IN std_logic := '0'; initial : IN integer := 1; high : IN integer := 1; low : IN integer := 1; mode : IN string := "bypass"; ph_tap : IN integer := 0; cout : OUT std_logic ); END hardcopyiii_scale_cntr; ARCHITECTURE behave of hardcopyiii_scale_cntr is begin process (clk, reset) variable tmp_cout : std_logic := '0'; variable count : integer := 1; variable output_shift_count : integer := 1; variable first_rising_edge : boolean := false; begin if (reset = '1') then count := 1; output_shift_count := 1; tmp_cout := '0'; first_rising_edge := false; elsif (clk'event) then if (mode = " off") then tmp_cout := '0'; elsif (mode = "bypass") then tmp_cout := clk; first_rising_edge := true; elsif (not first_rising_edge) then if (clk = '1') then if (output_shift_count = initial) then tmp_cout := clk; first_rising_edge := true; else output_shift_count := output_shift_count + 1; end if; end if; elsif (output_shift_count < initial) then if (clk = '1') then output_shift_count := output_shift_count + 1; end if; else count := count + 1; if (mode = " even" and (count = (high*2) + 1)) then tmp_cout := '0'; elsif (mode = " odd" and (count = high*2)) then tmp_cout := '0'; elsif (count = (high + low)*2 + 1) then tmp_cout := '1'; count := 1; -- reset count end if; end if; end if; cout <= transport tmp_cout; end process; end behave; --///////////////////////////////////////////////////////////////////////////// -- -- Entity Name : hardcopyiii_pll_reg -- -- Description : Simulation model for a simple DFF. -- This is required for the generation of the bit slip-signals. -- No timing, powers upto 0. -- --///////////////////////////////////////////////////////////////////////////// LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY hardcopyiii_pll_reg is PORT( clk : in std_logic; ena : in std_logic := '1'; d : in std_logic; clrn : in std_logic := '1'; prn : in std_logic := '1'; q : out std_logic ); end hardcopyiii_pll_reg; ARCHITECTURE behave of hardcopyiii_pll_reg is begin process (clk, prn, clrn) variable q_reg : std_logic := '0'; begin if (prn = '0') then q_reg := '1'; elsif (clrn = '0') then q_reg := '0'; elsif (clk'event and clk = '1' and (ena = '1')) then q_reg := D; end if; Q <= q_reg; end process; end behave; --/////////////////////////////////////////////////////////////////////////// -- -- Entity Name : hardcopyiii_pll -- -- Description : Timing simulation model for the HARDCOPYIII PLL. -- In the functional mode, it is also the model for the altpll -- megafunction. -- -- Limitations : Does not support Spread Spectrum and Bandwidth. -- -- Outputs : Up to 10 output clocks, each defined by its own set of -- parameters. Locked output (active high) indicates when the -- PLL locks. clkbad and activeclock are used for -- clock switchover to indicate which input clock has gone -- bad, when the clock switchover initiates and which input -- clock is being used as the reference, respectively. -- scandataout is the data output of the serial scan chain. -- --/////////////////////////////////////////////////////////////////////////// LIBRARY IEEE, std; USE IEEE.std_logic_1164.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE STD.TEXTIO.all; USE work.hardcopyiii_atom_pack.all; USE work.hardcopyiii_pllpack.all; USE work.hardcopyiii_mn_cntr; USE work.hardcopyiii_scale_cntr; USE work.hardcopyiii_dffe; USE work.hardcopyiii_pll_reg; -- New Features : The list below outlines key new features in HARDCOPYIII: -- 1. Dynamic Phase Reconfiguration -- 2. Dynamic PLL Reconfiguration (different protocol) -- 3. More output counters ENTITY hardcopyiii_pll is GENERIC ( operation_mode : string := "normal"; pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM compensate_clock : string := "clock0"; inclk0_input_frequency : integer := 0; inclk1_input_frequency : integer := 0; self_reset_on_loss_lock : string := "off"; switch_over_type : string := "auto"; switch_over_counter : integer := 1; enable_switch_over_counter : string := "off"; dpa_multiply_by : integer := 0; dpa_divide_by : integer := 0; dpa_divider : integer := 0; bandwidth : integer := 0; bandwidth_type : string := "auto"; use_dc_coupling : string := "false"; lock_c : integer := 4; sim_gate_lock_device_behavior : string := "off"; lock_high : integer := 0; lock_low : integer := 0; lock_window_ui : string := "0.05"; lock_window : time := 5 ps; test_bypass_lock_detect : string := "off"; clk0_output_frequency : integer := 0; clk0_multiply_by : integer := 0; clk0_divide_by : integer := 0; clk0_phase_shift : string := "0"; clk0_duty_cycle : integer := 50; clk1_output_frequency : integer := 0; clk1_multiply_by : integer := 0; clk1_divide_by : integer := 0; clk1_phase_shift : string := "0"; clk1_duty_cycle : integer := 50; clk2_output_frequency : integer := 0; clk2_multiply_by : integer := 0; clk2_divide_by : integer := 0; clk2_phase_shift : string := "0"; clk2_duty_cycle : integer := 50; clk3_output_frequency : integer := 0; clk3_multiply_by : integer := 0; clk3_divide_by : integer := 0; clk3_phase_shift : string := "0"; clk3_duty_cycle : integer := 50; clk4_output_frequency : integer := 0; clk4_multiply_by : integer := 0; clk4_divide_by : integer := 0; clk4_phase_shift : string := "0"; clk4_duty_cycle : integer := 50; clk5_output_frequency : integer := 0; clk5_multiply_by : integer := 0; clk5_divide_by : integer := 0; clk5_phase_shift : string := "0"; clk5_duty_cycle : integer := 50; clk6_output_frequency : integer := 0; clk6_multiply_by : integer := 0; clk6_divide_by : integer := 0; clk6_phase_shift : string := "0"; clk6_duty_cycle : integer := 50; clk7_output_frequency : integer := 0; clk7_multiply_by : integer := 0; clk7_divide_by : integer := 0; clk7_phase_shift : string := "0"; clk7_duty_cycle : integer := 50; clk8_output_frequency : integer := 0; clk8_multiply_by : integer := 0; clk8_divide_by : integer := 0; clk8_phase_shift : string := "0"; clk8_duty_cycle : integer := 50; clk9_output_frequency : integer := 0; clk9_multiply_by : integer := 0; clk9_divide_by : integer := 0; clk9_phase_shift : string := "0"; clk9_duty_cycle : integer := 50; pfd_min : integer := 0; pfd_max : integer := 0; vco_min : integer := 0; vco_max : integer := 0; vco_center : integer := 0; -- ADVANCED USER PARAMETERS m_initial : integer := 1; m : integer := 0; n : integer := 1; c0_high : integer := 1; c0_low : integer := 1; c0_initial : integer := 1; c0_mode : string := "bypass"; c0_ph : integer := 0; c1_high : integer := 1; c1_low : integer := 1; c1_initial : integer := 1; c1_mode : string := "bypass"; c1_ph : integer := 0; c2_high : integer := 1; c2_low : integer := 1; c2_initial : integer := 1; c2_mode : string := "bypass"; c2_ph : integer := 0; c3_high : integer := 1; c3_low : integer := 1; c3_initial : integer := 1; c3_mode : string := "bypass"; c3_ph : integer := 0; c4_high : integer := 1; c4_low : integer := 1; c4_initial : integer := 1; c4_mode : string := "bypass"; c4_ph : integer := 0; c5_high : integer := 1; c5_low : integer := 1; c5_initial : integer := 1; c5_mode : string := "bypass"; c5_ph : integer := 0; c6_high : integer := 1; c6_low : integer := 1; c6_initial : integer := 1; c6_mode : string := "bypass"; c6_ph : integer := 0; c7_high : integer := 1; c7_low : integer := 1; c7_initial : integer := 1; c7_mode : string := "bypass"; c7_ph : integer := 0; c8_high : integer := 1; c8_low : integer := 1; c8_initial : integer := 1; c8_mode : string := "bypass"; c8_ph : integer := 0; c9_high : integer := 1; c9_low : integer := 1; c9_initial : integer := 1; c9_mode : string := "bypass"; c9_ph : integer := 0; m_ph : integer := 0; clk0_counter : string := "unused"; clk1_counter : string := "unused"; clk2_counter : string := "unused"; clk3_counter : string := "unused"; clk4_counter : string := "unused"; clk5_counter : string := "unused"; clk6_counter : string := "unused"; clk7_counter : string := "unused"; clk8_counter : string := "unused"; clk9_counter : string := "unused"; c1_use_casc_in : string := "off"; c2_use_casc_in : string := "off"; c3_use_casc_in : string := "off"; c4_use_casc_in : string := "off"; c5_use_casc_in : string := "off"; c6_use_casc_in : string := "off"; c7_use_casc_in : string := "off"; c8_use_casc_in : string := "off"; c9_use_casc_in : string := "off"; m_test_source : integer := -1; c0_test_source : integer := -1; c1_test_source : integer := -1; c2_test_source : integer := -1; c3_test_source : integer := -1; c4_test_source : integer := -1; c5_test_source : integer := -1; c6_test_source : integer := -1; c7_test_source : integer := -1; c8_test_source : integer := -1; c9_test_source : integer := -1; vco_multiply_by : integer := 0; vco_divide_by : integer := 0; vco_post_scale : integer := 1; vco_frequency_control : string := "auto"; vco_phase_shift_step : integer := 0; charge_pump_current : integer := 10; loop_filter_r : string := " 1.0"; loop_filter_c : integer := 0; pll_compensation_delay : integer := 0; simulation_type : string := "functional"; lpm_type : string := "hardcopyiii_pll"; clk0_use_even_counter_mode : string := "off"; clk1_use_even_counter_mode : string := "off"; clk2_use_even_counter_mode : string := "off"; clk3_use_even_counter_mode : string := "off"; clk4_use_even_counter_mode : string := "off"; clk5_use_even_counter_mode : string := "off"; clk6_use_even_counter_mode : string := "off"; clk7_use_even_counter_mode : string := "off"; clk8_use_even_counter_mode : string := "off"; clk9_use_even_counter_mode : string := "off"; clk0_use_even_counter_value : string := "off"; clk1_use_even_counter_value : string := "off"; clk2_use_even_counter_value : string := "off"; clk3_use_even_counter_value : string := "off"; clk4_use_even_counter_value : string := "off"; clk5_use_even_counter_value : string := "off"; clk6_use_even_counter_value : string := "off"; clk7_use_even_counter_value : string := "off"; clk8_use_even_counter_value : string := "off"; clk9_use_even_counter_value : string := "off"; -- Test only init_block_reset_a_count : integer := 1; init_block_reset_b_count : integer := 1; charge_pump_current_bits : integer := 0; lock_window_ui_bits : integer := 0; loop_filter_c_bits : integer := 0; loop_filter_r_bits : integer := 0; test_counter_c0_delay_chain_bits : integer := 0; test_counter_c1_delay_chain_bits : integer := 0; test_counter_c2_delay_chain_bits : integer := 0; test_counter_c3_delay_chain_bits : integer := 0; test_counter_c4_delay_chain_bits : integer := 0; test_counter_c5_delay_chain_bits : integer := 0; test_counter_c6_delay_chain_bits : integer := 0; test_counter_c7_delay_chain_bits : integer := 0; test_counter_c8_delay_chain_bits : integer := 0; test_counter_c9_delay_chain_bits : integer := 0; test_counter_m_delay_chain_bits : integer := 0; test_counter_n_delay_chain_bits : integer := 0; test_feedback_comp_delay_chain_bits : integer := 0; test_input_comp_delay_chain_bits : integer := 0; test_volt_reg_output_mode_bits : integer := 0; test_volt_reg_output_voltage_bits : integer := 0; test_volt_reg_test_mode : string := "false"; vco_range_detector_high_bits : integer := -1; vco_range_detector_low_bits : integer := -1; scan_chain_mif_file : string := ""; dpa_output_clock_phase_shift : integer := 0; test_counter_c3_sclk_delay_chain_bits : integer := -1; test_counter_c4_sclk_delay_chain_bits : integer := -1; test_counter_c5_lden_delay_chain_bits : integer := -1; test_counter_c6_lden_delay_chain_bits : integer := -1; auto_settings : string := "true"; -- Simulation only generics family_name : string := "HARDCOPYIII"; -- VITAL generics XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; TimingChecksOn : Boolean := true; InstancePath : STRING := "*"; tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); tipd_ena : VitalDelayType01 := DefPropDelay01; tipd_pfdena : VitalDelayType01 := DefPropDelay01; tipd_areset : VitalDelayType01 := DefPropDelay01; tipd_fbin : VitalDelayType01 := DefPropDelay01; tipd_scanclk : VitalDelayType01 := DefPropDelay01; tipd_scanclkena : VitalDelayType01 := DefPropDelay01; tipd_scandata : VitalDelayType01 := DefPropDelay01; tipd_configupdate : VitalDelayType01 := DefPropDelay01; tipd_clkswitch : VitalDelayType01 := DefPropDelay01; tipd_phaseupdown : VitalDelayType01 := DefPropDelay01; tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); tipd_phasestep : VitalDelayType01 := DefPropDelay01; tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; use_vco_bypass : string := "false" ); PORT ( inclk : in std_logic_vector(1 downto 0); fbin : in std_logic := '0'; fbout : out std_logic; clkswitch : in std_logic := '0'; areset : in std_logic := '0'; pfdena : in std_logic := '1'; scandata : in std_logic := '0'; scanclk : in std_logic := '0'; scanclkena : in std_logic := '1'; configupdate : in std_logic := '0'; clk : out std_logic_vector(9 downto 0); phasecounterselect : in std_logic_vector(3 downto 0) := "0000"; phaseupdown : in std_logic := '0'; phasestep : in std_logic := '0'; clkbad : out std_logic_vector(1 downto 0); activeclock : out std_logic; locked : out std_logic; scandataout : out std_logic; scandone : out std_logic; phasedone : out std_logic; vcooverrange : out std_logic; vcounderrange : out std_logic ); END hardcopyiii_pll; ARCHITECTURE vital_pll of hardcopyiii_pll is function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is begin if (i_vco_post_scale = 1) then return vco_min * 2; else return vco_min; end if; end; function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is begin if (i_vco_post_scale = 1) then return vco_max * 2; else return vco_max; end if; end; TYPE int_array is ARRAY(NATURAL RANGE <>) of integer; TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6); TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9); TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic; constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale); constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale); -- internal advanced parameter signals signal i_vco_min : integer := vco_min; signal i_vco_max : integer := vco_max; signal i_vco_center : integer; signal i_pfd_min : integer; signal i_pfd_max : integer; signal c_ph_val : int_array(0 to 9) := (OTHERS => 0); signal c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0); signal c_high_val : int_array(0 to 9) := (OTHERS => 1); signal c_low_val : int_array(0 to 9) := (OTHERS => 1); signal c_initial_val : int_array(0 to 9) := (OTHERS => 1); signal c_mode_val : str_array(0 to 9); signal clk_num : str_array(0 to 9); -- old values signal c_high_val_old : int_array(0 to 9) := (OTHERS => 1); signal c_low_val_old : int_array(0 to 9) := (OTHERS => 1); signal c_ph_val_old : int_array(0 to 9) := (OTHERS => 0); signal c_mode_val_old : str_array(0 to 9); -- hold registers signal c_high_val_hold : int_array(0 to 9) := (OTHERS => 1); signal c_low_val_hold : int_array(0 to 9) := (OTHERS => 1); signal c_ph_val_hold : int_array(0 to 9) := (OTHERS => 0); signal c_mode_val_hold : str_array(0 to 9); -- temp registers signal sig_c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0); signal c_ph_val_orig : int_array(0 to 9) := (OTHERS => 0); signal i_clk9_counter : integer := 9; signal i_clk8_counter : integer := 8; signal i_clk7_counter : integer := 7; signal i_clk6_counter : integer := 6; signal i_clk5_counter : integer := 5; signal real_lock_high : integer := 0; signal i_clk4_counter : integer := 4; signal i_clk3_counter : integer := 3; signal i_clk2_counter : integer := 2; signal i_clk1_counter : integer := 1; signal i_clk0_counter : integer := 0; signal i_charge_pump_current : integer; signal i_loop_filter_r : integer; -- end internal advanced parameter signals -- CONSTANTS CONSTANT SCAN_CHAIN : integer := 144; CONSTANT GPP_SCAN_CHAIN : integer := 234; CONSTANT FAST_SCAN_CHAIN : integer := 180; CONSTANT cntrs : str_array(9 downto 0) := (" C9", " C8", " C7", " C6", " C5", " C4", " C3", " C2", " C1", " C0"); CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2"); CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0); CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0); CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); CONSTANT num_phase_taps : integer := 8; -- signals signal vcc : std_logic := '1'; signal fbclk : std_logic; signal refclk : std_logic; signal vco_over : std_logic := '0'; signal vco_under : std_logic := '1'; signal pll_locked : boolean := false; signal c_clk : std_logic_array(0 to 9); signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0'); -- signals to assign values to counter params signal m_val : integer := 1; signal n_val : integer := 1; signal m_ph_val : integer := 0; signal m_ph_initial : integer := 0; signal m_ph_val_tmp : integer := 0; signal m_initial_val : integer := m_initial; signal m_mode_val : string(1 to 6) := " "; signal n_mode_val : string(1 to 6) := " "; signal lfc_val : integer := 0; signal vco_cur : integer := vco_post_scale; signal cp_curr_val : integer := 0; signal lfr_val : string(1 to 2) := " "; signal cp_curr_old_bit_setting : integer := charge_pump_current_bits; signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0'); signal lfr_old_bit_setting : integer := loop_filter_r_bits; signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0'); signal lfc_old_bit_setting : integer := loop_filter_c_bits; signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0'); signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true -- old values signal m_val_old : integer := 1; signal n_val_old : integer := 1; signal m_mode_val_old : string(1 to 6) := " "; signal n_mode_val_old : string(1 to 6) := " "; signal m_ph_val_old : integer := 0; signal lfc_old : integer := 0; signal vco_old : integer := 0; signal cp_curr_old : integer := 0; signal lfr_old : string(1 to 2) := " "; signal num_output_cntrs : integer := 10; signal scanclk_period : time := 1 ps; signal scan_data : std_logic_vector(0 to 233) := (OTHERS => '0'); signal clk_pfd : std_logic_vector(0 to 9); signal clk0_tmp : std_logic; signal clk1_tmp : std_logic; signal clk2_tmp : std_logic; signal clk3_tmp : std_logic; signal clk4_tmp : std_logic; signal clk5_tmp : std_logic; signal clk6_tmp : std_logic; signal clk7_tmp : std_logic; signal clk8_tmp : std_logic; signal clk9_tmp : std_logic; signal update_conf_latches : std_logic := '0'; signal update_conf_latches_reg : std_logic := '0'; signal clkin : std_logic := '0'; signal gate_locked : std_logic := '0'; signal pfd_locked : std_logic := '0'; signal lock : std_logic := '0'; signal about_to_lock : boolean := false; signal reconfig_err : boolean := false; signal inclk_c0 : std_logic; signal inclk_c1 : std_logic; signal inclk_c2 : std_logic; signal inclk_c3 : std_logic; signal inclk_c4 : std_logic; signal inclk_c5 : std_logic; signal inclk_c6 : std_logic; signal inclk_c7 : std_logic; signal inclk_c8 : std_logic; signal inclk_c9 : std_logic; signal inclk_m : std_logic; signal devpor : std_logic; signal devclrn : std_logic; signal inclk0_ipd : std_logic; signal inclk1_ipd : std_logic; signal pfdena_ipd : std_logic; signal areset_ipd : std_logic; signal fbin_ipd : std_logic; signal scanclk_ipd : std_logic; signal scanclkena_ipd, scanclkena_reg : std_logic; signal scandata_ipd : std_logic; signal clkswitch_ipd : std_logic; signal phasecounterselect_ipd : std_logic_vector(3 downto 0); signal phaseupdown_ipd : std_logic; signal phasestep_ipd : std_logic; signal configupdate_ipd : std_logic; -- registered signals signal sig_offset : time := 0 ps; signal sig_refclk_time : time := 0 ps; signal sig_fbclk_period : time := 0 ps; signal sig_vco_period_was_phase_adjusted : boolean := false; signal sig_phase_adjust_was_scheduled : boolean := false; signal sig_stop_vco : std_logic := '0'; signal sig_m_times_vco_period : time := 0 ps; signal sig_new_m_times_vco_period : time := 0 ps; signal sig_got_refclk_posedge : boolean := false; signal sig_got_fbclk_posedge : boolean := false; signal sig_got_second_refclk : boolean := false; signal m_delay : integer := 0; signal n_delay : integer := 0; signal inclk1_tmp : std_logic := '0'; signal reset_low : std_logic := '0'; -- Phase Reconfig SIGNAL phasecounterselect_reg : std_logic_vector(3 DOWNTO 0); SIGNAL phaseupdown_reg : std_logic := '0'; SIGNAL phasestep_reg : std_logic := '0'; SIGNAL phasestep_high_count : integer := 0; SIGNAL update_phase : std_logic := '0'; signal scandataout_tmp : std_logic := '0'; signal scandata_in : std_logic := '0'; signal scandata_out : std_logic := '0'; signal scandone_tmp : std_logic := '1'; signal initiate_reconfig : std_logic := '0'; signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n; signal schedule_vco : std_logic := '0'; signal areset_ena_sig : std_logic := '0'; signal pll_in_test_mode : boolean := false; signal pll_has_just_been_reconfigured : boolean := false; signal inclk_c_from_vco : std_logic_array(0 to 9); signal inclk_m_from_vco : std_logic; SIGNAL inclk0_period : time := 0 ps; SIGNAL last_inclk0_period : time := 0 ps; SIGNAL last_inclk0_edge : time := 0 ps; SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0'; SIGNAL inclk1_period : time := 0 ps; SIGNAL last_inclk1_period : time := 0 ps; SIGNAL last_inclk1_edge : time := 0 ps; SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0'; COMPONENT hardcopyiii_mn_cntr PORT ( clk : IN std_logic; reset : IN std_logic := '0'; cout : OUT std_logic; initial_value : IN integer := 1; modulus : IN integer := 1; time_delay : IN integer := 0 ); END COMPONENT; COMPONENT hardcopyiii_scale_cntr PORT ( clk : IN std_logic; reset : IN std_logic := '0'; cout : OUT std_logic; initial : IN integer := 1; high : IN integer := 1; low : IN integer := 1; mode : IN string := "bypass"; ph_tap : IN integer := 0 ); END COMPONENT; COMPONENT hardcopyiii_dffe GENERIC( TimingChecksOn: Boolean := true; InstancePath: STRING := "*"; XOn: Boolean := DefGlitchXOn; MsgOn: Boolean := DefGlitchMsgOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01; tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01; tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01; tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01; tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst; tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst; thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tipd_D : VitalDelayType01 := DefPropDelay01; tipd_CLRN : VitalDelayType01 := DefPropDelay01; tipd_PRN : VitalDelayType01 := DefPropDelay01; tipd_CLK : VitalDelayType01 := DefPropDelay01; tipd_ENA : VitalDelayType01 := DefPropDelay01); PORT( Q : out STD_LOGIC := '0'; D : in STD_LOGIC := '1'; CLRN : in STD_LOGIC := '1'; PRN : in STD_LOGIC := '1'; CLK : in STD_LOGIC := '0'; ENA : in STD_LOGIC := '1'); END COMPONENT; COMPONENT hardcopyiii_pll_reg PORT( Q : out STD_LOGIC := '0'; D : in STD_LOGIC := '1'; CLRN : in STD_LOGIC := '1'; PRN : in STD_LOGIC := '1'; CLK : in STD_LOGIC := '0'; ENA : in STD_LOGIC := '1'); END COMPONENT; begin ---------------------- -- INPUT PATH DELAYs ---------------------- WireDelay : block begin VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0)); VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1)); VitalWireDelay (areset_ipd, areset, tipd_areset); VitalWireDelay (fbin_ipd, fbin, tipd_fbin); VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena); VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk); VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena); VitalWireDelay (scandata_ipd, scandata, tipd_scandata); VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate); VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch); VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown); VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep); VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0)); VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1)); VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2)); VitalWireDelay (phasecounterselect_ipd(3), phasecounterselect(3), tipd_phasecounterselect(3)); end block; inclk_m <= fbclk when m_test_source = 0 else refclk when m_test_source = 1 else inclk_m_from_vco; areset_ena_sig <= areset_ipd or sig_stop_vco; pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or c1_test_source /= -1 or c2_test_source /= -1 or c3_test_source /= -1 or c4_test_source /= -1 or c5_test_source /= -1 or c6_test_source /= -1 or c7_test_source /= -1 or c8_test_source /= -1 or c9_test_source /= -1) else false; real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0; m1 : hardcopyiii_mn_cntr port map ( clk => inclk_m, reset => areset_ena_sig, cout => fbclk, initial_value => m_initial_val, modulus => m_val, time_delay => m_delay ); -- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed -- in different simulation deltas. inclk1_tmp <= inclk1_ipd; -- Calculate the inclk0 period PROCESS VARIABLE inclk0_period_tmp : time := 0 ps; BEGIN WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1'); IF (first_inclk0_edge_detect = '0') THEN first_inclk0_edge_detect <= '1'; ELSE last_inclk0_period <= inclk0_period; inclk0_period_tmp := NOW - last_inclk0_edge; END IF; last_inclk0_edge <= NOW; inclk0_period <= inclk0_period_tmp; END PROCESS; -- Calculate the inclk1 period PROCESS VARIABLE inclk1_period_tmp : time := 0 ps; BEGIN WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1'); IF (first_inclk1_edge_detect = '0') THEN first_inclk1_edge_detect <= '1'; ELSE last_inclk1_period <= inclk1_period; inclk1_period_tmp := NOW - last_inclk1_edge; END IF; last_inclk1_edge <= NOW; inclk1_period <= inclk1_period_tmp; END PROCESS; process (inclk0_ipd, inclk1_tmp, clkswitch_ipd) variable input_value : std_logic := '0'; variable current_clock : integer := 0; variable clk0_count, clk1_count : integer := 0; variable clk0_is_bad, clk1_is_bad : std_logic := '0'; variable primary_clk_is_bad : boolean := false; variable current_clk_is_bad : boolean := false; variable got_curr_clk_falling_edge_after_clkswitch : boolean := false; variable switch_over_count : integer := 0; variable active_clock : std_logic := '0'; variable external_switch : boolean := false; variable diff_percent_period : integer := 0; variable buf : line; variable switch_clock : boolean := false; begin if (now = 0 ps) then if (switch_over_type = "manual" and clkswitch_ipd = '1') then current_clock := 1; active_clock := '1'; end if; end if; if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then external_switch := true; elsif (switch_over_type = "manual") then if (clkswitch_ipd'event and clkswitch_ipd = '1') then switch_clock := true; elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then switch_clock := false; end if; end if; if (switch_clock = true) then if (inclk0_ipd'event or inclk1_tmp'event) then if (current_clock = 0) then current_clock := 1; active_clock := '1'; clkin <= transport inclk1_tmp; elsif (current_clock = 1) then current_clock := 0; active_clock := '0'; clkin <= transport inclk0_ipd; end if; switch_clock := false; end if; end if; -- save the current inclk event value if (inclk0_ipd'event) then input_value := inclk0_ipd; elsif (inclk1_tmp'event) then input_value := inclk1_tmp; end if; -- check if either input clk is bad if (inclk0_ipd'event and inclk0_ipd = '1') then clk0_count := clk0_count + 1; clk0_is_bad := '0'; clk1_count := 0; if (clk0_count > 2) then -- no event on other clk for 2 cycles clk1_is_bad := '1'; if (current_clock = 1) then current_clk_is_bad := true; end if; end if; end if; if (inclk1_tmp'event and inclk1_tmp = '1') then clk1_count := clk1_count + 1; clk1_is_bad := '0'; clk0_count := 0; if (clk1_count > 2) then -- no event on other clk for 2 cycles clk0_is_bad := '1'; if (current_clock = 0) then current_clk_is_bad := true; end if; end if; end if; -- check if the bad clk is the primary clock if (clk0_is_bad = '1') then primary_clk_is_bad := true; else primary_clk_is_bad := false; end if; -- actual switching if (inclk0_ipd'event and current_clock = 0) then if (external_switch) then if (not got_curr_clk_falling_edge_after_clkswitch) then if (inclk0_ipd = '0') then got_curr_clk_falling_edge_after_clkswitch := true; end if; clkin <= transport inclk0_ipd; end if; else clkin <= transport inclk0_ipd; end if; elsif (inclk1_tmp'event and current_clock = 1) then if (external_switch) then if (not got_curr_clk_falling_edge_after_clkswitch) then if (inclk1_tmp = '0') then got_curr_clk_falling_edge_after_clkswitch := true; end if; clkin <= transport inclk1_tmp; end if; else clkin <= transport inclk1_tmp; end if; else if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then switch_over_count := switch_over_count + 1; end if; if ((input_value = '0')) then if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then got_curr_clk_falling_edge_after_clkswitch := false; if (areset_ipd = '0') then if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period; elsif (inclk0_period /= 0 ps) then diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period; end if; if((diff_percent_period > 20)and ( switch_over_type = "auto")) then WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality.")); writeline(output, buf); end if; end if; if (current_clock = 0) then current_clock := 1; else current_clock := 0; end if; active_clock := not active_clock; switch_over_count := 0; external_switch := false; current_clk_is_bad := false; else if(switch_over_type = "auto") then if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then current_clock := 1; active_clock := not active_clock; end if; if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then current_clock := 0; active_clock := not active_clock; end if; end if; end if; end if; end if; -- schedule outputs clkbad(0) <= clk0_is_bad; clkbad(1) <= clk1_is_bad; activeclock <= active_clock; end process; n1 : hardcopyiii_mn_cntr port map ( clk => clkin, reset => areset_ipd, cout => refclk, initial_value => n_val, modulus => n_val); inclk_c0 <= refclk when c0_test_source = 1 else fbclk when c0_test_source = 0 else inclk_c_from_vco(0); c0 : hardcopyiii_scale_cntr port map ( clk => inclk_c0, reset => areset_ena_sig, cout => c_clk(0), initial => c_initial_val(0), high => c_high_val(0), low => c_low_val(0), mode => c_mode_val(0), ph_tap => c_ph_val(0)); inclk_c1 <= refclk when c1_test_source = 1 else fbclk when c1_test_source = 0 else c_clk(0) when c1_use_casc_in = "on" else inclk_c_from_vco(1); c1 : hardcopyiii_scale_cntr port map ( clk => inclk_c1, reset => areset_ena_sig, cout => c_clk(1), initial => c_initial_val(1), high => c_high_val(1), low => c_low_val(1), mode => c_mode_val(1), ph_tap => c_ph_val(1)); inclk_c2 <= refclk when c2_test_source = 1 else fbclk when c2_test_source = 0 else c_clk(1) when c2_use_casc_in = "on" else inclk_c_from_vco(2); c2 : hardcopyiii_scale_cntr port map ( clk => inclk_c2, reset => areset_ena_sig, cout => c_clk(2), initial => c_initial_val(2), high => c_high_val(2), low => c_low_val(2), mode => c_mode_val(2), ph_tap => c_ph_val(2)); inclk_c3 <= refclk when c3_test_source = 1 else fbclk when c3_test_source = 0 else c_clk(2) when c3_use_casc_in = "on" else inclk_c_from_vco(3); c3 : hardcopyiii_scale_cntr port map ( clk => inclk_c3, reset => areset_ena_sig, cout => c_clk(3), initial => c_initial_val(3), high => c_high_val(3), low => c_low_val(3), mode => c_mode_val(3), ph_tap => c_ph_val(3)); inclk_c4 <= refclk when c4_test_source = 1 else fbclk when c4_test_source = 0 else c_clk(3) when (c4_use_casc_in = "on") else inclk_c_from_vco(4); c4 : hardcopyiii_scale_cntr port map ( clk => inclk_c4, reset => areset_ena_sig, cout => c_clk(4), initial => c_initial_val(4), high => c_high_val(4), low => c_low_val(4), mode => c_mode_val(4), ph_tap => c_ph_val(4)); inclk_c5 <= refclk when c5_test_source = 1 else fbclk when c5_test_source = 0 else c_clk(4) when c5_use_casc_in = "on" else inclk_c_from_vco(5); c5 : hardcopyiii_scale_cntr port map ( clk => inclk_c5, reset => areset_ena_sig, cout => c_clk(5), initial => c_initial_val(5), high => c_high_val(5), low => c_low_val(5), mode => c_mode_val(5), ph_tap => c_ph_val(5)); inclk_c6 <= refclk when c6_test_source = 1 else fbclk when c6_test_source = 0 else c_clk(5) when c6_use_casc_in = "on" else inclk_c_from_vco(6); c6 : hardcopyiii_scale_cntr port map ( clk => inclk_c6, reset => areset_ena_sig, cout => c_clk(6), initial => c_initial_val(6), high => c_high_val(6), low => c_low_val(6), mode => c_mode_val(6), ph_tap => c_ph_val(6)); inclk_c7 <= refclk when c7_test_source = 1 else fbclk when c7_test_source = 0 else c_clk(6) when c7_use_casc_in = "on" else inclk_c_from_vco(7); c7 : hardcopyiii_scale_cntr port map ( clk => inclk_c7, reset => areset_ena_sig, cout => c_clk(7), initial => c_initial_val(7), high => c_high_val(7), low => c_low_val(7), mode => c_mode_val(7), ph_tap => c_ph_val(7)); inclk_c8 <= refclk when c8_test_source = 1 else fbclk when c8_test_source = 0 else c_clk(7) when c8_use_casc_in = "on" else inclk_c_from_vco(8); c8 : hardcopyiii_scale_cntr port map ( clk => inclk_c8, reset => areset_ena_sig, cout => c_clk(8), initial => c_initial_val(8), high => c_high_val(8), low => c_low_val(8), mode => c_mode_val(8), ph_tap => c_ph_val(8)); inclk_c9 <= refclk when c9_test_source = 1 else fbclk when c9_test_source = 0 else c_clk(8) when c9_use_casc_in = "on" else inclk_c_from_vco(9); c9 : hardcopyiii_scale_cntr port map ( clk => inclk_c9, reset => areset_ena_sig, cout => c_clk(9), initial => c_initial_val(9), high => c_high_val(9), low => c_low_val(9), mode => c_mode_val(9), ph_tap => c_ph_val(9)); process(scandone_tmp, lock) begin if (scandone_tmp'event and (scandone_tmp = '1')) then pll_has_just_been_reconfigured <= true; elsif (lock'event and (lock = '1')) then pll_has_just_been_reconfigured <= false; end if; end process; process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco) variable c0_got_first_rising_edge : boolean := false; variable c0_count : integer := 2; variable c0_initial_count : integer := 1; variable c0_tmp, c1_tmp : std_logic := '0'; variable c1_got_first_rising_edge : boolean := false; variable c1_count : integer := 2; variable c1_initial_count : integer := 1; begin if (areset_ipd = '1' or sig_stop_vco = '1') then c0_count := 2; c1_count := 2; c0_initial_count := 1; c1_initial_count := 1; c0_got_first_rising_edge := false; c1_got_first_rising_edge := false; else if (not c0_got_first_rising_edge) then if (inclk_c0'event and inclk_c0 = '1') then if (c0_initial_count = c_initial_val(0)) then c0_got_first_rising_edge := true; else c0_initial_count := c0_initial_count + 1; end if; end if; elsif (inclk_c0'event) then c0_count := c0_count + 1; if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then c0_count := 1; end if; end if; if (inclk_c0'event and inclk_c0 = '0') then if (c0_count = 1) then c0_tmp := '1'; c0_got_first_rising_edge := false; else c0_tmp := '0'; end if; end if; if (not c1_got_first_rising_edge) then if (inclk_c1'event and inclk_c1 = '1') then if (c1_initial_count = c_initial_val(1)) then c1_got_first_rising_edge := true; else c1_initial_count := c1_initial_count + 1; end if; end if; elsif (inclk_c1'event) then c1_count := c1_count + 1; if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then c1_count := 1; end if; end if; if (inclk_c1'event and inclk_c1 = '0') then if (c1_count = 1) then c1_tmp := '1'; c1_got_first_rising_edge := false; else c1_tmp := '0'; end if; end if; end if; end process; locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE lock; process (scandone_tmp) variable buf : line; begin if (scandone_tmp'event and scandone_tmp = '1') then if (reconfig_err = false) then ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note; write (buf, string'(" N modulus = ")); write (buf, n_val); write (buf, string'(" ( ")); write (buf, n_val_old); write (buf, string'(" )")); writeline (output, buf); write (buf, string'(" M modulus = ")); write (buf, m_val); write (buf, string'(" ( ")); write (buf, m_val_old); write (buf, string'(" )")); writeline (output, buf); write (buf, string'(" M ph_tap = ")); write (buf, m_ph_val); write (buf, string'(" ( ")); write (buf, m_ph_val_old); write (buf, string'(" )")); writeline (output, buf); for i in 0 to (num_output_cntrs-1) loop write (buf, clk_num(i)); write (buf, string'(" : ")); write (buf, cntrs(i)); write (buf, string'(" : high = ")); write (buf, c_high_val(i)); write (buf, string'(" (")); write (buf, c_high_val_old(i)); write (buf, string'(") ")); write (buf, string'(" , low = ")); write (buf, c_low_val(i)); write (buf, string'(" (")); write (buf, c_low_val_old(i)); write (buf, string'(") ")); write (buf, string'(" , mode = ")); write (buf, c_mode_val(i)); write (buf, string'(" (")); write (buf, c_mode_val_old(i)); write (buf, string'(") ")); write (buf, string'(" , phase tap = ")); write (buf, c_ph_val(i)); write (buf, string'(" (")); write (buf, c_ph_val_old(i)); write (buf, string'(") ")); writeline(output, buf); end loop; IF (pll_reconfig_display_full_setting) THEN write (buf, string'(" Charge Pump Current (uA) = ")); write (buf, cp_curr_val); write (buf, string'(" ( ")); write (buf, cp_curr_old); write (buf, string'(" ) ")); writeline (output, buf); write (buf, string'(" Loop Filter Capacitor (pF) = ")); write (buf, lfc_val); write (buf, string'(" ( ")); write (buf, lfc_old); write (buf, string'(" ) ")); writeline (output, buf); write (buf, string'(" Loop Filter Resistor (Kohm) = ")); write (buf, lfr_val); write (buf, string'(" ( ")); write (buf, lfr_old); write (buf, string'(" ) ")); writeline (output, buf); write (buf, string'(" VCO_Post_Scale = ")); write (buf, vco_cur); write (buf, string'(" ( ")); write (buf, vco_old); write (buf, string'(" ) ")); writeline (output, buf); ELSE write (buf, string'(" Charge Pump Current (bit setting) = ")); write (buf, alt_conv_integer(cp_curr_val_bit_setting)); write (buf, string'(" ( ")); write (buf, cp_curr_old_bit_setting); write (buf, string'(" ) ")); writeline (output, buf); write (buf, string'(" Loop Filter Capacitor (bit setting) = ")); write (buf, alt_conv_integer(lfc_val_bit_setting)); write (buf, string'(" ( ")); write (buf, lfc_old_bit_setting); write (buf, string'(" ) ")); writeline (output, buf); write (buf, string'(" Loop Filter Resistor (bit setting) = ")); write (buf, alt_conv_integer(lfr_val_bit_setting)); write (buf, string'(" ( ")); write (buf, lfr_old_bit_setting); write (buf, string'(" ) ")); writeline (output, buf); write (buf, string'(" VCO_Post_Scale = ")); write (buf, vco_cur); write (buf, string'(" ( ")); write (buf, vco_old); write (buf, string'(" ) ")); writeline (output, buf); END IF; cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting); lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting); lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting); else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning; end if; end if; end process; update_conf_latches <= configupdate_ipd; process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), c_clk(6), c_clk(7), c_clk(8), c_clk(9), vco_out, fbclk, scanclk_ipd) variable init : boolean := true; variable low, high : std_logic_vector(7 downto 0); variable low_fast, high_fast : std_logic_vector(3 downto 0); variable mode : string(1 to 6) := "bypass"; variable is_error : boolean := false; variable m_tmp, n_tmp : std_logic_vector(8 downto 0); variable lfr_val_tmp : string(1 to 2) := " "; variable c_high_val_tmp,c_hval : int_array(0 to 9) := (OTHERS => 1); variable c_low_val_tmp,c_lval : int_array(0 to 9) := (OTHERS => 1); variable c_mode_val_tmp : str_array(0 to 9); variable m_val_tmp : integer := 0; variable c0_rising_edge_transfer_done : boolean := false; variable c1_rising_edge_transfer_done : boolean := false; variable c2_rising_edge_transfer_done : boolean := false; variable c3_rising_edge_transfer_done : boolean := false; variable c4_rising_edge_transfer_done : boolean := false; variable c5_rising_edge_transfer_done : boolean := false; variable c6_rising_edge_transfer_done : boolean := false; variable c7_rising_edge_transfer_done : boolean := false; variable c8_rising_edge_transfer_done : boolean := false; variable c9_rising_edge_transfer_done : boolean := false; -- variables for scaling of multiply_by and divide_by values variable i_clk0_mult_by : integer := 1; variable i_clk0_div_by : integer := 1; variable i_clk1_mult_by : integer := 1; variable i_clk1_div_by : integer := 1; variable i_clk2_mult_by : integer := 1; variable i_clk2_div_by : integer := 1; variable i_clk3_mult_by : integer := 1; variable i_clk3_div_by : integer := 1; variable i_clk4_mult_by : integer := 1; variable i_clk4_div_by : integer := 1; variable i_clk5_mult_by : integer := 1; variable i_clk5_div_by : integer := 1; variable i_clk6_mult_by : integer := 1; variable i_clk6_div_by : integer := 1; variable i_clk7_mult_by : integer := 1; variable i_clk7_div_by : integer := 1; variable i_clk8_mult_by : integer := 1; variable i_clk8_div_by : integer := 1; variable i_clk9_mult_by : integer := 1; variable i_clk9_div_by : integer := 1; variable max_d_value : integer := 1; variable new_multiplier : integer := 1; -- internal variables for storing the phase shift number.(used in lvds mode only) variable i_clk0_phase_shift : integer := 1; variable i_clk1_phase_shift : integer := 1; variable i_clk2_phase_shift : integer := 1; -- user to advanced variables variable max_neg_abs : integer := 0; variable i_m_initial : integer; variable i_m : integer := 1; variable i_n : integer := 1; variable i_c_high : int_array(0 to 9); variable i_c_low : int_array(0 to 9); variable i_c_initial : int_array(0 to 9); variable i_c_ph : int_array(0 to 9); variable i_c_mode : str_array(0 to 9); variable i_m_ph : integer; variable output_count : integer; variable new_divisor : integer; variable clk0_cntr : string(1 to 6) := " c0"; variable clk1_cntr : string(1 to 6) := " c1"; variable clk2_cntr : string(1 to 6) := " c2"; variable clk3_cntr : string(1 to 6) := " c3"; variable clk4_cntr : string(1 to 6) := " c4"; variable clk5_cntr : string(1 to 6) := " c5"; variable clk6_cntr : string(1 to 6) := " c6"; variable clk7_cntr : string(1 to 6) := " c7"; variable clk8_cntr : string(1 to 6) := " c8"; variable clk9_cntr : string(1 to 6) := " c9"; variable fbk_cntr : string(1 to 2); variable fbk_cntr_index : integer; variable start_bit : integer; variable quiet_time : time := 0 ps; variable slowest_clk_old : time := 0 ps; variable slowest_clk_new : time := 0 ps; variable i : integer := 0; variable j : integer := 0; variable scanread_active_edge : time := 0 ps; variable got_first_scanclk : boolean := false; variable scanclk_last_rising_edge : time := 0 ps; variable current_scan_data : std_logic_vector(0 to 233) := (OTHERS => '0'); variable index : integer := 0; variable Tviol_scandata_scanclk : std_ulogic := '0'; variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit; variable Tviol_scanclkena_scanclk : std_ulogic := '0'; variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit; variable scan_chain_length : integer := GPP_SCAN_CHAIN; variable tmp_rem : integer := 0; variable scanclk_cycles : integer := 0; variable lfc_tmp : std_logic_vector(1 downto 0); variable lfr_tmp : std_logic_vector(5 downto 0); variable lfr_int : integer := 0; variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0); variable buf : line; variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0'); variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0'); function slowest_clk ( C0 : integer; C0_mode : string(1 to 6); C1 : integer; C1_mode : string(1 to 6); C2 : integer; C2_mode : string(1 to 6); C3 : integer; C3_mode : string(1 to 6); C4 : integer; C4_mode : string(1 to 6); C5 : integer; C5_mode : string(1 to 6); C6 : integer; C6_mode : string(1 to 6); C7 : integer; C7_mode : string(1 to 6); C8 : integer; C8_mode : string(1 to 6); C9 : integer; C9_mode : string(1 to 6); refclk : time; m_mod : integer) return time is variable max_modulus : integer := 1; variable q_period : time := 0 ps; variable refclk_int : integer := 0; begin if (C0_mode /= "bypass" and C0_mode /= " off") then max_modulus := C0; end if; if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then max_modulus := C1; end if; if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then max_modulus := C2; end if; if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then max_modulus := C3; end if; if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then max_modulus := C4; end if; if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then max_modulus := C5; end if; if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then max_modulus := C6; end if; if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then max_modulus := C7; end if; if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then max_modulus := C8; end if; if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then max_modulus := C9; end if; refclk_int := refclk / 1 ps; if (m_mod /= 0) then q_period := (refclk_int * max_modulus / m_mod) * 1 ps; end if; return (2*q_period); end slowest_clk; function int2bin (arg : integer; size : integer) return std_logic_vector is variable int_val : integer := arg; variable result : std_logic_vector(size-1 downto 0); begin for i in 0 to result'left loop if ((int_val mod 2) = 0) then result(i) := '0'; else result(i) := '1'; end if; int_val := int_val/2; end loop; return result; end int2bin; function extract_cntr_string (arg:string) return string is variable str : string(1 to 6) := " c0"; begin if (arg = "c0") then str := " c0"; elsif (arg = "c1") then str := " c1"; elsif (arg = "c2") then str := " c2"; elsif (arg = "c3") then str := " c3"; elsif (arg = "c4") then str := " c4"; elsif (arg = "c5") then str := " c5"; elsif (arg = "c6") then str := " c6"; elsif (arg = "c7") then str := " c7"; elsif (arg = "c8") then str := " c8"; elsif (arg = "c9") then str := " c9"; else str := " c0"; end if; return str; end extract_cntr_string; function extract_cntr_index (arg:string) return integer is variable index : integer := 0; begin if (arg(6) = '0') then index := 0; elsif (arg(6) = '1') then index := 1; elsif (arg(6) = '2') then index := 2; elsif (arg(6) = '3') then index := 3; elsif (arg(6) = '4') then index := 4; elsif (arg(6) = '5') then index := 5; elsif (arg(6) = '6') then index := 6; elsif (arg(6) = '7') then index := 7; elsif (arg(6) = '8') then index := 8; else index := 9; end if; return index; end extract_cntr_index; function output_cntr_num (arg:string) return string is variable str : string(1 to 6) := "unused"; begin if (arg = "c0") then str := " clk0"; elsif (arg = "c1") then str := " clk1"; elsif (arg = "c2") then str := " clk2"; elsif (arg = "c3") then str := " clk3"; elsif (arg = "c4") then str := " clk4"; elsif (arg = "c5") then str := " clk5"; elsif (arg = "c6") then str := " clk6"; elsif (arg = "c7") then str := " clk7"; elsif (arg = "c8") then str := " clk8"; elsif (arg = "c9") then str := " clk9"; else str := "unused"; end if; return str; end output_cntr_num; begin IF (areset_ipd'EVENT AND areset_ipd = '1') then c_ph_val <= i_c_ph; END IF; if (init) then if (m = 0) then clk9_cntr := " c9"; clk8_cntr := " c8"; clk7_cntr := " c7"; clk6_cntr := " c6"; clk5_cntr := " c5"; clk4_cntr := " c4"; clk3_cntr := " c3"; clk2_cntr := " c2"; clk1_cntr := " c1"; clk0_cntr := " c0"; else clk9_cntr := extract_cntr_string(clk9_counter); clk8_cntr := extract_cntr_string(clk8_counter); clk7_cntr := extract_cntr_string(clk7_counter); clk6_cntr := extract_cntr_string(clk6_counter); clk5_cntr := extract_cntr_string(clk5_counter); clk4_cntr := extract_cntr_string(clk4_counter); clk3_cntr := extract_cntr_string(clk3_counter); clk2_cntr := extract_cntr_string(clk2_counter); clk1_cntr := extract_cntr_string(clk1_counter); clk0_cntr := extract_cntr_string(clk0_counter); end if; clk_num(9) <= output_cntr_num(clk9_counter); clk_num(8) <= output_cntr_num(clk8_counter); clk_num(7) <= output_cntr_num(clk7_counter); clk_num(6) <= output_cntr_num(clk6_counter); clk_num(5) <= output_cntr_num(clk5_counter); clk_num(4) <= output_cntr_num(clk4_counter); clk_num(3) <= output_cntr_num(clk3_counter); clk_num(2) <= output_cntr_num(clk2_counter); clk_num(1) <= output_cntr_num(clk1_counter); clk_num(0) <= output_cntr_num(clk0_counter); i_clk0_counter <= extract_cntr_index(clk0_cntr); i_clk1_counter <= extract_cntr_index(clk1_cntr); i_clk2_counter <= extract_cntr_index(clk2_cntr); i_clk3_counter <= extract_cntr_index(clk3_cntr); i_clk4_counter <= extract_cntr_index(clk4_cntr); i_clk5_counter <= extract_cntr_index(clk5_cntr); i_clk6_counter <= extract_cntr_index(clk6_cntr); i_clk7_counter <= extract_cntr_index(clk7_cntr); i_clk8_counter <= extract_cntr_index(clk8_cntr); i_clk9_counter <= extract_cntr_index(clk9_cntr); if (m = 0) then -- convert user parameters to advanced -- set the limit of the divide_by value that can be returned by -- the following function. max_d_value := 500; -- scale down the multiply_by and divide_by values provided by the design -- before attempting to use them in the calculations below find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by, max_d_value, i_clk0_mult_by, i_clk0_div_by); find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by, max_d_value, i_clk1_mult_by, i_clk1_div_by); find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by, max_d_value, i_clk2_mult_by, i_clk2_div_by); find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by, max_d_value, i_clk3_mult_by, i_clk3_div_by); find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by, max_d_value, i_clk4_mult_by, i_clk4_div_by); find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by, max_d_value, i_clk5_mult_by, i_clk5_div_by); find_simple_integer_fraction(clk6_multiply_by, clk6_divide_by, max_d_value, i_clk6_mult_by, i_clk6_div_by); find_simple_integer_fraction(clk7_multiply_by, clk7_divide_by, max_d_value, i_clk7_mult_by, i_clk7_div_by); find_simple_integer_fraction(clk8_multiply_by, clk8_divide_by, max_d_value, i_clk8_mult_by, i_clk8_div_by); find_simple_integer_fraction(clk9_multiply_by, clk9_divide_by, max_d_value, i_clk9_mult_by, i_clk9_div_by); if (vco_frequency_control = "manual_phase") then find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step, i_clk0_mult_by, i_clk1_mult_by, i_clk2_mult_by, i_clk3_mult_by, i_clk4_mult_by, i_clk5_mult_by,i_clk6_mult_by, i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by, i_clk0_div_by, i_clk1_div_by, i_clk2_div_by, i_clk3_div_by, i_clk4_div_by, i_clk5_div_by,i_clk6_div_by, i_clk7_div_by,i_clk8_div_by,i_clk9_div_by, clk0_counter, clk1_counter, clk2_counter, clk3_counter, clk4_counter, clk5_counter,clk6_counter, clk7_counter,clk8_counter,clk9_counter, i_m, i_n); elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then i_n := vco_divide_by; i_m := vco_multiply_by; else i_n := 1; if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then i_m := i_clk0_mult_by; else i_m := lcm (i_clk0_mult_by, i_clk1_mult_by, i_clk2_mult_by, i_clk3_mult_by, i_clk4_mult_by, i_clk5_mult_by,i_clk6_mult_by, i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by, inclk0_input_frequency); end if; end if; if (pll_type = "flvds") then -- Need to readjust phase shift values when the clock multiply value has been readjusted. new_multiplier := clk0_multiply_by / i_clk0_mult_by; i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier; i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier; i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier; else i_clk0_phase_shift := str2int(clk0_phase_shift); i_clk1_phase_shift := str2int(clk1_phase_shift); i_clk2_phase_shift := str2int(clk2_phase_shift); end if; max_neg_abs := maxnegabs(i_clk0_phase_shift, i_clk1_phase_shift, i_clk2_phase_shift, str2int(clk3_phase_shift), str2int(clk4_phase_shift), str2int(clk5_phase_shift), str2int(clk6_phase_shift), str2int(clk7_phase_shift), str2int(clk8_phase_shift), str2int(clk9_phase_shift) ); i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n); i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); i_c_ph(6) := counter_ph(get_phase_degree(ph_adjust(str2int(clk6_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); i_c_ph(7) := counter_ph(get_phase_degree(ph_adjust(str2int(clk7_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); i_c_ph(8) := counter_ph(get_phase_degree(ph_adjust(str2int(clk8_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); i_c_ph(9) := counter_ph(get_phase_degree(ph_adjust(str2int(clk9_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n), clk5_duty_cycle); i_c_high(6) := counter_high(output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n), clk6_duty_cycle); i_c_high(7) := counter_high(output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n), clk7_duty_cycle); i_c_high(8) := counter_high(output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n), clk8_duty_cycle); i_c_high(9) := counter_high(output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n), clk9_duty_cycle); i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n), clk5_duty_cycle); i_c_low(6) := counter_low(output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n), clk6_duty_cycle); i_c_low(7) := counter_low(output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n), clk7_duty_cycle); i_c_low(8) := counter_low(output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n), clk8_duty_cycle); i_c_low(9) := counter_low(output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n), clk9_duty_cycle); i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n); i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); i_c_initial(6) := counter_initial(get_phase_degree(ph_adjust(str2int(clk6_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); i_c_initial(7) := counter_initial(get_phase_degree(ph_adjust(str2int(clk7_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); i_c_initial(8) := counter_initial(get_phase_degree(ph_adjust(str2int(clk8_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); i_c_initial(9) := counter_initial(get_phase_degree(ph_adjust(str2int(clk9_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n)); i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n)); i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n)); i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n)); i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n)); i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n)); i_c_mode(6) := counter_mode(clk6_duty_cycle, output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n)); i_c_mode(7) := counter_mode(clk7_duty_cycle, output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n)); i_c_mode(8) := counter_mode(clk8_duty_cycle, output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n)); i_c_mode(9) := counter_mode(clk9_duty_cycle, output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n)); else -- m /= 0 i_n := n; i_m := m; i_m_initial := m_initial; i_m_ph := m_ph; i_c_ph(0) := c0_ph; i_c_ph(1) := c1_ph; i_c_ph(2) := c2_ph; i_c_ph(3) := c3_ph; i_c_ph(4) := c4_ph; i_c_ph(5) := c5_ph; i_c_ph(6) := c6_ph; i_c_ph(7) := c7_ph; i_c_ph(8) := c8_ph; i_c_ph(9) := c9_ph; i_c_high(0) := c0_high; i_c_high(1) := c1_high; i_c_high(2) := c2_high; i_c_high(3) := c3_high; i_c_high(4) := c4_high; i_c_high(5) := c5_high; i_c_high(6) := c6_high; i_c_high(7) := c7_high; i_c_high(8) := c8_high; i_c_high(9) := c9_high; i_c_low(0) := c0_low; i_c_low(1) := c1_low; i_c_low(2) := c2_low; i_c_low(3) := c3_low; i_c_low(4) := c4_low; i_c_low(5) := c5_low; i_c_low(6) := c6_low; i_c_low(7) := c7_low; i_c_low(8) := c8_low; i_c_low(9) := c9_low; i_c_initial(0) := c0_initial; i_c_initial(1) := c1_initial; i_c_initial(2) := c2_initial; i_c_initial(3) := c3_initial; i_c_initial(4) := c4_initial; i_c_initial(5) := c5_initial; i_c_initial(6) := c6_initial; i_c_initial(7) := c7_initial; i_c_initial(8) := c8_initial; i_c_initial(9) := c9_initial; i_c_mode(0) := translate_string(c0_mode); i_c_mode(1) := translate_string(c1_mode); i_c_mode(2) := translate_string(c2_mode); i_c_mode(3) := translate_string(c3_mode); i_c_mode(4) := translate_string(c4_mode); i_c_mode(5) := translate_string(c5_mode); i_c_mode(6) := translate_string(c6_mode); i_c_mode(7) := translate_string(c7_mode); i_c_mode(8) := translate_string(c8_mode); i_c_mode(9) := translate_string(c9_mode); end if; -- user to advanced conversion. m_initial_val <= i_m_initial; n_val <= i_n; m_val <= i_m; if (i_m = 1) then m_mode_val <= "bypass"; else m_mode_val <= " "; end if; if (i_n = 1) then n_mode_val <= "bypass"; else n_mode_val <= " "; end if; m_ph_val <= i_m_ph; m_ph_initial <= i_m_ph; m_val_tmp := i_m; for i in 0 to 9 loop if (i_c_mode(i) = "bypass") then if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then i_c_high(i) := 16; i_c_low(i) := 16; else i_c_high(i) := 256; i_c_low(i) := 256; end if; end if; c_ph_val(i) <= i_c_ph(i); c_initial_val(i) <= i_c_initial(i); c_high_val(i) <= i_c_high(i); c_low_val(i) <= i_c_low(i); c_mode_val(i) <= i_c_mode(i); c_high_val_tmp(i) := i_c_high(i); c_hval(i) := i_c_high(i); c_low_val_tmp(i) := i_c_low(i); c_lval(i) := i_c_low(i); c_mode_val_tmp(i) := i_c_mode(i); c_ph_val_orig(i) <= i_c_ph(i); c_high_val_hold(i) <= i_c_high(i); c_low_val_hold(i) <= i_c_low(i); c_mode_val_hold(i) <= i_c_mode(i); end loop; if (pll_type = "fast" OR (pll_type = "left_right")) then scan_chain_length := FAST_SCAN_CHAIN; else scan_chain_length := GPP_SCAN_CHAIN; end if; if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then num_output_cntrs <= 7; else num_output_cntrs <= 10; end if; init := false; elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then c0_rising_edge_transfer_done := false; c1_rising_edge_transfer_done := false; c2_rising_edge_transfer_done := false; c3_rising_edge_transfer_done := false; c4_rising_edge_transfer_done := false; c5_rising_edge_transfer_done := false; c6_rising_edge_transfer_done := false; c7_rising_edge_transfer_done := false; c8_rising_edge_transfer_done := false; c9_rising_edge_transfer_done := false; update_conf_latches_reg <= '0'; elsif (update_conf_latches'event and update_conf_latches = '1') then initiate_reconfig <= '1'; elsif (areset_ipd'event AND areset_ipd = '1') then if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if; elsif (scanclk_ipd'event and scanclk_ipd = '1') then IF (initiate_reconfig = '1') THEN initiate_reconfig <= '0'; ASSERT false REPORT "PLL Reprogramming Initiated" severity note; update_conf_latches_reg <= update_conf_latches; reconfig_err <= false; scandone_tmp <= '0'; cp_curr_old <= cp_curr_val; lfc_old <= lfc_val; lfr_old <= lfr_val; vco_old <= vco_cur; -- LF unused : bit 0,1 -- LF Capacitance : bits 2,3 : all values are legal buf_scan_data := scan_data(2 TO 3); IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data)); ELSE lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data)); END IF; -- LF Resistance : bits 4-8 -- valid values - 00000,00100,10000,10100,11000,11011,11100,11110 IF (scan_data(4 TO 8) = "00000") THEN lfr_val <= "20"; ELSIF (scan_data(4 TO 8) = "00100") THEN lfr_val <= "16"; ELSIF (scan_data(4 TO 8) = "10000") THEN lfr_val <= "12"; ELSIF (scan_data(4 TO 8) = "10100") THEN lfr_val <= "08"; ELSIF (scan_data(4 TO 8) = "11000") THEN lfr_val <= "06"; ELSIF (scan_data(4 TO 8) = "11011") THEN lfr_val <= "04"; ELSIF (scan_data(4 TO 8) = "11100") THEN lfr_val <= "02"; ELSE lfr_val <= "01"; END IF; -- VCO post scale assignment if (scan_data(9) = '1') then -- vco_post_scale = 1 i_vco_max <= VCO_MAX_NO_DIVISION/2; i_vco_min <= VCO_MIN_NO_DIVISION/2; vco_cur <= 1; else i_vco_max <= vco_max; i_vco_min <= vco_min; vco_cur <= 2; end if; -- CP -- Bit 9 : CRBYPASS -- Bit 10-14 : unused -- Bits 15-17 : all values are legal buf_scan_data_2 := scan_data(15 TO 17); cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2)); -- save old values for display info. cp_curr_val_bit_setting <= scan_data(15 TO 17); lfc_val_bit_setting <= scan_data(2 TO 3); lfr_val_bit_setting <= scan_data(4 TO 8); m_val_old <= m_val; n_val_old <= n_val; m_mode_val_old <= m_mode_val; n_mode_val_old <= n_mode_val; WHILE (i < num_output_cntrs) LOOP c_high_val_old(i) <= c_high_val(i); c_low_val_old(i) <= c_low_val(i); c_mode_val_old(i) <= c_mode_val(i); i := i + 1; END LOOP; -- M counter -- 1. Mode - bypass (bit 18) IF (scan_data(18) = '1') THEN m_mode_val <= "bypass"; -- 3. Mode - odd/even (bit 27) ELSIF (scan_data(27) = '1') THEN m_mode_val <= " odd"; ELSE m_mode_val <= " even"; END IF; -- 2. High (bit 19-26) m_hi := scan_data(19 TO 26); -- 4. Low (bit 28-35) m_lo := scan_data(28 TO 35); -- N counter -- 1. Mode - bypass (bit 36) IF (scan_data(36) = '1') THEN n_mode_val <= "bypass"; -- 3. Mode - odd/even (bit 45) ELSIF (scan_data(45) = '1') THEN n_mode_val <= " odd"; ELSE n_mode_val <= " even"; END IF; -- 2. High (bit 37-44) n_hi := scan_data(37 TO 44); -- 4. Low (bit 46-53) n_lo := scan_data(46 TO 53); -- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low i := 0; WHILE (i < num_output_cntrs) LOOP -- 1. Mode - bypass IF (scan_data(54 + i * 18 + 0) = '1') THEN c_mode_val_tmp(i) := "bypass"; -- 3. Mode - odd/even ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN c_mode_val_tmp(i) := " odd"; ELSE c_mode_val_tmp(i) := " even"; END IF; -- 2. Hi high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8); c_hval(i) := alt_conv_integer(high); IF (c_hval(i) /= 0) THEN c_high_val_tmp(i) := c_hval(i); ELSE c_high_val_tmp(i) := alt_conv_integer("000000001"); END IF; -- 4. Low low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17); c_lval(i) := alt_conv_integer(low); IF (c_lval(i) /= 0) THEN c_low_val_tmp(i) := c_lval(i); ELSE c_low_val_tmp(i) := alt_conv_integer("000000001"); END IF; i := i + 1; END LOOP; -- Legality Checks -- M counter value IF(scan_data(18) /= '1') THEN IF ((m_hi /= m_lo) and (scan_data(27) /= '1')) THEN reconfig_err <= TRUE; WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work")); writeline(output, buf); ELSIF (m_hi /= "00000000") THEN m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo); ELSE m_val_tmp := alt_conv_integer("000000001"); END IF; ELSE m_val_tmp := alt_conv_integer("10000000"); END IF; -- N counter value IF(scan_data(36) /= '1') THEN IF ((n_hi /= n_lo)and (scan_data(45) /= '1')) THEN reconfig_err <= TRUE; WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work")); writeline(output, buf); ELSIF (n_hi /= "00000000") THEN n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo); ELSE n_val <= alt_conv_integer("000000001"); END IF; ELSE n_val <= alt_conv_integer("10000000"); END IF; -- TODO : Give warnings/errors in the following cases? -- 1. Illegal counter values (error) -- 2. Change of mode (warning) -- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0) END IF; end if; if (fbclk'event and fbclk = '1') then m_val <= m_val_tmp; end if; if (update_conf_latches_reg = '1') then if (scanclk_ipd'event and scanclk_ipd = '1') then c0_rising_edge_transfer_done := true; c_high_val(0) <= c_high_val_tmp(0); c_mode_val(0) <= c_mode_val_tmp(0); end if; if (scanclk_ipd'event and scanclk_ipd = '1') then c1_rising_edge_transfer_done := true; c_high_val(1) <= c_high_val_tmp(1); c_mode_val(1) <= c_mode_val_tmp(1); end if; if (scanclk_ipd'event and scanclk_ipd = '1') then c2_rising_edge_transfer_done := true; c_high_val(2) <= c_high_val_tmp(2); c_mode_val(2) <= c_mode_val_tmp(2); end if; if (scanclk_ipd'event and scanclk_ipd = '1') then c_high_val(3) <= c_high_val_tmp(3); c_mode_val(3) <= c_mode_val_tmp(3); c3_rising_edge_transfer_done := true; end if; if (scanclk_ipd'event and scanclk_ipd = '1') then c_high_val(4) <= c_high_val_tmp(4); c_mode_val(4) <= c_mode_val_tmp(4); c4_rising_edge_transfer_done := true; end if; if (scanclk_ipd'event and scanclk_ipd = '1') then c_high_val(5) <= c_high_val_tmp(5); c_mode_val(5) <= c_mode_val_tmp(5); c5_rising_edge_transfer_done := true; end if; if (scanclk_ipd'event and scanclk_ipd = '1') then c_high_val(6) <= c_high_val_tmp(6); c_mode_val(6) <= c_mode_val_tmp(6); c6_rising_edge_transfer_done := true; end if; if (scanclk_ipd'event and scanclk_ipd = '1') then c_high_val(7) <= c_high_val_tmp(7); c_mode_val(7) <= c_mode_val_tmp(7); c7_rising_edge_transfer_done := true; end if; if (scanclk_ipd'event and scanclk_ipd = '1') then c_high_val(8) <= c_high_val_tmp(8); c_mode_val(8) <= c_mode_val_tmp(8); c8_rising_edge_transfer_done := true; end if; if (scanclk_ipd'event and scanclk_ipd = '1') then c_high_val(9) <= c_high_val_tmp(9); c_mode_val(9) <= c_mode_val_tmp(9); c9_rising_edge_transfer_done := true; end if; end if; if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then c_low_val(0) <= c_low_val_tmp(0); end if; if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then c_low_val(1) <= c_low_val_tmp(1); end if; if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then c_low_val(2) <= c_low_val_tmp(2); end if; if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then c_low_val(3) <= c_low_val_tmp(3); end if; if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then c_low_val(4) <= c_low_val_tmp(4); end if; if (scanclk_ipd'event and scanclk_ipd = '0' and c5_rising_edge_transfer_done) then c_low_val(5) <= c_low_val_tmp(5); end if; if (scanclk_ipd'event and scanclk_ipd = '0' and c6_rising_edge_transfer_done) then c_low_val(6) <= c_low_val_tmp(6); end if; if (scanclk_ipd'event and scanclk_ipd = '0' and c7_rising_edge_transfer_done) then c_low_val(7) <= c_low_val_tmp(7); end if; if (scanclk_ipd'event and scanclk_ipd = '0' and c8_rising_edge_transfer_done) then c_low_val(8) <= c_low_val_tmp(8); end if; if (scanclk_ipd'event and scanclk_ipd = '0' and c9_rising_edge_transfer_done) then c_low_val(9) <= c_low_val_tmp(9); end if; if (update_phase = '1') then if (vco_out(0)'event and vco_out(0) = '0') then for i in 0 to 9 loop if (c_ph_val(i) = 0) then c_ph_val(i) <= c_ph_val_tmp(i); end if; end loop; if (m_ph_val = 0) then m_ph_val <= m_ph_val_tmp; end if; end if; if (vco_out(1)'event and vco_out(1) = '0') then for i in 0 to 9 loop if (c_ph_val(i) = 1) then c_ph_val(i) <= c_ph_val_tmp(i); end if; end loop; if (m_ph_val = 1) then m_ph_val <= m_ph_val_tmp; end if; end if; if (vco_out(2)'event and vco_out(2) = '0') then for i in 0 to 9 loop if (c_ph_val(i) = 2) then c_ph_val(i) <= c_ph_val_tmp(i); end if; end loop; if (m_ph_val = 2) then m_ph_val <= m_ph_val_tmp; end if; end if; if (vco_out(3)'event and vco_out(3) = '0') then for i in 0 to 9 loop if (c_ph_val(i) = 3) then c_ph_val(i) <= c_ph_val_tmp(i); end if; end loop; if (m_ph_val = 3) then m_ph_val <= m_ph_val_tmp; end if; end if; if (vco_out(4)'event and vco_out(4) = '0') then for i in 0 to 9 loop if (c_ph_val(i) = 4) then c_ph_val(i) <= c_ph_val_tmp(i); end if; end loop; if (m_ph_val = 4) then m_ph_val <= m_ph_val_tmp; end if; end if; if (vco_out(5)'event and vco_out(5) = '0') then for i in 0 to 9 loop if (c_ph_val(i) = 5) then c_ph_val(i) <= c_ph_val_tmp(i); end if; end loop; if (m_ph_val = 5) then m_ph_val <= m_ph_val_tmp; end if; end if; if (vco_out(6)'event and vco_out(6) = '0') then for i in 0 to 9 loop if (c_ph_val(i) = 6) then c_ph_val(i) <= c_ph_val_tmp(i); end if; end loop; if (m_ph_val = 6) then m_ph_val <= m_ph_val_tmp; end if; end if; if (vco_out(7)'event and vco_out(7) = '0') then for i in 0 to 9 loop if (c_ph_val(i) = 7) then c_ph_val(i) <= c_ph_val_tmp(i); end if; end loop; if (m_ph_val = 7) then m_ph_val <= m_ph_val_tmp; end if; end if; end if; if (vco_out(0)'event) then for i in 0 to 9 loop if (c_ph_val(i) = 0) then inclk_c_from_vco(i) <= vco_out(0); end if; end loop; if (m_ph_val = 0) then inclk_m_from_vco <= vco_out(0); end if; end if; if (vco_out(1)'event) then for i in 0 to 9 loop if (c_ph_val(i) = 1) then inclk_c_from_vco(i) <= vco_out(1); end if; end loop; if (m_ph_val = 1) then inclk_m_from_vco <= vco_out(1); end if; end if; if (vco_out(2)'event) then for i in 0 to 9 loop if (c_ph_val(i) = 2) then inclk_c_from_vco(i) <= vco_out(2); end if; end loop; if (m_ph_val = 2) then inclk_m_from_vco <= vco_out(2); end if; end if; if (vco_out(3)'event) then for i in 0 to 9 loop if (c_ph_val(i) = 3) then inclk_c_from_vco(i) <= vco_out(3); end if; end loop; if (m_ph_val = 3) then inclk_m_from_vco <= vco_out(3); end if; end if; if (vco_out(4)'event) then for i in 0 to 9 loop if (c_ph_val(i) = 4) then inclk_c_from_vco(i) <= vco_out(4); end if; end loop; if (m_ph_val = 4) then inclk_m_from_vco <= vco_out(4); end if; end if; if (vco_out(5)'event) then for i in 0 to 9 loop if (c_ph_val(i) = 5) then inclk_c_from_vco(i) <= vco_out(5); end if; end loop; if (m_ph_val = 5) then inclk_m_from_vco <= vco_out(5); end if; end if; if (vco_out(6)'event) then for i in 0 to 9 loop if (c_ph_val(i) = 6) then inclk_c_from_vco(i) <= vco_out(6); end if; end loop; if (m_ph_val = 6) then inclk_m_from_vco <= vco_out(6); end if; end if; if (vco_out(7)'event) then for i in 0 to 9 loop if (c_ph_val(i) = 7) then inclk_c_from_vco(i) <= vco_out(7); end if; end loop; if (m_ph_val = 7) then inclk_m_from_vco <= vco_out(7); end if; end if; ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_scandata_scanclk, TimingData => TimingData_scandata_scanclk, TestSignal => scandata_ipd, TestSignalName => "scandata", RefSignal => scanclk_ipd, RefSignalName => "scanclk", SetupHigh => tsetup_scandata_scanclk_noedge_negedge, SetupLow => tsetup_scandata_scanclk_noedge_negedge, HoldHigh => thold_scandata_scanclk_noedge_negedge, HoldLow => thold_scandata_scanclk_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & "/hardcopyiii_pll", XOn => XOnChecks, MsgOn => MsgOnChecks ); VitalSetupHoldCheck ( Violation => Tviol_scanclkena_scanclk, TimingData => TimingData_scanclkena_scanclk, TestSignal => scanclkena_ipd, TestSignalName => "scanclkena", RefSignal => scanclk_ipd, RefSignalName => "scanclk", SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge, SetupLow => tsetup_scanclkena_scanclk_noedge_negedge, HoldHigh => thold_scanclkena_scanclk_noedge_negedge, HoldLow => thold_scanclkena_scanclk_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & "/hardcopyiii_pll", XOn => XOnChecks, MsgOn => MsgOnChecks ); end if; if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then scanclkena_reg <= scanclkena_ipd; if (scanclkena_reg = '1') then scandata_in <= scandata_ipd; scandata_out <= scandataout_tmp; end if; end if; if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then if (got_first_scanclk) then scanclk_period <= now - scanclk_last_rising_edge; else got_first_scanclk := true; end if; if (scanclkena_reg = '1') then for j in scan_chain_length - 1 downto 1 loop scan_data(j) <= scan_data(j-1); end loop; scan_data(0) <= scandata_in; end if; scanclk_last_rising_edge := now; end if; end process; -- PLL Phase Reconfiguration PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd) VARIABLE i : INTEGER := 0; VARIABLE c_ph : INTEGER := 0; VARIABLE m_ph : INTEGER := 0; VARIABLE select_counter : INTEGER := 0; BEGIN IF (NOW = 0 ps) THEN m_ph_val_tmp <= m_ph_initial; END IF; -- Latch phase enable (same as phasestep) on neg edge of scan clock IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN phasestep_reg <= phasestep_ipd; END IF; IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN IF (update_phase = '0') THEN phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart -- if not, next phasestep cycle is skipped END IF; END IF; -- revert counter phase tap values to POF programmed values -- if PLL is reset IF (areset_ipd'EVENT AND areset_ipd = '1') then c_ph_val_tmp <= c_ph_val_orig; m_ph_val_tmp <= m_ph_initial; END IF; IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN IF (phasestep_reg = '1') THEN IF (phasestep_high_count = 1) THEN phasecounterselect_reg <= phasecounterselect_ipd; phaseupdown_reg <= phaseupdown_ipd; -- start reconfiguration IF (phasecounterselect_ipd < "1100") THEN -- no counters selected IF (phasecounterselect_ipd = "0000") THEN i := 0; WHILE (i < num_output_cntrs) LOOP c_ph := c_ph_val(i); IF (phaseupdown_ipd = '1') THEN c_ph := (c_ph + 1) mod num_phase_taps; ELSIF (c_ph = 0) THEN c_ph := num_phase_taps - 1; ELSE c_ph := (c_ph - 1) mod num_phase_taps; END IF; c_ph_val_tmp(i) <= c_ph; i := i + 1; END LOOP; ELSIF (phasecounterselect_ipd = "0001") THEN m_ph := m_ph_val; IF (phaseupdown_ipd = '1') THEN m_ph := (m_ph + 1) mod num_phase_taps; ELSIF (m_ph = 0) THEN m_ph := num_phase_taps - 1; ELSE m_ph := (m_ph - 1) mod num_phase_taps; END IF; m_ph_val_tmp <= m_ph; ELSE select_counter := alt_conv_integer(phasecounterselect_ipd) - 2; c_ph := c_ph_val(select_counter); IF (phaseupdown_ipd = '1') THEN c_ph := (c_ph + 1) mod num_phase_taps; ELSIF (c_ph = 0) THEN c_ph := num_phase_taps - 1; ELSE c_ph := (c_ph - 1) mod num_phase_taps; END IF; c_ph_val_tmp(select_counter) <= c_ph; END IF; update_phase <= '1','0' AFTER (0.5 * scanclk_period); END IF; END IF; phasestep_high_count <= phasestep_high_count + 1; END IF; END IF; END PROCESS; scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-2) when (pll_type = "fast" or pll_type = "lvds" or pll_type = "left_right") else scan_data(GPP_SCAN_CHAIN-2); process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk) variable sched_time : time := 0 ps; TYPE time_array is ARRAY (0 to 7) of time; variable init : boolean := true; variable refclk_period : time; variable m_times_vco_period : time; variable new_m_times_vco_period : time; variable phase_shift : time_array := (OTHERS => 0 ps); variable last_phase_shift : time_array := (OTHERS => 0 ps); variable l_index : integer := 1; variable cycle_to_adjust : integer := 0; variable stop_vco : boolean := false; variable locked_tmp : std_logic := '0'; variable pll_is_locked : boolean := false; variable cycles_pfd_low : integer := 0; variable cycles_pfd_high : integer := 0; variable cycles_to_lock : integer := 0; variable cycles_to_unlock : integer := 0; variable got_first_refclk : boolean := false; variable got_second_refclk : boolean := false; variable got_first_fbclk : boolean := false; variable refclk_time : time := 0 ps; variable fbclk_time : time := 0 ps; variable first_fbclk_time : time := 0 ps; variable fbclk_period : time := 0 ps; variable first_schedule : boolean := true; variable vco_val : std_logic := '0'; variable vco_period_was_phase_adjusted : boolean := false; variable phase_adjust_was_scheduled : boolean := false; variable loop_xplier : integer; variable loop_initial : integer := 0; variable loop_ph : integer := 0; variable loop_time_delay : integer := 0; variable initial_delay : time := 0 ps; variable vco_per : time; variable tmp_rem : integer; variable my_rem : integer; variable fbk_phase : integer := 0; variable pull_back_M : integer := 0; variable total_pull_back : integer := 0; variable fbk_delay : integer := 0; variable offset : time := 0 ps; variable tmp_vco_per : integer := 0; variable high_time : time; variable low_time : time; variable got_refclk_posedge : boolean := false; variable got_fbclk_posedge : boolean := false; variable inclk_out_of_range : boolean := false; variable no_warn : boolean := false; variable ext_fbk_cntr_modulus : integer := 1; variable init_clks : boolean := true; variable pll_is_in_reset : boolean := false; variable buf : line; begin if (init) then -- jump-start the VCO -- add 1 ps delay to ensure all signals are updated to initial -- values schedule_vco <= transport not schedule_vco after 1 ps; init := false; end if; if (schedule_vco'event) then if (init_clks) then refclk_period := inclk0_input_frequency * n_val * 1 ps; m_times_vco_period := refclk_period; new_m_times_vco_period := refclk_period; init_clks := false; end if; sched_time := 0 ps; for i in 0 to 7 loop last_phase_shift(i) := phase_shift(i); end loop; cycle_to_adjust := 0; l_index := 1; m_times_vco_period := new_m_times_vco_period; end if; -- areset was asserted if (areset_ipd'event and areset_ipd = '1') then assert false report family_name & " PLL was reset" severity note; -- reset lock parameters pll_is_locked := false; cycles_to_lock := 0; cycles_to_unlock := 0; end if; if (areset_ipd = '1') then pll_is_in_reset := true; got_first_refclk := false; got_second_refclk := false; -- drop VCO taps to 0 for i in 0 to 7 loop vco_out(i) <= transport '0' after 1 ps; end loop; end if; if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then -- drop VCO taps to 0 for i in 0 to 7 loop vco_out(i) <= transport '0' after last_phase_shift(i); phase_shift(i) := 0 ps; last_phase_shift(i) := 0 ps; end loop; -- reset lock parameters pll_is_locked := false; cycles_to_lock := 0; cycles_to_unlock := 0; got_first_refclk := false; got_second_refclk := false; refclk_time := 0 ps; got_first_fbclk := false; fbclk_time := 0 ps; first_fbclk_time := 0 ps; fbclk_period := 0 ps; first_schedule := true; vco_val := '0'; vco_period_was_phase_adjusted := false; phase_adjust_was_scheduled := false; elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then -- note areset deassert time -- note it as refclk_time to prevent false triggering -- of stop_vco after areset if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then refclk_time := now; locked_tmp := '0'; end if; pll_is_in_reset := false; -- calculate loop_xplier : this will be different from m_val -- in external_feedback_mode loop_xplier := m_val; loop_initial := m_initial_val - 1; loop_ph := m_ph_val; -- convert initial value to delay initial_delay := (loop_initial * m_times_vco_period)/loop_xplier; -- convert loop ph_tap to delay my_rem := (m_times_vco_period/1 ps) rem loop_xplier; tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier; if (my_rem /= 0) then tmp_vco_per := tmp_vco_per + 1; end if; fbk_phase := (loop_ph * tmp_vco_per)/8; pull_back_M := initial_delay/1 ps + fbk_phase; total_pull_back := pull_back_M; if (simulation_type = "timing") then total_pull_back := total_pull_back + pll_compensation_delay; end if; while (total_pull_back > refclk_period/1 ps) loop total_pull_back := total_pull_back - refclk_period/1 ps; end loop; if (total_pull_back > 0) then offset := refclk_period - (total_pull_back * 1 ps); end if; fbk_delay := total_pull_back - fbk_phase; if (fbk_delay < 0) then offset := offset - (fbk_phase * 1 ps); fbk_delay := total_pull_back; end if; -- assign m_delay m_delay <= transport fbk_delay after 1 ps; my_rem := (m_times_vco_period/1 ps) rem loop_xplier; for i in 1 to loop_xplier loop -- adjust cycles tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier; if (my_rem /= 0 and l_index <= my_rem) then tmp_rem := (loop_xplier * l_index) rem my_rem; cycle_to_adjust := (loop_xplier * l_index) / my_rem; if (tmp_rem /= 0) then cycle_to_adjust := cycle_to_adjust + 1; end if; end if; if (cycle_to_adjust = i) then tmp_vco_per := tmp_vco_per + 1; l_index := l_index + 1; end if; -- calculate high and low periods vco_per := tmp_vco_per * 1 ps; high_time := (tmp_vco_per/2) * 1 ps; if (tmp_vco_per rem 2 /= 0) then high_time := high_time + 1 ps; end if; low_time := vco_per - high_time; -- schedule the rising and falling edges for j in 1 to 2 loop vco_val := not vco_val; if (vco_val = '0') then sched_time := sched_time + high_time; elsif (vco_val = '1') then sched_time := sched_time + low_time; end if; -- schedule the phase taps for k in 0 to 7 loop phase_shift(k) := (k * vco_per)/8; if (first_schedule) then vco_out(k) <= transport vco_val after (sched_time + phase_shift(k)); else vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k)); end if; end loop; end loop; end loop; -- schedule once more if (first_schedule) then vco_val := not vco_val; if (vco_val = '0') then sched_time := sched_time + high_time; elsif (vco_val = '1') then sched_time := sched_time + low_time; end if; -- schedule the phase taps for k in 0 to 7 loop phase_shift(k) := (k * vco_per)/8; vco_out(k) <= transport vco_val after (sched_time + phase_shift(k)); end loop; first_schedule := false; end if; schedule_vco <= transport not schedule_vco after sched_time; if (vco_period_was_phase_adjusted) then m_times_vco_period := refclk_period; new_m_times_vco_period := refclk_period; vco_period_was_phase_adjusted := false; phase_adjust_was_scheduled := true; vco_per := m_times_vco_period/loop_xplier; for k in 0 to 7 loop phase_shift(k) := (k * vco_per)/8; end loop; end if; end if; -- Bypass lock detect if (refclk'event and refclk = '1' and areset_ipd = '0') then if (test_bypass_lock_detect = "on") then if (pfdena_ipd = '1') then cycles_pfd_low := 0; if (pfd_locked = '0') then if (cycles_pfd_high = lock_high) then assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning; pfd_locked <= '1'; end if; cycles_pfd_high := cycles_pfd_high + 1; end if; end if; if (pfdena_ipd = '0') then cycles_pfd_high := 0; if (pfd_locked = '1') then if (cycles_pfd_low = lock_low) then assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning; pfd_locked <= '0'; end if; cycles_pfd_low := cycles_pfd_low + 1; end if; end if; end if; if (refclk'event and refclk = '1' and areset_ipd = '0') then got_refclk_posedge := true; if (not got_first_refclk) then got_first_refclk := true; else got_second_refclk := true; refclk_period := now - refclk_time; -- check if incoming freq. will cause VCO range to be -- exceeded if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and (((refclk_period/1 ps)/loop_xplier > i_vco_max) or ((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then if (pll_is_locked) then if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning; vco_over <= '1'; end if; if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning; vco_under <= '1'; end if; if (inclk_out_of_range) then pll_is_locked := false; locked_tmp := '0'; cycles_to_lock := 0; vco_period_was_phase_adjusted := false; phase_adjust_was_scheduled := false; assert false report family_name & " PLL lost lock." severity note; end if; elsif (not no_warn) then if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning; vco_over <= '1'; end if; if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning; vco_under <= '1'; end if; assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning; no_warn := true; end if; inclk_out_of_range := true; else vco_over <= '0'; vco_under <= '0'; inclk_out_of_range := false; no_warn := false; end if; end if; end if; if (stop_vco) then stop_vco := false; schedule_vco <= not schedule_vco; end if; refclk_time := now; else got_refclk_posedge := false; end if; -- Update M counter value on feedback clock edge if (fbclk'event and fbclk = '1') then got_fbclk_posedge := true; if (not got_first_fbclk) then got_first_fbclk := true; else fbclk_period := now - fbclk_time; end if; -- need refclk_period here, so initialized to proper value above if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or ( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then stop_vco := true; -- reset got_first_refclk := false; got_first_fbclk := false; got_second_refclk := false; if (pll_is_locked) then pll_is_locked := false; locked_tmp := '0'; assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note; if ((i_vco_max = 0) and (i_vco_min = 0)) then assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note; end if; end if; cycles_to_lock := 0; cycles_to_unlock := 0; first_schedule := true; vco_period_was_phase_adjusted := false; phase_adjust_was_scheduled := false; end if; fbclk_time := now; else got_fbclk_posedge := false; end if; if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then -- now we know actual incoming period if ( abs(fbclk_time - refclk_time) <= 5 ps or (got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then -- considered in phase if (cycles_to_lock = real_lock_high) then if (not pll_is_locked) then assert false report family_name & " PLL locked to incoming clock" severity note; end if; pll_is_locked := true; locked_tmp := '1'; cycles_to_unlock := 0; end if; -- increment lock counter only if second part of above -- time check is NOT true if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then cycles_to_lock := cycles_to_lock + 1; end if; -- adjust m_times_vco_period new_m_times_vco_period := refclk_period; else -- if locked, begin unlock if (pll_is_locked) then cycles_to_unlock := cycles_to_unlock + 1; if (cycles_to_unlock = lock_low) then pll_is_locked := false; locked_tmp := '0'; cycles_to_lock := 0; vco_period_was_phase_adjusted := false; phase_adjust_was_scheduled := false; assert false report family_name & " PLL lost lock." severity note; got_first_refclk := false; got_first_fbclk := false; got_second_refclk := false; end if; end if; if ( abs(refclk_period - fbclk_period) <= 2 ps ) then -- frequency is still good if (now = fbclk_time and (not phase_adjust_was_scheduled)) then if ( abs(fbclk_time - refclk_time) > refclk_period/2) then new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)); vco_period_was_phase_adjusted := true; else new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time); vco_period_was_phase_adjusted := true; end if; end if; else phase_adjust_was_scheduled := false; new_m_times_vco_period := refclk_period; end if; end if; end if; if (pfdena_ipd = '0') then if (pll_is_locked) then locked_tmp := 'X'; end if; pll_is_locked := false; cycles_to_lock := 0; end if; -- give message only at time of deassertion if (pfdena_ipd'event and pfdena_ipd = '0') then assert false report "PFDENA deasserted." severity note; elsif (pfdena_ipd'event and pfdena_ipd = '1') then got_first_refclk := false; got_second_refclk := false; refclk_time := now; end if; if (reconfig_err) then lock <= '0'; else lock <= locked_tmp; end if; -- signal to calculate quiet_time sig_refclk_period <= refclk_period; if (stop_vco = true) then sig_stop_vco <= '1'; else sig_stop_vco <= '0'; end if; pll_locked <= pll_is_locked; end process; clk0_tmp <= c_clk(i_clk0_counter); clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X'; clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; clk1_tmp <= c_clk(i_clk1_counter); clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X'; clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; clk2_tmp <= c_clk(i_clk2_counter); clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X'; clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; clk3_tmp <= c_clk(i_clk3_counter); clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X'; clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; clk4_tmp <= c_clk(i_clk4_counter); clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X'; clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; clk5_tmp <= c_clk(i_clk5_counter); clk_pfd(5) <= clk5_tmp WHEN (pfd_locked = '1') ELSE 'X'; clk(5) <= clk_pfd(5) WHEN (test_bypass_lock_detect = "on") ELSE clk5_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; clk6_tmp <= c_clk(i_clk6_counter); clk_pfd(6) <= clk6_tmp WHEN (pfd_locked = '1') ELSE 'X'; clk(6) <= clk_pfd(6) WHEN (test_bypass_lock_detect = "on") ELSE clk6_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; clk7_tmp <= c_clk(i_clk7_counter); clk_pfd(7) <= clk7_tmp WHEN (pfd_locked = '1') ELSE 'X'; clk(7) <= clk_pfd(7) WHEN (test_bypass_lock_detect = "on") ELSE clk7_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; clk8_tmp <= c_clk(i_clk8_counter); clk_pfd(8) <= clk8_tmp WHEN (pfd_locked = '1') ELSE 'X'; clk(8) <= clk_pfd(8) WHEN (test_bypass_lock_detect = "on") ELSE clk8_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; clk9_tmp <= c_clk(i_clk9_counter); clk_pfd(9) <= clk9_tmp WHEN (pfd_locked = '1') ELSE 'X'; clk(9) <= clk_pfd(9) WHEN (test_bypass_lock_detect = "on") ELSE clk9_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; scandataout <= scandata_out; scandone <= NOT scandone_tmp; phasedone <= NOT update_phase; vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over; vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under; fbout <= fbclk; end vital_pll; -- END ARCHITECTURE VITAL_PLL ------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_asmiblock -- -- Description : HARDCOPYIII ASMIBLOCK VHDL Simulation model -- ------------------------------------------------------------------- LIBRARY IEEE; use IEEE.std_logic_1164.all; use work.hardcopyiii_atom_pack.all; entity hardcopyiii_asmiblock is generic ( lpm_type : string := "hardcopyiii_asmiblock" ); port ( dclkin : in std_logic := '0'; scein : in std_logic := '0'; sdoin : in std_logic := '0'; data0in : in std_logic := '0'; oe : in std_logic := '0'; dclkout : out std_logic; sceout : out std_logic; sdoout : out std_logic; data0out: out std_logic ); end hardcopyiii_asmiblock; architecture architecture_asmiblock of hardcopyiii_asmiblock is begin end architecture_asmiblock; -- end of hardcopyiii_asmiblock --///////////////////////////////////////////////////////////////////////////// -- -- Module Name : hardcopyiii_lvds_reg -- -- Description : Simulation model for a simple DFF. -- This is used for registering the enable inputs. -- No timing, powers upto 0. -- --///////////////////////////////////////////////////////////////////////////// LIBRARY IEEE, std; USE ieee.std_logic_1164.all; --USE ieee.std_logic_unsigned.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_lvds_reg is GENERIC ( MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; TimingChecksOn : Boolean := True; InstancePath : String := "*"; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_ena : VitalDelayType01 := DefpropDelay01; tipd_d : VitalDelayType01 := DefpropDelay01; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01; tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01 ); PORT ( q : OUT std_logic; clk : IN std_logic; ena : IN std_logic := '1'; d : IN std_logic; clrn : IN std_logic := '1'; prn : IN std_logic := '1' ); END hardcopyiii_lvds_reg; ARCHITECTURE vital_hardcopyiii_lvds_reg of hardcopyiii_lvds_reg is -- INTERNAL SIGNALS signal clk_ipd : std_logic; signal d_ipd : std_logic; signal ena_ipd : std_logic; begin ---------------------- -- INPUT PATH DELAYs ---------------------- WireDelay : block begin VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (ena_ipd, ena, tipd_ena); VitalWireDelay (d_ipd, d, tipd_d); end block; process (clk_ipd, d_ipd, clrn, prn) variable q_tmp : std_logic := '0'; variable q_VitalGlitchData : VitalGlitchDataType; variable Tviol_d_clk : std_ulogic := '0'; variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit; begin ------------------------ -- Timing Check Section ------------------------ if (prn = '0') then q_tmp := '1'; elsif (clrn = '0') then q_tmp := '0'; elsif (clk_ipd'event and clk_ipd = '1') then if (ena_ipd = '1') then q_tmp := d_ipd; end if; end if; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => q, OutSignalName => "Q", OutTemp => q_tmp, Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)), GlitchData => q_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; end vital_hardcopyiii_lvds_reg; --///////////////////////////////////////////////////////////////////////////// -- -- Module Name : hardcopyiii_lvds_rx_fifo_sync_ram -- -- Description : -- --///////////////////////////////////////////////////////////////////////////// LIBRARY IEEE, std; USE ieee.std_logic_1164.all; --USE ieee.std_logic_unsigned.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_lvds_rx_fifo_sync_ram is PORT ( clk : IN std_logic; datain : IN std_logic := '0'; writereset : IN std_logic := '0'; waddr : IN std_logic_vector(2 DOWNTO 0) := "000"; raddr : IN std_logic_vector(2 DOWNTO 0) := "000"; we : IN std_logic := '0'; dataout : OUT std_logic ); END hardcopyiii_lvds_rx_fifo_sync_ram; ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF hardcopyiii_lvds_rx_fifo_sync_ram IS -- INTERNAL SIGNALS signal dataout_tmp : std_logic; signal ram_d : std_logic_vector(0 TO 5); signal ram_q : std_logic_vector(0 TO 5); signal data_reg : std_logic_vector(0 TO 5); begin dataout <= dataout_tmp; process (clk, writereset) variable initial : boolean := true; begin if (initial) then for i in 0 to 5 loop ram_q(i) <= '0'; end loop; initial := false; end if; if (writereset = '1') then for i in 0 to 5 loop ram_q(i) <= '0'; end loop; elsif (clk'event and clk = '1') then for i in 0 to 5 loop ram_q(i) <= ram_d(i); end loop; end if; end process; process (we, data_reg, ram_q) begin if (we = '1') then ram_d <= data_reg; else ram_d <= ram_q; end if; end process; data_reg(0) <= datain when (waddr = "000") else ram_q(0) ; data_reg(1) <= datain when (waddr = "001") else ram_q(1) ; data_reg(2) <= datain when (waddr = "010") else ram_q(2) ; data_reg(3) <= datain when (waddr = "011") else ram_q(3) ; data_reg(4) <= datain when (waddr = "100") else ram_q(4) ; data_reg(5) <= datain when (waddr = "101") else ram_q(5) ; process (ram_q, we, waddr, raddr) variable initial : boolean := true; begin if (initial) then dataout_tmp <= '0'; initial := false; end if; case raddr is when "000" => dataout_tmp <= ram_q(0); when "001" => dataout_tmp <= ram_q(1); when "010" => dataout_tmp <= ram_q(2); when "011" => dataout_tmp <= ram_q(3); when "100" => dataout_tmp <= ram_q(4); when "101" => dataout_tmp <= ram_q(5); when others => dataout_tmp <= '0'; end case; end process; END vital_arm_lvds_rx_fifo_sync_ram; --///////////////////////////////////////////////////////////////////////////// -- -- Module Name : hardcopyiii_lvds_rx_fifo -- -- Description : -- --///////////////////////////////////////////////////////////////////////////// LIBRARY IEEE, std; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE work.hardcopyiii_atom_pack.all; USE work.hardcopyiii_lvds_rx_fifo_sync_ram; ENTITY hardcopyiii_lvds_rx_fifo is GENERIC ( channel_width : integer := 10; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tipd_wclk : VitalDelayType01 := DefpropDelay01; tipd_rclk : VitalDelayType01 := DefpropDelay01; tipd_dparst : VitalDelayType01 := DefpropDelay01; tipd_fiforst : VitalDelayType01 := DefpropDelay01; tipd_datain : VitalDelayType01 := DefpropDelay01; tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01; tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01 ); PORT ( wclk : IN std_logic:= '0'; rclk : IN std_logic:= '0'; dparst : IN std_logic := '0'; fiforst : IN std_logic := '0'; datain : IN std_logic := '0'; dataout : OUT std_logic ); END hardcopyiii_lvds_rx_fifo; ARCHITECTURE vital_arm_lvds_rx_fifo of hardcopyiii_lvds_rx_fifo is -- INTERNAL SIGNALS signal datain_in : std_logic; signal rclk_in : std_logic; signal dparst_in : std_logic; signal fiforst_in : std_logic; signal wclk_in : std_logic; signal ram_datain : std_logic; signal ram_dataout : std_logic; signal wrPtr : std_logic_vector(2 DOWNTO 0); signal rdPtr : std_logic_vector(2 DOWNTO 0); signal rdAddr : std_logic_vector(2 DOWNTO 0); signal ram_we : std_logic; signal write_side_sync_reset : std_logic; signal read_side_sync_reset : std_logic; COMPONENT hardcopyiii_lvds_rx_fifo_sync_ram PORT ( clk : IN std_logic; datain : IN std_logic := '0'; writereset : IN std_logic := '0'; waddr : IN std_logic_vector(2 DOWNTO 0) := "000"; raddr : IN std_logic_vector(2 DOWNTO 0) := "000"; we : IN std_logic := '0'; dataout : OUT std_logic ); END COMPONENT; begin ---------------------- -- INPUT PATH DELAYs ---------------------- WireDelay : block begin VitalWireDelay (wclk_in, wclk, tipd_wclk); VitalWireDelay (rclk_in, rclk, tipd_rclk); VitalWireDelay (dparst_in, dparst, tipd_dparst); VitalWireDelay (fiforst_in, fiforst, tipd_fiforst); VitalWireDelay (datain_in, datain, tipd_datain); end block; rdAddr <= rdPtr ; s_fifo_ram : hardcopyiii_lvds_rx_fifo_sync_ram PORT MAP ( clk => wclk_in, datain => ram_datain, writereset => write_side_sync_reset, waddr => wrPtr, raddr => rdAddr, we => ram_we, dataout => ram_dataout ); process (wclk_in, dparst_in) variable initial : boolean := true; begin if (initial) then wrPtr <= "000"; write_side_sync_reset <= '0'; ram_we <= '0'; ram_datain <= '0'; initial := false; end if; if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then write_side_sync_reset <= '1'; ram_datain <= '0'; wrPtr <= "000"; ram_we <= '0'; elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then write_side_sync_reset <= '0'; end if; if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then ram_datain <= datain_in; ram_we <= '1'; case wrPtr is when "000" => wrPtr <= "001"; when "001" => wrPtr <= "010"; when "010" => wrPtr <= "011"; when "011" => wrPtr <= "100"; when "100" => wrPtr <= "101"; when "101" => wrPtr <= "000"; when others => wrPtr <= "000"; end case; end if; end process; process (rclk_in, dparst_in) variable initial : boolean := true; variable dataout_tmp : std_logic := '0'; variable dataout_VitalGlitchData : VitalGlitchDataType; begin if (initial) then rdPtr <= "011"; read_side_sync_reset <= '0'; dataout_tmp := '0'; initial := false; end if; if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then read_side_sync_reset <= '1'; rdPtr <= "011"; dataout_tmp := '0'; elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then read_side_sync_reset <= '0'; end if; if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then case rdPtr is when "000" => rdPtr <= "001"; when "001" => rdPtr <= "010"; when "010" => rdPtr <= "011"; when "011" => rdPtr <= "100"; when "100" => rdPtr <= "101"; when "101" => rdPtr <= "000"; when others => rdPtr <= "000"; end case; dataout_tmp := ram_dataout; end if; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( Outsignal => dataout, OutsignalName => "DATAOUT", OutTemp => dataout_tmp, Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)), GlitchData => dataout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; END vital_arm_lvds_rx_fifo; --///////////////////////////////////////////////////////////////////////////// -- -- Module Name : hardcopyiii_lvds_rx_bitslip -- -- Description : -- --///////////////////////////////////////////////////////////////////////////// LIBRARY IEEE, std; USE ieee.std_logic_1164.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE work.hardcopyiii_atom_pack.all; USE work.hardcopyiii_lvds_reg; ENTITY hardcopyiii_lvds_rx_bitslip is GENERIC ( channel_width : integer := 10; bitslip_rollover : integer := 12; x_on_bitslip : string := "on"; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tipd_clk0 : VitalDelayType01 := DefpropDelay01; tipd_bslipcntl : VitalDelayType01 := DefpropDelay01; tipd_bsliprst : VitalDelayType01 := DefpropDelay01; tipd_datain : VitalDelayType01 := DefpropDelay01; tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01; tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01 ); PORT ( clk0 : IN std_logic := '0'; bslipcntl : IN std_logic := '0'; bsliprst : IN std_logic := '0'; datain : IN std_logic := '0'; bslipmax : OUT std_logic; dataout : OUT std_logic ); END hardcopyiii_lvds_rx_bitslip; ARCHITECTURE vital_arm_lvds_rx_bitslip OF hardcopyiii_lvds_rx_bitslip IS -- INTERNAL SIGNALS signal clk0_in : std_logic; signal bslipcntl_in : std_logic; signal bsliprst_in : std_logic; signal datain_in : std_logic; signal slip_count : integer := 0; signal dataout_tmp : std_logic; signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000"; signal bslipcntl_reg : std_logic; signal vcc : std_logic := '1'; signal slip_data : std_logic := '0'; signal start_corrupt_bits : std_logic := '0'; signal num_corrupt_bits : integer := 0; COMPONENT hardcopyiii_lvds_reg GENERIC ( MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_ena : VitalDelayType01 := DefpropDelay01; tipd_d : VitalDelayType01 := DefpropDelay01; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01 ); PORT ( q : OUT std_logic; clk : IN std_logic; ena : IN std_logic := '1'; d : IN std_logic; clrn : IN std_logic := '1'; prn : IN std_logic := '1' ); END COMPONENT; begin ---------------------- -- INPUT PATH DELAYs ---------------------- WireDelay : block begin VitalWireDelay (clk0_in, clk0, tipd_clk0); VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl); VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst); VitalWireDelay (datain_in, datain, tipd_datain); end block; bslipcntlreg : hardcopyiii_lvds_reg PORT MAP ( d => bslipcntl_in, clk => clk0_in, ena => vcc, clrn => vcc, prn => vcc, q => bslipcntl_reg ); -- 4-bit slip counter and 12-bit shift register process (bslipcntl_reg, bsliprst_in, clk0_in) variable initial : boolean := true; variable bslipmax_tmp : std_logic := '0'; variable bslipmax_VitalGlitchData : VitalGlitchDataType; begin if (bsliprst_in = '1') then slip_count <= 0; bslipmax_tmp := '0'; -- bitslip_arr <= (OTHERS => '0'); if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note; end if; else if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then if (x_on_bitslip = "on") then start_corrupt_bits <= '1'; end if; num_corrupt_bits <= 0; if (slip_count = bitslip_rollover) then ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note; slip_count <= 0; bslipmax_tmp := '0'; else slip_count <= slip_count + 1; if ((slip_count + 1) = bitslip_rollover) then ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note; bslipmax_tmp := '1'; end if; end if; elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then start_corrupt_bits <= '0'; num_corrupt_bits <= 0; end if; end if; if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then bitslip_arr(0) <= datain_in; for i in 0 to (bitslip_rollover - 1) loop bitslip_arr(i + 1) <= bitslip_arr(i); end loop; if (start_corrupt_bits = '1') then num_corrupt_bits <= num_corrupt_bits + 1; end if; if (num_corrupt_bits+1 = 3) then start_corrupt_bits <= '0'; end if; end if; -- end if; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( Outsignal => bslipmax, OutsignalName => "BSLIPMAX", OutTemp => bslipmax_tmp, Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE), 2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)), GlitchData => bslipmax_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); end process; slip_data <= bitslip_arr(slip_count); dataoutreg : hardcopyiii_lvds_reg PORT MAP ( d => slip_data, clk => clk0_in, ena => vcc, clrn => vcc, prn => vcc, q => dataout_tmp ); dataout <= dataout_tmp when start_corrupt_bits = '0' else 'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else dataout_tmp; END vital_arm_lvds_rx_bitslip; --///////////////////////////////////////////////////////////////////////////// -- -- Module Name : hardcopyiii_lvds_rx_deser -- -- Description : Timing simulation model for the hardcopyiii LVDS RECEIVER -- DESERIALIZER. This module receives serial data and outputs -- parallel data word of width = channel width -- --//////////////////////////////////////////////////////////////////////////// LIBRARY IEEE; USE ieee.std_logic_1164.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_lvds_rx_deser IS GENERIC ( channel_width : integer := 4; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_datain : VitalDelayType01 := DefpropDelay01; tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01 ); PORT ( clk : IN std_logic := '0'; datain : IN std_logic := '0'; dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0); devclrn : IN std_logic := '1'; devpor : IN std_logic := '1' ); END hardcopyiii_lvds_rx_deser; ARCHITECTURE vital_arm_lvds_rx_deser OF hardcopyiii_lvds_rx_deser IS -- INTERNAL SIGNALS signal clk_ipd : std_logic; signal datain_ipd : std_logic; begin ---------------------- -- INPUT PATH DELAYs ---------------------- WireDelay : block begin VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (datain_ipd, datain, tipd_datain); end block; VITAL: process (clk_ipd, devpor, devclrn) variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0'); variable i : integer := 0; variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0); variable CQDelay : TIME := 0 ns; begin if (devclrn = '0' or devpor = '0') then dataout_tmp := (OTHERS => '0'); else if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then for i in channel_width - 1 DOWNTO 1 loop dataout_tmp(i) := dataout_tmp(i - 1); end loop; dataout_tmp(0) := datain_ipd; end if; end if; ---------------------- -- Path Delay Section ---------------------- CQDelay := SelectDelay ( (1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE)) ); dataout <= TRANSPORT dataout_tmp AFTER CQDelay; end process; END vital_arm_lvds_rx_deser; --///////////////////////////////////////////////////////////////////////////// -- -- Module Name : hardcopyiii_lvds_rx_parallel_reg -- -- Description : Timing simulation model for the hardcopyiii LVDS RECEIVER -- PARALLEL REGISTER. The data width equals max. channel width, -- which is 10. -- --//////////////////////////////////////////////////////////////////////////// LIBRARY IEEE; USE ieee.std_logic_1164.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_lvds_rx_parallel_reg IS GENERIC ( channel_width : integer := 4; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_enable : VitalDelayType01 := DefpropDelay01; tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01); tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01 ); PORT ( clk : IN std_logic; enable : IN std_logic := '1'; datain : IN std_logic_vector(channel_width - 1 DOWNTO 0); dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0); devclrn : IN std_logic := '1'; devpor : IN std_logic := '1' ); END hardcopyiii_lvds_rx_parallel_reg; ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF hardcopyiii_lvds_rx_parallel_reg IS -- INTERNAL SIGNALS signal clk_ipd : std_logic; signal datain_ipd : std_logic_vector(channel_width - 1 downto 0); signal enable_ipd : std_logic; begin ---------------------- -- INPUT PATH DELAYs ---------------------- WireDelay : block begin VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (enable_ipd, enable, tipd_enable); loopbits : FOR i in datain'RANGE GENERATE VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i)); END GENERATE; end block; VITAL: process (clk_ipd, devpor, devclrn) variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0'); variable i : integer := 0; variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0); variable CQDelay : TIME := 0 ns; begin if ((devpor = '0') or (devclrn = '0')) then dataout_tmp := (OTHERS => '0'); else if (clk_ipd'event and clk_ipd = '1') then if (enable_ipd = '1') then dataout_tmp := datain_ipd; end if; end if; end if; ---------------------- -- Path Delay Section ---------------------- CQDelay := SelectDelay ( (1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE)) ); dataout <= dataout_tmp AFTER CQDelay; end process; END vital_arm_lvds_rx_parallel_reg; ------------------------------------------------------------------------------- -- -- Module Name : hardcopyiii_pclk_divider -- -- Description : Simulation model for a clock divider -- output clock is divided by value specified -- in the parameter clk_divide_by -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY hardcopyiii_pclk_divider IS GENERIC ( clk_divide_by : integer := 1); PORT ( clkin : IN std_logic; lloaden : OUT std_logic; clkout : OUT std_logic); END hardcopyiii_pclk_divider; ARCHITECTURE arch OF hardcopyiii_pclk_divider IS SIGNAL lloaden_tmp : std_logic := '0'; SIGNAL clkout_tmp : std_logic := '0'; SIGNAL cnt : std_logic_vector(4 DOWNTO 0):= (others => '0'); BEGIN clkout <= clkin WHEN (clk_divide_by = 1) ELSE clkout_tmp; lloaden <= lloaden_tmp; PROCESS(clkin) variable count : std_logic := '0'; variable start : std_logic := '0'; variable prev_load : std_logic := '0'; BEGIN IF(clkin = '1') THEN count := '1'; END IF; if( count = '1') then IF (cnt < clk_divide_by) THEN clkout_tmp <= '0'; cnt <= cnt + "00001"; ELSE IF (cnt = (2 * clk_divide_by - 1)) THEN cnt <= "00000"; ELSE clkout_tmp <= '1'; cnt <= cnt + "00001"; END IF; END IF; end if; END PROCESS; process( clkin, cnt ) begin if( cnt =( 2*clk_divide_by -2) )then lloaden_tmp <= '1'; else if(cnt = 0)then lloaden_tmp <= '0'; end if; end if; end process; END arch; ------------------------------------------------------------------------------- -- -- Module Name : hardcopyiii_select_ini_phase_dpaclk -- -- Description : Simulation model for selecting the initial phase of the dpa clock -- -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.ALL; ENTITY hardcopyiii_select_ini_phase_dpaclk IS GENERIC( initial_phase_select : integer := 0 ); PORT ( clkin : IN STD_LOGIC; loaden : IN STD_LOGIC; enable : IN STD_LOGIC; clkout : OUT STD_LOGIC; loadenout : OUT STD_LOGIC ); END hardcopyiii_select_ini_phase_dpaclk; ARCHITECTURE trans OF hardcopyiii_select_ini_phase_dpaclk IS SIGNAL clk_period : time := 0 ps; SIGNAL last_clk_period : time := 0 ps; SIGNAL last_clkin_edge : time := 0 ps; SIGNAL first_clkin_edge_detect : STD_LOGIC := '0'; SIGNAL clk0_tmp : STD_LOGIC; SIGNAL clk1_tmp : STD_LOGIC; SIGNAL clk2_tmp : STD_LOGIC; SIGNAL clk3_tmp : STD_LOGIC; SIGNAL clk4_tmp : STD_LOGIC; SIGNAL clk5_tmp : STD_LOGIC; SIGNAL clk6_tmp : STD_LOGIC; SIGNAL clk7_tmp : STD_LOGIC; SIGNAL loaden0_tmp : STD_LOGIC; SIGNAL loaden1_tmp : STD_LOGIC; SIGNAL loaden2_tmp : STD_LOGIC; SIGNAL loaden3_tmp : STD_LOGIC; SIGNAL loaden4_tmp : STD_LOGIC; SIGNAL loaden5_tmp : STD_LOGIC; SIGNAL loaden6_tmp : STD_LOGIC; SIGNAL loaden7_tmp : STD_LOGIC; SIGNAL clkout_tmp : STD_LOGIC; SIGNAL loadenout_tmp : STD_LOGIC; BEGIN clkout_tmp <= clk1_tmp when (initial_phase_select = 1) else clk2_tmp when (initial_phase_select = 2) else clk3_tmp when (initial_phase_select = 3) else clk4_tmp when (initial_phase_select = 4) else clk5_tmp when (initial_phase_select = 5) else clk6_tmp when (initial_phase_select = 6) else clk7_tmp when (initial_phase_select = 7) else clk0_tmp; clkout <= clkout_tmp when enable = '1' else clkin; loadenout_tmp <= loaden1_tmp when (initial_phase_select = 1) else loaden2_tmp when (initial_phase_select = 2) else loaden3_tmp when (initial_phase_select = 3) else loaden4_tmp when (initial_phase_select = 4) else loaden5_tmp when (initial_phase_select = 5) else loaden6_tmp when (initial_phase_select = 6) else loaden7_tmp when (initial_phase_select = 7) else loaden0_tmp; loadenout <= loadenout_tmp when enable = '1' else loaden; -- Calculate the clock period PROCESS VARIABLE clk_period_tmp : time := 0 ps; BEGIN WAIT UNTIL (clkin'EVENT AND clkin = '1'); IF (first_clkin_edge_detect = '0') THEN first_clkin_edge_detect <= '1'; ELSE last_clk_period <= clk_period; clk_period_tmp := NOW - last_clkin_edge; END IF; last_clkin_edge <= NOW; clk_period <= clk_period_tmp; END PROCESS; -- Generate the phase shifted signals PROCESS (clkin) BEGIN clk0_tmp <= clkin; clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ; clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ; clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ; clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ; clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ; clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ; clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ; END PROCESS; PROCESS (loaden) BEGIN loaden0_tmp <= clkin; loaden1_tmp <= TRANSPORT loaden after (clk_period * 0.125) ; loaden2_tmp <= TRANSPORT loaden after (clk_period * 0.25) ; loaden3_tmp <= TRANSPORT loaden after (clk_period * 0.375) ; loaden4_tmp <= TRANSPORT loaden after (clk_period * 0.5) ; loaden5_tmp <= TRANSPORT loaden after (clk_period * 0.625) ; loaden6_tmp <= TRANSPORT loaden after (clk_period * 0.75) ; loaden7_tmp <= TRANSPORT loaden after (clk_period * 0.875) ; END PROCESS; END trans; ------------------------------------------------------------------------------- -- -- Module Name : hardcopyiii_dpa_retime_block -- -- Description : Simulation model for generating the retimed clock,data and loaden. -- Each of the signals has 8 different phase shifted versions. -- -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.ALL; ENTITY hardcopyiii_dpa_retime_block IS PORT ( clkin : IN STD_LOGIC; datain : IN STD_LOGIC; reset : IN STD_LOGIC; clk0 : OUT STD_LOGIC; clk1 : OUT STD_LOGIC; clk2 : OUT STD_LOGIC; clk3 : OUT STD_LOGIC; clk4 : OUT STD_LOGIC; clk5 : OUT STD_LOGIC; clk6 : OUT STD_LOGIC; clk7 : OUT STD_LOGIC; data0 : OUT STD_LOGIC; data1 : OUT STD_LOGIC; data2 : OUT STD_LOGIC; data3 : OUT STD_LOGIC; data4 : OUT STD_LOGIC; data5 : OUT STD_LOGIC; data6 : OUT STD_LOGIC; data7 : OUT STD_LOGIC; lock : OUT STD_LOGIC ); END hardcopyiii_dpa_retime_block; ARCHITECTURE trans OF hardcopyiii_dpa_retime_block IS SIGNAL clk_period : time := 0 ps; SIGNAL last_clk_period : time := 0 ps; SIGNAL last_clkin_edge : time := 0 ps; SIGNAL first_clkin_edge_detect : STD_LOGIC := '0'; SIGNAL clk0_tmp : STD_LOGIC; SIGNAL clk1_tmp : STD_LOGIC; SIGNAL clk2_tmp : STD_LOGIC; SIGNAL clk3_tmp : STD_LOGIC; SIGNAL clk4_tmp : STD_LOGIC; SIGNAL clk5_tmp : STD_LOGIC; SIGNAL clk6_tmp : STD_LOGIC; SIGNAL clk7_tmp : STD_LOGIC; SIGNAL data0_tmp : STD_LOGIC; SIGNAL data1_tmp : STD_LOGIC; SIGNAL data2_tmp : STD_LOGIC; SIGNAL data3_tmp : STD_LOGIC; SIGNAL data4_tmp : STD_LOGIC; SIGNAL data5_tmp : STD_LOGIC; SIGNAL data6_tmp : STD_LOGIC; SIGNAL data7_tmp : STD_LOGIC; SIGNAL lock_tmp : STD_LOGIC := '0'; BEGIN clk0 <= '0' WHEN reset = '1' ELSE clk0_tmp; clk1 <= '0' WHEN reset = '1' ELSE clk1_tmp; clk2 <= '0' WHEN reset = '1' ELSE clk2_tmp; clk3 <= '0' WHEN reset = '1' ELSE clk3_tmp; clk4 <= '0' WHEN reset = '1' ELSE clk4_tmp; clk5 <= '0' WHEN reset = '1' ELSE clk5_tmp; clk6 <= '0' WHEN reset = '1' ELSE clk6_tmp; clk7 <= '0' WHEN reset = '1' ELSE clk7_tmp; data0 <= '0' WHEN reset = '1' ELSE data0_tmp; data1 <= '0' WHEN reset = '1' ELSE data1_tmp; data2 <= '0' WHEN reset = '1' ELSE data2_tmp; data3 <= '0' WHEN reset = '1' ELSE data3_tmp; data4 <= '0' WHEN reset = '1' ELSE data4_tmp; data5 <= '0' WHEN reset = '1' ELSE data5_tmp; data6 <= '0' WHEN reset = '1' ELSE data6_tmp; data7 <= '0' WHEN reset = '1' ELSE data7_tmp; lock <= '0' WHEN reset = '1' ELSE lock_tmp; -- Calculate the clock period PROCESS VARIABLE clk_period_tmp : time := 0 ps; BEGIN WAIT UNTIL (clkin'EVENT AND clkin = '1'); IF (first_clkin_edge_detect = '0') THEN first_clkin_edge_detect <= '1'; ELSE last_clk_period <= clk_period; clk_period_tmp := NOW - last_clkin_edge; END IF; IF (((clk_period_tmp = last_clk_period) OR (clk_period_tmp = last_clk_period + 1 ps) OR (clk_period_tmp = last_clk_period - 1 ps)) AND (clk_period_tmp /= 0 ps ) AND (last_clk_period /= 0 ps)) THEN lock_tmp <= '1'; ELSE lock_tmp <= '0'; END IF; last_clkin_edge <= NOW; clk_period <= clk_period_tmp; END PROCESS; -- Generate the phase shifted signals PROCESS (clkin) BEGIN clk0_tmp <= clkin; clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ; clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ; clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ; clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ; clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ; clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ; clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ; END PROCESS; PROCESS (datain) BEGIN data0_tmp <= datain; data1_tmp <= TRANSPORT datain after (clk_period * 0.125) ; data2_tmp <= TRANSPORT datain after (clk_period * 0.25) ; data3_tmp <= TRANSPORT datain after (clk_period * 0.375) ; data4_tmp <= TRANSPORT datain after (clk_period * 0.5) ; data5_tmp <= TRANSPORT datain after (clk_period * 0.625) ; data6_tmp <= TRANSPORT datain after (clk_period * 0.75) ; data7_tmp <= TRANSPORT datain after (clk_period * 0.875) ; END PROCESS; END trans; ------------------------------------------------------------------------------- -- -- Module Name : hardcopyiii_dpa_block -- -- Description : Simulation model for selecting the retimed data, clock and loaden -- depending on the PPM varaiation and direction of shift. -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE work.hardcopyiii_dpa_retime_block; ENTITY hardcopyiii_dpa_block IS GENERIC ( net_ppm_variation : INTEGER := 0; is_negative_ppm_drift : STRING := "off"; enable_soft_cdr_mode: STRING := "on" ); PORT ( clkin : IN STD_LOGIC; dpareset : IN STD_LOGIC; dpahold : IN STD_LOGIC; datain : IN STD_LOGIC; clkout : OUT STD_LOGIC; dataout : OUT STD_LOGIC; dpalock : OUT STD_LOGIC ); END hardcopyiii_dpa_block; ARCHITECTURE trans OF hardcopyiii_dpa_block IS COMPONENT hardcopyiii_dpa_retime_block PORT ( clkin : IN STD_LOGIC; datain : IN STD_LOGIC; reset : IN STD_LOGIC; clk0 : OUT STD_LOGIC; clk1 : OUT STD_LOGIC; clk2 : OUT STD_LOGIC; clk3 : OUT STD_LOGIC; clk4 : OUT STD_LOGIC; clk5 : OUT STD_LOGIC; clk6 : OUT STD_LOGIC; clk7 : OUT STD_LOGIC; data0 : OUT STD_LOGIC; data1 : OUT STD_LOGIC; data2 : OUT STD_LOGIC; data3 : OUT STD_LOGIC; data4 : OUT STD_LOGIC; data5 : OUT STD_LOGIC; data6 : OUT STD_LOGIC; data7 : OUT STD_LOGIC; lock : OUT STD_LOGIC ); END COMPONENT; SIGNAL clk0_tmp : STD_LOGIC; SIGNAL clk1_tmp : STD_LOGIC; SIGNAL clk2_tmp : STD_LOGIC; SIGNAL clk3_tmp : STD_LOGIC; SIGNAL clk4_tmp : STD_LOGIC; SIGNAL clk5_tmp : STD_LOGIC; SIGNAL clk6_tmp : STD_LOGIC; SIGNAL clk7_tmp : STD_LOGIC; SIGNAL data0_tmp : STD_LOGIC; SIGNAL data1_tmp : STD_LOGIC; SIGNAL data2_tmp : STD_LOGIC; SIGNAL data3_tmp : STD_LOGIC; SIGNAL data4_tmp : STD_LOGIC; SIGNAL data5_tmp : STD_LOGIC; SIGNAL data6_tmp : STD_LOGIC; SIGNAL data7_tmp : STD_LOGIC; SIGNAL select_xhdl1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); SIGNAL clkout_tmp : STD_LOGIC; SIGNAL dataout_tmp : STD_LOGIC; SIGNAL counter_reset_value : INTEGER ; SIGNAL count_value : INTEGER ; SIGNAL i : INTEGER := 0; SIGNAL dpalock_xhdl0 : STD_LOGIC; BEGIN -- Drive referenced outputs dpalock <= dpalock_xhdl0; dataout <= dataout_tmp when (enable_soft_cdr_mode = "on") else datain; clkout <= clkout_tmp when (enable_soft_cdr_mode = "on") else clkin; data_clock_retime : hardcopyiii_dpa_retime_block PORT MAP ( clkin => clkin, datain => datain, reset => dpareset, clk0 => clk0_tmp, clk1 => clk1_tmp, clk2 => clk2_tmp, clk3 => clk3_tmp, clk4 => clk4_tmp, clk5 => clk5_tmp, clk6 => clk6_tmp, clk7 => clk7_tmp, data0 => data0_tmp, data1 => data1_tmp, data2 => data2_tmp, data3 => data3_tmp, data4 => data4_tmp, data5 => data5_tmp, data6 => data6_tmp, data7 => data7_tmp, lock => dpalock_xhdl0 ); PROCESS (clkin, dpareset, dpahold) variable initial : boolean := true; variable ppm_tmp : integer; BEGIN if(initial) then if(net_ppm_variation = 0) then ppm_tmp := 1; else ppm_tmp := net_ppm_variation; end if; if(net_ppm_variation = 0) then counter_reset_value <= 1; count_value <= 1; initial := false; else counter_reset_value <= 1000000 / (ppm_tmp * 8); count_value <= 1000000 / (ppm_tmp * 8); initial := false; end if; end if; IF (clkin'EVENT AND clkin = '1') THEN IF(net_ppm_variation = 0) THEN select_xhdl1 <= "000"; ELSE IF (dpareset = '1') THEN i <= 0; select_xhdl1 <= "000"; ELSE IF (dpahold = '0') THEN IF (i < count_value) THEN i <= i + 1; ELSE select_xhdl1 <= select_xhdl1 + "001"; i <= 0; END IF; END IF; END IF; END IF; END IF; END PROCESS; PROCESS (select_xhdl1, clk0_tmp, clk1_tmp, clk2_tmp, clk3_tmp, clk4_tmp, clk5_tmp, clk6_tmp, clk7_tmp, data0_tmp, data1_tmp, data2_tmp, data3_tmp, data4_tmp, data5_tmp, data6_tmp, data7_tmp) BEGIN if (select_xhdl1 = "000") then clkout_tmp <= clk0_tmp; dataout_tmp <= data0_tmp; elsif (select_xhdl1 = "001") then if( is_negative_ppm_drift = "off")then clkout_tmp <= clk1_tmp; dataout_tmp <= data1_tmp; else clkout_tmp <= clk7_tmp; dataout_tmp <= data7_tmp; end if; elsif (select_xhdl1 = "010") then if( is_negative_ppm_drift = "off")then clkout_tmp <= clk2_tmp; dataout_tmp <= data2_tmp; else clkout_tmp <= clk6_tmp; dataout_tmp <= data6_tmp; end if; elsif (select_xhdl1 = "011")then if( is_negative_ppm_drift = "off")then clkout_tmp <= clk3_tmp; dataout_tmp <= data3_tmp; else clkout_tmp <= clk5_tmp; dataout_tmp <= data5_tmp; end if; elsif (select_xhdl1 = "100")then clkout_tmp <= clk4_tmp; dataout_tmp <= data4_tmp; elsif (select_xhdl1 = "101")then if( is_negative_ppm_drift = "off")then clkout_tmp <= clk5_tmp; dataout_tmp <= data5_tmp; else clkout_tmp <= clk3_tmp; dataout_tmp <= data3_tmp; end if; elsif (select_xhdl1 = "110") then if( is_negative_ppm_drift = "off")then clkout_tmp <= clk6_tmp; dataout_tmp <= data6_tmp; else clkout_tmp <= clk2_tmp; dataout_tmp <= data2_tmp; end if; elsif (select_xhdl1 = "111")then if( is_negative_ppm_drift = "off")then clkout_tmp <= clk7_tmp; dataout_tmp <= data7_tmp; else clkout_tmp <= clk1_tmp; dataout_tmp <= data1_tmp; end if; else clkout_tmp <= clk0_tmp; dataout_tmp <= data0_tmp; end if; END PROCESS; END trans; --///////////////////////////////////////////////////////////////////////////// -- -- Module Name : hardcopyiii_LVDS_RECEIVER -- -- Description : Timing simulation model for the hardcopyiii LVDS RECEIVER -- atom. This module instantiates the following sub-modules : -- 1) hardcopyiii_lvds_rx_fifo -- 2) hardcopyiii_lvds_rx_bitslip -- 3) DFFEs for the LOADEN signals -- 4) hardcopyiii_lvds_rx_parallel_reg -- 5) hardcopyiii_pclk_divider -- 6) hardcopyiii_select_ini_phase_dpaclk -- 7) hardcopyiii_dpa_block -- --///////////////////////////////////////////////////////////////////////////// LIBRARY IEEE; USE ieee.std_logic_1164.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; USE work.hardcopyiii_atom_pack.all; USE work.hardcopyiii_lvds_rx_bitslip; USE work.hardcopyiii_lvds_rx_fifo; USE work.hardcopyiii_lvds_rx_deser; USE work.hardcopyiii_lvds_rx_parallel_reg; USE work.hardcopyiii_lvds_reg; USE work.hardcopyiii_pclk_divider; USE work.hardcopyiii_select_ini_phase_dpaclk; USE work.hardcopyiii_dpa_block; ENTITY hardcopyiii_lvds_receiver IS GENERIC ( channel_width : integer := 10; data_align_rollover : integer := 2; enable_dpa : string := "off"; lose_lock_on_one_change : string := "off"; reset_fifo_at_first_lock : string := "on"; align_to_rising_edge_only : string := "on"; use_serial_feedback_input : string := "off"; dpa_debug : string := "off"; enable_soft_cdr : string := "off"; dpa_output_clock_phase_shift : INTEGER := 0 ; enable_dpa_initial_phase_selection : string := "off"; dpa_initial_phase_value : INTEGER := 0; enable_dpa_align_to_rising_edge_only : string := "off"; net_ppm_variation : INTEGER := 0; is_negative_ppm_drift : string := "off"; rx_input_path_delay_engineering_bits : INTEGER := -1; x_on_bitslip : string := "on"; lpm_type : string := "hardcopyiii_lvds_receiver"; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tipd_clk0 : VitalDelayType01 := DefpropDelay01; tipd_datain : VitalDelayType01 := DefpropDelay01; tipd_enable0 : VitalDelayType01 := DefpropDelay01; tipd_dpareset : VitalDelayType01 := DefpropDelay01; tipd_dpahold : VitalDelayType01 := DefpropDelay01; tipd_dpaswitch : VitalDelayType01 := DefpropDelay01; tipd_fiforeset : VitalDelayType01 := DefpropDelay01; tipd_bitslip : VitalDelayType01 := DefpropDelay01; tipd_bitslipreset : VitalDelayType01 := DefpropDelay01; tipd_serialfbk : VitalDelayType01 := DefpropDelay01; tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01 ); PORT ( clk0 : IN std_logic; datain : IN std_logic := '0'; enable0 : IN std_logic := '0'; dpareset : IN std_logic := '0'; dpahold : IN std_logic := '0'; dpaswitch : IN std_logic := '0'; fiforeset : IN std_logic := '0'; bitslip : IN std_logic := '0'; bitslipreset : IN std_logic := '0'; serialfbk : IN std_logic := '0'; dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0); dpalock : OUT std_logic:= '0'; bitslipmax : OUT std_logic; serialdataout : OUT std_logic; postdpaserialdataout : OUT std_logic; divfwdclk : OUT std_logic; dpaclkout : OUT std_logic; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1' ); END hardcopyiii_lvds_receiver; ARCHITECTURE vital_arm_lvds_receiver OF hardcopyiii_lvds_receiver IS COMPONENT hardcopyiii_lvds_rx_bitslip GENERIC ( channel_width : integer := 10; bitslip_rollover : integer := 12; x_on_bitslip : string := "on"; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tipd_clk0 : VitalDelayType01 := DefpropDelay01; tipd_bslipcntl : VitalDelayType01 := DefpropDelay01; tipd_bsliprst : VitalDelayType01 := DefpropDelay01; tipd_datain : VitalDelayType01 := DefpropDelay01; tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01; tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01 ); PORT ( clk0 : IN std_logic := '0'; bslipcntl : IN std_logic := '0'; bsliprst : IN std_logic := '0'; datain : IN std_logic := '0'; bslipmax : OUT std_logic; dataout : OUT std_logic ); END COMPONENT; COMPONENT hardcopyiii_lvds_rx_fifo GENERIC ( channel_width : integer := 10 ); PORT ( wclk : IN std_logic := '0'; rclk : IN std_logic := '0'; fiforst : IN std_logic := '0'; dparst : IN std_logic := '0'; datain : IN std_logic := '0'; dataout : OUT std_logic ); END COMPONENT; COMPONENT hardcopyiii_lvds_rx_deser GENERIC ( channel_width : integer := 4 ); PORT ( clk : IN std_logic; datain : IN std_logic; dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0); devclrn : IN std_logic := '1'; devpor : IN std_logic := '1' ); END COMPONENT; COMPONENT hardcopyiii_lvds_rx_parallel_reg GENERIC ( channel_width : integer := 4 ); PORT ( clk : IN std_logic; enable : IN std_logic := '1'; datain : IN std_logic_vector(channel_width - 1 DOWNTO 0); dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0); devclrn : IN std_logic := '1'; devpor : IN std_logic := '1' ); END COMPONENT; COMPONENT hardcopyiii_lvds_reg GENERIC ( MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_ena : VitalDelayType01 := DefpropDelay01; tipd_d : VitalDelayType01 := DefpropDelay01; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01 ); PORT ( q : OUT std_logic; clk : IN std_logic; ena : IN std_logic := '1'; d : IN std_logic; clrn : IN std_logic := '1'; prn : IN std_logic := '1' ); END COMPONENT; COMPONENT hardcopyiii_pclk_divider GENERIC ( clk_divide_by : integer := 1); PORT ( clkin : IN std_logic; lloaden : OUT std_logic; clkout : OUT std_logic); END COMPONENT; COMPONENT hardcopyiii_select_ini_phase_dpaclk GENERIC( initial_phase_select : integer := 0 ); PORT ( clkin : IN STD_LOGIC; loaden : IN STD_LOGIC; enable : IN STD_LOGIC; loadenout : OUT STD_LOGIC; clkout : OUT STD_LOGIC ); END COMPONENT; COMPONENT hardcopyiii_dpa_block GENERIC ( net_ppm_variation : INTEGER := 0; is_negative_ppm_drift : STRING := "off"; enable_soft_cdr_mode: STRING := "on" ); PORT ( clkin : IN STD_LOGIC; dpareset : IN STD_LOGIC; dpahold : IN STD_LOGIC; datain : IN STD_LOGIC; clkout : OUT STD_LOGIC; dataout : OUT STD_LOGIC; dpalock : OUT STD_LOGIC ); END COMPONENT; -- INTERNAL SIGNALS signal bitslip_ipd : std_logic; signal bitslipreset_ipd : std_logic; signal clk0_ipd : std_logic; signal datain_ipd : std_logic; signal dpahold_ipd : std_logic; signal dpareset_ipd : std_logic; signal dpaswitch_ipd : std_logic; signal enable0_ipd : std_logic; signal fiforeset_ipd : std_logic; signal serialfbk_ipd : std_logic; signal fifo_wclk : std_logic; signal fifo_rclk : std_logic; signal fifo_datain : std_logic; signal fifo_dataout : std_logic; signal fifo_reset : std_logic; signal slip_datain : std_logic; signal slip_dataout : std_logic; signal bitslip_reset : std_logic; -- wire deser_dataout; signal dpa_clk : std_logic; signal dpa_rst : std_logic; signal datain_reg : std_logic; signal datain_reg_neg : std_logic; signal datain_reg_tmp : std_logic; signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0); signal reset_fifo : std_logic; signal gnd : std_logic := '0'; signal vcc : std_logic := '1'; signal in_reg_data : std_logic; signal slip_datain_tmp : std_logic; signal s_bitslip_clk : std_logic; signal loaden : std_logic; signal ini_dpa_clk : std_logic; signal ini_dpa_load : std_logic; signal ini_phase_select_enable : std_logic; signal dpa_clk_shift : std_logic; signal dpa_data_shift : std_logic; signal lloaden : std_logic; signal lock_tmp : std_logic; signal divfwdclk_tmp : std_logic; signal dpa_is_locked : std_logic; signal dpareg0_out : std_logic; signal dpareg1_out : std_logic; signal xhdl_12 : std_logic; signal rxload : std_logic; signal clk0_tmp : std_logic; signal clk0_tmp_neg : std_logic; begin WireDelay : block begin VitalWireDelay (clk0_ipd, clk0, tipd_clk0); VitalWireDelay (datain_ipd, datain, tipd_datain); VitalWireDelay (enable0_ipd, enable0, tipd_enable0); VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset); VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold); VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch); VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset); VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip); VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset); VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk); end block; process (clk0_ipd, dpareset_ipd,lock_tmp ) variable dpalock_VitalGlitchData : VitalGlitchDataType; variable initial : boolean := true; begin if (initial) then if (reset_fifo_at_first_lock = "on") then reset_fifo <= '1'; else reset_fifo <= '0'; end if; initial := false; end if; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => dpalock, OutSignalName => "DPALOCK", OutTemp => dpa_is_locked, Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")), GlitchData => dpalock_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); if(lock_tmp = '1') then reset_fifo <= '0'; else reset_fifo <= '1'; end if; end process; xhdl_12 <= devclrn OR devpor; -- input register in non-DPA mode for sampling incoming data in_reg : hardcopyiii_lvds_reg PORT MAP ( d => in_reg_data, clk => clk0_tmp, ena => vcc, clrn => xhdl_12, prn => vcc, q => datain_reg ); in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd; clk0_tmp <= clk0_ipd; clk0_tmp_neg <= not clk0_ipd; neg_reg : hardcopyiii_lvds_reg PORT MAP ( d => in_reg_data, clk => clk0_tmp_neg, ena => vcc, clrn => xhdl_12, prn => vcc, q => datain_reg_neg ); datain_reg_tmp <= datain_reg WHEN (align_to_rising_edge_only = "on") ELSE datain_reg_neg; -- dpa initial phase select ini_clk_phase_select: hardcopyiii_select_ini_phase_dpaclk GENERIC MAP( initial_phase_select => dpa_initial_phase_value ) PORT MAP( clkin => clk0_ipd, loaden => enable0_ipd, enable => ini_phase_select_enable, loadenout=>ini_dpa_load, clkout => ini_dpa_clk ); ini_phase_select_enable <= '1' when (enable_dpa_initial_phase_selection = "on") else '0'; -- DPA circuitary dpareg0 : hardcopyiii_lvds_reg PORT MAP ( d => in_reg_data, clk => ini_dpa_clk, clrn => vcc, prn => vcc, ena => vcc, q => dpareg0_out ); dpareg1 : hardcopyiii_lvds_reg PORT MAP ( d => dpareg0_out, clk => ini_dpa_clk, clrn => vcc, prn => vcc, ena => vcc, q => dpareg1_out ); dpa_circuit: hardcopyiii_dpa_block GENERIC MAP( net_ppm_variation => net_ppm_variation, is_negative_ppm_drift => is_negative_ppm_drift, enable_soft_cdr_mode => enable_soft_cdr ) PORT MAP( clkin => ini_dpa_clk, dpareset => dpareset_ipd, dpahold => dpahold_ipd, datain => dpareg1_out, clkout => dpa_clk_shift, dataout => dpa_data_shift, dpalock => lock_tmp ); dpa_clk <= dpa_clk_shift when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ; dpa_rst <= dpareset_ipd when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ; -- PCLK and lloaden generation clk_forward: hardcopyiii_pclk_divider GENERIC MAP ( clk_divide_by => channel_width ) PORT MAP( clkin => dpa_clk, lloaden => lloaden, clkout => divfwdclk_tmp ); -- FIFO s_fifo : hardcopyiii_lvds_rx_fifo GENERIC MAP ( channel_width => channel_width ) PORT MAP ( wclk => dpa_clk, rclk => fifo_rclk, fiforst => fifo_reset, dparst => dpa_rst, datain => fifo_datain, dataout => fifo_dataout ); fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ; fifo_wclk <= dpa_clk ; fifo_datain <= dpa_data_shift WHEN (enable_dpa = "on") ELSE gnd ; fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpa_rst OR reset_fifo ; -- Bit Slip s_bslip : hardcopyiii_lvds_rx_bitslip GENERIC MAP ( bitslip_rollover => data_align_rollover, channel_width => channel_width, x_on_bitslip => x_on_bitslip ) PORT MAP ( clk0 => s_bitslip_clk, bslipcntl => bitslip_ipd, bsliprst => bitslip_reset, datain => slip_datain, bslipmax => bitslipmax, dataout => slip_dataout ); bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ; slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" and dpaswitch_ipd = '1') else datain_reg_tmp ; slip_datain <= dpa_data_shift when(enable_soft_cdr = "on") else slip_datain_tmp; s_bitslip_clk <= dpa_clk when (enable_soft_cdr = "on") else clk0_ipd; -- DESERIALISER rxload_reg : hardcopyiii_lvds_reg PORT MAP ( d => loaden, clk => s_bitslip_clk, ena => vcc, clrn => vcc, prn => vcc, q => rxload ); loaden <= lloaden when (enable_soft_cdr = "on") else ini_dpa_load; s_deser : hardcopyiii_lvds_rx_deser GENERIC MAP (channel_width => channel_width ) PORT MAP (clk => s_bitslip_clk, datain => slip_dataout, devclrn => devclrn, devpor => devpor, dataout => deser_dataout ); output_reg : hardcopyiii_lvds_rx_parallel_reg GENERIC MAP ( channel_width => channel_width ) PORT MAP ( clk => s_bitslip_clk, enable => rxload, datain => deser_dataout, devpor => devpor, devclrn => devclrn, dataout => dataout ); dpa_is_locked <= gnd; dpaclkout <= dpa_clk_shift; postdpaserialdataout <= dpa_data_shift ; serialdataout <= datain_ipd; divfwdclk <= divfwdclk_tmp ; END vital_arm_lvds_receiver; ---------------------------------------------------------------------------------- --Module Name: hardcopyiii_pseudo_diff_out -- --Description: Simulation model for HARDCOPYIII Pseudo Differential -- -- Output Buffer -- ---------------------------------------------------------------------------------- LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_pseudo_diff_out IS GENERIC ( tipd_i : VitalDelayType01 := DefPropDelay01; tpd_i_o : VitalDelayType01 := DefPropDelay01; tpd_i_obar : VitalDelayType01 := DefPropDelay01; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; lpm_type : string := "hardcopyiii_pseudo_diff_out" ); PORT ( i : IN std_logic := '0'; o : OUT std_logic; obar : OUT std_logic ); END hardcopyiii_pseudo_diff_out; ARCHITECTURE arch OF hardcopyiii_pseudo_diff_out IS SIGNAL i_ipd : std_logic ; SIGNAL o_tmp : std_logic ; SIGNAL obar_tmp : std_logic; BEGIN WireDelay : block begin VitalWireDelay (i_ipd, i, tipd_i); end block; PROCESS( i_ipd) BEGIN IF (i_ipd = '0') THEN o_tmp <= '0'; obar_tmp <= '1'; ELSE IF (i_ipd = '1') THEN o_tmp <= '1'; obar_tmp <= '0'; ELSE o_tmp <= i_ipd; obar_tmp <= i_ipd; END IF; END IF; END PROCESS; --------------------- -- Path Delay Section ---------------------- PROCESS( o_tmp,obar_tmp) variable o_VitalGlitchData : VitalGlitchDataType; variable obar_VitalGlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => o, OutSignalName => "o", OutTemp => o_tmp, Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)), GlitchData => o_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); VitalPathDelay01 ( OutSignal => obar, OutSignalName => "obar", OutTemp => obar_tmp, Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)), GlitchData => obar_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); END PROCESS; END arch; -------------------------------------------------------------- -- -- Entity Name : hardcopyiii_bias_logic -- -- Description : HARDCOPYIII Bias Block's Logic Block -- VHDL simulation model -- -------------------------------------------------------------- LIBRARY IEEE; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use IEEE.std_logic_1164.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_bias_logic IS GENERIC ( tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_shiftnld : VitalDelayType01 := DefPropDelay01; tipd_captnupdt : VitalDelayType01 := DefPropDelay01; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks ); PORT ( clk : in std_logic := '0'; shiftnld : in std_logic := '0'; captnupdt : in std_logic := '0'; mainclk : out std_logic := '0'; updateclk : out std_logic := '0'; capture : out std_logic := '0'; update : out std_logic := '0' ); attribute VITAL_LEVEL0 of hardcopyiii_bias_logic : ENTITY IS TRUE; end hardcopyiii_bias_logic; ARCHITECTURE vital_bias_logic of hardcopyiii_bias_logic IS attribute VITAL_LEVEL0 of vital_bias_logic : ARCHITECTURE IS TRUE; signal clk_ipd : std_logic := '0'; signal shiftnld_ipd : std_logic := '0'; signal captnupdt_ipd : std_logic := '0'; begin WireDelay : block begin VitalWireDelay (clk_ipd, clk, tipd_clk); VitalWireDelay (shiftnld_ipd, shiftnld, tipd_shiftnld); VitalWireDelay (captnupdt_ipd, captnupdt, tipd_captnupdt); end block; process (clk_ipd, shiftnld_ipd, captnupdt_ipd) variable select_tmp : std_logic_vector(1 DOWNTO 0) := (others => '0'); begin select_tmp := captnupdt_ipd & shiftnld_ipd; case select_tmp IS when "10"|"11" => mainclk <= '0'; updateclk <= clk_ipd; capture <= '1'; update <= '0'; when "01" => mainclk <= '0'; updateclk <= clk_ipd; capture <= '0'; update <= '0'; when "00" => mainclk <= clk_ipd; updateclk <= '0'; capture <= '0'; update <= '1'; when others => mainclk <= '0'; updateclk <= '0'; capture <= '0'; update <= '0'; end case; end process; end vital_bias_logic; -------------------------------------------------------------- -- -- Entity Name : hardcopyiii_bias_generator -- -- Description : HARDCOPYIII Bias Generator VHDL simulation model -- -------------------------------------------------------------- LIBRARY IEEE; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use IEEE.std_logic_1164.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_bias_generator IS GENERIC ( tipd_din : VitalDelayType01 := DefPropDelay01; tipd_mainclk : VitalDelayType01 := DefPropDelay01; tipd_updateclk : VitalDelayType01 := DefPropDelay01; tipd_update : VitalDelayType01 := DefPropDelay01; tipd_capture : VitalDelayType01 := DefPropDelay01; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks ); PORT ( din : in std_logic := '0'; mainclk : in std_logic := '0'; updateclk : in std_logic := '0'; capture : in std_logic := '0'; update : in std_logic := '0'; dout : out std_logic := '0' ); attribute VITAL_LEVEL0 of hardcopyiii_bias_generator : ENTITY IS TRUE; end hardcopyiii_bias_generator; ARCHITECTURE vital_bias_generator of hardcopyiii_bias_generator IS attribute VITAL_LEVEL0 of vital_bias_generator : ARCHITECTURE IS TRUE; CONSTANT TOTAL_REG : integer := 100; signal din_ipd : std_logic := '0'; signal mainclk_ipd : std_logic := '0'; signal updateclk_ipd : std_logic := '0'; signal update_ipd : std_logic := '0'; signal capture_ipd : std_logic := '0'; signal generator_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0'); signal update_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0'); signal dout_tmp : std_logic := '0'; signal i : integer := 0; begin WireDelay : block begin VitalWireDelay (din_ipd, din, tipd_din); VitalWireDelay (mainclk_ipd, mainclk, tipd_mainclk); VitalWireDelay (updateclk_ipd, updateclk, tipd_updateclk); VitalWireDelay (update_ipd, update, tipd_update); VitalWireDelay (capture_ipd, capture, tipd_capture); end block; process (mainclk_ipd) begin if (mainclk_ipd'event AND (mainclk_ipd = '1') AND (mainclk_ipd'last_value = '0')) then if ((capture_ipd = '0') AND (update_ipd = '1')) then for i in 0 to (TOTAL_REG - 1) loop generator_reg(i) <= update_reg(i); end loop; end if; end if; end process; process (updateclk_ipd) begin if (updateclk_ipd'event AND (updateclk_ipd = '1') AND (updateclk_ipd'last_value = '0')) then dout_tmp <= update_reg(TOTAL_REG - 1); if ((capture_ipd = '0') AND (update_ipd = '0')) then for i in 1 to (TOTAL_REG - 1) loop update_reg(i) <= update_reg(i - 1); end loop; update_reg(0) <= din_ipd; elsif ((capture_ipd = '1') AND (update_ipd = '0')) then for i in 1 to (TOTAL_REG - 1) loop update_reg(i) <= generator_reg(i); end loop; end if; end if; end process; dout <= dout_tmp; end vital_bias_generator; -------------------------------------------------------------- -- -- Entity Name : hardcopyiii_bias_block -- -- Description : HARDCOPYIII Bias Block VHDL simulation model -- -------------------------------------------------------------- LIBRARY IEEE; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use IEEE.std_logic_1164.all; use work.hardcopyiii_atom_pack.all; ENTITY hardcopyiii_bias_block IS GENERIC ( lpm_type : string := "hardcopyiii_bias_block"; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_shiftnld : VitalDelayType01 := DefPropDelay01; tipd_captnupdt : VitalDelayType01 := DefPropDelay01; tipd_din : VitalDelayType01 := DefPropDelay01; tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks ); PORT ( clk : in std_logic := '0'; shiftnld : in std_logic := '0'; captnupdt : in std_logic := '0'; din : in std_logic := '0'; dout : out std_logic := '0' ); attribute VITAL_LEVEL0 of hardcopyiii_bias_block : ENTITY IS TRUE; end hardcopyiii_bias_block; ARCHITECTURE vital_bias_block of hardcopyiii_bias_block IS COMPONENT hardcopyiii_bias_logic GENERIC ( tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_shiftnld : VitalDelayType01 := DefPropDelay01; tipd_captnupdt : VitalDelayType01 := DefPropDelay01; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks ); PORT ( clk : in std_logic := '0'; shiftnld : in std_logic := '0'; captnupdt : in std_logic := '0'; mainclk : out std_logic := '0'; updateclk : out std_logic := '0'; capture : out std_logic := '0'; update : out std_logic := '0' ); end COMPONENT; COMPONENT hardcopyiii_bias_generator GENERIC ( tipd_din : VitalDelayType01 := DefPropDelay01; tipd_mainclk : VitalDelayType01 := DefPropDelay01; tipd_updateclk : VitalDelayType01 := DefPropDelay01; tipd_update : VitalDelayType01 := DefPropDelay01; tipd_capture : VitalDelayType01 := DefPropDelay01; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks ); PORT ( din : in std_logic := '0'; mainclk : in std_logic := '0'; updateclk : in std_logic := '0'; capture : in std_logic := '0'; update : in std_logic := '0'; dout : out std_logic := '0' ); end COMPONENT; signal mainclk_wire : std_logic := '0'; signal updateclk_wire : std_logic := '0'; signal capture_wire : std_logic := '0'; signal update_wire : std_logic := '0'; begin logic_block : hardcopyiii_bias_logic PORT MAP ( clk => clk, shiftnld => shiftnld, captnupdt => captnupdt, mainclk => mainclk_wire, updateclk => updateclk_wire, capture => capture_wire, update => update_wire ); bias_generator : hardcopyiii_bias_generator PORT MAP ( din => din, mainclk => mainclk_wire, updateclk => updateclk_wire, capture => capture_wire, update => update_wire, dout => dout ); end vital_bias_block; ------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_tsdblock -- -- Description : HARDCOPYIII TSDBLOCK VHDL Simulation model -- ------------------------------------------------------------------- LIBRARY IEEE; use IEEE.std_logic_1164.all; use work.hardcopyiii_atom_pack.all; entity hardcopyiii_tsdblock is generic ( poi_cal_temperature : integer := 85; clock_divider_enable : string := "on"; clock_divider_value : integer := 40; sim_tsdcalo : integer := 0; user_offset_enable : string := "off"; lpm_type : string := "hardcopyiii_tsdblock" ); port ( offset : in std_logic_vector(5 downto 0) := (OTHERS => '0'); clk : in std_logic := '0'; ce : in std_logic := '0'; clr : in std_logic := '0'; testin : in std_logic_vector(7 downto 0) := (OTHERS => '0'); tsdcalo : out std_logic_vector(7 downto 0); tsdcaldone : out std_logic; fdbkctrlfromcore : in std_logic := '0'; compouttest : in std_logic := '0'; tsdcompout : out std_logic; offsetout : out std_logic_vector(5 downto 0) ); end hardcopyiii_tsdblock; architecture architecture_tsdblock of hardcopyiii_tsdblock is begin end architecture_tsdblock; -- end of hardcopyiii_tsdblock ------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_jtag -- -- Description : Hcx JTAG VHDL Simulation model -- ------------------------------------------------------------------- LIBRARY IEEE; use IEEE.std_logic_1164.all; use work.hardcopyiii_atom_pack.all; entity hardcopyiii_jtag is generic ( lpm_type : string := "hardcopyiii_jtag" ); port ( tms : in std_logic := '0'; tck : in std_logic := '0'; tdi : in std_logic := '0'; ntrst : in std_logic := '0'; tdoutap : in std_logic := '0'; tdouser : in std_logic := '0'; tdo: out std_logic; tmsutap: out std_logic; tckutap: out std_logic; tdiutap: out std_logic; shiftuser: out std_logic; clkdruser: out std_logic; updateuser: out std_logic; runidleuser: out std_logic; usr1user: out std_logic ); end hardcopyiii_jtag; architecture architecture_jtag of hardcopyiii_jtag is begin end architecture_jtag; --------------------------------------------------------------------- -- -- Entity Name : hardcopyiii_lcell_hsadder -- -- Description : HARDCOPYIII LCELL_HSADDER VHDL simulation model -- -- --------------------------------------------------------------------- LIBRARY IEEE; use IEEE.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; use work.hardcopyiii_atom_pack.all; entity hardcopyiii_lcell_hsadder is generic ( dataa_width : integer := 2; datab_width : integer := 2; cin_inverted : string := "off"; lpm_type : string := "hardcopyiii_lcell_hsadder"; TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; InstancePath: STRING := "*"; tpd_dataa_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01); tpd_datab_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01); tpd_cin_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01); tpd_dataa_cout : VitalDelayType01 := DefPropDelay01; tpd_datab_cout : VitalDelayType01 := DefPropDelay01; tpd_cin_cout : VitalDelayType01 := DefPropDelay01; tipd_dataa : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01); tipd_datab : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01); tipd_cin : VitalDelayType01 := DefPropDelay01 ); port ( dataa : in std_logic_vector(dataa_width - 1 downto 0) := (OTHERS => '0'); datab : in std_logic_vector(datab_width - 1 downto 0) := (OTHERS => '0'); cin : in std_logic := '0'; sumout: out std_logic_vector((calc_sum_len(dataa_width, datab_width)) - 2 downto 0); cout : out std_logic ); --attribute VITAL_LEVEL0 of hardcopyiii_lcell_hsadder : entity is TRUE; end hardcopyiii_lcell_hsadder; architecture vital_lcell_hsadder of hardcopyiii_lcell_hsadder is -- attribute VITAL_LEVEL0 of vital_lcell_hsadder : architecture is TRUE; constant sumout_width : integer := calc_sum_len(dataa_width, datab_width); signal dataa_ipd : std_logic_vector(dataa_width - 1 downto 0); signal datab_ipd : std_logic_vector(datab_width - 1 downto 0); signal cin_ipd : std_logic := '0'; signal idataa_ipd : std_logic_vector(sumout_width - 1 downto 0); signal idatab_ipd : std_logic_vector(sumout_width - 1 downto 0); -- internal signal signal cin_sel : std_logic; -- output signal signal sumout_tmp : std_logic_vector(sumout_width - 1 DOWNTO 0) := (OTHERS => '0'); begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin loopa : FOR i in dataa'RANGE GENERATE VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i)); END GENERATE; loopb : FOR i in datab'RANGE GENERATE VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i)); END GENERATE; VitalWireDelay (cin_ipd, cin, tipd_cin); end block; idataa_ipd <= ('0' & dataa_ipd); idatab_ipd <= ('0' & datab_ipd); cin_sel <= (NOT cin_ipd) WHEN cin_inverted = "on" ELSE cin_ipd; sumout_tmp <= (idataa_ipd + idatab_ipd + 1) WHEN cin_sel = '1' ELSE (idataa_ipd + idatab_ipd); ------------------------ -- Timing Check Section ------------------------ ---------------------- -- Path Delay Section ---------------------- PathDelay : block begin do1 : for i in sumout'RANGE generate process(sumout_tmp(i)) VARIABLE sumout_VitalGlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => sumout(i), OutSignalName => "sumout", OutTemp => sumout_tmp(i), Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout(i), TRUE), 1 => (datab_ipd'last_event, tpd_datab_sumout(i), TRUE), 2 => (cin_ipd'last_event, tpd_cin_sumout(i), TRUE)) , GlitchData => sumout_VitalGlitchData, Mode => DefGlitchMode, MsgOn => FALSE, XOn => TRUE ); end process; end generate do1; process(sumout_tmp(sumout_width - 1)) VARIABLE cout_VitalGlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => cout, OutSignalName => "cout", OutTemp => sumout_tmp(sumout_width - 1), Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout,TRUE), 1 => (datab_ipd'last_event, tpd_datab_cout,TRUE), 2 => (cin_ipd'last_event, tpd_cin_cout,TRUE)) , GlitchData => cout_VitalGlitchData, Mode => DefGlitchMode, MsgOn => FALSE, XOn => TRUE ); end process; end block; end vital_lcell_hsadder; --------------------------------------------------------------------------------------- -- -- Entity Name: hardcopyiii_otp -- -- Description: VHDL Simulation model for HARDCOPYIII OTP (One Time Programmable) -- --------------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; LIBRARY STD; USE STD.textio.ALL; USE work.hardcopyiii_atom_pack.all; USE IEEE.VITAL_Timing.all; USE IEEE.VITAL_Primitives.all; ENTITY hardcopyiii_otp IS GENERIC ( -- generic control parameters -- MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; TimingChecksOn : Boolean := True; tipd_otpclken : VitalDelayType01 := DefpropDelay01; tipd_otpclk : VitalDelayType01 := DefpropDelay01; tipd_otpshiftnld : VitalDelayType01 := DefpropDelay01; tpd_otpshiftnld_otpdout : VitalDelayType01 := DefpropDelay01; tsetup_otpshiftnld_otpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_otpshiftnld_otpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; data_width : INTEGER := 128; init_data : STD_LOGIC_VECTOR(127 DOWNTO 0) := (OTHERS => '0'); init_file : STRING := "init_file.hex"; lpm_type : STRING := "hardcopyiii_otp"; lpm_hint : STRING := "true" ); ---------- PORT DECLARATIONS --------- PORT ( otpclken : IN STD_LOGIC := '1'; otpclk : IN STD_LOGIC := '0'; otpshiftnld : IN STD_LOGIC := '0'; otpdout : OUT STD_LOGIC ); END hardcopyiii_otp; ARCHITECTURE arch OF hardcopyiii_otp IS SIGNAL otpclken_ipd : STD_LOGIC := '1'; SIGNAL otpclk_ipd : STD_LOGIC := '0'; SIGNAL otpshiftnld_ipd : STD_LOGIC := '0'; SIGNAL otpdout_tmp : STD_LOGIC := '0'; SIGNAL viol_notifier : STD_LOGIC; SIGNAL reset : STD_LOGIC; SIGNAL prev_loc : INTEGER := -1; SIGNAL current_loc : INTEGER := 0; SIGNAL first_use : STD_LOGIC := '1'; BEGIN ------------------------ -- Wire Delay Block -- ------------------------ WireDelay : BLOCK BEGIN VitalWireDelay (otpclken_ipd, otpclken, tipd_otpclken); VitalWireDelay (otpclk_ipd, otpclk, tipd_otpclk); VitalWireDelay (otpshiftnld_ipd, otpshiftnld, tipd_otpshiftnld); END BLOCK; --------------------------- -- Timing check section -- --------------------------- TimingChecks: PROCESS(otpclk_ipd, otpshiftnld_ipd) VARIABLE Tviol_otpshiftnld_otpclk : STD_ULOGIC := '0'; VARIABLE TimingData_otpshiftnld_otpclk : VitalTimingDataType:= VitalTimingDataInit; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => otpshiftnld_ipd, TestSignalName => "otpshiftnld", RefSignal => otpclk_ipd, RefSignalName => "otpclk", SetupHigh => tsetup_otpshiftnld_otpclk_noedge_posedge, SetupLow => tsetup_otpshiftnld_otpclk_noedge_posedge, HoldHigh => thold_otpshiftnld_otpclk_noedge_posedge, HoldLow => thold_otpshiftnld_otpclk_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => "/hardcopyiii_otp", TimingData => TimingData_otpshiftnld_otpclk, Violation => Tviol_otpshiftnld_otpclk ); END IF; END PROCESS TimingChecks; ---------------------------- -- Functionality Section -- ---------------------------- PROCESS(prev_loc) BEGIN current_loc <= prev_loc + 1; END PROCESS; PROCESS(otpclk_ipd) BEGIN IF (otpclk_ipd'EVENT and otpclk_ipd = '1') THEN -- operation only if clock enable is high IF (otpclken_ipd = '1') THEN -- shift data IF (otpshiftnld_ipd = '1' AND first_use = '0') THEN -- shifting out '0' if otpclken and otpshiftnld is high beyond 128 clock cycles IF (prev_loc = 127) THEN otpdout_tmp <= '0'; -- shifting the data bit by bit ELSE otpdout_tmp <= init_data(current_loc); prev_loc <= current_loc; END IF; -- load data ELSIF (otpshiftnld_ipd = '0') THEN otpdout_tmp <= init_data(0); first_use <= '0'; prev_loc <= 0; END IF; END IF; END IF; END PROCESS; ------------------------- -- Path Delay Section -- ------------------------- PathDelay : BLOCK BEGIN PROCESS(otpdout_tmp) VARIABLE otpdout_VitalGlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => otpdout, OutSignalName => "otpdout", OutTemp => otpdout_tmp, Paths => ( 0 => (otpshiftnld_ipd'last_event, tpd_otpshiftnld_otpdout, TRUE)), GlitchData => otpdout_VitalGlitchData, Mode => DefGlitchMode, XOn => XOn, MsgOn => MsgOn ); END PROCESS; END BLOCK; END arch;
entity test_inst is generic( G_ROUND : natural := 0; G_ROUND_ENABLE : boolean := false ); port( i_value : in bit_vector(7 downto 0); o_ena : out bit; o_value : out bit_vector(7 downto 0) ); end test_inst; architecture rtl of test_inst is begin o_ena <='1' when G_ROUND_ENABLE else '0'; o_value <=(others=>'1') when G_ROUND=1 and G_ROUND_ENABLE else not i_value; end architecture rtl; entity issue153 is end entity issue153; architecture beh of issue153 is constant G_ROUND_ENABLE:boolean:=true; constant C_ADDROUND : bit_vector(7 downto 0):="00001111"; constant C_ZERO8 : bit_vector(7 downto 0):=(others=>'0'); signal s_ena:bit_vector(7 downto 0); type T_IN_DATA is array(integer range<>) of bit_vector(7 downto 0); --signal s_value: T_IN_DATA(7 downto -1);-- this should work anyway, uncomment this to compare with ghdl for bug 2 signal s_value: T_IN_DATA(7 downto 0);--this is for bug 1, nvc should report error begin GEN_MACS_V : for v in 0 to 7 generate signal C :bit_vector(7 downto 0); signal D :bit_vector(7 downto 0); begin --should fail here, but doesn't --GHDL failed here with "bound check failure" -- ghdl drives correct values on each instances, nvc doesn't C <= C_ADDROUND when v=0 and G_ROUND_ENABLE else s_value(v-1);--bug 1 -- below is workaround, but I am lazy enough to not use it :)))) --c_gen: if v=0 and G_ROUND_ENABLE generate -- C <= C_ADDROUND; --end generate c_gen; --nc_gen: if v>0 generate -- C <= s_value(v-1); --end generate nc_gen; test_i : entity work.test_inst generic map( G_ROUND => 1 ) port map( i_value => C, o_ena => s_ena(v), o_value => s_value(v) ); end generate GEN_MACS_V; process begin wait for 1 ns; assert s_value(0) = not C_ADDROUND; assert s_value(1) = C_ADDROUND; wait; end process; end architecture;
entity test_inst is generic( G_ROUND : natural := 0; G_ROUND_ENABLE : boolean := false ); port( i_value : in bit_vector(7 downto 0); o_ena : out bit; o_value : out bit_vector(7 downto 0) ); end test_inst; architecture rtl of test_inst is begin o_ena <='1' when G_ROUND_ENABLE else '0'; o_value <=(others=>'1') when G_ROUND=1 and G_ROUND_ENABLE else not i_value; end architecture rtl; entity issue153 is end entity issue153; architecture beh of issue153 is constant G_ROUND_ENABLE:boolean:=true; constant C_ADDROUND : bit_vector(7 downto 0):="00001111"; constant C_ZERO8 : bit_vector(7 downto 0):=(others=>'0'); signal s_ena:bit_vector(7 downto 0); type T_IN_DATA is array(integer range<>) of bit_vector(7 downto 0); --signal s_value: T_IN_DATA(7 downto -1);-- this should work anyway, uncomment this to compare with ghdl for bug 2 signal s_value: T_IN_DATA(7 downto 0);--this is for bug 1, nvc should report error begin GEN_MACS_V : for v in 0 to 7 generate signal C :bit_vector(7 downto 0); signal D :bit_vector(7 downto 0); begin --should fail here, but doesn't --GHDL failed here with "bound check failure" -- ghdl drives correct values on each instances, nvc doesn't C <= C_ADDROUND when v=0 and G_ROUND_ENABLE else s_value(v-1);--bug 1 -- below is workaround, but I am lazy enough to not use it :)))) --c_gen: if v=0 and G_ROUND_ENABLE generate -- C <= C_ADDROUND; --end generate c_gen; --nc_gen: if v>0 generate -- C <= s_value(v-1); --end generate nc_gen; test_i : entity work.test_inst generic map( G_ROUND => 1 ) port map( i_value => C, o_ena => s_ena(v), o_value => s_value(v) ); end generate GEN_MACS_V; process begin wait for 1 ns; assert s_value(0) = not C_ADDROUND; assert s_value(1) = C_ADDROUND; wait; end process; end architecture;
entity test_inst is generic( G_ROUND : natural := 0; G_ROUND_ENABLE : boolean := false ); port( i_value : in bit_vector(7 downto 0); o_ena : out bit; o_value : out bit_vector(7 downto 0) ); end test_inst; architecture rtl of test_inst is begin o_ena <='1' when G_ROUND_ENABLE else '0'; o_value <=(others=>'1') when G_ROUND=1 and G_ROUND_ENABLE else not i_value; end architecture rtl; entity issue153 is end entity issue153; architecture beh of issue153 is constant G_ROUND_ENABLE:boolean:=true; constant C_ADDROUND : bit_vector(7 downto 0):="00001111"; constant C_ZERO8 : bit_vector(7 downto 0):=(others=>'0'); signal s_ena:bit_vector(7 downto 0); type T_IN_DATA is array(integer range<>) of bit_vector(7 downto 0); --signal s_value: T_IN_DATA(7 downto -1);-- this should work anyway, uncomment this to compare with ghdl for bug 2 signal s_value: T_IN_DATA(7 downto 0);--this is for bug 1, nvc should report error begin GEN_MACS_V : for v in 0 to 7 generate signal C :bit_vector(7 downto 0); signal D :bit_vector(7 downto 0); begin --should fail here, but doesn't --GHDL failed here with "bound check failure" -- ghdl drives correct values on each instances, nvc doesn't C <= C_ADDROUND when v=0 and G_ROUND_ENABLE else s_value(v-1);--bug 1 -- below is workaround, but I am lazy enough to not use it :)))) --c_gen: if v=0 and G_ROUND_ENABLE generate -- C <= C_ADDROUND; --end generate c_gen; --nc_gen: if v>0 generate -- C <= s_value(v-1); --end generate nc_gen; test_i : entity work.test_inst generic map( G_ROUND => 1 ) port map( i_value => C, o_ena => s_ena(v), o_value => s_value(v) ); end generate GEN_MACS_V; process begin wait for 1 ns; assert s_value(0) = not C_ADDROUND; assert s_value(1) = C_ADDROUND; wait; end process; end architecture;
entity test_inst is generic( G_ROUND : natural := 0; G_ROUND_ENABLE : boolean := false ); port( i_value : in bit_vector(7 downto 0); o_ena : out bit; o_value : out bit_vector(7 downto 0) ); end test_inst; architecture rtl of test_inst is begin o_ena <='1' when G_ROUND_ENABLE else '0'; o_value <=(others=>'1') when G_ROUND=1 and G_ROUND_ENABLE else not i_value; end architecture rtl; entity issue153 is end entity issue153; architecture beh of issue153 is constant G_ROUND_ENABLE:boolean:=true; constant C_ADDROUND : bit_vector(7 downto 0):="00001111"; constant C_ZERO8 : bit_vector(7 downto 0):=(others=>'0'); signal s_ena:bit_vector(7 downto 0); type T_IN_DATA is array(integer range<>) of bit_vector(7 downto 0); --signal s_value: T_IN_DATA(7 downto -1);-- this should work anyway, uncomment this to compare with ghdl for bug 2 signal s_value: T_IN_DATA(7 downto 0);--this is for bug 1, nvc should report error begin GEN_MACS_V : for v in 0 to 7 generate signal C :bit_vector(7 downto 0); signal D :bit_vector(7 downto 0); begin --should fail here, but doesn't --GHDL failed here with "bound check failure" -- ghdl drives correct values on each instances, nvc doesn't C <= C_ADDROUND when v=0 and G_ROUND_ENABLE else s_value(v-1);--bug 1 -- below is workaround, but I am lazy enough to not use it :)))) --c_gen: if v=0 and G_ROUND_ENABLE generate -- C <= C_ADDROUND; --end generate c_gen; --nc_gen: if v>0 generate -- C <= s_value(v-1); --end generate nc_gen; test_i : entity work.test_inst generic map( G_ROUND => 1 ) port map( i_value => C, o_ena => s_ena(v), o_value => s_value(v) ); end generate GEN_MACS_V; process begin wait for 1 ns; assert s_value(0) = not C_ADDROUND; assert s_value(1) = C_ADDROUND; wait; end process; end architecture;
------------------------------------------------------------------------------- -- Author: Aragonés Orellana, Silvia -- García Garcia, Ruy -- Project Name: PIC -- Design Name: dma.vhd -- Module Name: dma.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dma is Port ( Clk : in STD_LOGIC; Reset : in STD_LOGIC; Databus : inout STD_LOGIC_VECTOR (7 downto 0); Address : out STD_LOGIC_VECTOR (7 downto 0); ChipSelect : out STD_LOGIC; WriteEnable : out STD_LOGIC; OutputEnable : out STD_LOGIC; Send : in STD_LOGIC; Ready : out STD_LOGIC; DMA_RQ : out STD_LOGIC; DMA_ACK : in STD_LOGIC; TX_data : out STD_LOGIC_VECTOR (7 downto 0); Valid_D : out STD_LOGIC; Ack_out : in STD_LOGIC; TX_RDY : in STD_LOGIC; RCVD_data : in STD_LOGIC_VECTOR (7 downto 0); Data_read : out STD_LOGIC; RX_Full : in STD_LOGIC; RX_empty : in STD_LOGIC); end dma; architecture Behavioral of dma is -- Declaración del componente Controlador de Bus. COMPONENT dma_bus_controller PORT( Clk : IN std_logic; Reset : IN std_logic; Send : IN std_logic; DMA_ACK : IN std_logic; RX_empty : IN std_logic; RX_Databus : IN std_logic_vector(7 downto 0); RX_Address : IN std_logic_vector(7 downto 0); RX_ChipSelect : IN std_logic; RX_WriteEnable : IN std_logic; RX_OutputEnable : IN std_logic; RX_end : IN std_logic; TX_Address : IN std_logic_vector(7 downto 0); TX_ChipSelect : IN std_logic; TX_WriteEnable : IN std_logic; TX_OutputEnable : IN std_logic; TX_ready : IN std_logic; TX_end : IN std_logic; Databus : INOUT std_logic_vector(7 downto 0); Address : OUT std_logic_vector(7 downto 0); ChipSelect : OUT std_logic; WriteEnable : OUT std_logic; OutputEnable : OUT std_logic; Ready : OUT std_logic; DMA_RQ : OUT std_logic; RX_start : OUT std_logic; TX_Databus : OUT std_logic_vector(7 downto 0); TX_start : OUT std_logic ); END COMPONENT; -- Declaración del componente Transmisor. COMPONENT dma_tx PORT( Clk : IN std_logic; Reset : IN std_logic; Databus : IN std_logic_vector(7 downto 0); Start_TX : IN std_logic; Ack_DO : IN std_logic; Address : OUT std_logic_vector(7 downto 0); ChipSelect : OUT std_logic; WriteEnable : OUT std_logic; OutputEnable : OUT std_logic; Ready_TX : OUT std_logic; End_TX : OUT std_logic; DataOut : OUT std_logic_vector(7 downto 0); Valid_DO : OUT std_logic ); END COMPONENT; -- Declaración del componente Receptor. COMPONENT dma_rx PORT( Clk : IN std_logic; Reset : IN std_logic; Start_RX : IN std_logic; DataIn : IN std_logic_vector(7 downto 0); Empty : IN std_logic; Databus : OUT std_logic_vector(7 downto 0); Address : OUT std_logic_vector(7 downto 0); ChipSelect : OUT std_logic; WriteEnable : OUT std_logic; OutputEnable : OUT std_logic; End_RX : OUT std_logic; Read_DI : OUT std_logic ); END COMPONENT; -- Buses y señales internas, procedentes del Transmisor, empleadas para la -- interconexión entre el subsistema Transmisor y el Controlador de bus. signal TX_Databus_i : std_logic_vector(7 downto 0); signal TX_Address_i : std_logic_vector(7 downto 0); signal TX_ChipSelect_i : std_logic; signal TX_WriteEnable_i : std_logic; signal TX_OutputEnable_i : std_logic; signal TX_start_i : std_logic; signal TX_ready_i : std_logic; signal TX_end_i : std_logic; -- Buses y señales internas, procedentes del Receptor, empleadas para la -- interconexión entre el subsistema Receptor y el Controlador de bus. signal RX_Databus_i : std_logic_vector(7 downto 0); signal RX_Address_i : std_logic_vector(7 downto 0); signal RX_ChipSelect_i : std_logic; signal RX_WriteEnable_i : std_logic; signal RX_OutputEnable_i : std_logic; signal RX_start_i : std_logic; signal RX_end_i : std_logic; begin -- Instancia del Controlador de Bus. bus_controller: dma_bus_controller PORT MAP( Clk => Clk, Reset => Reset, Databus => Databus, Address => Address, ChipSelect => ChipSelect, WriteEnable => WriteEnable, OutputEnable => OutputEnable, Send => Send, Ready => Ready, DMA_RQ => DMA_RQ, DMA_ACK => DMA_ACK, RX_empty => RX_empty, RX_Databus => RX_Databus_i, RX_Address => RX_Address_i, RX_ChipSelect => RX_ChipSelect_i, RX_WriteEnable => RX_WriteEnable_i, RX_OutputEnable => RX_OutputEnable_i, RX_start => RX_start_i, RX_end => RX_end_i, TX_Databus => TX_Databus_i, TX_Address => TX_Address_i, TX_ChipSelect => TX_ChipSelect_i, TX_WriteEnable => TX_WriteEnable_i, TX_OutputEnable => TX_OutputEnable_i, TX_start => TX_start_i, TX_ready => TX_ready_i, TX_end => TX_end_i ); -- Instancia del Transmisor. tx: dma_tx PORT MAP( Clk => Clk, Reset => Reset, Databus => TX_Databus_i, Address => TX_Address_i, ChipSelect => TX_ChipSelect_i, WriteEnable => TX_WriteEnable_i, OutputEnable => TX_OutputEnable_i, Start_TX => TX_start_i, Ready_TX => TX_ready_i, End_TX => TX_end_i, DataOut => TX_data, Valid_DO => Valid_D, Ack_DO => Ack_out ); -- Instancia del Receptor. rx: dma_rx PORT MAP( Clk => Clk, Reset => Reset, Databus => RX_Databus_i, Address => RX_Address_i, ChipSelect => RX_ChipSelect_i, WriteEnable => RX_WriteEnable_i, OutputEnable => RX_OutputEnable_i, Start_RX => RX_start_i, End_RX => RX_end_i, DataIn => RCVD_data, Read_DI => Data_read, Empty => RX_empty ); end Behavioral;
architecture rtl of fifo is begin process begin report "hello" severity FAILURE; report "hello" severity FAILURE; end process; end architecture rtl;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity read_data_stage is port( clk : in std_logic; reset_n : in std_logic; stall : in std_logic; -- inputs start_address : in std_logic_vector(31 downto 0); ex_w_addr : in std_logic_vector(31 downto 0); ex_w_data : in std_logic_vector(31 downto 0); ex_we : in std_logic; a_in : in std_logic_vector(31 downto 0); b_in : in std_logic_vector(31 downto 0); c_in : in std_logic_vector(31 downto 0); addr_a : in std_logic_vector(31 downto 0); addr_b : in std_logic_vector(31 downto 0); addr_c : in std_logic_vector(31 downto 0); next_pc : in std_logic_vector(31 downto 0); ubranch_in : in std_logic; cbranch_in : in std_logic; --outputs a_out : out std_logic_vector(31 downto 0); b_out : out std_logic_vector(31 downto 0); c_out : out std_logic_vector(31 downto 0); addr_a_out : out std_logic_vector(31 downto 0); addr_b_out : out std_logic_vector(31 downto 0); addr_c_out : out std_logic_vector(31 downto 0); ubranch_out : out std_logic; noop_out : out std_logic; r_addr_0 : out std_logic_vector(31 downto 0); r_addr_1 : out std_logic_vector(31 downto 0); next_pc_out : out std_logic_vector(31 downto 0) ); end entity; architecture a1 of read_data_stage is --signals signal ubranch : std_logic; signal noop : std_logic; signal a_in_fwd : std_logic_vector(31 downto 0); signal b_in_fwd : std_logic_vector(31 downto 0); --components begin --determine forwarding (change inputs before they are used) a_in_fwd <= ex_w_data when (ex_w_addr = addr_a and ex_we = '1') else a_in; b_in_fwd <= ex_w_addr when (ex_w_addr = addr_b and ex_we = '1') else b_in; --determine ubranch ubranch <= '1' when (a_in_fwd = b_in_fwd and not(next_pc = c_in) and not(ubranch_in = '1') and not(cbranch_in = '1')) else '0'; --determine noop noop <= ubranch_in or cbranch_in; --the ubranch generated above process(clk, reset_n, start_address) begin if (reset_n = '0') then --on boot noop_out <= '1'; ubranch_out <= '0'; r_addr_0 <= std_logic_vector(unsigned(start_address) + to_unsigned(4,32)); r_addr_1 <= std_logic_vector(unsigned(start_address) + to_unsigned(5,32)); elsif (rising_edge(clk)) then if(stall = '0') then ubranch_out <= ubranch; noop_out <= noop; a_out <= a_in; b_out <= b_in; c_out <= c_in; r_addr_0 <= a_in; r_addr_1 <= b_in; addr_a_out <= addr_a; addr_b_out <= addr_b; addr_c_out <= addr_c; next_pc_out <= next_pc; else --hold previous outputs on stall (automatic) end if; end if; end process; end architecture;
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; entity Shifter is port(shift_lsl :in std_logic; shift_lsr :in std_logic; shift_asr :in std_logic; shift_ror :in std_logic; shift_rrx :in std_logic; cin :in std_logic; shift_val :in std_logic_vector (4 downto 0); din :in std_logic_vector(31 downto 0); dout :out std_logic_vector(31 downto 0); cout :out std_logic; vdd :in bit; vss :in bit); end Shifter; architecture ArchiShifter of Shifter is signal res1, res2, res3, res4, res5, res6, res7 : std_logic_vector(31 downto 0):=x"00000000"; signal carryOut: std_logic; begin --LSL & LSR & ASR res1 <= din(30 downto 0) & '0' when shift_val(0)='1' and shift_lsl='1' else '0' & din(31 downto 1) when shift_val(0)='1' and (shift_lsr='1' or (shift_asr='1' and din(31)='0')) else '1' & din(31 downto 1) when shift_val(0)='1' and (shift_asr='1' and din(31)='1' ) else din; res2 <= res1(29 downto 0) & "00" when shift_val(1)='1' and shift_lsl='1' else "00" & res1(31 downto 2) when shift_val(1)='1' and (shift_lsr='1' or (shift_asr='1' and din(31)='0')) else "11" & res1(31 downto 2) when shift_val(1)='1' and (shift_asr='1'and din(31)='1' ) else res1; res3 <= res2(27 downto 0) & x"0" when shift_val(2)='1' and shift_lsl='1' else x"0" & res2(31 downto 4) when shift_val(2)='1' and (shift_lsr='1' or (shift_asr='1' and din(31)='0')) else x"F" & res2(31 downto 4) when shift_val(2)='1' and (shift_asr='1'and din(31)='1' ) else res2; res4 <= res3(23 downto 0) & x"00" when shift_val(3)='1' and shift_lsl='1' else x"00" & res3(31 downto 8) when shift_val(3)='1' and (shift_lsr='1' or (shift_asr='1' and din(31)='0')) else x"FF" & res3(31 downto 8) when shift_val(3)='1' and (shift_asr='1' and din(31)='1' ) else res3; res5 <= res4(15 downto 0) & x"0000" when shift_val(4)='1' and shift_lsl='1' else x"0000" & res4(31 downto 16) when shift_val(4)='1' and (shift_lsr='1' or (shift_asr='1' and din(31)='0')) else x"FFFF" & res4(31 downto 16) when shift_val(4)='1' and (shift_asr='1' and din(31)='1' ) else res4; carryOut <= din(32-to_integer(unsigned(shift_val))) when shift_val /="00000" and shift_lsl='1' else din(to_integer(unsigned(shift_val))-1) when shift_val /="00000" and (shift_lsr='1' or shift_asr='1' or shift_ror='1') else din(0) when shift_rrx='1' else cin; --RRX res6 <= cin & din(31 downto 1) when shift_rrx='1' else din; --ROR res7(31 downto (32-to_integer(unsigned(shift_val)))) <= din((to_integer(unsigned(shift_val))-1) downto 0) when shift_ror='1' and shift_val /="00000" else din; res7((31-to_integer(unsigned(shift_val))) downto 0) <= din(31 downto to_integer(unsigned(shift_val))) when shift_ror='1' and shift_val /="00000" else din; dout <= res5 when shift_lsl='1' or shift_asr='1' or shift_lsr='1' else res6 when shift_rrx='1' else res7 when shift_ror='1' else din; cout <= carryOut; end ArchiShifter;
---------------------------------------------------------------------------------- -- Module Name: tb_transceiver_test - Behavioral -- -- Description: A testbench for the transceiver_test -- ---------------------------------------------------------------------------------- -- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort ------------------------------------------------------------------------------------ -- The MIT License (MIT) -- -- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz> -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. ------------------------------------------------------------------------------------ ----- Want to say thanks? ---------------------------------------------------------- ------------------------------------------------------------------------------------ -- -- This design has taken many hours - 3 months of work. I'm more than happy -- to share it if you can make use of it. It is released under the MIT license, -- so you are not under any onus to say thanks, but.... -- -- If you what to say thanks for this design either drop me an email, or how about -- trying PayPal to my email (hamster@snap.net.nz)? -- -- Educational use - Enough for a beer -- Hobbyist use - Enough for a pizza -- Research use - Enough to take the family out to dinner -- Commercial use - A weeks pay for an engineer (I wish!) -------------------------------------------------------------------------------------- -- Ver | Date | Change --------+------------+--------------------------------------------------------------- -- 0.1 | 2015-09-17 | Initial Version ------------------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity tb_transceiver_test is end entity; architecture arch of tb_transceiver_test is component transceiver_test is port ( clk : in std_logic; debug_pmod : out std_logic_vector(7 downto 0) := (others => '0'); switches : in std_logic_vector(7 downto 0) := (others => '0'); leds : out std_logic_vector(7 downto 0) := (others => '0'); ------------------------------ refclk0_p : in STD_LOGIC; refclk0_n : in STD_LOGIC; refclk1_p : in STD_LOGIC; refclk1_n : in STD_LOGIC; gtptxp : out std_logic; gtptxn : out std_logic; ------------------------------ dp_tx_hp_detect : in std_logic; dp_tx_aux_p : inout std_logic; dp_tx_aux_n : inout std_logic; dp_rx_aux_p : inout std_logic; dp_rx_aux_n : inout std_logic ); end component; signal clk : std_logic := '0'; signal debug_pmod : std_logic_vector(7 downto 0) := (others => '0'); signal dp_tx_aux_p : std_logic := '0'; signal dp_tx_aux_n : std_logic := '0'; signal dp_rx_aux_p : std_logic := '0'; signal dp_rx_aux_n : std_logic := '0'; signal dp_tx_hpd : std_logic := '0'; signal refclk0_p : STD_LOGIC; signal refclk0_n : STD_LOGIC; signal refclk1_p : STD_LOGIC := '1'; signal refclk1_n : STD_LOGIC := '0'; signal gtptxp : std_logic; signal gtptxn : std_logic; begin uut: transceiver_test PORT MAP ( clk => clk, switches => (others => '0'), leds => open, debug_pmod => debug_pmod, dp_tx_aux_p => dp_tx_aux_p, dp_tx_aux_n => dp_tx_aux_n, dp_rx_aux_p => dp_rx_aux_p, dp_rx_aux_n => dp_rx_aux_n, dp_tx_hp_detect => dp_tx_hpd, refclk0_p => refclk0_p, refclk0_n => refclk0_n, refclk1_p => refclk1_p, refclk1_n => refclk1_n, gtptxp => gtptxp, gtptxn => gtptxn ); process begin wait for 5 ns; clk <= '1'; wait for 5 ns; clk <= '0'; end process; process begin refclk0_p <='1'; refclk0_n <='0'; wait for 3.6 ns; refclk0_p <='0'; refclk0_n <='1'; wait for 3.6 ns; end process; end architecture;
library verilog; use verilog.vl_types.all; entity ama_preadder_function is generic( preadder_mode : string := "SIMPLE"; width_in_a : integer := 1; width_in_b : integer := 1; width_in_c : integer := 1; width_in_coef : integer := 1; width_result_a : integer := 1; width_result_b : integer := 1; preadder_direction_0: string := "ADD"; preadder_direction_1: string := "ADD"; preadder_direction_2: string := "ADD"; preadder_direction_3: string := "ADD"; representation_preadder_adder: string := "UNSIGNED"; width_in_a_msb : vl_notype; width_in_b_msb : vl_notype; width_in_c_msb : vl_notype; width_in_coef_msb: vl_notype; width_result_a_msb: vl_notype; width_result_b_msb: vl_notype; width_preadder_adder_input: vl_notype; width_preadder_adder_input_msb: vl_notype; width_preadder_adder_result: vl_notype; width_preadder_adder_result_msb: vl_notype; width_preadder_adder_input_wire: vl_notype; width_preadder_adder_input_wire_msb: vl_notype; width_in_a_ext : vl_notype; width_in_b_ext : vl_notype; width_output_preadder: vl_notype; width_output_preadder_msb: vl_notype; width_output_coef: vl_notype; width_output_coef_msb: vl_notype; width_output_datab: vl_notype; width_output_datab_msb: vl_notype; width_output_datac: vl_notype; width_output_datac_msb: vl_notype ); port( dataa_in_0 : in vl_logic_vector; dataa_in_1 : in vl_logic_vector; dataa_in_2 : in vl_logic_vector; dataa_in_3 : in vl_logic_vector; datab_in_0 : in vl_logic_vector; datab_in_1 : in vl_logic_vector; datab_in_2 : in vl_logic_vector; datab_in_3 : in vl_logic_vector; datac_in_0 : in vl_logic_vector; datac_in_1 : in vl_logic_vector; datac_in_2 : in vl_logic_vector; datac_in_3 : in vl_logic_vector; coef0 : in vl_logic_vector; coef1 : in vl_logic_vector; coef2 : in vl_logic_vector; coef3 : in vl_logic_vector; result_a0 : out vl_logic_vector; result_a1 : out vl_logic_vector; result_a2 : out vl_logic_vector; result_a3 : out vl_logic_vector; result_b0 : out vl_logic_vector; result_b1 : out vl_logic_vector; result_b2 : out vl_logic_vector; result_b3 : out vl_logic_vector ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of preadder_mode : constant is 1; attribute mti_svvh_generic_type of width_in_a : constant is 1; attribute mti_svvh_generic_type of width_in_b : constant is 1; attribute mti_svvh_generic_type of width_in_c : constant is 1; attribute mti_svvh_generic_type of width_in_coef : constant is 1; attribute mti_svvh_generic_type of width_result_a : constant is 1; attribute mti_svvh_generic_type of width_result_b : constant is 1; attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1; attribute mti_svvh_generic_type of representation_preadder_adder : constant is 1; attribute mti_svvh_generic_type of width_in_a_msb : constant is 3; attribute mti_svvh_generic_type of width_in_b_msb : constant is 3; attribute mti_svvh_generic_type of width_in_c_msb : constant is 3; attribute mti_svvh_generic_type of width_in_coef_msb : constant is 3; attribute mti_svvh_generic_type of width_result_a_msb : constant is 3; attribute mti_svvh_generic_type of width_result_b_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_result : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_result_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_wire : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_wire_msb : constant is 3; attribute mti_svvh_generic_type of width_in_a_ext : constant is 3; attribute mti_svvh_generic_type of width_in_b_ext : constant is 3; attribute mti_svvh_generic_type of width_output_preadder : constant is 3; attribute mti_svvh_generic_type of width_output_preadder_msb : constant is 3; attribute mti_svvh_generic_type of width_output_coef : constant is 3; attribute mti_svvh_generic_type of width_output_coef_msb : constant is 3; attribute mti_svvh_generic_type of width_output_datab : constant is 3; attribute mti_svvh_generic_type of width_output_datab_msb : constant is 3; attribute mti_svvh_generic_type of width_output_datac : constant is 3; attribute mti_svvh_generic_type of width_output_datac_msb : constant is 3; end ama_preadder_function;
library verilog; use verilog.vl_types.all; entity ama_preadder_function is generic( preadder_mode : string := "SIMPLE"; width_in_a : integer := 1; width_in_b : integer := 1; width_in_c : integer := 1; width_in_coef : integer := 1; width_result_a : integer := 1; width_result_b : integer := 1; preadder_direction_0: string := "ADD"; preadder_direction_1: string := "ADD"; preadder_direction_2: string := "ADD"; preadder_direction_3: string := "ADD"; representation_preadder_adder: string := "UNSIGNED"; width_in_a_msb : vl_notype; width_in_b_msb : vl_notype; width_in_c_msb : vl_notype; width_in_coef_msb: vl_notype; width_result_a_msb: vl_notype; width_result_b_msb: vl_notype; width_preadder_adder_input: vl_notype; width_preadder_adder_input_msb: vl_notype; width_preadder_adder_result: vl_notype; width_preadder_adder_result_msb: vl_notype; width_preadder_adder_input_wire: vl_notype; width_preadder_adder_input_wire_msb: vl_notype; width_in_a_ext : vl_notype; width_in_b_ext : vl_notype; width_output_preadder: vl_notype; width_output_preadder_msb: vl_notype; width_output_coef: vl_notype; width_output_coef_msb: vl_notype; width_output_datab: vl_notype; width_output_datab_msb: vl_notype; width_output_datac: vl_notype; width_output_datac_msb: vl_notype ); port( dataa_in_0 : in vl_logic_vector; dataa_in_1 : in vl_logic_vector; dataa_in_2 : in vl_logic_vector; dataa_in_3 : in vl_logic_vector; datab_in_0 : in vl_logic_vector; datab_in_1 : in vl_logic_vector; datab_in_2 : in vl_logic_vector; datab_in_3 : in vl_logic_vector; datac_in_0 : in vl_logic_vector; datac_in_1 : in vl_logic_vector; datac_in_2 : in vl_logic_vector; datac_in_3 : in vl_logic_vector; coef0 : in vl_logic_vector; coef1 : in vl_logic_vector; coef2 : in vl_logic_vector; coef3 : in vl_logic_vector; result_a0 : out vl_logic_vector; result_a1 : out vl_logic_vector; result_a2 : out vl_logic_vector; result_a3 : out vl_logic_vector; result_b0 : out vl_logic_vector; result_b1 : out vl_logic_vector; result_b2 : out vl_logic_vector; result_b3 : out vl_logic_vector ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of preadder_mode : constant is 1; attribute mti_svvh_generic_type of width_in_a : constant is 1; attribute mti_svvh_generic_type of width_in_b : constant is 1; attribute mti_svvh_generic_type of width_in_c : constant is 1; attribute mti_svvh_generic_type of width_in_coef : constant is 1; attribute mti_svvh_generic_type of width_result_a : constant is 1; attribute mti_svvh_generic_type of width_result_b : constant is 1; attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1; attribute mti_svvh_generic_type of representation_preadder_adder : constant is 1; attribute mti_svvh_generic_type of width_in_a_msb : constant is 3; attribute mti_svvh_generic_type of width_in_b_msb : constant is 3; attribute mti_svvh_generic_type of width_in_c_msb : constant is 3; attribute mti_svvh_generic_type of width_in_coef_msb : constant is 3; attribute mti_svvh_generic_type of width_result_a_msb : constant is 3; attribute mti_svvh_generic_type of width_result_b_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_result : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_result_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_wire : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_wire_msb : constant is 3; attribute mti_svvh_generic_type of width_in_a_ext : constant is 3; attribute mti_svvh_generic_type of width_in_b_ext : constant is 3; attribute mti_svvh_generic_type of width_output_preadder : constant is 3; attribute mti_svvh_generic_type of width_output_preadder_msb : constant is 3; attribute mti_svvh_generic_type of width_output_coef : constant is 3; attribute mti_svvh_generic_type of width_output_coef_msb : constant is 3; attribute mti_svvh_generic_type of width_output_datab : constant is 3; attribute mti_svvh_generic_type of width_output_datab_msb : constant is 3; attribute mti_svvh_generic_type of width_output_datac : constant is 3; attribute mti_svvh_generic_type of width_output_datac_msb : constant is 3; end ama_preadder_function;
library verilog; use verilog.vl_types.all; entity ama_preadder_function is generic( preadder_mode : string := "SIMPLE"; width_in_a : integer := 1; width_in_b : integer := 1; width_in_c : integer := 1; width_in_coef : integer := 1; width_result_a : integer := 1; width_result_b : integer := 1; preadder_direction_0: string := "ADD"; preadder_direction_1: string := "ADD"; preadder_direction_2: string := "ADD"; preadder_direction_3: string := "ADD"; representation_preadder_adder: string := "UNSIGNED"; width_in_a_msb : vl_notype; width_in_b_msb : vl_notype; width_in_c_msb : vl_notype; width_in_coef_msb: vl_notype; width_result_a_msb: vl_notype; width_result_b_msb: vl_notype; width_preadder_adder_input: vl_notype; width_preadder_adder_input_msb: vl_notype; width_preadder_adder_result: vl_notype; width_preadder_adder_result_msb: vl_notype; width_preadder_adder_input_wire: vl_notype; width_preadder_adder_input_wire_msb: vl_notype; width_in_a_ext : vl_notype; width_in_b_ext : vl_notype; width_output_preadder: vl_notype; width_output_preadder_msb: vl_notype; width_output_coef: vl_notype; width_output_coef_msb: vl_notype; width_output_datab: vl_notype; width_output_datab_msb: vl_notype; width_output_datac: vl_notype; width_output_datac_msb: vl_notype ); port( dataa_in_0 : in vl_logic_vector; dataa_in_1 : in vl_logic_vector; dataa_in_2 : in vl_logic_vector; dataa_in_3 : in vl_logic_vector; datab_in_0 : in vl_logic_vector; datab_in_1 : in vl_logic_vector; datab_in_2 : in vl_logic_vector; datab_in_3 : in vl_logic_vector; datac_in_0 : in vl_logic_vector; datac_in_1 : in vl_logic_vector; datac_in_2 : in vl_logic_vector; datac_in_3 : in vl_logic_vector; coef0 : in vl_logic_vector; coef1 : in vl_logic_vector; coef2 : in vl_logic_vector; coef3 : in vl_logic_vector; result_a0 : out vl_logic_vector; result_a1 : out vl_logic_vector; result_a2 : out vl_logic_vector; result_a3 : out vl_logic_vector; result_b0 : out vl_logic_vector; result_b1 : out vl_logic_vector; result_b2 : out vl_logic_vector; result_b3 : out vl_logic_vector ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of preadder_mode : constant is 1; attribute mti_svvh_generic_type of width_in_a : constant is 1; attribute mti_svvh_generic_type of width_in_b : constant is 1; attribute mti_svvh_generic_type of width_in_c : constant is 1; attribute mti_svvh_generic_type of width_in_coef : constant is 1; attribute mti_svvh_generic_type of width_result_a : constant is 1; attribute mti_svvh_generic_type of width_result_b : constant is 1; attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1; attribute mti_svvh_generic_type of representation_preadder_adder : constant is 1; attribute mti_svvh_generic_type of width_in_a_msb : constant is 3; attribute mti_svvh_generic_type of width_in_b_msb : constant is 3; attribute mti_svvh_generic_type of width_in_c_msb : constant is 3; attribute mti_svvh_generic_type of width_in_coef_msb : constant is 3; attribute mti_svvh_generic_type of width_result_a_msb : constant is 3; attribute mti_svvh_generic_type of width_result_b_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_result : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_result_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_wire : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_wire_msb : constant is 3; attribute mti_svvh_generic_type of width_in_a_ext : constant is 3; attribute mti_svvh_generic_type of width_in_b_ext : constant is 3; attribute mti_svvh_generic_type of width_output_preadder : constant is 3; attribute mti_svvh_generic_type of width_output_preadder_msb : constant is 3; attribute mti_svvh_generic_type of width_output_coef : constant is 3; attribute mti_svvh_generic_type of width_output_coef_msb : constant is 3; attribute mti_svvh_generic_type of width_output_datab : constant is 3; attribute mti_svvh_generic_type of width_output_datab_msb : constant is 3; attribute mti_svvh_generic_type of width_output_datac : constant is 3; attribute mti_svvh_generic_type of width_output_datac_msb : constant is 3; end ama_preadder_function;
library verilog; use verilog.vl_types.all; entity ama_preadder_function is generic( preadder_mode : string := "SIMPLE"; width_in_a : integer := 1; width_in_b : integer := 1; width_in_c : integer := 1; width_in_coef : integer := 1; width_result_a : integer := 1; width_result_b : integer := 1; preadder_direction_0: string := "ADD"; preadder_direction_1: string := "ADD"; preadder_direction_2: string := "ADD"; preadder_direction_3: string := "ADD"; representation_preadder_adder: string := "UNSIGNED"; width_in_a_msb : vl_notype; width_in_b_msb : vl_notype; width_in_c_msb : vl_notype; width_in_coef_msb: vl_notype; width_result_a_msb: vl_notype; width_result_b_msb: vl_notype; width_preadder_adder_input: vl_notype; width_preadder_adder_input_msb: vl_notype; width_preadder_adder_result: vl_notype; width_preadder_adder_result_msb: vl_notype; width_preadder_adder_input_wire: vl_notype; width_preadder_adder_input_wire_msb: vl_notype; width_in_a_ext : vl_notype; width_in_b_ext : vl_notype; width_output_preadder: vl_notype; width_output_preadder_msb: vl_notype; width_output_coef: vl_notype; width_output_coef_msb: vl_notype; width_output_datab: vl_notype; width_output_datab_msb: vl_notype; width_output_datac: vl_notype; width_output_datac_msb: vl_notype ); port( dataa_in_0 : in vl_logic_vector; dataa_in_1 : in vl_logic_vector; dataa_in_2 : in vl_logic_vector; dataa_in_3 : in vl_logic_vector; datab_in_0 : in vl_logic_vector; datab_in_1 : in vl_logic_vector; datab_in_2 : in vl_logic_vector; datab_in_3 : in vl_logic_vector; datac_in_0 : in vl_logic_vector; datac_in_1 : in vl_logic_vector; datac_in_2 : in vl_logic_vector; datac_in_3 : in vl_logic_vector; coef0 : in vl_logic_vector; coef1 : in vl_logic_vector; coef2 : in vl_logic_vector; coef3 : in vl_logic_vector; result_a0 : out vl_logic_vector; result_a1 : out vl_logic_vector; result_a2 : out vl_logic_vector; result_a3 : out vl_logic_vector; result_b0 : out vl_logic_vector; result_b1 : out vl_logic_vector; result_b2 : out vl_logic_vector; result_b3 : out vl_logic_vector ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of preadder_mode : constant is 1; attribute mti_svvh_generic_type of width_in_a : constant is 1; attribute mti_svvh_generic_type of width_in_b : constant is 1; attribute mti_svvh_generic_type of width_in_c : constant is 1; attribute mti_svvh_generic_type of width_in_coef : constant is 1; attribute mti_svvh_generic_type of width_result_a : constant is 1; attribute mti_svvh_generic_type of width_result_b : constant is 1; attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1; attribute mti_svvh_generic_type of representation_preadder_adder : constant is 1; attribute mti_svvh_generic_type of width_in_a_msb : constant is 3; attribute mti_svvh_generic_type of width_in_b_msb : constant is 3; attribute mti_svvh_generic_type of width_in_c_msb : constant is 3; attribute mti_svvh_generic_type of width_in_coef_msb : constant is 3; attribute mti_svvh_generic_type of width_result_a_msb : constant is 3; attribute mti_svvh_generic_type of width_result_b_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_result : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_result_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_wire : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_wire_msb : constant is 3; attribute mti_svvh_generic_type of width_in_a_ext : constant is 3; attribute mti_svvh_generic_type of width_in_b_ext : constant is 3; attribute mti_svvh_generic_type of width_output_preadder : constant is 3; attribute mti_svvh_generic_type of width_output_preadder_msb : constant is 3; attribute mti_svvh_generic_type of width_output_coef : constant is 3; attribute mti_svvh_generic_type of width_output_coef_msb : constant is 3; attribute mti_svvh_generic_type of width_output_datab : constant is 3; attribute mti_svvh_generic_type of width_output_datab_msb : constant is 3; attribute mti_svvh_generic_type of width_output_datac : constant is 3; attribute mti_svvh_generic_type of width_output_datac_msb : constant is 3; end ama_preadder_function;
library verilog; use verilog.vl_types.all; entity ama_preadder_function is generic( preadder_mode : string := "SIMPLE"; width_in_a : integer := 1; width_in_b : integer := 1; width_in_c : integer := 1; width_in_coef : integer := 1; width_result_a : integer := 1; width_result_b : integer := 1; preadder_direction_0: string := "ADD"; preadder_direction_1: string := "ADD"; preadder_direction_2: string := "ADD"; preadder_direction_3: string := "ADD"; representation_preadder_adder: string := "UNSIGNED"; width_in_a_msb : vl_notype; width_in_b_msb : vl_notype; width_in_c_msb : vl_notype; width_in_coef_msb: vl_notype; width_result_a_msb: vl_notype; width_result_b_msb: vl_notype; width_preadder_adder_input: vl_notype; width_preadder_adder_input_msb: vl_notype; width_preadder_adder_result: vl_notype; width_preadder_adder_result_msb: vl_notype; width_preadder_adder_input_wire: vl_notype; width_preadder_adder_input_wire_msb: vl_notype; width_in_a_ext : vl_notype; width_in_b_ext : vl_notype; width_output_preadder: vl_notype; width_output_preadder_msb: vl_notype; width_output_coef: vl_notype; width_output_coef_msb: vl_notype; width_output_datab: vl_notype; width_output_datab_msb: vl_notype; width_output_datac: vl_notype; width_output_datac_msb: vl_notype ); port( dataa_in_0 : in vl_logic_vector; dataa_in_1 : in vl_logic_vector; dataa_in_2 : in vl_logic_vector; dataa_in_3 : in vl_logic_vector; datab_in_0 : in vl_logic_vector; datab_in_1 : in vl_logic_vector; datab_in_2 : in vl_logic_vector; datab_in_3 : in vl_logic_vector; datac_in_0 : in vl_logic_vector; datac_in_1 : in vl_logic_vector; datac_in_2 : in vl_logic_vector; datac_in_3 : in vl_logic_vector; coef0 : in vl_logic_vector; coef1 : in vl_logic_vector; coef2 : in vl_logic_vector; coef3 : in vl_logic_vector; result_a0 : out vl_logic_vector; result_a1 : out vl_logic_vector; result_a2 : out vl_logic_vector; result_a3 : out vl_logic_vector; result_b0 : out vl_logic_vector; result_b1 : out vl_logic_vector; result_b2 : out vl_logic_vector; result_b3 : out vl_logic_vector ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of preadder_mode : constant is 1; attribute mti_svvh_generic_type of width_in_a : constant is 1; attribute mti_svvh_generic_type of width_in_b : constant is 1; attribute mti_svvh_generic_type of width_in_c : constant is 1; attribute mti_svvh_generic_type of width_in_coef : constant is 1; attribute mti_svvh_generic_type of width_result_a : constant is 1; attribute mti_svvh_generic_type of width_result_b : constant is 1; attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1; attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1; attribute mti_svvh_generic_type of representation_preadder_adder : constant is 1; attribute mti_svvh_generic_type of width_in_a_msb : constant is 3; attribute mti_svvh_generic_type of width_in_b_msb : constant is 3; attribute mti_svvh_generic_type of width_in_c_msb : constant is 3; attribute mti_svvh_generic_type of width_in_coef_msb : constant is 3; attribute mti_svvh_generic_type of width_result_a_msb : constant is 3; attribute mti_svvh_generic_type of width_result_b_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_result : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_result_msb : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_wire : constant is 3; attribute mti_svvh_generic_type of width_preadder_adder_input_wire_msb : constant is 3; attribute mti_svvh_generic_type of width_in_a_ext : constant is 3; attribute mti_svvh_generic_type of width_in_b_ext : constant is 3; attribute mti_svvh_generic_type of width_output_preadder : constant is 3; attribute mti_svvh_generic_type of width_output_preadder_msb : constant is 3; attribute mti_svvh_generic_type of width_output_coef : constant is 3; attribute mti_svvh_generic_type of width_output_coef_msb : constant is 3; attribute mti_svvh_generic_type of width_output_datab : constant is 3; attribute mti_svvh_generic_type of width_output_datab_msb : constant is 3; attribute mti_svvh_generic_type of width_output_datac : constant is 3; attribute mti_svvh_generic_type of width_output_datac_msb : constant is 3; end ama_preadder_function;
------------------------------------------------------------------------------- -- Company : HSLU, Waj -- Create Date: 20-Apr-12 -- Project : ECS, Uebung 2 -- Description: Combinational circuit (Enable gate) described in different -- forms ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity EnableGate is port( x : in std_ulogic_vector(3 downto 0); en : in std_ulogic; y : out std_ulogic_vector(3 downto 0) ); end EnableGate; -- concurrent signal assignment (naive) architecture A_conc_sig_ass_1 of EnableGate is begin y(0) <= x(0) and en; y(1) <= x(1) and en; y(2) <= x(2) and en; y(3) <= x(3) and en; end architecture; architecture A_conc_sig_ass_2 of EnableGate is begin y <= x and (others => en); end architecture; -- conditional signal assignment architecture A_cond_sig_ass_1 of EnableGate is begin y <= x when en = '1' else (others => '0'); end architecture; -- selected signal assignment architecture A_sel_sig_ass_1 of EnableGate is begin with en select y <= x when '1', (others => '0') when others; end architecture; -- process statement with sequential signal ass. (naive) architecture A_proc_seq_sig_ass_1 of EnableGate is begin process(x, en) begin y(0) <= x(0) and en; y(1) <= x(1) and en; y(2) <= x(2) and en; y(3) <= x(3) and en; end process; end architecture;
-- file: dcm75MHz.vhd -- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------ -- User entered comments ------------------------------------------------------------------------------ -- None -- ------------------------------------------------------------------------------ -- "Output Output Phase Duty Pk-to-Pk Phase" -- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" ------------------------------------------------------------------------------ -- CLK_OUT1____75.000______0.000______50.0______466.666____150.000 -- ------------------------------------------------------------------------------ -- "Input Clock Freq (MHz) Input Jitter (UI)" ------------------------------------------------------------------------------ -- __primary______________27____________0.010 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity dcm75MHz is port (-- Clock in ports CLK_IN1 : in std_logic; -- Clock out ports CLK_OUT1 : out std_logic; -- Status and control signals RESET : in std_logic; LOCKED : out std_logic ); end dcm75MHz; architecture xilinx of dcm75MHz is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm75MHz,clk_wiz_v3_6,{component_name=dcm75MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=37.037,clkin2_period=37.037,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"; -- Input clock buffering / unused connectors signal clkin1 : std_logic; -- Output clock buffering signal clkfb : std_logic; signal clk0 : std_logic; signal clkfx : std_logic; signal clkfbout : std_logic; signal locked_internal : std_logic; signal status_internal : std_logic_vector(7 downto 0); begin -- Input buffering -------------------------------------- clkin1_buf : IBUFG port map (O => clkin1, I => CLK_IN1); -- Clocking primitive -------------------------------------- -- Instantiation of the DCM primitive -- * Unused inputs are tied off -- * Unused outputs are labeled unused dcm_sp_inst: DCM_SP generic map (CLKDV_DIVIDE => 2.000, CLKFX_DIVIDE => 9, CLKFX_MULTIPLY => 25, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 37.037, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "1X", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map -- Input clock (CLKIN => clkin1, CLKFB => clkfb, -- Output clocks CLK0 => clk0, CLK90 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLKFX => clkfx, CLKFX180 => open, CLKDV => open, -- Ports for dynamic phase shift PSCLK => '0', PSEN => '0', PSINCDEC => '0', PSDONE => open, -- Other control and status signals LOCKED => locked_internal, STATUS => status_internal, RST => RESET, -- Unused pin, tie low DSSEN => '0'); LOCKED <= locked_internal; -- Output buffering ------------------------------------- clkf_buf : BUFG port map (O => clkfb, I => clk0); clkout1_buf : BUFG port map (O => CLK_OUT1, I => clkfx); end xilinx;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity inline_13 is end entity inline_13; ---------------------------------------------------------------- architecture test of inline_13 is begin process_3_b : process is -- code from book: type array1 is array (1 to 100) of integer; type array2 is array (100 downto 1) of integer; variable a1 : array1; variable a2 : array2; -- end of code from book begin a1(11 to 20) := a1(11 to 20); a2(50 downto 41) := a2(50 downto 41); a1(10 to 1) := a1(10 to 1); a2(1 downto 10) := a2(1 downto 10); a1(10 downto 1) := a1(10 downto 1); -- illegal a2(1 to 10) := a2(1 to 10); -- illegal; wait; end process process_3_b; end architecture test;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity inline_13 is end entity inline_13; ---------------------------------------------------------------- architecture test of inline_13 is begin process_3_b : process is -- code from book: type array1 is array (1 to 100) of integer; type array2 is array (100 downto 1) of integer; variable a1 : array1; variable a2 : array2; -- end of code from book begin a1(11 to 20) := a1(11 to 20); a2(50 downto 41) := a2(50 downto 41); a1(10 to 1) := a1(10 to 1); a2(1 downto 10) := a2(1 downto 10); a1(10 downto 1) := a1(10 downto 1); -- illegal a2(1 to 10) := a2(1 to 10); -- illegal; wait; end process process_3_b; end architecture test;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity inline_13 is end entity inline_13; ---------------------------------------------------------------- architecture test of inline_13 is begin process_3_b : process is -- code from book: type array1 is array (1 to 100) of integer; type array2 is array (100 downto 1) of integer; variable a1 : array1; variable a2 : array2; -- end of code from book begin a1(11 to 20) := a1(11 to 20); a2(50 downto 41) := a2(50 downto 41); a1(10 to 1) := a1(10 to 1); a2(1 downto 10) := a2(1 downto 10); a1(10 downto 1) := a1(10 downto 1); -- illegal a2(1 to 10) := a2(1 to 10); -- illegal; wait; end process process_3_b; end architecture test;
------------------------------------------------------- --! @author Andrew Powell --! @date March 16, 2017 --! @brief Contains the entity and architecture of the --! Crossbar's Write Controller. ------------------------------------------------------- library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use ieee.numeric_std.all; use work.plasoc_crossbar_pack.all; entity plasoc_crossbar_axi4_write_cntrl is generic ( axi_slave_amount : integer := 2; axi_master_amount : integer := 4); port ( aclk : in std_logic; aresetn : in std_logic; axi_write_master_iden : in std_logic_vector(axi_slave_amount*clogb2(axi_master_amount)-1 downto 0); axi_write_slave_iden : in std_logic_vector(axi_master_amount*clogb2(axi_slave_amount)-1 downto 0); axi_address_write_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0); axi_data_write_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0); axi_response_write_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0); s_axi_awvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0); s_axi_wvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0); s_axi_wlast : in std_logic_vector(axi_slave_amount*1-1 downto 0); s_axi_bready : in std_logic_vector(axi_slave_amount*1-1 downto 0); m_axi_awready : in std_logic_vector(axi_master_amount*1-1 downto 0); m_axi_wready : in std_logic_vector(axi_master_amount*1-1 downto 0); m_axi_bvalid : in std_logic_vector(axi_master_amount*1-1 downto 0)); end plasoc_crossbar_axi4_write_cntrl; architecture Behavioral of plasoc_crossbar_axi4_write_cntrl is constant axi_slave_iden_width : integer := clogb2(axi_slave_amount); constant axi_master_iden_width : integer := clogb2(axi_master_amount); function reduce_enables_master( enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return std_logic_vector is variable or_reduced : std_logic; variable reduce_enables : std_logic_vector(axi_master_amount-1 downto 0); begin for each_master in 0 to axi_master_amount-1 loop or_reduced := '0'; for each_slave in 0 to axi_slave_amount-1 loop or_reduced := or_reduced or enables(each_slave+each_master*axi_slave_amount); end loop; reduce_enables(each_master) := or_reduced; end loop; return reduce_enables; end; function get_slave_handshakes ( valid : in std_logic_vector(axi_slave_amount-1 downto 0); ready : in std_logic_vector(axi_master_amount-1 downto 0); master_iden : in std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0) ) return std_logic_vector is variable master_iden_buff : integer range 0 to axi_master_amount-1; variable slave_handshakes : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0'); begin for each_slave in 0 to axi_slave_amount-1 loop master_iden_buff := to_integer(unsigned(master_iden((1+each_slave)*axi_master_iden_width-1 downto each_slave*axi_master_iden_width))); if valid(each_slave)='1' and ready(master_iden_buff)='1' then slave_handshakes(each_slave) := '1'; end if; end loop; return slave_handshakes; end; function get_slave_permissions ( slave_valid : in std_logic_vector(axi_slave_amount-1 downto 0); master_iden : in std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0); reduced_data_enables : in std_logic_vector(axi_master_amount-1 downto 0) ) return std_logic_vector is variable master_iden_buff : integer range 0 to axi_master_amount-1; variable slave_permissions : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0'); begin for each_master in 0 to axi_master_amount-1 loop for each_slave in 0 to axi_slave_amount-1 loop master_iden_buff := to_integer(unsigned(master_iden((1+each_slave)*axi_master_iden_width-1 downto each_slave*axi_master_iden_width))); if each_master=master_iden_buff and slave_valid(each_slave)='1' and reduced_data_enables(master_iden_buff)='0' then slave_permissions(each_slave) := '1'; exit; end if; end loop; end loop; return slave_permissions; end; function set_slave_enables_ff( slave_permissions : in std_logic_vector(axi_slave_amount-1 downto 0); slave_handshakes : in std_logic_vector(axi_slave_amount-1 downto 0); slave_last : in std_logic_vector(axi_slave_amount-1 downto 0); master_iden : in std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0); slave_enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return std_logic_vector is variable master_iden_buff : integer range 0 to axi_master_amount-1; variable slave_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0); begin slave_enables_buff := slave_enables; for each_slave in 0 to axi_slave_amount-1 loop master_iden_buff := to_integer(unsigned(master_iden((1+each_slave)*axi_master_iden_width-1 downto each_slave*axi_master_iden_width))); if slave_permissions(each_slave)='1' then slave_enables_buff(each_slave+master_iden_buff*axi_slave_amount) := '1'; elsif slave_handshakes(each_slave)='1' and slave_last(each_slave)='1' then for each_master in 0 to axi_master_amount-1 loop slave_enables_buff(each_slave+each_master*axi_slave_amount) := '0'; end loop; --slave_enables_buff(each_slave+master_iden_buff*axi_slave_amount) := '0'; end if; end loop; return slave_enables_buff; end; function reduce_enables_slave( enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return std_logic_vector is variable or_reduced : std_logic; variable reduce_enables : std_logic_vector(axi_slave_amount-1 downto 0); begin for each_slave in 0 to axi_slave_amount-1 loop or_reduced := '0'; for each_master in 0 to axi_master_amount-1 loop or_reduced := or_reduced or enables(each_slave+each_master*axi_slave_amount); end loop; reduce_enables(each_slave) := or_reduced; end loop; return reduce_enables; end; function get_master_handshakes ( valid : in std_logic_vector(axi_master_amount-1 downto 0); ready : in std_logic_vector(axi_slave_amount-1 downto 0); slave_iden : in std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0) ) return std_logic_vector is variable slave_iden_buff : integer range 0 to axi_slave_amount-1; variable master_handshakes : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0'); begin for each_master in 0 to axi_master_amount-1 loop slave_iden_buff := to_integer(unsigned(slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width))); if valid(each_master)='1' and ready(slave_iden_buff)='1' then master_handshakes(each_master) := '1'; end if; end loop; return master_handshakes; end; function get_master_permissions ( master_valid : in std_logic_vector(axi_master_amount-1 downto 0); slave_iden : in std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0); reduced_response_enables : in std_logic_vector(axi_slave_amount-1 downto 0) ) return std_logic_vector is variable slave_iden_buff : integer range 0 to axi_slave_amount-1; variable master_permissions : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0'); begin for each_master in 0 to axi_master_amount-1 loop slave_iden_buff := to_integer(unsigned(slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width))); for each_slave in 0 to axi_slave_amount-1 loop if each_slave=slave_iden_buff and master_valid(each_master)='1' and reduced_response_enables(slave_iden_buff)='0' then master_permissions(each_master) := '1'; exit; end if; end loop; end loop; return master_permissions; end; function set_master_enables_ff ( master_permissions : in std_logic_vector(axi_master_amount-1 downto 0); master_handshakes : in std_logic_vector(axi_master_amount-1 downto 0); slave_iden : in std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0); master_enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return std_logic_vector is variable slave_iden_buff : integer range 0 to axi_slave_amount-1; variable master_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0); begin master_enables_buff := master_enables; for each_master in 0 to axi_master_amount-1 loop slave_iden_buff := to_integer(unsigned(slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width))); if master_permissions(each_master)='1' then master_enables_buff(slave_iden_buff+each_master*axi_slave_amount) := '1'; elsif master_handshakes(each_master)='1' then for each_slave in 0 to axi_slave_amount-1 loop master_enables_buff(each_slave+each_master*axi_slave_amount) := '0'; end loop; end if; end loop; return master_enables_buff; end; signal address_slave_handshakes : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0'); signal data_slave_handshakes : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0'); signal axi_address_write_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) := (others=>'0'); signal axi_data_write_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) := (others=>'0'); signal reduced_data_write_enables : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0'); signal slave_permissions : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0'); signal response_master_handshakes : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0'); signal axi_response_write_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) := (others=>'0'); signal reduced_response_write_enables : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0'); signal master_permissions : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0'); begin axi_address_write_enables <= axi_address_write_enables_buff; axi_data_write_enables <= axi_data_write_enables_buff; axi_response_write_enables <= axi_response_write_enables_buff; process (s_axi_awvalid,m_axi_awready,axi_write_master_iden) begin address_slave_handshakes <= get_slave_handshakes(s_axi_awvalid,m_axi_awready,axi_write_master_iden); end process; process (s_axi_wvalid,m_axi_wready,axi_write_master_iden) begin data_slave_handshakes <= get_slave_handshakes(s_axi_wvalid,m_axi_wready,axi_write_master_iden); end process; process (axi_data_write_enables_buff) begin reduced_data_write_enables <= reduce_enables_master(axi_data_write_enables_buff); end process; process (s_axi_awvalid,axi_write_master_iden,reduced_data_write_enables) begin slave_permissions <= get_slave_permissions(s_axi_awvalid,axi_write_master_iden,reduced_data_write_enables); end process; process (m_axi_bvalid,s_axi_bready,axi_write_slave_iden) begin response_master_handshakes <= get_master_handshakes(m_axi_bvalid,s_axi_bready,axi_write_slave_iden); end process; process (axi_response_write_enables_buff) begin reduced_response_write_enables <= reduce_enables_slave(axi_response_write_enables_buff); end process; process (m_axi_bvalid,axi_write_slave_iden,reduced_response_write_enables) begin master_permissions <= get_master_permissions(m_axi_bvalid,axi_write_slave_iden,reduced_response_write_enables); end process; process (aclk) begin if rising_edge(aclk) then if aresetn='0' then axi_address_write_enables_buff <= (others=>'0'); axi_data_write_enables_buff <= (others=>'0'); axi_response_write_enables_buff <= (others=>'0'); else axi_address_write_enables_buff <= set_slave_enables_ff(slave_permissions,address_slave_handshakes,(others=>'1'),axi_write_master_iden,axi_address_write_enables_buff); axi_data_write_enables_buff <= set_slave_enables_ff(slave_permissions,data_slave_handshakes,s_axi_wlast,axi_write_master_iden,axi_data_write_enables_buff); axi_response_write_enables_buff <= set_master_enables_ff(master_permissions,response_master_handshakes,axi_write_slave_iden,axi_response_write_enables_buff); end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity vga_buffer is generic ( SIZE_POW2 : integer := 6 ); port ( clk_w : in std_logic; clk_r : in std_logic; wen : in std_logic; x_addr_w : in std_logic_vector(9 downto 0); y_addr_w : in std_logic_vector(9 downto 0); x_addr_r : in std_logic_vector(9 downto 0); y_addr_r : in std_logic_vector(9 downto 0); data_w : in std_logic_vector(23 downto 0); data_r : out std_logic_vector(23 downto 0) ); end vga_buffer; architecture Behavioral of vga_buffer is type DATA_BUFFER is array (2**SIZE_POW2 - 1 downto 0) of std_logic_vector(23 downto 0); signal data : DATA_BUFFER; signal c_addr_w, c_addr_r : std_logic_vector(19 downto 0); signal addr_w, addr_r : std_logic_vector(SIZE_POW2 - 1 downto 0); begin process(clk_w) begin if rising_edge(clk_w) then if wen = '1' then c_addr_w(9 downto 0) <= x_addr_w; c_addr_w(19 downto 10) <= y_addr_w; addr_w <= c_addr_w(SIZE_POW2 - 1 downto 0); data(to_integer(unsigned(addr_w))) <= data_w; end if; end if; end process; process(clk_r) begin if rising_edge(clk_r) then c_addr_r(9 downto 0) <= x_addr_r; c_addr_r(19 downto 10) <= y_addr_r; addr_r <= c_addr_r(SIZE_POW2 - 1 downto 0); data_r <= data(to_integer(unsigned(addr_r))); end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity vga_buffer is generic ( SIZE_POW2 : integer := 6 ); port ( clk_w : in std_logic; clk_r : in std_logic; wen : in std_logic; x_addr_w : in std_logic_vector(9 downto 0); y_addr_w : in std_logic_vector(9 downto 0); x_addr_r : in std_logic_vector(9 downto 0); y_addr_r : in std_logic_vector(9 downto 0); data_w : in std_logic_vector(23 downto 0); data_r : out std_logic_vector(23 downto 0) ); end vga_buffer; architecture Behavioral of vga_buffer is type DATA_BUFFER is array (2**SIZE_POW2 - 1 downto 0) of std_logic_vector(23 downto 0); signal data : DATA_BUFFER; signal c_addr_w, c_addr_r : std_logic_vector(19 downto 0); signal addr_w, addr_r : std_logic_vector(SIZE_POW2 - 1 downto 0); begin process(clk_w) begin if rising_edge(clk_w) then if wen = '1' then c_addr_w(9 downto 0) <= x_addr_w; c_addr_w(19 downto 10) <= y_addr_w; addr_w <= c_addr_w(SIZE_POW2 - 1 downto 0); data(to_integer(unsigned(addr_w))) <= data_w; end if; end if; end process; process(clk_r) begin if rising_edge(clk_r) then c_addr_r(9 downto 0) <= x_addr_r; c_addr_r(19 downto 10) <= y_addr_r; addr_r <= c_addr_r(SIZE_POW2 - 1 downto 0); data_r <= data(to_integer(unsigned(addr_r))); end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity vga_buffer is generic ( SIZE_POW2 : integer := 6 ); port ( clk_w : in std_logic; clk_r : in std_logic; wen : in std_logic; x_addr_w : in std_logic_vector(9 downto 0); y_addr_w : in std_logic_vector(9 downto 0); x_addr_r : in std_logic_vector(9 downto 0); y_addr_r : in std_logic_vector(9 downto 0); data_w : in std_logic_vector(23 downto 0); data_r : out std_logic_vector(23 downto 0) ); end vga_buffer; architecture Behavioral of vga_buffer is type DATA_BUFFER is array (2**SIZE_POW2 - 1 downto 0) of std_logic_vector(23 downto 0); signal data : DATA_BUFFER; signal c_addr_w, c_addr_r : std_logic_vector(19 downto 0); signal addr_w, addr_r : std_logic_vector(SIZE_POW2 - 1 downto 0); begin process(clk_w) begin if rising_edge(clk_w) then if wen = '1' then c_addr_w(9 downto 0) <= x_addr_w; c_addr_w(19 downto 10) <= y_addr_w; addr_w <= c_addr_w(SIZE_POW2 - 1 downto 0); data(to_integer(unsigned(addr_w))) <= data_w; end if; end if; end process; process(clk_r) begin if rising_edge(clk_r) then c_addr_r(9 downto 0) <= x_addr_r; c_addr_r(19 downto 10) <= y_addr_r; addr_r <= c_addr_r(SIZE_POW2 - 1 downto 0); data_r <= data(to_integer(unsigned(addr_r))); end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity vga_buffer is generic ( SIZE_POW2 : integer := 6 ); port ( clk_w : in std_logic; clk_r : in std_logic; wen : in std_logic; x_addr_w : in std_logic_vector(9 downto 0); y_addr_w : in std_logic_vector(9 downto 0); x_addr_r : in std_logic_vector(9 downto 0); y_addr_r : in std_logic_vector(9 downto 0); data_w : in std_logic_vector(23 downto 0); data_r : out std_logic_vector(23 downto 0) ); end vga_buffer; architecture Behavioral of vga_buffer is type DATA_BUFFER is array (2**SIZE_POW2 - 1 downto 0) of std_logic_vector(23 downto 0); signal data : DATA_BUFFER; signal c_addr_w, c_addr_r : std_logic_vector(19 downto 0); signal addr_w, addr_r : std_logic_vector(SIZE_POW2 - 1 downto 0); begin process(clk_w) begin if rising_edge(clk_w) then if wen = '1' then c_addr_w(9 downto 0) <= x_addr_w; c_addr_w(19 downto 10) <= y_addr_w; addr_w <= c_addr_w(SIZE_POW2 - 1 downto 0); data(to_integer(unsigned(addr_w))) <= data_w; end if; end if; end process; process(clk_r) begin if rising_edge(clk_r) then c_addr_r(9 downto 0) <= x_addr_r; c_addr_r(19 downto 10) <= y_addr_r; addr_r <= c_addr_r(SIZE_POW2 - 1 downto 0); data_r <= data(to_integer(unsigned(addr_r))); end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity vga_buffer is generic ( SIZE_POW2 : integer := 6 ); port ( clk_w : in std_logic; clk_r : in std_logic; wen : in std_logic; x_addr_w : in std_logic_vector(9 downto 0); y_addr_w : in std_logic_vector(9 downto 0); x_addr_r : in std_logic_vector(9 downto 0); y_addr_r : in std_logic_vector(9 downto 0); data_w : in std_logic_vector(23 downto 0); data_r : out std_logic_vector(23 downto 0) ); end vga_buffer; architecture Behavioral of vga_buffer is type DATA_BUFFER is array (2**SIZE_POW2 - 1 downto 0) of std_logic_vector(23 downto 0); signal data : DATA_BUFFER; signal c_addr_w, c_addr_r : std_logic_vector(19 downto 0); signal addr_w, addr_r : std_logic_vector(SIZE_POW2 - 1 downto 0); begin process(clk_w) begin if rising_edge(clk_w) then if wen = '1' then c_addr_w(9 downto 0) <= x_addr_w; c_addr_w(19 downto 10) <= y_addr_w; addr_w <= c_addr_w(SIZE_POW2 - 1 downto 0); data(to_integer(unsigned(addr_w))) <= data_w; end if; end if; end process; process(clk_r) begin if rising_edge(clk_r) then c_addr_r(9 downto 0) <= x_addr_r; c_addr_r(19 downto 10) <= y_addr_r; addr_r <= c_addr_r(SIZE_POW2 - 1 downto 0); data_r <= data(to_integer(unsigned(addr_r))); end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity vga_buffer is generic ( SIZE_POW2 : integer := 6 ); port ( clk_w : in std_logic; clk_r : in std_logic; wen : in std_logic; x_addr_w : in std_logic_vector(9 downto 0); y_addr_w : in std_logic_vector(9 downto 0); x_addr_r : in std_logic_vector(9 downto 0); y_addr_r : in std_logic_vector(9 downto 0); data_w : in std_logic_vector(23 downto 0); data_r : out std_logic_vector(23 downto 0) ); end vga_buffer; architecture Behavioral of vga_buffer is type DATA_BUFFER is array (2**SIZE_POW2 - 1 downto 0) of std_logic_vector(23 downto 0); signal data : DATA_BUFFER; signal c_addr_w, c_addr_r : std_logic_vector(19 downto 0); signal addr_w, addr_r : std_logic_vector(SIZE_POW2 - 1 downto 0); begin process(clk_w) begin if rising_edge(clk_w) then if wen = '1' then c_addr_w(9 downto 0) <= x_addr_w; c_addr_w(19 downto 10) <= y_addr_w; addr_w <= c_addr_w(SIZE_POW2 - 1 downto 0); data(to_integer(unsigned(addr_w))) <= data_w; end if; end if; end process; process(clk_r) begin if rising_edge(clk_r) then c_addr_r(9 downto 0) <= x_addr_r; c_addr_r(19 downto 10) <= y_addr_r; addr_r <= c_addr_r(SIZE_POW2 - 1 downto 0); data_r <= data(to_integer(unsigned(addr_r))); end if; end process; end Behavioral;
--Gatterschaltung zu Aufgabe 2.4 --Christian Rebischke 18.4.2014 -- x Eingänge, y Ausgang, z "zwischenstationen" library IEEE; use IEEE.std_logic_1164.all; entity Gatterschaltung is port(x: in STD_LOGIC_VECTOR(2 DOWNTO 0); y: out STD_LOGIC); end entity; architecture test of Gatterschaltung is signal z: STD_LOGIC_VECTOR(4 DOWNTO 0); begin z(0) <= not(x(1)); z(1) <= not(x(2)); z(2) <= x(0) nand x(1); z(3) <= x(0) nand (z(0) and x(2)); z(4) <= x(0) nand z(1); y <= z(2) nand (z(3) and z(4)); end architecture;
--Gatterschaltung zu Aufgabe 2.4 --Christian Rebischke 18.4.2014 -- x Eingänge, y Ausgang, z "zwischenstationen" library IEEE; use IEEE.std_logic_1164.all; entity Gatterschaltung is port(x: in STD_LOGIC_VECTOR(2 DOWNTO 0); y: out STD_LOGIC); end entity; architecture test of Gatterschaltung is signal z: STD_LOGIC_VECTOR(4 DOWNTO 0); begin z(0) <= not(x(1)); z(1) <= not(x(2)); z(2) <= x(0) nand x(1); z(3) <= x(0) nand (z(0) and x(2)); z(4) <= x(0) nand z(1); y <= z(2) nand (z(3) and z(4)); end architecture;
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -- Date : Tue Sep 19 09:38:30 2017 -- Host : DarkCube running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_processing_system7_0_0_stub.vhdl -- Design : zynq_design_1_processing_system7_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is Port ( TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; FTMT_F2P_TRIG_0 : in STD_LOGIC; FTMT_F2P_TRIGACK_0 : out STD_LOGIC; FTMT_P2F_TRIGACK_0 : in STD_LOGIC; FTMT_P2F_TRIG_0 : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,FTMT_F2P_TRIG_0,FTMT_F2P_TRIGACK_0,FTMT_P2F_TRIGACK_0,FTMT_P2F_TRIG_0,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.2"; begin end;
-- Copyright (c) 2013 Antonio de la Piedra -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY tb_noekeon IS END tb_noekeon; ARCHITECTURE behavior OF tb_noekeon IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT noekeon PORT( clk : IN std_logic; rst : IN std_logic; enc : IN std_logic; a_0_in : IN std_logic_vector(31 downto 0); a_1_in : IN std_logic_vector(31 downto 0); a_2_in : IN std_logic_vector(31 downto 0); a_3_in : IN std_logic_vector(31 downto 0); k_0_in : IN std_logic_vector(31 downto 0); k_1_in : IN std_logic_vector(31 downto 0); k_2_in : IN std_logic_vector(31 downto 0); k_3_in : IN std_logic_vector(31 downto 0); a_0_out : OUT std_logic_vector(31 downto 0); a_1_out : OUT std_logic_vector(31 downto 0); a_2_out : OUT std_logic_vector(31 downto 0); a_3_out : OUT std_logic_vector(31 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal rst : std_logic := '0'; signal enc : std_logic := '0'; signal a_0_in : std_logic_vector(31 downto 0) := (others => '0'); signal a_1_in : std_logic_vector(31 downto 0) := (others => '0'); signal a_2_in : std_logic_vector(31 downto 0) := (others => '0'); signal a_3_in : std_logic_vector(31 downto 0) := (others => '0'); signal k_0_in : std_logic_vector(31 downto 0) := (others => '0'); signal k_1_in : std_logic_vector(31 downto 0) := (others => '0'); signal k_2_in : std_logic_vector(31 downto 0) := (others => '0'); signal k_3_in : std_logic_vector(31 downto 0) := (others => '0'); --Outputs signal a_0_out : std_logic_vector(31 downto 0); signal a_1_out : std_logic_vector(31 downto 0); signal a_2_out : std_logic_vector(31 downto 0); signal a_3_out : std_logic_vector(31 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: noekeon PORT MAP ( clk => clk, rst => rst, enc => enc, a_0_in => a_0_in, a_1_in => a_1_in, a_2_in => a_2_in, a_3_in => a_3_in, k_0_in => k_0_in, k_1_in => k_1_in, k_2_in => k_2_in, k_3_in => k_3_in, a_0_out => a_0_out, a_1_out => a_1_out, a_2_out => a_2_out, a_3_out => a_3_out ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin wait for clk_period/2 + clk_period; rst <= '1'; enc <= '0'; a_0_in <= X"2a78421b"; a_1_in <= X"87c7d092"; a_2_in <= X"4f26113f"; a_3_in <= X"1d1349b2"; k_0_in <= X"b1656851"; k_1_in <= X"699e29fa"; k_2_in <= X"24b70148"; k_3_in <= X"503d2dfc"; wait for clk_period; rst <= '0'; wait for clk_period*64;-- + clk_period/2; assert a_0_out = X"e2f687e0" report "ENCRYPT ERROR (a_0)" severity FAILURE; assert a_1_out = X"7b75660f" report "ENCRYPT ERROR (a_1)" severity FAILURE; assert a_2_out = X"fc372233" report "ENCRYPT ERROR (a_2)" severity FAILURE; assert a_3_out = X"bc47532c" report "ENCRYPT ERROR (a_3)" severity FAILURE; -- wait for clk_period + clk_period/2; -- rst <= '1'; -- enc <= '1'; -- -- a_0_in <= X"e2f687e0"; -- a_1_in <= X"7b75660f"; -- a_2_in <= X"fc372233"; -- a_3_in <= X"bc47532c"; -- -- k_0_in <= X"b1656851"; -- k_1_in <= X"699e29fa"; -- k_2_in <= X"24b70148"; -- k_3_in <= X"503d2dfc"; -- -- wait for clk_period; -- rst <= '0'; -- -- wait for clk_period*15 + clk_period/2; -- -- assert a_0_out = X"2a78421b" -- report "DECRYPT ERROR (a_0)" severity FAILURE; -- -- assert a_1_out = X"87c7d092" -- report "DECRYPT ERROR (a_1)" severity FAILURE; -- -- assert a_2_out = X"4f26113f" -- report "DECRYPT ERROR (a_2)" severity FAILURE; -- -- assert a_3_out = X"1d1349b2" -- report "DECRYPT ERROR (a_3)" severity FAILURE; wait; end process; END;
-- ------------------------------------------------------------- -- -- Generated Architecture Declaration for rtl of inst_a_e -- -- Generated -- by: wig -- on: Sat Mar 3 11:02:57 2007 -- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_a_e-rtl-a.vhd,v 1.1 2007/03/03 11:17:34 wig Exp $ -- $Date: 2007/03/03 11:17:34 $ -- $Log: inst_a_e-rtl-a.vhd,v $ -- Revision 1.1 2007/03/03 11:17:34 wig -- Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL> -- -- -- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp -- -- Generator: mix_0.pl Revision: 1.47 , wilfried.gaensheimer@micronas.com -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/arch HOOK: global text to add to head of architecture, here is %::inst% -- -- -- Start of Generated Architecture rtl of inst_a_e -- architecture rtl of inst_a_e is -- -- Generated Constant Declarations -- -- -- Generated Components -- component inst_aa_e -- vhdl udc test for inst_aa_i -- No Generated Generics -- Generated Generics for Entity inst_aa_e -- End of Generated Generics for Entity inst_aa_e port ( -- Generated Port for Entity inst_aa_e port_xa_i : in std_ulogic; -- tie to low to create port port_xa_o : out std_ulogic -- signal test aa to ba -- End of Generated Port for Entity inst_aa_e ); end component; -- --------- component inst_ab_e -- vhdl udc test for inst_ab_i -- No Generated Generics port ( -- Generated Port for Entity inst_ab_e port_ab_i : in std_ulogic_vector(7 downto 0) -- vector test bb to ab -- End of Generated Port for Entity inst_ab_e ); end component; -- --------- -- -- Generated Signal List -- signal mix_logic0_0 : std_ulogic; signal signal_aa_ba : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ signal signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ -- -- End of Generated Signal List -- begin udc: THIS GOES TO BODY of inst_a_i; -- -- Generated Concurrent Statements -- -- -- Generated Signal Assignments -- mix_logic0_0 <= '0'; p_mix_signal_aa_ba_go <= signal_aa_ba; -- __I_O_BIT_PORT signal_bb_ab <= p_mix_signal_bb_ab_gi; -- __I_I_BUS_PORT -- -- Generated Instances and Port Mappings -- udc: pre_inst_udc for VHDL goes into inst_a_i -- Generated Instance Port Map for inst_aa_i inst_aa_i: inst_aa_e -- vhdl udc test for inst_aa_i port map ( port_xa_i => mix_logic0_0, -- tie to low to create port port_xa_o => signal_aa_ba -- signal test aa to ba ); -- End of Generated Instance Port Map for inst_aa_i udc: post_inst_udc VHDL for inst_aa_i goes into inst_a_i udc: pre_inst_udc for VHDL inst_ab_i -- Generated Instance Port Map for inst_ab_i inst_ab_i: inst_ab_e -- vhdl udc test for inst_ab_i port map ( port_ab_i => signal_bb_ab -- vector test bb to ab ); -- End of Generated Instance Port Map for inst_ab_i udc: post_inst_udc VHDL for inst_ab_i end rtl; -- --!End of Architecture/s -- --------------------------------------------------------------
------------------------------------------------------------------------------- -- -- $Id: t48_tb_pack-p.vhd,v 1.2 2004-04-14 20:53:54 arniml Exp $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- -- All rights reserved -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; package t48_tb_pack is -- Instruction strobe visibility signal tb_istrobe_s : std_logic; -- Accumulator visibilty signal tb_accu_s : std_logic_vector(7 downto 0); end t48_tb_pack;
-- -- vending machine FSM -- -------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -------------------------------------- entity vending_machine is --generic declarations port ( clk, rst: in std_logic; nickel_in, dime_in, quarter_in: in boolean; candy_out, nickel_out, dime_out: out std_logic); end entity vending_machine; -------------------------------------- architecture circuit of vending_machine is type state is (st0, st5, st10, st15, st20, st25, st30, st35, st40, st45); signal pr_state, nx_state: state; attribute enum_encoding: string; attribute enum_encoding of state: type is "sequential"; begin -------------------------------------- -- lower section of FSM (sequential part) -------------------------------------- process (rst, clk) --declarativepart begin if (rst = '1') then pr_state <= st0; elsif (clk'event and clk = '1') then pr_state <= nx_state; end if; end process; -------------------------------------- -- upper section of FSM (combinational part) -------------------------------------- process (pr_state, nickel_in, dime_in, quarter_in) --declarativepart begin case pr_state is when st0 => candy_out <= '0'; nickel_out <= '0'; dime_out <= '0'; if (nickel_in) then nx_state <= st5; elsif (dime_in) then nx_state <= st10; elsif (quarter_in) then nx_state <= st25; else nx_state <= st0; end if; when st5 => candy_out <= '0'; nickel_out <= '0'; dime_out <= '0'; if (nickel_in) then nx_state <= st10; elsif (dime_in) then nx_state <= st15; elsif (quarter_in) then nx_state <= st30; else nx_state <= st5; end if; when st10 => candy_out <= '0'; nickel_out <= '0'; dime_out <= '0'; if (nickel_in) then nx_state <= st15; elsif (dime_in) then nx_state <= st20; elsif (quarter_in) then nx_state <= st35; else nx_state <= st10; end if; when st15 => candy_out <= '0'; nickel_out <= '0'; dime_out <= '0'; if (nickel_in) then nx_state <= st20; elsif (dime_in) then nx_state <= st25; elsif (quarter_in) then nx_state <= st40; else nx_state <= st15; end if; when st20 => candy_out <= '0'; nickel_out <= '0'; dime_out <= '0'; if (nickel_in) then nx_state <= st25; elsif (dime_in) then nx_state <= st30; elsif (quarter_in) then nx_state <= st45; else nx_state <= st20; end if; when st25 => candy_out <= '1'; nickel_out <= '0'; dime_out <= '0'; nx_state <= st0; when st30 => candy_out <= '1'; nickel_out <= '1'; dime_out <= '0'; nx_state <= st0; when st35 => candy_out <= '1'; nickel_out <= '0'; dime_out <= '0'; nx_state <= st0; when st40 => candy_out <= '0'; nickel_out <= '1'; dime_out <= '0'; nx_state <= st35; when st45 => candy_out <= '0'; nickel_out <= '0'; dime_out <= '1'; nx_state <= st35; end case; end process; end architecture circuit;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library mblite; use mblite.config_Pkg.all; use mblite.core_Pkg.all; use mblite.std_Pkg.all; library work; use work.tl_string_util_pkg.all; library std; use std.textio.all; entity mblite_simu is end entity; architecture test of mblite_simu is signal clock : std_logic := '0'; signal reset : std_logic; signal imem_o : imem_out_type; signal imem_i : imem_in_type; signal dmem_o : dmem_out_type; signal dmem_i : dmem_in_type; signal irq_i : std_logic := '0'; signal irq_o : std_logic; type t_mem_array is array(natural range <>) of std_logic_vector(31 downto 0); shared variable memory : t_mem_array(0 to 1048575) := (others => (others => '0')); -- 4MB signal last_char : std_logic_vector(7 downto 0); BEGIN clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; core0 : core port map ( imem_o => imem_o, imem_i => imem_i, dmem_o => dmem_o, dmem_i => dmem_i, int_i => irq_i, int_o => irq_o, rst_i => reset, clk_i => clock ); -- memory and IO process(clock) variable s : line; variable char : character; variable byte : std_logic_vector(7 downto 0); begin if rising_edge(clock) then if imem_o.ena_o = '1' then imem_i.dat_i <= memory(to_integer(unsigned(imem_o.adr_o(21 downto 2)))); -- if (imem_i.dat_i(31 downto 26) = "000101") and (imem_i.dat_i(1 downto 0) = "01") then -- report "Suspicious CMPS" severity warning; -- end if; end if; if dmem_o.ena_o = '1' then if dmem_o.adr_o(31 downto 25) = "0000000" then if dmem_o.we_o = '1' then for i in 0 to 3 loop if dmem_o.sel_o(i) = '1' then memory(to_integer(unsigned(dmem_o.adr_o(21 downto 2))))(i*8+7 downto i*8) := dmem_o.dat_o(i*8+7 downto i*8); end if; end loop; else -- read dmem_i.dat_i <= memory(to_integer(unsigned(dmem_o.adr_o(21 downto 2)))); end if; else -- I/O if dmem_o.we_o = '1' then -- write case dmem_o.adr_o(19 downto 0) is when X"00000" => -- interrupt null; when X"00010" => -- UART_DATA byte := dmem_o.dat_o(31 downto 24); char := character'val(to_integer(unsigned(byte))); last_char <= char; if byte = X"0D" then -- Ignore character 13 elsif byte = X"0A" then -- Writeline on character 10 (newline) writeline(output, s); else -- Write to buffer write(s, char); end if; when others => report "I/O write to " & hstr(dmem_o.adr_o) & " dropped"; end case; else -- read case dmem_o.adr_o(19 downto 0) is when X"0000C" => -- Capabilities dmem_i.dat_i <= X"00000002"; when X"00012" => -- UART_FLAGS dmem_i.dat_i <= X"40404040"; when X"2000A" => -- 1541_A memmap dmem_i.dat_i <= X"3F3F3F3F"; when X"2000B" => -- 1541_A audiomap dmem_i.dat_i <= X"3E3E3E3E"; when others => report "I/O read to " & hstr(dmem_o.adr_o) & " dropped"; dmem_i.dat_i <= X"00000000"; end case; end if; end if; end if; if reset = '1' then imem_i.ena_i <= '1'; dmem_i.ena_i <= '1'; end if; end if; end process; end architecture;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block jb9Kq6vkzkXEU1vmtD5QucKALnpq9O4QaNmDuUUk4flNfyazXcgHC/2RBOkKKQZt/G7nyAbZ+63C cAH1WISUKQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block MGtVysV5czGTx5mwtdnKKLxesl2+RC/7smOjTrD/+cWCp+URSdbKKZAhqVU8tD2Mfi72RD5gGbmj GTF9OzX00FbRj21qyQjz1CggJunhtLEjpAn8o+fbL91W1m6jKKLrf0kY0CkQsFUnlQpNq9OUOJ4O XevrAGUwnGocq2blLk0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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-------------------------------------------------------------------------------- --Copyright (c) 2014, Benjamin Bässler <ccl@xunit.de> --All rights reserved. -- --Redistribution and use in source and binary forms, with or without --modification, are permitted provided that the following conditions are met: -- --* Redistributions of source code must retain the above copyright notice, this -- list of conditions and the following disclaimer. -- --* Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- --THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE --IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE --DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE --FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL --DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR --SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER --CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, --OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE --OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -------------------------------------------------------------------------------- --! @file stimgen.vhd --! @brief Generates Stimulies by using a counter --! @author Benjamin Bässler --! @email ccl@xunit.de --! @date 2013-09-02 -------------------------------------------------------------------------------- --! Use standard library library ieee; --! Use numeric std use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; use IEEE.math_real.all; use work.types.all; use work.utils.all; entity stimgen is generic( --! width of the input G_INPUT_WIDTH : NATURAL := C_IMAGE_WIDTH * C_IMAGE_HEIGHT ); port( --! Clock input clk_in : in STD_LOGIC; --! Reset input rst_in : in STD_LOGIC; --! error_out valid error_valid_out : out STD_LOGIC; --! error valu error_out : out STD_LOGIC_VECTOR(T_ERROR'range); --! stimuli lead to error stimuli_out : out STD_LOGIC_VECTOR(G_INPUT_WIDTH-1 downto 0); --! how many stimulis are processed --! this value has a error of G_COMP_INSTANCES processed_out : out STD_LOGIC_VECTOR(G_INPUT_WIDTH-1 downto 0); --! rises if check is done check_done_out : out STD_LOGIC ); end entity stimgen; architecture stimgen_arc of stimgen is CONSTANT C_MAX_STIM : UNSIGNED(G_INPUT_WIDTH-1 downto 0) := (others => '1'); Signal cnt_s : UNSIGNED(G_INPUT_WIDTH-1 downto 0); Signal cnt_inc_s : STD_LOGIC; Signal max_util_s : STD_LOGIC; Signal idle_s : STD_LOGIC; Signal stimuli_v_s : STD_LOGIC; Signal stimuli_s : UNSIGNED(G_INPUT_WIDTH-1 downto 0); Signal stimuli_out_s : UNSIGNED(G_INPUT_WIDTH-1 downto 0); Signal error_out_s : T_ERROR; begin stimuli_out <= std_logic_vector(stimuli_out_s); error_out <= std_logic_vector(error_out_s); --! generate new stimuli if the verificator has not max utilization --cnt_inc_s <= (not max_util_s) and (not rst_in); check_done_out <= '1' when cnt_s = C_MAX_STIM and idle_s = '1' else '0'; --! this value has a error of G_COMP_INSTANCES processed_out <= std_logic_vector(cnt_s); --! assign the stimuli valid signal clock dependent --! (the max_util_out dependt combinatorical on stimuli_v_in) p_inc : process (clk_in) is begin if rising_edge(clk_in) then stimuli_v_s <= '0'; cnt_inc_s <= '0'; if max_util_s = '0' and rst_in = '0' then stimuli_v_s <= '1'; stimuli_s <= cnt_s; cnt_inc_s <= '1'; end if; end if; end process p_inc; verificator : entity work.verificator PORT MAP( clk_in => clk_in, rst_in => rst_in, stimuli_v_in => stimuli_v_s, stimuli_in => stimuli_s, error_valid_out => error_valid_out, error_out => error_out_s, stimuli_out => stimuli_out_s, run_in => '1', max_util_out => max_util_s, idle_out => idle_s ); counter : entity work.counter GENERIC MAP( G_CNT_LENGTH => G_INPUT_WIDTH, G_INC_VALUE => 1, G_OFFSET => to_unsigned(1, 64) --to_unsigned(21, 64) --G_OFFSET => x"0000000700F73906" --there should be dragons ) PORT MAP( clk_in => clk_in, rst_in => rst_in, inc_in => cnt_inc_s, cnt_out => cnt_s ); end architecture stimgen_arc;
library IEEE; use IEEE.math_real.all; use IEEE.std_logic_1164.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.energy_systems.all; entity driver_ideal is generic (r_open : resistance := 1000.0; r_closed : resistance := 5.0; trans_time : real := 500.0e-12; cap : capacitance := 5.1e-12; delay : time := 0 ns); port( dig_input : in std_logic; terminal v_pwr : electrical; terminal v_gnd : electrical; terminal v_driver : electrical ); end driver_ideal; architecture linear of driver_ideal is signal d_input_inv : std_logic; signal r_pu_sig : resistance := r_open; signal r_pd_sig : resistance := r_open; quantity v_pu across i_pu through v_pwr to v_driver; quantity r_pu : resistance; quantity v_pd across i_pd through v_driver to v_gnd; quantity r_pd : resistance; quantity v_cap across i_cap through v_driver to v_gnd; quantity v_gc across i_gc through v_gnd to v_driver; quantity v_pc across i_pc through v_driver to v_pwr; constant isat : current := 1.0e-14; -- Saturation current [Amps] constant TempC : real := 27.0; -- Ambient Temperature [Degrees] constant TempK : real := 273.0 + TempC; -- Temperaure [Kelvin] constant vt : real := K*TempK/Q; -- Thermal Voltage begin d_input_inv <= not dig_input after delay; DetectPUState: process (dig_input) begin if (dig_input'event and dig_input = '0') then r_pu_sig <= r_open; elsif (dig_input'event and dig_input = '1') then r_pu_sig <= r_closed; end if; end process DetectPUState; r_pu == r_pu_sig'ramp(trans_time, trans_time); v_pu == r_pu*i_pu; DetectPDState: process (d_input_inv) begin if (d_input_inv'event and d_input_inv = '0') then r_pd_sig <= r_open; elsif (d_input_inv'event and d_input_inv = '1') then r_pd_sig <= r_closed; end if; end process DetectPDState; r_pd == r_pd_sig'ramp(trans_time, trans_time); v_pd == r_pd*i_pd; v_cap*cap == i_cap'integ; i_gc == isat*(exp(v_gc/vt) - 1.0); i_pc == isat*(exp(v_pc/vt) - 1.0); end linear;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc492.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY vests42 IS END vests42; ARCHITECTURE c03s02b02x00p01n01i00492arch OF vests42 IS type etype is (one,two,three,four,five,six,seven); type TR is record i : integer; b : bit; bo : boolean; bv : bit_vector (0 to 3); r : real; t : time; e : etype; c : character; end record; type T1 is record t : time; b : bit; i : integer; bo : boolean; r : real; bv : bit_vector (0 to 3); e : etype; c : character; end record; function FUNC1(signal recd1: TR) return T1 is variable recd2:T1; begin recd2.bv := recd1.bv; recd2.b := recd1.b; recd2.bo := recd1.bo; recd2.i := recd1.i; recd2.r := recd1.r; recd2.t := recd1.t; recd2.e := recd1.e; recd2.c := recd1.c; return recd2; end FUNC1; function FUNC2(signal recd1: TR) return integer is begin return recd1.i; end; function FUNC3(signal recd1: TR) return bit is begin return recd1.b; end; function FUNC4(signal recd1: TR) return boolean is begin return recd1.bo; end; function FUNC5(signal recd1: TR) return bit_vector is begin return recd1.bv; end; function FUNC6(signal recd1: TR) return real is begin return recd1.r; end; function FUNC7(signal recd1: TR) return time is begin return recd1.t; end; function FUNC8(signal recd1: TR) return etype is begin return recd1.e; end; function FUNC9(signal recd1: TR) return character is begin return recd1.c; end; signal var1: TR; signal var2: T1; BEGIN TESTING: PROCESS variable OkayCount : integer := 0; BEGIN wait for 1 ns; var2 <= (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a'); var1 <= (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%'); wait for 1 ns; var2 <= FUNC1(var1); wait for 1 ns; assert var2.bv = "0001" report "var2.bv /= 0001" severity note; assert var2.b = '1' report "var2.b /= 1" severity note; assert var2.bo = true report "var2.bo /= true" severity note; assert var2.i = 777 report "var2.i /= 777" severity note; assert var2.r = 333.767 report "var2.r /= 333.767" severity note; assert var2.t = 44 ms report "var2.t /= 44 ms" severity note; assert var2.e = seven report "var2.e /= seven" severity note; assert var2.c = '%' report "var2.c /= c" severity note; if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then OkayCount := OkayCount + 1; else assert false report "bad return on FUNC1" severity note; end if; var2 <= (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a'); wait for 1 ns; if var2 = (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a') then OkayCount := OkayCount + 1; end if; var2.i <= FUNC2(var1); var2.b <= FUNC3(var1); var2.bo <= FUNC4(var1); var2.bv <= FUNC5(var1); var2.r <= FUNC6(var1); var2.t <= FUNC7(var1); var2.e <= FUNC8(var1); var2.c <= FUNC9(var1); wait for 1 ns; assert var2.bv = "0001" report "var2.bv /= 0001" severity note; assert var2.b = '1' report "var2.b /= 1" severity note; assert var2.bo = true report "var2.bo /= true" severity note; assert var2.i = 777 report "var2.i /= 777" severity note; assert var2.r = 333.767 report "var2.r /= 333.767" severity note; assert var2.t = 44 ms report "var2.t /= 44 ms" severity note; assert var2.e = seven report "var2.e /= seven" severity note; assert var2.c = '%' report "var2.c /= c" severity note; if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then OkayCount := OkayCount + 1; else assert false report "bad return on FUNC2-8" severity note; end if; wait for 1 ns; assert NOT( OkayCount = 3 ) report "***PASSED TEST: c03s02b02x00p01n01i00492" severity NOTE; assert ( OkayCount = 3 ) report "***FAILED TEST: c03s02b02x00p01n01i00492 - Problem assigning record subelements in function." severity ERROR; wait; END PROCESS TESTING; END c03s02b02x00p01n01i00492arch;
-- ################################################################################################# -- # << NEO430 - Data memory ("DMEM") for Lattice ice40 UltraPlus >> # -- # ********************************************************************************************* # -- # BSD 3-Clause License # -- # # -- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # -- # # -- # Redistribution and use in source and binary forms, with or without modification, are # -- # permitted provided that the following conditions are met: # -- # # -- # 1. Redistributions of source code must retain the above copyright notice, this list of # -- # conditions and the following disclaimer. # -- # # -- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # -- # conditions and the following disclaimer in the documentation and/or other materials # -- # provided with the distribution. # -- # # -- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # -- # endorse or promote products derived from this software without specific prior written # -- # permission. # -- # # -- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # -- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # -- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # -- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # -- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # -- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # -- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # -- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # -- # OF THE POSSIBILITY OF SUCH DAMAGE. # -- # ********************************************************************************************* # -- # The NEO430 Processor - https://github.com/stnolting/neo430 # -- ################################################################################################# library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library neo430; use neo430.neo430_package.all; library iCE40UP; use iCE40UP.components.all; entity neo430_dmem is generic ( DMEM_SIZE : natural := 2*1024 -- internal DMEM size in bytes ); port ( clk_i : in std_ulogic; -- global clock line rden_i : in std_ulogic; -- read enable wren_i : in std_ulogic_vector(01 downto 0); -- write enable addr_i : in std_ulogic_vector(15 downto 0); -- address data_i : in std_ulogic_vector(15 downto 0); -- data in data_o : out std_ulogic_vector(15 downto 0) -- data out ); end neo430_dmem; architecture neo430_dmem_rtl of neo430_dmem is -- local signals -- signal acc_en : std_ulogic; signal rdata : std_ulogic_vector(15 downto 0); signal rden : std_ulogic; signal addr : integer; -- RAM -- type dmem_file_t is array (0 to DMEM_SIZE/2-1) of std_ulogic_vector(7 downto 0); signal dmem_file_l : dmem_file_t; signal dmem_file_h : dmem_file_t; -- RAM attribute to inhibit bypass-logic - Intel only! -- attribute ramstyle : string; attribute ramstyle of dmem_file_l : signal is "no_rw_check"; attribute ramstyle of dmem_file_h : signal is "no_rw_check"; -- RAM attribute to inhibit bypass-logic - Lattice ICE40up only! -- attribute syn_ramstyle : string; attribute syn_ramstyle of dmem_file_l : signal is "no_rw_check"; attribute syn_ramstyle of dmem_file_h : signal is "no_rw_check"; -- SPRAM signals -- signal spram_clk : std_logic; signal spram_addr : std_logic_vector(13 downto 0); signal spram_di : std_logic_vector(15 downto 0); signal spram_do : std_logic_vector(15 downto 0); signal spram_be : std_logic_vector(03 downto 0); signal spram_we : std_logic; begin -- Access Control ----------------------------------------------------------- -- ----------------------------------------------------------------------------- acc_en <= '1' when (addr_i >= dmem_base_c) and (addr_i < std_ulogic_vector(unsigned(dmem_base_c) + DMEM_SIZE)) else '0'; addr <= to_integer(unsigned(addr_i(index_size_f(DMEM_SIZE/2) downto 1))); -- word aligned -- Memory Access ------------------------------------------------------------ -- ----------------------------------------------------------------------------- dmem_spram_inst : SP256K port map ( AD => spram_addr, -- I DI => spram_di, -- I MASKWE => spram_be, -- I WE => spram_we, -- I CS => '1', -- I CK => spram_clk, -- I STDBY => '0', -- I SLEEP => '0', -- I PWROFF_N => '1', -- I DO => spram_do -- O ); -- signal type conversion -- spram_clk <= std_logic(clk_i); spram_addr <= std_logic_vector(addr_i(13+1 downto 0+1)); spram_di <= std_logic_vector(data_i(15 downto 0)); spram_we <= '1' when ((acc_en and (wren_i(0) or wren_i(1))) = '1') else '0'; -- global write enable rdata <= std_ulogic_vector(spram_do); spram_be(1 downto 0) <= "11" when (wren_i(0) = '1') else "00"; -- low byte write enable spram_be(3 downto 2) <= "11" when (wren_i(1) = '1') else "00"; -- high byte write enable buffer_ff: process(clk_i) begin -- sanity check if (DMEM_SIZE > 12*1024) then assert false report "D-mem size out of range! Max 12kB!" severity error; end if; -- buffer -- if rising_edge(clk_i) then rden <= rden_i and acc_en; end if; end process buffer_ff; -- output gate -- data_o <= rdata when (rden = '1') else (others => '0'); end neo430_dmem_rtl;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Module: A generic buffer module for the PoC.Stream protocol. -- -- Description: -- ------------------------------------ -- This module implements a generic buffer (FIFO) for the PoC.Stream protocol. -- It is generic in DATA_BITS and in META_BITS as well as in FIFO depths for -- data and meta information. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; library PoC; use PoC.utils.all; use PoC.vectors.all; use PoC.arith_prng; entity Stream_FrameGenerator is generic ( DATA_BITS : POSITIVE := 8; WORD_BITS : POSITIVE := 16; APPend : T_FRAMEGEN_APPend := FRAMEGEN_APP_NONE; FRAMEGROUPS : T_FRAMEGEN_FRAMEGROUP_VECTOR_8 := (0 => C_FRAMEGEN_FRAMEGROUP_EMPTY) ); port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; -- CSE interface Command : in T_FRAMEGEN_COMMAND; Status : out T_FRAMEGEN_STATUS; -- Control interface Pause : in T_SLV_16; FrameGroupIndex : in T_SLV_8; FrameIndex : in T_SLV_8; Sequences : in T_SLV_16; FrameLength : in T_SLV_16; -- OUT Port Out_Valid : out STD_LOGIC; Out_Data : out STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); Out_SOF : out STD_LOGIC; Out_EOF : out STD_LOGIC; Out_Ack : in STD_LOGIC ); end; architecture rtl of Stream_FrameGenerator is type T_STATE is ( ST_IDLE, ST_SEQUENCE_SOF, ST_SEQUENCE_DATA, ST_SEQUENCE_EOF, ST_RANDOM_SOF, ST_RANDOM_DATA, ST_RANDOM_EOF, ST_ERROR ); signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; signal FrameLengthCounter_rst : STD_LOGIC; signal FrameLengthCounter_en : STD_LOGIC; signal FrameLengthCounter_us : UNSIGNED(15 downto 0) := (others => '0'); signal SequencesCounter_rst : STD_LOGIC; signal SequencesCounter_en : STD_LOGIC; signal SequencesCounter_us : UNSIGNED(15 downto 0) := (others => '0'); signal ContentCounter_rst : STD_LOGIC; signal ContentCounter_en : STD_LOGIC; signal ContentCounter_us : UNSIGNED(WORD_BITS - 1 downto 0) := (others => '0'); signal PRNG_rst : STD_LOGIC; signal PRNG_got : STD_LOGIC; signal PRNG_Data : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); begin process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then State <= ST_IDLE; else State <= NextState; end if; end if; end process; process(State, Command, Out_Ack, Sequences, FrameLength, FrameLengthCounter_us, SequencesCounter_us, ContentCounter_us, PRNG_Data) begin NextState <= State; Status <= FRAMEGEN_STATUS_GENERATING; Out_Valid <= '0'; Out_Data <= (others => '0'); Out_SOF <= '0'; Out_EOF <= '0'; FrameLengthCounter_rst <= '0'; FrameLengthCounter_en <= '0'; SequencesCounter_rst <= '0'; SequencesCounter_en <= '0'; ContentCounter_rst <= '0'; ContentCounter_en <= '0'; PRNG_rst <= '0'; PRNG_got <= '0'; case State is when ST_IDLE => Status <= FRAMEGEN_STATUS_IDLE; FrameLengthCounter_rst <= '1'; SequencesCounter_rst <= '1'; ContentCounter_rst <= '1'; PRNG_rst <= '1'; case Command is when FRAMEGEN_CMD_NONE => NULL; when FRAMEGEN_CMD_SEQUENCE => NextState <= ST_SEQUENCE_SOF; when FRAMEGEN_CMD_RANDOM => NextState <= ST_RANDOM_SOF; when FRAMEGEN_CMD_SINGLE_FRAME => NextState <= ST_ERROR; when FRAMEGEN_CMD_SINGLE_FRAMEGROUP => NextState <= ST_ERROR; when FRAMEGEN_CMD_ALL_FRAMES => NextState <= ST_ERROR; when others => NextState <= ST_ERROR; end case; -- generate sequential numbers -- ---------------------------------------------------------------------- when ST_SEQUENCE_SOF => Out_Valid <= '1'; Out_Data <= std_logic_vector(ContentCounter_us); Out_SOF <= '1'; if (Out_Ack = '1') then FrameLengthCounter_en <= '1'; ContentCounter_en <= '1'; NextState <= ST_SEQUENCE_DATA; end if; when ST_SEQUENCE_DATA => Out_Valid <= '1'; Out_Data <= std_logic_vector(ContentCounter_us); if (Out_Ack = '1') then FrameLengthCounter_en <= '1'; ContentCounter_en <= '1'; if (FrameLengthCounter_us = (unsigned(FrameLength) - 2)) then NextState <= ST_SEQUENCE_EOF; end if; end if; when ST_SEQUENCE_EOF => Out_Valid <= '1'; Out_Data <= std_logic_vector(ContentCounter_us); Out_EOF <= '1'; if (Out_Ack = '1') then FrameLengthCounter_rst <= '1'; ContentCounter_en <= '1'; SequencesCounter_en <= '1'; -- if (Pause = (Pause'range => '0')) then if (SequencesCounter_us = (unsigned(Sequences) - 1)) then Status <= FRAMEGEN_STATUS_COMPLETE; NextState <= ST_IDLE; else NextState <= ST_SEQUENCE_SOF; end if; -- end if; end if; -- generate random numbers -- ---------------------------------------------------------------------- when ST_RANDOM_SOF => Out_Valid <= '1'; Out_Data <= PRNG_Data; Out_SOF <= '1'; if (Out_Ack = '1') then FrameLengthCounter_en <= '1'; PRNG_got <= '1'; NextState <= ST_RANDOM_DATA; end if; when ST_RANDOM_DATA => Out_Valid <= '1'; Out_Data <= PRNG_Data; if (Out_Ack = '1') then FrameLengthCounter_en <= '1'; PRNG_got <= '1'; if (FrameLengthCounter_us = (unsigned(FrameLength) - 2)) then NextState <= ST_RANDOM_EOF; end if; end if; when ST_RANDOM_EOF => Out_Valid <= '1'; Out_Data <= PRNG_Data; Out_EOF <= '1'; FrameLengthCounter_rst <= '1'; if (Out_Ack = '1') then PRNG_rst <= '1'; NextState <= ST_IDLE; end if; when ST_ERROR => Status <= FRAMEGEN_STATUS_ERROR; NextState <= ST_IDLE; end case; end process; process(Clock) begin if rising_edge(Clock) then if ((Reset or FrameLengthCounter_rst) = '1') then FrameLengthCounter_us <= (others => '0'); else if (FrameLengthCounter_en = '1') then FrameLengthCounter_us <= FrameLengthCounter_us + 1; end if; end if; end if; end process; process(Clock) begin if rising_edge(Clock) then if ((Reset or SequencesCounter_rst) = '1') then SequencesCounter_us <= (others => '0'); else if (SequencesCounter_en = '1') then SequencesCounter_us <= SequencesCounter_us + 1; end if; end if; end if; end process; process(Clock) begin if rising_edge(Clock) then if ((Reset or ContentCounter_rst) = '1') then ContentCounter_us <= (others => '0'); else if (ContentCounter_en = '1') then ContentCounter_us <= ContentCounter_us + 1; end if; end if; end if; end process; PRNG : entity Poc.alu_prng generic map ( BITS => DATA_BITS ) port map ( clk => Clock, rst => PRNG_rst, got => PRNG_got, val => PRNG_Data ); end;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Module: A generic buffer module for the PoC.Stream protocol. -- -- Description: -- ------------------------------------ -- This module implements a generic buffer (FIFO) for the PoC.Stream protocol. -- It is generic in DATA_BITS and in META_BITS as well as in FIFO depths for -- data and meta information. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; library PoC; use PoC.utils.all; use PoC.vectors.all; use PoC.arith_prng; entity Stream_FrameGenerator is generic ( DATA_BITS : POSITIVE := 8; WORD_BITS : POSITIVE := 16; APPend : T_FRAMEGEN_APPend := FRAMEGEN_APP_NONE; FRAMEGROUPS : T_FRAMEGEN_FRAMEGROUP_VECTOR_8 := (0 => C_FRAMEGEN_FRAMEGROUP_EMPTY) ); port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; -- CSE interface Command : in T_FRAMEGEN_COMMAND; Status : out T_FRAMEGEN_STATUS; -- Control interface Pause : in T_SLV_16; FrameGroupIndex : in T_SLV_8; FrameIndex : in T_SLV_8; Sequences : in T_SLV_16; FrameLength : in T_SLV_16; -- OUT Port Out_Valid : out STD_LOGIC; Out_Data : out STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); Out_SOF : out STD_LOGIC; Out_EOF : out STD_LOGIC; Out_Ack : in STD_LOGIC ); end; architecture rtl of Stream_FrameGenerator is type T_STATE is ( ST_IDLE, ST_SEQUENCE_SOF, ST_SEQUENCE_DATA, ST_SEQUENCE_EOF, ST_RANDOM_SOF, ST_RANDOM_DATA, ST_RANDOM_EOF, ST_ERROR ); signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; signal FrameLengthCounter_rst : STD_LOGIC; signal FrameLengthCounter_en : STD_LOGIC; signal FrameLengthCounter_us : UNSIGNED(15 downto 0) := (others => '0'); signal SequencesCounter_rst : STD_LOGIC; signal SequencesCounter_en : STD_LOGIC; signal SequencesCounter_us : UNSIGNED(15 downto 0) := (others => '0'); signal ContentCounter_rst : STD_LOGIC; signal ContentCounter_en : STD_LOGIC; signal ContentCounter_us : UNSIGNED(WORD_BITS - 1 downto 0) := (others => '0'); signal PRNG_rst : STD_LOGIC; signal PRNG_got : STD_LOGIC; signal PRNG_Data : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); begin process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then State <= ST_IDLE; else State <= NextState; end if; end if; end process; process(State, Command, Out_Ack, Sequences, FrameLength, FrameLengthCounter_us, SequencesCounter_us, ContentCounter_us, PRNG_Data) begin NextState <= State; Status <= FRAMEGEN_STATUS_GENERATING; Out_Valid <= '0'; Out_Data <= (others => '0'); Out_SOF <= '0'; Out_EOF <= '0'; FrameLengthCounter_rst <= '0'; FrameLengthCounter_en <= '0'; SequencesCounter_rst <= '0'; SequencesCounter_en <= '0'; ContentCounter_rst <= '0'; ContentCounter_en <= '0'; PRNG_rst <= '0'; PRNG_got <= '0'; case State is when ST_IDLE => Status <= FRAMEGEN_STATUS_IDLE; FrameLengthCounter_rst <= '1'; SequencesCounter_rst <= '1'; ContentCounter_rst <= '1'; PRNG_rst <= '1'; case Command is when FRAMEGEN_CMD_NONE => NULL; when FRAMEGEN_CMD_SEQUENCE => NextState <= ST_SEQUENCE_SOF; when FRAMEGEN_CMD_RANDOM => NextState <= ST_RANDOM_SOF; when FRAMEGEN_CMD_SINGLE_FRAME => NextState <= ST_ERROR; when FRAMEGEN_CMD_SINGLE_FRAMEGROUP => NextState <= ST_ERROR; when FRAMEGEN_CMD_ALL_FRAMES => NextState <= ST_ERROR; when others => NextState <= ST_ERROR; end case; -- generate sequential numbers -- ---------------------------------------------------------------------- when ST_SEQUENCE_SOF => Out_Valid <= '1'; Out_Data <= std_logic_vector(ContentCounter_us); Out_SOF <= '1'; if (Out_Ack = '1') then FrameLengthCounter_en <= '1'; ContentCounter_en <= '1'; NextState <= ST_SEQUENCE_DATA; end if; when ST_SEQUENCE_DATA => Out_Valid <= '1'; Out_Data <= std_logic_vector(ContentCounter_us); if (Out_Ack = '1') then FrameLengthCounter_en <= '1'; ContentCounter_en <= '1'; if (FrameLengthCounter_us = (unsigned(FrameLength) - 2)) then NextState <= ST_SEQUENCE_EOF; end if; end if; when ST_SEQUENCE_EOF => Out_Valid <= '1'; Out_Data <= std_logic_vector(ContentCounter_us); Out_EOF <= '1'; if (Out_Ack = '1') then FrameLengthCounter_rst <= '1'; ContentCounter_en <= '1'; SequencesCounter_en <= '1'; -- if (Pause = (Pause'range => '0')) then if (SequencesCounter_us = (unsigned(Sequences) - 1)) then Status <= FRAMEGEN_STATUS_COMPLETE; NextState <= ST_IDLE; else NextState <= ST_SEQUENCE_SOF; end if; -- end if; end if; -- generate random numbers -- ---------------------------------------------------------------------- when ST_RANDOM_SOF => Out_Valid <= '1'; Out_Data <= PRNG_Data; Out_SOF <= '1'; if (Out_Ack = '1') then FrameLengthCounter_en <= '1'; PRNG_got <= '1'; NextState <= ST_RANDOM_DATA; end if; when ST_RANDOM_DATA => Out_Valid <= '1'; Out_Data <= PRNG_Data; if (Out_Ack = '1') then FrameLengthCounter_en <= '1'; PRNG_got <= '1'; if (FrameLengthCounter_us = (unsigned(FrameLength) - 2)) then NextState <= ST_RANDOM_EOF; end if; end if; when ST_RANDOM_EOF => Out_Valid <= '1'; Out_Data <= PRNG_Data; Out_EOF <= '1'; FrameLengthCounter_rst <= '1'; if (Out_Ack = '1') then PRNG_rst <= '1'; NextState <= ST_IDLE; end if; when ST_ERROR => Status <= FRAMEGEN_STATUS_ERROR; NextState <= ST_IDLE; end case; end process; process(Clock) begin if rising_edge(Clock) then if ((Reset or FrameLengthCounter_rst) = '1') then FrameLengthCounter_us <= (others => '0'); else if (FrameLengthCounter_en = '1') then FrameLengthCounter_us <= FrameLengthCounter_us + 1; end if; end if; end if; end process; process(Clock) begin if rising_edge(Clock) then if ((Reset or SequencesCounter_rst) = '1') then SequencesCounter_us <= (others => '0'); else if (SequencesCounter_en = '1') then SequencesCounter_us <= SequencesCounter_us + 1; end if; end if; end if; end process; process(Clock) begin if rising_edge(Clock) then if ((Reset or ContentCounter_rst) = '1') then ContentCounter_us <= (others => '0'); else if (ContentCounter_en = '1') then ContentCounter_us <= ContentCounter_us + 1; end if; end if; end if; end process; PRNG : entity Poc.alu_prng generic map ( BITS => DATA_BITS ) port map ( clk => Clock, rst => PRNG_rst, got => PRNG_got, val => PRNG_Data ); end;
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Sun Sep 22 02:35:49 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode synth_stub -- d:/github/Digital-Hardware-Modelling/xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_auto_pc_0/zybo_zynq_design_auto_pc_0_stub.vhdl -- Design : zybo_zynq_design_auto_pc_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity zybo_zynq_design_auto_pc_0 is Port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end zybo_zynq_design_auto_pc_0; architecture stub of zybo_zynq_design_auto_pc_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2"; begin end;
library IEEE; use ieee.std_logic_1164.all; entity program_counter is port( input : in std_logic_vector(31 downto 0); clk, rst, pre, ce, control : in std_logic; output : out std_logic_vector(31 downto 0) ); end program_counter; architecture behav of program_counter is begin PC : entity work.thirty_two_bit_register(behav) port map(input, clk, rst, pre, control, output); end behav;
-- -- Knobs Galore - a free phase distortion synthesizer -- Copyright (C) 2015 Ilmo Euro -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.common.all; entity synthesizer_test is end entity; architecture synthesizer_test_impl of synthesizer_test is begin end architecture;
-- -- Knobs Galore - a free phase distortion synthesizer -- Copyright (C) 2015 Ilmo Euro -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.common.all; entity synthesizer_test is end entity; architecture synthesizer_test_impl of synthesizer_test is begin end architecture;
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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S1BmStfGQHnYs1Amd9GMgt4/HvDhFfAbglbu9Nl3zPbwrhcP/l/b0mAjQcC2qQo/p4RRmgUMNMtL h2TdltgiJw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block U187WAt6Y0njrfOh96RKw/lPfTsjqIhll5EQ+CPgpaigt72Ny9p0KV+rVz+Q7O12HqElBRi+YsEf vWL2bWTrGeiB3p8vqxYm23E3YlxBY7buHxlKNUF4/2asmFmXIlsjGrkihsfwqo+V7KorNoVLyowA MzKrhzU+jeGYzJtp1uQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: ddr_oreg -- File: ddr_oreg.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: DDR output reg with tech selection ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library techmap; use techmap.gencomp.all; use techmap.allddr.all; entity ddr_oreg is generic (tech : integer; arch : integer := 0); port ( Q : out std_ulogic; C1 : in std_ulogic; C2 : in std_ulogic; CE : in std_ulogic; D1 : in std_ulogic; D2 : in std_ulogic; R : in std_ulogic; S : in std_ulogic); end; architecture rtl of ddr_oreg is begin inf : if not ((tech = lattice) or (is_unisim(tech) = 1) or (tech = axcel) or (tech = axdsp) or (tech = apa3) or (tech = apa3e) or (tech = apa3l)) generate inf0 : gen_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S); end generate; ax : if (tech = axcel) or (tech = axdsp) generate ax0 : axcel_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S); end generate; pa3 : if (tech = apa3) generate pa0 : apa3_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S); end generate; pa3e : if (tech = apa3e) generate pa0 : apa3e_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S); end generate; pa3l : if (tech = apa3l) generate pa0 : apa3l_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S); end generate; lat : if tech = lattice generate lat0 : ec_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S); end generate; xil : if is_unisim(tech) = 1 generate xil0 : unisim_oddr_reg generic map (tech, arch) port map (Q, C1, C2, CE, D1, D2, R, S); end generate; --pragma translate_off assert (tech /= easic45) and (tech /= easic90) report "ddr_oreg: Not supported on eASIC. Use DDR pad instead." severity failure; --pragma translate_on end;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity issue is port (sig_gt, sig_ge, sig_lt, sig_le : out boolean; uns_gt, uns_ge, uns_lt, uns_le : out boolean); end issue; architecture beh of issue is begin -- all of those works uns_gt <= (unsigned'("1111") > unsigned'("0111")); uns_ge <= (unsigned'("1111") >= unsigned'("0111")); uns_lt <= (unsigned'("1111") < unsigned'("0111")); uns_le <= (unsigned'("1111") <= unsigned'("0111")); sig_gt <= (signed'("1111") > signed'("0111")); sig_ge <= (signed'("1111") >= signed'("0111")); sig_lt <= (signed'("1111") < signed'("0111")); sig_le <= (signed'("1111") <= signed'("0111")); end architecture beh;
---------------------------------------------------------------------------------- --Ben Oztalay, 2009-2010 -- --This VHDL code is part of the OZ-3, a 32-bit processor -- --Module Title: RegFile --Module Description: -- The register file of the OZ-3. It holds 32 32-bit registers, -- with register 0 hardwired to 0. It has three outputs and one -- input port, with four address ports to go with each. All of the -- ports can be used at once, and the register file writes on -- the falling edge. If it's being written to at address 0, the register -- file simply doesn't respond. ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity RegFile is Port ( clock : in STD_LOGIC; reset : in STD_LOGIC; write_e : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR(31 downto 0); r_addr1 : in STD_LOGIC_VECTOR(4 downto 0); r_addr2 : in STD_LOGIC_VECTOR(4 downto 0); r_addr3 : in STD_LOGIC_VECTOR(4 downto 0); w_addr1 : in STD_LOGIC_VECTOR(4 downto 0); data_out_1 : out STD_LOGIC_VECTOR(31 downto 0); --Operand A data_out_2 : out STD_LOGIC_VECTOR(31 downto 0); --Operand B data_out_3 : out STD_LOGIC_VECTOR(31 downto 0)); --Data to write to memory or mix with incoming data end RegFile; --from memory architecture Behavioral of RegFile is begin --The main process of the register file main: process (clock, reset, r_addr1, r_addr2, r_addr3) is type reg_array is array (31 downto 0) of --This new type of array was made to make a STD_LOGIC_VECTOR(31 downto 0); --2D array of 32x32 variable reg_file: reg_array := (others => x"00000000"); begin if falling_edge(clock) then if reset = '1' then --Reset reg_file := (others => x"00000000"); elsif write_e = '1' then --If it's a write operation if w_addr1 /= b"00000" then --and if address zero isn't trying to be written to reg_file(conv_integer(unsigned(w_addr1))) := data_in; --then write to the array end if; end if; end if; --All of the data outputs are asynchronous data_out_1 <= reg_file(conv_integer(unsigned(r_addr1))); data_out_2 <= reg_file(conv_integer(unsigned(r_addr2))); data_out_3 <= reg_file(conv_integer(unsigned(r_addr3))); end process; end Behavioral;
---------------------------------------------------------------------------------------------- -- -- Generated by X-HDL Verilog Translator - Version 4.0.0 Apr. 30, 2006 -- Wed Jun 17 2009 01:00:41 -- -- Input file : /home/samsonn/SandBox_LBranch_11.2/env/Databases/ip/src2/L/mig_v3_2/data/dlib/virtex6/ddr3_sdram/verilog/rtl/ecc/ecc_buf.v -- Component name : ecc_buf -- Author : -- Company : -- -- Description : -- -- ---------------------------------------------------------------------------------------------- library UNISIM; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; -- use UNISIM.VCOMPONENTS.all; entity ecc_buf is generic ( TCQ : integer := 100; PAYLOAD_WIDTH : integer := 64; DATA_BUF_ADDR_WIDTH : integer := 4; DATA_BUF_OFFSET_WIDTH : integer := 1; DATA_WIDTH : integer := 64 ); port ( -- Outputs -- Inputs -- RMW architecture supports only 16 data buffer entries. -- Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but -- assume the upper bits are used for tagging. -- block: rd_buffer_ram rd_merge_data : out std_logic_vector(4 * DATA_WIDTH - 1 downto 0); clk : in std_logic; rst : in std_logic; rd_data_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0); rd_data_offset : in std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0); wr_data_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0); wr_data_offset : in std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0); rd_data : in std_logic_vector(4 * PAYLOAD_WIDTH - 1 downto 0); wr_ecc_buf : in std_logic ); end entity ecc_buf; architecture trans of ecc_buf is component RAM32M generic ( INIT_A : bit_vector(63 downto 0) := X"0000000000000000"; INIT_B : bit_vector(63 downto 0) := X"0000000000000000"; INIT_C : bit_vector(63 downto 0) := X"0000000000000000"; INIT_D : bit_vector(63 downto 0) := X"0000000000000000" ); port ( DOA : out std_logic_vector (1 downto 0); DOB : out std_logic_vector (1 downto 0); DOC : out std_logic_vector (1 downto 0); DOD : out std_logic_vector (1 downto 0); ADDRA : in std_logic_vector(4 downto 0); ADDRB : in std_logic_vector(4 downto 0); ADDRC : in std_logic_vector(4 downto 0); ADDRD : in std_logic_vector(4 downto 0); DIA : in std_logic_vector (1 downto 0); DIB : in std_logic_vector (1 downto 0); DIC : in std_logic_vector (1 downto 0); DID : in std_logic_vector (1 downto 0); WCLK : in std_ulogic; WE : in std_ulogic ); end component; function f_RAM_CNT (FULL_RAM_CNT: integer; REMAINDER : integer) return integer is begin if (REMAINDER = 0) then return FULL_RAM_CNT ; else return FULL_RAM_CNT + 1 ; end if; end f_RAM_CNT; function nCOPY (A : in std_logic; B : in integer) return std_logic_vector is variable tmp : std_logic_vector(B - 1 downto 0); begin for i in 0 to B - 1 loop tmp(i) := A; end loop; return tmp; end function nCOPY; constant BUF_WIDTH : integer := 4 * DATA_WIDTH; constant FULL_RAM_CNT : integer := (BUF_WIDTH / 6); constant REMAINDER : integer := BUF_WIDTH mod 6; constant RAM_CNT : integer := f_RAM_CNT(FULL_RAM_CNT ,REMAINDER ); constant RAM_WIDTH : integer := (RAM_CNT * 6); signal buf_wr_addr : std_logic_vector(4 downto 0); signal buf_rd_addr_r : std_logic_vector(4 downto 0); signal payload : std_logic_vector(4 * DATA_WIDTH - 1 downto 0); signal h : integer; signal buf_out_data : std_logic_vector(RAM_WIDTH - 1 downto 0); signal buf_in_data : std_logic_vector(RAM_WIDTH - 1 downto 0); begin int0 : if (DATA_BUF_ADDR_WIDTH >= 4) generate process (clk) begin if (clk'event and clk = '1') then buf_rd_addr_r <= (wr_data_addr(3 downto 0) & wr_data_offset) after (TCQ)*1 ps; end if; end process; buf_wr_addr <= (rd_data_addr(3 downto 0) & rd_data_offset); end generate; int1 : if (not(DATA_BUF_ADDR_WIDTH >= 4)) generate process (clk) begin if (clk'event and clk = '1') then buf_rd_addr_r <= ( nCOPY('0',4 - DATA_BUF_ADDR_WIDTH) & wr_data_addr(DATA_BUF_ADDR_WIDTH - 1 downto 0) & wr_data_offset) after (TCQ)*1 ps; end if; end process; buf_wr_addr <= ( nCOPY('0',4 - DATA_BUF_ADDR_WIDTH) & rd_data_addr(DATA_BUF_ADDR_WIDTH - 1 downto 0) & rd_data_offset); end generate; process (rd_data) begin for h in 0 to 3 loop payload((DATA_WIDTH*h)+DATA_WIDTH-1 downto h * DATA_WIDTH) <= rd_data((PAYLOAD_WIDTH*h)+DATA_WIDTH-1 downto h * PAYLOAD_WIDTH); end loop; end process; int2 : if (REMAINDER = 0) generate buf_in_data <= payload; end generate; int3 : if (not(REMAINDER = 0)) generate buf_in_data <= nCOPY('0',6 - REMAINDER) & payload; end generate; rd_buffer_ram : for i in 0 to RAM_CNT - 1 generate RAM32M0 : RAM32M generic map ( INIT_A => "0000000000000000000000000000000000000000000000000000000000000000", INIT_B => "0000000000000000000000000000000000000000000000000000000000000000", INIT_C => "0000000000000000000000000000000000000000000000000000000000000000", INIT_D => "0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DOA => buf_out_data((i * 6) + 4 + 1 downto (i * 6) + 4), DOB => buf_out_data((i * 6) + 2 + 1 downto (i * 6) + 2), DOC => buf_out_data((i * 6) + 0 + 1 downto (i * 6) + 0), DOD => open, DIA => buf_in_data((i * 6) + 4 + 1 downto (i * 6) + 4), DIB => buf_in_data((i * 6) + 2 + 1 downto (i * 6) + 2), DIC => buf_in_data((i * 6) + 0 + 1 downto (i * 6) + 0), DID => "00", ADDRA => buf_rd_addr_r, ADDRB => buf_rd_addr_r, ADDRC => buf_rd_addr_r, ADDRD => buf_wr_addr, WE => wr_ecc_buf, WCLK => clk ); end generate; rd_merge_data <= buf_out_data(4 * DATA_WIDTH - 1 downto 0); end architecture trans;
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2014 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file fr_cmplr_v6_3_a7495039d232075b.vhd when simulating -- the core, fr_cmplr_v6_3_a7495039d232075b. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY fr_cmplr_v6_3_a7495039d232075b IS PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_data_tvalid : IN STD_LOGIC; s_axis_data_tready : OUT STD_LOGIC; s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_data_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); event_s_data_chanid_incorrect : OUT STD_LOGIC ); END fr_cmplr_v6_3_a7495039d232075b; ARCHITECTURE fr_cmplr_v6_3_a7495039d232075b_a OF fr_cmplr_v6_3_a7495039d232075b IS -- synthesis translate_off COMPONENT wrapped_fr_cmplr_v6_3_a7495039d232075b PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_data_tvalid : IN STD_LOGIC; s_axis_data_tready : OUT STD_LOGIC; s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_data_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); event_s_data_chanid_incorrect : OUT STD_LOGIC ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_fr_cmplr_v6_3_a7495039d232075b USE ENTITY XilinxCoreLib.fir_compiler_v6_3(behavioral) GENERIC MAP ( c_accum_op_path_widths => "45,45", c_accum_path_widths => "45,45", c_channel_pattern => "fixed", c_coef_file => "fr_cmplr_v6_3_a7495039d232075b.mif", c_coef_file_lines => 140, c_coef_mem_packing => 0, c_coef_memtype => 2, c_coef_path_sign => "0,0", c_coef_path_src => "0,0", c_coef_path_widths => "16,16", c_coef_reload => 0, c_coef_width => 16, c_col_config => "4", c_col_mode => 1, c_col_pipe_len => 4, c_component_name => "fr_cmplr_v6_3_a7495039d232075b", c_config_packet_size => 0, c_config_sync_mode => 0, c_config_tdata_width => 1, c_data_has_tlast => 0, c_data_mem_packing => 1, c_data_memtype => 1, c_data_path_sign => "0,0", c_data_path_src => "0,1", c_data_path_widths => "24,24", c_data_width => 24, c_datapath_memtype => 1, c_decim_rate => 35, c_ext_mult_cnfg => "none", c_filter_type => 1, c_filts_packed => 0, c_has_aclken => 1, c_has_aresetn => 0, c_has_config_channel => 0, c_input_rate => 1, c_interp_rate => 1, c_ipbuff_memtype => 0, c_latency => 12, c_m_data_has_tready => 0, c_m_data_has_tuser => 1, c_m_data_tdata_width => 64, c_m_data_tuser_width => 1, c_mem_arrangement => 1, c_num_channels => 2, c_num_filts => 1, c_num_madds => 4, c_num_reload_slots => 1, c_num_taps => 248, c_opbuff_memtype => 0, c_opt_madds => "none", c_optimization => 0, c_output_path_widths => "25,25", c_output_rate => 35, c_output_width => 25, c_oversampling_rate => 1, c_reload_tdata_width => 1, c_round_mode => 4, c_s_data_has_fifo => 0, c_s_data_has_tuser => 1, c_s_data_tdata_width => 48, c_s_data_tuser_width => 1, c_symmetry => 1, c_xdevicefamily => "virtex6", c_zero_packing_factor => 1 ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_fr_cmplr_v6_3_a7495039d232075b PORT MAP ( aclk => aclk, aclken => aclken, s_axis_data_tvalid => s_axis_data_tvalid, s_axis_data_tready => s_axis_data_tready, s_axis_data_tuser => s_axis_data_tuser, s_axis_data_tdata => s_axis_data_tdata, m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tuser => m_axis_data_tuser, m_axis_data_tdata => m_axis_data_tdata, event_s_data_chanid_incorrect => event_s_data_chanid_incorrect ); -- synthesis translate_on END fr_cmplr_v6_3_a7495039d232075b_a;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --============================================================================-- -- Design unit : DMA2AHB_Package (package declaration) -- -- File name : dma2ahb_pkg.vhd -- -- Purpose : Interface package for AMBA AHB master interface with DMA input -- -- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A, -- 13th May 1999, issue A, first release, ARM Limited -- The document can be retrieved from http://www.arm.com -- AMBA is a trademark of ARM Limited. -- ARM is a registered trademark of ARM Limited. -- -- Note : Naming convention according to AMBA(TM) Specification: -- Signal names are in upper case, except for the following: -- A lower case 'n' in the name indicates that the signal -- is active low. -- Constant names are in upper case. -- The least significant bit of an array is located to the right, -- carrying the index number zero. -- -- Limitations : See DMA2AHB VHDL core -- -- Library : gaisler -- -- Authors : Aeroflex Gaisler AB -- -- Contact : mailto:support@gaisler.com -- http://www.gaisler.com -- -- Disclaimer : All information is provided "as is", there is no warranty that -- the information is correct or suitable for any purpose, -- neither implicit nor explicit. -- -------------------------------------------------------------------------------- -- Version Author Date Changes -- -- 1.4 SH 1 Jul 2005 Support for fixed length incrementing bursts -- Support for record types -- 1.5 SH 1 Sep 2005 New library gaisler -- 1.6 SH 20 Sep 2005 Added transparent HSIZE support -- 1.7 SH 6 Dec 2007 Added syncrst generic -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; package DMA2AHB_Package is ----------------------------------------------------------------------------- -- Direct Memory Access to AMBA AHB Master Interface Types ----------------------------------------------------------------------------- type DMA_In_Type is record Reset: Std_Logic; Address: Std_Logic_Vector(32-1 downto 0); Data: Std_Logic_Vector(32-1 downto 0); Request: Std_Logic; -- access requested Burst: Std_Logic; -- burst requested Beat: Std_Logic_Vector(1 downto 0); -- incrementing beat Size: Std_Logic_Vector(1 downto 0); -- size Store: Std_Logic; -- data write requested Lock: Std_Logic; -- locked Transfer end record; type DMA_Out_Type is record Grant: Std_Logic; -- access accepted OKAY: Std_Logic; -- write access ready Ready: Std_Logic; -- read data ready Retry: Std_Logic; -- retry Fault: Std_Logic; -- error occured Data: Std_Logic_Vector(32-1 downto 0); end record; -- constants for HBURST definition (used with dma_in_type.Beat) constant HINCR: Std_Logic_Vector(1 downto 0) := "00"; constant HINCR4: Std_Logic_Vector(1 downto 0) := "01"; constant HINCR8: Std_Logic_Vector(1 downto 0) := "10"; constant HINCR16: Std_Logic_Vector(1 downto 0) := "11"; -- constants for HSIZE definition (used with dma_in_type.Size) constant HSIZE8: Std_Logic_Vector(1 downto 0) := "00"; constant HSIZE16: Std_Logic_Vector(1 downto 0) := "01"; constant HSIZE32: Std_Logic_Vector(1 downto 0) := "10"; ----------------------------------------------------------------------------- -- Direct Memory Access to AMBA AHB Master Interface ----------------------------------------------------------------------------- component DMA2AHB is generic( hindex: in Integer := 0; vendorid: in Integer := 0; deviceid: in Integer := 0; version: in Integer := 0; syncrst: in Integer := 1; boundary: in Integer := 1); port( -- AMBA AHB system signals HCLK: in Std_ULogic; HRESETn: in Std_ULogic; -- Direct Memory Access Interface DMAIn: in DMA_In_Type; DMAOut: out DMA_OUt_Type; -- AMBA AHB Master Interface AHBIn: in AHB_Mst_In_Type; AHBOut: out AHB_Mst_Out_Type); end component DMA2AHB; end package DMA2AHB_Package; --===============================================--
------------------------------------------------------------------------------- -- rs232_usb_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library xps_uartlite_v1_02_a; use xps_uartlite_v1_02_a.all; entity rs232_usb_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to 0); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 3); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 31); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to 1); Sl_MWrErr : out std_logic_vector(0 to 1); Sl_MRdErr : out std_logic_vector(0 to 1); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to 1); RX : in std_logic; TX : out std_logic; Interrupt : out std_logic ); attribute x_core_info : STRING; attribute x_core_info of rs232_usb_wrapper : entity is "xps_uartlite_v1_02_a"; end rs232_usb_wrapper; architecture STRUCTURE of rs232_usb_wrapper is component xps_uartlite is generic ( C_FAMILY : STRING; C_SPLB_CLK_FREQ_HZ : INTEGER; C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_SPLB_AWIDTH : INTEGER; C_SPLB_DWIDTH : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_SUPPORT_BURSTS : INTEGER; C_SPLB_NATIVE_DWIDTH : INTEGER; C_BAUDRATE : INTEGER; C_DATA_BITS : INTEGER; C_USE_PARITY : INTEGER; C_ODD_PARITY : INTEGER ); port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); RX : in std_logic; TX : out std_logic; Interrupt : out std_logic ); end component; begin RS232_USB : xps_uartlite generic map ( C_FAMILY => "spartan6", C_SPLB_CLK_FREQ_HZ => 50000000, C_BASEADDR => X"84000000", C_HIGHADDR => X"8400ffff", C_SPLB_AWIDTH => 32, C_SPLB_DWIDTH => 32, C_SPLB_P2P => 0, C_SPLB_MID_WIDTH => 1, C_SPLB_NUM_MASTERS => 2, C_SPLB_SUPPORT_BURSTS => 0, C_SPLB_NATIVE_DWIDTH => 32, C_BAUDRATE => 9600, C_DATA_BITS => 8, C_USE_PARITY => 0, C_ODD_PARITY => 0 ) port map ( SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_PAValid => PLB_PAValid, PLB_masterID => PLB_masterID, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_size => PLB_size, PLB_type => PLB_type, PLB_wrDBus => PLB_wrDBus, PLB_UABus => PLB_UABus, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_MSize => PLB_MSize, PLB_lockErr => PLB_lockErr, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_rdDBus => Sl_rdDBus, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_wrBTerm => Sl_wrBTerm, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdBTerm => Sl_rdBTerm, Sl_MIRQ => Sl_MIRQ, RX => RX, TX => TX, Interrupt => Interrupt ); end architecture STRUCTURE;
---------------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- Author: Mihaita Nagy -- Copyright 2014 Digilent, Inc. ---------------------------------------------------------------------------- -- -- Create Date: 14:24:36 04/02/2013 -- Design Name: -- Module Name: PdmDes - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- This module represents the deserializer of the microphone data. The module generates -- the pdm_m_clk_o signal to the ADMP421 Microphone (M_CLK) and data is read on the positive -- edge of this signal. -- -- Then the module deserializes the signal on 16 bits when en_i = '1' (it means that recoding -- is going on) -- -- The module also generates the pdm_clk_rising_o signal, that is active when the positive edge of the -- pdm_m_clk_o signal occures. This signal is used in the VGA controller, the MicDisplay component to -- display audio data on the screen. The signal is two system clock period length, in order to make it -- easier the synchronizing with the VGA clock domain (108MHz) -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ------------------------------------------------------------------------ -- Module Declaration ------------------------------------------------------------------------ entity PdmDes is generic( C_NR_OF_BITS : integer := 16; C_SYS_CLK_FREQ_MHZ : integer := 100; C_PDM_FREQ_HZ : integer := 2000000 ); port( clk_i : in std_logic; en_i : in std_logic; -- Enable deserializing (during record) done_o : out std_logic; -- Signaling that 16 bits are deserialized data_o : out std_logic_vector(C_NR_OF_BITS - 1 downto 0); -- output deserialized data -- PDM pdm_m_clk_o : out std_logic; -- Output M_CLK signal to the microphone pdm_m_data_i : in std_logic; -- Input PDM data from the microphone pdm_lrsel_o : out std_logic; -- Set to '0', therefore data is read on the positive edge pdm_clk_rising_o : out std_logic -- Signaling the rising edge of M_CLK, used by the MicDisplay -- component in the VGA controller ); end PdmDes; architecture Behavioral of PdmDes is ------------------------------------------------------------------------ -- Signal Declarations ------------------------------------------------------------------------ -- Divider to create pdm_m_clk_0 signal cnt_clk : integer range 0 to 127 := 0; -- Internal pdm_m_clk_o signal signal clk_int : std_logic := '0'; -- Piped clk_int signal to create pdm_clk_rising signal pdm_clk_rising : std_logic; -- Shift register to deserialize incoming microphone data signal pdm_tmp : std_logic_vector((C_NR_OF_BITS - 1) downto 0); -- Count the number of bits signal cnt_bits : integer range 0 to 31 := 0; -- To create a pdm_clk_rising impulse of two clock period length -- This signal will be registered in the MicDisplay module on the 108MHz pxlclk signal pdm_clk_rising_reg : std_logic_vector (2 downto 0); signal en_int : std_logic; signal done_int : std_logic; ------------------------------------------------------------------------ -- Module Implementation ------------------------------------------------------------------------ begin -- with L/R Sel tied to GND => output = DATA1 (rising edge) pdm_lrsel_o <= '0'; -- Synchronize the enable input SYNC: process(clk_i) begin if rising_edge(clk_i) then en_int <= en_i; end if; end process SYNC; ------------------------------------------------------------------------ -- Deserializer ------------------------------------------------------------------------ -- Sample input serial data process SHFT_IN: process(clk_i) begin if rising_edge(clk_i) then if pdm_clk_rising = '1' then pdm_tmp <= pdm_tmp(C_NR_OF_BITS-2 downto 0) & pdm_m_data_i; end if; end if; end process SHFT_IN; -- Count the number of sampled bits CNT: process(clk_i) begin if rising_edge(clk_i) then if en_int = '0' then cnt_bits <= 0; else if pdm_clk_rising = '1' then if cnt_bits = (C_NR_OF_BITS-1) then cnt_bits <= 0; else cnt_bits <= cnt_bits + 1; end if; end if; end if; end if; end process CNT; -- Generate the done signal process(clk_i) begin if rising_edge(clk_i) then if pdm_clk_rising = '1' then if cnt_bits = 0 then if en_int = '1' then done_int <= '1'; data_o <= pdm_tmp; end if; end if; else done_int <= '0'; end if; end if; end process; done_o <= done_int; -- Generate PDM Clock, that runs independent from the enable signal, therefore -- the onboard microphone will always send data, that is displayed on the VGA screen -- using the MicDisplay component CLK_CNT: process(clk_i) begin if rising_edge(clk_i) then if cnt_clk = (((C_SYS_CLK_FREQ_MHZ*1000000)/(C_PDM_FREQ_HZ*2))-1) then cnt_clk <= 0; clk_int <= not clk_int; if clk_int = '0' then pdm_clk_rising <= '1'; end if; else cnt_clk <= cnt_clk + 1; pdm_clk_rising <= '0'; end if; end if; end process CLK_CNT; pdm_m_clk_o <= clk_int; -- Register pdm_clk_rising -- to create a two clock period length impulse RISING_IMP: process(clk_i) begin if rising_edge(clk_i) then pdm_clk_rising_reg <= pdm_clk_rising_reg (1 downto 0) & pdm_clk_rising; end if; end process RISING_IMP; -- Assign the output pdm_clk_rising impulse ASSIGN_PDM_CLK_RISING_IMP: process(clk_i) begin if rising_edge(clk_i) then pdm_clk_rising_o <= (pdm_clk_rising_reg(0) or pdm_clk_rising_reg(1)) and (not pdm_clk_rising_reg(2)); end if; end process ASSIGN_PDM_CLK_RISING_IMP; end Behavioral;
-- TestBench Template LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS -- Component Declaration COMPONENT spaceinvaders PORT( clk : IN std_logic; reset : IN std_logic; red : OUT std_logic_vector(3 downto 0); green : OUT std_logic_vector(3 downto 0); blue : OUT std_logic_vector(3 downto 0); hsync : OUT std_logic; vsync : OUT std_logic; leds : OUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; --Outputs signal red : STD_LOGIC_VECTOR (3 downto 0); signal green : STD_LOGIC_VECTOR (3 downto 0); signal blue : STD_LOGIC_VECTOR (3 downto 0); signal hsync : std_logic; signal vsync : std_logic; signal reset : std_logic; signal leds : STD_LOGIC_VECTOR (3 downto 0); -- Clock period definitions constant clk_period : time := 31.25 ns; --constant clk_period : time := 10 ns; --constant clk_period : time := 7.518ns; BEGIN -- Component Instantiation uut: spaceinvaders PORT MAP( clk => clk, red => red, green => green, blue => blue, hsync => hsync, vsync => vsync, reset => reset, leds => leds ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for clk_period*10; wait; end process; END;
-- This Source Code Form is subject to the terms of the Mozilla Public -- License, v. 2.0. If a copy of the MPL was not distributed with this file, -- You can obtain one at http://mozilla.org/MPL/2.0/. -- -- Copyright (c) 2015, Olof Kraigher olof.kraigher@gmail.com use std.textio.all; library vunit_lib; context vunit_lib.vunit_context; use work.memory_model_ptype_pkg.all; entity tb_memory_model is generic ( runner_cfg : runner_cfg_t); end entity; architecture tb of tb_memory_model is begin main : process variable ptr, ptr2, ptr3 : natural; variable memory_model : memory_model_t; begin test_runner_setup(runner, runner_cfg); while test_suite loop memory_model.reset(memory_size_in_bytes => 2**10); if run("test that memory can be allocated") then ptr := memory_model.allocate(num_bytes => 11); check_equal(ptr, 0); elsif run("test that two allocations does not share base address") then ptr := memory_model.allocate(num_bytes => 10); ptr2 := memory_model.allocate(num_bytes => 20); ptr3 := memory_model.allocate(num_bytes => 3); check(ptr /= ptr2); check_equal(ptr, 0); check_equal(ptr2, 10); check_equal(ptr3, 30); elsif run("test that allocate with alignment") then for alignment in 1 to 5 loop ptr := memory_model.allocate(num_bytes => 2**(alignment-1), alignment => 2**alignment); check_equal(ptr mod 2**alignment, 0); end loop; elsif run("test read and write byte") then ptr := memory_model.allocate(num_bytes => 1); memory_model.write_byte(ptr, 77); check_equal(memory_model.read_byte(ptr), 77); end if; end loop; test_runner_cleanup(runner); end process; end architecture; -- vunit_pragma fail_on_warning -- vunit_pragma run_all_in_same_sim
------------------------------------------------------------------------------- -- system_xps_intc_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library xps_intc_v2_01_a; use xps_intc_v2_01_a.all; entity system_xps_intc_0_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to 63); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to 5); Intr : in std_logic_vector(1 downto 0); Irq : out std_logic ); end system_xps_intc_0_wrapper; architecture STRUCTURE of system_xps_intc_0_wrapper is component xps_intc is generic ( C_FAMILY : STRING; C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_SPLB_AWIDTH : INTEGER; C_SPLB_DWIDTH : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NATIVE_DWIDTH : INTEGER; C_SPLB_SUPPORT_BURSTS : INTEGER; C_NUM_INTR_INPUTS : INTEGER; C_KIND_OF_INTR : std_logic_vector(31 downto 0); C_KIND_OF_EDGE : std_logic_vector(31 downto 0); C_KIND_OF_LVL : std_logic_vector(31 downto 0); C_HAS_IPR : INTEGER; C_HAS_SIE : INTEGER; C_HAS_CIE : INTEGER; C_HAS_IVR : INTEGER; C_IRQ_IS_LEVEL : INTEGER; C_IRQ_ACTIVE : std_logic ); port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Intr : in std_logic_vector((C_NUM_INTR_INPUTS-1) downto 0); Irq : out std_logic ); end component; begin xps_intc_0 : xps_intc generic map ( C_FAMILY => "virtex5", C_BASEADDR => X"81800000", C_HIGHADDR => X"8180ffff", C_SPLB_AWIDTH => 32, C_SPLB_DWIDTH => 64, C_SPLB_P2P => 0, C_SPLB_NUM_MASTERS => 6, C_SPLB_MID_WIDTH => 3, C_SPLB_NATIVE_DWIDTH => 32, C_SPLB_SUPPORT_BURSTS => 0, C_NUM_INTR_INPUTS => 2, C_KIND_OF_INTR => B"11111111111111111111111111111100", C_KIND_OF_EDGE => B"11111111111111111111111111111111", C_KIND_OF_LVL => B"11111111111111111111111111111111", C_HAS_IPR => 1, C_HAS_SIE => 1, C_HAS_CIE => 1, C_HAS_IVR => 1, C_IRQ_IS_LEVEL => 1, C_IRQ_ACTIVE => '1' ) port map ( SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_PAValid => PLB_PAValid, PLB_masterID => PLB_masterID, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_size => PLB_size, PLB_type => PLB_type, PLB_wrDBus => PLB_wrDBus, PLB_UABus => PLB_UABus, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_MSize => PLB_MSize, PLB_lockErr => PLB_lockErr, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_rdDBus => Sl_rdDBus, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_wrBTerm => Sl_wrBTerm, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdBTerm => Sl_rdBTerm, Sl_MIRQ => Sl_MIRQ, Intr => Intr, Irq => Irq ); end architecture STRUCTURE;
---------------------------------------------------------------------------- ---- Create Date: 00:12:45 10/23/2010 ---- Design Name: pic ---- Project Name: PIC ---- Description: ---- A Programmable Interrupt Controller which can handle upto 8 ---- ---- level triggered interrupts.The operating modes available are ---- ---- polling fixed priority modes. ---- ---- ---------------------------------------------------------------------------- ---- ---- ---- This file is a part of the pic project at ---- ---- http://www.opencores.org/ ---- ---- ---- ---- Author(s): ---- ---- Vipin Lal, lalnitt@gmail.com ---- ---- ---- ---------------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2010 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer. ---- ---- ---- ---- This source file is free software; you can redistribute it ---- ---- and/or modify it under the terms of the GNU Lesser General ---- ---- Public License as published by the Free Software Foundation; ---- ---- either version 2.1 of the License, or (at your option) any ---- ---- later version. ---- ---- ---- ---- This source is distributed in the hope that it will be ---- ---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ---- PURPOSE. See the GNU Lesser General Public License for more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU Lesser General ---- ---- Public License along with this source; if not, download it ---- ---- from http://www.opencores.org/lgpl.shtml ---- ---- ---- ---------------------------------------------------------------------------- library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity PIC is port ( CLK_I : in std_logic; -- Clock. RST_I : in std_logic; -- Reset IR : in unsigned(7 downto 0); -- Interrupt requests from peripherals. DATABUS : inout unsigned(7 downto 0); -- Data bus between processor PIC. INTR_O : out std_logic; -- Interrupt Request pin of processor. INTA_I : in std_logic -- Interrupt ack. ); end entity PIC; architecture BEHAVIORAL of PIC is type state_type is ( RESET_S, GET_COMMANDS, JUMP_INT_METHOD, START_POLLING, TX_INT_INFO_POLLING, ACK_ISR_DONE, ACK_TXINFO_RXD, START_PRIORITY_CHECK, TX_INT_INFO_PRIORITY, ACK_TXINFO_RXD_PRIORITY, ACK_ISR_DONE_PT ); signal next_s : state_type :=reset_s; signal int_type : unsigned(1 downto 0):="01"; signal int_index, count_cmd : integer := 0; type prior_table is array (0 to 7) of unsigned(2 downto 0); signal pt : prior_table := (others => (others => '0')); signal int_pt : unsigned(2 downto 0):="000"; signal flag, flag1 : std_logic := '0'; -- These flags are used for timing purposes. begin process (CLK_I, RST_I) is begin if (RST_I = '1') then next_s <= reset_s; elsif (rising_edge(CLK_I)) then flag <= INTA_I; case next_s is when reset_s => -- initialze signals to zero. flag <= '0'; flag1 <= '0'; int_type <= "00"; int_index <= 0; count_cmd <= 0; int_pt <= "000"; pt <= (others => (others => '0')); if (RST_I = '0') then next_s <= get_commands; else next_s <= reset_s; end if; DATABUS <= (others => 'Z'); when get_commands => -- Get commands and operating mode from the processor. if (DATABUS(1 downto 0) = "01") then int_type <= "01"; next_s <= jump_int_method; elsif (DATABUS(1 downto 0) = "10" and count_cmd = 0) then pt(0) <= DATABUS(7 downto 5); pt(1) <= DATABUS(4 downto 2); count_cmd <= count_cmd + 1; next_s <= get_commands; elsif (DATABUS(1 downto 0) = "10" and count_cmd = 1) then pt(2) <= DATABUS(7 downto 5); pt(3) <= DATABUS(4 downto 2); count_cmd <= count_cmd + 1; next_s <= get_commands; elsif (DATABUS(1 downto 0) = "10" and count_cmd = 2) then pt(4) <= DATABUS(7 downto 5); pt(5) <= DATABUS(4 downto 2); count_cmd <= count_cmd + 1; next_s <= get_commands; elsif (DATABUS(1 downto 0) = "10" and count_cmd = 3) then pt(6) <= DATABUS(7 downto 5); pt(7) <= DATABUS(4 downto 2); count_cmd <= 0; int_type <= "10"; next_s <= jump_int_method; else next_s <= get_commands; end if; when jump_int_method => -- Check which method is used to determine the interrupts. flag <= '0'; flag1 <= '0'; int_index <= 0; count_cmd <= 0; int_pt <= "000"; if (int_type = "01") then next_s <= start_polling; -- Polling method for checking the interrupts. elsif (int_type = "10") then next_s <= start_priority_check; -- Fixed priority scheme. else next_s <= reset_s; -- Error if no method is specified. end if; DATABUS <= (others => 'Z'); when start_polling => -- Check for interrupts(one by one) using polling method. if (IR(int_index) = '1') then INTR_O <= '1'; next_s <= tx_int_info_polling; else INTR_O <= '0'; end if; if (int_index = 7) then int_index <= 0; else int_index <= int_index + 1; end if; DATABUS <= (others => 'Z'); when tx_int_info_polling => -- Transmit interrupt information if an interrupt is found. if (INTA_I = '0') then INTR_O <= '0'; end if; if (flag = '0') then DATABUS <= "01011" & to_unsigned((int_index - 1), 3); -- MSB "01011" is for matching purpose. flag1 <= '1'; else flag1 <= '0'; end if; if (flag1 = '1') then next_s <= ack_txinfo_rxd; if (INTA_I = '0') then DATABUS <= (others => 'Z'); end if; end if; when ack_txinfo_rxd => -- ACK send by processor to tell PIC that interrupt info is received correctly. if (INTA_I <= '0') then next_s <= ack_ISR_done; DATABUS <= (others => 'Z'); end if; when ack_ISR_done => -- Wait for the ISR for the particular interrupt to get over. if (INTA_I = '0' and DATABUS(7 downto 3) = "10100" and DATABUS(2 downto 0) = to_unsigned(int_index - 1, 3)) then next_s <= start_polling; else next_s <= ack_ISR_done; end if; when start_priority_check => -- Fixed priority method for interrupt handling. -- Interrupts are checked based on their priority. if (IR(to_integer(pt(0))) = '1') then int_pt <= pt(0); INTR_O <= '1'; next_s <= tx_int_info_priority; elsif (IR(to_integer(pt(1))) = '1') then int_pt <= pt(1); INTR_O <= '1'; next_s <= tx_int_info_priority; elsif (IR(to_integer(pt(2))) = '1') then int_pt <= pt(2); INTR_O <= '1'; next_s <= tx_int_info_priority; elsif (IR(to_integer(pt(3))) = '1') then int_pt <= pt(3); INTR_O <= '1'; next_s <= tx_int_info_priority; elsif (IR(to_integer(pt(4))) = '1') then int_pt <= pt(4); INTR_O <= '1'; next_s <= tx_int_info_priority; elsif (IR(to_integer(pt(5))) = '1') then int_pt <= pt(5); INTR_O <= '1'; next_s <= tx_int_info_priority; elsif (IR(to_integer(pt(6))) = '1') then int_pt <= pt(6); INTR_O <= '1'; next_s <= tx_int_info_priority; elsif (IR(to_integer(pt(7))) = '1') then int_pt <= pt(7); INTR_O <= '1'; next_s <= tx_int_info_priority; else next_s <= start_priority_check; end if; DATABUS <= (others => 'Z'); when tx_int_info_priority => -- Transmit interrupt information if an interrupt is found. if (INTA_I = '0') then INTR_O <= '0'; end if; if (flag = '0') then DATABUS <= "10011" & int_pt; -- MSB "10011" is for matching purpose. flag1 <= '1'; else flag1 <= '0'; end if; if (flag1 = '1') then next_s <= ack_txinfo_rxd_priority; if (INTA_I = '0') then DATABUS <= (others => 'Z'); end if; end if; when ack_txinfo_rxd_priority => -- ACK send by processor to tell PIC that interrupt info is received correctly. if (INTA_I <= '0') then next_s <= ack_ISR_done_pt; DATABUS <= (others => 'Z'); end if; when ack_ISR_done_pt => -- Wait for the ISR for the particular interrupt to get over. if (INTA_I = '0' and DATABUS(7 downto 3) = "01100" and DATABUS(2 downto 0) = int_pt) then next_s <= start_priority_check; elsif (DATABUS(7 downto 3) /= "01100" or DATABUS(2 downto 0) /= int_pt) then next_s <= reset_s; -- Error. else next_s <= ack_ISR_done_pt; end if; when others => DATABUS <= (others => 'Z'); end case; end if; end process; end architecture BEHAVIORAL;
-- -- and_gate_test.vhdl -- library ieee; use ieee.std_logic_1164.all; entity and_gate_test is end entity; architecture sim of and_gate_test is signal a : std_logic := '0'; signal b : std_logic := '0'; signal c : std_logic; begin uut : entity work.and_gate port map ( a => a, b => b, c => c ); test : process begin report "Starting and_gate test"; wait for 1 us; assert c = '0' report "Error, output should be '0'"; a <= '1'; wait for 1 us; assert c = '0' report "Error, output should be '0'"; b <= '1'; wait for 1 us; assert c = '1' report "Error, output should be '1'"; a <= '0'; wait for 1 us; assert c = '0' report "Error, output should be '0'"; report "Completed and_gate test"; wait; end process; end;
/*************************************************************************************************** / / Author: Antonio Pastor González / ¯¯¯¯¯¯ / / Date: / ¯¯¯¯ / / Version: / ¯¯¯¯¯¯¯ / / Notes: / ¯¯¯¯¯ / This design makes use of some features from VHDL-2008, all of which have been implemented in / Vivado by Xilinx / A 3 space tab is used throughout the document / / / Description: / ¯¯¯¯¯¯¯¯¯¯¯ / This package contains functions and utilities that are used in testbenches / **************************************************************************************************/ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; library work; use work.common_pkg.all; use work.fixed_generic_pkg.all; use work.common_data_types_pkg.all; /*================================================================================================*/ /*================================================================================================*/ /*================================================================================================*/ package tb_pkg is function exception_value( arg : positive_exc) return integer; function exception_value( arg : positive_exc) return positive_exc; function exception_value( arg : natural_exc) return integer; function exception_value( arg : natural_exc) return natural_exc; function exception_value( arg : integer_exc) return integer_exc; function exception_value( arg : real_exc) return real_exc; function exception_value( arg : boolean_exc) return boolean_exc; ---------------------------------------------------------------------------------------------------- function value_used( arg : positive_exc_tb) return positive_exc; function value_used( arg : natural_exc_tb) return natural_exc; function value_used( arg : integer_exc_tb) return integer_exc; function value_used( arg : real_exc_tb) return real_exc; function value_used( arg : boolean_exc_tb) return boolean_exc; function value_used( arg : T_speed_tb) return T_speed; ---------------------------------------------------------------------------------------------------- function value_used( arg : boolean_tb; default_value : boolean) return boolean; function value_used( arg : integer_tb; default_value : integer) return integer; function value_used( arg : real_tb; default_value : real) return real; function value_used( arg : T_round_style_tb; default_value : T_round_style) return T_round_style; end package; /*================================================================================================*/ /*================================================================================================*/ /*================================================================================================*/ Package body tb_pkg is function exception_value( arg : positive_exc) return integer is begin return integer(arg'subtype'low); end function; function exception_value( arg : positive_exc) return positive_exc is begin return arg'subtype'low; end function; function exception_value( arg : natural_exc) return integer is begin return integer(arg'subtype'low); end function; function exception_value( arg : natural_exc) return natural_exc is begin return arg'subtype'low; end function; function exception_value( arg : integer_exc) return integer_exc is begin return arg'subtype'low; end function; function exception_value( arg : real_exc) return real_exc is begin return arg'subtype'low; end function; function exception_value( arg : boolean_exc) return boolean_exc is begin return arg'subtype'low; end function; ---------------------------------------------------------------------------------------------------- function value_used( arg : positive_exc_tb) return positive_exc is begin if arg.is_defined then return arg.value; else return exception_value(arg.value); end if; end function; function value_used( arg : natural_exc_tb) return natural_exc is begin if arg.is_defined then return arg.value; else return exception_value(arg.value); end if; end function; function value_used( arg : integer_exc_tb) return integer_exc is begin if arg.is_defined then return arg.value; else return exception_value(arg.value); end if; end function; function value_used( arg : real_exc_tb) return real_exc is begin if arg.is_defined then return arg.value; else return exception_value(arg.value); end if; end function; function value_used( arg : boolean_exc_tb) return boolean_exc is begin if arg.is_defined then return arg.value; else return exception_value(arg.value); end if; end function; function value_used( arg : T_speed_tb) return T_speed is begin if arg.is_defined then return arg.value; else return t_exc; end if; end function; ---------------------------------------------------------------------------------------------------- function value_used( arg : boolean_tb; default_value : boolean) return boolean is begin if arg.is_defined then return arg.value; else return default_value; end if; end function; function value_used( arg : integer_tb; default_value : integer) return integer is begin if arg.is_defined then return arg.value; else return default_value; end if; end function; function value_used( arg : real_tb; default_value : real) return real is begin if arg.is_defined then return arg.value; else return default_value; end if; end function; function value_used( arg : T_round_style_tb; default_value : T_round_style) return T_round_style is begin if arg.is_defined then return arg.value; else return default_value; end if; end function; end package body;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: clkand -- File: clkand.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: Clock gating ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use work.gencomp.all; use work.allclkgen.all; entity clkand is generic( tech : integer := 0; ren : integer range 0 to 1 := 0); -- registered enable port( i : in std_ulogic; en : in std_ulogic; o : out std_ulogic; tsten : in std_ulogic := '0' ); end entity; architecture rtl of clkand is signal eni : std_ulogic; begin re : if ren = 1 generate renproc : process(i) begin if falling_edge(i) then eni <= en; end if; end process; end generate; ce : if ren = 0 generate eni <= en; end generate; struct : if has_clkand(tech) = 1 generate xil : if is_unisim(tech) = 1 generate clkgate : clkand_unisim port map(I => i, en => eni, O => o); end generate; ut : if (tech = ut25) generate clkgate : clkand_ut025crh port map(I => i, en => eni, O => o); end generate; rhl : if (tech = rhlib18t) generate clkgate : clkand_rh_lib18t port map(I => i, en => eni, O => o, tsten => tsten); end generate; ut13 : if (tech = ut130) generate clkgate : clkand_ut130hbd port map(I => i, en => eni, O => o, tsten => tsten); end generate; ut09 : if (tech = ut90) generate clkgate : clkand_ut90nhbd port map(I => i, en => eni, O => o, tsten => tsten); end generate; n2x : if (tech = easic45) generate clkgate : clkand_n2x port map(i => i, en => eni, o => o, tsten => tsten); end generate; saed : if (tech = saed32) generate clkgate : clkand_saed32 port map(i => i, en => eni, o => o, tsten => tsten); end generate; dar : if (tech = dare) generate clkgate : clkand_dare port map(i => i, en => eni, o => o, tsten => tsten); end generate; end generate; gen : if has_clkand(tech) = 0 generate o <= i and (eni or tsten); end generate; end architecture; library ieee; use ieee.std_logic_1164.all; use work.gencomp.all; use work.allclkgen.all; entity clkrand is generic( tech : integer := 0); port( i : in std_ulogic; en : in std_ulogic; o : out std_ulogic; tsten : in std_ulogic := '0' ); end entity; architecture rtl of clkrand is signal eni : std_ulogic; begin ut13 : if (tech = ut130) generate eni <= en or tsten; clkgate : clkrand_ut130hbd port map(I => i, en => en, O => o); end generate; nonut13 : if (tech /= ut130) generate clkgate : clkand generic map (tech, 1) port map (i, en, o, tsten); end generate; end;
------------------------------------------------------------------------------ -- LEON3 Demonstration design test bench -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library gaisler; use gaisler.libdcom.all; use gaisler.sim.all; use work.debug.all; library techmap; use techmap.gencomp.all; library micron; use micron.components.all; library grlib; use grlib.stdlib.all; use work.config.all; -- configuration entity testbench is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; clkperiod : integer := 20; -- system clock period romdepth : integer := 20; -- rom address depth sramwidth : integer := 32; -- ram data width (8/16/32) sramdepth : integer := 20; -- ram address depth srambanks : integer := 2 -- number of ram banks ); end; architecture behav of testbench is constant promfile : string := "prom.srec"; -- rom contents constant sramfile : string := "ram.srec"; -- ram contents constant sdramfile : string := "ram.srec"; -- sdram contents signal clk : std_logic := '0'; signal Rst : std_logic := '0'; -- Reset constant ct : integer := clkperiod/2; signal sma_clkout : std_ulogic; signal address : std_logic_vector(22 downto 0); signal data : std_logic_vector(31 downto 24); signal ramsn : std_logic_vector(4 downto 0); signal ramoen : std_logic_vector(4 downto 0); signal rwen : std_logic_vector(3 downto 0); signal rwenx : std_logic_vector(3 downto 0); signal romsn : std_logic; signal iosn : std_logic; signal oen : std_logic; signal read : std_logic; signal writen : std_logic; signal brdyn : std_logic; signal bexcn : std_logic; signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic; signal dsurst : std_logic; signal test : std_logic; signal error : std_logic; signal gpio : std_logic_vector(35 downto 0); signal GND : std_logic := '0'; signal VCC : std_logic := '1'; signal NC : std_logic := 'Z'; signal clk2 : std_logic := '1'; signal sdcke : std_logic; signal sdcsn : std_logic; signal sdwen : std_logic; -- write en signal sdrasn : std_logic; -- row addr stb signal sdcasn : std_logic; -- col addr stb signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask signal sdclk : std_logic; signal plllock : std_logic; signal txd1, rxd1 : std_logic; signal etx_clk, erx_clk, erx_dv, erx_er, erx_col : std_logic := '0'; signal eth_gtxclk, erx_crs, etx_en, etx_er : std_logic :='0'; signal eth_macclk : std_logic := '0'; signal erxd, etxd : std_logic_vector(7 downto 0) := (others => '0'); signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used signal emdintn : std_logic := '1'; signal emddis : std_logic; signal epwrdwn : std_logic; signal ereset : std_logic; signal esleep : std_logic; signal epause : std_logic; constant lresp : boolean := false; signal sa : std_logic_vector(14 downto 0); signal sd : std_logic_vector(31 downto 0); signal can_txd : std_logic_vector(0 to CFG_CAN_NUM-1); signal can_rxd : std_logic_vector(0 to CFG_CAN_NUM-1); signal can_stb : std_logic_vector(0 to CFG_CAN_NUM-1); begin -- clock and reset clk <= not clk after ct * 1 ns; rst <= dsurst; dsuen <= '1'; dsubre <= '1'; -- inverted on the board rxd1 <= '1'; can_rxd <= (others => 'H'); bexcn <= '1'; gpio(2 downto 0) <= "LHL"; gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H'); eth_macclk <= not eth_macclk after 4 ns; ereset <= 'H'; d3 : entity work.leon3mp generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow ) port map (rst, clk, sma_clkout, error, address(22 downto 0), data, sa(12 downto 0), sa(14 downto 13), sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm, dsutx, dsurx, dsubre, dsuact, oen, writen, open, open, romsn, gpio, emdio, eth_macclk, etx_clk, erx_clk, erxd(3 downto 0), erx_dv, erx_er, erx_col, erx_crs, emdintn, ereset, etxd(3 downto 0), etx_en, etx_er, emdc, can_txd, can_rxd, can_stb ); sd1 : if ((CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1)) generate u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile) PORT MAP( Dq => sd(31 downto 16), Addr => sa(12 downto 0), Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke, Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(3 downto 2)); u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile) PORT MAP( Dq => sd(15 downto 0), Addr => sa(12 downto 0), Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke, Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(1 downto 0)); end generate; prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile) port map (address(romdepth-1 downto 0), data(31 downto 24), romsn, writen, oen); -- sram0 : for i in 0 to (sramwidth/8)-1 generate -- sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile) -- port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0), -- rwen(0), ramoen(0)); -- end generate; phy0 : if (CFG_GRETH = 1) generate emdio <= 'H'; p0: phy generic map(address => 16) port map(ereset, emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, eth_macclk); end generate; error <= 'H'; -- ERROR pull-up iuerr : process begin wait for 2500 ns; if to_x01(error) = '1' then wait on error; end if; assert (to_x01(error) = '1') report "*** IU in error mode, simulation halted ***" severity failure ; end process; -- test0 : grtestmod -- port map ( rst, clk, error, address(21 downto 2), data, -- iosn, oen, writen, brdyn); -- data <= buskeep(data), (others => 'H') after 250 ns; data <= buskeep(data) after 5 ns; -- sd <= buskeep(sd), (others => 'H') after 250 ns; sd <= buskeep(sd) after 5 ns; dsucom : process procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is variable w32 : std_logic_vector(31 downto 0); variable c8 : std_logic_vector(7 downto 0); constant txp : time := 160 * 1 ns; begin dsutx <= '1'; dsurst <= '0'; wait for 500 ns; dsurst <= '1'; wait; wait for 5000 ns; txc(dsutx, 16#55#, txp); -- sync uart -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp); -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp); -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp); -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp); txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp); txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp); txc(dsutx, 16#80#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); rxi(dsurx, w32, txp, lresp); txc(dsutx, 16#a0#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp); rxi(dsurx, w32, txp, lresp); end; begin dsucfg(dsutx, dsurx); wait; end process; end ;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 3.92 -- \ \ Application : MIG -- / / Filename : example_top.vhd -- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $ -- \ \ / \ Date Created : Jul 03 2009 -- \___\/\___\ -- --Device : Spartan-6 --Design Name : DDR/DDR2/DDR3/LPDDR --Purpose : This is the design top level. which instantiates top wrapper, -- test bench top and infrastructure modules. --Reference : --Revision History : --***************************************************************************** library ieee; use ieee.std_logic_1164.all; entity example_top is generic ( C3_P0_MASK_SIZE : integer := 4; C3_P0_DATA_PORT_SIZE : integer := 32; C3_P1_MASK_SIZE : integer := 4; C3_P1_DATA_PORT_SIZE : integer := 32; C3_MEMCLK_PERIOD : integer := 3200; -- Memory data transfer clock period. C3_RST_ACT_LOW : integer := 0; -- # = 1 for active low reset, -- # = 0 for active high reset. C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED"; -- input clock type DIFFERENTIAL or SINGLE_ENDED. C3_CALIB_SOFT_IP : string := "TRUE"; -- # = TRUE, Enables the soft calibration logic, -- # = FALSE, Disables the soft calibration logic. C3_SIMULATION : string := "FALSE"; -- # = TRUE, Simulating the design. Useful to reduce the simulation time, -- # = FALSE, Implementing the design. C3_HW_TESTING : string := "FALSE"; -- Determines the address space accessed by the traffic generator, -- # = FALSE, Smaller address space, -- # = TRUE, Large address space. DEBUG_EN : integer := 0; -- # = 1, Enable debug signals/controls, -- = 0, Disable debug signals/controls. C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- The order in which user address is provided to the memory controller, -- ROW_BANK_COLUMN or BANK_ROW_COLUMN. C3_NUM_DQ_PINS : integer := 16; -- External memory data width. C3_MEM_ADDR_WIDTH : integer := 13; -- External memory address width. C3_MEM_BANKADDR_WIDTH : integer := 3 -- External memory bank address width. ); port ( calib_done : out std_logic; error : out std_logic; mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0); mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0); mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_rzq : inout std_logic; mcb3_zio : inout std_logic; mcb3_dram_udm : out std_logic; c3_sys_clk : in std_logic; c3_sys_rst_i : in std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic ); end example_top; architecture arc of example_top is component memc3_infrastructure is generic ( C_RST_ACT_LOW : integer; C_INPUT_CLK_TYPE : string; C_CLKOUT0_DIVIDE : integer; C_CLKOUT1_DIVIDE : integer; C_CLKOUT2_DIVIDE : integer; C_CLKOUT3_DIVIDE : integer; C_CLKFBOUT_MULT : integer; C_DIVCLK_DIVIDE : integer; C_INCLK_PERIOD : integer ); port ( sys_clk_p : in std_logic; sys_clk_n : in std_logic; sys_clk : in std_logic; sys_rst_i : in std_logic; clk0 : out std_logic; rst0 : out std_logic; async_rst : out std_logic; sysclk_2x : out std_logic; sysclk_2x_180 : out std_logic; pll_ce_0 : out std_logic; pll_ce_90 : out std_logic; pll_lock : out std_logic; mcb_drp_clk : out std_logic ); end component; component memc3_wrapper is generic ( C_MEMCLK_PERIOD : integer; C_CALIB_SOFT_IP : string; C_SIMULATION : string; C_P0_MASK_SIZE : integer; C_P0_DATA_PORT_SIZE : integer; C_P1_MASK_SIZE : integer; C_P1_DATA_PORT_SIZE : integer; C_ARB_NUM_TIME_SLOTS : integer; C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0); C_MEM_TRAS : integer; C_MEM_TRCD : integer; C_MEM_TREFI : integer; C_MEM_TRFC : integer; C_MEM_TRP : integer; C_MEM_TWR : integer; C_MEM_TRTP : integer; C_MEM_TWTR : integer; C_MEM_ADDR_ORDER : string; C_NUM_DQ_PINS : integer; C_MEM_TYPE : string; C_MEM_DENSITY : string; C_MEM_BURST_LEN : integer; C_MEM_CAS_LATENCY : integer; C_MEM_ADDR_WIDTH : integer; C_MEM_BANKADDR_WIDTH : integer; C_MEM_NUM_COL_BITS : integer; C_MEM_DDR1_2_ODS : string; C_MEM_DDR2_RTT : string; C_MEM_DDR2_DIFF_DQS_EN : string; C_MEM_DDR2_3_PA_SR : string; C_MEM_DDR2_3_HIGH_TEMP_SR : string; C_MEM_DDR3_CAS_LATENCY : integer; C_MEM_DDR3_ODS : string; C_MEM_DDR3_RTT : string; C_MEM_DDR3_CAS_WR_LATENCY : integer; C_MEM_DDR3_AUTO_SR : string; C_MEM_DDR3_DYN_WRT_ODT : string; C_MEM_MOBILE_PA_SR : string; C_MEM_MDDR_ODS : string; C_MC_CALIB_BYPASS : string; C_MC_CALIBRATION_MODE : string; C_MC_CALIBRATION_DELAY : string; C_SKIP_IN_TERM_CAL : integer; C_SKIP_DYNAMIC_CAL : integer; C_LDQSP_TAP_DELAY_VAL : integer; C_LDQSN_TAP_DELAY_VAL : integer; C_UDQSP_TAP_DELAY_VAL : integer; C_UDQSN_TAP_DELAY_VAL : integer; C_DQ0_TAP_DELAY_VAL : integer; C_DQ1_TAP_DELAY_VAL : integer; C_DQ2_TAP_DELAY_VAL : integer; C_DQ3_TAP_DELAY_VAL : integer; C_DQ4_TAP_DELAY_VAL : integer; C_DQ5_TAP_DELAY_VAL : integer; C_DQ6_TAP_DELAY_VAL : integer; C_DQ7_TAP_DELAY_VAL : integer; C_DQ8_TAP_DELAY_VAL : integer; C_DQ9_TAP_DELAY_VAL : integer; C_DQ10_TAP_DELAY_VAL : integer; C_DQ11_TAP_DELAY_VAL : integer; C_DQ12_TAP_DELAY_VAL : integer; C_DQ13_TAP_DELAY_VAL : integer; C_DQ14_TAP_DELAY_VAL : integer; C_DQ15_TAP_DELAY_VAL : integer ); port ( mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0); mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0); mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_rzq : inout std_logic; mcb3_zio : inout std_logic; mcb3_dram_udm : out std_logic; calib_done : out std_logic; async_rst : in std_logic; sysclk_2x : in std_logic; sysclk_2x_180 : in std_logic; pll_ce_0 : in std_logic; pll_ce_90 : in std_logic; pll_lock : in std_logic; mcb_drp_clk : in std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic; p2_cmd_clk : in std_logic; p2_cmd_en : in std_logic; p2_cmd_instr : in std_logic_vector(2 downto 0); p2_cmd_bl : in std_logic_vector(5 downto 0); p2_cmd_byte_addr : in std_logic_vector(29 downto 0); p2_cmd_empty : out std_logic; p2_cmd_full : out std_logic; p2_rd_clk : in std_logic; p2_rd_en : in std_logic; p2_rd_data : out std_logic_vector(31 downto 0); p2_rd_full : out std_logic; p2_rd_empty : out std_logic; p2_rd_count : out std_logic_vector(6 downto 0); p2_rd_overflow : out std_logic; p2_rd_error : out std_logic; p3_cmd_clk : in std_logic; p3_cmd_en : in std_logic; p3_cmd_instr : in std_logic_vector(2 downto 0); p3_cmd_bl : in std_logic_vector(5 downto 0); p3_cmd_byte_addr : in std_logic_vector(29 downto 0); p3_cmd_empty : out std_logic; p3_cmd_full : out std_logic; p3_wr_clk : in std_logic; p3_wr_en : in std_logic; p3_wr_mask : in std_logic_vector(3 downto 0); p3_wr_data : in std_logic_vector(31 downto 0); p3_wr_full : out std_logic; p3_wr_empty : out std_logic; p3_wr_count : out std_logic_vector(6 downto 0); p3_wr_underrun : out std_logic; p3_wr_error : out std_logic; selfrefresh_enter : in std_logic; selfrefresh_mode : out std_logic ); end component; component memc3_tb_top is generic ( C_SIMULATION : string; C_P0_MASK_SIZE : integer; C_P0_DATA_PORT_SIZE : integer; C_P1_MASK_SIZE : integer; C_P1_DATA_PORT_SIZE : integer; C_NUM_DQ_PINS : integer; C_MEM_BURST_LEN : integer; C_MEM_NUM_COL_BITS : integer; C_SMALL_DEVICE : string; C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0); C_p2_DATA_MODE : std_logic_vector(3 downto 0); C_p2_END_ADDRESS : std_logic_vector(31 downto 0); C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0); C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0); C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0); C_p3_DATA_MODE : std_logic_vector(3 downto 0); C_p3_END_ADDRESS : std_logic_vector(31 downto 0); C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0); C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) ); port ( error : out std_logic; calib_done : in std_logic; clk0 : in std_logic; rst0 : in std_logic; cmp_error : out std_logic; cmp_data_valid : out std_logic; vio_modify_enable : in std_logic; error_status : out std_logic_vector(127 downto 0); vio_data_mode_value : in std_logic_vector(2 downto 0); vio_addr_mode_value : in std_logic_vector(2 downto 0); cmp_data : out std_logic_vector(31 downto 0); p2_mcb_cmd_en_o : out std_logic; p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0); p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0); p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0); p2_mcb_cmd_full_i : in std_logic; p2_mcb_rd_en_o : out std_logic; p2_mcb_rd_data_i : in std_logic_vector(31 downto 0); p2_mcb_rd_empty_i : in std_logic; p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0); p3_mcb_cmd_en_o : out std_logic; p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0); p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0); p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0); p3_mcb_cmd_full_i : in std_logic; p3_mcb_wr_en_o : out std_logic; p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0); p3_mcb_wr_data_o : out std_logic_vector(31 downto 0); p3_mcb_wr_full_i : in std_logic; p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0) ); end component; function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is begin if (C3_HW_TESTING = "FALSE") then return val1; else return val2; end if; end function; constant C3_CLKOUT0_DIVIDE : integer := 1; constant C3_CLKOUT1_DIVIDE : integer := 1; constant C3_CLKOUT2_DIVIDE : integer := 16; constant C3_CLKOUT3_DIVIDE : integer := 8; constant C3_CLKFBOUT_MULT : integer := 2; constant C3_DIVCLK_DIVIDE : integer := 1; constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2)); constant C3_ARB_NUM_TIME_SLOTS : integer := 12; constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"32"; constant C3_MEM_TRAS : integer := 42500; constant C3_MEM_TRCD : integer := 12500; constant C3_MEM_TREFI : integer := 7800000; constant C3_MEM_TRFC : integer := 127500; constant C3_MEM_TRP : integer := 12500; constant C3_MEM_TWR : integer := 15000; constant C3_MEM_TRTP : integer := 7500; constant C3_MEM_TWTR : integer := 7500; constant C3_MEM_TYPE : string := "DDR2"; constant C3_MEM_DENSITY : string := "1Gb"; constant C3_MEM_BURST_LEN : integer := 4; constant C3_MEM_CAS_LATENCY : integer := 5; constant C3_MEM_NUM_COL_BITS : integer := 10; constant C3_MEM_DDR1_2_ODS : string := "FULL"; constant C3_MEM_DDR2_RTT : string := "50OHMS"; constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES"; constant C3_MEM_DDR2_3_PA_SR : string := "FULL"; constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL"; constant C3_MEM_DDR3_CAS_LATENCY : integer := 6; constant C3_MEM_DDR3_ODS : string := "DIV6"; constant C3_MEM_DDR3_RTT : string := "DIV2"; constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5; constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED"; constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF"; constant C3_MEM_MOBILE_PA_SR : string := "FULL"; constant C3_MEM_MDDR_ODS : string := "FULL"; constant C3_MC_CALIB_BYPASS : string := "NO"; constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION"; constant C3_MC_CALIBRATION_DELAY : string := "HALF"; constant C3_SKIP_IN_TERM_CAL : integer := 0; constant C3_SKIP_DYNAMIC_CAL : integer := 0; constant C3_LDQSP_TAP_DELAY_VAL : integer := 0; constant C3_LDQSN_TAP_DELAY_VAL : integer := 0; constant C3_UDQSP_TAP_DELAY_VAL : integer := 0; constant C3_UDQSN_TAP_DELAY_VAL : integer := 0; constant C3_DQ0_TAP_DELAY_VAL : integer := 0; constant C3_DQ1_TAP_DELAY_VAL : integer := 0; constant C3_DQ2_TAP_DELAY_VAL : integer := 0; constant C3_DQ3_TAP_DELAY_VAL : integer := 0; constant C3_DQ4_TAP_DELAY_VAL : integer := 0; constant C3_DQ5_TAP_DELAY_VAL : integer := 0; constant C3_DQ6_TAP_DELAY_VAL : integer := 0; constant C3_DQ7_TAP_DELAY_VAL : integer := 0; constant C3_DQ8_TAP_DELAY_VAL : integer := 0; constant C3_DQ9_TAP_DELAY_VAL : integer := 0; constant C3_DQ10_TAP_DELAY_VAL : integer := 0; constant C3_DQ11_TAP_DELAY_VAL : integer := 0; constant C3_DQ12_TAP_DELAY_VAL : integer := 0; constant C3_DQ13_TAP_DELAY_VAL : integer := 0; constant C3_DQ14_TAP_DELAY_VAL : integer := 0; constant C3_DQ15_TAP_DELAY_VAL : integer := 0; constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device -- as most of them cannot fit the complete example design when the -- Chip scope modules are enabled constant C3_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000"); constant C3_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010"; constant C3_p2_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff"); constant C3_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000"); constant C3_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000"); constant C3_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000"); constant C3_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010"; constant C3_p3_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000006ff", x"06ffffff"); constant C3_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"f8000000"); constant C3_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000"); signal c3_sys_clk_p : std_logic; signal c3_sys_clk_n : std_logic; signal c3_error : std_logic; signal c3_calib_done : std_logic; signal c3_clk0 : std_logic; signal c3_rst0 : std_logic; signal c3_async_rst : std_logic; signal c3_sysclk_2x : std_logic; signal c3_sysclk_2x_180 : std_logic; signal c3_pll_ce_0 : std_logic; signal c3_pll_ce_90 : std_logic; signal c3_pll_lock : std_logic; signal c3_mcb_drp_clk : std_logic; signal c3_cmp_error : std_logic; signal c3_cmp_data_valid : std_logic; signal c3_vio_modify_enable : std_logic; signal c3_error_status : std_logic_vector(127 downto 0); signal c3_vio_data_mode_value : std_logic_vector(2 downto 0); signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0); signal c3_cmp_data : std_logic_vector(31 downto 0); signal c3_p2_cmd_en : std_logic; signal c3_p2_cmd_instr : std_logic_vector(2 downto 0); signal c3_p2_cmd_bl : std_logic_vector(5 downto 0); signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0); signal c3_p2_cmd_empty : std_logic; signal c3_p2_cmd_full : std_logic; signal c3_p2_rd_en : std_logic; signal c3_p2_rd_data : std_logic_vector(31 downto 0); signal c3_p2_rd_full : std_logic; signal c3_p2_rd_empty : std_logic; signal c3_p2_rd_count : std_logic_vector(6 downto 0); signal c3_p2_rd_overflow : std_logic; signal c3_p2_rd_error : std_logic; signal c3_p3_cmd_en : std_logic; signal c3_p3_cmd_instr : std_logic_vector(2 downto 0); signal c3_p3_cmd_bl : std_logic_vector(5 downto 0); signal c3_p3_cmd_byte_addr : std_logic_vector(29 downto 0); signal c3_p3_cmd_empty : std_logic; signal c3_p3_cmd_full : std_logic; signal c3_p3_wr_en : std_logic; signal c3_p3_wr_mask : std_logic_vector(3 downto 0); signal c3_p3_wr_data : std_logic_vector(31 downto 0); signal c3_p3_wr_full : std_logic; signal c3_p3_wr_empty : std_logic; signal c3_p3_wr_count : std_logic_vector(6 downto 0); signal c3_p3_wr_underrun : std_logic; signal c3_p3_wr_error : std_logic; signal c3_selfrefresh_enter : std_logic; signal c3_selfrefresh_mode : std_logic; begin error <= c3_error; calib_done <= c3_calib_done; c3_sys_clk_p <= '0'; c3_sys_clk_n <= '0'; c3_selfrefresh_enter <= '0'; memc3_infrastructure_inst : memc3_infrastructure generic map ( C_RST_ACT_LOW => C3_RST_ACT_LOW, C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE, C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE, C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE, C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE, C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE, C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT, C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE, C_INCLK_PERIOD => C3_INCLK_PERIOD ) port map ( sys_clk_p => c3_sys_clk_p, sys_clk_n => c3_sys_clk_n, sys_clk => c3_sys_clk, sys_rst_i => c3_sys_rst_i, clk0 => c3_clk0, rst0 => c3_rst0, async_rst => c3_async_rst, sysclk_2x => c3_sysclk_2x, sysclk_2x_180 => c3_sysclk_2x_180, pll_ce_0 => c3_pll_ce_0, pll_ce_90 => c3_pll_ce_90, pll_lock => c3_pll_lock, mcb_drp_clk => c3_mcb_drp_clk ); -- wrapper instantiation memc3_wrapper_inst : memc3_wrapper generic map ( C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD, C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP, C_SIMULATION => C3_SIMULATION, C_P0_MASK_SIZE => C3_P0_MASK_SIZE, C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE, C_P1_MASK_SIZE => C3_P1_MASK_SIZE, C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE, C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS, C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0, C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1, C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2, C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3, C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4, C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5, C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6, C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7, C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8, C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9, C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10, C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11, C_MEM_TRAS => C3_MEM_TRAS, C_MEM_TRCD => C3_MEM_TRCD, C_MEM_TREFI => C3_MEM_TREFI, C_MEM_TRFC => C3_MEM_TRFC, C_MEM_TRP => C3_MEM_TRP, C_MEM_TWR => C3_MEM_TWR, C_MEM_TRTP => C3_MEM_TRTP, C_MEM_TWTR => C3_MEM_TWTR, C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER, C_NUM_DQ_PINS => C3_NUM_DQ_PINS, C_MEM_TYPE => C3_MEM_TYPE, C_MEM_DENSITY => C3_MEM_DENSITY, C_MEM_BURST_LEN => C3_MEM_BURST_LEN, C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY, C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH, C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH, C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS, C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS, C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT, C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN, C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR, C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR, C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY, C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS, C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT, C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY, C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR, C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT, C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR, C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS, C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS, C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE, C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY, C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL, C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL, C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL, C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL, C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL, C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL, C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL, C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL, C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL, C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL, C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL, C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL, C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL, C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL, C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL, C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL, C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL, C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL, C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL, C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL, C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL, C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL ) port map ( mcb3_dram_dq => mcb3_dram_dq, mcb3_dram_a => mcb3_dram_a, mcb3_dram_ba => mcb3_dram_ba, mcb3_dram_ras_n => mcb3_dram_ras_n, mcb3_dram_cas_n => mcb3_dram_cas_n, mcb3_dram_we_n => mcb3_dram_we_n, mcb3_dram_odt => mcb3_dram_odt, mcb3_dram_cke => mcb3_dram_cke, mcb3_dram_dm => mcb3_dram_dm, mcb3_dram_udqs => mcb3_dram_udqs, mcb3_dram_udqs_n => mcb3_dram_udqs_n, mcb3_rzq => mcb3_rzq, mcb3_zio => mcb3_zio, mcb3_dram_udm => mcb3_dram_udm, calib_done => c3_calib_done, async_rst => c3_async_rst, sysclk_2x => c3_sysclk_2x, sysclk_2x_180 => c3_sysclk_2x_180, pll_ce_0 => c3_pll_ce_0, pll_ce_90 => c3_pll_ce_90, pll_lock => c3_pll_lock, mcb_drp_clk => c3_mcb_drp_clk, mcb3_dram_dqs => mcb3_dram_dqs, mcb3_dram_dqs_n => mcb3_dram_dqs_n, mcb3_dram_ck => mcb3_dram_ck, mcb3_dram_ck_n => mcb3_dram_ck_n, p2_cmd_clk => c3_clk0, p2_cmd_en => c3_p2_cmd_en, p2_cmd_instr => c3_p2_cmd_instr, p2_cmd_bl => c3_p2_cmd_bl, p2_cmd_byte_addr => c3_p2_cmd_byte_addr, p2_cmd_empty => c3_p2_cmd_empty, p2_cmd_full => c3_p2_cmd_full, p2_rd_clk => c3_clk0, p2_rd_en => c3_p2_rd_en, p2_rd_data => c3_p2_rd_data, p2_rd_full => c3_p2_rd_full, p2_rd_empty => c3_p2_rd_empty, p2_rd_count => c3_p2_rd_count, p2_rd_overflow => c3_p2_rd_overflow, p2_rd_error => c3_p2_rd_error, p3_cmd_clk => c3_clk0, p3_cmd_en => c3_p3_cmd_en, p3_cmd_instr => c3_p3_cmd_instr, p3_cmd_bl => c3_p3_cmd_bl, p3_cmd_byte_addr => c3_p3_cmd_byte_addr, p3_cmd_empty => c3_p3_cmd_empty, p3_cmd_full => c3_p3_cmd_full, p3_wr_clk => c3_clk0, p3_wr_en => c3_p3_wr_en, p3_wr_mask => c3_p3_wr_mask, p3_wr_data => c3_p3_wr_data, p3_wr_full => c3_p3_wr_full, p3_wr_empty => c3_p3_wr_empty, p3_wr_count => c3_p3_wr_count, p3_wr_underrun => c3_p3_wr_underrun, p3_wr_error => c3_p3_wr_error, selfrefresh_enter => c3_selfrefresh_enter, selfrefresh_mode => c3_selfrefresh_mode ); memc3_tb_top_inst : memc3_tb_top generic map ( C_SIMULATION => C3_SIMULATION, C_P0_MASK_SIZE => C3_P0_MASK_SIZE, C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE, C_P1_MASK_SIZE => C3_P1_MASK_SIZE, C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE, C_NUM_DQ_PINS => C3_NUM_DQ_PINS, C_MEM_BURST_LEN => C3_MEM_BURST_LEN, C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS, C_SMALL_DEVICE => C3_SMALL_DEVICE, C_p2_BEGIN_ADDRESS => C3_p2_BEGIN_ADDRESS, C_p2_DATA_MODE => C3_p2_DATA_MODE, C_p2_END_ADDRESS => C3_p2_END_ADDRESS, C_p2_PRBS_EADDR_MASK_POS => C3_p2_PRBS_EADDR_MASK_POS, C_p2_PRBS_SADDR_MASK_POS => C3_p2_PRBS_SADDR_MASK_POS, C_p3_BEGIN_ADDRESS => C3_p3_BEGIN_ADDRESS, C_p3_DATA_MODE => C3_p3_DATA_MODE, C_p3_END_ADDRESS => C3_p3_END_ADDRESS, C_p3_PRBS_EADDR_MASK_POS => C3_p3_PRBS_EADDR_MASK_POS, C_p3_PRBS_SADDR_MASK_POS => C3_p3_PRBS_SADDR_MASK_POS ) port map ( error => c3_error, calib_done => c3_calib_done, clk0 => c3_clk0, rst0 => c3_rst0, cmp_error => c3_cmp_error, cmp_data_valid => c3_cmp_data_valid, vio_modify_enable => c3_vio_modify_enable, error_status => c3_error_status, vio_data_mode_value => c3_vio_data_mode_value, vio_addr_mode_value => c3_vio_addr_mode_value, cmp_data => c3_cmp_data, p2_mcb_cmd_en_o => c3_p2_cmd_en, p2_mcb_cmd_instr_o => c3_p2_cmd_instr, p2_mcb_cmd_bl_o => c3_p2_cmd_bl, p2_mcb_cmd_addr_o => c3_p2_cmd_byte_addr, p2_mcb_cmd_full_i => c3_p2_cmd_full, p2_mcb_rd_en_o => c3_p2_rd_en, p2_mcb_rd_data_i => c3_p2_rd_data, p2_mcb_rd_empty_i => c3_p2_rd_empty, p2_mcb_rd_fifo_counts => c3_p2_rd_count, p3_mcb_cmd_en_o => c3_p3_cmd_en, p3_mcb_cmd_instr_o => c3_p3_cmd_instr, p3_mcb_cmd_bl_o => c3_p3_cmd_bl, p3_mcb_cmd_addr_o => c3_p3_cmd_byte_addr, p3_mcb_cmd_full_i => c3_p3_cmd_full, p3_mcb_wr_en_o => c3_p3_wr_en, p3_mcb_wr_mask_o => c3_p3_wr_mask, p3_mcb_wr_data_o => c3_p3_wr_data, p3_mcb_wr_full_i => c3_p3_wr_full, p3_mcb_wr_fifo_counts => c3_p3_wr_count ); end arc;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 3.92 -- \ \ Application : MIG -- / / Filename : example_top.vhd -- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $ -- \ \ / \ Date Created : Jul 03 2009 -- \___\/\___\ -- --Device : Spartan-6 --Design Name : DDR/DDR2/DDR3/LPDDR --Purpose : This is the design top level. which instantiates top wrapper, -- test bench top and infrastructure modules. --Reference : --Revision History : --***************************************************************************** library ieee; use ieee.std_logic_1164.all; entity example_top is generic ( C3_P0_MASK_SIZE : integer := 4; C3_P0_DATA_PORT_SIZE : integer := 32; C3_P1_MASK_SIZE : integer := 4; C3_P1_DATA_PORT_SIZE : integer := 32; C3_MEMCLK_PERIOD : integer := 3200; -- Memory data transfer clock period. C3_RST_ACT_LOW : integer := 0; -- # = 1 for active low reset, -- # = 0 for active high reset. C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED"; -- input clock type DIFFERENTIAL or SINGLE_ENDED. C3_CALIB_SOFT_IP : string := "TRUE"; -- # = TRUE, Enables the soft calibration logic, -- # = FALSE, Disables the soft calibration logic. C3_SIMULATION : string := "FALSE"; -- # = TRUE, Simulating the design. Useful to reduce the simulation time, -- # = FALSE, Implementing the design. C3_HW_TESTING : string := "FALSE"; -- Determines the address space accessed by the traffic generator, -- # = FALSE, Smaller address space, -- # = TRUE, Large address space. DEBUG_EN : integer := 0; -- # = 1, Enable debug signals/controls, -- = 0, Disable debug signals/controls. C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- The order in which user address is provided to the memory controller, -- ROW_BANK_COLUMN or BANK_ROW_COLUMN. C3_NUM_DQ_PINS : integer := 16; -- External memory data width. C3_MEM_ADDR_WIDTH : integer := 13; -- External memory address width. C3_MEM_BANKADDR_WIDTH : integer := 3 -- External memory bank address width. ); port ( calib_done : out std_logic; error : out std_logic; mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0); mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0); mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_rzq : inout std_logic; mcb3_zio : inout std_logic; mcb3_dram_udm : out std_logic; c3_sys_clk : in std_logic; c3_sys_rst_i : in std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic ); end example_top; architecture arc of example_top is component memc3_infrastructure is generic ( C_RST_ACT_LOW : integer; C_INPUT_CLK_TYPE : string; C_CLKOUT0_DIVIDE : integer; C_CLKOUT1_DIVIDE : integer; C_CLKOUT2_DIVIDE : integer; C_CLKOUT3_DIVIDE : integer; C_CLKFBOUT_MULT : integer; C_DIVCLK_DIVIDE : integer; C_INCLK_PERIOD : integer ); port ( sys_clk_p : in std_logic; sys_clk_n : in std_logic; sys_clk : in std_logic; sys_rst_i : in std_logic; clk0 : out std_logic; rst0 : out std_logic; async_rst : out std_logic; sysclk_2x : out std_logic; sysclk_2x_180 : out std_logic; pll_ce_0 : out std_logic; pll_ce_90 : out std_logic; pll_lock : out std_logic; mcb_drp_clk : out std_logic ); end component; component memc3_wrapper is generic ( C_MEMCLK_PERIOD : integer; C_CALIB_SOFT_IP : string; C_SIMULATION : string; C_P0_MASK_SIZE : integer; C_P0_DATA_PORT_SIZE : integer; C_P1_MASK_SIZE : integer; C_P1_DATA_PORT_SIZE : integer; C_ARB_NUM_TIME_SLOTS : integer; C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0); C_MEM_TRAS : integer; C_MEM_TRCD : integer; C_MEM_TREFI : integer; C_MEM_TRFC : integer; C_MEM_TRP : integer; C_MEM_TWR : integer; C_MEM_TRTP : integer; C_MEM_TWTR : integer; C_MEM_ADDR_ORDER : string; C_NUM_DQ_PINS : integer; C_MEM_TYPE : string; C_MEM_DENSITY : string; C_MEM_BURST_LEN : integer; C_MEM_CAS_LATENCY : integer; C_MEM_ADDR_WIDTH : integer; C_MEM_BANKADDR_WIDTH : integer; C_MEM_NUM_COL_BITS : integer; C_MEM_DDR1_2_ODS : string; C_MEM_DDR2_RTT : string; C_MEM_DDR2_DIFF_DQS_EN : string; C_MEM_DDR2_3_PA_SR : string; C_MEM_DDR2_3_HIGH_TEMP_SR : string; C_MEM_DDR3_CAS_LATENCY : integer; C_MEM_DDR3_ODS : string; C_MEM_DDR3_RTT : string; C_MEM_DDR3_CAS_WR_LATENCY : integer; C_MEM_DDR3_AUTO_SR : string; C_MEM_DDR3_DYN_WRT_ODT : string; C_MEM_MOBILE_PA_SR : string; C_MEM_MDDR_ODS : string; C_MC_CALIB_BYPASS : string; C_MC_CALIBRATION_MODE : string; C_MC_CALIBRATION_DELAY : string; C_SKIP_IN_TERM_CAL : integer; C_SKIP_DYNAMIC_CAL : integer; C_LDQSP_TAP_DELAY_VAL : integer; C_LDQSN_TAP_DELAY_VAL : integer; C_UDQSP_TAP_DELAY_VAL : integer; C_UDQSN_TAP_DELAY_VAL : integer; C_DQ0_TAP_DELAY_VAL : integer; C_DQ1_TAP_DELAY_VAL : integer; C_DQ2_TAP_DELAY_VAL : integer; C_DQ3_TAP_DELAY_VAL : integer; C_DQ4_TAP_DELAY_VAL : integer; C_DQ5_TAP_DELAY_VAL : integer; C_DQ6_TAP_DELAY_VAL : integer; C_DQ7_TAP_DELAY_VAL : integer; C_DQ8_TAP_DELAY_VAL : integer; C_DQ9_TAP_DELAY_VAL : integer; C_DQ10_TAP_DELAY_VAL : integer; C_DQ11_TAP_DELAY_VAL : integer; C_DQ12_TAP_DELAY_VAL : integer; C_DQ13_TAP_DELAY_VAL : integer; C_DQ14_TAP_DELAY_VAL : integer; C_DQ15_TAP_DELAY_VAL : integer ); port ( mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0); mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0); mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_rzq : inout std_logic; mcb3_zio : inout std_logic; mcb3_dram_udm : out std_logic; calib_done : out std_logic; async_rst : in std_logic; sysclk_2x : in std_logic; sysclk_2x_180 : in std_logic; pll_ce_0 : in std_logic; pll_ce_90 : in std_logic; pll_lock : in std_logic; mcb_drp_clk : in std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic; p2_cmd_clk : in std_logic; p2_cmd_en : in std_logic; p2_cmd_instr : in std_logic_vector(2 downto 0); p2_cmd_bl : in std_logic_vector(5 downto 0); p2_cmd_byte_addr : in std_logic_vector(29 downto 0); p2_cmd_empty : out std_logic; p2_cmd_full : out std_logic; p2_rd_clk : in std_logic; p2_rd_en : in std_logic; p2_rd_data : out std_logic_vector(31 downto 0); p2_rd_full : out std_logic; p2_rd_empty : out std_logic; p2_rd_count : out std_logic_vector(6 downto 0); p2_rd_overflow : out std_logic; p2_rd_error : out std_logic; p3_cmd_clk : in std_logic; p3_cmd_en : in std_logic; p3_cmd_instr : in std_logic_vector(2 downto 0); p3_cmd_bl : in std_logic_vector(5 downto 0); p3_cmd_byte_addr : in std_logic_vector(29 downto 0); p3_cmd_empty : out std_logic; p3_cmd_full : out std_logic; p3_wr_clk : in std_logic; p3_wr_en : in std_logic; p3_wr_mask : in std_logic_vector(3 downto 0); p3_wr_data : in std_logic_vector(31 downto 0); p3_wr_full : out std_logic; p3_wr_empty : out std_logic; p3_wr_count : out std_logic_vector(6 downto 0); p3_wr_underrun : out std_logic; p3_wr_error : out std_logic; selfrefresh_enter : in std_logic; selfrefresh_mode : out std_logic ); end component; component memc3_tb_top is generic ( C_SIMULATION : string; C_P0_MASK_SIZE : integer; C_P0_DATA_PORT_SIZE : integer; C_P1_MASK_SIZE : integer; C_P1_DATA_PORT_SIZE : integer; C_NUM_DQ_PINS : integer; C_MEM_BURST_LEN : integer; C_MEM_NUM_COL_BITS : integer; C_SMALL_DEVICE : string; C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0); C_p2_DATA_MODE : std_logic_vector(3 downto 0); C_p2_END_ADDRESS : std_logic_vector(31 downto 0); C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0); C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0); C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0); C_p3_DATA_MODE : std_logic_vector(3 downto 0); C_p3_END_ADDRESS : std_logic_vector(31 downto 0); C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0); C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) ); port ( error : out std_logic; calib_done : in std_logic; clk0 : in std_logic; rst0 : in std_logic; cmp_error : out std_logic; cmp_data_valid : out std_logic; vio_modify_enable : in std_logic; error_status : out std_logic_vector(127 downto 0); vio_data_mode_value : in std_logic_vector(2 downto 0); vio_addr_mode_value : in std_logic_vector(2 downto 0); cmp_data : out std_logic_vector(31 downto 0); p2_mcb_cmd_en_o : out std_logic; p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0); p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0); p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0); p2_mcb_cmd_full_i : in std_logic; p2_mcb_rd_en_o : out std_logic; p2_mcb_rd_data_i : in std_logic_vector(31 downto 0); p2_mcb_rd_empty_i : in std_logic; p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0); p3_mcb_cmd_en_o : out std_logic; p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0); p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0); p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0); p3_mcb_cmd_full_i : in std_logic; p3_mcb_wr_en_o : out std_logic; p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0); p3_mcb_wr_data_o : out std_logic_vector(31 downto 0); p3_mcb_wr_full_i : in std_logic; p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0) ); end component; function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is begin if (C3_HW_TESTING = "FALSE") then return val1; else return val2; end if; end function; constant C3_CLKOUT0_DIVIDE : integer := 1; constant C3_CLKOUT1_DIVIDE : integer := 1; constant C3_CLKOUT2_DIVIDE : integer := 16; constant C3_CLKOUT3_DIVIDE : integer := 8; constant C3_CLKFBOUT_MULT : integer := 2; constant C3_DIVCLK_DIVIDE : integer := 1; constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2)); constant C3_ARB_NUM_TIME_SLOTS : integer := 12; constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"32"; constant C3_MEM_TRAS : integer := 42500; constant C3_MEM_TRCD : integer := 12500; constant C3_MEM_TREFI : integer := 7800000; constant C3_MEM_TRFC : integer := 127500; constant C3_MEM_TRP : integer := 12500; constant C3_MEM_TWR : integer := 15000; constant C3_MEM_TRTP : integer := 7500; constant C3_MEM_TWTR : integer := 7500; constant C3_MEM_TYPE : string := "DDR2"; constant C3_MEM_DENSITY : string := "1Gb"; constant C3_MEM_BURST_LEN : integer := 4; constant C3_MEM_CAS_LATENCY : integer := 5; constant C3_MEM_NUM_COL_BITS : integer := 10; constant C3_MEM_DDR1_2_ODS : string := "FULL"; constant C3_MEM_DDR2_RTT : string := "50OHMS"; constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES"; constant C3_MEM_DDR2_3_PA_SR : string := "FULL"; constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL"; constant C3_MEM_DDR3_CAS_LATENCY : integer := 6; constant C3_MEM_DDR3_ODS : string := "DIV6"; constant C3_MEM_DDR3_RTT : string := "DIV2"; constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5; constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED"; constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF"; constant C3_MEM_MOBILE_PA_SR : string := "FULL"; constant C3_MEM_MDDR_ODS : string := "FULL"; constant C3_MC_CALIB_BYPASS : string := "NO"; constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION"; constant C3_MC_CALIBRATION_DELAY : string := "HALF"; constant C3_SKIP_IN_TERM_CAL : integer := 0; constant C3_SKIP_DYNAMIC_CAL : integer := 0; constant C3_LDQSP_TAP_DELAY_VAL : integer := 0; constant C3_LDQSN_TAP_DELAY_VAL : integer := 0; constant C3_UDQSP_TAP_DELAY_VAL : integer := 0; constant C3_UDQSN_TAP_DELAY_VAL : integer := 0; constant C3_DQ0_TAP_DELAY_VAL : integer := 0; constant C3_DQ1_TAP_DELAY_VAL : integer := 0; constant C3_DQ2_TAP_DELAY_VAL : integer := 0; constant C3_DQ3_TAP_DELAY_VAL : integer := 0; constant C3_DQ4_TAP_DELAY_VAL : integer := 0; constant C3_DQ5_TAP_DELAY_VAL : integer := 0; constant C3_DQ6_TAP_DELAY_VAL : integer := 0; constant C3_DQ7_TAP_DELAY_VAL : integer := 0; constant C3_DQ8_TAP_DELAY_VAL : integer := 0; constant C3_DQ9_TAP_DELAY_VAL : integer := 0; constant C3_DQ10_TAP_DELAY_VAL : integer := 0; constant C3_DQ11_TAP_DELAY_VAL : integer := 0; constant C3_DQ12_TAP_DELAY_VAL : integer := 0; constant C3_DQ13_TAP_DELAY_VAL : integer := 0; constant C3_DQ14_TAP_DELAY_VAL : integer := 0; constant C3_DQ15_TAP_DELAY_VAL : integer := 0; constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device -- as most of them cannot fit the complete example design when the -- Chip scope modules are enabled constant C3_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000"); constant C3_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010"; constant C3_p2_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff"); constant C3_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000"); constant C3_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000"); constant C3_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000"); constant C3_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010"; constant C3_p3_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000006ff", x"06ffffff"); constant C3_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"f8000000"); constant C3_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000"); signal c3_sys_clk_p : std_logic; signal c3_sys_clk_n : std_logic; signal c3_error : std_logic; signal c3_calib_done : std_logic; signal c3_clk0 : std_logic; signal c3_rst0 : std_logic; signal c3_async_rst : std_logic; signal c3_sysclk_2x : std_logic; signal c3_sysclk_2x_180 : std_logic; signal c3_pll_ce_0 : std_logic; signal c3_pll_ce_90 : std_logic; signal c3_pll_lock : std_logic; signal c3_mcb_drp_clk : std_logic; signal c3_cmp_error : std_logic; signal c3_cmp_data_valid : std_logic; signal c3_vio_modify_enable : std_logic; signal c3_error_status : std_logic_vector(127 downto 0); signal c3_vio_data_mode_value : std_logic_vector(2 downto 0); signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0); signal c3_cmp_data : std_logic_vector(31 downto 0); signal c3_p2_cmd_en : std_logic; signal c3_p2_cmd_instr : std_logic_vector(2 downto 0); signal c3_p2_cmd_bl : std_logic_vector(5 downto 0); signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0); signal c3_p2_cmd_empty : std_logic; signal c3_p2_cmd_full : std_logic; signal c3_p2_rd_en : std_logic; signal c3_p2_rd_data : std_logic_vector(31 downto 0); signal c3_p2_rd_full : std_logic; signal c3_p2_rd_empty : std_logic; signal c3_p2_rd_count : std_logic_vector(6 downto 0); signal c3_p2_rd_overflow : std_logic; signal c3_p2_rd_error : std_logic; signal c3_p3_cmd_en : std_logic; signal c3_p3_cmd_instr : std_logic_vector(2 downto 0); signal c3_p3_cmd_bl : std_logic_vector(5 downto 0); signal c3_p3_cmd_byte_addr : std_logic_vector(29 downto 0); signal c3_p3_cmd_empty : std_logic; signal c3_p3_cmd_full : std_logic; signal c3_p3_wr_en : std_logic; signal c3_p3_wr_mask : std_logic_vector(3 downto 0); signal c3_p3_wr_data : std_logic_vector(31 downto 0); signal c3_p3_wr_full : std_logic; signal c3_p3_wr_empty : std_logic; signal c3_p3_wr_count : std_logic_vector(6 downto 0); signal c3_p3_wr_underrun : std_logic; signal c3_p3_wr_error : std_logic; signal c3_selfrefresh_enter : std_logic; signal c3_selfrefresh_mode : std_logic; begin error <= c3_error; calib_done <= c3_calib_done; c3_sys_clk_p <= '0'; c3_sys_clk_n <= '0'; c3_selfrefresh_enter <= '0'; memc3_infrastructure_inst : memc3_infrastructure generic map ( C_RST_ACT_LOW => C3_RST_ACT_LOW, C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE, C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE, C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE, C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE, C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE, C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT, C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE, C_INCLK_PERIOD => C3_INCLK_PERIOD ) port map ( sys_clk_p => c3_sys_clk_p, sys_clk_n => c3_sys_clk_n, sys_clk => c3_sys_clk, sys_rst_i => c3_sys_rst_i, clk0 => c3_clk0, rst0 => c3_rst0, async_rst => c3_async_rst, sysclk_2x => c3_sysclk_2x, sysclk_2x_180 => c3_sysclk_2x_180, pll_ce_0 => c3_pll_ce_0, pll_ce_90 => c3_pll_ce_90, pll_lock => c3_pll_lock, mcb_drp_clk => c3_mcb_drp_clk ); -- wrapper instantiation memc3_wrapper_inst : memc3_wrapper generic map ( C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD, C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP, C_SIMULATION => C3_SIMULATION, C_P0_MASK_SIZE => C3_P0_MASK_SIZE, C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE, C_P1_MASK_SIZE => C3_P1_MASK_SIZE, C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE, C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS, C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0, C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1, C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2, C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3, C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4, C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5, C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6, C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7, C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8, C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9, C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10, C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11, C_MEM_TRAS => C3_MEM_TRAS, C_MEM_TRCD => C3_MEM_TRCD, C_MEM_TREFI => C3_MEM_TREFI, C_MEM_TRFC => C3_MEM_TRFC, C_MEM_TRP => C3_MEM_TRP, C_MEM_TWR => C3_MEM_TWR, C_MEM_TRTP => C3_MEM_TRTP, C_MEM_TWTR => C3_MEM_TWTR, C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER, C_NUM_DQ_PINS => C3_NUM_DQ_PINS, C_MEM_TYPE => C3_MEM_TYPE, C_MEM_DENSITY => C3_MEM_DENSITY, C_MEM_BURST_LEN => C3_MEM_BURST_LEN, C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY, C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH, C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH, C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS, C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS, C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT, C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN, C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR, C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR, C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY, C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS, C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT, C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY, C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR, C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT, C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR, C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS, C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS, C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE, C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY, C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL, C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL, C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL, C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL, C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL, C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL, C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL, C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL, C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL, C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL, C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL, C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL, C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL, C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL, C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL, C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL, C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL, C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL, C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL, C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL, C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL, C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL ) port map ( mcb3_dram_dq => mcb3_dram_dq, mcb3_dram_a => mcb3_dram_a, mcb3_dram_ba => mcb3_dram_ba, mcb3_dram_ras_n => mcb3_dram_ras_n, mcb3_dram_cas_n => mcb3_dram_cas_n, mcb3_dram_we_n => mcb3_dram_we_n, mcb3_dram_odt => mcb3_dram_odt, mcb3_dram_cke => mcb3_dram_cke, mcb3_dram_dm => mcb3_dram_dm, mcb3_dram_udqs => mcb3_dram_udqs, mcb3_dram_udqs_n => mcb3_dram_udqs_n, mcb3_rzq => mcb3_rzq, mcb3_zio => mcb3_zio, mcb3_dram_udm => mcb3_dram_udm, calib_done => c3_calib_done, async_rst => c3_async_rst, sysclk_2x => c3_sysclk_2x, sysclk_2x_180 => c3_sysclk_2x_180, pll_ce_0 => c3_pll_ce_0, pll_ce_90 => c3_pll_ce_90, pll_lock => c3_pll_lock, mcb_drp_clk => c3_mcb_drp_clk, mcb3_dram_dqs => mcb3_dram_dqs, mcb3_dram_dqs_n => mcb3_dram_dqs_n, mcb3_dram_ck => mcb3_dram_ck, mcb3_dram_ck_n => mcb3_dram_ck_n, p2_cmd_clk => c3_clk0, p2_cmd_en => c3_p2_cmd_en, p2_cmd_instr => c3_p2_cmd_instr, p2_cmd_bl => c3_p2_cmd_bl, p2_cmd_byte_addr => c3_p2_cmd_byte_addr, p2_cmd_empty => c3_p2_cmd_empty, p2_cmd_full => c3_p2_cmd_full, p2_rd_clk => c3_clk0, p2_rd_en => c3_p2_rd_en, p2_rd_data => c3_p2_rd_data, p2_rd_full => c3_p2_rd_full, p2_rd_empty => c3_p2_rd_empty, p2_rd_count => c3_p2_rd_count, p2_rd_overflow => c3_p2_rd_overflow, p2_rd_error => c3_p2_rd_error, p3_cmd_clk => c3_clk0, p3_cmd_en => c3_p3_cmd_en, p3_cmd_instr => c3_p3_cmd_instr, p3_cmd_bl => c3_p3_cmd_bl, p3_cmd_byte_addr => c3_p3_cmd_byte_addr, p3_cmd_empty => c3_p3_cmd_empty, p3_cmd_full => c3_p3_cmd_full, p3_wr_clk => c3_clk0, p3_wr_en => c3_p3_wr_en, p3_wr_mask => c3_p3_wr_mask, p3_wr_data => c3_p3_wr_data, p3_wr_full => c3_p3_wr_full, p3_wr_empty => c3_p3_wr_empty, p3_wr_count => c3_p3_wr_count, p3_wr_underrun => c3_p3_wr_underrun, p3_wr_error => c3_p3_wr_error, selfrefresh_enter => c3_selfrefresh_enter, selfrefresh_mode => c3_selfrefresh_mode ); memc3_tb_top_inst : memc3_tb_top generic map ( C_SIMULATION => C3_SIMULATION, C_P0_MASK_SIZE => C3_P0_MASK_SIZE, C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE, C_P1_MASK_SIZE => C3_P1_MASK_SIZE, C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE, C_NUM_DQ_PINS => C3_NUM_DQ_PINS, C_MEM_BURST_LEN => C3_MEM_BURST_LEN, C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS, C_SMALL_DEVICE => C3_SMALL_DEVICE, C_p2_BEGIN_ADDRESS => C3_p2_BEGIN_ADDRESS, C_p2_DATA_MODE => C3_p2_DATA_MODE, C_p2_END_ADDRESS => C3_p2_END_ADDRESS, C_p2_PRBS_EADDR_MASK_POS => C3_p2_PRBS_EADDR_MASK_POS, C_p2_PRBS_SADDR_MASK_POS => C3_p2_PRBS_SADDR_MASK_POS, C_p3_BEGIN_ADDRESS => C3_p3_BEGIN_ADDRESS, C_p3_DATA_MODE => C3_p3_DATA_MODE, C_p3_END_ADDRESS => C3_p3_END_ADDRESS, C_p3_PRBS_EADDR_MASK_POS => C3_p3_PRBS_EADDR_MASK_POS, C_p3_PRBS_SADDR_MASK_POS => C3_p3_PRBS_SADDR_MASK_POS ) port map ( error => c3_error, calib_done => c3_calib_done, clk0 => c3_clk0, rst0 => c3_rst0, cmp_error => c3_cmp_error, cmp_data_valid => c3_cmp_data_valid, vio_modify_enable => c3_vio_modify_enable, error_status => c3_error_status, vio_data_mode_value => c3_vio_data_mode_value, vio_addr_mode_value => c3_vio_addr_mode_value, cmp_data => c3_cmp_data, p2_mcb_cmd_en_o => c3_p2_cmd_en, p2_mcb_cmd_instr_o => c3_p2_cmd_instr, p2_mcb_cmd_bl_o => c3_p2_cmd_bl, p2_mcb_cmd_addr_o => c3_p2_cmd_byte_addr, p2_mcb_cmd_full_i => c3_p2_cmd_full, p2_mcb_rd_en_o => c3_p2_rd_en, p2_mcb_rd_data_i => c3_p2_rd_data, p2_mcb_rd_empty_i => c3_p2_rd_empty, p2_mcb_rd_fifo_counts => c3_p2_rd_count, p3_mcb_cmd_en_o => c3_p3_cmd_en, p3_mcb_cmd_instr_o => c3_p3_cmd_instr, p3_mcb_cmd_bl_o => c3_p3_cmd_bl, p3_mcb_cmd_addr_o => c3_p3_cmd_byte_addr, p3_mcb_cmd_full_i => c3_p3_cmd_full, p3_mcb_wr_en_o => c3_p3_wr_en, p3_mcb_wr_mask_o => c3_p3_wr_mask, p3_mcb_wr_data_o => c3_p3_wr_data, p3_mcb_wr_full_i => c3_p3_wr_full, p3_mcb_wr_fifo_counts => c3_p3_wr_count ); end arc;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 3.92 -- \ \ Application : MIG -- / / Filename : example_top.vhd -- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $ -- \ \ / \ Date Created : Jul 03 2009 -- \___\/\___\ -- --Device : Spartan-6 --Design Name : DDR/DDR2/DDR3/LPDDR --Purpose : This is the design top level. which instantiates top wrapper, -- test bench top and infrastructure modules. --Reference : --Revision History : --***************************************************************************** library ieee; use ieee.std_logic_1164.all; entity example_top is generic ( C3_P0_MASK_SIZE : integer := 4; C3_P0_DATA_PORT_SIZE : integer := 32; C3_P1_MASK_SIZE : integer := 4; C3_P1_DATA_PORT_SIZE : integer := 32; C3_MEMCLK_PERIOD : integer := 3200; -- Memory data transfer clock period. C3_RST_ACT_LOW : integer := 0; -- # = 1 for active low reset, -- # = 0 for active high reset. C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED"; -- input clock type DIFFERENTIAL or SINGLE_ENDED. C3_CALIB_SOFT_IP : string := "TRUE"; -- # = TRUE, Enables the soft calibration logic, -- # = FALSE, Disables the soft calibration logic. C3_SIMULATION : string := "FALSE"; -- # = TRUE, Simulating the design. Useful to reduce the simulation time, -- # = FALSE, Implementing the design. C3_HW_TESTING : string := "FALSE"; -- Determines the address space accessed by the traffic generator, -- # = FALSE, Smaller address space, -- # = TRUE, Large address space. DEBUG_EN : integer := 0; -- # = 1, Enable debug signals/controls, -- = 0, Disable debug signals/controls. C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- The order in which user address is provided to the memory controller, -- ROW_BANK_COLUMN or BANK_ROW_COLUMN. C3_NUM_DQ_PINS : integer := 16; -- External memory data width. C3_MEM_ADDR_WIDTH : integer := 13; -- External memory address width. C3_MEM_BANKADDR_WIDTH : integer := 3 -- External memory bank address width. ); port ( calib_done : out std_logic; error : out std_logic; mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0); mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0); mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_rzq : inout std_logic; mcb3_zio : inout std_logic; mcb3_dram_udm : out std_logic; c3_sys_clk : in std_logic; c3_sys_rst_i : in std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic ); end example_top; architecture arc of example_top is component memc3_infrastructure is generic ( C_RST_ACT_LOW : integer; C_INPUT_CLK_TYPE : string; C_CLKOUT0_DIVIDE : integer; C_CLKOUT1_DIVIDE : integer; C_CLKOUT2_DIVIDE : integer; C_CLKOUT3_DIVIDE : integer; C_CLKFBOUT_MULT : integer; C_DIVCLK_DIVIDE : integer; C_INCLK_PERIOD : integer ); port ( sys_clk_p : in std_logic; sys_clk_n : in std_logic; sys_clk : in std_logic; sys_rst_i : in std_logic; clk0 : out std_logic; rst0 : out std_logic; async_rst : out std_logic; sysclk_2x : out std_logic; sysclk_2x_180 : out std_logic; pll_ce_0 : out std_logic; pll_ce_90 : out std_logic; pll_lock : out std_logic; mcb_drp_clk : out std_logic ); end component; component memc3_wrapper is generic ( C_MEMCLK_PERIOD : integer; C_CALIB_SOFT_IP : string; C_SIMULATION : string; C_P0_MASK_SIZE : integer; C_P0_DATA_PORT_SIZE : integer; C_P1_MASK_SIZE : integer; C_P1_DATA_PORT_SIZE : integer; C_ARB_NUM_TIME_SLOTS : integer; C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0); C_MEM_TRAS : integer; C_MEM_TRCD : integer; C_MEM_TREFI : integer; C_MEM_TRFC : integer; C_MEM_TRP : integer; C_MEM_TWR : integer; C_MEM_TRTP : integer; C_MEM_TWTR : integer; C_MEM_ADDR_ORDER : string; C_NUM_DQ_PINS : integer; C_MEM_TYPE : string; C_MEM_DENSITY : string; C_MEM_BURST_LEN : integer; C_MEM_CAS_LATENCY : integer; C_MEM_ADDR_WIDTH : integer; C_MEM_BANKADDR_WIDTH : integer; C_MEM_NUM_COL_BITS : integer; C_MEM_DDR1_2_ODS : string; C_MEM_DDR2_RTT : string; C_MEM_DDR2_DIFF_DQS_EN : string; C_MEM_DDR2_3_PA_SR : string; C_MEM_DDR2_3_HIGH_TEMP_SR : string; C_MEM_DDR3_CAS_LATENCY : integer; C_MEM_DDR3_ODS : string; C_MEM_DDR3_RTT : string; C_MEM_DDR3_CAS_WR_LATENCY : integer; C_MEM_DDR3_AUTO_SR : string; C_MEM_DDR3_DYN_WRT_ODT : string; C_MEM_MOBILE_PA_SR : string; C_MEM_MDDR_ODS : string; C_MC_CALIB_BYPASS : string; C_MC_CALIBRATION_MODE : string; C_MC_CALIBRATION_DELAY : string; C_SKIP_IN_TERM_CAL : integer; C_SKIP_DYNAMIC_CAL : integer; C_LDQSP_TAP_DELAY_VAL : integer; C_LDQSN_TAP_DELAY_VAL : integer; C_UDQSP_TAP_DELAY_VAL : integer; C_UDQSN_TAP_DELAY_VAL : integer; C_DQ0_TAP_DELAY_VAL : integer; C_DQ1_TAP_DELAY_VAL : integer; C_DQ2_TAP_DELAY_VAL : integer; C_DQ3_TAP_DELAY_VAL : integer; C_DQ4_TAP_DELAY_VAL : integer; C_DQ5_TAP_DELAY_VAL : integer; C_DQ6_TAP_DELAY_VAL : integer; C_DQ7_TAP_DELAY_VAL : integer; C_DQ8_TAP_DELAY_VAL : integer; C_DQ9_TAP_DELAY_VAL : integer; C_DQ10_TAP_DELAY_VAL : integer; C_DQ11_TAP_DELAY_VAL : integer; C_DQ12_TAP_DELAY_VAL : integer; C_DQ13_TAP_DELAY_VAL : integer; C_DQ14_TAP_DELAY_VAL : integer; C_DQ15_TAP_DELAY_VAL : integer ); port ( mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0); mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0); mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_rzq : inout std_logic; mcb3_zio : inout std_logic; mcb3_dram_udm : out std_logic; calib_done : out std_logic; async_rst : in std_logic; sysclk_2x : in std_logic; sysclk_2x_180 : in std_logic; pll_ce_0 : in std_logic; pll_ce_90 : in std_logic; pll_lock : in std_logic; mcb_drp_clk : in std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic; p2_cmd_clk : in std_logic; p2_cmd_en : in std_logic; p2_cmd_instr : in std_logic_vector(2 downto 0); p2_cmd_bl : in std_logic_vector(5 downto 0); p2_cmd_byte_addr : in std_logic_vector(29 downto 0); p2_cmd_empty : out std_logic; p2_cmd_full : out std_logic; p2_rd_clk : in std_logic; p2_rd_en : in std_logic; p2_rd_data : out std_logic_vector(31 downto 0); p2_rd_full : out std_logic; p2_rd_empty : out std_logic; p2_rd_count : out std_logic_vector(6 downto 0); p2_rd_overflow : out std_logic; p2_rd_error : out std_logic; p3_cmd_clk : in std_logic; p3_cmd_en : in std_logic; p3_cmd_instr : in std_logic_vector(2 downto 0); p3_cmd_bl : in std_logic_vector(5 downto 0); p3_cmd_byte_addr : in std_logic_vector(29 downto 0); p3_cmd_empty : out std_logic; p3_cmd_full : out std_logic; p3_wr_clk : in std_logic; p3_wr_en : in std_logic; p3_wr_mask : in std_logic_vector(3 downto 0); p3_wr_data : in std_logic_vector(31 downto 0); p3_wr_full : out std_logic; p3_wr_empty : out std_logic; p3_wr_count : out std_logic_vector(6 downto 0); p3_wr_underrun : out std_logic; p3_wr_error : out std_logic; selfrefresh_enter : in std_logic; selfrefresh_mode : out std_logic ); end component; component memc3_tb_top is generic ( C_SIMULATION : string; C_P0_MASK_SIZE : integer; C_P0_DATA_PORT_SIZE : integer; C_P1_MASK_SIZE : integer; C_P1_DATA_PORT_SIZE : integer; C_NUM_DQ_PINS : integer; C_MEM_BURST_LEN : integer; C_MEM_NUM_COL_BITS : integer; C_SMALL_DEVICE : string; C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0); C_p2_DATA_MODE : std_logic_vector(3 downto 0); C_p2_END_ADDRESS : std_logic_vector(31 downto 0); C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0); C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0); C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0); C_p3_DATA_MODE : std_logic_vector(3 downto 0); C_p3_END_ADDRESS : std_logic_vector(31 downto 0); C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0); C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) ); port ( error : out std_logic; calib_done : in std_logic; clk0 : in std_logic; rst0 : in std_logic; cmp_error : out std_logic; cmp_data_valid : out std_logic; vio_modify_enable : in std_logic; error_status : out std_logic_vector(127 downto 0); vio_data_mode_value : in std_logic_vector(2 downto 0); vio_addr_mode_value : in std_logic_vector(2 downto 0); cmp_data : out std_logic_vector(31 downto 0); p2_mcb_cmd_en_o : out std_logic; p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0); p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0); p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0); p2_mcb_cmd_full_i : in std_logic; p2_mcb_rd_en_o : out std_logic; p2_mcb_rd_data_i : in std_logic_vector(31 downto 0); p2_mcb_rd_empty_i : in std_logic; p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0); p3_mcb_cmd_en_o : out std_logic; p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0); p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0); p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0); p3_mcb_cmd_full_i : in std_logic; p3_mcb_wr_en_o : out std_logic; p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0); p3_mcb_wr_data_o : out std_logic_vector(31 downto 0); p3_mcb_wr_full_i : in std_logic; p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0) ); end component; function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is begin if (C3_HW_TESTING = "FALSE") then return val1; else return val2; end if; end function; constant C3_CLKOUT0_DIVIDE : integer := 1; constant C3_CLKOUT1_DIVIDE : integer := 1; constant C3_CLKOUT2_DIVIDE : integer := 16; constant C3_CLKOUT3_DIVIDE : integer := 8; constant C3_CLKFBOUT_MULT : integer := 2; constant C3_DIVCLK_DIVIDE : integer := 1; constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2)); constant C3_ARB_NUM_TIME_SLOTS : integer := 12; constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"32"; constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"23"; constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"32"; constant C3_MEM_TRAS : integer := 42500; constant C3_MEM_TRCD : integer := 12500; constant C3_MEM_TREFI : integer := 7800000; constant C3_MEM_TRFC : integer := 127500; constant C3_MEM_TRP : integer := 12500; constant C3_MEM_TWR : integer := 15000; constant C3_MEM_TRTP : integer := 7500; constant C3_MEM_TWTR : integer := 7500; constant C3_MEM_TYPE : string := "DDR2"; constant C3_MEM_DENSITY : string := "1Gb"; constant C3_MEM_BURST_LEN : integer := 4; constant C3_MEM_CAS_LATENCY : integer := 5; constant C3_MEM_NUM_COL_BITS : integer := 10; constant C3_MEM_DDR1_2_ODS : string := "FULL"; constant C3_MEM_DDR2_RTT : string := "50OHMS"; constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES"; constant C3_MEM_DDR2_3_PA_SR : string := "FULL"; constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL"; constant C3_MEM_DDR3_CAS_LATENCY : integer := 6; constant C3_MEM_DDR3_ODS : string := "DIV6"; constant C3_MEM_DDR3_RTT : string := "DIV2"; constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5; constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED"; constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF"; constant C3_MEM_MOBILE_PA_SR : string := "FULL"; constant C3_MEM_MDDR_ODS : string := "FULL"; constant C3_MC_CALIB_BYPASS : string := "NO"; constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION"; constant C3_MC_CALIBRATION_DELAY : string := "HALF"; constant C3_SKIP_IN_TERM_CAL : integer := 0; constant C3_SKIP_DYNAMIC_CAL : integer := 0; constant C3_LDQSP_TAP_DELAY_VAL : integer := 0; constant C3_LDQSN_TAP_DELAY_VAL : integer := 0; constant C3_UDQSP_TAP_DELAY_VAL : integer := 0; constant C3_UDQSN_TAP_DELAY_VAL : integer := 0; constant C3_DQ0_TAP_DELAY_VAL : integer := 0; constant C3_DQ1_TAP_DELAY_VAL : integer := 0; constant C3_DQ2_TAP_DELAY_VAL : integer := 0; constant C3_DQ3_TAP_DELAY_VAL : integer := 0; constant C3_DQ4_TAP_DELAY_VAL : integer := 0; constant C3_DQ5_TAP_DELAY_VAL : integer := 0; constant C3_DQ6_TAP_DELAY_VAL : integer := 0; constant C3_DQ7_TAP_DELAY_VAL : integer := 0; constant C3_DQ8_TAP_DELAY_VAL : integer := 0; constant C3_DQ9_TAP_DELAY_VAL : integer := 0; constant C3_DQ10_TAP_DELAY_VAL : integer := 0; constant C3_DQ11_TAP_DELAY_VAL : integer := 0; constant C3_DQ12_TAP_DELAY_VAL : integer := 0; constant C3_DQ13_TAP_DELAY_VAL : integer := 0; constant C3_DQ14_TAP_DELAY_VAL : integer := 0; constant C3_DQ15_TAP_DELAY_VAL : integer := 0; constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device -- as most of them cannot fit the complete example design when the -- Chip scope modules are enabled constant C3_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000"); constant C3_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010"; constant C3_p2_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff"); constant C3_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000"); constant C3_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000"); constant C3_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000"); constant C3_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010"; constant C3_p3_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000006ff", x"06ffffff"); constant C3_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"f8000000"); constant C3_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000"); signal c3_sys_clk_p : std_logic; signal c3_sys_clk_n : std_logic; signal c3_error : std_logic; signal c3_calib_done : std_logic; signal c3_clk0 : std_logic; signal c3_rst0 : std_logic; signal c3_async_rst : std_logic; signal c3_sysclk_2x : std_logic; signal c3_sysclk_2x_180 : std_logic; signal c3_pll_ce_0 : std_logic; signal c3_pll_ce_90 : std_logic; signal c3_pll_lock : std_logic; signal c3_mcb_drp_clk : std_logic; signal c3_cmp_error : std_logic; signal c3_cmp_data_valid : std_logic; signal c3_vio_modify_enable : std_logic; signal c3_error_status : std_logic_vector(127 downto 0); signal c3_vio_data_mode_value : std_logic_vector(2 downto 0); signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0); signal c3_cmp_data : std_logic_vector(31 downto 0); signal c3_p2_cmd_en : std_logic; signal c3_p2_cmd_instr : std_logic_vector(2 downto 0); signal c3_p2_cmd_bl : std_logic_vector(5 downto 0); signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0); signal c3_p2_cmd_empty : std_logic; signal c3_p2_cmd_full : std_logic; signal c3_p2_rd_en : std_logic; signal c3_p2_rd_data : std_logic_vector(31 downto 0); signal c3_p2_rd_full : std_logic; signal c3_p2_rd_empty : std_logic; signal c3_p2_rd_count : std_logic_vector(6 downto 0); signal c3_p2_rd_overflow : std_logic; signal c3_p2_rd_error : std_logic; signal c3_p3_cmd_en : std_logic; signal c3_p3_cmd_instr : std_logic_vector(2 downto 0); signal c3_p3_cmd_bl : std_logic_vector(5 downto 0); signal c3_p3_cmd_byte_addr : std_logic_vector(29 downto 0); signal c3_p3_cmd_empty : std_logic; signal c3_p3_cmd_full : std_logic; signal c3_p3_wr_en : std_logic; signal c3_p3_wr_mask : std_logic_vector(3 downto 0); signal c3_p3_wr_data : std_logic_vector(31 downto 0); signal c3_p3_wr_full : std_logic; signal c3_p3_wr_empty : std_logic; signal c3_p3_wr_count : std_logic_vector(6 downto 0); signal c3_p3_wr_underrun : std_logic; signal c3_p3_wr_error : std_logic; signal c3_selfrefresh_enter : std_logic; signal c3_selfrefresh_mode : std_logic; begin error <= c3_error; calib_done <= c3_calib_done; c3_sys_clk_p <= '0'; c3_sys_clk_n <= '0'; c3_selfrefresh_enter <= '0'; memc3_infrastructure_inst : memc3_infrastructure generic map ( C_RST_ACT_LOW => C3_RST_ACT_LOW, C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE, C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE, C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE, C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE, C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE, C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT, C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE, C_INCLK_PERIOD => C3_INCLK_PERIOD ) port map ( sys_clk_p => c3_sys_clk_p, sys_clk_n => c3_sys_clk_n, sys_clk => c3_sys_clk, sys_rst_i => c3_sys_rst_i, clk0 => c3_clk0, rst0 => c3_rst0, async_rst => c3_async_rst, sysclk_2x => c3_sysclk_2x, sysclk_2x_180 => c3_sysclk_2x_180, pll_ce_0 => c3_pll_ce_0, pll_ce_90 => c3_pll_ce_90, pll_lock => c3_pll_lock, mcb_drp_clk => c3_mcb_drp_clk ); -- wrapper instantiation memc3_wrapper_inst : memc3_wrapper generic map ( C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD, C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP, C_SIMULATION => C3_SIMULATION, C_P0_MASK_SIZE => C3_P0_MASK_SIZE, C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE, C_P1_MASK_SIZE => C3_P1_MASK_SIZE, C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE, C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS, C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0, C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1, C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2, C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3, C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4, C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5, C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6, C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7, C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8, C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9, C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10, C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11, C_MEM_TRAS => C3_MEM_TRAS, C_MEM_TRCD => C3_MEM_TRCD, C_MEM_TREFI => C3_MEM_TREFI, C_MEM_TRFC => C3_MEM_TRFC, C_MEM_TRP => C3_MEM_TRP, C_MEM_TWR => C3_MEM_TWR, C_MEM_TRTP => C3_MEM_TRTP, C_MEM_TWTR => C3_MEM_TWTR, C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER, C_NUM_DQ_PINS => C3_NUM_DQ_PINS, C_MEM_TYPE => C3_MEM_TYPE, C_MEM_DENSITY => C3_MEM_DENSITY, C_MEM_BURST_LEN => C3_MEM_BURST_LEN, C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY, C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH, C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH, C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS, C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS, C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT, C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN, C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR, C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR, C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY, C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS, C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT, C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY, C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR, C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT, C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR, C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS, C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS, C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE, C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY, C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL, C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL, C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL, C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL, C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL, C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL, C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL, C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL, C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL, C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL, C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL, C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL, C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL, C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL, C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL, C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL, C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL, C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL, C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL, C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL, C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL, C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL ) port map ( mcb3_dram_dq => mcb3_dram_dq, mcb3_dram_a => mcb3_dram_a, mcb3_dram_ba => mcb3_dram_ba, mcb3_dram_ras_n => mcb3_dram_ras_n, mcb3_dram_cas_n => mcb3_dram_cas_n, mcb3_dram_we_n => mcb3_dram_we_n, mcb3_dram_odt => mcb3_dram_odt, mcb3_dram_cke => mcb3_dram_cke, mcb3_dram_dm => mcb3_dram_dm, mcb3_dram_udqs => mcb3_dram_udqs, mcb3_dram_udqs_n => mcb3_dram_udqs_n, mcb3_rzq => mcb3_rzq, mcb3_zio => mcb3_zio, mcb3_dram_udm => mcb3_dram_udm, calib_done => c3_calib_done, async_rst => c3_async_rst, sysclk_2x => c3_sysclk_2x, sysclk_2x_180 => c3_sysclk_2x_180, pll_ce_0 => c3_pll_ce_0, pll_ce_90 => c3_pll_ce_90, pll_lock => c3_pll_lock, mcb_drp_clk => c3_mcb_drp_clk, mcb3_dram_dqs => mcb3_dram_dqs, mcb3_dram_dqs_n => mcb3_dram_dqs_n, mcb3_dram_ck => mcb3_dram_ck, mcb3_dram_ck_n => mcb3_dram_ck_n, p2_cmd_clk => c3_clk0, p2_cmd_en => c3_p2_cmd_en, p2_cmd_instr => c3_p2_cmd_instr, p2_cmd_bl => c3_p2_cmd_bl, p2_cmd_byte_addr => c3_p2_cmd_byte_addr, p2_cmd_empty => c3_p2_cmd_empty, p2_cmd_full => c3_p2_cmd_full, p2_rd_clk => c3_clk0, p2_rd_en => c3_p2_rd_en, p2_rd_data => c3_p2_rd_data, p2_rd_full => c3_p2_rd_full, p2_rd_empty => c3_p2_rd_empty, p2_rd_count => c3_p2_rd_count, p2_rd_overflow => c3_p2_rd_overflow, p2_rd_error => c3_p2_rd_error, p3_cmd_clk => c3_clk0, p3_cmd_en => c3_p3_cmd_en, p3_cmd_instr => c3_p3_cmd_instr, p3_cmd_bl => c3_p3_cmd_bl, p3_cmd_byte_addr => c3_p3_cmd_byte_addr, p3_cmd_empty => c3_p3_cmd_empty, p3_cmd_full => c3_p3_cmd_full, p3_wr_clk => c3_clk0, p3_wr_en => c3_p3_wr_en, p3_wr_mask => c3_p3_wr_mask, p3_wr_data => c3_p3_wr_data, p3_wr_full => c3_p3_wr_full, p3_wr_empty => c3_p3_wr_empty, p3_wr_count => c3_p3_wr_count, p3_wr_underrun => c3_p3_wr_underrun, p3_wr_error => c3_p3_wr_error, selfrefresh_enter => c3_selfrefresh_enter, selfrefresh_mode => c3_selfrefresh_mode ); memc3_tb_top_inst : memc3_tb_top generic map ( C_SIMULATION => C3_SIMULATION, C_P0_MASK_SIZE => C3_P0_MASK_SIZE, C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE, C_P1_MASK_SIZE => C3_P1_MASK_SIZE, C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE, C_NUM_DQ_PINS => C3_NUM_DQ_PINS, C_MEM_BURST_LEN => C3_MEM_BURST_LEN, C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS, C_SMALL_DEVICE => C3_SMALL_DEVICE, C_p2_BEGIN_ADDRESS => C3_p2_BEGIN_ADDRESS, C_p2_DATA_MODE => C3_p2_DATA_MODE, C_p2_END_ADDRESS => C3_p2_END_ADDRESS, C_p2_PRBS_EADDR_MASK_POS => C3_p2_PRBS_EADDR_MASK_POS, C_p2_PRBS_SADDR_MASK_POS => C3_p2_PRBS_SADDR_MASK_POS, C_p3_BEGIN_ADDRESS => C3_p3_BEGIN_ADDRESS, C_p3_DATA_MODE => C3_p3_DATA_MODE, C_p3_END_ADDRESS => C3_p3_END_ADDRESS, C_p3_PRBS_EADDR_MASK_POS => C3_p3_PRBS_EADDR_MASK_POS, C_p3_PRBS_SADDR_MASK_POS => C3_p3_PRBS_SADDR_MASK_POS ) port map ( error => c3_error, calib_done => c3_calib_done, clk0 => c3_clk0, rst0 => c3_rst0, cmp_error => c3_cmp_error, cmp_data_valid => c3_cmp_data_valid, vio_modify_enable => c3_vio_modify_enable, error_status => c3_error_status, vio_data_mode_value => c3_vio_data_mode_value, vio_addr_mode_value => c3_vio_addr_mode_value, cmp_data => c3_cmp_data, p2_mcb_cmd_en_o => c3_p2_cmd_en, p2_mcb_cmd_instr_o => c3_p2_cmd_instr, p2_mcb_cmd_bl_o => c3_p2_cmd_bl, p2_mcb_cmd_addr_o => c3_p2_cmd_byte_addr, p2_mcb_cmd_full_i => c3_p2_cmd_full, p2_mcb_rd_en_o => c3_p2_rd_en, p2_mcb_rd_data_i => c3_p2_rd_data, p2_mcb_rd_empty_i => c3_p2_rd_empty, p2_mcb_rd_fifo_counts => c3_p2_rd_count, p3_mcb_cmd_en_o => c3_p3_cmd_en, p3_mcb_cmd_instr_o => c3_p3_cmd_instr, p3_mcb_cmd_bl_o => c3_p3_cmd_bl, p3_mcb_cmd_addr_o => c3_p3_cmd_byte_addr, p3_mcb_cmd_full_i => c3_p3_cmd_full, p3_mcb_wr_en_o => c3_p3_wr_en, p3_mcb_wr_mask_o => c3_p3_wr_mask, p3_mcb_wr_data_o => c3_p3_wr_data, p3_mcb_wr_full_i => c3_p3_wr_full, p3_mcb_wr_fifo_counts => c3_p3_wr_count ); end arc;
---------------------------------------------------------------------------- -- UART_TX_CTRL.vhd -- UART Data Transfer Component ---------------------------------------------------------------------------- -- Author: Sam Bobrowicz -- Copyright 2011 Digilent, Inc. ---------------------------------------------------------------------------- -- ---------------------------------------------------------------------------- -- This component may be used to transfer data over a UART device. It will -- serialize a byte of data and transmit it over a TXD line. The serialized -- data has the following characteristics: -- *9600 Baud Rate -- *8 data bits, LSB first -- *1 stop bit -- *no parity -- -- Port Descriptions: -- -- SEND - Used to trigger a send operation. The upper layer logic should -- set this signal high for a single clock cycle to trigger a -- send. When this signal is set high DATA must be valid . Should -- not be asserted unless READY is high. -- DATA - The parallel data to be sent. Must be valid the clock cycle -- that SEND has gone high. -- CLK - A 100 MHz clock is expected -- READY - This signal goes low once a send operation has begun and -- remains low until it has completed and the module is ready to -- send another byte. -- UART_TX - This signal should be routed to the appropriate TX pin of the -- external UART device. -- ---------------------------------------------------------------------------- -- ---------------------------------------------------------------------------- -- Revision History: -- 08/08/2011(SamB): Created using Xilinx Tools 13.2 ---------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_unsigned.all; entity UART_TX_CTRL is Port ( SEND : in STD_LOGIC; DATA : in STD_LOGIC_VECTOR (7 downto 0); CLK : in STD_LOGIC; READY : out STD_LOGIC; UART_TX : out STD_LOGIC); end UART_TX_CTRL; architecture Behavioral of UART_TX_CTRL is type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT); constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1 constant BIT_INDEX_MAX : natural := 10; --Counter that keeps track of the number of clock cycles the current bit has been held stable over the --UART TX line. It is used to signal when the ne signal bitTmr : std_logic_vector(13 downto 0) := (others => '0'); --combinatorial logic that goes high when bitTmr has counted to the proper value to ensure --a 9600 baud rate signal bitDone : std_logic; --Contains the index of the next bit in txData that needs to be transferred signal bitIndex : natural; --a register that holds the current data being sent over the UART TX line signal txBit : std_logic := '1'; --A register that contains the whole data packet to be sent, including start and stop bits. signal txData : std_logic_vector(9 downto 0); signal txState : TX_STATE_TYPE := RDY; begin --Next state logic next_txState_process : process (CLK) begin if (rising_edge(CLK)) then case txState is when RDY => if (SEND = '1') then txState <= LOAD_BIT; end if; when LOAD_BIT => txState <= SEND_BIT; when SEND_BIT => if (bitDone = '1') then if (bitIndex = BIT_INDEX_MAX) then txState <= RDY; else txState <= LOAD_BIT; end if; end if; when others=> --should never be reached txState <= RDY; end case; end if; end process; bit_timing_process : process (CLK) begin if (rising_edge(CLK)) then if (txState = RDY) then bitTmr <= (others => '0'); else if (bitDone = '1') then bitTmr <= (others => '0'); else bitTmr <= bitTmr + 1; end if; end if; end if; end process; bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else '0'; bit_counting_process : process (CLK) begin if (rising_edge(CLK)) then if (txState = RDY) then bitIndex <= 0; elsif (txState = LOAD_BIT) then bitIndex <= bitIndex + 1; end if; end if; end process; tx_data_latch_process : process (CLK) begin if (rising_edge(CLK)) then if (SEND = '1') then txData <= '1' & DATA & '0'; end if; end if; end process; tx_bit_process : process (CLK) begin if (rising_edge(CLK)) then if (txState = RDY) then txBit <= '1'; elsif (txState = LOAD_BIT) then txBit <= txData(bitIndex); end if; end if; end process; UART_TX <= txBit; READY <= '1' when (txState = RDY) else '0'; end Behavioral;
---------------------------------------------------------------------------------- -- group_selector.vhd -- -- Copyright (C) 2011 -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- multiplexes valid groups, output is registered -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity group_selector is port( clock : in std_logic; la_input : in std_logic_vector(31 downto 0); la_input_ready : in std_logic; output : out std_logic_vector(31 downto 0); output_ready : out std_logic; disabledGroups : in std_logic_vector(3 downto 0) ); end group_selector; architecture behavioral of group_selector is signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0); signal tmp : std_logic_vector(31 downto 0); begin ib0 <= la_input(7 downto 0); ib1 <= la_input(15 downto 8); ib2 <= la_input(23 downto 16); ib3 <= la_input(31 downto 24); tmp <= -- select 8-bit enabled group x"000000" & ib0 when disabledGroups = "1110" else x"000000" & ib1 when disabledGroups = "1101" else x"000000" & ib2 when disabledGroups = "1011" else x"000000" & ib3 when disabledGroups = "0111" else -- select 2 8-bit enabled groups x"0000" & ib1 & ib0 when disabledGroups = "1100" else x"0000" & ib2 & ib0 when disabledGroups = "1010" else x"0000" & ib3 & ib0 when disabledGroups = "0110" else x"0000" & ib2 & ib1 when disabledGroups = "1001" else x"0000" & ib3 & ib1 when disabledGroups = "0101" else x"0000" & ib3 & ib2 when disabledGroups = "0011" else -- clear unused group ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else -- full la_input when disabledGroups = "0000" else (others => 'X'); process (clock) begin if rising_edge(clock) then output <= tmp; output_ready <= la_input_ready; end if; end process; end behavioral;
---------------------------------------------------------------------------------- -- group_selector.vhd -- -- Copyright (C) 2011 -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- multiplexes valid groups, output is registered -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity group_selector is port( clock : in std_logic; la_input : in std_logic_vector(31 downto 0); la_input_ready : in std_logic; output : out std_logic_vector(31 downto 0); output_ready : out std_logic; disabledGroups : in std_logic_vector(3 downto 0) ); end group_selector; architecture behavioral of group_selector is signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0); signal tmp : std_logic_vector(31 downto 0); begin ib0 <= la_input(7 downto 0); ib1 <= la_input(15 downto 8); ib2 <= la_input(23 downto 16); ib3 <= la_input(31 downto 24); tmp <= -- select 8-bit enabled group x"000000" & ib0 when disabledGroups = "1110" else x"000000" & ib1 when disabledGroups = "1101" else x"000000" & ib2 when disabledGroups = "1011" else x"000000" & ib3 when disabledGroups = "0111" else -- select 2 8-bit enabled groups x"0000" & ib1 & ib0 when disabledGroups = "1100" else x"0000" & ib2 & ib0 when disabledGroups = "1010" else x"0000" & ib3 & ib0 when disabledGroups = "0110" else x"0000" & ib2 & ib1 when disabledGroups = "1001" else x"0000" & ib3 & ib1 when disabledGroups = "0101" else x"0000" & ib3 & ib2 when disabledGroups = "0011" else -- clear unused group ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else -- full la_input when disabledGroups = "0000" else (others => 'X'); process (clock) begin if rising_edge(clock) then output <= tmp; output_ready <= la_input_ready; end if; end process; end behavioral;
---------------------------------------------------------------------------------- -- group_selector.vhd -- -- Copyright (C) 2011 -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- multiplexes valid groups, output is registered -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity group_selector is port( clock : in std_logic; la_input : in std_logic_vector(31 downto 0); la_input_ready : in std_logic; output : out std_logic_vector(31 downto 0); output_ready : out std_logic; disabledGroups : in std_logic_vector(3 downto 0) ); end group_selector; architecture behavioral of group_selector is signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0); signal tmp : std_logic_vector(31 downto 0); begin ib0 <= la_input(7 downto 0); ib1 <= la_input(15 downto 8); ib2 <= la_input(23 downto 16); ib3 <= la_input(31 downto 24); tmp <= -- select 8-bit enabled group x"000000" & ib0 when disabledGroups = "1110" else x"000000" & ib1 when disabledGroups = "1101" else x"000000" & ib2 when disabledGroups = "1011" else x"000000" & ib3 when disabledGroups = "0111" else -- select 2 8-bit enabled groups x"0000" & ib1 & ib0 when disabledGroups = "1100" else x"0000" & ib2 & ib0 when disabledGroups = "1010" else x"0000" & ib3 & ib0 when disabledGroups = "0110" else x"0000" & ib2 & ib1 when disabledGroups = "1001" else x"0000" & ib3 & ib1 when disabledGroups = "0101" else x"0000" & ib3 & ib2 when disabledGroups = "0011" else -- clear unused group ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else -- full la_input when disabledGroups = "0000" else (others => 'X'); process (clock) begin if rising_edge(clock) then output <= tmp; output_ready <= la_input_ready; end if; end process; end behavioral;
---------------------------------------------------------------------------------- -- group_selector.vhd -- -- Copyright (C) 2011 -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- multiplexes valid groups, output is registered -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity group_selector is port( clock : in std_logic; la_input : in std_logic_vector(31 downto 0); la_input_ready : in std_logic; output : out std_logic_vector(31 downto 0); output_ready : out std_logic; disabledGroups : in std_logic_vector(3 downto 0) ); end group_selector; architecture behavioral of group_selector is signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0); signal tmp : std_logic_vector(31 downto 0); begin ib0 <= la_input(7 downto 0); ib1 <= la_input(15 downto 8); ib2 <= la_input(23 downto 16); ib3 <= la_input(31 downto 24); tmp <= -- select 8-bit enabled group x"000000" & ib0 when disabledGroups = "1110" else x"000000" & ib1 when disabledGroups = "1101" else x"000000" & ib2 when disabledGroups = "1011" else x"000000" & ib3 when disabledGroups = "0111" else -- select 2 8-bit enabled groups x"0000" & ib1 & ib0 when disabledGroups = "1100" else x"0000" & ib2 & ib0 when disabledGroups = "1010" else x"0000" & ib3 & ib0 when disabledGroups = "0110" else x"0000" & ib2 & ib1 when disabledGroups = "1001" else x"0000" & ib3 & ib1 when disabledGroups = "0101" else x"0000" & ib3 & ib2 when disabledGroups = "0011" else -- clear unused group ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else -- full la_input when disabledGroups = "0000" else (others => 'X'); process (clock) begin if rising_edge(clock) then output <= tmp; output_ready <= la_input_ready; end if; end process; end behavioral;
---------------------------------------------------------------------------------- -- group_selector.vhd -- -- Copyright (C) 2011 -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- multiplexes valid groups, output is registered -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity group_selector is port( clock : in std_logic; la_input : in std_logic_vector(31 downto 0); la_input_ready : in std_logic; output : out std_logic_vector(31 downto 0); output_ready : out std_logic; disabledGroups : in std_logic_vector(3 downto 0) ); end group_selector; architecture behavioral of group_selector is signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0); signal tmp : std_logic_vector(31 downto 0); begin ib0 <= la_input(7 downto 0); ib1 <= la_input(15 downto 8); ib2 <= la_input(23 downto 16); ib3 <= la_input(31 downto 24); tmp <= -- select 8-bit enabled group x"000000" & ib0 when disabledGroups = "1110" else x"000000" & ib1 when disabledGroups = "1101" else x"000000" & ib2 when disabledGroups = "1011" else x"000000" & ib3 when disabledGroups = "0111" else -- select 2 8-bit enabled groups x"0000" & ib1 & ib0 when disabledGroups = "1100" else x"0000" & ib2 & ib0 when disabledGroups = "1010" else x"0000" & ib3 & ib0 when disabledGroups = "0110" else x"0000" & ib2 & ib1 when disabledGroups = "1001" else x"0000" & ib3 & ib1 when disabledGroups = "0101" else x"0000" & ib3 & ib2 when disabledGroups = "0011" else -- clear unused group ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else -- full la_input when disabledGroups = "0000" else (others => 'X'); process (clock) begin if rising_edge(clock) then output <= tmp; output_ready <= la_input_ready; end if; end process; end behavioral;
---------------------------------------------------------------------------------- -- group_selector.vhd -- -- Copyright (C) 2011 -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- multiplexes valid groups, output is registered -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity group_selector is port( clock : in std_logic; la_input : in std_logic_vector(31 downto 0); la_input_ready : in std_logic; output : out std_logic_vector(31 downto 0); output_ready : out std_logic; disabledGroups : in std_logic_vector(3 downto 0) ); end group_selector; architecture behavioral of group_selector is signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0); signal tmp : std_logic_vector(31 downto 0); begin ib0 <= la_input(7 downto 0); ib1 <= la_input(15 downto 8); ib2 <= la_input(23 downto 16); ib3 <= la_input(31 downto 24); tmp <= -- select 8-bit enabled group x"000000" & ib0 when disabledGroups = "1110" else x"000000" & ib1 when disabledGroups = "1101" else x"000000" & ib2 when disabledGroups = "1011" else x"000000" & ib3 when disabledGroups = "0111" else -- select 2 8-bit enabled groups x"0000" & ib1 & ib0 when disabledGroups = "1100" else x"0000" & ib2 & ib0 when disabledGroups = "1010" else x"0000" & ib3 & ib0 when disabledGroups = "0110" else x"0000" & ib2 & ib1 when disabledGroups = "1001" else x"0000" & ib3 & ib1 when disabledGroups = "0101" else x"0000" & ib3 & ib2 when disabledGroups = "0011" else -- clear unused group ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else -- full la_input when disabledGroups = "0000" else (others => 'X'); process (clock) begin if rising_edge(clock) then output <= tmp; output_ready <= la_input_ready; end if; end process; end behavioral;
---------------------------------------------------------------------------------- -- group_selector.vhd -- -- Copyright (C) 2011 -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- multiplexes valid groups, output is registered -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity group_selector is port( clock : in std_logic; la_input : in std_logic_vector(31 downto 0); la_input_ready : in std_logic; output : out std_logic_vector(31 downto 0); output_ready : out std_logic; disabledGroups : in std_logic_vector(3 downto 0) ); end group_selector; architecture behavioral of group_selector is signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0); signal tmp : std_logic_vector(31 downto 0); begin ib0 <= la_input(7 downto 0); ib1 <= la_input(15 downto 8); ib2 <= la_input(23 downto 16); ib3 <= la_input(31 downto 24); tmp <= -- select 8-bit enabled group x"000000" & ib0 when disabledGroups = "1110" else x"000000" & ib1 when disabledGroups = "1101" else x"000000" & ib2 when disabledGroups = "1011" else x"000000" & ib3 when disabledGroups = "0111" else -- select 2 8-bit enabled groups x"0000" & ib1 & ib0 when disabledGroups = "1100" else x"0000" & ib2 & ib0 when disabledGroups = "1010" else x"0000" & ib3 & ib0 when disabledGroups = "0110" else x"0000" & ib2 & ib1 when disabledGroups = "1001" else x"0000" & ib3 & ib1 when disabledGroups = "0101" else x"0000" & ib3 & ib2 when disabledGroups = "0011" else -- clear unused group ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else -- full la_input when disabledGroups = "0000" else (others => 'X'); process (clock) begin if rising_edge(clock) then output <= tmp; output_ready <= la_input_ready; end if; end process; end behavioral;
---------------------------------------------------------------------------------- -- group_selector.vhd -- -- Copyright (C) 2011 -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- multiplexes valid groups, output is registered -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity group_selector is port( clock : in std_logic; la_input : in std_logic_vector(31 downto 0); la_input_ready : in std_logic; output : out std_logic_vector(31 downto 0); output_ready : out std_logic; disabledGroups : in std_logic_vector(3 downto 0) ); end group_selector; architecture behavioral of group_selector is signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0); signal tmp : std_logic_vector(31 downto 0); begin ib0 <= la_input(7 downto 0); ib1 <= la_input(15 downto 8); ib2 <= la_input(23 downto 16); ib3 <= la_input(31 downto 24); tmp <= -- select 8-bit enabled group x"000000" & ib0 when disabledGroups = "1110" else x"000000" & ib1 when disabledGroups = "1101" else x"000000" & ib2 when disabledGroups = "1011" else x"000000" & ib3 when disabledGroups = "0111" else -- select 2 8-bit enabled groups x"0000" & ib1 & ib0 when disabledGroups = "1100" else x"0000" & ib2 & ib0 when disabledGroups = "1010" else x"0000" & ib3 & ib0 when disabledGroups = "0110" else x"0000" & ib2 & ib1 when disabledGroups = "1001" else x"0000" & ib3 & ib1 when disabledGroups = "0101" else x"0000" & ib3 & ib2 when disabledGroups = "0011" else -- clear unused group ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else -- full la_input when disabledGroups = "0000" else (others => 'X'); process (clock) begin if rising_edge(clock) then output <= tmp; output_ready <= la_input_ready; end if; end process; end behavioral;
---------------------------------------------------------------------------------- -- group_selector.vhd -- -- Copyright (C) 2011 -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- multiplexes valid groups, output is registered -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity group_selector is port( clock : in std_logic; la_input : in std_logic_vector(31 downto 0); la_input_ready : in std_logic; output : out std_logic_vector(31 downto 0); output_ready : out std_logic; disabledGroups : in std_logic_vector(3 downto 0) ); end group_selector; architecture behavioral of group_selector is signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0); signal tmp : std_logic_vector(31 downto 0); begin ib0 <= la_input(7 downto 0); ib1 <= la_input(15 downto 8); ib2 <= la_input(23 downto 16); ib3 <= la_input(31 downto 24); tmp <= -- select 8-bit enabled group x"000000" & ib0 when disabledGroups = "1110" else x"000000" & ib1 when disabledGroups = "1101" else x"000000" & ib2 when disabledGroups = "1011" else x"000000" & ib3 when disabledGroups = "0111" else -- select 2 8-bit enabled groups x"0000" & ib1 & ib0 when disabledGroups = "1100" else x"0000" & ib2 & ib0 when disabledGroups = "1010" else x"0000" & ib3 & ib0 when disabledGroups = "0110" else x"0000" & ib2 & ib1 when disabledGroups = "1001" else x"0000" & ib3 & ib1 when disabledGroups = "0101" else x"0000" & ib3 & ib2 when disabledGroups = "0011" else -- clear unused group ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else -- full la_input when disabledGroups = "0000" else (others => 'X'); process (clock) begin if rising_edge(clock) then output <= tmp; output_ready <= la_input_ready; end if; end process; end behavioral;
---------------------------------------------------------------------------------- -- group_selector.vhd -- -- Copyright (C) 2011 -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA -- ---------------------------------------------------------------------------------- -- -- Details: http://www.sump.org/projects/analyzer/ -- -- multiplexes valid groups, output is registered -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity group_selector is port( clock : in std_logic; la_input : in std_logic_vector(31 downto 0); la_input_ready : in std_logic; output : out std_logic_vector(31 downto 0); output_ready : out std_logic; disabledGroups : in std_logic_vector(3 downto 0) ); end group_selector; architecture behavioral of group_selector is signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0); signal tmp : std_logic_vector(31 downto 0); begin ib0 <= la_input(7 downto 0); ib1 <= la_input(15 downto 8); ib2 <= la_input(23 downto 16); ib3 <= la_input(31 downto 24); tmp <= -- select 8-bit enabled group x"000000" & ib0 when disabledGroups = "1110" else x"000000" & ib1 when disabledGroups = "1101" else x"000000" & ib2 when disabledGroups = "1011" else x"000000" & ib3 when disabledGroups = "0111" else -- select 2 8-bit enabled groups x"0000" & ib1 & ib0 when disabledGroups = "1100" else x"0000" & ib2 & ib0 when disabledGroups = "1010" else x"0000" & ib3 & ib0 when disabledGroups = "0110" else x"0000" & ib2 & ib1 when disabledGroups = "1001" else x"0000" & ib3 & ib1 when disabledGroups = "0101" else x"0000" & ib3 & ib2 when disabledGroups = "0011" else -- clear unused group ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else -- full la_input when disabledGroups = "0000" else (others => 'X'); process (clock) begin if rising_edge(clock) then output <= tmp; output_ready <= la_input_ready; end if; end process; end behavioral;