content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
-- MacAddrRAM - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- MacAddrRAM - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- MacAddrRAM - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- MacAddrRAM - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... |
-------------------------------------------------------------------------------
--
-- The testbench for t48_core.
--
-- $Id: tb-c.vhd,v 1.4 2006-06-21 01:04:05 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
use work.procedures.all;
entity tb_serial is
end tb_serial;
architecture behav of tb_serial is
signal rst : std_logic := '1';
signal clk :... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--single line
ENTITY SimpleComentedUnit2 IS
PORT(
a : IN STD_LOGIC;
b : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SimpleComentedUnit2 IS
BEGIN
b <= a;
END ARCHITECTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOR2Gate is
port(inPort0 : in std_logic;
inPort1 : in std_logic;
outPort : out std_logic);
end NOR2Gate;
architecture Structural of NOR2Gate is
signal s_orOut : std_logic;
begin
or_gate : entity work.OR2Gate(Behavioral)
port map(inPort0 => inPort0,
... |
--------------------------------------------------------------------------------
-- Author: Elahe Jalalpour (el.jalalpour@gmail.com)
--
-- Create Date: 27-08-2015
-- Module Name: ha.vhd
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
Library IEEE;
Use IEEE.std_logic_1164.All;
Use IEEE.std_logic_arith.All;
Use IEEE.std_logic_unsigned.All;
Use Work.RC5_pkg.All;
Entity rc5_Struct is
Port
(
clr : in std_logic;
clk : in std_logic;
enc : in std_logic;
key_vld : in std_logic;
key : in std_logic_vector (127 downto 0);
... |
Library IEEE;
Use IEEE.std_logic_1164.All;
Use IEEE.std_logic_arith.All;
Use IEEE.std_logic_unsigned.All;
Use Work.RC5_pkg.All;
Entity rc5_Struct is
Port
(
clr : in std_logic;
clk : in std_logic;
enc : in std_logic;
key_vld : in std_logic;
key : in std_logic_vector (127 downto 0);
... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.3 (lin64) Build 1034051 Fri Oct 3 16:31:15 MDT 2014
-- Date : Sun Nov 2 20:42:29 2014
-- Host : ubuntu-imac running 64-bit Ubuntu 14... |
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM_5.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ====================... |
library ieee;
use ieee.std_logic_1164.all;
entity sr_latch_testbench is end sr_latch_testbench;
architecture behavioral of sr_latch_testbench IS
component sr_latch
port (
s : in std_logic;
r : in std_logic;
q_n : inout std_logic;
q : inou... |
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
entity test_inst is
generic(
G_ROUND : natural := 0;
G_ROUND_ENABLE : boolean := false
);
port(
i_value : in bit_vector(7 downto 0);
o_ena : out bit;
o_value : out bit_vector(7 downto 0)
);
end test_inst;
architecture rtl of test_inst is
begin
o_ena <... |
entity test_inst is
generic(
G_ROUND : natural := 0;
G_ROUND_ENABLE : boolean := false
);
port(
i_value : in bit_vector(7 downto 0);
o_ena : out bit;
o_value : out bit_vector(7 downto 0)
);
end test_inst;
architecture rtl of test_inst is
begin
o_ena <... |
entity test_inst is
generic(
G_ROUND : natural := 0;
G_ROUND_ENABLE : boolean := false
);
port(
i_value : in bit_vector(7 downto 0);
o_ena : out bit;
o_value : out bit_vector(7 downto 0)
);
end test_inst;
architecture rtl of test_inst is
begin
o_ena <... |
entity test_inst is
generic(
G_ROUND : natural := 0;
G_ROUND_ENABLE : boolean := false
);
port(
i_value : in bit_vector(7 downto 0);
o_ena : out bit;
o_value : out bit_vector(7 downto 0)
);
end test_inst;
architecture rtl of test_inst is
begin
o_ena <... |
-------------------------------------------------------------------------------
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: dma.vhd
-- Module Name: dma.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEE... |
architecture rtl of fifo is
begin
process begin
report "hello" severity FAILURE;
report "hello" severity FAILURE;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity read_data_stage is
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
-- inputs
start_address : in std_logic_vector(31 downto 0);
ex_w_addr : in std_logic_vector(31 downto 0);
ex_w_data : in std_logic_vecto... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
entity Shifter is
port(shift_lsl :in std_logic;
shift_lsr :in std_logic;
shift_asr :in std_logic;
shift_ror :in std_logic;
shift_rrx :in std_logic;
cin :in std_logic;
shift_val :in std_logic_vecto... |
----------------------------------------------------------------------------------
-- Module Name: tb_transceiver_test - Behavioral
--
-- Description: A testbench for the transceiver_test
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github... |
library verilog;
use verilog.vl_types.all;
entity ama_preadder_function is
generic(
preadder_mode : string := "SIMPLE";
width_in_a : integer := 1;
width_in_b : integer := 1;
width_in_c : integer := 1;
width_in_coef : integer := 1;
width_result_a :... |
library verilog;
use verilog.vl_types.all;
entity ama_preadder_function is
generic(
preadder_mode : string := "SIMPLE";
width_in_a : integer := 1;
width_in_b : integer := 1;
width_in_c : integer := 1;
width_in_coef : integer := 1;
width_result_a :... |
library verilog;
use verilog.vl_types.all;
entity ama_preadder_function is
generic(
preadder_mode : string := "SIMPLE";
width_in_a : integer := 1;
width_in_b : integer := 1;
width_in_c : integer := 1;
width_in_coef : integer := 1;
width_result_a :... |
library verilog;
use verilog.vl_types.all;
entity ama_preadder_function is
generic(
preadder_mode : string := "SIMPLE";
width_in_a : integer := 1;
width_in_b : integer := 1;
width_in_c : integer := 1;
width_in_coef : integer := 1;
width_result_a :... |
library verilog;
use verilog.vl_types.all;
entity ama_preadder_function is
generic(
preadder_mode : string := "SIMPLE";
width_in_a : integer := 1;
width_in_b : integer := 1;
width_in_c : integer := 1;
width_in_coef : integer := 1;
width_result_a :... |
-------------------------------------------------------------------------------
-- Company : HSLU, Waj
-- Create Date: 20-Apr-12
-- Project : ECS, Uebung 2
-- Description: Combinational circuit (Enable gate) described in different
-- forms
-------------------------------------------------... |
-- file: dcm75MHz.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaime... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! Crossbar's Write Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsig... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity vga_buffer is
generic (
SIZE_POW2 : integer := 6
);
port (
clk_w : in std_logic;
clk_r : in std_logic;
wen : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in st... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity vga_buffer is
generic (
SIZE_POW2 : integer := 6
);
port (
clk_w : in std_logic;
clk_r : in std_logic;
wen : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in st... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity vga_buffer is
generic (
SIZE_POW2 : integer := 6
);
port (
clk_w : in std_logic;
clk_r : in std_logic;
wen : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in st... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity vga_buffer is
generic (
SIZE_POW2 : integer := 6
);
port (
clk_w : in std_logic;
clk_r : in std_logic;
wen : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in st... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity vga_buffer is
generic (
SIZE_POW2 : integer := 6
);
port (
clk_w : in std_logic;
clk_r : in std_logic;
wen : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in st... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity vga_buffer is
generic (
SIZE_POW2 : integer := 6
);
port (
clk_w : in std_logic;
clk_r : in std_logic;
wen : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in st... |
--Gatterschaltung zu Aufgabe 2.4
--Christian Rebischke 18.4.2014
-- x Eingänge, y Ausgang, z "zwischenstationen"
library IEEE;
use IEEE.std_logic_1164.all;
entity Gatterschaltung is
port(x: in STD_LOGIC_VECTOR(2 DOWNTO 0);
y: out STD_LOGIC);
end entity;
architecture test of Gatterschaltung is
signal z: ST... |
--Gatterschaltung zu Aufgabe 2.4
--Christian Rebischke 18.4.2014
-- x Eingänge, y Ausgang, z "zwischenstationen"
library IEEE;
use IEEE.std_logic_1164.all;
entity Gatterschaltung is
port(x: in STD_LOGIC_VECTOR(2 DOWNTO 0);
y: out STD_LOGIC);
end entity;
architecture test of Gatterschaltung is
signal z: ST... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:30 2017
-- Host : DarkCube running 64-bit major re... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 11:02:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this fi... |
-------------------------------------------------------------------------------
--
-- $Id: t48_tb_pack-p.vhd,v 1.2 2004-04-14 20:53:54 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
... |
--
-- vending machine FSM
--
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity vending_machine is
--generic declarations
port (
clk, rst: in std_logic;
nickel_in, dime_in, quarter_in: in boolean;... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mblite_simu is
end entity;
architecture test of mblite_simu is
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <ccl@xunit.de>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redis... |
library IEEE;
use IEEE.math_real.all;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.energy_systems.all;
entity driver_ideal is
generic (r_open : resistance := 1000.0;
r_closed : resistance := 5.0;
trans_time : real ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- #################################################################################################
-- # << NEO430 - Data memory ("DMEM") for Lattice ice40 UltraPlus >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: A generic buffer modul... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: A generic buffer modul... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 02:35:49 2019
-- Host : varun-laptop running 64-bit Serv... |
library IEEE;
use ieee.std_logic_1164.all;
entity program_counter is
port(
input : in std_logic_vector(31 downto 0);
clk, rst, pre, ce, control : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end program_counter;
architecture behav of program_counter is
begin
PC : entity work.thirty_two_bit_r... |
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
... |
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue is
port (sig_gt, sig_ge, sig_lt, sig_le : out boolean;
uns_gt, uns_ge, uns_lt, uns_le : out boolean);
end issue;
architecture beh of issue is
begin
-- all of those works
uns_gt <= (unsigned'("1111") > unsigned'("0... |
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--This VHDL code is part of the OZ-3, a 32-bit processor
--
--Module Title: RegFile
--Module Description:
-- The register file of the OZ-3. It holds 32 32-bit registers,
-- with register 0 hardwired to... |
----------------------------------------------------------------------------------------------
--
-- Generated by X-HDL Verilog Translator - Version 4.0.0 Apr. 30, 2006
-- Wed Jun 17 2009 01:00:41
--
-- Input file : /home/samsonn/SandBox_LBranch_11.2/env/Databases/ip/src2/L/mig_v3_2/data/dlib/virtex6/ddr3_sdr... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
-- rs232_usb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_uartlite_v1_02_a;
use xps_uartlite... |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Da... |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT spaceinvaders
PORT(
clk : IN std_logic;
reset : IN std_logic;
red : OUT std_logic_... |
-- This Source Code Form is subject to the terms of the Mozilla Public
-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
-- You can obtain one at http://mozilla.org/MPL/2.0/.
--
-- Copyright (c) 2015, Olof Kraigher olof.kraigher@gmail.com
use std.textio.all;
library vunit_lib;
context vunit... |
-------------------------------------------------------------------------------
-- system_xps_intc_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_intc_v2_01_a;
use xps_intc... |
----------------------------------------------------------------------------
---- Create Date: 00:12:45 10/23/2010
---- Design Name: pic
---- Project Name: PIC
---- Description:
---- A Programmable Interrupt Controller which can handle upto 8 ----
---- level triggered interrupts.The operating modes available are ... |
--
-- and_gate_test.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
entity and_gate_test is
end entity;
architecture sim of and_gate_test is
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic;
begin
uut : entity work.and_gate port map (
a => a,
b => b,
... |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemen... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
----------------------------------------------------------------------------
-- UART_TX_CTRL.vhd -- UART Data Transfer Component
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
-----------------------------------------... |
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either ver... |
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either ver... |
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either ver... |
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either ver... |
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either ver... |
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either ver... |
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either ver... |
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either ver... |
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either ver... |
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either ver... |
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