content stringlengths 1 1.04M ⌀ |
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity wifidar_fpga is
generic(
num_samples: integer range 0 to 20000 := 395;
sample_length_bits: integer range 0 to 32 := 14
);
port(
-- rot_a: in std_logic;
-- rot_b: in std_logic;
-- button_in: in std_logic_vector(3 downto 0);
switches: in std_logic_vector(3 downto 0);
change_amp: in std_logic;
SPI_SS_B: out std_logic;
AMP_CS: out std_logic;
AD_CONV: out std_logic;
SF_CE0: out std_logic;
FPGA_INIT_B: out std_logic;
AMP_SHDN: out std_logic;
SPI_MOSI: out std_logic;
SPI_MISO: in std_logic;
SPI_SCK: out std_logic;
-- DAC_SCK: out std_logic;
-- DAC_CS: out std_logic;
-- DAC_MOSI: out std_logic;
-- current_mode_out: out std_logic_vector(1 downto 0);
initial_sample: in std_logic;
uart_tx: out std_logic;
debug: out std_logic;
debug2: out std_logic;
rst: in std_logic;
clk: in std_logic
);
end wifidar_fpga;
architecture structural of wifidar_fpga is
component uart
generic(
clk_freq: integer := 50000000;
baud_rate: integer := 38400
);
port(
uart_tx: out std_logic;
data_in: in std_logic_vector(7 downto 0);
ready: out std_logic;
send_data: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component sample_buffer
generic(
num_samples: integer range 0 to 20000 := 20;
sample_length_bits: integer range 0 to 32 := 14
);
port(
sample_in: in std_logic_vector(sample_length_bits - 1 downto 0);
sample_out: out std_logic_vector(sample_length_bits - 1 downto 0);
sample_in_ready: in std_logic;
initial_sample: in std_logic;
sample_out_index: in std_logic_vector(integer(ceil(log(real(num_samples))/log(real(2)))) downto 0);
buffer_full: out std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component adc_controller
generic(
sample_div: integer := 2500
);
port(
spi_to_amp: out std_logic_vector(3 downto 0);
req_adc: out std_logic;
req_amp: out std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component uart_minibuf
generic(
num_samples: integer range 0 to 20000 := 20;
sample_length_bits: integer range 0 to 32 := 14
);
port(
data_in: in std_logic_vector (sample_length_bits -1 downto 0);
data_out: out std_logic_vector(7 downto 0);
index_data_in: out std_logic_vector(integer(ceil(log(real(num_samples))/log(real(2)))) downto 0);
sample_buffer_full: in std_logic;
uart_send_data: out std_logic;
uart_ready: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component spi_arbitrator
port(
----- other devices on SPI BUS ---
SPI_SS_B: out std_logic; -- set to 1
SF_CE0: out std_logic; -- set to 1
FPGA_INIT_B: out std_logic; -- set to 1
----- chip selects ---
AMP_CS: out std_logic; -- active low pre-amp chip select
--AD_CONV: out std_logic; -- active high ADC chip select
--DAC_CS: out std_logic; -- active low DAC chip select
----- resets ---
AMP_SHDN: out std_logic; -- ADC pre-amp shutdown signal (active high)
-- control signals
spi_controller_busy: in std_logic;
dac_ready: in std_logic;
adc_send_data: out std_logic;
amp_send_data: out std_logic;
dac_send_data: out std_logic;
req_adc: in std_logic;
req_amp: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component adc_receiver
port(
send_data: in std_logic;
busy: out std_logic;
spi_sck: out std_logic;
spi_miso: in std_logic;
ad_conv: out std_logic;
outputA: out std_logic_vector (13 downto 0);
outputB: out std_logic_vector (13 downto 0);
new_reading: out std_logic;
clk: in std_logic
);
end component;
component preamp_config
port(
preamp_done: out std_logic;
send_data: in std_logic;
busy: out std_logic;
gain_in: in std_logic_vector(3 downto 0);
spi_mosi: out std_logic;
spi_sck: out std_logic;
clk: in std_logic
);
end component;
component dac_serial
port(
SPI_SCK: out std_logic; -- spi clock
DAC_CS: out std_logic; -- chip select
SPI_MOSI_1: out std_logic; -- Master output, slave (DAC) input
--SPI_MISO: in std_logic; -- Master input, slave (DAC) output
--- control ---
data_in_1: in std_logic_vector(11 downto 0);
ready_flag: out std_logic; -- sending data flag
send_data: in std_logic; -- send sine data over SPI
clk: in std_logic -- master clock
);
end component;
signal uart_data: std_logic_vector(7 downto 0);
signal uart_send_data: std_logic;
signal uart_ready: std_logic;
signal adc_sample_data: std_logic_vector(13 downto 0);
signal sample_buffer_out: std_logic_vector(13 downto 0);
signal load_adc: std_logic;
signal sample_out_index: std_logic_vector(integer(ceil(log(real(num_samples))/log(real(2)))) downto 0);
signal sample_buffer_full: std_logic;
--signal spi_to_amp: std_logic_vector(3 downto 0);
signal req_adc: std_logic;
signal req_amp: std_logic;
signal spi_controller_busy: std_logic;
signal spi_mosi_sig2: std_logic;
signal spi_sck_sig2: std_logic;
signal spi_sck_sig3: std_logic;
signal adc_busy: std_logic;
signal adc_send: std_logic;
signal amp_send: std_logic;
signal amp_busy: std_logic;
signal req_amp_controller: std_logic;
begin
uarter: uart port map (uart_tx,uart_data,uart_ready,uart_send_data,rst,clk);
sample_buefferer: sample_buffer generic map (num_samples,sample_length_bits) port map (adc_sample_data,sample_buffer_out,load_adc,initial_sample,sample_out_index,sample_buffer_full,rst,clk);
adc_controllerer: adc_controller port map (open,req_adc,req_amp_controller,rst,clk);
uart_minibuffer: uart_minibuf generic map (num_samples,sample_length_bits) port map (sample_buffer_out,uart_data,sample_out_index,sample_buffer_full,uart_send_data,uart_ready,rst,clk);
spi_arbitratorer: spi_arbitrator port map (SPI_SS_B,SF_CE0,FPGA_INIT_B,AMP_CS,AMP_SHDN,
spi_controller_busy,'0',adc_send,amp_send,open,
req_adc,req_amp,rst,clk);
--dac_controller: dac_serial port map (DAC_SCK,DAC_CS,DAC_MOSI,ramp_data_sig,dac_ready,dac_send,clk);
adc_spi_control: adc_receiver port map (adc_send,adc_busy,spi_sck_sig2,SPI_MISO,AD_CONV,adc_sample_data,open,load_adc,clk);
amp_controller: preamp_config port map (open,amp_send,amp_busy,switches,spi_mosi_sig2,spi_sck_sig3,clk);
SPI_MOSI <= spi_mosi_sig2;
SPI_SCK <= spi_sck_sig2 or spi_sck_sig3;
req_amp <= req_amp_controller or change_amp;
spi_controller_busy <= adc_busy or amp_busy;
debug <= sample_buffer_full;
debug2 <= initial_sample;
end structural;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GN7UJNSI7B is
generic ( decode : string := "101";
pipeline : natural := 1;
width : natural := 3);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GN7UJNSI7B is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 3,
decode => "101",
pipeline => 1)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GN7UJNSI7B is
generic ( decode : string := "101";
pipeline : natural := 1;
width : natural := 3);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GN7UJNSI7B is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 3,
decode => "101",
pipeline => 1)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; |
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_jtag_debug_module_tck is
port(
MonDReg : in vl_logic_vector(31 downto 0);
break_readreg : in vl_logic_vector(31 downto 0);
dbrk_hit0_latch : in vl_logic;
dbrk_hit1_latch : in vl_logic;
dbrk_hit2_latch : in vl_logic;
dbrk_hit3_latch : in vl_logic;
debugack : in vl_logic;
ir_in : in vl_logic_vector(1 downto 0);
jtag_state_rti : in vl_logic;
monitor_error : in vl_logic;
monitor_ready : in vl_logic;
reset_n : in vl_logic;
resetlatch : in vl_logic;
tck : in vl_logic;
tdi : in vl_logic;
tracemem_on : in vl_logic;
tracemem_trcdata: in vl_logic_vector(35 downto 0);
tracemem_tw : in vl_logic;
trc_im_addr : in vl_logic_vector(6 downto 0);
trc_on : in vl_logic;
trc_wrap : in vl_logic;
trigbrktype : in vl_logic;
trigger_state_1 : in vl_logic;
vs_cdr : in vl_logic;
vs_sdr : in vl_logic;
vs_uir : in vl_logic;
ir_out : out vl_logic_vector(1 downto 0);
jrst_n : out vl_logic;
sr : out vl_logic_vector(37 downto 0);
st_ready_test_idle: out vl_logic;
tdo : out vl_logic
);
end finalproject_cpu_jtag_debug_module_tck;
|
--------------------------------------------------------------------------------
---- ----
---- This file is part of the yaVGA project ----
---- http://www.opencores.org/?do=project&who=yavga ----
---- ----
---- Description ----
---- Implementation of yaVGA IP core ----
---- ----
---- To Do: ----
---- ----
---- ----
---- Author(s): ----
---- Sandro Amato, sdroamt@netscape.net ----
---- ----
--------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2009, Sandro Amato ----
---- All rights reserved. ----
---- ----
---- Redistribution and use in source and binary forms, with or without ----
---- modification, are permitted provided that the following conditions ----
---- are met: ----
---- ----
---- * Redistributions of source code must retain the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer. ----
---- * Redistributions in binary form must reproduce the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer in the documentation and/or other ----
---- materials provided with the distribution. ----
---- * Neither the name of SANDRO AMATO nor the names of its ----
---- contributors may be used to endorse or promote products ----
---- derived from this software without specific prior written ----
---- permission. ----
---- ----
---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ----
---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ----
---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ----
---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ----
---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ----
---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ----
---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.yavga_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity s3e_starter_1600k is
port (i_clk : in std_logic;
o_hsync : out std_logic;
o_vsync : out std_logic;
o_r : out std_logic;
o_g : out std_logic;
o_b : out std_logic);
end s3e_starter_1600k;
architecture Behavioral of s3e_starter_1600k is
component vga_ctrl
port(
i_clk : in std_logic;
i_reset : in std_logic;
i_h_sync_en : in std_logic;
i_v_sync_en : in std_logic;
i_chr_addr : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
i_chr_data : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
i_chr_clk : in std_logic;
i_chr_en : in std_logic;
i_chr_we : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);
i_chr_rst : in std_logic;
i_wav_d : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
i_wav_clk : in std_logic;
i_wav_we : in std_logic;
i_wav_addr : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
o_h_sync : out std_logic;
o_v_sync : out std_logic;
o_r : out std_logic;
o_g : out std_logic;
o_b : out std_logic;
o_chr_data : out std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0)
);
end component;
signal s_hsync : std_logic;
signal s_vsync : std_logic;
signal s_r : std_logic;
signal s_g : std_logic;
signal s_b : std_logic;
signal s_vsync_count : std_logic_vector(7 downto 0) := (others => '0');
signal s_vsync1 : std_logic;
signal s_chr_addr : std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0); -- := (others => '0');
signal s_chr_data : std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0); -- := (others => '0');
signal s_rnd : std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0); -- := (others => '0');
signal s_chr_we : std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);
signal s_wav_addr : std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
signal s_wav_d : std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
signal s_mul : std_logic_vector(7 downto 0);
signal s_initialized : std_logic := '0';
attribute U_SET : string;
attribute U_SET of "u1_vga_ctrl" : label is "u1_vga_ctrl_uset";
begin
o_hsync <= s_hsync;
o_vsync <= s_vsync;
o_r <= s_r;
o_g <= s_g;
o_b <= s_b;
u1_vga_ctrl : vga_ctrl port map(
i_clk => i_clk,
i_reset => '0',
o_h_sync => s_hsync,
o_v_sync => s_vsync,
i_h_sync_en => '1',
i_v_sync_en => '1',
o_r => s_r,
o_g => s_g,
o_b => s_b,
i_chr_addr => s_chr_addr, --B"000_0000_0000",
i_chr_data => s_chr_data, --X"00000000",
o_chr_data => open,
i_chr_clk => i_clk,
i_chr_en => '1',
i_chr_we => s_chr_we,
i_chr_rst => '0',
i_wav_d => s_wav_d, --X"0000", --s_rnd(15 downto 0), --
i_wav_clk => i_clk,
i_wav_we => '0', --'0', -- '1',
i_wav_addr => s_wav_addr --B"00_0000_0000" --s_chr_addr(9 downto 0) --
);
s_wav_addr <= s_rnd(1 downto 0) & s_vsync_count;
s_mul <= s_vsync_count(3 downto 0) * s_vsync_count(3 downto 0);
s_wav_d <= B"000" & s_rnd(2 downto 0) & B"00" & s_mul;
--s_wav_d <= B"000" & "100" & B"00" & s_mul;
-- s_chr_data <= s_rnd;
-- p_write_chars : process(i_clk)
-- begin
-- if rising_edge(i_clk) then
-- -- during the sync time in order to avoid flickering
-- -- and each 128 vsync in order to stop for a while
-- -- will write random chars...
-- if s_vsync_count(7) = '1' and (s_hsync = '0' or s_vsync = '0') then
-- -- generate a pseudo random 32 bit number
-- s_rnd <= s_rnd(30 downto 0) & (s_rnd(31) xnor s_rnd(21) xnor s_rnd(1) xnor s_rnd(0));
-- -- increment the address and write enable...
-- s_chr_addr <= s_chr_addr + 1;
-- s_chr_we <= "1111";
-- else
-- s_chr_addr <= s_chr_addr;
-- s_chr_we <= "0000";
-- s_rnd <= s_rnd;
-- end if;
-- end if;
-- end process;
-- cols cols
-- 00_01_02_03 ... 96_97_98_99
-- row_00 "00000000000" ... "00000011000"
-- row_01 "00000100000" ... "00000111000"
-- ... ... ...
-- row_37 "10010100000" ... "10010111000"
p_write_chars : process(i_clk)
begin
if rising_edge(i_clk) then
if s_initialized = '0' then
case s_vsync_count(2 downto 0) is
when "000" => -- write ABCD
s_chr_we <= "1111";
s_chr_addr <= "00000000000";
s_chr_data <= "01000001" & "01000010" & "01000011" & "01000100";
when "001" => -- write EFGH
s_chr_we <= "1111";
s_chr_addr <= "00000011000";
s_chr_data <= "01000101" & "01000110" & "01000111" & "01001000";
when "010" => -- write IJKL
s_chr_we <= "1111";
s_chr_addr <= "00000100000";
s_chr_data <= "01001001" & "01001010" & "01001011" & "01001100";
when "011" => -- write MNOP
s_chr_we <= "1111";
s_chr_addr <= "10010100000";
s_chr_data <= "01001101" & "01001110" & "01001111" & "01010000";
when "100" => -- write QRST
s_chr_we <= "1111";
s_chr_addr <= "10010111000";
s_chr_data <= "01010001" & "01010010" & "01010011" & "01010100";
when "101" => -- write config grid and cursor color (overwrite RAM defaults)
s_chr_we <= "1111";
s_chr_addr <= c_CFG_BG_CUR_COLOR_ADDR(c_CFG_BG_CUR_COLOR_ADDR'left downto 2); -- c_CFG_BG_CUR_COLOR_ADDR >> 2
-- ND bgColor grid,cur ND curs_x curs_y
s_chr_data <= "00" & "000" & "101" & "000" & "00111000010" & "0101011110";
-- |--------108-------|-------109-------|----110-----|--111--|
s_initialized <= '1';
when others =>
s_chr_we <= (others => '0');
s_chr_addr <= (others => '1');
s_chr_data <= "10111110" & "10111101" & "10111100" & "10111011";
end case;
else
s_chr_we <= (others => '0');
end if;
end if;
end process;
-- p_rnd_bit : process(i_clk)
-- variable v_rnd_fb : std_logic;
-- variable v_rnd : std_logic_vector(31 downto 0);
-- begin
-- if rising_edge(i_clk) then
-- s_rnd_bit <= v_rnd_fb;
-- v_rnd_fb := v_rnd(31) xnor v_rnd(21) xnor v_rnd(1) xnor v_rnd(0);
-- v_rnd := v_rnd(30 downto 0) & v_rnd_fb;
-- end if;
-- end process;
p_vsync_count : process(i_clk)
begin
if rising_edge(i_clk) then
s_vsync1 <= s_vsync;
if (not s_vsync and s_vsync1) = '1' then -- pulse on vsync falling
s_vsync_count <= s_vsync_count + 1;
end if;
end if;
end process;
end Behavioral;
|
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16576)
`protect data_block
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1560.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01560ent IS
END c08s10b00x00p03n01i01560ent;
ARCHITECTURE c08s10b00x00p03n01i01560arch OF c08s10b00x00p03n01i01560ent IS
BEGIN
TESTING: PROCESS
variable s : integer := 0;
BEGIN
K : for j in 1 to 10 loop
L : for i in 1 to 10 loop
next K when ( (j = 3) and (i = 1) );
s := s + 1;
end loop L;
end loop K;
assert NOT(s = 90)
report "***PASSED TEST: c08s10b00x00p03n01i01560"
severity NOTE;
assert (s = 90)
report "***FAILED TEST: c08s10b00x00p03n01i01560 - A next statement with a loop label inside a labeled loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01560arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1560.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01560ent IS
END c08s10b00x00p03n01i01560ent;
ARCHITECTURE c08s10b00x00p03n01i01560arch OF c08s10b00x00p03n01i01560ent IS
BEGIN
TESTING: PROCESS
variable s : integer := 0;
BEGIN
K : for j in 1 to 10 loop
L : for i in 1 to 10 loop
next K when ( (j = 3) and (i = 1) );
s := s + 1;
end loop L;
end loop K;
assert NOT(s = 90)
report "***PASSED TEST: c08s10b00x00p03n01i01560"
severity NOTE;
assert (s = 90)
report "***FAILED TEST: c08s10b00x00p03n01i01560 - A next statement with a loop label inside a labeled loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01560arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1560.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01560ent IS
END c08s10b00x00p03n01i01560ent;
ARCHITECTURE c08s10b00x00p03n01i01560arch OF c08s10b00x00p03n01i01560ent IS
BEGIN
TESTING: PROCESS
variable s : integer := 0;
BEGIN
K : for j in 1 to 10 loop
L : for i in 1 to 10 loop
next K when ( (j = 3) and (i = 1) );
s := s + 1;
end loop L;
end loop K;
assert NOT(s = 90)
report "***PASSED TEST: c08s10b00x00p03n01i01560"
severity NOTE;
assert (s = 90)
report "***FAILED TEST: c08s10b00x00p03n01i01560 - A next statement with a loop label inside a labeled loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01560arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity oc_pusher is
port (
clock : in std_logic;
sig_in : in std_logic;
oc_out : out std_logic );
end entity;
architecture gideon of oc_pusher is
signal sig_d : std_logic;
signal drive : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
sig_d <= sig_in;
end if;
end process;
drive <= not sig_in or not sig_d;
oc_out <= sig_in when drive='1' else 'Z';
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
entity oc_pusher is
port (
clock : in std_logic;
sig_in : in std_logic;
oc_out : out std_logic );
end entity;
architecture gideon of oc_pusher is
signal sig_d : std_logic;
signal drive : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
sig_d <= sig_in;
end if;
end process;
drive <= not sig_in or not sig_d;
oc_out <= sig_in when drive='1' else 'Z';
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
entity oc_pusher is
port (
clock : in std_logic;
sig_in : in std_logic;
oc_out : out std_logic );
end entity;
architecture gideon of oc_pusher is
signal sig_d : std_logic;
signal drive : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
sig_d <= sig_in;
end if;
end process;
drive <= not sig_in or not sig_d;
oc_out <= sig_in when drive='1' else 'Z';
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
entity oc_pusher is
port (
clock : in std_logic;
sig_in : in std_logic;
oc_out : out std_logic );
end entity;
architecture gideon of oc_pusher is
signal sig_d : std_logic;
signal drive : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
sig_d <= sig_in;
end if;
end process;
drive <= not sig_in or not sig_d;
oc_out <= sig_in when drive='1' else 'Z';
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
entity oc_pusher is
port (
clock : in std_logic;
sig_in : in std_logic;
oc_out : out std_logic );
end entity;
architecture gideon of oc_pusher is
signal sig_d : std_logic;
signal drive : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
sig_d <= sig_in;
end if;
end process;
drive <= not sig_in or not sig_d;
oc_out <= sig_in when drive='1' else 'Z';
end gideon;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & af_chk_i & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (EMPTY = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Tue Apr 4 05:28:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../hier.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-e.vhd,v 1.1 2006/04/11 13:36:52 wig Exp $
-- $Date: 2006/04/11 13:36:52 $
-- $Log: inst_b_e-e.vhd,v $
-- Revision 1.1 2006/04/11 13:36:52 wig
-- Updated testcases: left constant/* and verilog/uamn open.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_b_e
--
entity inst_b_e is
-- Generics:
-- No Generated Generics for Entity inst_b_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_b_e
port_a : in std_logic; -- auto_a from a to b
port_b : in std_ulogic_vector(7 downto 0); -- auto_b from c to a and b
port_e : in std_ulogic_vector(23 downto 0) -- auto_e is O bus with internal in to other module
-- End of Generated Port for Entity inst_b_e
);
end inst_b_e;
--
-- End of Generated Entity inst_b_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- TC_Core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_core.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Dual Timer/Counter for PLB bus
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- --tc_core.vhd
-- --mux_onehot_f.vhd
-- --family_support.vhd
-- --timer_control.vhd
-- --count_module.vhd
-- --counter_f.vhd
-- --family_support.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_FAMILY -- Default family
-- C_AWIDTH -- PLB address bus width
-- C_DWIDTH -- PLB data bus width
-- C_COUNT_WIDTH -- Width in the bits of the counter
-- C_ONE_TIMER_ONLY -- Number of the Timer
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- PLB Clock
-- Rst -- PLB Reset
-- Bus2ip_addr -- bus to ip address bus
-- Bus2ip_be -- byte enables
-- Bus2ip_data -- bus to ip data bus
--
-- TC_DBus -- ip to bus data bus
-- bus2ip_rdce -- read select
-- bus2ip_wrce -- write select
-- ip2bus_rdack -- read acknowledge
-- ip2bus_wrack -- write acknowledge
-- TC_errAck -- error acknowledge
-------------------------------------------------------------------------------
-- Timer/Counter signals
-------------------------------------------------------------------------------
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- PWM0 -- Pulse Width Modulation Ouput 0
-- Interrupt -- Interrupt
-- Freeze -- Freeze count value
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_timer_v2_0_10;
use axi_timer_v2_0_10.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0_10.TC_Types.PWMA0_POS;
use axi_timer_v2_0_10.TC_Types.PWMB0_POS;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_3.ipif_pkg.INTEGER_ARRAY_TYPE;
library unisim;
use unisim.vcomponents.FDRS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity tc_core is
generic (
C_FAMILY : string := "virtex5";
C_COUNT_WIDTH : integer := 32;
C_ONE_TIMER_ONLY : integer := 0;
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 5;
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Rst : in std_logic;
-- PLB signals
Bus2ip_addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2ip_be : in std_logic_vector(0 to 3);
Bus2ip_data : in std_logic_vector(0 to 31);
TC_DBus : out std_logic_vector(0 to 31);
bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
TC_errAck : out std_logic;
-- PTC signals
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
PWM0 : out std_logic;
Interrupt : out std_logic;
Freeze : in std_logic
);
end entity tc_core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of tc_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
--Attribute declaration
attribute syn_keep : boolean;
--Signal declaration
signal load_Counter_Reg : std_logic_vector(0 to 1);
signal load_Load_Reg : std_logic_vector(0 to 1);
signal write_Load_Reg : std_logic_vector(0 to 1);
signal captGen_Mux_Sel : std_logic_vector(0 to 1);
signal loadReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH*2-1);
signal counterReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH*2-1);
signal tCSR0_Reg : QUADLET_TYPE;
signal tCSR1_Reg : QUADLET_TYPE;
signal counter_TC : std_logic_vector(0 to 1);
signal counter_En : std_logic_vector(0 to 1);
signal count_Down : std_logic_vector(0 to 1);
attribute syn_keep of count_Down : signal is true;
signal iPWM0 : std_logic;
signal iGenerateOut0 : std_logic;
signal iGenerateOut1 : std_logic;
signal pwm_Reset : std_logic;
signal Read_Reg_In : QUADLET_TYPE;
signal read_Mux_In : std_logic_vector(0 to 6*32-1);
signal read_Mux_S : std_logic_vector(0 to 5);
begin -- architecture imp
-----------------------------------------------------------------------------
-- Generating the acknowledgement/error signals
-----------------------------------------------------------------------------
ip2bus_rdack <= (Bus2ip_rdce(0) or Bus2ip_rdce(1) or Bus2ip_rdce(2) or
Bus2ip_rdce(4) or Bus2ip_rdce(5) or
Bus2ip_rdce(6) or Bus2ip_rdce(7));
ip2bus_wrack <= (Bus2ip_wrce(0) or Bus2ip_wrce(1) or Bus2ip_wrce(2) or
Bus2ip_wrce(4) or Bus2ip_wrce(5) or
Bus2ip_wrce(6) or Bus2ip_wrce(7));
--TCR0 AND TCR1 is read only register, hence writing to these register
--will not generate error ack.
--Modify TC_errAck <= (Bus2ip_wrce(2)or Bus2ip_wrce(6)) on 11/11/08 to;
TC_errAck <= '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--Process :READ_MUX_INPUT
-----------------------------------------------------------------------------
READ_MUX_INPUT: process (TCSR0_Reg,TCSR1_Reg,LoadReg_DBus,CounterReg_DBus) is
begin
read_Mux_In(0 to 19) <= (others => '0');
read_Mux_In(20 to 31) <= TCSR0_Reg(20 to 31);
read_Mux_In(32 to 52) <= (others => '0');
read_Mux_In(53 to 63) <= TCSR1_Reg(21 to 31);
if C_COUNT_WIDTH < C_DWIDTH then
for i in 1 to C_DWIDTH-C_COUNT_WIDTH loop
read_Mux_In(63 +i) <= '0';
read_Mux_In(95 +i) <= '0';
read_Mux_In(127+i) <= '0';
read_Mux_In(159+i) <= '0';
end loop;
end if;
read_Mux_In(64 +C_DWIDTH-C_COUNT_WIDTH to 95) <=
LoadReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1);
read_Mux_In(96 +C_DWIDTH-C_COUNT_WIDTH to 127) <=
LoadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1);
read_Mux_In(128+C_DWIDTH-C_COUNT_WIDTH to 159) <=
CounterReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1);
read_Mux_In(160+C_DWIDTH-C_COUNT_WIDTH to 191) <=
CounterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1);
end process READ_MUX_INPUT;
---------------------------------------------------------
-- Create read mux select input
-- Bus2ip_rdce(0) -->TCSR0 REG READ ENABLE
-- Bus2ip_rdce(4) -->TCSR1 REG READ ENABLE
-- Bus2ip_rdce(1) -->TLR0 REG READ ENABLE
-- Bus2ip_rdce(5) -->TLR1 REG READ ENABLE
-- Bus2ip_rdce(2) -->TCR0 REG READ ENABLE
-- Bus2ip_rdce(6) -->TCR1 REG READ ENABLE
---------------------------------------------------------
read_Mux_S <= Bus2ip_rdce(0) & Bus2ip_rdce(4)& Bus2ip_rdce(1)
& Bus2ip_rdce(5) & Bus2ip_rdce(2) & Bus2ip_rdce(6);
-- mux_onehot_f
READ_MUX_I: entity axi_timer_v2_0_10.mux_onehot_f
generic map(
C_DW => 32,
C_NB => 6,
C_FAMILY => C_FAMILY)
port map(
D => read_Mux_In, --[in]
S => read_Mux_S, --[in]
Y => Read_Reg_In --[out]
);
--slave to bus data bus assignment
TC_DBus <= Read_Reg_In ;
------------------------------------------------------------------
------------------------------------------------------------------
-- COUNTER MODULE
------------------------------------------------------------------
COUNTER_0_I: entity axi_timer_v2_0_10.count_module
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH)
port map (
Clk => Clk, --[in]
Reset => Rst, --[in]
Load_DBus => Bus2ip_data(C_DWIDTH-C_COUNT_WIDTH to C_DWIDTH-1), --[in]
Load_Counter_Reg => load_Counter_Reg(0), --[in]
Load_Load_Reg => load_Load_Reg(0), --[in]
Write_Load_Reg => write_Load_Reg(0), --[in]
CaptGen_Mux_Sel => captGen_Mux_Sel(0), --[in]
Counter_En => counter_En(0), --[in]
Count_Down => count_Down(0), --[in]
BE => Bus2ip_be, --[in]
LoadReg_DBus => loadReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1), --[out]
CounterReg_DBus => counterReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1), --[out]
Counter_TC => counter_TC(0) --[out]
);
----------------------------------------------------------------------
--GEN_SECOND_TIMER:SECOND COUNTER MODULE IS ADDED TO DESIGN
--WHEN C_ONE_TIMER_ONLY /= 1
----------------------------------------------------------------------
GEN_SECOND_TIMER: if C_ONE_TIMER_ONLY /= 1 generate
COUNTER_1_I: entity axi_timer_v2_0_10.count_module
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH)
port map (
Clk => Clk, --[in]
Reset => Rst, --[in]
Load_DBus => Bus2ip_data(C_DWIDTH-C_COUNT_WIDTH to C_DWIDTH-1), --[in]
Load_Counter_Reg => load_Counter_Reg(1), --[in]
Load_Load_Reg => load_Load_Reg(1), --[in]
Write_Load_Reg => write_Load_Reg(1), --[in]
CaptGen_Mux_Sel => captGen_Mux_Sel(1), --[in]
Counter_En => counter_En(1), --[in]
Count_Down => count_Down(1), --[in]
BE => Bus2ip_be, --[in]
LoadReg_DBus => loadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1), --[out]
CounterReg_DBus => counterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1), --[out]
Counter_TC => counter_TC(1) --[out]
);
end generate GEN_SECOND_TIMER;
----------------------------------------------------------------------
--GEN_NO_SECOND_TIMER: GENERATE WHEN C_ONE_TIMER_ONLY = 1
----------------------------------------------------------------------
GEN_NO_SECOND_TIMER: if C_ONE_TIMER_ONLY = 1 generate
loadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1) <= (others => '0');
counterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1) <= (others => '0');
counter_TC(1) <= '0';
end generate GEN_NO_SECOND_TIMER;
----------------------------------------------------------------------
--TIMER_CONTROL_I: TIMER_CONTROL MODULE
----------------------------------------------------------------------
TIMER_CONTROL_I: entity axi_timer_v2_0_10.timer_control
generic map (
C_TRIG0_ASSERT => C_TRIG0_ASSERT,
C_TRIG1_ASSERT => C_TRIG1_ASSERT,
C_GEN0_ASSERT => C_GEN0_ASSERT,
C_GEN1_ASSERT => C_GEN1_ASSERT,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map (
Clk => Clk, -- [in]
Reset => Rst, -- [in]
CaptureTrig0 => CaptureTrig0, -- [in]
CaptureTrig1 => CaptureTrig1, -- [in]
GenerateOut0 => iGenerateOut0, -- [out]
GenerateOut1 => iGenerateOut1, -- [out]
Interrupt => Interrupt, -- [out]
Counter_TC => counter_TC, -- [in]
Bus2ip_data => Bus2ip_data, -- [in]
BE => Bus2ip_be, -- [in]
Load_Counter_Reg => load_Counter_Reg, -- [out]
Load_Load_Reg => load_Load_Reg, -- [out]
Write_Load_Reg => write_Load_Reg, -- [out]
CaptGen_Mux_Sel => captGen_Mux_Sel, -- [out]
Counter_En => counter_En, -- [out]
Count_Down => count_Down, -- [out]
Bus2ip_rdce => Bus2ip_rdce, -- [in]
Bus2ip_wrce => Bus2ip_wrce, -- [in]
Freeze => Freeze, -- [in]
TCSR0_Reg => tCSR0_Reg(20 to 31), -- [out]
TCSR1_Reg => tCSR1_Reg(21 to 31) -- [out]
);
tCSR0_Reg (0 to 19) <= (others => '0');
tCSR1_Reg (0 to 20) <= (others => '0');
pwm_Reset <= iGenerateOut1 or
(not tCSR0_Reg(PWMA0_POS) and not tCSR1_Reg(PWMB0_POS));
PWM_FF_I: component FDRS
port map (
Q => iPWM0, -- [out]
C => Clk, -- [in]
D => iPWM0, -- [in]
R => pwm_Reset, -- [in]
S => iGenerateOut0 -- [in]
);
PWM0 <= iPWM0;
GenerateOut0 <= iGenerateOut0;
GenerateOut1 <= iGenerateOut1;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- TC_Core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_core.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Dual Timer/Counter for PLB bus
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- --tc_core.vhd
-- --mux_onehot_f.vhd
-- --family_support.vhd
-- --timer_control.vhd
-- --count_module.vhd
-- --counter_f.vhd
-- --family_support.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_FAMILY -- Default family
-- C_AWIDTH -- PLB address bus width
-- C_DWIDTH -- PLB data bus width
-- C_COUNT_WIDTH -- Width in the bits of the counter
-- C_ONE_TIMER_ONLY -- Number of the Timer
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- PLB Clock
-- Rst -- PLB Reset
-- Bus2ip_addr -- bus to ip address bus
-- Bus2ip_be -- byte enables
-- Bus2ip_data -- bus to ip data bus
--
-- TC_DBus -- ip to bus data bus
-- bus2ip_rdce -- read select
-- bus2ip_wrce -- write select
-- ip2bus_rdack -- read acknowledge
-- ip2bus_wrack -- write acknowledge
-- TC_errAck -- error acknowledge
-------------------------------------------------------------------------------
-- Timer/Counter signals
-------------------------------------------------------------------------------
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- PWM0 -- Pulse Width Modulation Ouput 0
-- Interrupt -- Interrupt
-- Freeze -- Freeze count value
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_timer_v2_0_10;
use axi_timer_v2_0_10.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0_10.TC_Types.PWMA0_POS;
use axi_timer_v2_0_10.TC_Types.PWMB0_POS;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_3.ipif_pkg.INTEGER_ARRAY_TYPE;
library unisim;
use unisim.vcomponents.FDRS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity tc_core is
generic (
C_FAMILY : string := "virtex5";
C_COUNT_WIDTH : integer := 32;
C_ONE_TIMER_ONLY : integer := 0;
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 5;
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Rst : in std_logic;
-- PLB signals
Bus2ip_addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2ip_be : in std_logic_vector(0 to 3);
Bus2ip_data : in std_logic_vector(0 to 31);
TC_DBus : out std_logic_vector(0 to 31);
bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
TC_errAck : out std_logic;
-- PTC signals
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
PWM0 : out std_logic;
Interrupt : out std_logic;
Freeze : in std_logic
);
end entity tc_core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of tc_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
--Attribute declaration
attribute syn_keep : boolean;
--Signal declaration
signal load_Counter_Reg : std_logic_vector(0 to 1);
signal load_Load_Reg : std_logic_vector(0 to 1);
signal write_Load_Reg : std_logic_vector(0 to 1);
signal captGen_Mux_Sel : std_logic_vector(0 to 1);
signal loadReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH*2-1);
signal counterReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH*2-1);
signal tCSR0_Reg : QUADLET_TYPE;
signal tCSR1_Reg : QUADLET_TYPE;
signal counter_TC : std_logic_vector(0 to 1);
signal counter_En : std_logic_vector(0 to 1);
signal count_Down : std_logic_vector(0 to 1);
attribute syn_keep of count_Down : signal is true;
signal iPWM0 : std_logic;
signal iGenerateOut0 : std_logic;
signal iGenerateOut1 : std_logic;
signal pwm_Reset : std_logic;
signal Read_Reg_In : QUADLET_TYPE;
signal read_Mux_In : std_logic_vector(0 to 6*32-1);
signal read_Mux_S : std_logic_vector(0 to 5);
begin -- architecture imp
-----------------------------------------------------------------------------
-- Generating the acknowledgement/error signals
-----------------------------------------------------------------------------
ip2bus_rdack <= (Bus2ip_rdce(0) or Bus2ip_rdce(1) or Bus2ip_rdce(2) or
Bus2ip_rdce(4) or Bus2ip_rdce(5) or
Bus2ip_rdce(6) or Bus2ip_rdce(7));
ip2bus_wrack <= (Bus2ip_wrce(0) or Bus2ip_wrce(1) or Bus2ip_wrce(2) or
Bus2ip_wrce(4) or Bus2ip_wrce(5) or
Bus2ip_wrce(6) or Bus2ip_wrce(7));
--TCR0 AND TCR1 is read only register, hence writing to these register
--will not generate error ack.
--Modify TC_errAck <= (Bus2ip_wrce(2)or Bus2ip_wrce(6)) on 11/11/08 to;
TC_errAck <= '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--Process :READ_MUX_INPUT
-----------------------------------------------------------------------------
READ_MUX_INPUT: process (TCSR0_Reg,TCSR1_Reg,LoadReg_DBus,CounterReg_DBus) is
begin
read_Mux_In(0 to 19) <= (others => '0');
read_Mux_In(20 to 31) <= TCSR0_Reg(20 to 31);
read_Mux_In(32 to 52) <= (others => '0');
read_Mux_In(53 to 63) <= TCSR1_Reg(21 to 31);
if C_COUNT_WIDTH < C_DWIDTH then
for i in 1 to C_DWIDTH-C_COUNT_WIDTH loop
read_Mux_In(63 +i) <= '0';
read_Mux_In(95 +i) <= '0';
read_Mux_In(127+i) <= '0';
read_Mux_In(159+i) <= '0';
end loop;
end if;
read_Mux_In(64 +C_DWIDTH-C_COUNT_WIDTH to 95) <=
LoadReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1);
read_Mux_In(96 +C_DWIDTH-C_COUNT_WIDTH to 127) <=
LoadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1);
read_Mux_In(128+C_DWIDTH-C_COUNT_WIDTH to 159) <=
CounterReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1);
read_Mux_In(160+C_DWIDTH-C_COUNT_WIDTH to 191) <=
CounterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1);
end process READ_MUX_INPUT;
---------------------------------------------------------
-- Create read mux select input
-- Bus2ip_rdce(0) -->TCSR0 REG READ ENABLE
-- Bus2ip_rdce(4) -->TCSR1 REG READ ENABLE
-- Bus2ip_rdce(1) -->TLR0 REG READ ENABLE
-- Bus2ip_rdce(5) -->TLR1 REG READ ENABLE
-- Bus2ip_rdce(2) -->TCR0 REG READ ENABLE
-- Bus2ip_rdce(6) -->TCR1 REG READ ENABLE
---------------------------------------------------------
read_Mux_S <= Bus2ip_rdce(0) & Bus2ip_rdce(4)& Bus2ip_rdce(1)
& Bus2ip_rdce(5) & Bus2ip_rdce(2) & Bus2ip_rdce(6);
-- mux_onehot_f
READ_MUX_I: entity axi_timer_v2_0_10.mux_onehot_f
generic map(
C_DW => 32,
C_NB => 6,
C_FAMILY => C_FAMILY)
port map(
D => read_Mux_In, --[in]
S => read_Mux_S, --[in]
Y => Read_Reg_In --[out]
);
--slave to bus data bus assignment
TC_DBus <= Read_Reg_In ;
------------------------------------------------------------------
------------------------------------------------------------------
-- COUNTER MODULE
------------------------------------------------------------------
COUNTER_0_I: entity axi_timer_v2_0_10.count_module
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH)
port map (
Clk => Clk, --[in]
Reset => Rst, --[in]
Load_DBus => Bus2ip_data(C_DWIDTH-C_COUNT_WIDTH to C_DWIDTH-1), --[in]
Load_Counter_Reg => load_Counter_Reg(0), --[in]
Load_Load_Reg => load_Load_Reg(0), --[in]
Write_Load_Reg => write_Load_Reg(0), --[in]
CaptGen_Mux_Sel => captGen_Mux_Sel(0), --[in]
Counter_En => counter_En(0), --[in]
Count_Down => count_Down(0), --[in]
BE => Bus2ip_be, --[in]
LoadReg_DBus => loadReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1), --[out]
CounterReg_DBus => counterReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1), --[out]
Counter_TC => counter_TC(0) --[out]
);
----------------------------------------------------------------------
--GEN_SECOND_TIMER:SECOND COUNTER MODULE IS ADDED TO DESIGN
--WHEN C_ONE_TIMER_ONLY /= 1
----------------------------------------------------------------------
GEN_SECOND_TIMER: if C_ONE_TIMER_ONLY /= 1 generate
COUNTER_1_I: entity axi_timer_v2_0_10.count_module
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH)
port map (
Clk => Clk, --[in]
Reset => Rst, --[in]
Load_DBus => Bus2ip_data(C_DWIDTH-C_COUNT_WIDTH to C_DWIDTH-1), --[in]
Load_Counter_Reg => load_Counter_Reg(1), --[in]
Load_Load_Reg => load_Load_Reg(1), --[in]
Write_Load_Reg => write_Load_Reg(1), --[in]
CaptGen_Mux_Sel => captGen_Mux_Sel(1), --[in]
Counter_En => counter_En(1), --[in]
Count_Down => count_Down(1), --[in]
BE => Bus2ip_be, --[in]
LoadReg_DBus => loadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1), --[out]
CounterReg_DBus => counterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1), --[out]
Counter_TC => counter_TC(1) --[out]
);
end generate GEN_SECOND_TIMER;
----------------------------------------------------------------------
--GEN_NO_SECOND_TIMER: GENERATE WHEN C_ONE_TIMER_ONLY = 1
----------------------------------------------------------------------
GEN_NO_SECOND_TIMER: if C_ONE_TIMER_ONLY = 1 generate
loadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1) <= (others => '0');
counterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1) <= (others => '0');
counter_TC(1) <= '0';
end generate GEN_NO_SECOND_TIMER;
----------------------------------------------------------------------
--TIMER_CONTROL_I: TIMER_CONTROL MODULE
----------------------------------------------------------------------
TIMER_CONTROL_I: entity axi_timer_v2_0_10.timer_control
generic map (
C_TRIG0_ASSERT => C_TRIG0_ASSERT,
C_TRIG1_ASSERT => C_TRIG1_ASSERT,
C_GEN0_ASSERT => C_GEN0_ASSERT,
C_GEN1_ASSERT => C_GEN1_ASSERT,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map (
Clk => Clk, -- [in]
Reset => Rst, -- [in]
CaptureTrig0 => CaptureTrig0, -- [in]
CaptureTrig1 => CaptureTrig1, -- [in]
GenerateOut0 => iGenerateOut0, -- [out]
GenerateOut1 => iGenerateOut1, -- [out]
Interrupt => Interrupt, -- [out]
Counter_TC => counter_TC, -- [in]
Bus2ip_data => Bus2ip_data, -- [in]
BE => Bus2ip_be, -- [in]
Load_Counter_Reg => load_Counter_Reg, -- [out]
Load_Load_Reg => load_Load_Reg, -- [out]
Write_Load_Reg => write_Load_Reg, -- [out]
CaptGen_Mux_Sel => captGen_Mux_Sel, -- [out]
Counter_En => counter_En, -- [out]
Count_Down => count_Down, -- [out]
Bus2ip_rdce => Bus2ip_rdce, -- [in]
Bus2ip_wrce => Bus2ip_wrce, -- [in]
Freeze => Freeze, -- [in]
TCSR0_Reg => tCSR0_Reg(20 to 31), -- [out]
TCSR1_Reg => tCSR1_Reg(21 to 31) -- [out]
);
tCSR0_Reg (0 to 19) <= (others => '0');
tCSR1_Reg (0 to 20) <= (others => '0');
pwm_Reset <= iGenerateOut1 or
(not tCSR0_Reg(PWMA0_POS) and not tCSR1_Reg(PWMB0_POS));
PWM_FF_I: component FDRS
port map (
Q => iPWM0, -- [out]
C => Clk, -- [in]
D => iPWM0, -- [in]
R => pwm_Reset, -- [in]
S => iGenerateOut0 -- [in]
);
PWM0 <= iPWM0;
GenerateOut0 <= iGenerateOut0;
GenerateOut1 <= iGenerateOut1;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- TC_Core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_core.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Dual Timer/Counter for PLB bus
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- --tc_core.vhd
-- --mux_onehot_f.vhd
-- --family_support.vhd
-- --timer_control.vhd
-- --count_module.vhd
-- --counter_f.vhd
-- --family_support.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_FAMILY -- Default family
-- C_AWIDTH -- PLB address bus width
-- C_DWIDTH -- PLB data bus width
-- C_COUNT_WIDTH -- Width in the bits of the counter
-- C_ONE_TIMER_ONLY -- Number of the Timer
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- PLB Clock
-- Rst -- PLB Reset
-- Bus2ip_addr -- bus to ip address bus
-- Bus2ip_be -- byte enables
-- Bus2ip_data -- bus to ip data bus
--
-- TC_DBus -- ip to bus data bus
-- bus2ip_rdce -- read select
-- bus2ip_wrce -- write select
-- ip2bus_rdack -- read acknowledge
-- ip2bus_wrack -- write acknowledge
-- TC_errAck -- error acknowledge
-------------------------------------------------------------------------------
-- Timer/Counter signals
-------------------------------------------------------------------------------
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- PWM0 -- Pulse Width Modulation Ouput 0
-- Interrupt -- Interrupt
-- Freeze -- Freeze count value
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_timer_v2_0_10;
use axi_timer_v2_0_10.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0_10.TC_Types.PWMA0_POS;
use axi_timer_v2_0_10.TC_Types.PWMB0_POS;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_3.ipif_pkg.INTEGER_ARRAY_TYPE;
library unisim;
use unisim.vcomponents.FDRS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity tc_core is
generic (
C_FAMILY : string := "virtex5";
C_COUNT_WIDTH : integer := 32;
C_ONE_TIMER_ONLY : integer := 0;
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 5;
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Rst : in std_logic;
-- PLB signals
Bus2ip_addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2ip_be : in std_logic_vector(0 to 3);
Bus2ip_data : in std_logic_vector(0 to 31);
TC_DBus : out std_logic_vector(0 to 31);
bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
TC_errAck : out std_logic;
-- PTC signals
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
PWM0 : out std_logic;
Interrupt : out std_logic;
Freeze : in std_logic
);
end entity tc_core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of tc_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
--Attribute declaration
attribute syn_keep : boolean;
--Signal declaration
signal load_Counter_Reg : std_logic_vector(0 to 1);
signal load_Load_Reg : std_logic_vector(0 to 1);
signal write_Load_Reg : std_logic_vector(0 to 1);
signal captGen_Mux_Sel : std_logic_vector(0 to 1);
signal loadReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH*2-1);
signal counterReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH*2-1);
signal tCSR0_Reg : QUADLET_TYPE;
signal tCSR1_Reg : QUADLET_TYPE;
signal counter_TC : std_logic_vector(0 to 1);
signal counter_En : std_logic_vector(0 to 1);
signal count_Down : std_logic_vector(0 to 1);
attribute syn_keep of count_Down : signal is true;
signal iPWM0 : std_logic;
signal iGenerateOut0 : std_logic;
signal iGenerateOut1 : std_logic;
signal pwm_Reset : std_logic;
signal Read_Reg_In : QUADLET_TYPE;
signal read_Mux_In : std_logic_vector(0 to 6*32-1);
signal read_Mux_S : std_logic_vector(0 to 5);
begin -- architecture imp
-----------------------------------------------------------------------------
-- Generating the acknowledgement/error signals
-----------------------------------------------------------------------------
ip2bus_rdack <= (Bus2ip_rdce(0) or Bus2ip_rdce(1) or Bus2ip_rdce(2) or
Bus2ip_rdce(4) or Bus2ip_rdce(5) or
Bus2ip_rdce(6) or Bus2ip_rdce(7));
ip2bus_wrack <= (Bus2ip_wrce(0) or Bus2ip_wrce(1) or Bus2ip_wrce(2) or
Bus2ip_wrce(4) or Bus2ip_wrce(5) or
Bus2ip_wrce(6) or Bus2ip_wrce(7));
--TCR0 AND TCR1 is read only register, hence writing to these register
--will not generate error ack.
--Modify TC_errAck <= (Bus2ip_wrce(2)or Bus2ip_wrce(6)) on 11/11/08 to;
TC_errAck <= '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--Process :READ_MUX_INPUT
-----------------------------------------------------------------------------
READ_MUX_INPUT: process (TCSR0_Reg,TCSR1_Reg,LoadReg_DBus,CounterReg_DBus) is
begin
read_Mux_In(0 to 19) <= (others => '0');
read_Mux_In(20 to 31) <= TCSR0_Reg(20 to 31);
read_Mux_In(32 to 52) <= (others => '0');
read_Mux_In(53 to 63) <= TCSR1_Reg(21 to 31);
if C_COUNT_WIDTH < C_DWIDTH then
for i in 1 to C_DWIDTH-C_COUNT_WIDTH loop
read_Mux_In(63 +i) <= '0';
read_Mux_In(95 +i) <= '0';
read_Mux_In(127+i) <= '0';
read_Mux_In(159+i) <= '0';
end loop;
end if;
read_Mux_In(64 +C_DWIDTH-C_COUNT_WIDTH to 95) <=
LoadReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1);
read_Mux_In(96 +C_DWIDTH-C_COUNT_WIDTH to 127) <=
LoadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1);
read_Mux_In(128+C_DWIDTH-C_COUNT_WIDTH to 159) <=
CounterReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1);
read_Mux_In(160+C_DWIDTH-C_COUNT_WIDTH to 191) <=
CounterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1);
end process READ_MUX_INPUT;
---------------------------------------------------------
-- Create read mux select input
-- Bus2ip_rdce(0) -->TCSR0 REG READ ENABLE
-- Bus2ip_rdce(4) -->TCSR1 REG READ ENABLE
-- Bus2ip_rdce(1) -->TLR0 REG READ ENABLE
-- Bus2ip_rdce(5) -->TLR1 REG READ ENABLE
-- Bus2ip_rdce(2) -->TCR0 REG READ ENABLE
-- Bus2ip_rdce(6) -->TCR1 REG READ ENABLE
---------------------------------------------------------
read_Mux_S <= Bus2ip_rdce(0) & Bus2ip_rdce(4)& Bus2ip_rdce(1)
& Bus2ip_rdce(5) & Bus2ip_rdce(2) & Bus2ip_rdce(6);
-- mux_onehot_f
READ_MUX_I: entity axi_timer_v2_0_10.mux_onehot_f
generic map(
C_DW => 32,
C_NB => 6,
C_FAMILY => C_FAMILY)
port map(
D => read_Mux_In, --[in]
S => read_Mux_S, --[in]
Y => Read_Reg_In --[out]
);
--slave to bus data bus assignment
TC_DBus <= Read_Reg_In ;
------------------------------------------------------------------
------------------------------------------------------------------
-- COUNTER MODULE
------------------------------------------------------------------
COUNTER_0_I: entity axi_timer_v2_0_10.count_module
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH)
port map (
Clk => Clk, --[in]
Reset => Rst, --[in]
Load_DBus => Bus2ip_data(C_DWIDTH-C_COUNT_WIDTH to C_DWIDTH-1), --[in]
Load_Counter_Reg => load_Counter_Reg(0), --[in]
Load_Load_Reg => load_Load_Reg(0), --[in]
Write_Load_Reg => write_Load_Reg(0), --[in]
CaptGen_Mux_Sel => captGen_Mux_Sel(0), --[in]
Counter_En => counter_En(0), --[in]
Count_Down => count_Down(0), --[in]
BE => Bus2ip_be, --[in]
LoadReg_DBus => loadReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1), --[out]
CounterReg_DBus => counterReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1), --[out]
Counter_TC => counter_TC(0) --[out]
);
----------------------------------------------------------------------
--GEN_SECOND_TIMER:SECOND COUNTER MODULE IS ADDED TO DESIGN
--WHEN C_ONE_TIMER_ONLY /= 1
----------------------------------------------------------------------
GEN_SECOND_TIMER: if C_ONE_TIMER_ONLY /= 1 generate
COUNTER_1_I: entity axi_timer_v2_0_10.count_module
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH)
port map (
Clk => Clk, --[in]
Reset => Rst, --[in]
Load_DBus => Bus2ip_data(C_DWIDTH-C_COUNT_WIDTH to C_DWIDTH-1), --[in]
Load_Counter_Reg => load_Counter_Reg(1), --[in]
Load_Load_Reg => load_Load_Reg(1), --[in]
Write_Load_Reg => write_Load_Reg(1), --[in]
CaptGen_Mux_Sel => captGen_Mux_Sel(1), --[in]
Counter_En => counter_En(1), --[in]
Count_Down => count_Down(1), --[in]
BE => Bus2ip_be, --[in]
LoadReg_DBus => loadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1), --[out]
CounterReg_DBus => counterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1), --[out]
Counter_TC => counter_TC(1) --[out]
);
end generate GEN_SECOND_TIMER;
----------------------------------------------------------------------
--GEN_NO_SECOND_TIMER: GENERATE WHEN C_ONE_TIMER_ONLY = 1
----------------------------------------------------------------------
GEN_NO_SECOND_TIMER: if C_ONE_TIMER_ONLY = 1 generate
loadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1) <= (others => '0');
counterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1) <= (others => '0');
counter_TC(1) <= '0';
end generate GEN_NO_SECOND_TIMER;
----------------------------------------------------------------------
--TIMER_CONTROL_I: TIMER_CONTROL MODULE
----------------------------------------------------------------------
TIMER_CONTROL_I: entity axi_timer_v2_0_10.timer_control
generic map (
C_TRIG0_ASSERT => C_TRIG0_ASSERT,
C_TRIG1_ASSERT => C_TRIG1_ASSERT,
C_GEN0_ASSERT => C_GEN0_ASSERT,
C_GEN1_ASSERT => C_GEN1_ASSERT,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map (
Clk => Clk, -- [in]
Reset => Rst, -- [in]
CaptureTrig0 => CaptureTrig0, -- [in]
CaptureTrig1 => CaptureTrig1, -- [in]
GenerateOut0 => iGenerateOut0, -- [out]
GenerateOut1 => iGenerateOut1, -- [out]
Interrupt => Interrupt, -- [out]
Counter_TC => counter_TC, -- [in]
Bus2ip_data => Bus2ip_data, -- [in]
BE => Bus2ip_be, -- [in]
Load_Counter_Reg => load_Counter_Reg, -- [out]
Load_Load_Reg => load_Load_Reg, -- [out]
Write_Load_Reg => write_Load_Reg, -- [out]
CaptGen_Mux_Sel => captGen_Mux_Sel, -- [out]
Counter_En => counter_En, -- [out]
Count_Down => count_Down, -- [out]
Bus2ip_rdce => Bus2ip_rdce, -- [in]
Bus2ip_wrce => Bus2ip_wrce, -- [in]
Freeze => Freeze, -- [in]
TCSR0_Reg => tCSR0_Reg(20 to 31), -- [out]
TCSR1_Reg => tCSR1_Reg(21 to 31) -- [out]
);
tCSR0_Reg (0 to 19) <= (others => '0');
tCSR1_Reg (0 to 20) <= (others => '0');
pwm_Reset <= iGenerateOut1 or
(not tCSR0_Reg(PWMA0_POS) and not tCSR1_Reg(PWMB0_POS));
PWM_FF_I: component FDRS
port map (
Q => iPWM0, -- [out]
C => Clk, -- [in]
D => iPWM0, -- [in]
R => pwm_Reset, -- [in]
S => iGenerateOut0 -- [in]
);
PWM0 <= iPWM0;
GenerateOut0 <= iGenerateOut0;
GenerateOut1 <= iGenerateOut1;
end architecture IMP;
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: sine_rom.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY sine_rom IS
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END sine_rom;
ARCHITECTURE SYN OF sine_rom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "sine128.mif",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 128,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 7,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "sine128.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "7"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "sine128.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sine_rom.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sine_rom.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sine_rom.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sine_rom.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sine_rom_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A133";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539A803";
when 16#00069# => romdata <= X"8410A261";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"0539A81B";
when 16#00077# => romdata <= X"8410A260";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000008";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D1003FF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A133";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539A803";
when 16#00069# => romdata <= X"8410A261";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"0539A81B";
when 16#00077# => romdata <= X"8410A260";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000008";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D1003FF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A133";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539A803";
when 16#00069# => romdata <= X"8410A261";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"0539A81B";
when 16#00077# => romdata <= X"8410A260";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000008";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D1003FF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: madd - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
-- calculates a*b+c
entity madd is -- latency = mul core latency + 1 if add incl
generic (
MUL_LATENCY : integer := 3;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
INCLUDE_ADD : boolean := false;
C_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
c : in std_logic_vector(C_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end madd;
architecture Behavioral of madd is
constant INT_BITWIDTH : integer := A_BITWIDTH+B_BITWIDTH+1;
type data_delay_type is array(0 to MUL_LATENCY-1) of std_logic_vector(C_BITWIDTH-1 downto 0);
function sext(val : std_logic_vector; length : integer) return std_logic_vector is
variable val_msb : std_logic;
variable result : std_logic_vector(length-1 downto 0);
begin
val_msb := val(val'length-1);
result(val'length-1 downto 0) := val;
result(length-1 downto val'length) := (others => val_msb);
return result;
end sext;
component mul
port (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(A_BITWIDTH-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(B_BITWIDTH DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(A_BITWIDTH+B_BITWIDTH-1 DOWNTO 0)
);
end component;
component addorsub is
generic (
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
signal tmp_pout : std_logic_vector(A_BITWIDTH+B_BITWIDTH-1 downto 0);
signal pout : std_logic_vector(INT_BITWIDTH-1 downto 0);
signal summand_1 : signed(INT_BITWIDTH-1 downto 0);
signal summand_2 : signed(INT_BITWIDTH-1 downto 0);
signal sum_reg : signed(INT_BITWIDTH-1 downto 0);
signal delay_line : std_logic_vector(0 to MUL_LATENCY+1-1);
signal data_delay_line : data_delay_type;
begin
-- compensate mul latency
delay_line_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
delay_line <= (others => '0');
else
delay_line(0) <= nd;
delay_line(1 to MUL_LATENCY+1-1) <= delay_line(0 to MUL_LATENCY+1-2);
end if;
end if;
end process delay_line_proc;
G_N_ADD : if INCLUDE_ADD = false generate
mul_inst : mul
port map (
clk => clk,
a => a,
b => b,
p => tmp_pout
);
pout <= sext(tmp_pout,INT_BITWIDTH);
res <= pout(INT_BITWIDTH-1 downto INT_BITWIDTH-RES_BITWIDTH);
rdy <= delay_line(MUL_LATENCY-1);
end generate G_N_ADD;
G_ADD : if INCLUDE_ADD = true generate
mul_inst : mul
port map (
clk => clk,
a => a,
b => b,
p => tmp_pout
);
data_delay_proc : process(clk)
begin
if rising_edge(clk) then
data_delay_line(0) <= c;
data_delay_line(1 to MUL_LATENCY-1) <= data_delay_line(0 to MUL_LATENCY-2);
end if;
end process data_delay_proc;
summand_1 <= signed(sext(data_delay_line(MUL_LATENCY-1),INT_BITWIDTH));
summand_2 <= signed(sext(tmp_pout,INT_BITWIDTH));
sum_reg_proc : process(clk)
begin
if rising_edge(clk) then
sum_reg <= summand_1 + summand_2;
end if;
end process sum_reg_proc;
res <= std_logic_vector(sum_reg(INT_BITWIDTH-1 downto INT_BITWIDTH-RES_BITWIDTH));
rdy <= delay_line(MUL_LATENCY+1-1);
end generate G_ADD;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: NTU ATHENS - BNL
-- Engineer: Paris Moschovakos
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Paris Moschovakos
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 21.07.2016
-- Design Name:
-- Module Name: vmm_readout.vhd - Behavioral
-- Project Name: MMFE8
-- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
--
-- Changelog:
-- 22.08.2016 Changed state_dt (integer) to state_dt (4 bit vector) (Reid Pinkham)
-- 26.02.2017 Moved to a global clock domain @125MHz (Paris)
-- 06.06.2017 Added vmm_driver interfacing process and readout buffer. (Christos Bakalis)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity vmm_readout is
Port (
clkTkProc : in std_logic; -- Used to clock checking for data process
clkDtProc : in std_logic; -- Used to clock word readout process
clk : in std_logic; -- Main clock
vmm_data0_vec : in std_logic_vector(8 downto 1); -- Single-ended data0 from VMM
vmm_data1_vec : in std_logic_vector(8 downto 1); -- Single-ended data1 from VMM
vmm_ckdt_enable : out std_logic_vector(8 downto 1); -- Enable signal for VMM CKDT
vmm_cktk_vec : out std_logic_vector(8 downto 1); -- Strobe to VMM CKTK
vmm_wen_vec : out std_logic_vector(8 downto 1); -- Strobe to VMM WEN
vmm_ena_vec : out std_logic_vector(8 downto 1); -- Strobe to VMM ENA
vmm_ckdt : out std_logic; -- Strobe to VMM CKDT
daq_enable : in std_logic;
trigger_pulse : in std_logic; -- Trigger
cktk_max : in std_logic_vector(7 downto 0); -- Max number of CKTKs
vmmId : in std_logic_vector(2 downto 0); -- VMM to be readout
ethernet_fifo_wr_en : out std_logic; -- To be used for reading out seperate FIFOs in VMMx8 parallel readout
vmm_data_buf : buffer std_logic_vector(37 downto 0);
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic;
rd_en : in std_logic;
dt_state_o : out std_logic_vector(3 downto 0);
dt_cntr_st_o : out std_logic_vector(3 downto 0)
);
end vmm_readout;
architecture Behavioral of vmm_readout is
-- Interconnected signals
signal reading_out_word : std_logic := '0';
signal reading_out_word_stage1 : std_logic := '0';
signal reading_out_word_ff_sync : std_logic := '0';
signal reading_out_word_i_125 : std_logic := '0';
signal reading_out_word_s_125 : std_logic := '0';
signal cktkSent : std_logic := '0';
signal cktkSent_stage1 : std_logic := '0';
signal cktkSent_ff_sync : std_logic := '0';
signal timeoutCnt : unsigned(3 downto 0) := b"0000";
signal timeout : unsigned(3 downto 0) := b"0111";
signal daq_enable_stage1_Dt : std_logic := '0';
signal daq_enable_ff_sync_Dt : std_logic := '0';
-- tokenProc
signal state_tk : std_logic_vector( 3 downto 0 ) := x"1";
signal daq_enable_stage1 : std_logic := '0';
signal daq_enable_ff_sync : std_logic := '0';
signal vmm_wen_i : std_logic := '0';
signal vmm_ena_i : std_logic := '0';
signal vmm_cktk_i : std_logic := '0';
signal NoFlg_counter : unsigned(7 downto 0) := (others => '0'); -- Counter of CKTKs
signal cktk_max_i : std_logic_vector(7 downto 0) := x"07";
signal cktk_max_sync : std_logic_vector(7 downto 0) := x"07";
signal vmmEventDone_i : std_logic := '0';
signal vmmEventDone_i_125 : std_logic := '0';
signal vmmEventDone_s_125 : std_logic := '0';
signal trigger_pulse_stage1 : std_logic := '0';
signal trigger_pulse_ff_sync: std_logic := '0';
signal hitsLen_cnt : integer := 0;
signal hitsLenMax : integer := 150; --Real maximum is 1119 for a jumbo UDP frame and 184 for a normal UDP frame
-- readoutProc
signal vmm_data_buf_i : std_logic_vector( 37 downto 0 ) := ( others => '0' );
signal state_dt : std_logic_vector(3 downto 0) := "0000";
signal dt_cntr_intg0 : integer := 0;
signal dt_cntr_intg1 : integer := 0;
signal dataBitRead : integer := 0;
signal vmmWordReady_i : std_logic := '0';
signal vmmWord_i : std_logic_vector(63 downto 0);
signal vmm_data1 : std_logic := '0';
signal vmm_data0 : std_logic := '0';
signal vmm_data0_stage1 : std_logic := '0';
signal vmm_data0_ff_sync : std_logic := '0';
signal vmm_data1_stage1 : std_logic := '0';
signal vmm_data1_ff_sync : std_logic := '0';
signal vmm_cktk : std_logic := '0'; -- Strobe to VMM CKTK
signal vmm_ckdt_i : std_logic := '0';
-- driverInterface and readout buffer
signal wr_rst_busy : std_logic := '0';
signal rd_rst_busy : std_logic := '0';
signal rst_buff : std_logic := '0';
signal wr_en : std_logic := '0';
signal fifo_empty : std_logic := '0';
signal fifo_full : std_logic := '0';
signal dbg_intf_state : std_logic_vector(2 downto 0) := (others => '0');
type stateType is (ST_IDLE, ST_WAIT_FOR_DATA, ST_WAIT_FOR_DONE, ST_WAIT_FOR_READ, ST_DONE);
signal state_intf : stateType := ST_IDLE;
-- ASYNC_REG attributes
attribute ASYNC_REG : string;
attribute ASYNC_REG of vmmEventDone_i_125 : signal is "TRUE";
attribute ASYNC_REG of vmmEventDone_s_125 : signal is "TRUE";
attribute ASYNC_REG of daq_enable_stage1 : signal is "TRUE";
attribute ASYNC_REG of daq_enable_ff_sync : signal is "TRUE";
attribute ASYNC_REG of daq_enable_stage1_Dt : signal is "TRUE";
attribute ASYNC_REG of daq_enable_ff_sync_Dt : signal is "TRUE";
attribute ASYNC_REG of trigger_pulse_stage1 : signal is "TRUE";
attribute ASYNC_REG of trigger_pulse_ff_sync : signal is "TRUE";
attribute ASYNC_REG of cktk_max_i : signal is "TRUE";
attribute ASYNC_REG of cktk_max_sync : signal is "TRUE";
attribute ASYNC_REG of reading_out_word_stage1 : signal is "TRUE";
attribute ASYNC_REG of reading_out_word_ff_sync : signal is "TRUE";
attribute ASYNC_REG of reading_out_word_i_125 : signal is "TRUE";
attribute ASYNC_REG of reading_out_word_s_125 : signal is "TRUE";
attribute ASYNC_REG of vmm_data0_stage1 : signal is "TRUE";
attribute ASYNC_REG of vmm_data0_ff_sync : signal is "TRUE";
attribute ASYNC_REG of vmm_data1_stage1 : signal is "TRUE";
attribute ASYNC_REG of vmm_data1_ff_sync : signal is "TRUE";
attribute ASYNC_REG of cktkSent_stage1 : signal is "TRUE";
attribute ASYNC_REG of cktkSent_ff_sync : signal is "TRUE";
-- Debugging
signal probe0_out : std_logic_vector(127 downto 0);
-------------------------------------------------------------------
-- Keep signals for ILA
-----------------------------------------------------------------
attribute mark_debug : string;
-- attribute mark_debug of state_tk : signal is "true";
-- attribute mark_debug of NoFlg_counter : signal is "true";
-- attribute mark_debug of reading_out_word : signal is "true";
-- attribute mark_debug of cktkSent_ff_sync : signal is "true";
-- attribute mark_debug of vmm_ckdt_i : signal is "true";
-- attribute mark_debug of vmm_cktk_i : signal is "true";
-- attribute mark_debug of vmm_data0_ff_sync : signal is "true";
-- attribute mark_debug of vmm_data1_ff_sync : signal is "true";
-- attribute mark_debug of dataBitRead : signal is "true";
-- attribute mark_debug of state_dt : signal is "true";
-- attribute mark_debug of vmmEventDone_i : signal is "true";
-- attribute mark_debug of hitsLen_cnt : signal is "true";
-- attribute mark_debug of vmmWordReady_i : signal is "true";
-- attribute mark_debug of vmmWord_i : signal is "true";
-- attribute mark_debug of trigger_pulse : signal is "true";
-- attribute mark_debug of reading_out_word_ff_sync : signal is "true";
-- attribute mark_debug of timeoutCnt : signal is "true";
-- attribute mark_debug of fifo_empty : signal is "true";
-- attribute mark_debug of dbg_intf_state : signal is "true";
-- attribute mark_debug of rd_en : signal is "true";
-- attribute mark_debug of wr_en : signal is "true";
-- attribute mark_debug of vmm_data0 : signal is "true";
component vmmSignalsDemux
port(
selVMM : in std_logic_vector(2 downto 0);
vmm_data0_vec : in std_logic_vector(8 downto 1);
vmm_data1_vec : in std_logic_vector(8 downto 1);
vmm_data0 : out std_logic;
vmm_data1 : out std_logic;
vmm_cktk : in std_logic;
vmm_ckdt_enable : out std_logic_vector(8 downto 1);
vmm_cktk_vec : out std_logic_vector(8 downto 1)
);
end component;
component ila_readout
port(
clk : in std_logic;
probe0 : in std_logic_vector(127 downto 0)
);
end component;
component cont_buffer
port(
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
full : out std_logic;
empty : out std_logic;
wr_rst_busy : out std_logic;
rd_rst_busy : out std_logic
);
end component;
begin
-- by using this clock the CKTK strobe has f=20MHz (T=50ns, D=50%)
tokenProc: process(clkTkProc)
begin
if (rising_edge(clkTkProc)) then
if (daq_enable_ff_sync = '1') then
case state_tk is
when x"1" =>
vmmEventDone_i <= '0';
if (trigger_pulse_ff_sync = '1') then
state_tk <= x"2";
end if;
when x"2" =>
if (reading_out_word_ff_sync = '0') then -- If we are not reading issue a CKTK
vmm_cktk_i <= '1';
cktkSent <= '1';
hitsLen_cnt <= hitsLen_cnt + 1;
state_tk <= x"3";
else
NoFlg_counter <= ( others => '0' );
state_tk <= x"5";
end if;
when x"3" =>
vmm_cktk_i <= '0';
timeoutCnt <= b"0000";
state_tk <= x"4";
when x"4" =>
if (NoFlg_counter = unsigned(cktk_max_sync)) then
cktkSent <= '0'; -- cktkSent intentionally stays high for x1.5 of ckdt proc clock + VMM delay + datapath delay
state_tk <= x"6"; -- If NoFlg_counter = 7 : time to transmit data
elsif (timeoutCnt = timeout) then -- No data (wait for reading_out_word signal to pass through the synchronizer)
cktkSent <= '0'; -- cktkSent intentionally stays high for x1.5 of ckdt proc clock + VMM delay + datapath delay
NoFlg_counter <= NoFlg_counter + 1;
state_tk <= x"2";
elsif (reading_out_word_ff_sync = '1') then -- Data proc started clocking out VMM data. Wait...
cktkSent <= '0'; -- cktkSent intentionally stays high for x1.5 of ckdt proc clock + VMM delay + datapath delay
NoFlg_counter <= ( others => '0' );
state_tk <= x"5";
else
timeoutCnt <= timeoutCnt + 1;
end if;
when x"5" => -- Wait until word readout is done
if (reading_out_word_ff_sync = '0') then
if hitsLen_cnt >= hitsLenMax then -- Maximum UDP packet length reached
state_tk <= x"6";
else
state_tk <= x"2"; -- Issue new CKTK strobe
end if;
end if;
when x"6" => -- Start the soft reset sequence, there is still a chance
if (reading_out_word_ff_sync = '0') then -- of getting data at this point so check that before soft reset
NoFlg_counter <= ( others => '0' );
state_tk <= x"7";
else
NoFlg_counter <= ( others => '0' );
state_tk <= x"5";
end if;
when x"7" =>
hitsLen_cnt <= 0;
vmmEventDone_i <= '1';
state_tk <= x"1";
when others =>
hitsLen_cnt <= 0;
NoFlg_counter <= ( others => '0' );
state_tk <= x"1";
end case;
else
state_tk <= x"1";
vmm_ena_i <= '0';
vmm_cktk_i <= '0';
timeoutCnt <= b"0000";
hitsLen_cnt <= 0;
NoFlg_counter <= ( others => '0' );
cktkSent <= '0';
vmm_wen_i <= '0';
end if;
end if;
end process;
-- by using this clock the CKDT strobe has f=25MHz (T=40ns, D=50%, phase=0deg) to clock in data0 and data1
readoutProc: process(clkDtProc)
begin
if rising_edge(clkDtProc) then
if (daq_enable_ff_sync_Dt = '1') then
case state_dt is
when x"0" =>
reading_out_word <= '0';
vmm_data_buf <= (others => '0');
dt_cntr_intg0 <= 0;
dt_cntr_intg1 <= 1;
wr_en <= '0';
vmm_ckdt_i <= '0';
if (cktkSent_ff_sync = '1' and vmm_data0_ff_sync = '1') then
state_dt <= x"1";
end if;
when x"1" =>
reading_out_word<= '1';
vmm_ckdt_i <= '1';
state_dt <= x"a";
when x"a" =>
vmm_ckdt_i <= '0';
state_dt <= x"b";
when x"b" =>
if (dataBitRead < 19) then
vmm_ckdt_i <= '1';
end if;
state_dt <= x"2";
when x"2" => -- 19 ckdt and collect data
vmm_ckdt_i <= '0';
if (dataBitRead /= 19) then
vmm_data_buf(dt_cntr_intg0) <= vmm_data0_ff_sync;
vmm_data_buf(dt_cntr_intg1) <= vmm_data1_ff_sync;
vmm_data_buf_i <= vmm_data_buf;
state_dt <= x"b";
dataBitRead <= dataBitRead + 1;
else
vmm_data_buf(dt_cntr_intg0) <= vmm_data0_ff_sync;
vmm_data_buf(dt_cntr_intg1) <= vmm_data1_ff_sync;
vmm_data_buf_i <= vmm_data_buf;
dataBitRead <= 1;
state_dt <= x"3";
end if;
dt_cntr_intg0 <= dt_cntr_intg0 + 2;
dt_cntr_intg1 <= dt_cntr_intg1 + 2;
when x"3" =>
wr_en <= '0';
state_dt <= x"4";
when x"4" =>
wr_en <= '1';
state_dt <= x"5";
when x"5" =>
wr_en <= '0';
state_dt <= x"6";
when x"6" =>
dt_cntr_intg0 <= 0;
dt_cntr_intg1 <= 1;
state_dt <= x"0";
when others =>
dt_cntr_intg0 <= 0;
dt_cntr_intg1 <= 1;
state_dt <= x"0";
end case;
else
dt_cntr_intg0 <= 0;
dt_cntr_intg1 <= 1;
wr_en <= '0';
reading_out_word <= '0';
vmm_ckdt_i <= '0';
state_dt <= x"0";
end if;
end if;
end process;
-- FSM that interfaces with driver
driverInterface: process(clk)
begin
if(rising_edge(clk))then
if(daq_enable = '0')then
state_intf <= ST_IDLE;
vmmWordReady <= '0';
vmmEventDone <= '0';
else
case state_intf is
when ST_IDLE =>
dbg_intf_state <= "000";
vmmWordReady <= '0';
vmmEventDone <= '0';
if(trigger_pulse = '1')then
state_intf <= ST_WAIT_FOR_DATA;
else
state_intf <= ST_IDLE;
end if;
when ST_WAIT_FOR_DATA =>
dbg_intf_state <= "001";
vmmWordReady <= '0';
vmmEventDone <= '0';
if(reading_out_word_s_125 = '1')then -- data detected, wait all to be read out
state_intf <= ST_WAIT_FOR_DONE;
elsif(vmmEventDone_s_125 = '1')then -- no data in the first place
state_intf <= ST_DONE;
else
state_intf <= ST_WAIT_FOR_DATA;
end if;
when ST_WAIT_FOR_DONE =>
dbg_intf_state <= "010";
vmmWordReady <= '0';
vmmEventDone <= '0';
if(vmmEventDone_s_125 = '1')then -- all have been read out
state_intf <= ST_WAIT_FOR_READ;
else
state_intf <= ST_WAIT_FOR_DONE;
end if;
when ST_WAIT_FOR_READ =>
dbg_intf_state <= "011";
vmmWordReady <= '1';
vmmEventDone <= '0';
if(fifo_empty = '1')then -- fifo emptied, go to IDLE
state_intf <= ST_DONE;
else
state_intf <= ST_WAIT_FOR_READ;
end if;
when ST_DONE =>
dbg_intf_state <= "100";
vmmWordReady <= '0';
vmmEventDone <= '1';
if(vmmEventDone_s_125 = '0' and trigger_pulse = '1')then
state_intf <= ST_WAIT_FOR_DATA;
else
state_intf <= ST_DONE;
end if;
end case;
end if;
end if;
end process;
driverInterfaceSynchronizer: process(clk) -- 125
begin
if(rising_edge(clk))then
reading_out_word_i_125 <= reading_out_word;
reading_out_word_s_125 <= reading_out_word_i_125;
vmmEventDone_i_125 <= vmmEventDone_i;
vmmEventDone_s_125 <= vmmEventDone_i_125;
end if;
end process;
tokenProcSynchronizer: process(clkTkProc) --40
begin
if rising_edge (clkTkProc) then
daq_enable_stage1 <= daq_enable;
daq_enable_ff_sync <= daq_enable_stage1;
trigger_pulse_stage1 <= trigger_pulse;
trigger_pulse_ff_sync <= trigger_pulse_stage1;
reading_out_word_stage1 <= reading_out_word;
reading_out_word_ff_sync <= reading_out_word_stage1;
cktk_max_i <= cktk_max;
cktk_max_sync <= cktk_max_i;
end if;
end process;
readoutProcSynchronizer: process(clkDtProc) --50
begin
if rising_edge(clkDtProc) then
daq_enable_stage1_Dt <= daq_enable;
daq_enable_ff_sync_Dt <= daq_enable_stage1_Dt;
cktkSent_stage1 <= cktkSent;
cktkSent_ff_sync <= cktkSent_stage1;
vmm_data0_stage1 <= vmm_data0;
vmm_data0_ff_sync <= vmm_data0_stage1;
vmm_data1_stage1 <= vmm_data1;
vmm_data1_ff_sync <= vmm_data1_stage1;
end if;
end process;
cont_buffer_inst: cont_buffer
PORT MAP (
rst => rst_buff,
wr_clk => clkDtProc,
rd_clk => clk,
din => vmmWord_i,
wr_en => wr_en,
rd_en => rd_en,
dout => vmmWord,
full => fifo_full,
empty => fifo_empty,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy
);
vmm_cktk <= vmm_cktk_i;
vmm_ckdt <= vmm_ckdt_i;
dt_state_o <= state_tk;
dt_cntr_st_o <= state_dt;
rst_buff <= not daq_enable;
vmmWord_i <= b"00" & vmm_data_buf(25 downto 18) & vmm_data_buf(37 downto 26) & vmm_data_buf(17 downto 8) & b"000000000000000000000000" & vmm_data_buf(7 downto 2) & vmm_data_buf(1) & vmm_data_buf(0);
-- TDO & Gray & PDO & & Address & Threshold & Flag;
VMMdemux: vmmSignalsDemux
port map(
selVMM => vmmId,
vmm_data0_vec => vmm_data0_vec,
vmm_data1_vec => vmm_data1_vec,
vmm_data0 => vmm_data0,
vmm_data1 => vmm_data1,
vmm_cktk => vmm_cktk,
vmm_ckdt_enable => vmm_ckdt_enable,
vmm_cktk_vec => vmm_cktk_vec
);
--ilaDAQ: ila_readout
--port map
-- (
-- clk => clk,
-- probe0 => probe0_out
-- );
-- probe0_out(0) <= vmm_cktk_i; -- OK
-- probe0_out(4 downto 1) <= state_tk; -- OK
-- probe0_out(5) <= vmm_data0;
-- probe0_out(7 downto 6) <= (others => '0');
-- probe0_out(10 downto 8) <= (others => '0'); -- OK
-- probe0_out(14 downto 11) <= state_dt; -- OK
-- probe0_out(15) <= daq_enable_ff_sync; -- OK
-- probe0_out(16) <= reading_out_word; -- OK
-- probe0_out(17) <= cktkSent_ff_sync; -- OK
-- probe0_out(18) <= vmm_ckdt_i; -- OK
-- probe0_out(19) <= vmm_data0_ff_sync; -- OK
-- probe0_out(20) <= vmm_data1_ff_sync; -- OK
-- probe0_out(25 downto 21) <= std_logic_vector(to_unsigned(dataBitRead, probe0_out(28 downto 24)'length)); -- OK
-- probe0_out(26) <= vmmWordReady_i; -- OK
-- probe0_out(90 downto 27) <= vmmWord_i; -- OK
-- probe0_out(91) <= trigger_pulse; -- OK
-- probe0_out(92) <= reading_out_word_ff_sync;
-- probe0_out(96 downto 93) <= std_logic_vector(timeoutCnt);
-- probe0_out(97) <= fifo_empty;
-- probe0_out(98) <= rd_en;
-- probe0_out(99) <= wr_en;
-- probe0_out(102 downto 100) <= dbg_intf_state;
-- probe0_out(127 downto 103) <= (others => '0');
end Behavioral; |
-- NEED RESULT: ARCH00134.P1: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P2: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P3: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P4: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P5: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P6: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P7: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P8: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P9: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P10: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P11: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P12: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P13: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P14: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P15: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P16: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P17: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: P17: Inertial transactions entirely completed passed
-- NEED RESULT: P16: Inertial transactions entirely completed passed
-- NEED RESULT: P15: Inertial transactions entirely completed passed
-- NEED RESULT: P14: Inertial transactions entirely completed passed
-- NEED RESULT: P13: Inertial transactions entirely completed passed
-- NEED RESULT: P12: Inertial transactions entirely completed passed
-- NEED RESULT: P11: Inertial transactions entirely completed passed
-- NEED RESULT: P10: Inertial transactions entirely completed passed
-- NEED RESULT: P9: Inertial transactions entirely completed passed
-- NEED RESULT: P8: Inertial transactions entirely completed passed
-- NEED RESULT: P7: Inertial transactions entirely completed passed
-- NEED RESULT: P6: Inertial transactions entirely completed passed
-- NEED RESULT: P5: Inertial transactions entirely completed passed
-- NEED RESULT: P4: Inertial transactions entirely completed passed
-- NEED RESULT: P3: Inertial transactions entirely completed passed
-- NEED RESULT: P2: Inertial transactions entirely completed passed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00134
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00134(ARCH00134)
-- ENT00134_Test_Bench(ARCH00134_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00134 is
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
end ENT00134 ;
--
architecture ARCH00134 of ENT00134 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_boolean <=
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <=
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_boolean <= c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <= transport
c_boolean_1 after 100 ns ;
--
when 5
=> correct :=
s_boolean = c_boolean_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <=
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns ;
--
when 6
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <= -- Last transaction above is marked
c_boolean_1 after 40 ns ;
--
when 7
=> correct :=
s_boolean = c_boolean_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_boolean = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_boolean <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_boolean'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_bit <=
c_bit_2 after 10 ns,
c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <=
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_bit <= c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <= transport
c_bit_1 after 100 ns ;
--
when 5
=> correct :=
s_bit = c_bit_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <=
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns ;
--
when 6
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <= -- Last transaction above is marked
c_bit_1 after 40 ns ;
--
when 7
=> correct :=
s_bit = c_bit_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_bit = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_bit <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_bit'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_severity_level <=
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <=
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_severity_level <= c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <= transport
c_severity_level_1 after 100 ns ;
--
when 5
=> correct :=
s_severity_level = c_severity_level_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <=
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns ;
--
when 6
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <= -- Last transaction above is marked
c_severity_level_1 after 40 ns ;
--
when 7
=> correct :=
s_severity_level = c_severity_level_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_severity_level = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_severity_level <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_severity_level'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_character <=
c_character_2 after 10 ns,
c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <=
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_character <= c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <= transport
c_character_1 after 100 ns ;
--
when 5
=> correct :=
s_character = c_character_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <=
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns ;
--
when 6
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <= -- Last transaction above is marked
c_character_1 after 40 ns ;
--
when 7
=> correct :=
s_character = c_character_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_character = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_character <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_character'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_enum1 <=
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <=
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1 <= c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <= transport
c_st_enum1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_enum1 = c_st_enum1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <=
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <= -- Last transaction above is marked
c_st_enum1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_enum1 = c_st_enum1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_enum1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_integer <=
c_integer_2 after 10 ns,
c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <=
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_integer <= c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <= transport
c_integer_1 after 100 ns ;
--
when 5
=> correct :=
s_integer = c_integer_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <=
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns ;
--
when 6
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <= -- Last transaction above is marked
c_integer_1 after 40 ns ;
--
when 7
=> correct :=
s_integer = c_integer_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_integer = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_integer <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_integer'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_int1 <=
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <=
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1 <= c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <= transport
c_st_int1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_int1 = c_st_int1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <=
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <= -- Last transaction above is marked
c_st_int1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_int1 = c_st_int1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_int1 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_int1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_time <=
c_time_2 after 10 ns,
c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <=
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_time <= c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <= transport
c_time_1 after 100 ns ;
--
when 5
=> correct :=
s_time = c_time_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <=
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns ;
--
when 6
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <= -- Last transaction above is marked
c_time_1 after 40 ns ;
--
when 7
=> correct :=
s_time = c_time_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_time = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_time <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_time'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_phys1 <=
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <=
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1 <= c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <= transport
c_st_phys1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_phys1 = c_st_phys1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <=
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <= -- Last transaction above is marked
c_st_phys1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_phys1 = c_st_phys1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_phys1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_real <=
c_real_2 after 10 ns,
c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <=
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_real <= c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <= transport
c_real_1 after 100 ns ;
--
when 5
=> correct :=
s_real = c_real_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <=
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns ;
--
when 6
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <= -- Last transaction above is marked
c_real_1 after 40 ns ;
--
when 7
=> correct :=
s_real = c_real_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_real = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_real <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_real'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_real1 <=
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <=
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1 <= c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <= transport
c_st_real1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_real1 = c_st_real1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <=
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <= -- Last transaction above is marked
c_st_real1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_real1 = c_st_real1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_real1 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_real1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec1 <=
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <=
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1 <= c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <= transport
c_st_rec1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1 = c_st_rec1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <=
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <= -- Last transaction above is marked
c_st_rec1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1 = c_st_rec1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec2 <=
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <=
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2 <= c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <= transport
c_st_rec2_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2 = c_st_rec2_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <=
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <= -- Last transaction above is marked
c_st_rec2_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2 = c_st_rec2_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec3 <=
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <=
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3 <= c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <= transport
c_st_rec3_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3 = c_st_rec3_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <=
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <= -- Last transaction above is marked
c_st_rec3_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3 = c_st_rec3_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr1 <=
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <=
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 <= c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <= transport
c_st_arr1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr1 = c_st_arr1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <=
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <= -- Last transaction above is marked
c_st_arr1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr1 = c_st_arr1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr2 <=
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <=
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 <= c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <= transport
c_st_arr2_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr2 = c_st_arr2_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <=
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <= -- Last transaction above is marked
c_st_arr2_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr2 = c_st_arr2_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr3 <=
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <=
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 <= c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <= transport
c_st_arr3_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr3 = c_st_arr3_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <=
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <= -- Last transaction above is marked
c_st_arr3_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr3 = c_st_arr3_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00134 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00134_Test_Bench is
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00134_Test_Bench ;
--
architecture ARCH00134_Test_Bench of ENT00134_Test_Bench is
begin
L1:
block
component UUT
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00134 ( ARCH00134 ) ;
begin
CIS1 : UUT
port map (
s_boolean
, s_bit
, s_severity_level
, s_character
, s_st_enum1
, s_integer
, s_st_int1
, s_time
, s_st_phys1
, s_real
, s_st_real1
, s_st_rec1
, s_st_rec2
, s_st_rec3
, s_st_arr1
, s_st_arr2
, s_st_arr3
) ;
end block L1 ;
end ARCH00134_Test_Bench ;
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Cadre : GEN1333 - Conception des circuits integrés --
-- : Projet de conception individuel 1 --
-- Par : Maxime Gauthier --
-- Date : 03 / 21 / 2015 --
-- Fichier : subtractor_n.vhd --
-- Description : VHDL pour une unité arithmétique logique générique (n bits) --
-- : basé sur du matériel de cours fourni par Ahmed Lakhsassi --
-- : et du code originellement écrit par Antoine Shaneen --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- librairie a inclure
library ieee;
use ieee.std_logic_1164.all;
-- déclaration de l'entité de l'additionneur générique (n bits) paramétrable
entity subtractor_n is
generic ( N : integer := 8);
port (
minuend, subtrahend : in std_logic_vector ( N downto 1 );
carry_in : in std_logic;
difference : out std_logic_vector ( N downto 1 );
overflow_flag : out std_logic
);
end entity subtractor_n;
-- architecture structurelle de l'additionneur générique (n bits).
architecture subtractor_n_impl of subtractor_n is
-- declaration des composants
component adder_n
port(
augend, addend : in std_logic_vector ( N downto 1 );
carry_in : in std_logic;
sum : out std_logic_vector ( N downto 1 );
carry_out : out std_logic
);
end component;
component twos_complement_n
port(
x : in std_logic_vector ( N downto 1 );
y : out std_logic_vector ( N downto 1 )
);
end component;
-- zone de déclaration
signal s : std_logic_vector ( N downto 1 );
begin
adder_1 : adder_n port map(minuend, s, carry_in, difference, overflow_flag);
twos_1 : twos_complement_n port map(subtrahend, s);
end architecture subtractor_n_impl;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fpext_0_no_dsp_32 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END ANN_ap_fpext_0_no_dsp_32;
ARCHITECTURE ANN_ap_fpext_0_no_dsp_32_arch OF ANN_ap_fpext_0_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fpext_0_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fpext_0_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fpext_0_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fpext_0_no_dsp_32_arch;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL23X56.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 23 and 56 bit inputs, 4 pipes ***
--*** ***
--*** 07/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul23x56 IS
GENERIC (device : integer := 0);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 1)
);
END fp_mul23x56;
ARCHITECTURE SYN OF fp_mul23x56 IS
constant AW : integer := 23;
constant BW : integer := 56;
constant RW : integer := AW+BW;
-- use 27-bit multipliers on SV/AV/CV,
-- use 36-bit multipliers on SIII/SIV
-- split multiplication into two equal parts on other architectures
function chooseMaxMulWidth(device : integer) return integer is
begin
if (device = 2) then
return 27;
elsif (device = 1) then
return 36;
else
return 28;
end if;
end function;
constant MAXMULWIDTH : integer := chooseMaxMulWidth(device);
constant use_2_multipliers : boolean := BW <= 2 * MAXMULWIDTH;
constant use_3_multipliers : boolean := not use_2_multipliers;
component fp_mul2s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
component fp_mul3s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
signal zerovec : STD_LOGIC_VECTOR(MAXMULWIDTH DOWNTO 1);
BEGIN
zerovec <= (others => '0');
gen2mul: IF use_2_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := BW - BLW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal adderff : STD_LOGIC_VECTOR(RW DOWNTO 1);
BEGIN
ml: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff <= (zerovec(RW-(BLW+AW) DOWNTO 1) & multiplier_low) +
(multiplier_high & zerovec(RW-(BHW+AW) DOWNTO 1));
END IF;
END IF;
END PROCESS;
result <= adderff;
END GENERATE;
gen3mul: IF use_3_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := MAXMULWIDTH;
constant BTW : integer := BW - BLW - BHW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal multiplier_top : STD_LOGIC_VECTOR(BTW+AW DOWNTO 1);
signal adderff0 : STD_LOGIC_VECTOR (RW DOWNTO 1);
signal adderff1 : STD_LOGIC_VECTOR (RW DOWNTO 1);
BEGIN
ml: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
mt: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BTW,widthcc=>BTW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BTW+BHW+BLW DOWNTO BHW+BLW+1),
result=>multiplier_top);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff0 <= (others => '0');
adderff1 <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff0 <= (multiplier_top & zerovec(RW-(BTW+AW)-(BLW+AW) DOWNTO 1) & multiplier_low) +
(zerovec(RW-(BHW+AW)-BLW DOWNTO 1) & multiplier_high & zerovec(BLW DOWNTO 1));
adderff1 <= adderff0;
END IF;
END IF;
END PROCESS;
result <= adderff1;
END GENERATE;
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL23X56.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 23 and 56 bit inputs, 4 pipes ***
--*** ***
--*** 07/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul23x56 IS
GENERIC (device : integer := 0);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 1)
);
END fp_mul23x56;
ARCHITECTURE SYN OF fp_mul23x56 IS
constant AW : integer := 23;
constant BW : integer := 56;
constant RW : integer := AW+BW;
-- use 27-bit multipliers on SV/AV/CV,
-- use 36-bit multipliers on SIII/SIV
-- split multiplication into two equal parts on other architectures
function chooseMaxMulWidth(device : integer) return integer is
begin
if (device = 2) then
return 27;
elsif (device = 1) then
return 36;
else
return 28;
end if;
end function;
constant MAXMULWIDTH : integer := chooseMaxMulWidth(device);
constant use_2_multipliers : boolean := BW <= 2 * MAXMULWIDTH;
constant use_3_multipliers : boolean := not use_2_multipliers;
component fp_mul2s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
component fp_mul3s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
signal zerovec : STD_LOGIC_VECTOR(MAXMULWIDTH DOWNTO 1);
BEGIN
zerovec <= (others => '0');
gen2mul: IF use_2_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := BW - BLW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal adderff : STD_LOGIC_VECTOR(RW DOWNTO 1);
BEGIN
ml: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff <= (zerovec(RW-(BLW+AW) DOWNTO 1) & multiplier_low) +
(multiplier_high & zerovec(RW-(BHW+AW) DOWNTO 1));
END IF;
END IF;
END PROCESS;
result <= adderff;
END GENERATE;
gen3mul: IF use_3_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := MAXMULWIDTH;
constant BTW : integer := BW - BLW - BHW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal multiplier_top : STD_LOGIC_VECTOR(BTW+AW DOWNTO 1);
signal adderff0 : STD_LOGIC_VECTOR (RW DOWNTO 1);
signal adderff1 : STD_LOGIC_VECTOR (RW DOWNTO 1);
BEGIN
ml: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
mt: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BTW,widthcc=>BTW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BTW+BHW+BLW DOWNTO BHW+BLW+1),
result=>multiplier_top);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff0 <= (others => '0');
adderff1 <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff0 <= (multiplier_top & zerovec(RW-(BTW+AW)-(BLW+AW) DOWNTO 1) & multiplier_low) +
(zerovec(RW-(BHW+AW)-BLW DOWNTO 1) & multiplier_high & zerovec(BLW DOWNTO 1));
adderff1 <= adderff0;
END IF;
END IF;
END PROCESS;
result <= adderff1;
END GENERATE;
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL23X56.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 23 and 56 bit inputs, 4 pipes ***
--*** ***
--*** 07/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul23x56 IS
GENERIC (device : integer := 0);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 1)
);
END fp_mul23x56;
ARCHITECTURE SYN OF fp_mul23x56 IS
constant AW : integer := 23;
constant BW : integer := 56;
constant RW : integer := AW+BW;
-- use 27-bit multipliers on SV/AV/CV,
-- use 36-bit multipliers on SIII/SIV
-- split multiplication into two equal parts on other architectures
function chooseMaxMulWidth(device : integer) return integer is
begin
if (device = 2) then
return 27;
elsif (device = 1) then
return 36;
else
return 28;
end if;
end function;
constant MAXMULWIDTH : integer := chooseMaxMulWidth(device);
constant use_2_multipliers : boolean := BW <= 2 * MAXMULWIDTH;
constant use_3_multipliers : boolean := not use_2_multipliers;
component fp_mul2s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
component fp_mul3s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
signal zerovec : STD_LOGIC_VECTOR(MAXMULWIDTH DOWNTO 1);
BEGIN
zerovec <= (others => '0');
gen2mul: IF use_2_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := BW - BLW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal adderff : STD_LOGIC_VECTOR(RW DOWNTO 1);
BEGIN
ml: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff <= (zerovec(RW-(BLW+AW) DOWNTO 1) & multiplier_low) +
(multiplier_high & zerovec(RW-(BHW+AW) DOWNTO 1));
END IF;
END IF;
END PROCESS;
result <= adderff;
END GENERATE;
gen3mul: IF use_3_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := MAXMULWIDTH;
constant BTW : integer := BW - BLW - BHW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal multiplier_top : STD_LOGIC_VECTOR(BTW+AW DOWNTO 1);
signal adderff0 : STD_LOGIC_VECTOR (RW DOWNTO 1);
signal adderff1 : STD_LOGIC_VECTOR (RW DOWNTO 1);
BEGIN
ml: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
mt: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BTW,widthcc=>BTW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BTW+BHW+BLW DOWNTO BHW+BLW+1),
result=>multiplier_top);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff0 <= (others => '0');
adderff1 <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff0 <= (multiplier_top & zerovec(RW-(BTW+AW)-(BLW+AW) DOWNTO 1) & multiplier_low) +
(zerovec(RW-(BHW+AW)-BLW DOWNTO 1) & multiplier_high & zerovec(BLW DOWNTO 1));
adderff1 <= adderff0;
END IF;
END IF;
END PROCESS;
result <= adderff1;
END GENERATE;
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL23X56.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 23 and 56 bit inputs, 4 pipes ***
--*** ***
--*** 07/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul23x56 IS
GENERIC (device : integer := 0);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 1)
);
END fp_mul23x56;
ARCHITECTURE SYN OF fp_mul23x56 IS
constant AW : integer := 23;
constant BW : integer := 56;
constant RW : integer := AW+BW;
-- use 27-bit multipliers on SV/AV/CV,
-- use 36-bit multipliers on SIII/SIV
-- split multiplication into two equal parts on other architectures
function chooseMaxMulWidth(device : integer) return integer is
begin
if (device = 2) then
return 27;
elsif (device = 1) then
return 36;
else
return 28;
end if;
end function;
constant MAXMULWIDTH : integer := chooseMaxMulWidth(device);
constant use_2_multipliers : boolean := BW <= 2 * MAXMULWIDTH;
constant use_3_multipliers : boolean := not use_2_multipliers;
component fp_mul2s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
component fp_mul3s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
signal zerovec : STD_LOGIC_VECTOR(MAXMULWIDTH DOWNTO 1);
BEGIN
zerovec <= (others => '0');
gen2mul: IF use_2_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := BW - BLW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal adderff : STD_LOGIC_VECTOR(RW DOWNTO 1);
BEGIN
ml: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff <= (zerovec(RW-(BLW+AW) DOWNTO 1) & multiplier_low) +
(multiplier_high & zerovec(RW-(BHW+AW) DOWNTO 1));
END IF;
END IF;
END PROCESS;
result <= adderff;
END GENERATE;
gen3mul: IF use_3_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := MAXMULWIDTH;
constant BTW : integer := BW - BLW - BHW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal multiplier_top : STD_LOGIC_VECTOR(BTW+AW DOWNTO 1);
signal adderff0 : STD_LOGIC_VECTOR (RW DOWNTO 1);
signal adderff1 : STD_LOGIC_VECTOR (RW DOWNTO 1);
BEGIN
ml: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
mt: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BTW,widthcc=>BTW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BTW+BHW+BLW DOWNTO BHW+BLW+1),
result=>multiplier_top);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff0 <= (others => '0');
adderff1 <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff0 <= (multiplier_top & zerovec(RW-(BTW+AW)-(BLW+AW) DOWNTO 1) & multiplier_low) +
(zerovec(RW-(BHW+AW)-BLW DOWNTO 1) & multiplier_high & zerovec(BLW DOWNTO 1));
adderff1 <= adderff0;
END IF;
END IF;
END PROCESS;
result <= adderff1;
END GENERATE;
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL23X56.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 23 and 56 bit inputs, 4 pipes ***
--*** ***
--*** 07/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul23x56 IS
GENERIC (device : integer := 0);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 1)
);
END fp_mul23x56;
ARCHITECTURE SYN OF fp_mul23x56 IS
constant AW : integer := 23;
constant BW : integer := 56;
constant RW : integer := AW+BW;
-- use 27-bit multipliers on SV/AV/CV,
-- use 36-bit multipliers on SIII/SIV
-- split multiplication into two equal parts on other architectures
function chooseMaxMulWidth(device : integer) return integer is
begin
if (device = 2) then
return 27;
elsif (device = 1) then
return 36;
else
return 28;
end if;
end function;
constant MAXMULWIDTH : integer := chooseMaxMulWidth(device);
constant use_2_multipliers : boolean := BW <= 2 * MAXMULWIDTH;
constant use_3_multipliers : boolean := not use_2_multipliers;
component fp_mul2s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
component fp_mul3s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
signal zerovec : STD_LOGIC_VECTOR(MAXMULWIDTH DOWNTO 1);
BEGIN
zerovec <= (others => '0');
gen2mul: IF use_2_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := BW - BLW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal adderff : STD_LOGIC_VECTOR(RW DOWNTO 1);
BEGIN
ml: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff <= (zerovec(RW-(BLW+AW) DOWNTO 1) & multiplier_low) +
(multiplier_high & zerovec(RW-(BHW+AW) DOWNTO 1));
END IF;
END IF;
END PROCESS;
result <= adderff;
END GENERATE;
gen3mul: IF use_3_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := MAXMULWIDTH;
constant BTW : integer := BW - BLW - BHW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal multiplier_top : STD_LOGIC_VECTOR(BTW+AW DOWNTO 1);
signal adderff0 : STD_LOGIC_VECTOR (RW DOWNTO 1);
signal adderff1 : STD_LOGIC_VECTOR (RW DOWNTO 1);
BEGIN
ml: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
mt: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BTW,widthcc=>BTW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BTW+BHW+BLW DOWNTO BHW+BLW+1),
result=>multiplier_top);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff0 <= (others => '0');
adderff1 <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff0 <= (multiplier_top & zerovec(RW-(BTW+AW)-(BLW+AW) DOWNTO 1) & multiplier_low) +
(zerovec(RW-(BHW+AW)-BLW DOWNTO 1) & multiplier_high & zerovec(BLW DOWNTO 1));
adderff1 <= adderff0;
END IF;
END IF;
END PROCESS;
result <= adderff1;
END GENERATE;
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL23X56.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 23 and 56 bit inputs, 4 pipes ***
--*** ***
--*** 07/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul23x56 IS
GENERIC (device : integer := 0);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 1)
);
END fp_mul23x56;
ARCHITECTURE SYN OF fp_mul23x56 IS
constant AW : integer := 23;
constant BW : integer := 56;
constant RW : integer := AW+BW;
-- use 27-bit multipliers on SV/AV/CV,
-- use 36-bit multipliers on SIII/SIV
-- split multiplication into two equal parts on other architectures
function chooseMaxMulWidth(device : integer) return integer is
begin
if (device = 2) then
return 27;
elsif (device = 1) then
return 36;
else
return 28;
end if;
end function;
constant MAXMULWIDTH : integer := chooseMaxMulWidth(device);
constant use_2_multipliers : boolean := BW <= 2 * MAXMULWIDTH;
constant use_3_multipliers : boolean := not use_2_multipliers;
component fp_mul2s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
component fp_mul3s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
signal zerovec : STD_LOGIC_VECTOR(MAXMULWIDTH DOWNTO 1);
BEGIN
zerovec <= (others => '0');
gen2mul: IF use_2_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := BW - BLW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal adderff : STD_LOGIC_VECTOR(RW DOWNTO 1);
BEGIN
ml: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff <= (zerovec(RW-(BLW+AW) DOWNTO 1) & multiplier_low) +
(multiplier_high & zerovec(RW-(BHW+AW) DOWNTO 1));
END IF;
END IF;
END PROCESS;
result <= adderff;
END GENERATE;
gen3mul: IF use_3_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := MAXMULWIDTH;
constant BTW : integer := BW - BLW - BHW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal multiplier_top : STD_LOGIC_VECTOR(BTW+AW DOWNTO 1);
signal adderff0 : STD_LOGIC_VECTOR (RW DOWNTO 1);
signal adderff1 : STD_LOGIC_VECTOR (RW DOWNTO 1);
BEGIN
ml: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
mt: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BTW,widthcc=>BTW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BTW+BHW+BLW DOWNTO BHW+BLW+1),
result=>multiplier_top);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff0 <= (others => '0');
adderff1 <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff0 <= (multiplier_top & zerovec(RW-(BTW+AW)-(BLW+AW) DOWNTO 1) & multiplier_low) +
(zerovec(RW-(BHW+AW)-BLW DOWNTO 1) & multiplier_high & zerovec(BLW DOWNTO 1));
adderff1 <= adderff0;
END IF;
END IF;
END PROCESS;
result <= adderff1;
END GENERATE;
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL23X56.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 23 and 56 bit inputs, 4 pipes ***
--*** ***
--*** 07/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul23x56 IS
GENERIC (device : integer := 0);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 1)
);
END fp_mul23x56;
ARCHITECTURE SYN OF fp_mul23x56 IS
constant AW : integer := 23;
constant BW : integer := 56;
constant RW : integer := AW+BW;
-- use 27-bit multipliers on SV/AV/CV,
-- use 36-bit multipliers on SIII/SIV
-- split multiplication into two equal parts on other architectures
function chooseMaxMulWidth(device : integer) return integer is
begin
if (device = 2) then
return 27;
elsif (device = 1) then
return 36;
else
return 28;
end if;
end function;
constant MAXMULWIDTH : integer := chooseMaxMulWidth(device);
constant use_2_multipliers : boolean := BW <= 2 * MAXMULWIDTH;
constant use_3_multipliers : boolean := not use_2_multipliers;
component fp_mul2s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
component fp_mul3s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
signal zerovec : STD_LOGIC_VECTOR(MAXMULWIDTH DOWNTO 1);
BEGIN
zerovec <= (others => '0');
gen2mul: IF use_2_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := BW - BLW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal adderff : STD_LOGIC_VECTOR(RW DOWNTO 1);
BEGIN
ml: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff <= (zerovec(RW-(BLW+AW) DOWNTO 1) & multiplier_low) +
(multiplier_high & zerovec(RW-(BHW+AW) DOWNTO 1));
END IF;
END IF;
END PROCESS;
result <= adderff;
END GENERATE;
gen3mul: IF use_3_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := MAXMULWIDTH;
constant BTW : integer := BW - BLW - BHW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal multiplier_top : STD_LOGIC_VECTOR(BTW+AW DOWNTO 1);
signal adderff0 : STD_LOGIC_VECTOR (RW DOWNTO 1);
signal adderff1 : STD_LOGIC_VECTOR (RW DOWNTO 1);
BEGIN
ml: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
mt: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BTW,widthcc=>BTW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BTW+BHW+BLW DOWNTO BHW+BLW+1),
result=>multiplier_top);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff0 <= (others => '0');
adderff1 <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff0 <= (multiplier_top & zerovec(RW-(BTW+AW)-(BLW+AW) DOWNTO 1) & multiplier_low) +
(zerovec(RW-(BHW+AW)-BLW DOWNTO 1) & multiplier_high & zerovec(BLW DOWNTO 1));
adderff1 <= adderff0;
END IF;
END IF;
END PROCESS;
result <= adderff1;
END GENERATE;
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL23X56.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 23 and 56 bit inputs, 4 pipes ***
--*** ***
--*** 07/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul23x56 IS
GENERIC (device : integer := 0);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 1)
);
END fp_mul23x56;
ARCHITECTURE SYN OF fp_mul23x56 IS
constant AW : integer := 23;
constant BW : integer := 56;
constant RW : integer := AW+BW;
-- use 27-bit multipliers on SV/AV/CV,
-- use 36-bit multipliers on SIII/SIV
-- split multiplication into two equal parts on other architectures
function chooseMaxMulWidth(device : integer) return integer is
begin
if (device = 2) then
return 27;
elsif (device = 1) then
return 36;
else
return 28;
end if;
end function;
constant MAXMULWIDTH : integer := chooseMaxMulWidth(device);
constant use_2_multipliers : boolean := BW <= 2 * MAXMULWIDTH;
constant use_3_multipliers : boolean := not use_2_multipliers;
component fp_mul2s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
component fp_mul3s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
signal zerovec : STD_LOGIC_VECTOR(MAXMULWIDTH DOWNTO 1);
BEGIN
zerovec <= (others => '0');
gen2mul: IF use_2_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := BW - BLW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal adderff : STD_LOGIC_VECTOR(RW DOWNTO 1);
BEGIN
ml: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff <= (zerovec(RW-(BLW+AW) DOWNTO 1) & multiplier_low) +
(multiplier_high & zerovec(RW-(BHW+AW) DOWNTO 1));
END IF;
END IF;
END PROCESS;
result <= adderff;
END GENERATE;
gen3mul: IF use_3_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := MAXMULWIDTH;
constant BTW : integer := BW - BLW - BHW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal multiplier_top : STD_LOGIC_VECTOR(BTW+AW DOWNTO 1);
signal adderff0 : STD_LOGIC_VECTOR (RW DOWNTO 1);
signal adderff1 : STD_LOGIC_VECTOR (RW DOWNTO 1);
BEGIN
ml: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
mt: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BTW,widthcc=>BTW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BTW+BHW+BLW DOWNTO BHW+BLW+1),
result=>multiplier_top);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff0 <= (others => '0');
adderff1 <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff0 <= (multiplier_top & zerovec(RW-(BTW+AW)-(BLW+AW) DOWNTO 1) & multiplier_low) +
(zerovec(RW-(BHW+AW)-BLW DOWNTO 1) & multiplier_high & zerovec(BLW DOWNTO 1));
adderff1 <= adderff0;
END IF;
END IF;
END PROCESS;
result <= adderff1;
END GENERATE;
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL23X56.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 23 and 56 bit inputs, 4 pipes ***
--*** ***
--*** 07/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul23x56 IS
GENERIC (device : integer := 0);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 1)
);
END fp_mul23x56;
ARCHITECTURE SYN OF fp_mul23x56 IS
constant AW : integer := 23;
constant BW : integer := 56;
constant RW : integer := AW+BW;
-- use 27-bit multipliers on SV/AV/CV,
-- use 36-bit multipliers on SIII/SIV
-- split multiplication into two equal parts on other architectures
function chooseMaxMulWidth(device : integer) return integer is
begin
if (device = 2) then
return 27;
elsif (device = 1) then
return 36;
else
return 28;
end if;
end function;
constant MAXMULWIDTH : integer := chooseMaxMulWidth(device);
constant use_2_multipliers : boolean := BW <= 2 * MAXMULWIDTH;
constant use_3_multipliers : boolean := not use_2_multipliers;
component fp_mul2s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
component fp_mul3s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
signal zerovec : STD_LOGIC_VECTOR(MAXMULWIDTH DOWNTO 1);
BEGIN
zerovec <= (others => '0');
gen2mul: IF use_2_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := BW - BLW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal adderff : STD_LOGIC_VECTOR(RW DOWNTO 1);
BEGIN
ml: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff <= (zerovec(RW-(BLW+AW) DOWNTO 1) & multiplier_low) +
(multiplier_high & zerovec(RW-(BHW+AW) DOWNTO 1));
END IF;
END IF;
END PROCESS;
result <= adderff;
END GENERATE;
gen3mul: IF use_3_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := MAXMULWIDTH;
constant BTW : integer := BW - BLW - BHW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal multiplier_top : STD_LOGIC_VECTOR(BTW+AW DOWNTO 1);
signal adderff0 : STD_LOGIC_VECTOR (RW DOWNTO 1);
signal adderff1 : STD_LOGIC_VECTOR (RW DOWNTO 1);
BEGIN
ml: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
mt: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BTW,widthcc=>BTW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BTW+BHW+BLW DOWNTO BHW+BLW+1),
result=>multiplier_top);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff0 <= (others => '0');
adderff1 <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff0 <= (multiplier_top & zerovec(RW-(BTW+AW)-(BLW+AW) DOWNTO 1) & multiplier_low) +
(zerovec(RW-(BHW+AW)-BLW DOWNTO 1) & multiplier_high & zerovec(BLW DOWNTO 1));
adderff1 <= adderff0;
END IF;
END IF;
END PROCESS;
result <= adderff1;
END GENERATE;
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL23X56.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 23 and 56 bit inputs, 4 pipes ***
--*** ***
--*** 07/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul23x56 IS
GENERIC (device : integer := 0);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 1)
);
END fp_mul23x56;
ARCHITECTURE SYN OF fp_mul23x56 IS
constant AW : integer := 23;
constant BW : integer := 56;
constant RW : integer := AW+BW;
-- use 27-bit multipliers on SV/AV/CV,
-- use 36-bit multipliers on SIII/SIV
-- split multiplication into two equal parts on other architectures
function chooseMaxMulWidth(device : integer) return integer is
begin
if (device = 2) then
return 27;
elsif (device = 1) then
return 36;
else
return 28;
end if;
end function;
constant MAXMULWIDTH : integer := chooseMaxMulWidth(device);
constant use_2_multipliers : boolean := BW <= 2 * MAXMULWIDTH;
constant use_3_multipliers : boolean := not use_2_multipliers;
component fp_mul2s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
component fp_mul3s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
signal zerovec : STD_LOGIC_VECTOR(MAXMULWIDTH DOWNTO 1);
BEGIN
zerovec <= (others => '0');
gen2mul: IF use_2_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := BW - BLW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal adderff : STD_LOGIC_VECTOR(RW DOWNTO 1);
BEGIN
ml: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff <= (zerovec(RW-(BLW+AW) DOWNTO 1) & multiplier_low) +
(multiplier_high & zerovec(RW-(BHW+AW) DOWNTO 1));
END IF;
END IF;
END PROCESS;
result <= adderff;
END GENERATE;
gen3mul: IF use_3_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := MAXMULWIDTH;
constant BTW : integer := BW - BLW - BHW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal multiplier_top : STD_LOGIC_VECTOR(BTW+AW DOWNTO 1);
signal adderff0 : STD_LOGIC_VECTOR (RW DOWNTO 1);
signal adderff1 : STD_LOGIC_VECTOR (RW DOWNTO 1);
BEGIN
ml: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
mt: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BTW,widthcc=>BTW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BTW+BHW+BLW DOWNTO BHW+BLW+1),
result=>multiplier_top);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff0 <= (others => '0');
adderff1 <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff0 <= (multiplier_top & zerovec(RW-(BTW+AW)-(BLW+AW) DOWNTO 1) & multiplier_low) +
(zerovec(RW-(BHW+AW)-BLW DOWNTO 1) & multiplier_high & zerovec(BLW DOWNTO 1));
adderff1 <= adderff0;
END IF;
END IF;
END PROCESS;
result <= adderff1;
END GENERATE;
END SYN;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for constant arrays access
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constant_array_pkg.all;
entity constant_array is
port (index : in std_logic_vector(2 downto 0);
output : out std_logic_vector(7 downto 0));
end entity constant_array;
architecture test of constant_array is
type logic_array is array (integer range <>) of std_logic_vector(0 to 3);
constant test_array : logic_array(0 to 5) :=
(0 => "0010",
1 => "1000",
2 => "0100",
3 => "0110",
4 => "0101",
5 => "1100");
-- Check if constant vectors are not broken with the changes
constant vector : std_logic_vector(5 downto 0) := "110011";
signal test_a : unsigned(7 downto 0);
signal test_b : std_logic_vector(3 downto 0);
signal test_c : std_logic_vector(2 downto 0);
signal test_d : std_logic;
begin
test_a <= const_array(3);
test_b <= test_array(2);
test_c <= vector(4 downto 2);
test_d <= vector(5);
process (index)
begin
output <= const_array(to_integer(unsigned(index)));
end process;
end architecture test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for constant arrays access
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constant_array_pkg.all;
entity constant_array is
port (index : in std_logic_vector(2 downto 0);
output : out std_logic_vector(7 downto 0));
end entity constant_array;
architecture test of constant_array is
type logic_array is array (integer range <>) of std_logic_vector(0 to 3);
constant test_array : logic_array(0 to 5) :=
(0 => "0010",
1 => "1000",
2 => "0100",
3 => "0110",
4 => "0101",
5 => "1100");
-- Check if constant vectors are not broken with the changes
constant vector : std_logic_vector(5 downto 0) := "110011";
signal test_a : unsigned(7 downto 0);
signal test_b : std_logic_vector(3 downto 0);
signal test_c : std_logic_vector(2 downto 0);
signal test_d : std_logic;
begin
test_a <= const_array(3);
test_b <= test_array(2);
test_c <= vector(4 downto 2);
test_d <= vector(5);
process (index)
begin
output <= const_array(to_integer(unsigned(index)));
end process;
end architecture test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for constant arrays access
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constant_array_pkg.all;
entity constant_array is
port (index : in std_logic_vector(2 downto 0);
output : out std_logic_vector(7 downto 0));
end entity constant_array;
architecture test of constant_array is
type logic_array is array (integer range <>) of std_logic_vector(0 to 3);
constant test_array : logic_array(0 to 5) :=
(0 => "0010",
1 => "1000",
2 => "0100",
3 => "0110",
4 => "0101",
5 => "1100");
-- Check if constant vectors are not broken with the changes
constant vector : std_logic_vector(5 downto 0) := "110011";
signal test_a : unsigned(7 downto 0);
signal test_b : std_logic_vector(3 downto 0);
signal test_c : std_logic_vector(2 downto 0);
signal test_d : std_logic;
begin
test_a <= const_array(3);
test_b <= test_array(2);
test_c <= vector(4 downto 2);
test_d <= vector(5);
process (index)
begin
output <= const_array(to_integer(unsigned(index)));
end process;
end architecture test;
|
entity sub is
generic (l : natural);
port (a : out bit;
b : bit_vector (0 to 3);
c : bit_vector (0 to l - 1));
end sub;
architecture behav of sub is
begin
a <= b (0) xor c (0);
end behav;
entity tb is
end tb;
architecture behav of tb is
signal a : bit;
signal b: bit_vector (0 to 3);
signal c: bit_vector (0 to 7);
type state is (S0, S1, S_done);
signal s : state := S0;
begin
my_sub: entity work.sub
generic map (l => c'length)
port map (a => a, b => b, c => c);
process
begin
wait for 1 ns;
assert a = '0';
b <= x"0";
c <= x"80";
s <= s1;
wait for 1 ns;
assert a = '1';
s <= S_done;
wait for 1 ns;
wait;
end process;
end behav;
|
entity sub is
generic (l : natural);
port (a : out bit;
b : bit_vector (0 to 3);
c : bit_vector (0 to l - 1));
end sub;
architecture behav of sub is
begin
a <= b (0) xor c (0);
end behav;
entity tb is
end tb;
architecture behav of tb is
signal a : bit;
signal b: bit_vector (0 to 3);
signal c: bit_vector (0 to 7);
type state is (S0, S1, S_done);
signal s : state := S0;
begin
my_sub: entity work.sub
generic map (l => c'length)
port map (a => a, b => b, c => c);
process
begin
wait for 1 ns;
assert a = '0';
b <= x"0";
c <= x"80";
s <= s1;
wait for 1 ns;
assert a = '1';
s <= S_done;
wait for 1 ns;
wait;
end process;
end behav;
|
--library IEEE;
--use IEEE.std_logic_1164.all;
entity ANDGATE is
port (
I1 : in bit;
I2 : in bit;
O : out bit);
end entity ANDGATE;
architecture RTL of ANDGATE is
-- signal I1, I2, O : bit := '0';
begin
O <= I1 and I2;
end architecture RTL; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity taint is
generic (
COUNT: integer := 16
);
port (
clk: in std_logic;
rst: in std_logic;
req1_en: in std_logic;
req1_r: in regaddress_type;
req2_en: in std_logic;
req2_r: in regaddress_type;
ready: out std_logic;
set_en: in std_logic;
set_r: in regaddress_type;
clr_en: in std_logic;
clr_r: in regaddress_type;
taint: out std_logic_vector(COUNT-1 downto 0)
);
end taint;
architecture behave of taint is
signal t: std_logic_vector(COUNT-1 downto 0);
signal req1_ok: std_logic;
signal req2_ok: std_logic;
begin
process(req1_en, req1_r, clr_en, clr_r)
variable idx: integer range 0 to COUNT-1;
begin
if req1_en='0' then
req1_ok<='1';
else
idx := to_integer(unsigned(req1_r));
if clr_en='1' and clr_r=req1_r then
req1_ok <= '1';
else
req1_ok <= t(idx);
end if;
end if;
end process;
process(req2_en, req2_r, clr_en, clr_r)
variable idx: integer range 0 to COUNT-1;
begin
if req2_en='0' then
req2_ok<='1';
else
idx := to_integer(unsigned(req2_r));
if clr_en='1' and clr_r=req2_r then
req2_ok <= '1';
else
req2_ok <= t(idx);
end if;
end if;
end process;
ready <= req1_ok and req2_ok;
process(clk)
variable idxs,idxc: integer range 0 to COUNT-1;
begin
if rising_edge(clk) then
if rst='1' then
t <= (others => '1');
else
idxs := to_integer(unsigned(set_r));
idxc := to_integer(unsigned(clr_r));
if set_en='1' then
t(idxs) <= '0';
end if;
if clr_en='1' then
t(idxc) <= '1';
end if;
end if;
end if;
end process;
end behave; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
library work;
use work.i2c_arb_pkg.all;
ENTITY testbench_i2c_arbiter_ss_detector IS
END testbench_i2c_arbiter_ss_detector;
ARCHITECTURE behavior OF testbench_i2c_arbiter_ss_detector IS
signal clk : std_logic := '0';
signal reset : std_logic := '1'; -- low-level active
constant clk_period : time := 16 ns; -- 62.5 MHz
signal input_sda_i : std_logic;
signal input_scl_i : std_logic;
signal start_ack : std_logic;
signal stop_ack : std_logic;
signal start_state : std_logic;
signal stop_state : std_logic;
BEGIN
uut: i2c_arbiter_ss_detector
port map (
clk_i => clk,
rst_n_i => reset,
input_sda_i => input_sda_i,
input_scl_i => input_scl_i,
start_ack_i => start_ack,
stop_ack_i => stop_ack,
start_state_o => start_state,
stop_state_o => stop_state
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <='0'; -- reset!
wait for 3 ns;
reset <='1';
input_sda_i <= '1';
input_scl_i <= '1';
start_ack <= '0';
stop_ack <= '0';
wait for 250 ns;
input_sda_i <= '0';
wait for 250ns;
input_scl_i <= '0';
wait for 250 ns;
start_ack <= '1';
input_scl_i <= '1';
wait for 250 ns;
input_scl_i <= '0';
start_ack <= '0';
wait for 250 ns;
input_scl_i <= '1';
wait for 250 ns;
input_scl_i <= '0';
wait for 250 ns;
input_scl_i <= '1';
wait for 250 ns;
input_sda_i <= '1';
wait for 100 ns;
stop_ack <= '1';
wait for 30 ns;
stop_ack <= '0';
wait;
end process;
END;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity fg_18_06 is
end entity fg_18_06;
architecture test of fg_18_06 is
begin
-- code from book
stimulus_generator : process is
type directory_file is file of string;
file directory : directory_file open read_mode is "stimulus-directory";
variable file_name : string(1 to 50);
variable file_name_length : natural;
variable open_status : file_open_status;
subtype stimulus_vector is std_logic_vector(0 to 9);
type stimulus_file is file of stimulus_vector;
file stimuli : stimulus_file;
variable current_stimulus : stimulus_vector;
-- . . .
begin
file_loop : while not endfile(directory) loop
read( directory, file_name, file_name_length );
if file_name_length > file_name'length then
report "file name too long: " & file_name & "... - file skipped"
severity warning;
next file_loop;
end if;
file_open ( open_status, stimuli,
file_name(1 to file_name_length), read_mode );
if open_status /= open_ok then
report file_open_status'image(open_status) & " while opening file "
& file_name(1 to file_name_length) & " - file skipped"
severity warning;
next file_loop;
end if;
stimulus_loop : while not endfile(stimuli) loop
read(stimuli, current_stimulus);
-- . . . -- apply the stimulus
end loop stimulus_loop;
file_close(stimuli);
end loop file_loop;
wait;
end process stimulus_generator;
-- end code from book
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity fg_18_06 is
end entity fg_18_06;
architecture test of fg_18_06 is
begin
-- code from book
stimulus_generator : process is
type directory_file is file of string;
file directory : directory_file open read_mode is "stimulus-directory";
variable file_name : string(1 to 50);
variable file_name_length : natural;
variable open_status : file_open_status;
subtype stimulus_vector is std_logic_vector(0 to 9);
type stimulus_file is file of stimulus_vector;
file stimuli : stimulus_file;
variable current_stimulus : stimulus_vector;
-- . . .
begin
file_loop : while not endfile(directory) loop
read( directory, file_name, file_name_length );
if file_name_length > file_name'length then
report "file name too long: " & file_name & "... - file skipped"
severity warning;
next file_loop;
end if;
file_open ( open_status, stimuli,
file_name(1 to file_name_length), read_mode );
if open_status /= open_ok then
report file_open_status'image(open_status) & " while opening file "
& file_name(1 to file_name_length) & " - file skipped"
severity warning;
next file_loop;
end if;
stimulus_loop : while not endfile(stimuli) loop
read(stimuli, current_stimulus);
-- . . . -- apply the stimulus
end loop stimulus_loop;
file_close(stimuli);
end loop file_loop;
wait;
end process stimulus_generator;
-- end code from book
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity fg_18_06 is
end entity fg_18_06;
architecture test of fg_18_06 is
begin
-- code from book
stimulus_generator : process is
type directory_file is file of string;
file directory : directory_file open read_mode is "stimulus-directory";
variable file_name : string(1 to 50);
variable file_name_length : natural;
variable open_status : file_open_status;
subtype stimulus_vector is std_logic_vector(0 to 9);
type stimulus_file is file of stimulus_vector;
file stimuli : stimulus_file;
variable current_stimulus : stimulus_vector;
-- . . .
begin
file_loop : while not endfile(directory) loop
read( directory, file_name, file_name_length );
if file_name_length > file_name'length then
report "file name too long: " & file_name & "... - file skipped"
severity warning;
next file_loop;
end if;
file_open ( open_status, stimuli,
file_name(1 to file_name_length), read_mode );
if open_status /= open_ok then
report file_open_status'image(open_status) & " while opening file "
& file_name(1 to file_name_length) & " - file skipped"
severity warning;
next file_loop;
end if;
stimulus_loop : while not endfile(stimuli) loop
read(stimuli, current_stimulus);
-- . . . -- apply the stimulus
end loop stimulus_loop;
file_close(stimuli);
end loop file_loop;
wait;
end process stimulus_generator;
-- end code from book
end architecture test;
|
--------------------------------------------------------------------------------
-- WARNING! --
-- You have entered the Twilight Zone --
-- Beyond this world strange things are known. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lib;
use lib.io.all;
--------------------------------------------------------------------------------
-- VGA MODULE
--------------------------------------------------------------------------------
entity vga_module is
generic (
RX : integer := 160; -- Number of horizontal pixels
RY : integer := 120; -- Number of vertical pixels
NUM_OF_ALIENS : integer := 24 -- Number of enemies
);
port (
clk27M : in std_logic;
reset : in std_logic;
game_state_i : GAME_STATE;
nave_x : integer range 0 to RX; -- ship x coordinate
nave_y : integer range 0 to RY; -- ship y coordinate
nave_d : std_logic; -- ship destroy
tiro_x : integer range 0 to RX; -- shoot x coordinate
tiro_y : integer range 0 to RY; -- shoot y coordinate
tiro_enemy_x : integer range 0 to RX; -- enemy shoot x coordinate
tiro_enemy_y : integer range 0 to RY; -- enemy shoot y coordinate
cpu_e : std_logic_vector(NUM_OF_ALIENS-1 downto 0);
cpu_d : std_logic_vector(NUM_OF_ALIENS-1 downto 0);
cpu_x : pos_arr_xt;
cpu_y : pos_arr_yt;
red, green, blue : out std_logic_vector (3 downto 0);
hsync, vsync : out std_logic
);
end entity;
architecture behavior of vga_module is
component vgacon is
generic (
NUM_HORZ_PIXELS : natural := 128; -- Number of horizontal pixels
NUM_VERT_PIXELS : natural := 96 -- Number of vertical pixels
);
port (
clk27M, rstn : in std_logic;
write_clk, write_enable : in std_logic;
write_addr : in integer range 0 to NUM_HORZ_PIXELS * NUM_VERT_PIXELS - 1;
data_in : in std_logic_vector (2 downto 0);
red, green, blue : out std_logic_vector (3 downto 0);
hsync, vsync : out std_logic
);
end component;
constant CONS_CLOCK_DIV : integer := 400000;
constant HORZ_SIZE : integer := 160;
constant VERT_SIZE : integer := 120;
constant NUM_HORZ_PIXELS1 : integer := 160;
constant NUM_VERT_PIXELS1 : integer := 120;
signal slow_clock : std_logic;
signal video_address : integer range 0 TO HORZ_SIZE * VERT_SIZE - 1;
signal video_word : std_logic_vector (2 downto 0);
signal video_word_s : std_logic_vector (2 downto 0);
-- Sprites
signal inv1, inv2 : std_logic_vector (87 downto 0);
signal dead_player : std_logic_vector (119 downto 0);
signal space_inv : std_logic_vector (1304 downto 0);
signal big_alien : std_logic_vector (2199 downto 0);
signal you_win : std_logic_vector (674 downto 0);
signal game_over : std_logic_vector (872 downto 0);
signal dead_inv : std_logic_vector (87 downto 0);
begin
vga_component: vgacon
generic map (
NUM_HORZ_PIXELS => HORZ_SIZE,
NUM_VERT_PIXELS => VERT_SIZE
) port map (
clk27M => clk27M,
rstn => reset,
write_clk => clk27M,
write_enable => '1',
write_addr => video_address,
data_in => video_word,
red => red,
green => green,
blue => blue,
hsync => hsync,
vsync => vsync
);
-- Clock Divider
clock_divider:
process (clk27M, reset)
variable i : INTEGER := 0;
begin
if (reset = '0') then
i := 0;
slow_clock <= '0';
elsif (rising_edge(clk27M)) then
if (i <= CONS_CLOCK_DIV/2) then
i := i + 1;
slow_clock <= '0';
elsif (i < CONS_CLOCK_DIV-1) then
i := i + 1;
slow_clock <= '1';
else
i := 0;
end if;
end if;
end process;
----------------------------------------
----------------------------------------
-- SPRITES
-- Really, these numbers are sprites!
----------------------------------------
-- Invader
inv1 <= "0001101100010100000101101111111011111111111101101110110001111111000001000100000100000100";
inv2 <= "0100000001000100000100011111111100111111111011101110111101111111011001000100100100000100";
dead_inv <= "1001000100101001010010001000001001100000001100100000100010010100101001000100100000000000";
-- Dead ship (player)
dead_player <= "011111111110101001111111100100100010110101000000000110110000001001000000000000001010100000000000000010000000001000000000";
-- Text: SPACE INVADERS
space_inv <= "111111111001100000110011111111100001111111001100000110000011000000110000011001100000000000001111111110011111111100110000011000000000110011111111111111111100110000011001111111110000111111100110000011000001100000011000001100110000000000000111111111001111111110011000001100000000011001111111111100000000000100001100000000011001100000110011000001100001101100001100000110011000000000000000000001100000000011001100000110000000001100110000000110000000000010000110000000001100110000011001100000110000110110000110000011001100000000000000000000110000000001100110000011000000000110011000000011111111100111111111000001111110011000001100111111111001100000110011000001100110000000000000000111111000000000110011111111100111111111001111111110000000110011000001100000000011001100000110011000001100110000011001100000110011000000000000000000001100000000011001100000110011000001100000000011000000011001100000110000000001100110000011001100000110011000001100110000011001100000000000000000000110000000001100110000011001100000110000000001111111111100111111111001111111110000111111100111111111001100000110011111111100110000000000000111111111001111111110011111111100111111111001111111111111111110011111111100111111111000011111110011111111100110000011001111111110011000000000000011111111100111111111001111111110011111111100111111111";
-- Text: YOU WIN
you_win <= "110000011001111111110011000001100000000000001111111110011111111100000110000110000011001111111110011000001100000000000001111111110011111111100000110000111000011000000100000011110111100000000000001100000110011000001100000110000111000011000000100000011110111100000000000001100000110011000001100000110000110110011000000100000011001001100000000000001100000110011000001100111111111110001111000000100000011000001100000000000001100000110011000001100110000011110001111000000100000011000001100000000000001100000110011000001100110000011110000011001111111110011000001100000000000001100000110011111111100110000011110000011001111111110011000001100000000000001100000110011111111100110000011";
-- Text: GAME OVER
game_over <= "110000011001111111110000011000000111111111000000000000011111111100110000011001100000110011111111111000001100111111111000001100000011111111100000000000001111111110011000001100110000011001111111110010000110000000001100001101100001100000110000000000000000000011001100000110011000001100110000011001000011000000000110000110110000110000011000000000000000000001100110000011001100000110011000001111111111100000111111001100000110011000001100000000000000001111110011011001100111111111001111100111100000110000000001100110000011001100000110000000000000000000011001111011110011000001100000000011110000011000000000110011000001100110000011000000000000000000001100111101111001100000110000000001100111111100111111111001100000110011111111100000000000001111111110011000001100111111111001111111110011111110011111111100110000011001111111110000000000000111111111001100000110011111111100111111111";
-- Big Invader
big_alien <= "0000011111000000000000000000000000000000000001111100000000001111100000000000000000000000000000000000111110000000000111110000000000000000000000000000000000011111000000000011111000000000000000000000000000000000001111100000000001111100000000000000000000000000000000000111110000000000000001111100000000000000000000000001111100000000000000000000111110000000000000000000000000111110000000000000000000011111000000000000000000000000011111000000000000000000001111100000000000000000000000001111100000000000000000000111110000000000000000000000000111110000000000000001111111111111111111111111111111111111111111110000000000111111111111111111111111111111111111111111111000000000011111111111111111111111111111111111111111111100000000001111111111111111111111111111111111111111111110000000000111111111111111111111111111111111111111111111000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000111111111111111000001111111111111111111111111111110000011111111111111100000111111111111111111111111111111000001111111111111110000011111111111111111111111111111100000111111111111111000001111111111111111111111111111110000011111111111111100000111111111111111111110000011111111111111111111111111111111111000001111111111000001111111111111111111111111111111111100000111111111100000111111111111111111111111111111111110000011111111110000011111111111111111111111111111111111000001111111111000001111111111111111111111111111111111100000111111111100000000001111100000000000000011111000000000011111111110000000000111110000000000000001111100000000001111111111000000000011111000000000000000111110000000000111111111100000000001111100000000000000011111000000000011111111110000000000111110000000000000001111100000000001111100000000001111100000000000000000000000001111100000000000000000000111110000000000000000000000000111110000000000000000000011111000000000000000000000000011111000000000000000000001111100000000000000000000000001111100000000000000000000111110000000000000000000000000111110000000000";
vga_fsm:
process (clk27M)
begin
if rising_edge(clk27M) then
case game_state_i is
-- START SCREEN
when START =>
video_word <= "000";
-- Text SPACE INVADERS
if video_address >= 4*HORZ_SIZE AND video_address < (9+4)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= 7 AND (video_address mod HORZ_SIZE) < 145+7 then
video_word <= (OTHERS => space_inv( (video_address mod 160-7) + 145*(video_address/160-4))) ;
end if;
-- Big Invader
elsif video_address >= 40*HORZ_SIZE AND video_address < (40+40)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= 52 AND (video_address mod HORZ_SIZE) < 55+52 then
video_word <= "0" & big_alien( (video_address mod 160-52) + 55*(video_address/160-40)) & "0" ;
end IF;
end if;
video_address <= video_address + 1;
-- GAME OVER SCREEN
when GAME_OVER_STATE =>
video_word <= "000";
-- Text "GAME OVER"
if video_address >= 4*HORZ_SIZE AND video_address < (9+4)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= 32 AND (video_address mod HORZ_SIZE) < 97+32 then
video_word <= (OTHERS => game_over( (video_address mod 160-32) + 97*(video_address/160-4))) ;
end if;
-- Big Invader
elsif video_address >= 40*HORZ_SIZE AND video_address < (40+40)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= 52 AND (video_address mod HORZ_SIZE) < 55+52 then
video_word <= big_alien( (video_address mod 160-52) + 55*(video_address/160-40)) & "00" ;
end if;
end if;
video_address <= video_address + 1;
-- WIN SCREEN
when WIN =>
video_word <= "000";
-- Text YOU WIN
if video_address >= 4*HORZ_SIZE AND video_address < (9+4)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= 42 AND (video_address mod HORZ_SIZE) < 75+42 then
video_word <= (OTHERS => you_win( (video_address mod 160-42) + 75*(video_address/160-4))) ;
end if;
-- Big Invader
elsif video_address >= 40*HORZ_SIZE AND video_address < (40+40)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= 52 AND (video_address mod HORZ_SIZE) < 55+52 then
video_word <= "0" & big_alien( (video_address mod 160-52) + 55*(video_address/160-40)) & "0" ;
end if;
end if;
video_address <= video_address + 1;
when PLAYING =>
video_word <= "000";
video_address <= video_address + 1;
----------------------------------------
-- DRAWS THE PLAYER SHOT
----------------------------------------
if (tiro_x + tiro_y > 0) AND (video_address = (tiro_x + tiro_y*HORZ_SIZE)
OR video_address = (tiro_x + (tiro_y+1)*HORZ_SIZE)
OR video_address = (tiro_x + (tiro_y+2)*HORZ_SIZE)) then
video_word <= "001";
end if;
----------------------------------------
----------------------------------------
-- DRAWS THE PLAYER SHIP
----------------------------------------
if nave_d = '1' then
if video_address >= nave_y*HORZ_SIZE AND video_address < (nave_y+8)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= (nave_x) AND (video_address mod HORZ_SIZE) < nave_x+15 then
video_word <= '0' & dead_player( (video_address mod 160-nave_x) + 15*(video_address/160-nave_y)) & '0' ;
end if;
end if;
else
if video_address >= (nave_y)*HORZ_SIZE AND video_address < (nave_y+2)*HORZ_SIZE then
video_word <= "000";
if (video_address mod HORZ_SIZE) >= (nave_x+4) AND (video_address mod HORZ_SIZE) <= (nave_x+8) then
video_word <= "010";
end if;
elsif video_address >= (nave_y+2)*HORZ_SIZE AND video_address < (nave_y+6)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= (nave_x) AND (video_address mod HORZ_SIZE) <= (nave_x+12) then
video_word <= "010";
end if;
end if;
end if;
----------------------------------------
----------------------------------------
-- DRAWS ENEMY SHIPS
----------------------------------------
for i in NUM_OF_ALIENS-1 downto 0 loop
if video_address >= (cpu_y(i))*HORZ_SIZE and video_address < (cpu_y(i)+8)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= (cpu_x(i)) and (video_address mod HORZ_SIZE) <= (cpu_x(i)+10) then
if cpu_d(i)='1' then
video_word <= (others => dead_inv( (video_address mod 160)-cpu_x(i) + 11*(video_address/160 - cpu_y(i)))) ;
elsif cpu_e(i)='1' then
if (cpu_x(i) rem 2) = 0 then
video_word <= (others => inv1( (video_address mod 160)-cpu_x(i) + 11*(video_address/160 - cpu_y(i)))) ;
else
video_word <= (others => inv2( (video_address mod 160)-cpu_x(i) + 11*(video_address/160 - cpu_y(i)))) ;
end if;
end if;
end if;
end if;
end loop;
----------------------------------------
----------------------------------------
-- DRAWS ENEMY SHOTS
----------------------------------------
if (tiro_enemy_x + tiro_enemy_y > 0) AND (video_address = (tiro_enemy_x + tiro_enemy_y*HORZ_SIZE)
OR video_address = (tiro_enemy_x + (tiro_enemy_y+1)*HORZ_SIZE)) then
video_word <= "100";
end if;
----------------------------------------
when others =>
end case;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- package with component to test on this testbench
use work.fifo_pkg.all;
use work.guarded_fifo_pkg.all;
entity testbench is
end entity;
architecture simulation of testbench is
-- clock generation
constant clk_period : time := 20 ns;
constant clk_fast_period : time := 4 ns;
-- signals to connect to fifo
constant depth : integer := 2; -- the number of fifo entries is 2**depth
constant bit_width : integer := 32; -- number of bits in each entry
signal clk_fast : std_logic;
signal clk : std_logic;
signal rst_fast : std_logic;
signal rst : std_logic;
signal d, q : std_logic_vector ( bit_width-1 downto 0 );
signal push, data_acknowledge : std_logic;
signal full, data_ready : std_logic;
-- the value that is pushed to the fifo
signal ctr : std_logic_vector ( bit_width-1 downto 0 ) := (others => '0');
-- the value that is expected to be read from the fifo (initialized with -1)
signal expected : std_logic_vector ( bit_width-1 downto 0 ) := (others => '0');
begin
-- instantiate device under test (dut)
dut : work.guarded_fifo_pkg.guarded_fifo
generic map (
depth => depth ,
bit_width => bit_width
)
port map (
clk_fast_i => clk_fast,
clk_i => clk,
rst_fast_i => rst_fast,
rst_i => rst,
d_i => ctr,
q_o => q,
push_i => push,
dack_i => data_acknowledge,
full_o => full,
drdy_o => data_ready
);
clk_gen: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
clk_fast_gen: process
begin
wait for 0.567 ns;
for i in 0 to 1000000000 loop
clk_fast <= '0';
wait for clk_fast_period/2;
clk_fast <= '1';
wait for clk_fast_period/2;
end loop;
end process;
rst_initial: process
begin
rst <= '1';
rst_fast <= '1';
wait for clk_period*20;
rst <= '0';
rst_fast <= '0';
wait;
end process;
p_read_write : process
begin
push <= '0';
--=============================
-- fill fifo
--=============================
--wait for clk_period*40.5;
wait until falling_edge(rst);
for i in 0 to 10000 loop
wait until rising_edge(clk_fast);
push <= not push;
end loop;
end process;
p_read: process
begin
data_acknowledge <= '0';
for i in 0 to 10000 loop
wait until data_ready = '1';
wait for clk_period;
data_acknowledge <= '1';
wait for clk_period;
data_acknowledge <= '0';
end loop;
end process;
-- this process increments the counter (that is the value which is written to the fifo)
-- only on rising clock edges when the acknowledge signal was sent back from the fifo, i.e.
-- if a value was successfully pushed into the fifo.
p_increment_ctr : process(clk_fast)
begin
if rising_edge(clk_fast) then
if full = '0' and push = '1' then
ctr <= std_logic_vector(unsigned(ctr) + 1);
end if;
end if;
end process;
end architecture; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc111.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00111ent IS
END c04s03b02x00p29n06i00111ent;
ARCHITECTURE c04s03b02x00p29n06i00111arch OF c04s03b02x00p29n06i00111ent IS
PROCEDURE p1 ( prm_out : OUT INTEGER ) IS
ATTRIBUTE attr1 : INTEGER;
ATTRIBUTE attr1 OF prm_out : VARIABLE IS 300;
BEGIN
ASSERT prm_out'attr1 = 300 REPORT "ERROR: Bad value for prm_out'attr1" SEVERITY FAILURE;
assert NOT(prm_out'attr1 = 300)
report "***PASSED TEST: c04s03b02x00p29n06i00111"
severity NOTE;
assert (prm_out'attr1 = 300)
report "***FAILED TEST: c04s03b02x00p29n06i00111 - Reading of the attributes of the interface element of mode out in a subprogram testing failed."
severity ERROR;
END;
BEGIN
TESTING: PROCESS
VARIABLE tmp : INTEGER;
BEGIN
--
p1 ( tmp );
--
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00111arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc111.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00111ent IS
END c04s03b02x00p29n06i00111ent;
ARCHITECTURE c04s03b02x00p29n06i00111arch OF c04s03b02x00p29n06i00111ent IS
PROCEDURE p1 ( prm_out : OUT INTEGER ) IS
ATTRIBUTE attr1 : INTEGER;
ATTRIBUTE attr1 OF prm_out : VARIABLE IS 300;
BEGIN
ASSERT prm_out'attr1 = 300 REPORT "ERROR: Bad value for prm_out'attr1" SEVERITY FAILURE;
assert NOT(prm_out'attr1 = 300)
report "***PASSED TEST: c04s03b02x00p29n06i00111"
severity NOTE;
assert (prm_out'attr1 = 300)
report "***FAILED TEST: c04s03b02x00p29n06i00111 - Reading of the attributes of the interface element of mode out in a subprogram testing failed."
severity ERROR;
END;
BEGIN
TESTING: PROCESS
VARIABLE tmp : INTEGER;
BEGIN
--
p1 ( tmp );
--
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00111arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc111.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00111ent IS
END c04s03b02x00p29n06i00111ent;
ARCHITECTURE c04s03b02x00p29n06i00111arch OF c04s03b02x00p29n06i00111ent IS
PROCEDURE p1 ( prm_out : OUT INTEGER ) IS
ATTRIBUTE attr1 : INTEGER;
ATTRIBUTE attr1 OF prm_out : VARIABLE IS 300;
BEGIN
ASSERT prm_out'attr1 = 300 REPORT "ERROR: Bad value for prm_out'attr1" SEVERITY FAILURE;
assert NOT(prm_out'attr1 = 300)
report "***PASSED TEST: c04s03b02x00p29n06i00111"
severity NOTE;
assert (prm_out'attr1 = 300)
report "***FAILED TEST: c04s03b02x00p29n06i00111 - Reading of the attributes of the interface element of mode out in a subprogram testing failed."
severity ERROR;
END;
BEGIN
TESTING: PROCESS
VARIABLE tmp : INTEGER;
BEGIN
--
p1 ( tmp );
--
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00111arch;
|
use My_Math_Stuff.MY_STRING_STUFF.my_math_stuff;
use My_Math_Stuff.My_Math_Stuff.my_math_stuff;
use My_Logic_Stuff.my_logic_stuff.MY_MATH_STUFF;
|
use My_Math_Stuff.MY_STRING_STUFF.my_math_stuff;
use My_Math_Stuff.My_Math_Stuff.my_math_stuff;
use My_Logic_Stuff.my_logic_stuff.MY_MATH_STUFF;
|
use My_Math_Stuff.MY_STRING_STUFF.my_math_stuff;
use My_Math_Stuff.My_Math_Stuff.my_math_stuff;
use My_Logic_Stuff.my_logic_stuff.MY_MATH_STUFF;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1295.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01295ent IS
END c08s04b00x00p06n01i01295ent;
ARCHITECTURE c08s04b00x00p06n01i01295arch OF c08s04b00x00p06n01i01295ent IS
signal DID : bit;
BEGIN
TESTING: PROCESS
variable NUM1 : bit;
BEGIN
NUM1 <= DID;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p06n01i01295 - Signal assignment to variable is not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01295arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1295.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01295ent IS
END c08s04b00x00p06n01i01295ent;
ARCHITECTURE c08s04b00x00p06n01i01295arch OF c08s04b00x00p06n01i01295ent IS
signal DID : bit;
BEGIN
TESTING: PROCESS
variable NUM1 : bit;
BEGIN
NUM1 <= DID;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p06n01i01295 - Signal assignment to variable is not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01295arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1295.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01295ent IS
END c08s04b00x00p06n01i01295ent;
ARCHITECTURE c08s04b00x00p06n01i01295arch OF c08s04b00x00p06n01i01295ent IS
signal DID : bit;
BEGIN
TESTING: PROCESS
variable NUM1 : bit;
BEGIN
NUM1 <= DID;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p06n01i01295 - Signal assignment to variable is not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01295arch;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_ch_11_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package ch_11_02 is
-- code from book
type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
function resolved ( s : std_ulogic_vector ) return std_ulogic;
subtype std_logic is resolved std_ulogic;
type std_logic_vector is array ( natural range <>) of std_logic;
subtype X01 is resolved std_ulogic range 'X' to '1'; -- ('X','0','1')
subtype X01Z is resolved std_ulogic range 'X' to 'Z'; -- ('X','0','1','Z')
subtype UX01 is resolved std_ulogic range 'U' to '1'; -- ('U','X','0','1')
subtype UX01Z is resolved std_ulogic range 'U' to 'Z'; -- ('U','X','0','1','Z')
-- end code from book
end package ch_11_02;
package body ch_11_02 is
function resolved ( s : std_ulogic_vector ) return std_ulogic is
begin
end function resolved;
end package body ch_11_02;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_ch_11_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package ch_11_02 is
-- code from book
type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
function resolved ( s : std_ulogic_vector ) return std_ulogic;
subtype std_logic is resolved std_ulogic;
type std_logic_vector is array ( natural range <>) of std_logic;
subtype X01 is resolved std_ulogic range 'X' to '1'; -- ('X','0','1')
subtype X01Z is resolved std_ulogic range 'X' to 'Z'; -- ('X','0','1','Z')
subtype UX01 is resolved std_ulogic range 'U' to '1'; -- ('U','X','0','1')
subtype UX01Z is resolved std_ulogic range 'U' to 'Z'; -- ('U','X','0','1','Z')
-- end code from book
end package ch_11_02;
package body ch_11_02 is
function resolved ( s : std_ulogic_vector ) return std_ulogic is
begin
end function resolved;
end package body ch_11_02;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_ch_11_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package ch_11_02 is
-- code from book
type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
function resolved ( s : std_ulogic_vector ) return std_ulogic;
subtype std_logic is resolved std_ulogic;
type std_logic_vector is array ( natural range <>) of std_logic;
subtype X01 is resolved std_ulogic range 'X' to '1'; -- ('X','0','1')
subtype X01Z is resolved std_ulogic range 'X' to 'Z'; -- ('X','0','1','Z')
subtype UX01 is resolved std_ulogic range 'U' to '1'; -- ('U','X','0','1')
subtype UX01Z is resolved std_ulogic range 'U' to 'Z'; -- ('U','X','0','1','Z')
-- end code from book
end package ch_11_02;
package body ch_11_02 is
function resolved ( s : std_ulogic_vector ) return std_ulogic is
begin
end function resolved;
end package body ch_11_02;
|
--------------------------------------------------------------------------------
-- Title : Demo testbench
-- Project : Automotive Ethernet Gateway, created from Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : demo_tb.vhd
-- -----------------------------------------------------------------------------
-- Description: This testbench will exercise the ports of the MAC core
-- to demonstrate the functionality.
--------------------------------------------------------------------------------
--
-- This testbench performs the following operations:
-- - The MDIO interface will respond to a read request with data to prevent the
-- example design thinking it is real hardware
-- - Four frames are then pushed into the receiver from the PHY
-- interface (GMII):
-- The first is of minimum length (Length/Type = Length = 46 bytes).
-- The second frame sets Length/Type to Type = 0x8000.
-- The third frame has an error inserted.
-- The fourth frame only sends 4 bytes of data: the remainder of the
-- data field is padded up to the minimum frame length i.e. 46 bytes.
-- - These frames are then parsed from the MAC into the MAC's design
-- example. The design example provides a MAC client loopback
-- function so that frames which are received without error will be
-- looped back to the MAC transmitter and transmitted back to the
-- testbench. The testbench verifies that this data matches that
-- previously injected into the receiver.
------------------------------------------------------------------------
-- DEMONSTRATION TESTBENCH |
-- |
-- |
-- ---------------------------------------------- |
-- | TOP LEVEL WRAPPER (DUT) | |
-- | ------------------- ---------------- | |
-- | | USER LOOPBACK | | TRI-MODE | | |
-- | | DESIGN EXAMPLE | | ETHERNET MAC | | |
-- | | | | CORE | | |
-- | | | | | | Monitor |
-- | | ------->|--->| Tx |--------> Frames |
-- | | | | | PHY | | |
-- | | | | | I/F | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | | | | Rx | | |
-- | | | | | PHY | | |
-- | | --------|<---| I/F |<-------- Generate |
-- | | | | | | Frames |
-- | ------------------- ---------------- | |
-- --------------------------------^------------- |
-- | |
-- | |
-- Stimulate |
-- Management I/F |
-- (if present) |
-- |
------------------------------------------------------------------------
entity demo_tb is
end demo_tb;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of demo_tb is
constant GMII_DATA_WIDTH : integer := 8;
constant SWITCH_DATA_WIDTH : integer := 8;
constant RX_STATISTICS_WIDTH : integer := 28;
constant TX_STATISTICS_WIDTH : integer := 32;
constant TX_IFG_DELAY_WIDTH : integer := 8;
constant PAUSE_VAL_WIDTH : integer := 16;
------------------------------------------------------------------------------
-- Component Declaration for Device Under Test (DUT).
------------------------------------------------------------------------------
component automotive_ethernet_gateway
Generic (
GMII_DATA_WIDTH : integer;
SWITCH_DATA_WIDTH : integer;
RX_STATISTICS_WIDTH : integer;
TX_STATISTICS_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- Serialised statistics vectors
--------------------------------
tx_statistics_s : out std_logic;
rx_statistics_s : out std_logic;
-- Serialised Pause interface controls
--------------------------------------
pause_req_s : in std_logic;
-- Main example design controls
-------------------------------
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_response : out std_logic;
enable_phy_loopback : in std_logic;
reset_error : in std_logic
);
end component;
------------------------------------------------------------------------------
-- types to support frame data
------------------------------------------------------------------------------
-- Tx Data and Data_valid record
type data_typ is record
data : bit_vector(7 downto 0); -- data
valid : bit; -- data_valid
error : bit; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
-- Tx Data, Data_valid and underrun record
type tri_mode_ethernet_mac_0_frame_typ is record
columns : frame_of_data_typ(0 to 65);-- data field
bad_frame : boolean; -- does this frame contain an error?
end record;
type frame_typ_ary is array (natural range <>) of tri_mode_ethernet_mac_0_frame_typ;
------------------------------------------------------------------------------
-- Stimulus - Frame data
------------------------------------------------------------------------------
-- The following constant holds the stimulus for the testbench. It is
-- an ordered array of frames, with frame 0 the first to be injected
-- into the core transmit interface by the testbench.
------------------------------------------------------------------------------
constant frame_data : frame_typ_ary := (
-------------
-- Frame 0
-------------
0 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- Length/Type = Length = 46
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"04", VALID => '1', ERROR => '0'),
18 => ( DATA => X"05", VALID => '1', ERROR => '0'),
19 => ( DATA => X"06", VALID => '1', ERROR => '0'),
20 => ( DATA => X"07", VALID => '1', ERROR => '0'),
21 => ( DATA => X"08", VALID => '1', ERROR => '0'),
22 => ( DATA => X"09", VALID => '1', ERROR => '0'),
23 => ( DATA => X"0A", VALID => '1', ERROR => '0'),
24 => ( DATA => X"0B", VALID => '1', ERROR => '0'),
25 => ( DATA => X"0C", VALID => '1', ERROR => '0'),
26 => ( DATA => X"0D", VALID => '1', ERROR => '0'),
27 => ( DATA => X"0E", VALID => '1', ERROR => '0'),
28 => ( DATA => X"0F", VALID => '1', ERROR => '0'),
29 => ( DATA => X"10", VALID => '1', ERROR => '0'),
30 => ( DATA => X"11", VALID => '1', ERROR => '0'),
31 => ( DATA => X"12", VALID => '1', ERROR => '0'),
32 => ( DATA => X"13", VALID => '1', ERROR => '0'),
33 => ( DATA => X"14", VALID => '1', ERROR => '0'),
34 => ( DATA => X"15", VALID => '1', ERROR => '0'),
35 => ( DATA => X"16", VALID => '1', ERROR => '0'),
36 => ( DATA => X"17", VALID => '1', ERROR => '0'),
37 => ( DATA => X"18", VALID => '1', ERROR => '0'),
38 => ( DATA => X"19", VALID => '1', ERROR => '0'),
39 => ( DATA => X"1A", VALID => '1', ERROR => '0'),
40 => ( DATA => X"1B", VALID => '1', ERROR => '0'),
41 => ( DATA => X"1C", VALID => '1', ERROR => '0'),
42 => ( DATA => X"1D", VALID => '1', ERROR => '0'),
43 => ( DATA => X"1E", VALID => '1', ERROR => '0'),
44 => ( DATA => X"1F", VALID => '1', ERROR => '0'),
45 => ( DATA => X"20", VALID => '1', ERROR => '0'),
46 => ( DATA => X"21", VALID => '1', ERROR => '0'),
47 => ( DATA => X"22", VALID => '1', ERROR => '0'),
48 => ( DATA => X"23", VALID => '1', ERROR => '0'),
49 => ( DATA => X"24", VALID => '1', ERROR => '0'),
50 => ( DATA => X"25", VALID => '1', ERROR => '0'),
51 => ( DATA => X"26", VALID => '1', ERROR => '0'),
52 => ( DATA => X"27", VALID => '1', ERROR => '0'),
53 => ( DATA => X"28", VALID => '1', ERROR => '0'),
54 => ( DATA => X"29", VALID => '1', ERROR => '0'),
55 => ( DATA => X"2A", VALID => '1', ERROR => '0'),
56 => ( DATA => X"2B", VALID => '1', ERROR => '0'),
57 => ( DATA => X"2C", VALID => '1', ERROR => '0'),
58 => ( DATA => X"2D", VALID => '1', ERROR => '0'),
59 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- 46th Byte of Data
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 1
-------------
1 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"80", VALID => '1', ERROR => '0'), -- Length/Type = Type = 8000
13 => ( DATA => X"00", VALID => '1', ERROR => '0'),
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"04", VALID => '1', ERROR => '0'),
18 => ( DATA => X"05", VALID => '1', ERROR => '0'),
19 => ( DATA => X"06", VALID => '1', ERROR => '0'),
20 => ( DATA => X"07", VALID => '1', ERROR => '0'),
21 => ( DATA => X"08", VALID => '1', ERROR => '0'),
22 => ( DATA => X"09", VALID => '1', ERROR => '0'),
23 => ( DATA => X"0A", VALID => '1', ERROR => '0'),
24 => ( DATA => X"0B", VALID => '1', ERROR => '0'),
25 => ( DATA => X"0C", VALID => '1', ERROR => '0'),
26 => ( DATA => X"0D", VALID => '1', ERROR => '0'),
27 => ( DATA => X"0E", VALID => '1', ERROR => '0'),
28 => ( DATA => X"0F", VALID => '1', ERROR => '0'),
29 => ( DATA => X"10", VALID => '1', ERROR => '0'),
30 => ( DATA => X"11", VALID => '1', ERROR => '0'),
31 => ( DATA => X"12", VALID => '1', ERROR => '0'),
32 => ( DATA => X"13", VALID => '1', ERROR => '0'),
33 => ( DATA => X"14", VALID => '1', ERROR => '0'),
34 => ( DATA => X"15", VALID => '1', ERROR => '0'),
35 => ( DATA => X"16", VALID => '1', ERROR => '0'),
36 => ( DATA => X"17", VALID => '1', ERROR => '0'),
37 => ( DATA => X"18", VALID => '1', ERROR => '0'),
38 => ( DATA => X"19", VALID => '1', ERROR => '0'),
39 => ( DATA => X"1A", VALID => '1', ERROR => '0'),
40 => ( DATA => X"1B", VALID => '1', ERROR => '0'),
41 => ( DATA => X"1C", VALID => '1', ERROR => '0'),
42 => ( DATA => X"1D", VALID => '1', ERROR => '0'),
43 => ( DATA => X"1E", VALID => '1', ERROR => '0'),
44 => ( DATA => X"1F", VALID => '1', ERROR => '0'),
45 => ( DATA => X"20", VALID => '1', ERROR => '0'),
46 => ( DATA => X"21", VALID => '1', ERROR => '0'),
47 => ( DATA => X"22", VALID => '1', ERROR => '0'),
48 => ( DATA => X"23", VALID => '1', ERROR => '0'),
49 => ( DATA => X"24", VALID => '1', ERROR => '0'),
50 => ( DATA => X"25", VALID => '1', ERROR => '0'),
51 => ( DATA => X"26", VALID => '1', ERROR => '0'),
52 => ( DATA => X"27", VALID => '1', ERROR => '0'),
53 => ( DATA => X"28", VALID => '1', ERROR => '0'),
54 => ( DATA => X"29", VALID => '1', ERROR => '0'),
55 => ( DATA => X"2A", VALID => '1', ERROR => '0'),
56 => ( DATA => X"2B", VALID => '1', ERROR => '0'),
57 => ( DATA => X"2C", VALID => '1', ERROR => '0'),
58 => ( DATA => X"2D", VALID => '1', ERROR => '0'),
59 => ( DATA => X"2E", VALID => '1', ERROR => '0'),
60 => ( DATA => X"2F", VALID => '1', ERROR => '0'), -- 47th Data byte
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2
-------------
2 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- Length/Type = Length = 46
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"00", VALID => '1', ERROR => '0'),
18 => ( DATA => X"00", VALID => '1', ERROR => '0'),
19 => ( DATA => X"00", VALID => '1', ERROR => '0'),
20 => ( DATA => X"00", VALID => '1', ERROR => '0'),
21 => ( DATA => X"00", VALID => '1', ERROR => '0'),
22 => ( DATA => X"00", VALID => '1', ERROR => '0'),
23 => ( DATA => X"00", VALID => '1', ERROR => '1'), -- Error asserted
24 => ( DATA => X"00", VALID => '1', ERROR => '0'),
25 => ( DATA => X"00", VALID => '1', ERROR => '0'),
26 => ( DATA => X"00", VALID => '1', ERROR => '0'),
27 => ( DATA => X"00", VALID => '1', ERROR => '0'),
28 => ( DATA => X"00", VALID => '1', ERROR => '0'),
29 => ( DATA => X"00", VALID => '1', ERROR => '0'),
30 => ( DATA => X"00", VALID => '1', ERROR => '0'),
31 => ( DATA => X"00", VALID => '1', ERROR => '0'),
32 => ( DATA => X"00", VALID => '1', ERROR => '0'),
33 => ( DATA => X"00", VALID => '1', ERROR => '0'),
34 => ( DATA => X"00", VALID => '1', ERROR => '0'),
35 => ( DATA => X"00", VALID => '1', ERROR => '0'),
36 => ( DATA => X"00", VALID => '1', ERROR => '0'),
37 => ( DATA => X"00", VALID => '1', ERROR => '0'),
38 => ( DATA => X"00", VALID => '1', ERROR => '0'),
39 => ( DATA => X"00", VALID => '1', ERROR => '0'),
40 => ( DATA => X"00", VALID => '1', ERROR => '0'),
41 => ( DATA => X"00", VALID => '1', ERROR => '0'),
42 => ( DATA => X"00", VALID => '1', ERROR => '0'),
43 => ( DATA => X"00", VALID => '1', ERROR => '0'),
44 => ( DATA => X"00", VALID => '1', ERROR => '0'),
45 => ( DATA => X"00", VALID => '1', ERROR => '0'),
46 => ( DATA => X"00", VALID => '1', ERROR => '0'),
47 => ( DATA => X"00", VALID => '1', ERROR => '0'),
48 => ( DATA => X"00", VALID => '1', ERROR => '0'),
49 => ( DATA => X"00", VALID => '1', ERROR => '0'),
50 => ( DATA => X"00", VALID => '1', ERROR => '0'),
51 => ( DATA => X"00", VALID => '1', ERROR => '0'),
52 => ( DATA => X"00", VALID => '1', ERROR => '0'),
53 => ( DATA => X"00", VALID => '1', ERROR => '0'),
54 => ( DATA => X"00", VALID => '1', ERROR => '0'),
55 => ( DATA => X"00", VALID => '1', ERROR => '0'),
56 => ( DATA => X"00", VALID => '1', ERROR => '0'),
57 => ( DATA => X"00", VALID => '1', ERROR => '0'),
58 => ( DATA => X"00", VALID => '1', ERROR => '0'),
59 => ( DATA => X"00", VALID => '1', ERROR => '0'),
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- Error this frame
bad_frame => true),
-------------
-- Frame 3
-------------
3 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"03", VALID => '1', ERROR => '0'), -- Length/Type = Length = 03
14 => ( DATA => X"01", VALID => '1', ERROR => '0'), -- Therefore padding is required
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- Padding starts here
18 => ( DATA => X"00", VALID => '1', ERROR => '0'),
19 => ( DATA => X"00", VALID => '1', ERROR => '0'),
20 => ( DATA => X"00", VALID => '1', ERROR => '0'),
21 => ( DATA => X"00", VALID => '1', ERROR => '0'),
22 => ( DATA => X"00", VALID => '1', ERROR => '0'),
23 => ( DATA => X"00", VALID => '1', ERROR => '0'),
24 => ( DATA => X"00", VALID => '1', ERROR => '0'),
25 => ( DATA => X"00", VALID => '1', ERROR => '0'),
26 => ( DATA => X"00", VALID => '1', ERROR => '0'),
27 => ( DATA => X"00", VALID => '1', ERROR => '0'),
28 => ( DATA => X"00", VALID => '1', ERROR => '0'),
29 => ( DATA => X"00", VALID => '1', ERROR => '0'),
30 => ( DATA => X"00", VALID => '1', ERROR => '0'),
31 => ( DATA => X"00", VALID => '1', ERROR => '0'),
32 => ( DATA => X"00", VALID => '1', ERROR => '0'),
33 => ( DATA => X"00", VALID => '1', ERROR => '0'),
34 => ( DATA => X"00", VALID => '1', ERROR => '0'),
35 => ( DATA => X"00", VALID => '1', ERROR => '0'),
36 => ( DATA => X"00", VALID => '1', ERROR => '0'),
37 => ( DATA => X"00", VALID => '1', ERROR => '0'),
38 => ( DATA => X"00", VALID => '1', ERROR => '0'),
39 => ( DATA => X"00", VALID => '1', ERROR => '0'),
40 => ( DATA => X"00", VALID => '1', ERROR => '0'),
41 => ( DATA => X"00", VALID => '1', ERROR => '0'),
42 => ( DATA => X"00", VALID => '1', ERROR => '0'),
43 => ( DATA => X"00", VALID => '1', ERROR => '0'),
44 => ( DATA => X"00", VALID => '1', ERROR => '0'),
45 => ( DATA => X"00", VALID => '1', ERROR => '0'),
46 => ( DATA => X"00", VALID => '1', ERROR => '0'),
47 => ( DATA => X"00", VALID => '1', ERROR => '0'),
48 => ( DATA => X"00", VALID => '1', ERROR => '0'),
49 => ( DATA => X"00", VALID => '1', ERROR => '0'),
50 => ( DATA => X"00", VALID => '1', ERROR => '0'),
51 => ( DATA => X"00", VALID => '1', ERROR => '0'),
52 => ( DATA => X"00", VALID => '1', ERROR => '0'),
53 => ( DATA => X"00", VALID => '1', ERROR => '0'),
54 => ( DATA => X"00", VALID => '1', ERROR => '0'),
55 => ( DATA => X"00", VALID => '1', ERROR => '0'),
56 => ( DATA => X"00", VALID => '1', ERROR => '0'),
57 => ( DATA => X"00", VALID => '1', ERROR => '0'),
58 => ( DATA => X"00", VALID => '1', ERROR => '0'),
59 => ( DATA => X"00", VALID => '1', ERROR => '0'),
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false)
);
------------------------------------------------------------------------------
-- CRC engine
------------------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
------------------------------------------------------------------------------
-- Test Bench signals and constants
------------------------------------------------------------------------------
-- Delay to provide setup and hold timing at the GMII/RGMII.
constant dly : time := 4.8 ns;
constant gtx_period : time := 2.5 ns;
-- testbench signals
signal gtx_clk : std_logic;
signal gtx_clkn : std_logic;
signal reset : std_logic := '0';
signal demo_mode_error : std_logic := '0';
signal mdc : std_logic;
signal mdio : std_logic;
signal mdio_count : unsigned(5 downto 0) := (others => '0');
signal last_mdio : std_logic;
signal mdio_read : std_logic;
signal mdio_addr : std_logic;
signal mdio_fail : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0) := (others => '0');
signal gmii_rx_clk : std_logic;
signal gmii_rx_dv : std_logic := '0';
signal gmii_rx_er : std_logic := '0';
signal gmii_rxd : std_logic_vector(7 downto 0) := (others => '0');
signal mii_tx_clk : std_logic := '0';
signal mii_tx_clk100 : std_logic := '0';
signal mii_tx_clk10 : std_logic := '0';
-- testbench control signals
signal tx_monitor_finished_1G : boolean := false;
signal tx_monitor_finished_10M : boolean := false;
signal tx_monitor_finished_100M : boolean := false;
signal management_config_finished : boolean := false;
signal rx_stimulus_finished : boolean := false;
signal send_complete : std_logic := '0';
signal phy_speed : std_logic_vector(1 downto 0) := "10";
signal mac_speed : std_logic_vector(1 downto 0) := "10";
signal update_speed : std_logic := '0';
signal serial_response : std_logic;
signal enable_phy_loopback : std_logic := '0';
begin
------------------------------------------------------------------------------
-- Wire up Device Under Test
------------------------------------------------------------------------------
dut: automotive_ethernet_gateway
Generic map (
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
SWITCH_DATA_WIDTH => SWITCH_DATA_WIDTH,
RX_STATISTICS_WIDTH => RX_STATISTICS_WIDTH,
TX_STATISTICS_WIDTH => TX_STATISTICS_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH
)
port map (
-- asynchronous reset
--------------------------------
glbl_rst => reset,
-- 200MHz clock input from board
clk_in_p => gtx_clk,
clk_in_n => gtx_clkn,
phy_resetn => open,
-- GMII Interface
--------------------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdc => mdc,
mdio => mdio,
-- Serialised statistics vectors
--------------------------------
tx_statistics_s => open,
rx_statistics_s => open,
-- Serialised Pause interface controls
--------------------------------------
pause_req_s => '0',
-- Main example design controls
-------------------------------
mac_speed => mac_speed,
update_speed => update_speed,
serial_response => serial_response,
enable_phy_loopback => enable_phy_loopback,
reset_error => '0'
);
------------------------------------------------------------------------------
-- If the simulation is still going after delay below
-- then something has gone wrong: terminate with an error
------------------------------------------------------------------------------
p_timebomb : process
begin
wait for 250 us;
assert false
report "ERROR - Simulation running forever!"
severity failure;
end process p_timebomb;
------------------------------------------------------------------------------
-- Simulate the MDIO
------------------------------------------------------------------------------
-- respond with sensible data to mdio reads and accept writes.
-- expect mdio to try and read from reg addr 1 - return all 1's if we don't
-- want any other mdio accesses
-- if any other response then mdio will write to reg_addr 9 then 4 then 0
-- (may check for expected write data?)
-- finally mdio read from reg addr 1 until bit 5 is seen high
-- NOTE - do not check any other bits so could drive all high again..
p_mdio_count : process (mdc, reset)
begin
if (reset = '1') then
mdio_count <= (others => '0');
last_mdio <= '0';
elsif mdc'event and mdc = '1' then
last_mdio <= mdio;
if mdio_count >= "100000" then
mdio_count <= (others => '0');
elsif (mdio_count /= "000000") then
mdio_count <= mdio_count + "000001";
else -- only get here if mdio state is 0 - now look for a start
if mdio = '1' and last_mdio = '0' then
mdio_count <= "000001";
end if;
end if;
end if;
end process p_mdio_count;
mdio <= '1' when (mdio_read = '1' and (mdio_count >= "001110") and (mdio_count <= "011111")) else 'Z';
-- only respond to phy and reg address == 1 (PHY_STATUS)
p_mdio_check : process (mdc, reset)
begin
if (reset = '1') then
mdio_read <= '0';
mdio_addr <= '1'; -- this will go low if the address doesn't match required
mdio_fail <= '0';
elsif mdc'event and mdc = '1' then
if (mdio_count = "000010") then
mdio_addr <= '1'; -- reset at the start of a new access to enable the address to be revalidated
if last_mdio = '1' and mdio = '0' then
mdio_read <= '1';
else -- take a write as a default as won't drive at the wrong time
mdio_read <= '0';
end if;
elsif mdio_count <= "001100" then
-- check the phy_addr is 7 and the reg_addr is 0
if mdio_count <= "000111" and mdio_count >= "000101" then
if (mdio /= '1') then
mdio_addr <= '0';
end if;
else
if (mdio /= '0') then
mdio_addr <= '0';
end if;
end if;
elsif mdio_count = "001110" then
if mdio_read = '0' and (mdio = '1' or last_mdio = '0') then
assert false
report "ERROR - Write TA phase is incorrect" & cr
severity failure;
end if;
elsif (mdio_count >= "001111") and (mdio_count <= "011110") and mdio_addr = '1' then
if (mdio_read = '0') then
if (mdio_count = "010100") then
if (mdio = '1') then
mdio_fail <= '1';
assert false
report "ERROR - Expected bit 10 of mdio write data to be 0" & cr
severity failure;
end if;
else
if (mdio = '0') then
mdio_fail <= '1';
assert false
report "ERROR - Expected all except bit 10 of mdio write data to be 1" & cr
severity failure;
end if;
end if;
end if;
end if;
end if;
end process p_mdio_check;
------------------------------------------------------------------------------
-- Clock drivers
------------------------------------------------------------------------------
-- drives input to an MMCM at 200MHz which creates gtx_clk at 125 MHz
p_gtx_clk : process
begin
gtx_clk <= '0';
gtx_clkn <= '1';
wait for 80 ns;
loop
wait for gtx_period;
gtx_clk <= '1';
gtx_clkn <= '0';
wait for gtx_period;
gtx_clk <= '0';
gtx_clkn <= '1';
end loop;
end process p_gtx_clk;
-- drives mii_tx_clk100 at 25 MHz
p_mii_tx_clk100 : process
begin
mii_tx_clk100 <= '0';
wait for 20 ns;
loop
wait for 20 ns;
mii_tx_clk100 <= '1';
wait for 20 ns;
mii_tx_clk100 <= '0';
end loop;
end process p_mii_tx_clk100;
-- drives mii_tx_clk10 at 2.5 MHz
p_mii_tx_clk10 : process
begin
mii_tx_clk10 <= '0';
wait for 10 ns;
loop
wait for 200 ns;
mii_tx_clk10 <= '1';
wait for 200 ns;
mii_tx_clk10 <= '0';
end loop;
end process p_mii_tx_clk10;
-- Select between 10Mb/s and 100Mb/s MII Tx clock frequencies
p_mii_tx_clk : process(phy_speed, mii_tx_clk100, mii_tx_clk10)
begin
if phy_speed = "11" then
mii_tx_clk <= '0';
elsif phy_speed = "01" then
mii_tx_clk <= mii_tx_clk100;
else
mii_tx_clk <= mii_tx_clk10;
end if;
end process p_mii_tx_clk;
-- Receiver and transmitter clocks are the same in this simulation: connect
-- the appropriate Tx clock source (based on operating speed) to the receiver
-- clock
gmii_rx_clk <= gmii_tx_clk when phy_speed = "10" else mii_tx_clk;
-----------------------------------------------------------------------------
-- Management process. This process sets up the configuration by
-- turning off flow control, and checks gathered statistics at the
-- end of transmission
-----------------------------------------------------------------------------
p_management : process
-- Procedure to reset the MAC
------------------------------
procedure mac_reset is
begin
assert false
report "Resetting core..." & cr
severity note;
reset <= '1';
wait for 400 ns;
reset <= '0';
assert false
report "Timing checks are valid" & cr
severity note;
end procedure mac_reset;
begin -- process p_management
assert false
report "Timing checks are not valid" & cr
severity note;
mac_speed <= "10";
phy_speed <= "10";
update_speed <= '0';
-- reset the core
mac_reset;
wait until mdio_count = "100000";
wait until mdio_count = "000000";
-- Signal that configuration is complete. Other processes will now
-- be allowed to run.
management_config_finished <= true;
-- The stimulus process will now send 4 frames at 1Gb/s.
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
wait;
end process p_management;
------------------------------------------------------------------------------
-- Stimulus process. This process will inject frames of data into the
-- PHY side of the receiver.
------------------------------------------------------------------------------
p_stimulus : process
----------------------------------------------------------
-- Procedure to inject a frame into the receiver at 1Gb/s
----------------------------------------------------------
procedure send_frame_1g (current_frame : in natural) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd <= "01010101" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "11010101" after dly;
gmii_rx_dv <= '1' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := 0;
gmii_rxd <= to_stdlogicvector(frame_data(current_frame).columns(current_col).data) after dly;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after dly;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after dly;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data(current_frame).columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= to_stdlogicvector(frame_data(current_frame).columns(current_col).data) after dly;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after dly;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after dly;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
current_col := current_col + 1;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd <= fcs(((8*j)+7) downto (8*j)) after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after dly;
gmii_rx_dv <= '0' after dly;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
end send_frame_1g;
begin
-- Send four frames through the MAC and Design Exampled
-- at each state Ethernet speed
-- -- frame 0 = minimum length frame
-- -- frame 1 = type frame
-- -- frame 2 = errored frame
-- -- frame 3 = padded frame
-------------------------------------------------------
-- 1 Gb/s speed
-------------------------------------------------------
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
assert false
report "Sending five frames at 1Gb/s..." & cr
severity note;
for current_frame in frame_data'low to frame_data'high loop
send_frame_1g(current_frame);
if current_frame = 3 then
send_complete <= '1';
else
send_complete <= '0';
end if;
end loop;
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
rx_stimulus_finished <= true;
-- Our work here is done
if (demo_mode_error = '0') then
assert false
report "Test completed successfully"
severity note;
end if;
assert false
report "Simulation stopped"
severity failure;
end process p_stimulus;
------------------------------------------------------------------------------
-- Monitor process. This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
------------------------------------------------------------------------------
p_monitor : process
---------------------------------------------------
-- Procedure to check a transmitted frame at 1Gb/s
---------------------------------------------------
procedure check_frame_1g (current_frame : in natural) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable frame_type : string(1 to 4) := (others => ' ');
-- variable frame_filtered : integer := 0;
variable addr_comp_reg : std_logic_vector(95 downto 0);
begin
-- Reset the FCS calculation
fcs := (others => '0');
while current_col < 12 loop
addr_comp_reg((current_col*8 + 7) downto (current_col*8)) := to_stdlogicvector(frame_data(current_frame).columns(current_col).data);
current_col := current_col + 1;
end loop;
current_col := 0;
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "01010101" loop
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "11010101") then
demo_mode_error <= '1';
assert false
report "SFD not present" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
-- Start comparing transmitted data to received data
assert false
report "Comparing Transmitted Data Frames to Received Data Frames" & cr
severity note;
-- frame has started, loop over columns of frame
while ((frame_data(current_frame).columns(current_col).valid)='1') loop
if gmii_tx_en /= to_stdulogic(frame_data(current_frame).columns(current_col).valid) then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect" & cr
severity error;
end if;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 6 then
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Destination Address field" & cr
severity error;
end if;
-- The transmitted Source Address was the Destination Address of the injected frame
elsif current_col >= 6 and current_col < 12 then
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Source Address field" & cr
severity error;
end if;
-- for remainder of frame
else
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
end if;
end if;
-- calculate expected crc for the frame
fcs := calc_crc(gmii_txd, fcs);
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- j
end check_frame_1g;
variable f : tri_mode_ethernet_mac_0_frame_typ; -- temporary frame variable
variable current_frame : natural := 0; -- current frame pointer
begin -- process p_monitor
-- Compare the transmitted frame to the received frames
-- -- frame 0 = minimum length frame
-- -- frame 1 = type frame
-- -- frame 2 = errored frame
-- -- frame 3 = padded frame
-- Repeated for all stated speeds.
-------------------------------------------------------
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until reset'event and reset = '0';
wait until management_config_finished;
wait for 300 ns;
-- 1 Gb/s speed
-------------------------------------------------------
current_frame := 0;
-- Look for 1Gb/s frames.
-- loop over all the frames in the stimulus record
loop
-- If the current frame had an error inserted then it would have been
-- dropped by the FIFO in the design example. Therefore move immediately
-- on to the next frame.
while frame_data(current_frame).bad_frame loop
current_frame := current_frame + 1;
if current_frame = frame_data'high + 1 then
exit;
end if;
end loop;
-- There are only 4 frames in this test.
if current_frame = frame_data'high + 1 then
exit;
end if;
-- Check the current frame
check_frame_1g(current_frame);
-- move to the next frame
if current_frame = frame_data'high then
exit;
else
current_frame := current_frame + 1;
end if;
end loop;
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_1G <= true;
wait;
end process p_monitor;
end behav;
|
--------------------------------------------------------------------------------
-- Title : Demo testbench
-- Project : Automotive Ethernet Gateway, created from Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : demo_tb.vhd
-- -----------------------------------------------------------------------------
-- Description: This testbench will exercise the ports of the MAC core
-- to demonstrate the functionality.
--------------------------------------------------------------------------------
--
-- This testbench performs the following operations:
-- - The MDIO interface will respond to a read request with data to prevent the
-- example design thinking it is real hardware
-- - Four frames are then pushed into the receiver from the PHY
-- interface (GMII):
-- The first is of minimum length (Length/Type = Length = 46 bytes).
-- The second frame sets Length/Type to Type = 0x8000.
-- The third frame has an error inserted.
-- The fourth frame only sends 4 bytes of data: the remainder of the
-- data field is padded up to the minimum frame length i.e. 46 bytes.
-- - These frames are then parsed from the MAC into the MAC's design
-- example. The design example provides a MAC client loopback
-- function so that frames which are received without error will be
-- looped back to the MAC transmitter and transmitted back to the
-- testbench. The testbench verifies that this data matches that
-- previously injected into the receiver.
------------------------------------------------------------------------
-- DEMONSTRATION TESTBENCH |
-- |
-- |
-- ---------------------------------------------- |
-- | TOP LEVEL WRAPPER (DUT) | |
-- | ------------------- ---------------- | |
-- | | USER LOOPBACK | | TRI-MODE | | |
-- | | DESIGN EXAMPLE | | ETHERNET MAC | | |
-- | | | | CORE | | |
-- | | | | | | Monitor |
-- | | ------->|--->| Tx |--------> Frames |
-- | | | | | PHY | | |
-- | | | | | I/F | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | | | | Rx | | |
-- | | | | | PHY | | |
-- | | --------|<---| I/F |<-------- Generate |
-- | | | | | | Frames |
-- | ------------------- ---------------- | |
-- --------------------------------^------------- |
-- | |
-- | |
-- Stimulate |
-- Management I/F |
-- (if present) |
-- |
------------------------------------------------------------------------
entity demo_tb is
end demo_tb;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of demo_tb is
constant GMII_DATA_WIDTH : integer := 8;
constant SWITCH_DATA_WIDTH : integer := 8;
constant RX_STATISTICS_WIDTH : integer := 28;
constant TX_STATISTICS_WIDTH : integer := 32;
constant TX_IFG_DELAY_WIDTH : integer := 8;
constant PAUSE_VAL_WIDTH : integer := 16;
------------------------------------------------------------------------------
-- Component Declaration for Device Under Test (DUT).
------------------------------------------------------------------------------
component automotive_ethernet_gateway
Generic (
GMII_DATA_WIDTH : integer;
SWITCH_DATA_WIDTH : integer;
RX_STATISTICS_WIDTH : integer;
TX_STATISTICS_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- Serialised statistics vectors
--------------------------------
tx_statistics_s : out std_logic;
rx_statistics_s : out std_logic;
-- Serialised Pause interface controls
--------------------------------------
pause_req_s : in std_logic;
-- Main example design controls
-------------------------------
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_response : out std_logic;
enable_phy_loopback : in std_logic;
reset_error : in std_logic
);
end component;
------------------------------------------------------------------------------
-- types to support frame data
------------------------------------------------------------------------------
-- Tx Data and Data_valid record
type data_typ is record
data : bit_vector(7 downto 0); -- data
valid : bit; -- data_valid
error : bit; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
-- Tx Data, Data_valid and underrun record
type tri_mode_ethernet_mac_0_frame_typ is record
columns : frame_of_data_typ(0 to 65);-- data field
bad_frame : boolean; -- does this frame contain an error?
end record;
type frame_typ_ary is array (natural range <>) of tri_mode_ethernet_mac_0_frame_typ;
------------------------------------------------------------------------------
-- Stimulus - Frame data
------------------------------------------------------------------------------
-- The following constant holds the stimulus for the testbench. It is
-- an ordered array of frames, with frame 0 the first to be injected
-- into the core transmit interface by the testbench.
------------------------------------------------------------------------------
constant frame_data : frame_typ_ary := (
-------------
-- Frame 0
-------------
0 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- Length/Type = Length = 46
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"04", VALID => '1', ERROR => '0'),
18 => ( DATA => X"05", VALID => '1', ERROR => '0'),
19 => ( DATA => X"06", VALID => '1', ERROR => '0'),
20 => ( DATA => X"07", VALID => '1', ERROR => '0'),
21 => ( DATA => X"08", VALID => '1', ERROR => '0'),
22 => ( DATA => X"09", VALID => '1', ERROR => '0'),
23 => ( DATA => X"0A", VALID => '1', ERROR => '0'),
24 => ( DATA => X"0B", VALID => '1', ERROR => '0'),
25 => ( DATA => X"0C", VALID => '1', ERROR => '0'),
26 => ( DATA => X"0D", VALID => '1', ERROR => '0'),
27 => ( DATA => X"0E", VALID => '1', ERROR => '0'),
28 => ( DATA => X"0F", VALID => '1', ERROR => '0'),
29 => ( DATA => X"10", VALID => '1', ERROR => '0'),
30 => ( DATA => X"11", VALID => '1', ERROR => '0'),
31 => ( DATA => X"12", VALID => '1', ERROR => '0'),
32 => ( DATA => X"13", VALID => '1', ERROR => '0'),
33 => ( DATA => X"14", VALID => '1', ERROR => '0'),
34 => ( DATA => X"15", VALID => '1', ERROR => '0'),
35 => ( DATA => X"16", VALID => '1', ERROR => '0'),
36 => ( DATA => X"17", VALID => '1', ERROR => '0'),
37 => ( DATA => X"18", VALID => '1', ERROR => '0'),
38 => ( DATA => X"19", VALID => '1', ERROR => '0'),
39 => ( DATA => X"1A", VALID => '1', ERROR => '0'),
40 => ( DATA => X"1B", VALID => '1', ERROR => '0'),
41 => ( DATA => X"1C", VALID => '1', ERROR => '0'),
42 => ( DATA => X"1D", VALID => '1', ERROR => '0'),
43 => ( DATA => X"1E", VALID => '1', ERROR => '0'),
44 => ( DATA => X"1F", VALID => '1', ERROR => '0'),
45 => ( DATA => X"20", VALID => '1', ERROR => '0'),
46 => ( DATA => X"21", VALID => '1', ERROR => '0'),
47 => ( DATA => X"22", VALID => '1', ERROR => '0'),
48 => ( DATA => X"23", VALID => '1', ERROR => '0'),
49 => ( DATA => X"24", VALID => '1', ERROR => '0'),
50 => ( DATA => X"25", VALID => '1', ERROR => '0'),
51 => ( DATA => X"26", VALID => '1', ERROR => '0'),
52 => ( DATA => X"27", VALID => '1', ERROR => '0'),
53 => ( DATA => X"28", VALID => '1', ERROR => '0'),
54 => ( DATA => X"29", VALID => '1', ERROR => '0'),
55 => ( DATA => X"2A", VALID => '1', ERROR => '0'),
56 => ( DATA => X"2B", VALID => '1', ERROR => '0'),
57 => ( DATA => X"2C", VALID => '1', ERROR => '0'),
58 => ( DATA => X"2D", VALID => '1', ERROR => '0'),
59 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- 46th Byte of Data
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 1
-------------
1 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"80", VALID => '1', ERROR => '0'), -- Length/Type = Type = 8000
13 => ( DATA => X"00", VALID => '1', ERROR => '0'),
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"04", VALID => '1', ERROR => '0'),
18 => ( DATA => X"05", VALID => '1', ERROR => '0'),
19 => ( DATA => X"06", VALID => '1', ERROR => '0'),
20 => ( DATA => X"07", VALID => '1', ERROR => '0'),
21 => ( DATA => X"08", VALID => '1', ERROR => '0'),
22 => ( DATA => X"09", VALID => '1', ERROR => '0'),
23 => ( DATA => X"0A", VALID => '1', ERROR => '0'),
24 => ( DATA => X"0B", VALID => '1', ERROR => '0'),
25 => ( DATA => X"0C", VALID => '1', ERROR => '0'),
26 => ( DATA => X"0D", VALID => '1', ERROR => '0'),
27 => ( DATA => X"0E", VALID => '1', ERROR => '0'),
28 => ( DATA => X"0F", VALID => '1', ERROR => '0'),
29 => ( DATA => X"10", VALID => '1', ERROR => '0'),
30 => ( DATA => X"11", VALID => '1', ERROR => '0'),
31 => ( DATA => X"12", VALID => '1', ERROR => '0'),
32 => ( DATA => X"13", VALID => '1', ERROR => '0'),
33 => ( DATA => X"14", VALID => '1', ERROR => '0'),
34 => ( DATA => X"15", VALID => '1', ERROR => '0'),
35 => ( DATA => X"16", VALID => '1', ERROR => '0'),
36 => ( DATA => X"17", VALID => '1', ERROR => '0'),
37 => ( DATA => X"18", VALID => '1', ERROR => '0'),
38 => ( DATA => X"19", VALID => '1', ERROR => '0'),
39 => ( DATA => X"1A", VALID => '1', ERROR => '0'),
40 => ( DATA => X"1B", VALID => '1', ERROR => '0'),
41 => ( DATA => X"1C", VALID => '1', ERROR => '0'),
42 => ( DATA => X"1D", VALID => '1', ERROR => '0'),
43 => ( DATA => X"1E", VALID => '1', ERROR => '0'),
44 => ( DATA => X"1F", VALID => '1', ERROR => '0'),
45 => ( DATA => X"20", VALID => '1', ERROR => '0'),
46 => ( DATA => X"21", VALID => '1', ERROR => '0'),
47 => ( DATA => X"22", VALID => '1', ERROR => '0'),
48 => ( DATA => X"23", VALID => '1', ERROR => '0'),
49 => ( DATA => X"24", VALID => '1', ERROR => '0'),
50 => ( DATA => X"25", VALID => '1', ERROR => '0'),
51 => ( DATA => X"26", VALID => '1', ERROR => '0'),
52 => ( DATA => X"27", VALID => '1', ERROR => '0'),
53 => ( DATA => X"28", VALID => '1', ERROR => '0'),
54 => ( DATA => X"29", VALID => '1', ERROR => '0'),
55 => ( DATA => X"2A", VALID => '1', ERROR => '0'),
56 => ( DATA => X"2B", VALID => '1', ERROR => '0'),
57 => ( DATA => X"2C", VALID => '1', ERROR => '0'),
58 => ( DATA => X"2D", VALID => '1', ERROR => '0'),
59 => ( DATA => X"2E", VALID => '1', ERROR => '0'),
60 => ( DATA => X"2F", VALID => '1', ERROR => '0'), -- 47th Data byte
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2
-------------
2 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- Length/Type = Length = 46
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"00", VALID => '1', ERROR => '0'),
18 => ( DATA => X"00", VALID => '1', ERROR => '0'),
19 => ( DATA => X"00", VALID => '1', ERROR => '0'),
20 => ( DATA => X"00", VALID => '1', ERROR => '0'),
21 => ( DATA => X"00", VALID => '1', ERROR => '0'),
22 => ( DATA => X"00", VALID => '1', ERROR => '0'),
23 => ( DATA => X"00", VALID => '1', ERROR => '1'), -- Error asserted
24 => ( DATA => X"00", VALID => '1', ERROR => '0'),
25 => ( DATA => X"00", VALID => '1', ERROR => '0'),
26 => ( DATA => X"00", VALID => '1', ERROR => '0'),
27 => ( DATA => X"00", VALID => '1', ERROR => '0'),
28 => ( DATA => X"00", VALID => '1', ERROR => '0'),
29 => ( DATA => X"00", VALID => '1', ERROR => '0'),
30 => ( DATA => X"00", VALID => '1', ERROR => '0'),
31 => ( DATA => X"00", VALID => '1', ERROR => '0'),
32 => ( DATA => X"00", VALID => '1', ERROR => '0'),
33 => ( DATA => X"00", VALID => '1', ERROR => '0'),
34 => ( DATA => X"00", VALID => '1', ERROR => '0'),
35 => ( DATA => X"00", VALID => '1', ERROR => '0'),
36 => ( DATA => X"00", VALID => '1', ERROR => '0'),
37 => ( DATA => X"00", VALID => '1', ERROR => '0'),
38 => ( DATA => X"00", VALID => '1', ERROR => '0'),
39 => ( DATA => X"00", VALID => '1', ERROR => '0'),
40 => ( DATA => X"00", VALID => '1', ERROR => '0'),
41 => ( DATA => X"00", VALID => '1', ERROR => '0'),
42 => ( DATA => X"00", VALID => '1', ERROR => '0'),
43 => ( DATA => X"00", VALID => '1', ERROR => '0'),
44 => ( DATA => X"00", VALID => '1', ERROR => '0'),
45 => ( DATA => X"00", VALID => '1', ERROR => '0'),
46 => ( DATA => X"00", VALID => '1', ERROR => '0'),
47 => ( DATA => X"00", VALID => '1', ERROR => '0'),
48 => ( DATA => X"00", VALID => '1', ERROR => '0'),
49 => ( DATA => X"00", VALID => '1', ERROR => '0'),
50 => ( DATA => X"00", VALID => '1', ERROR => '0'),
51 => ( DATA => X"00", VALID => '1', ERROR => '0'),
52 => ( DATA => X"00", VALID => '1', ERROR => '0'),
53 => ( DATA => X"00", VALID => '1', ERROR => '0'),
54 => ( DATA => X"00", VALID => '1', ERROR => '0'),
55 => ( DATA => X"00", VALID => '1', ERROR => '0'),
56 => ( DATA => X"00", VALID => '1', ERROR => '0'),
57 => ( DATA => X"00", VALID => '1', ERROR => '0'),
58 => ( DATA => X"00", VALID => '1', ERROR => '0'),
59 => ( DATA => X"00", VALID => '1', ERROR => '0'),
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- Error this frame
bad_frame => true),
-------------
-- Frame 3
-------------
3 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"03", VALID => '1', ERROR => '0'), -- Length/Type = Length = 03
14 => ( DATA => X"01", VALID => '1', ERROR => '0'), -- Therefore padding is required
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- Padding starts here
18 => ( DATA => X"00", VALID => '1', ERROR => '0'),
19 => ( DATA => X"00", VALID => '1', ERROR => '0'),
20 => ( DATA => X"00", VALID => '1', ERROR => '0'),
21 => ( DATA => X"00", VALID => '1', ERROR => '0'),
22 => ( DATA => X"00", VALID => '1', ERROR => '0'),
23 => ( DATA => X"00", VALID => '1', ERROR => '0'),
24 => ( DATA => X"00", VALID => '1', ERROR => '0'),
25 => ( DATA => X"00", VALID => '1', ERROR => '0'),
26 => ( DATA => X"00", VALID => '1', ERROR => '0'),
27 => ( DATA => X"00", VALID => '1', ERROR => '0'),
28 => ( DATA => X"00", VALID => '1', ERROR => '0'),
29 => ( DATA => X"00", VALID => '1', ERROR => '0'),
30 => ( DATA => X"00", VALID => '1', ERROR => '0'),
31 => ( DATA => X"00", VALID => '1', ERROR => '0'),
32 => ( DATA => X"00", VALID => '1', ERROR => '0'),
33 => ( DATA => X"00", VALID => '1', ERROR => '0'),
34 => ( DATA => X"00", VALID => '1', ERROR => '0'),
35 => ( DATA => X"00", VALID => '1', ERROR => '0'),
36 => ( DATA => X"00", VALID => '1', ERROR => '0'),
37 => ( DATA => X"00", VALID => '1', ERROR => '0'),
38 => ( DATA => X"00", VALID => '1', ERROR => '0'),
39 => ( DATA => X"00", VALID => '1', ERROR => '0'),
40 => ( DATA => X"00", VALID => '1', ERROR => '0'),
41 => ( DATA => X"00", VALID => '1', ERROR => '0'),
42 => ( DATA => X"00", VALID => '1', ERROR => '0'),
43 => ( DATA => X"00", VALID => '1', ERROR => '0'),
44 => ( DATA => X"00", VALID => '1', ERROR => '0'),
45 => ( DATA => X"00", VALID => '1', ERROR => '0'),
46 => ( DATA => X"00", VALID => '1', ERROR => '0'),
47 => ( DATA => X"00", VALID => '1', ERROR => '0'),
48 => ( DATA => X"00", VALID => '1', ERROR => '0'),
49 => ( DATA => X"00", VALID => '1', ERROR => '0'),
50 => ( DATA => X"00", VALID => '1', ERROR => '0'),
51 => ( DATA => X"00", VALID => '1', ERROR => '0'),
52 => ( DATA => X"00", VALID => '1', ERROR => '0'),
53 => ( DATA => X"00", VALID => '1', ERROR => '0'),
54 => ( DATA => X"00", VALID => '1', ERROR => '0'),
55 => ( DATA => X"00", VALID => '1', ERROR => '0'),
56 => ( DATA => X"00", VALID => '1', ERROR => '0'),
57 => ( DATA => X"00", VALID => '1', ERROR => '0'),
58 => ( DATA => X"00", VALID => '1', ERROR => '0'),
59 => ( DATA => X"00", VALID => '1', ERROR => '0'),
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false)
);
------------------------------------------------------------------------------
-- CRC engine
------------------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
------------------------------------------------------------------------------
-- Test Bench signals and constants
------------------------------------------------------------------------------
-- Delay to provide setup and hold timing at the GMII/RGMII.
constant dly : time := 4.8 ns;
constant gtx_period : time := 2.5 ns;
-- testbench signals
signal gtx_clk : std_logic;
signal gtx_clkn : std_logic;
signal reset : std_logic := '0';
signal demo_mode_error : std_logic := '0';
signal mdc : std_logic;
signal mdio : std_logic;
signal mdio_count : unsigned(5 downto 0) := (others => '0');
signal last_mdio : std_logic;
signal mdio_read : std_logic;
signal mdio_addr : std_logic;
signal mdio_fail : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0) := (others => '0');
signal gmii_rx_clk : std_logic;
signal gmii_rx_dv : std_logic := '0';
signal gmii_rx_er : std_logic := '0';
signal gmii_rxd : std_logic_vector(7 downto 0) := (others => '0');
signal mii_tx_clk : std_logic := '0';
signal mii_tx_clk100 : std_logic := '0';
signal mii_tx_clk10 : std_logic := '0';
-- testbench control signals
signal tx_monitor_finished_1G : boolean := false;
signal tx_monitor_finished_10M : boolean := false;
signal tx_monitor_finished_100M : boolean := false;
signal management_config_finished : boolean := false;
signal rx_stimulus_finished : boolean := false;
signal send_complete : std_logic := '0';
signal phy_speed : std_logic_vector(1 downto 0) := "10";
signal mac_speed : std_logic_vector(1 downto 0) := "10";
signal update_speed : std_logic := '0';
signal serial_response : std_logic;
signal enable_phy_loopback : std_logic := '0';
begin
------------------------------------------------------------------------------
-- Wire up Device Under Test
------------------------------------------------------------------------------
dut: automotive_ethernet_gateway
Generic map (
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
SWITCH_DATA_WIDTH => SWITCH_DATA_WIDTH,
RX_STATISTICS_WIDTH => RX_STATISTICS_WIDTH,
TX_STATISTICS_WIDTH => TX_STATISTICS_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH
)
port map (
-- asynchronous reset
--------------------------------
glbl_rst => reset,
-- 200MHz clock input from board
clk_in_p => gtx_clk,
clk_in_n => gtx_clkn,
phy_resetn => open,
-- GMII Interface
--------------------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdc => mdc,
mdio => mdio,
-- Serialised statistics vectors
--------------------------------
tx_statistics_s => open,
rx_statistics_s => open,
-- Serialised Pause interface controls
--------------------------------------
pause_req_s => '0',
-- Main example design controls
-------------------------------
mac_speed => mac_speed,
update_speed => update_speed,
serial_response => serial_response,
enable_phy_loopback => enable_phy_loopback,
reset_error => '0'
);
------------------------------------------------------------------------------
-- If the simulation is still going after delay below
-- then something has gone wrong: terminate with an error
------------------------------------------------------------------------------
p_timebomb : process
begin
wait for 250 us;
assert false
report "ERROR - Simulation running forever!"
severity failure;
end process p_timebomb;
------------------------------------------------------------------------------
-- Simulate the MDIO
------------------------------------------------------------------------------
-- respond with sensible data to mdio reads and accept writes.
-- expect mdio to try and read from reg addr 1 - return all 1's if we don't
-- want any other mdio accesses
-- if any other response then mdio will write to reg_addr 9 then 4 then 0
-- (may check for expected write data?)
-- finally mdio read from reg addr 1 until bit 5 is seen high
-- NOTE - do not check any other bits so could drive all high again..
p_mdio_count : process (mdc, reset)
begin
if (reset = '1') then
mdio_count <= (others => '0');
last_mdio <= '0';
elsif mdc'event and mdc = '1' then
last_mdio <= mdio;
if mdio_count >= "100000" then
mdio_count <= (others => '0');
elsif (mdio_count /= "000000") then
mdio_count <= mdio_count + "000001";
else -- only get here if mdio state is 0 - now look for a start
if mdio = '1' and last_mdio = '0' then
mdio_count <= "000001";
end if;
end if;
end if;
end process p_mdio_count;
mdio <= '1' when (mdio_read = '1' and (mdio_count >= "001110") and (mdio_count <= "011111")) else 'Z';
-- only respond to phy and reg address == 1 (PHY_STATUS)
p_mdio_check : process (mdc, reset)
begin
if (reset = '1') then
mdio_read <= '0';
mdio_addr <= '1'; -- this will go low if the address doesn't match required
mdio_fail <= '0';
elsif mdc'event and mdc = '1' then
if (mdio_count = "000010") then
mdio_addr <= '1'; -- reset at the start of a new access to enable the address to be revalidated
if last_mdio = '1' and mdio = '0' then
mdio_read <= '1';
else -- take a write as a default as won't drive at the wrong time
mdio_read <= '0';
end if;
elsif mdio_count <= "001100" then
-- check the phy_addr is 7 and the reg_addr is 0
if mdio_count <= "000111" and mdio_count >= "000101" then
if (mdio /= '1') then
mdio_addr <= '0';
end if;
else
if (mdio /= '0') then
mdio_addr <= '0';
end if;
end if;
elsif mdio_count = "001110" then
if mdio_read = '0' and (mdio = '1' or last_mdio = '0') then
assert false
report "ERROR - Write TA phase is incorrect" & cr
severity failure;
end if;
elsif (mdio_count >= "001111") and (mdio_count <= "011110") and mdio_addr = '1' then
if (mdio_read = '0') then
if (mdio_count = "010100") then
if (mdio = '1') then
mdio_fail <= '1';
assert false
report "ERROR - Expected bit 10 of mdio write data to be 0" & cr
severity failure;
end if;
else
if (mdio = '0') then
mdio_fail <= '1';
assert false
report "ERROR - Expected all except bit 10 of mdio write data to be 1" & cr
severity failure;
end if;
end if;
end if;
end if;
end if;
end process p_mdio_check;
------------------------------------------------------------------------------
-- Clock drivers
------------------------------------------------------------------------------
-- drives input to an MMCM at 200MHz which creates gtx_clk at 125 MHz
p_gtx_clk : process
begin
gtx_clk <= '0';
gtx_clkn <= '1';
wait for 80 ns;
loop
wait for gtx_period;
gtx_clk <= '1';
gtx_clkn <= '0';
wait for gtx_period;
gtx_clk <= '0';
gtx_clkn <= '1';
end loop;
end process p_gtx_clk;
-- drives mii_tx_clk100 at 25 MHz
p_mii_tx_clk100 : process
begin
mii_tx_clk100 <= '0';
wait for 20 ns;
loop
wait for 20 ns;
mii_tx_clk100 <= '1';
wait for 20 ns;
mii_tx_clk100 <= '0';
end loop;
end process p_mii_tx_clk100;
-- drives mii_tx_clk10 at 2.5 MHz
p_mii_tx_clk10 : process
begin
mii_tx_clk10 <= '0';
wait for 10 ns;
loop
wait for 200 ns;
mii_tx_clk10 <= '1';
wait for 200 ns;
mii_tx_clk10 <= '0';
end loop;
end process p_mii_tx_clk10;
-- Select between 10Mb/s and 100Mb/s MII Tx clock frequencies
p_mii_tx_clk : process(phy_speed, mii_tx_clk100, mii_tx_clk10)
begin
if phy_speed = "11" then
mii_tx_clk <= '0';
elsif phy_speed = "01" then
mii_tx_clk <= mii_tx_clk100;
else
mii_tx_clk <= mii_tx_clk10;
end if;
end process p_mii_tx_clk;
-- Receiver and transmitter clocks are the same in this simulation: connect
-- the appropriate Tx clock source (based on operating speed) to the receiver
-- clock
gmii_rx_clk <= gmii_tx_clk when phy_speed = "10" else mii_tx_clk;
-----------------------------------------------------------------------------
-- Management process. This process sets up the configuration by
-- turning off flow control, and checks gathered statistics at the
-- end of transmission
-----------------------------------------------------------------------------
p_management : process
-- Procedure to reset the MAC
------------------------------
procedure mac_reset is
begin
assert false
report "Resetting core..." & cr
severity note;
reset <= '1';
wait for 400 ns;
reset <= '0';
assert false
report "Timing checks are valid" & cr
severity note;
end procedure mac_reset;
begin -- process p_management
assert false
report "Timing checks are not valid" & cr
severity note;
mac_speed <= "10";
phy_speed <= "10";
update_speed <= '0';
-- reset the core
mac_reset;
wait until mdio_count = "100000";
wait until mdio_count = "000000";
-- Signal that configuration is complete. Other processes will now
-- be allowed to run.
management_config_finished <= true;
-- The stimulus process will now send 4 frames at 1Gb/s.
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
wait;
end process p_management;
------------------------------------------------------------------------------
-- Stimulus process. This process will inject frames of data into the
-- PHY side of the receiver.
------------------------------------------------------------------------------
p_stimulus : process
----------------------------------------------------------
-- Procedure to inject a frame into the receiver at 1Gb/s
----------------------------------------------------------
procedure send_frame_1g (current_frame : in natural) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd <= "01010101" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "11010101" after dly;
gmii_rx_dv <= '1' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := 0;
gmii_rxd <= to_stdlogicvector(frame_data(current_frame).columns(current_col).data) after dly;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after dly;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after dly;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data(current_frame).columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= to_stdlogicvector(frame_data(current_frame).columns(current_col).data) after dly;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after dly;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after dly;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
current_col := current_col + 1;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd <= fcs(((8*j)+7) downto (8*j)) after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after dly;
gmii_rx_dv <= '0' after dly;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
end send_frame_1g;
begin
-- Send four frames through the MAC and Design Exampled
-- at each state Ethernet speed
-- -- frame 0 = minimum length frame
-- -- frame 1 = type frame
-- -- frame 2 = errored frame
-- -- frame 3 = padded frame
-------------------------------------------------------
-- 1 Gb/s speed
-------------------------------------------------------
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
assert false
report "Sending five frames at 1Gb/s..." & cr
severity note;
for current_frame in frame_data'low to frame_data'high loop
send_frame_1g(current_frame);
if current_frame = 3 then
send_complete <= '1';
else
send_complete <= '0';
end if;
end loop;
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
rx_stimulus_finished <= true;
-- Our work here is done
if (demo_mode_error = '0') then
assert false
report "Test completed successfully"
severity note;
end if;
assert false
report "Simulation stopped"
severity failure;
end process p_stimulus;
------------------------------------------------------------------------------
-- Monitor process. This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
------------------------------------------------------------------------------
p_monitor : process
---------------------------------------------------
-- Procedure to check a transmitted frame at 1Gb/s
---------------------------------------------------
procedure check_frame_1g (current_frame : in natural) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable frame_type : string(1 to 4) := (others => ' ');
-- variable frame_filtered : integer := 0;
variable addr_comp_reg : std_logic_vector(95 downto 0);
begin
-- Reset the FCS calculation
fcs := (others => '0');
while current_col < 12 loop
addr_comp_reg((current_col*8 + 7) downto (current_col*8)) := to_stdlogicvector(frame_data(current_frame).columns(current_col).data);
current_col := current_col + 1;
end loop;
current_col := 0;
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "01010101" loop
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "11010101") then
demo_mode_error <= '1';
assert false
report "SFD not present" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
-- Start comparing transmitted data to received data
assert false
report "Comparing Transmitted Data Frames to Received Data Frames" & cr
severity note;
-- frame has started, loop over columns of frame
while ((frame_data(current_frame).columns(current_col).valid)='1') loop
if gmii_tx_en /= to_stdulogic(frame_data(current_frame).columns(current_col).valid) then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect" & cr
severity error;
end if;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 6 then
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Destination Address field" & cr
severity error;
end if;
-- The transmitted Source Address was the Destination Address of the injected frame
elsif current_col >= 6 and current_col < 12 then
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Source Address field" & cr
severity error;
end if;
-- for remainder of frame
else
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
end if;
end if;
-- calculate expected crc for the frame
fcs := calc_crc(gmii_txd, fcs);
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- j
end check_frame_1g;
variable f : tri_mode_ethernet_mac_0_frame_typ; -- temporary frame variable
variable current_frame : natural := 0; -- current frame pointer
begin -- process p_monitor
-- Compare the transmitted frame to the received frames
-- -- frame 0 = minimum length frame
-- -- frame 1 = type frame
-- -- frame 2 = errored frame
-- -- frame 3 = padded frame
-- Repeated for all stated speeds.
-------------------------------------------------------
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until reset'event and reset = '0';
wait until management_config_finished;
wait for 300 ns;
-- 1 Gb/s speed
-------------------------------------------------------
current_frame := 0;
-- Look for 1Gb/s frames.
-- loop over all the frames in the stimulus record
loop
-- If the current frame had an error inserted then it would have been
-- dropped by the FIFO in the design example. Therefore move immediately
-- on to the next frame.
while frame_data(current_frame).bad_frame loop
current_frame := current_frame + 1;
if current_frame = frame_data'high + 1 then
exit;
end if;
end loop;
-- There are only 4 frames in this test.
if current_frame = frame_data'high + 1 then
exit;
end if;
-- Check the current frame
check_frame_1g(current_frame);
-- move to the next frame
if current_frame = frame_data'high then
exit;
else
current_frame := current_frame + 1;
end if;
end loop;
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_1G <= true;
wait;
end process p_monitor;
end behav;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
use work.cpu_or1knd_i5_mmu_inst_pkg.all;
package cpu_mmu_inst_pkg is
subtype cpu_mmu_inst_ctrl_in_type is cpu_or1knd_i5_mmu_inst_ctrl_in_type;
subtype cpu_mmu_inst_ctrl_out_type is cpu_or1knd_i5_mmu_inst_ctrl_out_type;
subtype cpu_mmu_inst_dp_in_type is cpu_or1knd_i5_mmu_inst_dp_in_type;
subtype cpu_mmu_inst_dp_out_type is cpu_or1knd_i5_mmu_inst_dp_out_type;
end package;
|
----------------------------------------------------------------------
-- Project : LeafySan
-- Module : Moisture Sensor Module
-- Authors : Florian Winkler
-- Lust update : 01.09.2017
-- Description : Reads a digital soil moisture sensor through an I2C bus
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity moisture_sensor is
generic (
CYCLE_TICKS : natural := 50000000
);
port(
clock : in std_ulogic;
reset : in std_ulogic;
-- i2c bus
i2c_clk_ctrl : out std_ulogic;
i2c_clk_in : in std_ulogic;
i2c_clk_out : out std_ulogic;
i2c_dat_ctrl : out std_ulogic;
i2c_dat_in : in std_ulogic;
i2c_dat_out : out std_ulogic;
moisture : out unsigned(15 downto 0);
temperature : out unsigned(15 downto 0);
address : out unsigned(6 downto 0);
enabled : in std_ulogic
);
end moisture_sensor;
architecture rtl of moisture_sensor is
component i2c_master is
generic (
GV_SYS_CLOCK_RATE : natural := 50000000;
GV_I2C_CLOCK_RATE : natural := 400000; -- fast mode: 400000 Hz (400 kHz)
GW_SLAVE_ADDR : natural := 7;
GV_MAX_BYTES : natural := 16;
GB_USE_INOUT : boolean := false; -- seperated io signals (ctrl, out, in)
GB_TIMEOUT : boolean := false
);
port (
clock : in std_ulogic;
reset_n : in std_ulogic;
-- separated in / out
i2c_clk_ctrl : out std_ulogic;
i2c_clk_in : in std_ulogic;
i2c_clk_out : out std_ulogic;
-- separated in / out
i2c_dat_ctrl : out std_ulogic;
i2c_dat_in : in std_ulogic;
i2c_dat_out : out std_ulogic;
-- interface
busy : out std_ulogic;
cs : in std_ulogic;
mode : in std_ulogic_vector(1 downto 0); -- 00: only read; 01: only write; 10: first read, second write; 11: first write, second read
slave_addr : in std_ulogic_vector(GW_SLAVE_ADDR - 1 downto 0);
bytes_tx : in unsigned(to_log2(GV_MAX_BYTES + 1) - 1 downto 0);
bytes_rx : in unsigned(to_log2(GV_MAX_BYTES + 1) - 1 downto 0);
tx_data : in std_ulogic_vector(7 downto 0);
tx_data_valid : in std_ulogic;
rx_data_en : in std_ulogic;
rx_data : out std_ulogic_vector(7 downto 0);
rx_data_valid : out std_ulogic;
error : out std_ulogic
);
end component i2c_master;
type moist_state_t is (S_ADDR_SCAN, S_ADDR_REGISTER_BYTE0, S_ADDR_REGISTER_BYTE1, S_ADDR_REGISTER_SEND, S_ADDR_CHECK,
S_ADDR_RESET_BYTE0, S_ADDR_RESET_SEND, S_MST_BOOT_DELAY, S_MST_IDLE, S_MST_REGISTER_BYTE0, S_MST_REGISTER_SEND_BYTE0,
S_MST_READ_DELAY, S_MST_READ_START, S_MST_READ_WAIT, S_MST_READ_BYTES, S_MST_CHECK, S_TMP_REGISTER_BYTE0,
S_TMP_REGISTER_SEND_BYTE0, S_TMP_READ_DELAY, S_TMP_READ_START, S_TMP_READ_WAIT, S_TMP_READ_BYTES, S_TMP_CHECK);
signal moist_state, moist_state_nxt : moist_state_t;
constant MOIST_SLAVE_ADDR : std_ulogic_vector(6 downto 0) := "0100000"; -- 0x20 (default address)
constant SCAN_ADDR_START : unsigned(6 downto 0) := "0001000"; -- 0x08 (lowest available i2c address)
constant SCAN_ADDR_END : unsigned(6 downto 0) := "1110111"; -- 0x77 (highest available i2c address)
-- moisture register addresses
constant MOIST_REG_RESET : std_ulogic_vector(7 downto 0) := "00000110"; -- 0x06
constant MOIST_REG_SLEEP : std_ulogic_vector(7 downto 0) := "00001000"; -- 0x08
constant MOIST_REG_MOISTURE : std_ulogic_vector(7 downto 0) := "00000000"; -- 0x00
constant MOIST_REG_SET_ADDR : std_ulogic_vector(7 downto 0) := "00000001"; -- 0x01
constant MOIST_REG_TEMP : std_ulogic_vector(7 downto 0) := "00000101"; -- 0x05
constant MOIST_VALUES_WIDTH : natural := 2; -- 2 bytes
signal moist_received_cnt, moist_received_cnt_nxt : unsigned(to_log2(MOIST_VALUES_WIDTH + 1) - 1 downto 0);
signal moist_valid, moist_valid_nxt : std_ulogic;
type moist_vals_array is array (natural range <>) of std_ulogic_vector(7 downto 0);
signal moist_vals, moist_vals_nxt : moist_vals_array(0 to MOIST_VALUES_WIDTH - 1);
signal moist_busy : std_ulogic;
constant MOIST_BOOT_DELAY_TICKS : natural := 50000000; -- 1s
constant MOIST_READ_DELAY_TICKS : natural := 1000000; -- 20ms
signal moist_boot_delay_cnt, moist_boot_delay_cnt_nxt : unsigned(to_log2(MOIST_BOOT_DELAY_TICKS) - 1 downto 0);
signal moist_read_delay_cnt, moist_read_delay_cnt_nxt : unsigned(to_log2(MOIST_READ_DELAY_TICKS) - 1 downto 0);
signal scan_addr, scan_addr_nxt : unsigned(6 downto 0);
-- signals of `i2c_master` component
signal i2c_reset_n : std_ulogic;
signal i2c_busy : std_ulogic;
signal i2c_cs : std_ulogic;
signal i2c_mode : std_ulogic_vector(1 downto 0);
signal i2c_slave_addr : std_ulogic_vector(6 downto 0);
signal i2c_bytes_tx : unsigned(4 downto 0);
signal i2c_bytes_rx : unsigned(4 downto 0);
signal i2c_tx_data : std_ulogic_vector(7 downto 0);
signal i2c_tx_data_valid : std_ulogic;
signal i2c_rx_data_en : std_ulogic;
signal i2c_rx_data : std_ulogic_vector(7 downto 0);
signal i2c_rx_data_valid : std_ulogic;
signal i2c_error : std_ulogic;
-- output registers
signal moisture_reg, moisture_reg_nxt : unsigned(15 downto 0);
signal temp_reg, temp_reg_nxt : unsigned(15 downto 0);
-- cycle registers
signal cycle_cnt, cycle_cnt_nxt : unsigned(to_log2(CYCLE_TICKS) - 1 downto 0);
signal cycle_pulse : std_ulogic;
begin
-- configure `i2c_master` signal assignments
i2c_master_inst : i2c_master
generic map (
GV_SYS_CLOCK_RATE => CV_SYS_CLOCK_RATE,
GV_I2C_CLOCK_RATE => 400000, -- fast mode 400kHz
GW_SLAVE_ADDR => 7,
GV_MAX_BYTES => 16,
GB_USE_INOUT => false,
GB_TIMEOUT => false
)
port map (
clock => clock,
reset_n => i2c_reset_n,
i2c_clk_ctrl => i2c_clk_ctrl,
i2c_clk_in => i2c_clk_in,
i2c_clk_out => i2c_clk_out,
i2c_dat_ctrl => i2c_dat_ctrl,
i2c_dat_in => i2c_dat_in,
i2c_dat_out => i2c_dat_out,
busy => i2c_busy,
cs => i2c_cs,
mode => i2c_mode,
slave_addr => i2c_slave_addr,
bytes_tx => i2c_bytes_tx,
bytes_rx => i2c_bytes_rx,
tx_data => i2c_tx_data,
tx_data_valid => i2c_tx_data_valid,
rx_data => i2c_rx_data,
rx_data_valid => i2c_rx_data_valid,
rx_data_en => i2c_rx_data_en,
error => i2c_error
);
-- sequential process
process(clock, reset)
begin
-- "manually" connect i2c_reset_n with the inverse of the reset signal
i2c_reset_n <= not(reset);
if reset = '1' then
moist_state <= S_ADDR_SCAN;
moist_received_cnt <= (others => '0');
moist_valid <= '0';
moist_vals <= (others => (others => '0'));
moist_read_delay_cnt <= (others => '0');
moist_boot_delay_cnt <= (others => '0');
moisture_reg <= (others => '0');
temp_reg <= (others => '0');
cycle_cnt <= (others => '0');
scan_addr <= (others => '0');
elsif rising_edge(clock) then
moist_state <= moist_state_nxt;
moist_received_cnt <= moist_received_cnt_nxt;
moist_valid <= moist_valid_nxt;
moist_vals <= moist_vals_nxt;
moist_read_delay_cnt <= moist_read_delay_cnt_nxt;
moist_boot_delay_cnt <= moist_boot_delay_cnt_nxt;
moisture_reg <= moisture_reg_nxt;
temp_reg <= temp_reg_nxt;
cycle_cnt <= cycle_cnt_nxt;
scan_addr <= scan_addr_nxt;
end if;
end process;
-- generate cycle pulse every second
process(enabled, moist_busy, cycle_cnt)
begin
cycle_pulse <= '0';
cycle_cnt_nxt <= cycle_cnt;
if cycle_cnt = to_unsigned(CYCLE_TICKS - 1, cycle_cnt'length) then
-- reset clock only if sensor isn't busy anymore and main entity enabled the reading process (enabled = '1')
if enabled = '1' and moist_busy = '0' then
-- set pulse to HIGH when the sensor isn't busy anymore
cycle_pulse <= '1';
cycle_cnt_nxt <= (others => '0');
end if;
else
-- increment counter
cycle_cnt_nxt <= cycle_cnt + to_unsigned(1, cycle_cnt'length);
end if;
end process;
process(cycle_pulse, i2c_error, i2c_busy, i2c_rx_data, i2c_rx_data_valid, moist_state, moist_received_cnt, moist_busy, moist_valid, moist_vals, moist_read_delay_cnt, moist_boot_delay_cnt, moisture_reg, temp_reg, scan_addr)
-- variable is used to store the read value temporally
-- it allows us to compare the value to certain constants more easily
variable temp_value : unsigned(23 downto 0) := (others => '0');
begin
-- output values
moisture <= moisture_reg;
temperature <= temp_reg;
address <= scan_addr;
-- hold value by default
moist_state_nxt <= moist_state;
moist_received_cnt_nxt <= moist_received_cnt;
moist_valid_nxt <= moist_valid;
moist_vals_nxt <= moist_vals;
moist_read_delay_cnt_nxt <= moist_read_delay_cnt;
moist_boot_delay_cnt_nxt <= moist_boot_delay_cnt;
scan_addr_nxt <= scan_addr;
moisture_reg_nxt <= moisture_reg;
temp_reg_nxt <= temp_reg;
-- default assignments of `i2c_master` component
i2c_cs <= '0';
i2c_mode <= "00";
i2c_slave_addr <= MOIST_SLAVE_ADDR;
i2c_bytes_rx <= (others => '0');
i2c_bytes_tx <= (others => '0');
i2c_rx_data_en <= '0';
i2c_tx_data_valid <= '0';
i2c_tx_data <= (others => '0');
-- always busy by default
moist_busy <= '1';
case moist_state is
when S_ADDR_SCAN =>
-- wait for cycle pulse to start the scan process
moist_busy <= i2c_busy;
if cycle_pulse = '1' then
-- start with the lowest possible i2c address
scan_addr_nxt <= SCAN_ADDR_START;
moist_state_nxt <= S_ADDR_REGISTER_BYTE0;
end if;
when S_ADDR_REGISTER_BYTE0 =>
-- write "SET_ADDRESS" register address to tx fifo
i2c_tx_data <= MOIST_REG_SET_ADDR;
i2c_tx_data_valid <= '1';
moist_state_nxt <= S_ADDR_REGISTER_BYTE1;
when S_ADDR_REGISTER_BYTE1 =>
-- write new address (0x20) to tx fifo
i2c_tx_data <= "0" & MOIST_SLAVE_ADDR; -- add "0" because slave address has a bit width of 7 elements only
i2c_tx_data_valid <= '1';
moist_state_nxt <= S_ADDR_REGISTER_SEND;
when S_ADDR_REGISTER_SEND =>
if i2c_busy = '0' then
-- start transmission
i2c_cs <= '1';
i2c_mode <= "01"; -- write only
i2c_slave_addr <= std_ulogic_vector(scan_addr); -- write to current slave address
i2c_bytes_tx <= to_unsigned(2, i2c_bytes_tx'length); -- write two bytes
moist_state_nxt <= S_ADDR_CHECK;
end if;
when S_ADDR_CHECK =>
if i2c_busy = '0' then
if i2c_error = '0' then
-- no error occured because the slave acked, thus found correct address
moist_state_nxt <= S_ADDR_RESET_BYTE0;
else
-- slave didn't acked, thus found incorrect address
if scan_addr = SCAN_ADDR_END then
-- reached end of possible i2c addresses, restart with lowest address
moist_state_nxt <= S_ADDR_SCAN;
else
-- increment address value to try the next possible
scan_addr_nxt <= scan_addr + to_unsigned(1, scan_addr'length);
moist_state_nxt <= S_ADDR_REGISTER_BYTE0;
end if;
end if;
end if;
when S_ADDR_RESET_BYTE0 =>
-- write reset command to tx fifo
i2c_tx_data <= MOIST_REG_RESET;
i2c_tx_data_valid <= '1';
moist_state_nxt <= S_ADDR_RESET_SEND;
when S_ADDR_RESET_SEND =>
-- send reset command
if i2c_busy = '0' then
i2c_cs <= '1';
i2c_mode <= "01"; -- write only
i2c_slave_addr <= std_ulogic_vector(scan_addr);
i2c_bytes_tx <= to_unsigned(1, i2c_bytes_tx'length); -- write one byte
moist_state_nxt <= S_MST_BOOT_DELAY;
end if;
when S_MST_BOOT_DELAY =>
-- wait 1s to boot up moisture sensor
if moist_boot_delay_cnt = to_unsigned(MOIST_BOOT_DELAY_TICKS - 1, moist_boot_delay_cnt'length) then
moist_boot_delay_cnt_nxt <= (others => '0');
moist_state_nxt <= S_MST_IDLE;
else
moist_boot_delay_cnt_nxt <= moist_boot_delay_cnt + to_unsigned(1, moist_boot_delay_cnt'length);
end if;
when S_MST_IDLE =>
-- wait for cycle_pulse
moist_busy <= i2c_busy;
if cycle_pulse = '1' then
moist_state_nxt <= S_MST_REGISTER_BYTE0;
end if;
when S_MST_REGISTER_BYTE0 =>
-- write register address to tx fifo
i2c_tx_data <= MOIST_REG_MOISTURE;
i2c_tx_data_valid <= '1';
moist_state_nxt <= S_MST_REGISTER_SEND_BYTE0;
when S_MST_REGISTER_SEND_BYTE0 =>
if i2c_busy = '0' then
-- start transmission
i2c_cs <= '1';
i2c_mode <= "01"; -- write only
i2c_bytes_tx <= to_unsigned(1, i2c_bytes_tx'length); -- write one byte
moist_state_nxt <= S_MST_READ_DELAY;
end if;
when S_MST_READ_DELAY =>
-- wait 20ms as recommended
if moist_read_delay_cnt = to_unsigned(MOIST_READ_DELAY_TICKS - 1, moist_read_delay_cnt'length) then
moist_read_delay_cnt_nxt <= (others => '0');
moist_state_nxt <= S_MST_READ_START;
else
moist_read_delay_cnt_nxt <= moist_read_delay_cnt + to_unsigned(1, moist_read_delay_cnt'length);
end if;
when S_MST_READ_START =>
if i2c_busy = '0' then
-- start transmission
i2c_cs <= '1';
i2c_mode <= "00"; -- read only
i2c_bytes_rx <= to_unsigned(MOIST_VALUES_WIDTH, i2c_bytes_rx'length); -- read two bytes
moist_state_nxt <= S_MST_READ_WAIT;
end if;
when S_MST_READ_WAIT =>
-- wait for i2c_master to finish communication
if i2c_busy = '0' then
moist_state_nxt <= S_MST_READ_BYTES;
moist_valid_nxt <= '1'; -- valid by default
end if;
when S_MST_READ_BYTES =>
if i2c_rx_data_valid = '1' then
-- read two bytes from rx fifo
i2c_rx_data_en <= '1';
-- increment amount of received bytes
moist_received_cnt_nxt <= moist_received_cnt + to_unsigned(1, moist_received_cnt'length);
if moist_received_cnt < to_unsigned(MOIST_VALUES_WIDTH, moist_received_cnt'length) then
-- assign byte to vals register
moist_vals_nxt(to_integer(moist_received_cnt)) <= i2c_rx_data;
end if;
if i2c_error = '1' then
-- an error occured, data isn't valid anymore
moist_valid_nxt <= '0';
end if;
else
-- rx fifo empty
moist_state_nxt <= S_MST_CHECK;
end if;
when S_MST_CHECK =>
-- clean up for next cycle, independent from `data_valid`
moist_received_cnt_nxt <= (others => '0');
if moist_valid = '1' then
-- data is valid
temp_value := resize(unsigned(std_ulogic_vector'(moist_vals(0) & moist_vals(1))), temp_value'length); -- reverse byte order
-- check if received value is in a reasonable range
if temp_value < to_unsigned(400, temp_value'length) then
-- too low, clip to 0%
moisture_reg_nxt <= (others => '0');
elsif temp_value > to_unsigned(580, temp_value'length) then
-- too damn high, clip to 99.9%
moisture_reg_nxt <= to_unsigned(999, moisture_reg'length);
else
-- in bounds, update moisture register
moisture_reg_nxt <= resize(shift_right((temp_value - 400) * 45511, 13), moisture_reg'length);
end if;
end if;
moist_state_nxt <= S_TMP_REGISTER_BYTE0;
when S_TMP_REGISTER_BYTE0 =>
-- fill tx fifo with register address of temperature register
i2c_tx_data <= MOIST_REG_TEMP;
i2c_tx_data_valid <= '1';
moist_state_nxt <= S_TMP_REGISTER_SEND_BYTE0;
when S_TMP_REGISTER_SEND_BYTE0 =>
if i2c_busy = '0' then
i2c_cs <= '1';
i2c_mode <= "01"; -- write only
i2c_bytes_tx <= to_unsigned(1, i2c_bytes_tx'length); -- write one byte
moist_state_nxt <= S_TMP_READ_DELAY;
end if;
when S_TMP_READ_DELAY =>
-- wait 20ms as recommended
if moist_read_delay_cnt = to_unsigned(MOIST_READ_DELAY_TICKS - 1, moist_read_delay_cnt'length) then
moist_read_delay_cnt_nxt <= (others => '0');
moist_state_nxt <= S_TMP_READ_START;
else
moist_read_delay_cnt_nxt <= moist_read_delay_cnt + to_unsigned(1, moist_read_delay_cnt'length);
end if;
when S_TMP_READ_START =>
if i2c_busy = '0' then
i2c_cs <= '1';
i2c_mode <= "00"; -- read only
i2c_bytes_rx <= to_unsigned(MOIST_VALUES_WIDTH, i2c_bytes_rx'length); -- read two bytes
moist_state_nxt <= S_TMP_READ_WAIT;
end if;
when S_TMP_READ_WAIT =>
-- wait for i2c_master to finish communication
if i2c_busy = '0' then
moist_state_nxt <= S_TMP_READ_BYTES;
moist_valid_nxt <= '1'; -- valid by default
end if;
when S_TMP_READ_BYTES =>
-- read bytes that are in rx fifo
if i2c_rx_data_valid = '1' then
-- get one byte
i2c_rx_data_en <= '1';
-- increment amount of received bytes
moist_received_cnt_nxt <= moist_received_cnt + to_unsigned(1, moist_received_cnt'length);
if moist_received_cnt < to_unsigned(MOIST_VALUES_WIDTH, moist_received_cnt'length) then
-- assign byte to vals register
moist_vals_nxt(to_integer(moist_received_cnt)) <= i2c_rx_data;
end if;
if i2c_error = '1' then
-- an error occured, data isn't valid anymore
moist_valid_nxt <= '0';
end if;
else
-- rx fifo empty
moist_state_nxt <= S_TMP_CHECK;
end if;
when S_TMP_CHECK =>
-- clean up for next cycle, independent from `data_valid`
moist_received_cnt_nxt <= (others => '0');
if moist_valid = '1' then
-- data is valid
temp_value := resize(unsigned(std_ulogic_vector'(moist_vals(0) & moist_vals(1))), temp_value'length);
-- check if received value is in a reasonable range
if temp_value > to_unsigned(150, temp_value'length) and temp_value < to_unsigned(350, temp_value'length) then
-- update moisture register
temp_reg_nxt <= unsigned(std_ulogic_vector'(moist_vals(0) & moist_vals(1)));
end if;
end if;
-- go back to idle state
moist_state_nxt <= S_MST_IDLE;
end case;
end process;
end rtl;
|
-------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_2_0_rport_v6.vhd
-- Description: Spartan-6 solution wrapper : Root Port for PCI Express
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity pcie_2_0_rport_v6 is
generic (
REF_CLK_FREQ : integer := 0; -- 0 - 100MHz, 1 - 125 MHz, 2 - 250 MHz
PIPE_PIPELINE_STAGES : integer := 0; -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
PCIE_DRP_ENABLE : boolean := FALSE;
DS_PORT_HOT_RST : boolean := FALSE; -- FALSE - for ROOT PORT(default), TRUE - for DOWNSTREAM PORT
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
LTSSM_MAX_LINK_WIDTH : bit_vector := X"01";
AER_BASE_PTR : bit_vector := X"128";
AER_CAP_ECRC_CHECK_CAPABLE : boolean := FALSE;
AER_CAP_ECRC_GEN_CAPABLE : boolean := FALSE;
AER_CAP_ID : bit_vector := X"1111";
AER_CAP_INT_MSG_NUM_MSI : bit_vector := X"0A";
AER_CAP_INT_MSG_NUM_MSIX : bit_vector := X"15";
AER_CAP_NEXTPTR : bit_vector := X"160";
AER_CAP_ON : boolean := FALSE;
AER_CAP_PERMIT_ROOTERR_UPDATE : boolean := TRUE;
AER_CAP_VERSION : bit_vector := X"1";
ALLOW_X8_GEN2 : boolean := FALSE;
BAR0 : bit_vector := X"00000000"; -- Memory aperture disabled
BAR1 : bit_vector := X"00000000"; -- Memory aperture disabled
BAR2 : bit_vector := X"00FFFFFF"; -- Constant for rport
BAR3 : bit_vector := X"FFFF0000"; -- IO Limit/Base Registers not implemented
BAR4 : bit_vector := X"FFF0FFF0"; -- Constant for rport
BAR5 : bit_vector := X"FFF1FFF1"; -- Prefetchable Memory Limit/Base Registers implemented
CAPABILITIES_PTR : bit_vector := X"40";
CARDBUS_CIS_POINTER : bit_vector := X"00000000";
CLASS_CODE : bit_vector := X"060400";
CMD_INTX_IMPLEMENTED : boolean := TRUE;
CPL_TIMEOUT_DISABLE_SUPPORTED : boolean := FALSE;
CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector := X"0";
CRM_MODULE_RSTS : bit_vector := X"00";
DEVICE_ID : bit_vector := X"0007";
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : boolean := TRUE;
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : boolean := TRUE;
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 0;
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 0;
DEV_CAP_EXT_TAG_SUPPORTED : boolean := TRUE;
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : boolean := FALSE;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
DEV_CAP_RSVD_14_12 : integer := 0;
DEV_CAP_RSVD_17_16 : integer := 0;
DEV_CAP_RSVD_31_29 : integer := 0;
DEV_CONTROL_AUX_POWER_SUPPORTED : boolean := FALSE;
DISABLE_ASPM_L1_TIMER : boolean := FALSE;
DISABLE_BAR_FILTERING : boolean := TRUE;
DISABLE_ID_CHECK : boolean := TRUE;
DISABLE_LANE_REVERSAL : boolean := FALSE;
DISABLE_RX_TC_FILTER : boolean := TRUE;
DISABLE_SCRAMBLING : boolean := FALSE;
DNSTREAM_LINK_NUM : bit_vector := X"00";
DSN_BASE_PTR : bit_vector := X"100";
DSN_CAP_ID : bit_vector := X"0003";
DSN_CAP_NEXTPTR : bit_vector := X"01C";
DSN_CAP_ON : boolean := TRUE;
DSN_CAP_VERSION : bit_vector := X"1";
ENABLE_MSG_ROUTE : bit_vector := X"000";
ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;
ENTER_RVRY_EI_L0 : boolean := TRUE;
EXIT_LOOPBACK_ON_EI : boolean := TRUE;
EXPANSION_ROM : bit_vector := X"00000000"; -- Memory aperture disabled
EXT_CFG_CAP_PTR : bit_vector := X"3F";
EXT_CFG_XP_CAP_PTR : bit_vector := X"3FF";
HEADER_TYPE : bit_vector := X"01";
INFER_EI : bit_vector := X"0C";
INTERRUPT_PIN : bit_vector := X"01";
IS_SWITCH : boolean := FALSE;
LAST_CONFIG_DWORD : bit_vector := X"042";
LINK_CAP_ASPM_SUPPORT : integer := 1;
LINK_CAP_CLOCK_POWER_MANAGEMENT : boolean := FALSE;
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : boolean := FALSE;
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer := 7;
LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer := 7;
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer := 7;
LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer := 7;
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean := FALSE;
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
LINK_CAP_RSVD_23_22 : integer := 0;
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : boolean := FALSE;
LINK_CONTROL_RCB : integer := 0;
LINK_CTRL2_DEEMPHASIS : boolean := FALSE;
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : boolean := FALSE;
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := TRUE;
LL_ACK_TIMEOUT : bit_vector := X"0000";
LL_ACK_TIMEOUT_EN : boolean := FALSE;
LL_ACK_TIMEOUT_FUNC : integer := 0;
LL_REPLAY_TIMEOUT : bit_vector := X"0000";
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
LL_REPLAY_TIMEOUT_FUNC : integer := 0;
MSIX_BASE_PTR : bit_vector := X"9C";
MSIX_CAP_ID : bit_vector := X"11";
MSIX_CAP_NEXTPTR : bit_vector := X"00";
MSIX_CAP_ON : boolean := TRUE;
MSIX_CAP_PBA_BIR : integer := 0;
MSIX_CAP_PBA_OFFSET : bit_vector := X"00000050";
MSIX_CAP_TABLE_BIR : integer := 0;
MSIX_CAP_TABLE_OFFSET : bit_vector := X"00000040";
MSIX_CAP_TABLE_SIZE : bit_vector := X"000";
MSI_BASE_PTR : bit_vector := X"48";
MSI_CAP_64_BIT_ADDR_CAPABLE : boolean := TRUE;
MSI_CAP_ID : bit_vector := X"05";
MSI_CAP_MULTIMSGCAP : integer := 0;
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
MSI_CAP_NEXTPTR : bit_vector := X"60";
MSI_CAP_ON : boolean := TRUE;
MSI_CAP_PER_VECTOR_MASKING_CAPABLE : boolean := TRUE;
N_FTS_COMCLK_GEN1 : integer := 255;
N_FTS_COMCLK_GEN2 : integer := 255;
N_FTS_GEN1 : integer := 255;
N_FTS_GEN2 : integer := 255;
PCIE_BASE_PTR : bit_vector := X"60";
PCIE_CAP_CAPABILITY_ID : bit_vector := X"10";
PCIE_CAP_CAPABILITY_VERSION : bit_vector := X"2";
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := X"4";
PCIE_CAP_INT_MSG_NUM : bit_vector := X"00";
PCIE_CAP_NEXTPTR : bit_vector := X"9C";
PCIE_CAP_ON : boolean := TRUE;
PCIE_CAP_RSVD_15_14 : integer := 0;
PCIE_CAP_SLOT_IMPLEMENTED : boolean := TRUE;
PCIE_REVISION : integer := 2;
PGL0_LANE : integer := 0;
PGL1_LANE : integer := 1;
PGL2_LANE : integer := 2;
PGL3_LANE : integer := 3;
PGL4_LANE : integer := 4;
PGL5_LANE : integer := 5;
PGL6_LANE : integer := 6;
PGL7_LANE : integer := 7;
PL_AUTO_CONFIG : integer := 0;
PL_FAST_TRAIN : boolean := FALSE;
PM_BASE_PTR : bit_vector := X"40";
PM_CAP_AUXCURRENT : integer := 0;
PM_CAP_D1SUPPORT : boolean := TRUE;
PM_CAP_D2SUPPORT : boolean := TRUE;
PM_CAP_DSI : boolean := FALSE;
PM_CAP_ID : bit_vector := X"11";
PM_CAP_NEXTPTR : bit_vector := X"48";
PM_CAP_ON : boolean := TRUE;
PM_CAP_PMESUPPORT : bit_vector := X"0F";
PM_CAP_PME_CLOCK : boolean := FALSE;
PM_CAP_RSVD_04 : integer := 0;
PM_CAP_VERSION : integer := 3;
PM_CSR_B2B3 : boolean := FALSE;
PM_CSR_BPCCEN : boolean := FALSE;
PM_CSR_NOSOFTRST : boolean := TRUE;
PM_DATA0 : bit_vector := X"01";
PM_DATA1 : bit_vector := X"01";
PM_DATA2 : bit_vector := X"01";
PM_DATA3 : bit_vector := X"01";
PM_DATA4 : bit_vector := X"01";
PM_DATA5 : bit_vector := X"01";
PM_DATA6 : bit_vector := X"01";
PM_DATA7 : bit_vector := X"01";
PM_DATA_SCALE0 : bit_vector := X"1";
PM_DATA_SCALE1 : bit_vector := X"1";
PM_DATA_SCALE2 : bit_vector := X"1";
PM_DATA_SCALE3 : bit_vector := X"1";
PM_DATA_SCALE4 : bit_vector := X"1";
PM_DATA_SCALE5 : bit_vector := X"1";
PM_DATA_SCALE6 : bit_vector := X"1";
PM_DATA_SCALE7 : bit_vector := X"1";
RECRC_CHK : integer := 0;
RECRC_CHK_TRIM : boolean := FALSE;
REVISION_ID : bit_vector := X"00";
ROOT_CAP_CRS_SW_VISIBILITY : boolean := FALSE;
SELECT_DLL_IF : boolean := FALSE;
SIM_VERSION : string := "1.0";
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
SLOT_CAP_ELEC_INTERLOCK_PRESENT : boolean := FALSE;
SLOT_CAP_HOTPLUG_CAPABLE : boolean := FALSE;
SLOT_CAP_HOTPLUG_SURPRISE : boolean := FALSE;
SLOT_CAP_MRL_SENSOR_PRESENT : boolean := FALSE;
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : boolean := FALSE;
SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector := X"0000";
SLOT_CAP_POWER_CONTROLLER_PRESENT : boolean := FALSE;
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer := 0;
SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector := X"00";
SPARE_BIT0 : integer := 0;
SPARE_BIT1 : integer := 0;
SPARE_BIT2 : integer := 0;
SPARE_BIT3 : integer := 0;
SPARE_BIT4 : integer := 0;
SPARE_BIT5 : integer := 0;
SPARE_BIT6 : integer := 0;
SPARE_BIT7 : integer := 0;
SPARE_BIT8 : integer := 0;
SPARE_BYTE0 : bit_vector := X"00";
SPARE_BYTE1 : bit_vector := X"00";
SPARE_BYTE2 : bit_vector := X"00";
SPARE_BYTE3 : bit_vector := X"00";
SPARE_WORD0 : bit_vector := X"00000000";
SPARE_WORD1 : bit_vector := X"00000000";
SPARE_WORD2 : bit_vector := X"00000000";
SPARE_WORD3 : bit_vector := X"00000000";
SUBSYSTEM_ID : bit_vector := X"0007";
SUBSYSTEM_VENDOR_ID : bit_vector := X"10EE";
TL_RBYPASS : boolean := FALSE;
TL_RX_RAM_RADDR_LATENCY : integer := 0;
TL_RX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_WRITE_LATENCY : integer := 0;
TL_TFC_DISABLE : boolean := FALSE;
TL_TX_CHECKS_DISABLE : boolean := FALSE;
TL_TX_RAM_RADDR_LATENCY : integer := 0;
TL_TX_RAM_RDATA_LATENCY : integer := 2;
TL_TX_RAM_WRITE_LATENCY : integer := 0;
UPCONFIG_CAPABLE : boolean := TRUE;
UPSTREAM_FACING : boolean := FALSE;
UR_INV_REQ : boolean := TRUE;
USER_CLK_FREQ : integer := 3;
VC0_CPL_INFINITE : boolean := TRUE;
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
VC0_TOTAL_CREDITS_CD : integer := 127;
VC0_TOTAL_CREDITS_CH : integer := 31;
VC0_TOTAL_CREDITS_NPH : integer := 12;
VC0_TOTAL_CREDITS_PD : integer := 288;
VC0_TOTAL_CREDITS_PH : integer := 32;
VC0_TX_LASTPACKET : integer := 31;
VC_BASE_PTR : bit_vector := X"10C";
VC_CAP_ID : bit_vector := X"0002";
VC_CAP_NEXTPTR : bit_vector := X"128";
VC_CAP_ON : boolean := TRUE;
VC_CAP_REJECT_SNOOP_TRANSACTIONS : boolean := FALSE;
VC_CAP_VERSION : bit_vector := X"1";
VENDOR_ID : bit_vector := X"10EE";
VSEC_BASE_PTR : bit_vector := X"160";
VSEC_CAP_HDR_ID : bit_vector := X"1234";
VSEC_CAP_HDR_LENGTH : bit_vector := X"018";
VSEC_CAP_HDR_REVISION : bit_vector := X"1";
VSEC_CAP_ID : bit_vector := X"000B";
VSEC_CAP_IS_LINK_VISIBLE : boolean := TRUE;
VSEC_CAP_NEXTPTR : bit_vector := X"000";
VSEC_CAP_ON : boolean := TRUE;
VSEC_CAP_VERSION : bit_vector := X"1"
);
port (
---------------------------------------------------------
-- 1. PCI Express (pci_exp) Interface
---------------------------------------------------------
-- Tx
pci_exp_txp : out std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
pci_exp_txn : out std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
-- Rx
pci_exp_rxp : in std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
pci_exp_rxn : in std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
---------------------------------------------------------
-- 2. Transaction (TRN) Interface
---------------------------------------------------------
-- Common
trn_clk : out std_logic;
trn_reset_n : out std_logic;
trn_lnk_up_n : out std_logic;
-- Tx
trn_tbuf_av : out std_logic_vector(5 downto 0);
trn_tcfg_req_n : out std_logic;
trn_terr_drop_n : out std_logic;
trn_tdst_rdy_n : out std_logic;
trn_td : in std_logic_vector(63 downto 0);
trn_trem_n : in std_logic;
trn_tsof_n : in std_logic;
trn_teof_n : in std_logic;
trn_tsrc_rdy_n : in std_logic;
trn_tsrc_dsc_n : in std_logic;
trn_terrfwd_n : in std_logic;
trn_tcfg_gnt_n : in std_logic;
trn_tstr_n : in std_logic;
-- Rx
trn_rd : out std_logic_vector(63 downto 0);
trn_rrem_n : out std_logic;
trn_rsof_n : out std_logic;
trn_reof_n : out std_logic;
trn_rsrc_rdy_n : out std_logic;
trn_rsrc_dsc_n : out std_logic;
trn_rerrfwd_n : out std_logic;
trn_rbar_hit_n : out std_logic_vector(6 downto 0);
trn_rdst_rdy_n : in std_logic;
trn_rnp_ok_n : in std_logic;
trn_recrc_err_n : out std_logic;
-- Flow Control
trn_fc_cpld : out std_logic_vector(11 downto 0);
trn_fc_cplh : out std_logic_vector(7 downto 0);
trn_fc_npd : out std_logic_vector(11 downto 0);
trn_fc_nph : out std_logic_vector(7 downto 0);
trn_fc_pd : out std_logic_vector(11 downto 0);
trn_fc_ph : out std_logic_vector(7 downto 0);
trn_fc_sel : in std_logic_vector(2 downto 0);
---------------------------------------------------------
-- 3. Configuration (CFG) Interface
---------------------------------------------------------
cfg_do : out std_logic_vector(31 downto 0);
cfg_rd_wr_done_n : out std_logic;
cfg_di : in std_logic_vector(31 downto 0);
cfg_byte_en_n : in std_logic_vector(3 downto 0);
cfg_dwaddr : in std_logic_vector(9 downto 0);
cfg_wr_en_n : in std_logic;
cfg_wr_rw1c_as_rw_n : in std_logic;
cfg_rd_en_n : in std_logic;
cfg_err_cor_n : in std_logic;
cfg_err_ur_n : in std_logic;
cfg_err_ecrc_n : in std_logic;
cfg_err_cpl_timeout_n : in std_logic;
cfg_err_cpl_abort_n : in std_logic;
cfg_err_cpl_unexpect_n : in std_logic;
cfg_err_posted_n : in std_logic;
cfg_err_locked_n : in std_logic;
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
cfg_err_cpl_rdy_n : out std_logic;
cfg_interrupt_n : in std_logic;
cfg_interrupt_rdy_n : out std_logic;
cfg_interrupt_assert_n : in std_logic;
cfg_interrupt_di : in std_logic_vector(7 downto 0);
cfg_interrupt_do : out std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
cfg_interrupt_msienable : out std_logic;
cfg_interrupt_msixenable : out std_logic;
cfg_interrupt_msixfm : out std_logic;
cfg_trn_pending_n : in std_logic;
cfg_pm_send_pme_to_n : in std_logic;
cfg_status : out std_logic_vector(15 downto 0);
cfg_command : out std_logic_vector(15 downto 0);
cfg_dstatus : out std_logic_vector(15 downto 0);
cfg_dcommand : out std_logic_vector(15 downto 0);
cfg_lstatus : out std_logic_vector(15 downto 0);
cfg_lcommand : out std_logic_vector(15 downto 0);
cfg_dcommand2 : out std_logic_vector(15 downto 0);
cfg_pcie_link_state_n : out std_logic_vector(2 downto 0);
cfg_dsn : in std_logic_vector(63 downto 0);
cfg_pmcsr_pme_en : out std_logic;
cfg_pmcsr_pme_status : out std_logic;
cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0);
cfg_msg_received : out std_logic;
cfg_msg_data : out std_logic_vector(15 downto 0);
cfg_msg_received_err_cor : out std_logic;
cfg_msg_received_err_non_fatal : out std_logic;
cfg_msg_received_err_fatal : out std_logic;
cfg_msg_received_pme_to_ack : out std_logic;
cfg_msg_received_assert_inta : out std_logic;
cfg_msg_received_assert_intb : out std_logic;
cfg_msg_received_assert_intc : out std_logic;
cfg_msg_received_assert_intd : out std_logic;
cfg_msg_received_deassert_inta : out std_logic;
cfg_msg_received_deassert_intb : out std_logic;
cfg_msg_received_deassert_intc : out std_logic;
cfg_msg_received_deassert_intd : out std_logic;
cfg_ds_bus_number : in std_logic_vector(7 downto 0);
cfg_ds_device_number : in std_logic_vector(4 downto 0);
---------------------------------------------------------
-- 4. Physical Layer Control and Status (PL) Interface
---------------------------------------------------------
pl_initial_link_width : out std_logic_vector(2 downto 0);
pl_lane_reversal_mode : out std_logic_vector(1 downto 0);
pl_link_gen2_capable : out std_logic;
pl_link_partner_gen2_supported : out std_logic;
pl_link_upcfg_capable : out std_logic;
pl_ltssm_state : out std_logic_vector(5 downto 0);
pl_sel_link_rate : out std_logic;
pl_sel_link_width : out std_logic_vector(1 downto 0);
pl_directed_link_auton : in std_logic;
pl_directed_link_change : in std_logic_vector(1 downto 0);
pl_directed_link_speed : in std_logic;
pl_directed_link_width : in std_logic_vector(1 downto 0);
pl_upstream_prefer_deemph : in std_logic;
pl_transmit_hot_rst : in std_logic;
---------------------------------------------------------
-- 5. PCIe DRP (PCIe DRP) Interface
---------------------------------------------------------
pcie_drp_clk : in std_logic;
pcie_drp_den : in std_logic;
pcie_drp_dwe : in std_logic;
pcie_drp_daddr : in std_logic_vector(8 downto 0);
pcie_drp_di : in std_logic_vector(15 downto 0);
pcie_drp_do : out std_logic_vector(15 downto 0);
pcie_drp_drdy : out std_logic;
---------------------------------------------------------
-- 6. System (SYS) Interface
---------------------------------------------------------
sys_clk : in std_logic;
sys_reset_n : in std_logic
);
end pcie_2_0_rport_v6;
architecture v6_pcie of pcie_2_0_rport_v6 is
component pcie_reset_delay_v6
generic (
PL_FAST_TRAIN : boolean;
REF_CLK_FREQ : integer);
port (
ref_clk : in std_logic;
sys_reset_n : in std_logic;
delayed_sys_reset_n : out std_logic);
end component;
component pcie_clocking_v6
generic (
IS_ENDPOINT : boolean;
CAP_LINK_WIDTH : integer;
CAP_LINK_SPEED : integer;
REF_CLK_FREQ : integer;
USER_CLK_FREQ : integer);
port (
sys_clk : in std_logic;
gt_pll_lock : in std_logic;
sel_lnk_rate : in std_logic;
sel_lnk_width : in std_logic_vector(1 downto 0);
sys_clk_bufg : out std_logic;
pipe_clk : out std_logic;
user_clk : out std_logic;
block_clk : out std_logic;
drp_clk : out std_logic;
clock_locked : out std_logic);
end component;
component pcie_2_0_v6_rp
generic (
REF_CLK_FREQ : integer;
PIPE_PIPELINE_STAGES : integer;
LINK_CAP_MAX_LINK_WIDTH_int : integer;
AER_BASE_PTR : bit_vector;
AER_CAP_ECRC_CHECK_CAPABLE : boolean;
AER_CAP_ECRC_GEN_CAPABLE : boolean;
AER_CAP_ID : bit_vector;
AER_CAP_INT_MSG_NUM_MSI : bit_vector;
AER_CAP_INT_MSG_NUM_MSIX : bit_vector;
AER_CAP_NEXTPTR : bit_vector;
AER_CAP_ON : boolean;
AER_CAP_PERMIT_ROOTERR_UPDATE : boolean;
AER_CAP_VERSION : bit_vector;
ALLOW_X8_GEN2 : boolean;
BAR0 : bit_vector;
BAR1 : bit_vector;
BAR2 : bit_vector;
BAR3 : bit_vector;
BAR4 : bit_vector;
BAR5 : bit_vector;
CAPABILITIES_PTR : bit_vector;
CARDBUS_CIS_POINTER : bit_vector;
CLASS_CODE : bit_vector;
CMD_INTX_IMPLEMENTED : boolean;
CPL_TIMEOUT_DISABLE_SUPPORTED : boolean;
CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector;
CRM_MODULE_RSTS : bit_vector;
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : boolean;
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : boolean;
DEV_CAP_ENDPOINT_L0S_LATENCY : integer;
DEV_CAP_ENDPOINT_L1_LATENCY : integer;
DEV_CAP_EXT_TAG_SUPPORTED : boolean;
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : boolean;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer;
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer;
DEV_CAP_ROLE_BASED_ERROR : boolean;
DEV_CAP_RSVD_14_12 : integer;
DEV_CAP_RSVD_17_16 : integer;
DEV_CAP_RSVD_31_29 : integer;
DEV_CONTROL_AUX_POWER_SUPPORTED : boolean;
DEVICE_ID : bit_vector;
DISABLE_ASPM_L1_TIMER : boolean;
DISABLE_BAR_FILTERING : boolean;
DISABLE_ID_CHECK : boolean;
DISABLE_LANE_REVERSAL : boolean;
DISABLE_RX_TC_FILTER : boolean;
DISABLE_SCRAMBLING : boolean;
DNSTREAM_LINK_NUM : bit_vector;
DSN_BASE_PTR : bit_vector;
DSN_CAP_ID : bit_vector;
DSN_CAP_NEXTPTR : bit_vector;
DSN_CAP_ON : boolean;
DSN_CAP_VERSION : bit_vector;
ENABLE_MSG_ROUTE : bit_vector;
ENABLE_RX_TD_ECRC_TRIM : boolean;
ENTER_RVRY_EI_L0 : boolean;
EXPANSION_ROM : bit_vector;
EXT_CFG_CAP_PTR : bit_vector;
EXT_CFG_XP_CAP_PTR : bit_vector;
HEADER_TYPE : bit_vector;
INFER_EI : bit_vector;
INTERRUPT_PIN : bit_vector;
IS_SWITCH : boolean;
LAST_CONFIG_DWORD : bit_vector;
LINK_CAP_ASPM_SUPPORT : integer;
LINK_CAP_CLOCK_POWER_MANAGEMENT : boolean;
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : boolean;
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer;
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer;
LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer;
LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer;
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer;
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer;
LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer;
LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer;
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean;
LINK_CAP_MAX_LINK_SPEED : bit_vector;
LINK_CAP_MAX_LINK_WIDTH : bit_vector;
LINK_CAP_RSVD_23_22 : integer;
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : boolean;
LINK_CONTROL_RCB : integer;
LINK_CTRL2_DEEMPHASIS : boolean;
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : boolean;
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector;
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean;
LL_ACK_TIMEOUT : bit_vector;
LL_ACK_TIMEOUT_EN : boolean;
LL_ACK_TIMEOUT_FUNC : integer;
LL_REPLAY_TIMEOUT : bit_vector;
LL_REPLAY_TIMEOUT_EN : boolean;
LL_REPLAY_TIMEOUT_FUNC : integer;
LTSSM_MAX_LINK_WIDTH : bit_vector;
MSI_BASE_PTR : bit_vector;
MSI_CAP_ID : bit_vector;
MSI_CAP_MULTIMSGCAP : integer;
MSI_CAP_MULTIMSG_EXTENSION : integer;
MSI_CAP_NEXTPTR : bit_vector;
MSI_CAP_ON : boolean;
MSI_CAP_PER_VECTOR_MASKING_CAPABLE : boolean;
MSI_CAP_64_BIT_ADDR_CAPABLE : boolean;
MSIX_BASE_PTR : bit_vector;
MSIX_CAP_ID : bit_vector;
MSIX_CAP_NEXTPTR : bit_vector;
MSIX_CAP_ON : boolean;
MSIX_CAP_PBA_BIR : integer;
MSIX_CAP_PBA_OFFSET : bit_vector;
MSIX_CAP_TABLE_BIR : integer;
MSIX_CAP_TABLE_OFFSET : bit_vector;
MSIX_CAP_TABLE_SIZE : bit_vector;
N_FTS_COMCLK_GEN1 : integer;
N_FTS_COMCLK_GEN2 : integer;
N_FTS_GEN1 : integer;
N_FTS_GEN2 : integer;
PCIE_BASE_PTR : bit_vector;
PCIE_CAP_CAPABILITY_ID : bit_vector;
PCIE_CAP_CAPABILITY_VERSION : bit_vector;
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector;
PCIE_CAP_INT_MSG_NUM : bit_vector;
PCIE_CAP_NEXTPTR : bit_vector;
PCIE_CAP_ON : boolean;
PCIE_CAP_RSVD_15_14 : integer;
PCIE_CAP_SLOT_IMPLEMENTED : boolean;
PCIE_REVISION : integer;
PGL0_LANE : integer;
PGL1_LANE : integer;
PGL2_LANE : integer;
PGL3_LANE : integer;
PGL4_LANE : integer;
PGL5_LANE : integer;
PGL6_LANE : integer;
PGL7_LANE : integer;
PL_AUTO_CONFIG : integer;
PL_FAST_TRAIN : boolean;
PM_BASE_PTR : bit_vector;
PM_CAP_AUXCURRENT : integer;
PM_CAP_DSI : boolean;
PM_CAP_D1SUPPORT : boolean;
PM_CAP_D2SUPPORT : boolean;
PM_CAP_ID : bit_vector;
PM_CAP_NEXTPTR : bit_vector;
PM_CAP_ON : boolean;
PM_CAP_PME_CLOCK : boolean;
PM_CAP_PMESUPPORT : bit_vector;
PM_CAP_RSVD_04 : integer;
PM_CAP_VERSION : integer;
PM_CSR_BPCCEN : boolean;
PM_CSR_B2B3 : boolean;
PM_CSR_NOSOFTRST : boolean;
PM_DATA0 : bit_vector;
PM_DATA1 : bit_vector;
PM_DATA2 : bit_vector;
PM_DATA3 : bit_vector;
PM_DATA4 : bit_vector;
PM_DATA5 : bit_vector;
PM_DATA6 : bit_vector;
PM_DATA7 : bit_vector;
PM_DATA_SCALE0 : bit_vector;
PM_DATA_SCALE1 : bit_vector;
PM_DATA_SCALE2 : bit_vector;
PM_DATA_SCALE3 : bit_vector;
PM_DATA_SCALE4 : bit_vector;
PM_DATA_SCALE5 : bit_vector;
PM_DATA_SCALE6 : bit_vector;
PM_DATA_SCALE7 : bit_vector;
RECRC_CHK : integer;
RECRC_CHK_TRIM : boolean;
REVISION_ID : bit_vector;
ROOT_CAP_CRS_SW_VISIBILITY : boolean;
SELECT_DLL_IF : boolean;
SLOT_CAP_ATT_BUTTON_PRESENT : boolean;
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean;
SLOT_CAP_ELEC_INTERLOCK_PRESENT : boolean;
SLOT_CAP_HOTPLUG_CAPABLE : boolean;
SLOT_CAP_HOTPLUG_SURPRISE : boolean;
SLOT_CAP_MRL_SENSOR_PRESENT : boolean;
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : boolean;
SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector;
SLOT_CAP_POWER_CONTROLLER_PRESENT : boolean;
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean;
SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer;
SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector;
SPARE_BIT0 : integer;
SPARE_BIT1 : integer;
SPARE_BIT2 : integer;
SPARE_BIT3 : integer;
SPARE_BIT4 : integer;
SPARE_BIT5 : integer;
SPARE_BIT6 : integer;
SPARE_BIT7 : integer;
SPARE_BIT8 : integer;
SPARE_BYTE0 : bit_vector;
SPARE_BYTE1 : bit_vector;
SPARE_BYTE2 : bit_vector;
SPARE_BYTE3 : bit_vector;
SPARE_WORD0 : bit_vector;
SPARE_WORD1 : bit_vector;
SPARE_WORD2 : bit_vector;
SPARE_WORD3 : bit_vector;
SUBSYSTEM_ID : bit_vector;
SUBSYSTEM_VENDOR_ID : bit_vector;
TL_RBYPASS : boolean;
TL_RX_RAM_RADDR_LATENCY : integer;
TL_RX_RAM_RDATA_LATENCY : integer;
TL_RX_RAM_WRITE_LATENCY : integer;
TL_TFC_DISABLE : boolean;
TL_TX_CHECKS_DISABLE : boolean;
TL_TX_RAM_RADDR_LATENCY : integer;
TL_TX_RAM_RDATA_LATENCY : integer;
TL_TX_RAM_WRITE_LATENCY : integer;
UPCONFIG_CAPABLE : boolean;
UPSTREAM_FACING : boolean;
UR_INV_REQ : boolean;
USER_CLK_FREQ : integer;
EXIT_LOOPBACK_ON_EI : boolean;
VC_BASE_PTR : bit_vector;
VC_CAP_ID : bit_vector;
VC_CAP_NEXTPTR : bit_vector;
VC_CAP_ON : boolean;
VC_CAP_REJECT_SNOOP_TRANSACTIONS : boolean;
VC_CAP_VERSION : bit_vector;
VC0_CPL_INFINITE : boolean;
VC0_RX_RAM_LIMIT : bit_vector;
VC0_TOTAL_CREDITS_CD : integer;
VC0_TOTAL_CREDITS_CH : integer;
VC0_TOTAL_CREDITS_NPH : integer;
VC0_TOTAL_CREDITS_PD : integer;
VC0_TOTAL_CREDITS_PH : integer;
VC0_TX_LASTPACKET : integer;
VENDOR_ID : bit_vector;
VSEC_BASE_PTR : bit_vector;
VSEC_CAP_HDR_ID : bit_vector;
VSEC_CAP_HDR_LENGTH : bit_vector;
VSEC_CAP_HDR_REVISION : bit_vector;
VSEC_CAP_ID : bit_vector;
VSEC_CAP_IS_LINK_VISIBLE : boolean;
VSEC_CAP_NEXTPTR : bit_vector;
VSEC_CAP_ON : boolean;
VSEC_CAP_VERSION : bit_vector);
port (
PCIEXPRXN : in std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
PCIEXPRXP : in std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
PCIEXPTXN : out std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
PCIEXPTXP : out std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
SYSCLK : in std_logic;
FUNDRSTN : in std_logic;
TRNLNKUPN : out std_logic;
TRNCLK : out std_logic;
PHYRDYN : out std_logic;
USERRSTN : out std_logic;
RECEIVEDFUNCLVLRSTN : out std_logic;
LNKCLKEN : out std_logic;
SYSRSTN : in std_logic;
PLRSTN : in std_logic;
DLRSTN : in std_logic;
TLRSTN : in std_logic;
FUNCLVLRSTN : in std_logic;
CMRSTN : in std_logic;
CMSTICKYRSTN : in std_logic;
TRNRBARHITN : out std_logic_vector(6 downto 0);
TRNRD : out std_logic_vector(63 downto 0);
TRNRECRCERRN : out std_logic;
TRNREOFN : out std_logic;
TRNRERRFWDN : out std_logic;
TRNRREMN : out std_logic;
TRNRSOFN : out std_logic;
TRNRSRCDSCN : out std_logic;
TRNRSRCRDYN : out std_logic;
TRNRDSTRDYN : in std_logic;
TRNRNPOKN : in std_logic;
TRNTBUFAV : out std_logic_vector(5 downto 0);
TRNTCFGREQN : out std_logic;
TRNTDLLPDSTRDYN : out std_logic;
TRNTDSTRDYN : out std_logic;
TRNTERRDROPN : out std_logic;
TRNTCFGGNTN : in std_logic;
TRNTD : in std_logic_vector(63 downto 0);
TRNTDLLPDATA : in std_logic_vector(31 downto 0);
TRNTDLLPSRCRDYN : in std_logic;
TRNTECRCGENN : in std_logic;
TRNTEOFN : in std_logic;
TRNTERRFWDN : in std_logic;
TRNTREMN : in std_logic;
TRNTSOFN : in std_logic;
TRNTSRCDSCN : in std_logic;
TRNTSRCRDYN : in std_logic;
TRNTSTRN : in std_logic;
TRNFCCPLD : out std_logic_vector(11 downto 0);
TRNFCCPLH : out std_logic_vector(7 downto 0);
TRNFCNPD : out std_logic_vector(11 downto 0);
TRNFCNPH : out std_logic_vector(7 downto 0);
TRNFCPD : out std_logic_vector(11 downto 0);
TRNFCPH : out std_logic_vector(7 downto 0);
TRNFCSEL : in std_logic_vector(2 downto 0);
CFGAERECRCCHECKEN : out std_logic;
CFGAERECRCGENEN : out std_logic;
CFGCOMMANDBUSMASTERENABLE : out std_logic;
CFGCOMMANDINTERRUPTDISABLE : out std_logic;
CFGCOMMANDIOENABLE : out std_logic;
CFGCOMMANDMEMENABLE : out std_logic;
CFGCOMMANDSERREN : out std_logic;
CFGDEVCONTROLAUXPOWEREN : out std_logic;
CFGDEVCONTROLCORRERRREPORTINGEN : out std_logic;
CFGDEVCONTROLENABLERO : out std_logic;
CFGDEVCONTROLEXTTAGEN : out std_logic;
CFGDEVCONTROLFATALERRREPORTINGEN : out std_logic;
CFGDEVCONTROLMAXPAYLOAD : out std_logic_vector(2 downto 0);
CFGDEVCONTROLMAXREADREQ : out std_logic_vector(2 downto 0);
CFGDEVCONTROLNONFATALREPORTINGEN : out std_logic;
CFGDEVCONTROLNOSNOOPEN : out std_logic;
CFGDEVCONTROLPHANTOMEN : out std_logic;
CFGDEVCONTROLURERRREPORTINGEN : out std_logic;
CFGDEVCONTROL2CPLTIMEOUTDIS : out std_logic;
CFGDEVCONTROL2CPLTIMEOUTVAL : out std_logic_vector(3 downto 0);
CFGDEVSTATUSCORRERRDETECTED : out std_logic;
CFGDEVSTATUSFATALERRDETECTED : out std_logic;
CFGDEVSTATUSNONFATALERRDETECTED : out std_logic;
CFGDEVSTATUSURDETECTED : out std_logic;
CFGDO : out std_logic_vector(31 downto 0);
CFGERRAERHEADERLOGSETN : out std_logic;
CFGERRCPLRDYN : out std_logic;
CFGINTERRUPTDO : out std_logic_vector(7 downto 0);
CFGINTERRUPTMMENABLE : out std_logic_vector(2 downto 0);
CFGINTERRUPTMSIENABLE : out std_logic;
CFGINTERRUPTMSIXENABLE : out std_logic;
CFGINTERRUPTMSIXFM : out std_logic;
CFGINTERRUPTRDYN : out std_logic;
CFGLINKCONTROLRCB : out std_logic;
CFGLINKCONTROLASPMCONTROL : out std_logic_vector(1 downto 0);
CFGLINKCONTROLAUTOBANDWIDTHINTEN : out std_logic;
CFGLINKCONTROLBANDWIDTHINTEN : out std_logic;
CFGLINKCONTROLCLOCKPMEN : out std_logic;
CFGLINKCONTROLCOMMONCLOCK : out std_logic;
CFGLINKCONTROLEXTENDEDSYNC : out std_logic;
CFGLINKCONTROLHWAUTOWIDTHDIS : out std_logic;
CFGLINKCONTROLLINKDISABLE : out std_logic;
CFGLINKCONTROLRETRAINLINK : out std_logic;
CFGLINKSTATUSAUTOBANDWIDTHSTATUS : out std_logic;
CFGLINKSTATUSBANDWITHSTATUS : out std_logic;
CFGLINKSTATUSCURRENTSPEED : out std_logic_vector(1 downto 0);
CFGLINKSTATUSDLLACTIVE : out std_logic;
CFGLINKSTATUSLINKTRAINING : out std_logic;
CFGLINKSTATUSNEGOTIATEDWIDTH : out std_logic_vector(3 downto 0);
CFGMSGDATA : out std_logic_vector(15 downto 0);
CFGMSGRECEIVED : out std_logic;
CFGMSGRECEIVEDASSERTINTA : out std_logic;
CFGMSGRECEIVEDASSERTINTB : out std_logic;
CFGMSGRECEIVEDASSERTINTC : out std_logic;
CFGMSGRECEIVEDASSERTINTD : out std_logic;
CFGMSGRECEIVEDDEASSERTINTA : out std_logic;
CFGMSGRECEIVEDDEASSERTINTB : out std_logic;
CFGMSGRECEIVEDDEASSERTINTC : out std_logic;
CFGMSGRECEIVEDDEASSERTINTD : out std_logic;
CFGMSGRECEIVEDERRCOR : out std_logic;
CFGMSGRECEIVEDERRFATAL : out std_logic;
CFGMSGRECEIVEDERRNONFATAL : out std_logic;
CFGMSGRECEIVEDPMASNAK : out std_logic;
CFGMSGRECEIVEDPMETO : out std_logic;
CFGMSGRECEIVEDPMETOACK : out std_logic;
CFGMSGRECEIVEDPMPME : out std_logic;
CFGMSGRECEIVEDSETSLOTPOWERLIMIT : out std_logic;
CFGMSGRECEIVEDUNLOCK : out std_logic;
CFGPCIELINKSTATE : out std_logic_vector(2 downto 0);
CFGPMCSRPMEEN : out std_logic;
CFGPMCSRPMESTATUS : out std_logic;
CFGPMCSRPOWERSTATE : out std_logic_vector(1 downto 0);
CFGPMRCVASREQL1N : out std_logic;
CFGPMRCVENTERL1N : out std_logic;
CFGPMRCVENTERL23N : out std_logic;
CFGPMRCVREQACKN : out std_logic;
CFGRDWRDONEN : out std_logic;
CFGSLOTCONTROLELECTROMECHILCTLPULSE : out std_logic;
CFGTRANSACTION : out std_logic;
CFGTRANSACTIONADDR : out std_logic_vector(6 downto 0);
CFGTRANSACTIONTYPE : out std_logic;
CFGVCTCVCMAP : out std_logic_vector(6 downto 0);
CFGBYTEENN : in std_logic_vector(3 downto 0);
CFGDI : in std_logic_vector(31 downto 0);
CFGDSBUSNUMBER : in std_logic_vector(7 downto 0);
CFGDSDEVICENUMBER : in std_logic_vector(4 downto 0);
CFGDSFUNCTIONNUMBER : in std_logic_vector(2 downto 0);
CFGDSN : in std_logic_vector(63 downto 0);
CFGDWADDR : in std_logic_vector(9 downto 0);
CFGERRACSN : in std_logic;
CFGERRAERHEADERLOG : in std_logic_vector(127 downto 0);
CFGERRCORN : in std_logic;
CFGERRCPLABORTN : in std_logic;
CFGERRCPLTIMEOUTN : in std_logic;
CFGERRCPLUNEXPECTN : in std_logic;
CFGERRECRCN : in std_logic;
CFGERRLOCKEDN : in std_logic;
CFGERRPOSTEDN : in std_logic;
CFGERRTLPCPLHEADER : in std_logic_vector(47 downto 0);
CFGERRURN : in std_logic;
CFGINTERRUPTASSERTN : in std_logic;
CFGINTERRUPTDI : in std_logic_vector(7 downto 0);
CFGINTERRUPTN : in std_logic;
CFGPMDIRECTASPML1N : in std_logic;
CFGPMSENDPMACKN : in std_logic;
CFGPMSENDPMETON : in std_logic;
CFGPMSENDPMNAKN : in std_logic;
CFGPMTURNOFFOKN : in std_logic;
CFGPMWAKEN : in std_logic;
CFGPORTNUMBER : in std_logic_vector(7 downto 0);
CFGRDENN : in std_logic;
CFGTRNPENDINGN : in std_logic;
CFGWRENN : in std_logic;
CFGWRREADONLYN : in std_logic;
CFGWRRW1CASRWN : in std_logic;
PLINITIALLINKWIDTH : out std_logic_vector(2 downto 0);
PLLANEREVERSALMODE : out std_logic_vector(1 downto 0);
PLLINKGEN2CAP : out std_logic;
PLLINKPARTNERGEN2SUPPORTED : out std_logic;
PLLINKUPCFGCAP : out std_logic;
PLLTSSMSTATE : out std_logic_vector(5 downto 0);
PLPHYLNKUPN : out std_logic;
PLRECEIVEDHOTRST : out std_logic;
PLRXPMSTATE : out std_logic_vector(1 downto 0);
PLSELLNKRATE : out std_logic;
PLSELLNKWIDTH : out std_logic_vector(1 downto 0);
PLTXPMSTATE : out std_logic_vector(2 downto 0);
PLDIRECTEDLINKAUTON : in std_logic;
PLDIRECTEDLINKCHANGE : in std_logic_vector(1 downto 0);
PLDIRECTEDLINKSPEED : in std_logic;
PLDIRECTEDLINKWIDTH : in std_logic_vector(1 downto 0);
PLDOWNSTREAMDEEMPHSOURCE : in std_logic;
PLUPSTREAMPREFERDEEMPH : in std_logic;
PLTRANSMITHOTRST : in std_logic;
DBGSCLRA : out std_logic;
DBGSCLRB : out std_logic;
DBGSCLRC : out std_logic;
DBGSCLRD : out std_logic;
DBGSCLRE : out std_logic;
DBGSCLRF : out std_logic;
DBGSCLRG : out std_logic;
DBGSCLRH : out std_logic;
DBGSCLRI : out std_logic;
DBGSCLRJ : out std_logic;
DBGSCLRK : out std_logic;
DBGVECA : out std_logic_vector(63 downto 0);
DBGVECB : out std_logic_vector(63 downto 0);
DBGVECC : out std_logic_vector(11 downto 0);
PLDBGVEC : out std_logic_vector(11 downto 0);
DBGMODE : in std_logic_vector(1 downto 0);
DBGSUBMODE : in std_logic;
PLDBGMODE : in std_logic_vector(2 downto 0);
PCIEDRPDO : out std_logic_vector(15 downto 0);
PCIEDRPDRDY : out std_logic;
PCIEDRPCLK : in std_logic;
PCIEDRPDADDR : in std_logic_vector(8 downto 0);
PCIEDRPDEN : in std_logic;
PCIEDRPDI : in std_logic_vector(15 downto 0);
PCIEDRPDWE : in std_logic;
GTPLLLOCK : out std_logic;
PIPECLK : in std_logic;
USERCLK : in std_logic;
DRPCLK : in std_logic;
CLOCKLOCKED : in std_logic;
TxOutClk : out std_logic);
end component;
FUNCTION to_integer (
val_in : bit_vector) RETURN integer IS
CONSTANT vctr : bit_vector(val_in'high-val_in'low DOWNTO 0) := val_in;
VARIABLE ret : integer := 0;
BEGIN
FOR index IN vctr'RANGE LOOP
IF (vctr(index) = '1') THEN
ret := ret + (2**index);
END IF;
END LOOP;
RETURN(ret);
END to_integer;
FUNCTION to_stdlogic (
in_val : IN boolean) RETURN std_logic IS
BEGIN
IF (in_val) THEN
RETURN('1');
ELSE
RETURN('0');
END IF;
END to_stdlogic;
function lp_lnk_bw_notif (
link_width : integer;
link_spd : integer)
return boolean is
begin -- lp_lnk_bw_notif
if ((link_width > 1) or (link_spd > 1)) then
return true;
else
return false;
end if;
end lp_lnk_bw_notif;
function pad_gen (
in_vec : bit_vector;
op_len : integer)
return bit_vector is
variable ret : bit_vector(op_len-1 downto 0) := (others => '0');
constant len : integer := in_vec'length; -- length of input vector
begin -- pad_gen
for i in 0 to op_len-1 loop
if (i < len) then
ret(i) := in_vec(len-i-1);
else
ret(i) := '0';
end if;
end loop; -- i
return ret;
end pad_gen;
constant LINK_CAP_MAX_LINK_SPEED_int : integer := to_integer(LINK_CAP_MAX_LINK_SPEED);
constant LP_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean := lp_lnk_bw_notif(LINK_CAP_MAX_LINK_WIDTH_int, LINK_CAP_MAX_LINK_SPEED_int);
constant LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus : std_logic := to_stdlogic(LINK_STATUS_SLOT_CLOCK_CONFIG);
signal rx_func_level_reset_n : std_logic;
signal block_clk : std_logic;
signal cfg_cmd_bme : std_logic;
signal cfg_cmd_intdis : std_logic;
signal cfg_cmd_io_en : std_logic;
signal cfg_cmd_mem_en : std_logic;
signal cfg_cmd_serr_en : std_logic;
signal cfg_dev_control_aux_power_en : std_logic;
signal cfg_dev_control_corr_err_reporting_en : std_logic;
signal cfg_dev_control_enable_relaxed_order : std_logic;
signal cfg_dev_control_ext_tag_en : std_logic;
signal cfg_dev_control_fatal_err_reporting_en : std_logic;
signal cfg_dev_control_maxpayload : std_logic_vector(2 downto 0);
signal cfg_dev_control_max_read_req : std_logic_vector(2 downto 0);
signal cfg_dev_control_non_fatal_reporting_en : std_logic;
signal cfg_dev_control_nosnoop_en : std_logic;
signal cfg_dev_control_phantom_en : std_logic;
signal cfg_dev_control_ur_err_reporting_en : std_logic;
signal cfg_dev_control2_cpltimeout_dis : std_logic;
signal cfg_dev_control2_cpltimeout_val : std_logic_vector(3 downto 0);
signal cfg_dev_status_corr_err_detected : std_logic;
signal cfg_dev_status_fatal_err_detected : std_logic;
signal cfg_dev_status_nonfatal_err_detected : std_logic;
signal cfg_dev_status_ur_detected : std_logic;
signal cfg_link_control_auto_bandwidth_int_en : std_logic;
signal cfg_link_control_bandwidth_int_en : std_logic;
signal cfg_link_control_hw_auto_width_dis : std_logic;
signal cfg_link_control_clock_pm_en : std_logic;
signal cfg_link_control_extended_sync : std_logic;
signal cfg_link_control_common_clock : std_logic;
signal cfg_link_control_retrain_link : std_logic;
signal cfg_link_control_linkdisable : std_logic;
signal cfg_link_control_rcb : std_logic;
signal cfg_link_control_aspm_control : std_logic_vector(1 downto 0);
signal cfg_link_status_auto_bandwidth_status : std_logic;
signal cfg_link_status_bandwidth_status : std_logic;
signal cfg_link_status_dll_active : std_logic;
signal cfg_link_status_link_training : std_logic;
signal cfg_link_status_negotiated_link_width : std_logic_vector(3 downto 0);
signal cfg_link_status_current_speed : std_logic_vector(1 downto 0);
signal sys_reset_n_d : std_logic;
signal phy_rdy_n : std_logic;
signal trn_lnk_up_n_int : std_logic;
signal trn_lnk_up_n_int1 : std_logic;
signal trn_reset_n_int : std_logic;
signal trn_reset_n_int1 : std_logic;
signal TxOutClk : std_logic;
signal TxOutClk_bufg : std_logic;
signal gt_pll_lock : std_logic;
signal user_clk : std_logic;
signal drp_clk : std_logic;
signal clock_locked : std_logic;
-- X-HDL generated signals
signal v6pcie63 : std_logic;
signal v6pcie64 : std_logic;
signal v6pcie65 : std_logic;
signal v6pcie66 : std_logic;
signal v6pcie67 : std_logic;
signal v6pcie68 : std_logic_vector(1 downto 0);
signal v6pcie69 : std_logic;
signal func_lvl_rstn : std_logic;
signal cm_rstn : std_logic;
-- Declare intermediate signals for referenced outputs
signal pci_exp_txp_v6pcie28 : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
signal pci_exp_txn_v6pcie27 : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
signal trn_clk_v6pcie41 : std_logic;
signal trn_reset_n_v6pcie54 : std_logic;
signal trn_lnk_up_n_v6pcie48 : std_logic;
signal trn_tbuf_av_v6pcie59 : std_logic_vector(5 downto 0);
signal trn_tcfg_req_n_v6pcie60 : std_logic;
signal trn_terr_drop_n_v6pcie62 : std_logic;
signal trn_tdst_rdy_n_v6pcie61 : std_logic;
signal trn_rd_v6pcie50 : std_logic_vector(63 downto 0);
signal trn_rrem_n_v6pcie55 : std_logic;
signal trn_rsof_n_v6pcie56 : std_logic;
signal trn_reof_n_v6pcie52 : std_logic;
signal trn_rsrc_rdy_n_v6pcie58 : std_logic;
signal trn_rsrc_dsc_n_v6pcie57 : std_logic;
signal trn_rerrfwd_n_v6pcie53 : std_logic;
signal trn_rbar_hit_n_v6pcie49 : std_logic_vector(6 downto 0);
signal trn_recrc_err_n_v6pcie51 : std_logic;
signal trn_fc_cpld_v6pcie42 : std_logic_vector(11 downto 0);
signal trn_fc_cplh_v6pcie43 : std_logic_vector(7 downto 0);
signal trn_fc_npd_v6pcie44 : std_logic_vector(11 downto 0);
signal trn_fc_nph_v6pcie45 : std_logic_vector(7 downto 0);
signal trn_fc_pd_v6pcie46 : std_logic_vector(11 downto 0);
signal trn_fc_ph_v6pcie47 : std_logic_vector(7 downto 0);
signal cfg_err_cpl_rdy_n_v6pcie1 : std_logic;
signal cfg_interrupt_rdy_n_v6pcie7 : std_logic;
signal cfg_interrupt_do_v6pcie2 : std_logic_vector(7 downto 0);
signal cfg_interrupt_mmenable_v6pcie3 : std_logic_vector(2 downto 0);
signal cfg_interrupt_msienable_v6pcie4 : std_logic;
signal cfg_interrupt_msixenable_v6pcie5 : std_logic;
signal cfg_interrupt_msixfm_v6pcie6 : std_logic;
signal cfg_pcie_link_state_n_v6pcie22 : std_logic_vector(2 downto 0);
signal cfg_pmcsr_pme_en_v6pcie23 : std_logic;
signal cfg_pmcsr_pme_status_v6pcie24 : std_logic;
signal cfg_pmcsr_powerstate_v6pcie25 : std_logic_vector(1 downto 0);
signal cfg_msg_received_v6pcie9 : std_logic;
signal cfg_msg_data_v6pcie8 : std_logic_vector(15 downto 0);
signal cfg_msg_received_err_cor_v6pcie18 : std_logic;
signal cfg_msg_received_err_non_fatal_v6pcie20 : std_logic;
signal cfg_msg_received_err_fatal_v6pcie19 : std_logic;
signal cfg_msg_received_pme_to_ack_v6pcie21 : std_logic;
signal cfg_msg_received_assert_inta_v6pcie10 : std_logic;
signal cfg_msg_received_assert_intb_v6pcie11 : std_logic;
signal cfg_msg_received_assert_intc_v6pcie12 : std_logic;
signal cfg_msg_received_assert_intd_v6pcie13 : std_logic;
signal cfg_msg_received_deassert_inta_v6pcie14 : std_logic;
signal cfg_msg_received_deassert_intb_v6pcie15 : std_logic;
signal cfg_msg_received_deassert_intc_v6pcie16 : std_logic;
signal cfg_msg_received_deassert_intd_v6pcie17 : std_logic;
signal pipe_clk : std_logic;
signal pl_phy_lnk_up_n : std_logic;
signal pl_initial_link_width_v6pcie32 : std_logic_vector(2 downto 0);
signal pl_lane_reversal_mode_v6pcie33 : std_logic_vector(1 downto 0);
signal pl_link_gen2_capable_v6pcie34 : std_logic;
signal pl_link_partner_gen2_supported_v6pcie35 : std_logic;
signal pl_link_upcfg_capable_v6pcie36 : std_logic;
signal pl_ltssm_state_v6pcie37 : std_logic_vector(5 downto 0);
signal pl_sel_link_rate_v6pcie39 : std_logic;
signal pl_sel_link_width_v6pcie40 : std_logic_vector(1 downto 0);
signal pcie_drp_do_v6pcie29 : std_logic_vector(15 downto 0);
signal pcie_drp_drdy_v6pcie30 : std_logic;
begin
-- Drive referenced outputs
pci_exp_txp <= pci_exp_txp_v6pcie28;
pci_exp_txn <= pci_exp_txn_v6pcie27;
trn_clk <= trn_clk_v6pcie41;
trn_reset_n <= trn_reset_n_v6pcie54;
trn_lnk_up_n <= trn_lnk_up_n_v6pcie48;
trn_tbuf_av <= trn_tbuf_av_v6pcie59;
trn_tcfg_req_n <= trn_tcfg_req_n_v6pcie60;
trn_terr_drop_n <= trn_terr_drop_n_v6pcie62;
trn_tdst_rdy_n <= trn_tdst_rdy_n_v6pcie61;
trn_rd <= trn_rd_v6pcie50;
trn_rrem_n <= trn_rrem_n_v6pcie55;
trn_rsof_n <= trn_rsof_n_v6pcie56;
trn_reof_n <= trn_reof_n_v6pcie52;
trn_rsrc_rdy_n <= trn_rsrc_rdy_n_v6pcie58;
trn_rsrc_dsc_n <= trn_rsrc_dsc_n_v6pcie57;
trn_rerrfwd_n <= trn_rerrfwd_n_v6pcie53;
trn_rbar_hit_n <= trn_rbar_hit_n_v6pcie49;
trn_recrc_err_n <= trn_recrc_err_n_v6pcie51;
trn_fc_cpld <= trn_fc_cpld_v6pcie42;
trn_fc_cplh <= trn_fc_cplh_v6pcie43;
trn_fc_npd <= trn_fc_npd_v6pcie44;
trn_fc_nph <= trn_fc_nph_v6pcie45;
trn_fc_pd <= trn_fc_pd_v6pcie46;
trn_fc_ph <= trn_fc_ph_v6pcie47;
cfg_err_cpl_rdy_n <= cfg_err_cpl_rdy_n_v6pcie1;
cfg_interrupt_rdy_n <= cfg_interrupt_rdy_n_v6pcie7;
cfg_interrupt_do <= cfg_interrupt_do_v6pcie2;
cfg_interrupt_mmenable <= cfg_interrupt_mmenable_v6pcie3;
cfg_interrupt_msienable <= cfg_interrupt_msienable_v6pcie4;
cfg_interrupt_msixenable <= cfg_interrupt_msixenable_v6pcie5;
cfg_interrupt_msixfm <= cfg_interrupt_msixfm_v6pcie6;
cfg_pcie_link_state_n <= cfg_pcie_link_state_n_v6pcie22;
cfg_pmcsr_pme_en <= cfg_pmcsr_pme_en_v6pcie23;
cfg_pmcsr_pme_status <= cfg_pmcsr_pme_status_v6pcie24;
cfg_pmcsr_powerstate <= cfg_pmcsr_powerstate_v6pcie25;
cfg_msg_received <= cfg_msg_received_v6pcie9;
cfg_msg_data <= cfg_msg_data_v6pcie8;
cfg_msg_received_err_cor <= cfg_msg_received_err_cor_v6pcie18;
cfg_msg_received_err_non_fatal <= cfg_msg_received_err_non_fatal_v6pcie20;
cfg_msg_received_err_fatal <= cfg_msg_received_err_fatal_v6pcie19;
cfg_msg_received_pme_to_ack <= cfg_msg_received_pme_to_ack_v6pcie21;
cfg_msg_received_assert_inta <= cfg_msg_received_assert_inta_v6pcie10;
cfg_msg_received_assert_intb <= cfg_msg_received_assert_intb_v6pcie11;
cfg_msg_received_assert_intc <= cfg_msg_received_assert_intc_v6pcie12;
cfg_msg_received_assert_intd <= cfg_msg_received_assert_intd_v6pcie13;
cfg_msg_received_deassert_inta <= cfg_msg_received_deassert_inta_v6pcie14;
cfg_msg_received_deassert_intb <= cfg_msg_received_deassert_intb_v6pcie15;
cfg_msg_received_deassert_intc <= cfg_msg_received_deassert_intc_v6pcie16;
cfg_msg_received_deassert_intd <= cfg_msg_received_deassert_intd_v6pcie17;
pl_initial_link_width <= pl_initial_link_width_v6pcie32;
pl_lane_reversal_mode <= pl_lane_reversal_mode_v6pcie33;
pl_link_gen2_capable <= pl_link_gen2_capable_v6pcie34;
pl_link_partner_gen2_supported <= pl_link_partner_gen2_supported_v6pcie35;
pl_link_upcfg_capable <= pl_link_upcfg_capable_v6pcie36;
pl_ltssm_state <= pl_ltssm_state_v6pcie37;
pl_sel_link_rate <= pl_sel_link_rate_v6pcie39;
pl_sel_link_width <= pl_sel_link_width_v6pcie40;
pcie_drp_do <= pcie_drp_do_v6pcie29;
pcie_drp_drdy <= pcie_drp_drdy_v6pcie30;
-- assigns to outputs
cfg_status <= "0000000000000000";
cfg_command <= ("00000" &
cfg_cmd_intdis &
'0' &
cfg_cmd_serr_en &
"00000" &
cfg_cmd_bme &
cfg_cmd_mem_en &
cfg_cmd_io_en);
cfg_dstatus <= ("0000000000" &
cfg_trn_pending_n &
'0' &
cfg_dev_status_ur_detected &
cfg_dev_status_fatal_err_detected &
cfg_dev_status_nonfatal_err_detected &
cfg_dev_status_corr_err_detected);
cfg_dcommand <= ('0' &
cfg_dev_control_max_read_req &
cfg_dev_control_nosnoop_en &
cfg_dev_control_aux_power_en &
cfg_dev_control_phantom_en &
cfg_dev_control_ext_tag_en &
cfg_dev_control_maxpayload &
cfg_dev_control_enable_relaxed_order &
cfg_dev_control_ur_err_reporting_en &
cfg_dev_control_fatal_err_reporting_en &
cfg_dev_control_non_fatal_reporting_en &
cfg_dev_control_corr_err_reporting_en);
cfg_lstatus <= (cfg_link_status_auto_bandwidth_status &
cfg_link_status_bandwidth_status &
cfg_link_status_dll_active &
LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus &
cfg_link_status_link_training &
'0' &
("00" & cfg_link_status_negotiated_link_width) &
("00" & cfg_link_status_current_speed));
cfg_lcommand <= ("0000" &
cfg_link_control_auto_bandwidth_int_en &
cfg_link_control_bandwidth_int_en &
cfg_link_control_hw_auto_width_dis &
cfg_link_control_clock_pm_en &
cfg_link_control_extended_sync &
cfg_link_control_common_clock &
cfg_link_control_retrain_link &
cfg_link_control_linkdisable &
cfg_link_control_rcb &
'0' &
cfg_link_control_aspm_control);
cfg_dcommand2 <= ("00000000000" &
cfg_dev_control2_cpltimeout_dis &
cfg_dev_control2_cpltimeout_val);
-- Generate trn_lnk_up_n
trn_lnk_up_n_i : FDCP
generic map (
INIT => '1'
)
port map (
Q => trn_lnk_up_n_v6pcie48,
D => trn_lnk_up_n_int1,
C => trn_clk_v6pcie41,
CLR => '0',
PRE => '0'
);
trn_lnk_up_n_int_i : FDCP
generic map (
INIT => '1'
)
port map (
Q => trn_lnk_up_n_int1,
D => trn_lnk_up_n_int,
C => trn_clk_v6pcie41,
CLR => '0',
PRE => '0'
);
-- Generate trn_reset_n
v6pcie63 <= trn_reset_n_int1 and not(phy_rdy_n);
v6pcie64 <= not(sys_reset_n_d);
-- Generate trn_reset_n
trn_reset_n_i : FDCP
generic map (
INIT => '0'
)
port map (
Q => trn_reset_n_v6pcie54,
D => v6pcie63,
C => trn_clk_v6pcie41,
CLR => v6pcie64,
PRE => '0'
);
v6pcie65 <= trn_reset_n_int and not(phy_rdy_n);
v6pcie66 <= not(sys_reset_n_d);
trn_reset_n_int_i : FDCP
generic map (
INIT => '0'
)
port map (
Q => trn_reset_n_int1,
D => v6pcie65,
C => trn_clk_v6pcie41,
CLR => v6pcie66,
PRE => '0'
);
---------------------------------------------------------
-- PCI Express Reset Delay Module
---------------------------------------------------------
pcie_reset_delay_i : pcie_reset_delay_v6
generic map (
PL_FAST_TRAIN => PL_FAST_TRAIN,
REF_CLK_FREQ => REF_CLK_FREQ
)
port map (
ref_clk => TxOutClk_bufg,
sys_reset_n => sys_reset_n,
delayed_sys_reset_n => sys_reset_n_d
);
---------------------------------------------------------
-- PCI Express Clocking Module
---------------------------------------------------------
pcie_clocking_i : pcie_clocking_v6
generic map (
IS_ENDPOINT => FALSE,
CAP_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH_int,
CAP_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED_int,
REF_CLK_FREQ => REF_CLK_FREQ,
USER_CLK_FREQ => USER_CLK_FREQ
)
port map (
sys_clk => TxOutClk,
gt_pll_lock => gt_pll_lock,
sel_lnk_rate => pl_sel_link_rate_v6pcie39,
sel_lnk_width => pl_sel_link_width_v6pcie40,
sys_clk_bufg => TxOutClk_bufg,
pipe_clk => pipe_clk,
user_clk => user_clk,
block_clk => open,
drp_clk => drp_clk,
clock_locked => clock_locked
);
---------------------------------------------------------
-- Virtex6 PCI Express Block Module
---------------------------------------------------------
v6pcie67 <= not(phy_rdy_n);
v6pcie68 <= pl_directed_link_change;
v6pcie69 <= pl_directed_link_speed;
func_lvl_rstn <= not(pl_transmit_hot_rst) when DS_PORT_HOT_RST else
'1';
cm_rstn <= not(pl_transmit_hot_rst) when DS_PORT_HOT_RST else
'1';
pcie_2_0_i : pcie_2_0_v6_rp
generic map (
REF_CLK_FREQ => REF_CLK_FREQ,
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES,
LINK_CAP_MAX_LINK_WIDTH_int => LINK_CAP_MAX_LINK_WIDTH_int,
AER_BASE_PTR => AER_BASE_PTR,
AER_CAP_ECRC_CHECK_CAPABLE => AER_CAP_ECRC_CHECK_CAPABLE,
AER_CAP_ECRC_GEN_CAPABLE => AER_CAP_ECRC_GEN_CAPABLE,
AER_CAP_ID => AER_CAP_ID,
AER_CAP_INT_MSG_NUM_MSI => AER_CAP_INT_MSG_NUM_MSI,
AER_CAP_INT_MSG_NUM_MSIX => AER_CAP_INT_MSG_NUM_MSIX,
AER_CAP_NEXTPTR => AER_CAP_NEXTPTR,
AER_CAP_ON => AER_CAP_ON,
AER_CAP_PERMIT_ROOTERR_UPDATE => AER_CAP_PERMIT_ROOTERR_UPDATE,
AER_CAP_VERSION => AER_CAP_VERSION,
ALLOW_X8_GEN2 => ALLOW_X8_GEN2,
BAR0 => pad_gen(BAR0, 32),
BAR1 => pad_gen(BAR1, 32),
BAR2 => pad_gen(BAR2, 32),
BAR3 => pad_gen(BAR3, 32),
BAR4 => pad_gen(BAR4, 32),
BAR5 => pad_gen(BAR5, 32),
CAPABILITIES_PTR => CAPABILITIES_PTR,
CARDBUS_CIS_POINTER => pad_gen(CARDBUS_CIS_POINTER, 32),
CLASS_CODE => pad_gen(CLASS_CODE, 24),
CMD_INTX_IMPLEMENTED => CMD_INTX_IMPLEMENTED,
CPL_TIMEOUT_DISABLE_SUPPORTED => CPL_TIMEOUT_DISABLE_SUPPORTED,
CPL_TIMEOUT_RANGES_SUPPORTED => pad_gen(CPL_TIMEOUT_RANGES_SUPPORTED, 4),
CRM_MODULE_RSTS => CRM_MODULE_RSTS,
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE,
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE,
DEV_CAP_ENDPOINT_L0S_LATENCY => DEV_CAP_ENDPOINT_L0S_LATENCY,
DEV_CAP_ENDPOINT_L1_LATENCY => DEV_CAP_ENDPOINT_L1_LATENCY,
DEV_CAP_EXT_TAG_SUPPORTED => DEV_CAP_EXT_TAG_SUPPORTED,
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE => DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE,
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT,
DEV_CAP_ROLE_BASED_ERROR => DEV_CAP_ROLE_BASED_ERROR,
DEV_CAP_RSVD_14_12 => DEV_CAP_RSVD_14_12,
DEV_CAP_RSVD_17_16 => DEV_CAP_RSVD_17_16,
DEV_CAP_RSVD_31_29 => DEV_CAP_RSVD_31_29,
DEV_CONTROL_AUX_POWER_SUPPORTED => DEV_CONTROL_AUX_POWER_SUPPORTED,
DEVICE_ID => pad_gen(DEVICE_ID, 16),
DISABLE_ASPM_L1_TIMER => DISABLE_ASPM_L1_TIMER,
DISABLE_BAR_FILTERING => DISABLE_BAR_FILTERING,
DISABLE_ID_CHECK => DISABLE_ID_CHECK,
DISABLE_LANE_REVERSAL => DISABLE_LANE_REVERSAL,
DISABLE_RX_TC_FILTER => DISABLE_RX_TC_FILTER,
DISABLE_SCRAMBLING => DISABLE_SCRAMBLING,
DNSTREAM_LINK_NUM => DNSTREAM_LINK_NUM,
DSN_BASE_PTR => pad_gen(DSN_BASE_PTR, 12),
DSN_CAP_ID => DSN_CAP_ID,
DSN_CAP_NEXTPTR => pad_gen(DSN_CAP_NEXTPTR, 12),
DSN_CAP_ON => DSN_CAP_ON,
DSN_CAP_VERSION => DSN_CAP_VERSION,
ENABLE_MSG_ROUTE => pad_gen(ENABLE_MSG_ROUTE, 11),
ENABLE_RX_TD_ECRC_TRIM => ENABLE_RX_TD_ECRC_TRIM,
ENTER_RVRY_EI_L0 => ENTER_RVRY_EI_L0,
EXPANSION_ROM => pad_gen(EXPANSION_ROM, 32),
EXT_CFG_CAP_PTR => EXT_CFG_CAP_PTR,
EXT_CFG_XP_CAP_PTR => pad_gen(EXT_CFG_XP_CAP_PTR, 10),
HEADER_TYPE => pad_gen(HEADER_TYPE, 8),
INFER_EI => INFER_EI,
INTERRUPT_PIN => pad_gen(INTERRUPT_PIN, 8),
IS_SWITCH => IS_SWITCH,
LAST_CONFIG_DWORD => LAST_CONFIG_DWORD,
LINK_CAP_ASPM_SUPPORT => LINK_CAP_ASPM_SUPPORT,
LINK_CAP_CLOCK_POWER_MANAGEMENT => LINK_CAP_CLOCK_POWER_MANAGEMENT,
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP => LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP,
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP => LP_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP,
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1,
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2,
LINK_CAP_L0S_EXIT_LATENCY_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_GEN1,
LINK_CAP_L0S_EXIT_LATENCY_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_GEN2,
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1,
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2,
LINK_CAP_L1_EXIT_LATENCY_GEN1 => LINK_CAP_L1_EXIT_LATENCY_GEN1,
LINK_CAP_L1_EXIT_LATENCY_GEN2 => LINK_CAP_L1_EXIT_LATENCY_GEN2,
LINK_CAP_MAX_LINK_SPEED => pad_gen(LINK_CAP_MAX_LINK_SPEED, 4),
LINK_CAP_MAX_LINK_WIDTH => pad_gen(LINK_CAP_MAX_LINK_WIDTH, 6),
LINK_CAP_RSVD_23_22 => LINK_CAP_RSVD_23_22,
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE => LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE,
LINK_CONTROL_RCB => LINK_CONTROL_RCB,
LINK_CTRL2_DEEMPHASIS => LINK_CTRL2_DEEMPHASIS,
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE => LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE,
LINK_CTRL2_TARGET_LINK_SPEED => pad_gen(LINK_CTRL2_TARGET_LINK_SPEED, 4),
LINK_STATUS_SLOT_CLOCK_CONFIG => LINK_STATUS_SLOT_CLOCK_CONFIG,
LL_ACK_TIMEOUT => pad_gen(LL_ACK_TIMEOUT, 15),
LL_ACK_TIMEOUT_EN => LL_ACK_TIMEOUT_EN,
LL_ACK_TIMEOUT_FUNC => LL_ACK_TIMEOUT_FUNC,
LL_REPLAY_TIMEOUT => pad_gen(LL_REPLAY_TIMEOUT, 15),
LL_REPLAY_TIMEOUT_EN => LL_REPLAY_TIMEOUT_EN,
LL_REPLAY_TIMEOUT_FUNC => LL_REPLAY_TIMEOUT_FUNC,
LTSSM_MAX_LINK_WIDTH => pad_gen(LTSSM_MAX_LINK_WIDTH, 6),
MSI_BASE_PTR => MSI_BASE_PTR,
MSI_CAP_ID => MSI_CAP_ID,
MSI_CAP_MULTIMSGCAP => MSI_CAP_MULTIMSGCAP,
MSI_CAP_MULTIMSG_EXTENSION => MSI_CAP_MULTIMSG_EXTENSION,
MSI_CAP_NEXTPTR => MSI_CAP_NEXTPTR,
MSI_CAP_ON => MSI_CAP_ON,
MSI_CAP_PER_VECTOR_MASKING_CAPABLE => MSI_CAP_PER_VECTOR_MASKING_CAPABLE,
MSI_CAP_64_BIT_ADDR_CAPABLE => MSI_CAP_64_BIT_ADDR_CAPABLE,
MSIX_BASE_PTR => MSIX_BASE_PTR,
MSIX_CAP_ID => MSIX_CAP_ID,
MSIX_CAP_NEXTPTR => MSIX_CAP_NEXTPTR,
MSIX_CAP_ON => MSIX_CAP_ON,
MSIX_CAP_PBA_BIR => MSIX_CAP_PBA_BIR,
MSIX_CAP_PBA_OFFSET => pad_gen(MSIX_CAP_PBA_OFFSET, 29),
MSIX_CAP_TABLE_BIR => MSIX_CAP_TABLE_BIR,
MSIX_CAP_TABLE_OFFSET => pad_gen(MSIX_CAP_TABLE_OFFSET, 29),
MSIX_CAP_TABLE_SIZE => pad_gen(MSIX_CAP_TABLE_SIZE, 11),
N_FTS_COMCLK_GEN1 => N_FTS_COMCLK_GEN1,
N_FTS_COMCLK_GEN2 => N_FTS_COMCLK_GEN2,
N_FTS_GEN1 => N_FTS_GEN1,
N_FTS_GEN2 => N_FTS_GEN2,
PCIE_BASE_PTR => PCIE_BASE_PTR,
PCIE_CAP_CAPABILITY_ID => PCIE_CAP_CAPABILITY_ID,
PCIE_CAP_CAPABILITY_VERSION => PCIE_CAP_CAPABILITY_VERSION,
PCIE_CAP_DEVICE_PORT_TYPE => pad_gen(PCIE_CAP_DEVICE_PORT_TYPE, 4),
PCIE_CAP_INT_MSG_NUM => pad_gen(PCIE_CAP_INT_MSG_NUM, 5),
PCIE_CAP_NEXTPTR => pad_gen(PCIE_CAP_NEXTPTR, 8),
PCIE_CAP_ON => PCIE_CAP_ON,
PCIE_CAP_RSVD_15_14 => PCIE_CAP_RSVD_15_14,
PCIE_CAP_SLOT_IMPLEMENTED => PCIE_CAP_SLOT_IMPLEMENTED,
PCIE_REVISION => PCIE_REVISION,
PGL0_LANE => PGL0_LANE,
PGL1_LANE => PGL1_LANE,
PGL2_LANE => PGL2_LANE,
PGL3_LANE => PGL3_LANE,
PGL4_LANE => PGL4_LANE,
PGL5_LANE => PGL5_LANE,
PGL6_LANE => PGL6_LANE,
PGL7_LANE => PGL7_LANE,
PL_AUTO_CONFIG => PL_AUTO_CONFIG,
PL_FAST_TRAIN => PL_FAST_TRAIN,
PM_BASE_PTR => PM_BASE_PTR,
PM_CAP_AUXCURRENT => PM_CAP_AUXCURRENT,
PM_CAP_DSI => PM_CAP_DSI,
PM_CAP_D1SUPPORT => PM_CAP_D1SUPPORT,
PM_CAP_D2SUPPORT => PM_CAP_D2SUPPORT,
PM_CAP_ID => PM_CAP_ID,
PM_CAP_NEXTPTR => PM_CAP_NEXTPTR,
PM_CAP_ON => PM_CAP_ON,
PM_CAP_PME_CLOCK => PM_CAP_PME_CLOCK,
PM_CAP_PMESUPPORT => pad_gen(PM_CAP_PMESUPPORT, 5),
PM_CAP_RSVD_04 => PM_CAP_RSVD_04,
PM_CAP_VERSION => PM_CAP_VERSION,
PM_CSR_BPCCEN => PM_CSR_BPCCEN,
PM_CSR_B2B3 => PM_CSR_B2B3,
PM_CSR_NOSOFTRST => PM_CSR_NOSOFTRST,
PM_DATA_SCALE0 => pad_gen(PM_DATA_SCALE0, 2),
PM_DATA_SCALE1 => pad_gen(PM_DATA_SCALE1, 2),
PM_DATA_SCALE2 => pad_gen(PM_DATA_SCALE2, 2),
PM_DATA_SCALE3 => pad_gen(PM_DATA_SCALE3, 2),
PM_DATA_SCALE4 => pad_gen(PM_DATA_SCALE4, 2),
PM_DATA_SCALE5 => pad_gen(PM_DATA_SCALE5, 2),
PM_DATA_SCALE6 => pad_gen(PM_DATA_SCALE6, 2),
PM_DATA_SCALE7 => pad_gen(PM_DATA_SCALE7, 2),
PM_DATA0 => pad_gen(PM_DATA0, 8),
PM_DATA1 => pad_gen(PM_DATA1, 8),
PM_DATA2 => pad_gen(PM_DATA2, 8),
PM_DATA3 => pad_gen(PM_DATA3, 8),
PM_DATA4 => pad_gen(PM_DATA4, 8),
PM_DATA5 => pad_gen(PM_DATA5, 8),
PM_DATA6 => pad_gen(PM_DATA6, 8),
PM_DATA7 => pad_gen(PM_DATA7, 8),
RECRC_CHK => RECRC_CHK,
RECRC_CHK_TRIM => RECRC_CHK_TRIM,
REVISION_ID => pad_gen(REVISION_ID, 8),
ROOT_CAP_CRS_SW_VISIBILITY => ROOT_CAP_CRS_SW_VISIBILITY,
SELECT_DLL_IF => SELECT_DLL_IF,
SLOT_CAP_ATT_BUTTON_PRESENT => SLOT_CAP_ATT_BUTTON_PRESENT,
SLOT_CAP_ATT_INDICATOR_PRESENT => SLOT_CAP_ATT_INDICATOR_PRESENT,
SLOT_CAP_ELEC_INTERLOCK_PRESENT => SLOT_CAP_ELEC_INTERLOCK_PRESENT,
SLOT_CAP_HOTPLUG_CAPABLE => SLOT_CAP_HOTPLUG_CAPABLE,
SLOT_CAP_HOTPLUG_SURPRISE => SLOT_CAP_HOTPLUG_SURPRISE,
SLOT_CAP_MRL_SENSOR_PRESENT => SLOT_CAP_MRL_SENSOR_PRESENT,
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT => SLOT_CAP_NO_CMD_COMPLETED_SUPPORT,
SLOT_CAP_PHYSICAL_SLOT_NUM => SLOT_CAP_PHYSICAL_SLOT_NUM,
SLOT_CAP_POWER_CONTROLLER_PRESENT => SLOT_CAP_POWER_CONTROLLER_PRESENT,
SLOT_CAP_POWER_INDICATOR_PRESENT => SLOT_CAP_POWER_INDICATOR_PRESENT,
SLOT_CAP_SLOT_POWER_LIMIT_SCALE => SLOT_CAP_SLOT_POWER_LIMIT_SCALE,
SLOT_CAP_SLOT_POWER_LIMIT_VALUE => SLOT_CAP_SLOT_POWER_LIMIT_VALUE,
SPARE_BIT0 => SPARE_BIT0,
SPARE_BIT1 => SPARE_BIT1,
SPARE_BIT2 => SPARE_BIT2,
SPARE_BIT3 => SPARE_BIT3,
SPARE_BIT4 => SPARE_BIT4,
SPARE_BIT5 => SPARE_BIT5,
SPARE_BIT6 => SPARE_BIT6,
SPARE_BIT7 => SPARE_BIT7,
SPARE_BIT8 => SPARE_BIT8,
SPARE_BYTE0 => SPARE_BYTE0,
SPARE_BYTE1 => SPARE_BYTE1,
SPARE_BYTE2 => SPARE_BYTE2,
SPARE_BYTE3 => SPARE_BYTE3,
SPARE_WORD0 => SPARE_WORD0,
SPARE_WORD1 => SPARE_WORD1,
SPARE_WORD2 => SPARE_WORD2,
SPARE_WORD3 => SPARE_WORD3,
SUBSYSTEM_ID => pad_gen(SUBSYSTEM_ID, 16),
SUBSYSTEM_VENDOR_ID => pad_gen(SUBSYSTEM_VENDOR_ID, 16),
TL_RBYPASS => TL_RBYPASS,
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY,
TL_TFC_DISABLE => TL_TFC_DISABLE,
TL_TX_CHECKS_DISABLE => TL_TX_CHECKS_DISABLE,
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
TL_TX_RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY,
UPCONFIG_CAPABLE => UPCONFIG_CAPABLE,
UPSTREAM_FACING => UPSTREAM_FACING,
EXIT_LOOPBACK_ON_EI => EXIT_LOOPBACK_ON_EI,
UR_INV_REQ => UR_INV_REQ,
USER_CLK_FREQ => USER_CLK_FREQ,
VC_BASE_PTR => pad_gen(VC_BASE_PTR, 12),
VC_CAP_ID => VC_CAP_ID,
VC_CAP_NEXTPTR => pad_gen(VC_CAP_NEXTPTR, 12),
VC_CAP_ON => VC_CAP_ON,
VC_CAP_REJECT_SNOOP_TRANSACTIONS => VC_CAP_REJECT_SNOOP_TRANSACTIONS,
VC_CAP_VERSION => VC_CAP_VERSION,
VC0_CPL_INFINITE => VC0_CPL_INFINITE,
VC0_RX_RAM_LIMIT => pad_gen(VC0_RX_RAM_LIMIT, 13),
VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD,
VC0_TOTAL_CREDITS_CH => VC0_TOTAL_CREDITS_CH,
VC0_TOTAL_CREDITS_NPH => VC0_TOTAL_CREDITS_NPH,
VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_PD,
VC0_TOTAL_CREDITS_PH => VC0_TOTAL_CREDITS_PH,
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET,
VENDOR_ID => pad_gen(VENDOR_ID, 16),
VSEC_BASE_PTR => pad_gen(VSEC_BASE_PTR, 12),
VSEC_CAP_HDR_ID => VSEC_CAP_HDR_ID,
VSEC_CAP_HDR_LENGTH => VSEC_CAP_HDR_LENGTH,
VSEC_CAP_HDR_REVISION => VSEC_CAP_HDR_REVISION,
VSEC_CAP_ID => VSEC_CAP_ID,
VSEC_CAP_IS_LINK_VISIBLE => VSEC_CAP_IS_LINK_VISIBLE,
VSEC_CAP_NEXTPTR => pad_gen(VSEC_CAP_NEXTPTR, 12),
VSEC_CAP_ON => VSEC_CAP_ON,
VSEC_CAP_VERSION => VSEC_CAP_VERSION
)
port map (
PCIEXPRXN => pci_exp_rxn,
PCIEXPRXP => pci_exp_rxp,
PCIEXPTXN => pci_exp_txn_v6pcie27,
PCIEXPTXP => pci_exp_txp_v6pcie28,
SYSCLK => sys_clk,
TRNLNKUPN => trn_lnk_up_n_int,
TRNCLK => trn_clk_v6pcie41,
FUNDRSTN => sys_reset_n_d,
PHYRDYN => phy_rdy_n,
LNKCLKEN => open,
USERRSTN => trn_reset_n_int,
RECEIVEDFUNCLVLRSTN => rx_func_level_reset_n,
SYSRSTN => v6pcie67,
PLRSTN => '1',
DLRSTN => '1',
TLRSTN => '1',
FUNCLVLRSTN => func_lvl_rstn,
CMRSTN => cm_rstn,
CMSTICKYRSTN => '1',
TRNRBARHITN => trn_rbar_hit_n_v6pcie49,
TRNRD => trn_rd_v6pcie50,
TRNRECRCERRN => trn_recrc_err_n_v6pcie51,
TRNREOFN => trn_reof_n_v6pcie52,
TRNRERRFWDN => trn_rerrfwd_n_v6pcie53,
TRNRREMN => trn_rrem_n_v6pcie55,
TRNRSOFN => trn_rsof_n_v6pcie56,
TRNRSRCDSCN => trn_rsrc_dsc_n_v6pcie57,
TRNRSRCRDYN => trn_rsrc_rdy_n_v6pcie58,
TRNRDSTRDYN => trn_rdst_rdy_n,
TRNRNPOKN => trn_rnp_ok_n,
TRNTBUFAV => trn_tbuf_av_v6pcie59,
TRNTCFGREQN => trn_tcfg_req_n_v6pcie60,
TRNTDLLPDSTRDYN => open,
TRNTDSTRDYN => trn_tdst_rdy_n_v6pcie61,
TRNTERRDROPN => trn_terr_drop_n_v6pcie62,
TRNTCFGGNTN => trn_tcfg_gnt_n,
TRNTD => trn_td,
TRNTDLLPDATA => "00000000000000000000000000000000",
TRNTDLLPSRCRDYN => '1',
TRNTECRCGENN => '1',
TRNTEOFN => trn_teof_n,
TRNTERRFWDN => trn_terrfwd_n,
TRNTREMN => trn_trem_n,
TRNTSOFN => trn_tsof_n,
TRNTSRCDSCN => trn_tsrc_dsc_n,
TRNTSRCRDYN => trn_tsrc_rdy_n,
TRNTSTRN => trn_tstr_n,
TRNFCCPLD => trn_fc_cpld_v6pcie42,
TRNFCCPLH => trn_fc_cplh_v6pcie43,
TRNFCNPD => trn_fc_npd_v6pcie44,
TRNFCNPH => trn_fc_nph_v6pcie45,
TRNFCPD => trn_fc_pd_v6pcie46,
TRNFCPH => trn_fc_ph_v6pcie47,
TRNFCSEL => trn_fc_sel,
CFGAERECRCCHECKEN => open,
CFGAERECRCGENEN => open,
CFGCOMMANDBUSMASTERENABLE => cfg_cmd_bme,
CFGCOMMANDINTERRUPTDISABLE => cfg_cmd_intdis,
CFGCOMMANDIOENABLE => cfg_cmd_io_en,
CFGCOMMANDMEMENABLE => cfg_cmd_mem_en,
CFGCOMMANDSERREN => cfg_cmd_serr_en,
CFGDEVCONTROLAUXPOWEREN => cfg_dev_control_aux_power_en,
CFGDEVCONTROLCORRERRREPORTINGEN => cfg_dev_control_corr_err_reporting_en,
CFGDEVCONTROLENABLERO => cfg_dev_control_enable_relaxed_order,
CFGDEVCONTROLEXTTAGEN => cfg_dev_control_ext_tag_en,
CFGDEVCONTROLFATALERRREPORTINGEN => cfg_dev_control_fatal_err_reporting_en,
CFGDEVCONTROLMAXPAYLOAD => cfg_dev_control_maxpayload,
CFGDEVCONTROLMAXREADREQ => cfg_dev_control_max_read_req,
CFGDEVCONTROLNONFATALREPORTINGEN => cfg_dev_control_non_fatal_reporting_en,
CFGDEVCONTROLNOSNOOPEN => cfg_dev_control_nosnoop_en,
CFGDEVCONTROLPHANTOMEN => cfg_dev_control_phantom_en,
CFGDEVCONTROLURERRREPORTINGEN => cfg_dev_control_ur_err_reporting_en,
CFGDEVCONTROL2CPLTIMEOUTDIS => cfg_dev_control2_cpltimeout_dis,
CFGDEVCONTROL2CPLTIMEOUTVAL => cfg_dev_control2_cpltimeout_val,
CFGDEVSTATUSCORRERRDETECTED => cfg_dev_status_corr_err_detected,
CFGDEVSTATUSFATALERRDETECTED => cfg_dev_status_fatal_err_detected,
CFGDEVSTATUSNONFATALERRDETECTED => cfg_dev_status_nonfatal_err_detected,
CFGDEVSTATUSURDETECTED => cfg_dev_status_ur_detected,
CFGDO => cfg_do,
CFGERRAERHEADERLOGSETN => open,
CFGERRCPLRDYN => cfg_err_cpl_rdy_n_v6pcie1,
CFGINTERRUPTDO => cfg_interrupt_do_v6pcie2,
CFGINTERRUPTMMENABLE => cfg_interrupt_mmenable_v6pcie3,
CFGINTERRUPTMSIENABLE => cfg_interrupt_msienable_v6pcie4,
CFGINTERRUPTMSIXENABLE => cfg_interrupt_msixenable_v6pcie5,
CFGINTERRUPTMSIXFM => cfg_interrupt_msixfm_v6pcie6,
CFGINTERRUPTRDYN => cfg_interrupt_rdy_n_v6pcie7,
CFGLINKCONTROLRCB => cfg_link_control_rcb,
CFGLINKCONTROLASPMCONTROL => cfg_link_control_aspm_control,
CFGLINKCONTROLAUTOBANDWIDTHINTEN => cfg_link_control_auto_bandwidth_int_en,
CFGLINKCONTROLBANDWIDTHINTEN => cfg_link_control_bandwidth_int_en,
CFGLINKCONTROLCLOCKPMEN => cfg_link_control_clock_pm_en,
CFGLINKCONTROLCOMMONCLOCK => cfg_link_control_common_clock,
CFGLINKCONTROLEXTENDEDSYNC => cfg_link_control_extended_sync,
CFGLINKCONTROLHWAUTOWIDTHDIS => cfg_link_control_hw_auto_width_dis,
CFGLINKCONTROLLINKDISABLE => cfg_link_control_linkdisable,
CFGLINKCONTROLRETRAINLINK => cfg_link_control_retrain_link,
CFGLINKSTATUSAUTOBANDWIDTHSTATUS => cfg_link_status_auto_bandwidth_status,
CFGLINKSTATUSBANDWITHSTATUS => cfg_link_status_bandwidth_status,
CFGLINKSTATUSCURRENTSPEED => cfg_link_status_current_speed,
CFGLINKSTATUSDLLACTIVE => cfg_link_status_dll_active,
CFGLINKSTATUSLINKTRAINING => cfg_link_status_link_training,
CFGLINKSTATUSNEGOTIATEDWIDTH => cfg_link_status_negotiated_link_width,
CFGMSGDATA => cfg_msg_data_v6pcie8,
CFGMSGRECEIVED => cfg_msg_received_v6pcie9,
CFGMSGRECEIVEDASSERTINTA => cfg_msg_received_assert_inta_v6pcie10,
CFGMSGRECEIVEDASSERTINTB => cfg_msg_received_assert_intb_v6pcie11,
CFGMSGRECEIVEDASSERTINTC => cfg_msg_received_assert_intc_v6pcie12,
CFGMSGRECEIVEDASSERTINTD => cfg_msg_received_assert_intd_v6pcie13,
CFGMSGRECEIVEDDEASSERTINTA => cfg_msg_received_deassert_inta_v6pcie14,
CFGMSGRECEIVEDDEASSERTINTB => cfg_msg_received_deassert_intb_v6pcie15,
CFGMSGRECEIVEDDEASSERTINTC => cfg_msg_received_deassert_intc_v6pcie16,
CFGMSGRECEIVEDDEASSERTINTD => cfg_msg_received_deassert_intd_v6pcie17,
CFGMSGRECEIVEDERRCOR => cfg_msg_received_err_cor_v6pcie18,
CFGMSGRECEIVEDERRFATAL => cfg_msg_received_err_fatal_v6pcie19,
CFGMSGRECEIVEDERRNONFATAL => cfg_msg_received_err_non_fatal_v6pcie20,
CFGMSGRECEIVEDPMASNAK => open,
CFGMSGRECEIVEDPMETO => open,
CFGMSGRECEIVEDPMETOACK => cfg_msg_received_pme_to_ack_v6pcie21,
CFGMSGRECEIVEDPMPME => open,
CFGMSGRECEIVEDSETSLOTPOWERLIMIT => open,
CFGMSGRECEIVEDUNLOCK => open,
CFGPCIELINKSTATE => cfg_pcie_link_state_n_v6pcie22,
CFGPMRCVASREQL1N => open,
CFGPMRCVENTERL1N => open,
CFGPMRCVENTERL23N => open,
CFGPMRCVREQACKN => open,
CFGPMCSRPMEEN => cfg_pmcsr_pme_en_v6pcie23,
CFGPMCSRPMESTATUS => cfg_pmcsr_pme_status_v6pcie24,
CFGPMCSRPOWERSTATE => cfg_pmcsr_powerstate_v6pcie25,
CFGRDWRDONEN => cfg_rd_wr_done_n,
CFGSLOTCONTROLELECTROMECHILCTLPULSE => open,
CFGTRANSACTION => open,
CFGTRANSACTIONADDR => open,
CFGTRANSACTIONTYPE => open,
CFGVCTCVCMAP => open,
CFGBYTEENN => cfg_byte_en_n,
CFGDI => cfg_di,
CFGDSBUSNUMBER => cfg_ds_bus_number,
CFGDSDEVICENUMBER => cfg_ds_device_number,
CFGDSFUNCTIONNUMBER => "000",
CFGDSN => cfg_dsn,
CFGDWADDR => cfg_dwaddr,
CFGERRACSN => '1',
CFGERRAERHEADERLOG => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
CFGERRCORN => cfg_err_cor_n,
CFGERRCPLABORTN => cfg_err_cpl_abort_n,
CFGERRCPLTIMEOUTN => cfg_err_cpl_timeout_n,
CFGERRCPLUNEXPECTN => cfg_err_cpl_unexpect_n,
CFGERRECRCN => cfg_err_ecrc_n,
CFGERRLOCKEDN => cfg_err_locked_n,
CFGERRPOSTEDN => cfg_err_posted_n,
CFGERRTLPCPLHEADER => cfg_err_tlp_cpl_header,
CFGERRURN => cfg_err_ur_n,
CFGINTERRUPTASSERTN => cfg_interrupt_assert_n,
CFGINTERRUPTDI => cfg_interrupt_di,
CFGINTERRUPTN => cfg_interrupt_n,
CFGPMDIRECTASPML1N => '1',
CFGPMSENDPMACKN => '1',
CFGPMSENDPMETON => cfg_pm_send_pme_to_n,
CFGPMSENDPMNAKN => '1',
CFGPMTURNOFFOKN => '1',
CFGPMWAKEN => '1',
CFGPORTNUMBER => "00000000",
CFGRDENN => cfg_rd_en_n,
CFGTRNPENDINGN => cfg_trn_pending_n,
CFGWRENN => cfg_wr_en_n,
CFGWRREADONLYN => '1',
CFGWRRW1CASRWN => '1',
PLINITIALLINKWIDTH => pl_initial_link_width_v6pcie32,
PLLANEREVERSALMODE => pl_lane_reversal_mode_v6pcie33,
PLLINKGEN2CAP => pl_link_gen2_capable_v6pcie34,
PLLINKPARTNERGEN2SUPPORTED => pl_link_partner_gen2_supported_v6pcie35,
PLLINKUPCFGCAP => pl_link_upcfg_capable_v6pcie36,
PLLTSSMSTATE => pl_ltssm_state_v6pcie37,
PLPHYLNKUPN => pl_phy_lnk_up_n,
PLRECEIVEDHOTRST => open,
PLRXPMSTATE => open,
PLSELLNKRATE => pl_sel_link_rate_v6pcie39,
PLSELLNKWIDTH => pl_sel_link_width_v6pcie40,
PLTXPMSTATE => open,
PLDIRECTEDLINKAUTON => pl_directed_link_auton,
PLDIRECTEDLINKCHANGE => v6pcie68,
PLDIRECTEDLINKSPEED => v6pcie69,
PLDIRECTEDLINKWIDTH => pl_directed_link_width,
PLDOWNSTREAMDEEMPHSOURCE => '0',
PLUPSTREAMPREFERDEEMPH => pl_upstream_prefer_deemph,
PLTRANSMITHOTRST => pl_transmit_hot_rst,
DBGSCLRA => open,
DBGSCLRB => open,
DBGSCLRC => open,
DBGSCLRD => open,
DBGSCLRE => open,
DBGSCLRF => open,
DBGSCLRG => open,
DBGSCLRH => open,
DBGSCLRI => open,
DBGSCLRJ => open,
DBGSCLRK => open,
DBGVECA => open,
DBGVECB => open,
DBGVECC => open,
PLDBGVEC => open,
DBGMODE => "00",
DBGSUBMODE => '0',
PLDBGMODE => "000",
PCIEDRPDO => pcie_drp_do_v6pcie29,
PCIEDRPDRDY => pcie_drp_drdy_v6pcie30,
PCIEDRPCLK => pcie_drp_clk,
PCIEDRPDADDR => pcie_drp_daddr,
PCIEDRPDEN => pcie_drp_den,
PCIEDRPDI => pcie_drp_di,
PCIEDRPDWE => pcie_drp_dwe,
GTPLLLOCK => gt_pll_lock,
PIPECLK => pipe_clk,
USERCLK => user_clk,
DRPCLK => drp_clk,
CLOCKLOCKED => clock_locked,
TxOutClk => TxOutClk );
end v6_pcie;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc265.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p02n01i00265ent IS
END c03s01b03x00p02n01i00265ent;
ARCHITECTURE c03s01b03x00p02n01i00265arch OF c03s01b03x00p02n01i00265ent IS
type J is -- physical type decl
range 0 to 1000
units
A;
B = 10 A;
C = 10 B;
D = 10 C;
end units;
type J1 is access J; -- Success_here
BEGIN
TESTING: PROCESS
variable k : J;
BEGIN
k := 10 C;
assert NOT( k=100 B )
report "***PASSED TEST: c03s01b03x00p02n01i00265"
severity NOTE;
assert ( k=100 B)
report "***FAILED TEST: c03s01b03x00p02n01i00265 - In the physical type definition, the range constraint is immediately followed by reserved word units."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p02n01i00265arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc265.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p02n01i00265ent IS
END c03s01b03x00p02n01i00265ent;
ARCHITECTURE c03s01b03x00p02n01i00265arch OF c03s01b03x00p02n01i00265ent IS
type J is -- physical type decl
range 0 to 1000
units
A;
B = 10 A;
C = 10 B;
D = 10 C;
end units;
type J1 is access J; -- Success_here
BEGIN
TESTING: PROCESS
variable k : J;
BEGIN
k := 10 C;
assert NOT( k=100 B )
report "***PASSED TEST: c03s01b03x00p02n01i00265"
severity NOTE;
assert ( k=100 B)
report "***FAILED TEST: c03s01b03x00p02n01i00265 - In the physical type definition, the range constraint is immediately followed by reserved word units."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p02n01i00265arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc265.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p02n01i00265ent IS
END c03s01b03x00p02n01i00265ent;
ARCHITECTURE c03s01b03x00p02n01i00265arch OF c03s01b03x00p02n01i00265ent IS
type J is -- physical type decl
range 0 to 1000
units
A;
B = 10 A;
C = 10 B;
D = 10 C;
end units;
type J1 is access J; -- Success_here
BEGIN
TESTING: PROCESS
variable k : J;
BEGIN
k := 10 C;
assert NOT( k=100 B )
report "***PASSED TEST: c03s01b03x00p02n01i00265"
severity NOTE;
assert ( k=100 B)
report "***FAILED TEST: c03s01b03x00p02n01i00265 - In the physical type definition, the range constraint is immediately followed by reserved word units."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p02n01i00265arch;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic; -- gnd = disable
dqs_pad : out std_logic; -- DQS pad
dqsn_pad : out std_logic -- DQSN pad
);
end;
architecture rtl of adqsout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component cycloneiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component cycloneiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
port(
i : in std_logic := '0';
oe : in std_logic := '1';
--devoe : in std_logic := '1';
o : out std_logic;
obar : out std_logic--;
--seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_reg, dqs_buf, dqsn_buf, dqs_oe_n : std_logic;
signal dqs_oe_reg, dqs_oe_reg_n, dqs_oct_reg : std_logic;
signal dqsn_oe_reg, dqsn_oe_reg_n, dqsn_oct_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQS output register --------------------------------------------------------------
dqs_reg0 : cycloneiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => dqs,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Outout enable and DQS ------------------------------------------------------------
-- ****** ????????? invert dqs_oe also ??????
dqs_oe_n <= not dqs_oe;
dqs_oe_reg0 : cycloneiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqs_oe_reg_n <= not dqs_oe_reg;
-- Out buffer (DQS) -----------------------------------------------------------------
dqs_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => dqs_reg,
oe => dqs_oe_reg_n,
--devoe => vcc,
o => dqs_pad,
obar => open
--seriesterminationcontrol => gnd,
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic; -- gnd = disable
dqs_pad : out std_logic; -- DQS pad
dqsn_pad : out std_logic -- DQSN pad
);
end;
architecture rtl of adqsout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component cycloneiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component cycloneiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
port(
i : in std_logic := '0';
oe : in std_logic := '1';
--devoe : in std_logic := '1';
o : out std_logic;
obar : out std_logic--;
--seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_reg, dqs_buf, dqsn_buf, dqs_oe_n : std_logic;
signal dqs_oe_reg, dqs_oe_reg_n, dqs_oct_reg : std_logic;
signal dqsn_oe_reg, dqsn_oe_reg_n, dqsn_oct_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQS output register --------------------------------------------------------------
dqs_reg0 : cycloneiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => dqs,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Outout enable and DQS ------------------------------------------------------------
-- ****** ????????? invert dqs_oe also ??????
dqs_oe_n <= not dqs_oe;
dqs_oe_reg0 : cycloneiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqs_oe_reg_n <= not dqs_oe_reg;
-- Out buffer (DQS) -----------------------------------------------------------------
dqs_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => dqs_reg,
oe => dqs_oe_reg_n,
--devoe => vcc,
o => dqs_pad,
obar => open
--seriesterminationcontrol => gnd,
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic; -- gnd = disable
dqs_pad : out std_logic; -- DQS pad
dqsn_pad : out std_logic -- DQSN pad
);
end;
architecture rtl of adqsout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component cycloneiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component cycloneiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
port(
i : in std_logic := '0';
oe : in std_logic := '1';
--devoe : in std_logic := '1';
o : out std_logic;
obar : out std_logic--;
--seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_reg, dqs_buf, dqsn_buf, dqs_oe_n : std_logic;
signal dqs_oe_reg, dqs_oe_reg_n, dqs_oct_reg : std_logic;
signal dqsn_oe_reg, dqsn_oe_reg_n, dqsn_oct_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQS output register --------------------------------------------------------------
dqs_reg0 : cycloneiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => dqs,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Outout enable and DQS ------------------------------------------------------------
-- ****** ????????? invert dqs_oe also ??????
dqs_oe_n <= not dqs_oe;
dqs_oe_reg0 : cycloneiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqs_oe_reg_n <= not dqs_oe_reg;
-- Out buffer (DQS) -----------------------------------------------------------------
dqs_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => dqs_reg,
oe => dqs_oe_reg_n,
--devoe => vcc,
o => dqs_pad,
obar => open
--seriesterminationcontrol => gnd,
);
end;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_intc.vhd
-- Version: v3.1
-- Description: Interrupt controller interfaced to AXI.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_intc.vhd (wrapper for top level)
-- -- axi_lite_ipif.vhd
-- -- intc_core.vhd
--
-------------------------------------------------------------------------------
-- Author: PB
-- History:
-- PB 07/29/09
-- ^^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
-- PB 03/26/10
--
-- - updated based on the xps_intc_v2_01_a
-- PB 09/21/10
--
-- - updated the axi_lite_ipif from v1.00.a to v1.01.a
-- ~~~~~~
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-- ^^^^^^^
-- SA 03/25/13
--
-- 1. Added software interrupt support
-- ~~~~~~
-- SA 09/05/13
--
-- 1. Added support for nested interrupts using ILR register in v4.1
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------
-- Library axi_lite_ipif_v3_0 is used because it contains the
-- axi_lite_ipif which interraces intc_core to AXI.
-------------------------------------------------------------------------
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------
-- Library axi_intc_v4_1 is used because it contains the intc_core.
-- The complete interrupt controller logic is designed in intc_core.
-------------------------------------------------------------------------
library axi_intc_v4_1;
use axi_intc_v4_1.intc_core;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- System Parameter
-- C_FAMILY -- Target FPGA family
-- AXI Parameters
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- Intc Parameters
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_NUM_SW_INTR -- Number of software interrupts
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_ASYNC_INTR -- Interrupt is asynchronous (0-sync/1-async)
-- C_NUM_SYNC_FF -- Number of synchronization flip-flops for async interrupts
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_HAS_ILR -- Set to 1 if has Interrupt Level Register for nested interupt support
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
-- C_IVR_RESET_VALUE -- Reset value for the vectroed interrupt registers in RAM
-- C_DISABLE_SYNCHRONIZERS -- If the processor clock and axi clock are of same
-- value then user can decide to disable this
-- C_MB_CLK_NOT_CONNECTED -- If the processor clock is not connected or used in design
-- C_HAS_FAST -- If user wants to choose the fast interrupt mode of the core
-- -- then it is needed to have this paraemter set. Default is Standard Mode interrupt
-- C_ENABLE_ASYNC -- This parameter is used only for Vivado standalone mode of the core, not used in RTL
-- C_EN_CASCADE_MODE -- If no. of interrupts goes beyond 32, then this parameter need to set
-- C_CASCADE_MASTER -- If cascade mode is set, then this parameter should be set to the first instance
-- -- of the core which is connected to the processor
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clocks and reset
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset - Active Low Reset
-- Axi interface signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- Intc Interface Signals
-- intr -- Input Interruput request
-- irq -- Output Interruput request
-- processor_clk -- in put same as processor clock
-- processor_rst -- in put same as processor reset
-- processor_ack -- input Connected to processor ACK
-- interrupt_address -- output Connected to processor interrupt address pins
-- interrupt_address_in-- Input this is coming from lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-- processor_ack_out -- Output this is going to lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
entity axi_intc is
generic
(
-- System Parameter
C_FAMILY : string := "virtex6";
C_INSTANCE : string := "axi_intc_inst";
-- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 9; -- 9
C_S_AXI_DATA_WIDTH : integer := 32;
-- Intc Parameters
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_NUM_SW_INTR : integer range 0 to 31 := 0;
C_KIND_OF_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_ASYNC_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_NUM_SYNC_FF : integer range 0 to 7 := 2;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000";
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_HAS_ILR : integer range 0 to 1 := 0;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1';
C_DISABLE_SYNCHRONIZERS : integer range 0 to 1 := 0;
C_MB_CLK_NOT_CONNECTED : integer range 0 to 1 := 1;
C_HAS_FAST : integer range 0 to 1 := 0;
-- The below parameter is unused in RTL but required in Vivado Native
C_ENABLE_ASYNC : integer range 0 to 1 := 0; --not used for EDK, used only for Vivado
--
C_EN_CASCADE_MODE : integer range 0 to 1 := 0; -- default no cascade mode, if set enable cascade mode
C_CASCADE_MASTER : integer range 0 to 1 := 0 -- default slave, if set become cascade master and connects ports to Processor
--
);
port
(
-- system signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- axi interface signals
s_axi_awaddr : in std_logic_vector (8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector (31 downto 0);
s_axi_wstrb : in std_logic_vector (3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector (8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector (31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Intc iInterface signals
intr : in std_logic_vector(C_NUM_INTR_INPUTS-1 downto 0);
processor_clk : in std_logic; --- MB Clk, clock from MicroBlaze
processor_rst : in std_logic; --- MB rst, reset from MicroBlaze
irq : out std_logic;
processor_ack : in std_logic_vector(1 downto 0); --- newly added port
interrupt_address : out std_logic_vector(31 downto 0); --- newly added port
--
interrupt_address_in : in std_logic_vector(31 downto 0);
processor_ack_out : out std_logic_vector(1 downto 0)
--
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of S_AXI_ACLK : signal is "10000";
ATTRIBUTE MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
-- SIGIS attribute for specifying clocks,interrupts,resets for EDK
ATTRIBUTE IP_GROUP : string;
ATTRIBUTE IP_GROUP of axi_intc : entity is "LOGICORE";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE of axi_intc : entity is "PERIPHERAL";
ATTRIBUTE HDL : string;
ATTRIBUTE HDL of axi_intc : entity is "VHDL";
ATTRIBUTE STYLE : string;
ATTRIBUTE STYLE of axi_intc : entity is "HDL";
ATTRIBUTE IMP_NETLIST : string;
ATTRIBUTE IMP_NETLIST of axi_intc : entity is "TRUE";
ATTRIBUTE RUN_NGCBUILD : string;
ATTRIBUTE RUN_NGCBUILD of axi_intc : entity is "TRUE";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of S_AXI_ACLK : signal is "Clk";
ATTRIBUTE SIGIS of S_AXI_ARESETN : signal is "Rstn";
end axi_intc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_intc is
---------------------------------------------------------------------------
-- Component Declarations
---------------------------------------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(31 downto 0)
:= (others => '0');
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := (0 => 1);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= (
ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & (X"00000000" or X"0000003F"), --- changed the high address
ZERO_ADDR_PAD & (X"00000000" or X"00000100"), --- changed the high address
ZERO_ADDR_PAD & (X"00000000" or X"0000017F") --- changed the high address
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (16, 1); --- changed no. of chip enables
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000017F"; --- changed min memory size required
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 8;
constant RESET_ACTIVE : std_logic := '0';
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
signal register_addr : std_logic_vector(6 downto 0); -- changed
signal read_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal write_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal bus2ip_addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector((
(ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(
calc_num_ce(ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(
calc_num_ce(ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_be : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal word_access : std_logic;
signal ip2bus_rdack_int : std_logic;
signal ip2bus_wrack_int : std_logic;
signal ip2bus_rdack_int_d1 : std_logic;
signal ip2bus_wrack_int_d1 : std_logic;
signal ip2bus_rdack_prev2 : std_logic;
signal ip2bus_wrack_prev2 : std_logic;
function Or128_vec2stdlogic (vec_in : std_logic_vector) return std_logic is
variable or_out : std_logic := '0';
begin
for i in 0 to 16 loop
or_out := vec_in(i) or or_out;
end loop;
return or_out;
end function Or128_vec2stdlogic;
------------------------------------------------------------------------------
-----
begin
-----
assert C_NUM_SW_INTR + C_NUM_INTR_INPUTS <= 32
report "C_NUM_SW_INTR + C_NUM_INTR_INPUTS must be less than or equal to 32"
severity error;
register_addr <= bus2ip_addr(8 downto 2); -- changed the range as no. of register increased
--- Internal ack signals
ip2bus_rdack_int <= Or128_vec2stdlogic(bus2ip_rdce); -- changed, utilized function as no. chip enables increased
ip2bus_wrack_int <= Or128_vec2stdlogic(bus2ip_wrce); -- changed, utilized function as no. chip enables increased
-- Error signal generation
word_access <= bus2ip_be(0) and
bus2ip_be(1) and
bus2ip_be(2) and
bus2ip_be(3);
ip2bus_error <= not word_access;
--------------------------------------------------------------------------
-- Process DACK_DELAY_P for generating write and read data acknowledge
-- signals.
--------------------------------------------------------------------------
DACK_DELAY_P: process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk='1' then
if bus2ip_resetn = RESET_ACTIVE then
ip2bus_rdack_int_d1 <= '0';
ip2bus_wrack_int_d1 <= '0';
ip2bus_rdack <= '0';
ip2bus_wrack <= '0';
else
ip2bus_rdack_int_d1 <= ip2bus_rdack_int;
ip2bus_wrack_int_d1 <= ip2bus_wrack_int;
ip2bus_rdack <= ip2bus_rdack_prev2;
ip2bus_wrack <= ip2bus_wrack_prev2;
end if;
end if;
end process DACK_DELAY_P;
-- Detecting rising edge by creating one shot
ip2bus_rdack_prev2 <= ip2bus_rdack_int and (not ip2bus_rdack_int_d1);
ip2bus_wrack_prev2 <= ip2bus_wrack_int and (not ip2bus_wrack_int_d1);
---------------------------------------------------------------------------
-- Component Instantiations
---------------------------------------------------------------------------
-----------------------------------------------------------------
-- Instantiating intc_core from axi_intc_v4_1
-----------------------------------------------------------------
INTC_CORE_I : entity axi_intc_v4_1.intc_core
generic map
(
C_FAMILY => C_FAMILY,
C_DWIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_INTR_INPUTS => C_NUM_INTR_INPUTS,
C_NUM_SW_INTR => C_NUM_SW_INTR,
C_KIND_OF_INTR => C_KIND_OF_INTR,
C_KIND_OF_EDGE => C_KIND_OF_EDGE,
C_KIND_OF_LVL => C_KIND_OF_LVL,
C_ASYNC_INTR => C_ASYNC_INTR,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HAS_IPR => C_HAS_IPR,
C_HAS_SIE => C_HAS_SIE,
C_HAS_CIE => C_HAS_CIE,
C_HAS_IVR => C_HAS_IVR,
C_HAS_ILR => C_HAS_ILR,
C_IRQ_IS_LEVEL => C_IRQ_IS_LEVEL,
C_IRQ_ACTIVE => C_IRQ_ACTIVE,
C_DISABLE_SYNCHRONIZERS => C_DISABLE_SYNCHRONIZERS,
C_MB_CLK_NOT_CONNECTED => C_MB_CLK_NOT_CONNECTED,
C_HAS_FAST => C_HAS_FAST,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE,
--
C_EN_CASCADE_MODE => C_EN_CASCADE_MODE,
C_CASCADE_MASTER => C_CASCADE_MASTER
--
)
port map
(
-- Intc Interface Signals
Clk => bus2ip_clk,
Rst_n => bus2ip_resetn,
Intr => intr,
Reg_addr => register_addr,
Bus2ip_rdce => bus2ip_rdce,
Bus2ip_wrce => bus2ip_wrce,
Wr_data => write_data,
Rd_data => read_data,
Processor_clk => processor_clk,
Processor_rst => processor_rst,
Irq => Irq,
Processor_ack => processor_ack,
Interrupt_address => interrupt_address,
Interrupt_address_in => interrupt_address_in,
Processor_ack_out => processor_ack_out
);
-----------------------------------------------------------------
--Instantiating axi_lite_ipif from axi_lite_ipif_v3_0
-----------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY=> ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
--System signals
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
-- AXI interface signals
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- Controls to the IP/IPIF modules
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce,
Bus2IP_Data => write_data,
IP2Bus_Data => read_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error
);
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_intc.vhd
-- Version: v3.1
-- Description: Interrupt controller interfaced to AXI.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_intc.vhd (wrapper for top level)
-- -- axi_lite_ipif.vhd
-- -- intc_core.vhd
--
-------------------------------------------------------------------------------
-- Author: PB
-- History:
-- PB 07/29/09
-- ^^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
-- PB 03/26/10
--
-- - updated based on the xps_intc_v2_01_a
-- PB 09/21/10
--
-- - updated the axi_lite_ipif from v1.00.a to v1.01.a
-- ~~~~~~
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-- ^^^^^^^
-- SA 03/25/13
--
-- 1. Added software interrupt support
-- ~~~~~~
-- SA 09/05/13
--
-- 1. Added support for nested interrupts using ILR register in v4.1
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------
-- Library axi_lite_ipif_v3_0 is used because it contains the
-- axi_lite_ipif which interraces intc_core to AXI.
-------------------------------------------------------------------------
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------
-- Library axi_intc_v4_1 is used because it contains the intc_core.
-- The complete interrupt controller logic is designed in intc_core.
-------------------------------------------------------------------------
library axi_intc_v4_1;
use axi_intc_v4_1.intc_core;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- System Parameter
-- C_FAMILY -- Target FPGA family
-- AXI Parameters
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- Intc Parameters
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_NUM_SW_INTR -- Number of software interrupts
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_ASYNC_INTR -- Interrupt is asynchronous (0-sync/1-async)
-- C_NUM_SYNC_FF -- Number of synchronization flip-flops for async interrupts
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_HAS_ILR -- Set to 1 if has Interrupt Level Register for nested interupt support
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
-- C_IVR_RESET_VALUE -- Reset value for the vectroed interrupt registers in RAM
-- C_DISABLE_SYNCHRONIZERS -- If the processor clock and axi clock are of same
-- value then user can decide to disable this
-- C_MB_CLK_NOT_CONNECTED -- If the processor clock is not connected or used in design
-- C_HAS_FAST -- If user wants to choose the fast interrupt mode of the core
-- -- then it is needed to have this paraemter set. Default is Standard Mode interrupt
-- C_ENABLE_ASYNC -- This parameter is used only for Vivado standalone mode of the core, not used in RTL
-- C_EN_CASCADE_MODE -- If no. of interrupts goes beyond 32, then this parameter need to set
-- C_CASCADE_MASTER -- If cascade mode is set, then this parameter should be set to the first instance
-- -- of the core which is connected to the processor
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clocks and reset
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset - Active Low Reset
-- Axi interface signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- Intc Interface Signals
-- intr -- Input Interruput request
-- irq -- Output Interruput request
-- processor_clk -- in put same as processor clock
-- processor_rst -- in put same as processor reset
-- processor_ack -- input Connected to processor ACK
-- interrupt_address -- output Connected to processor interrupt address pins
-- interrupt_address_in-- Input this is coming from lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-- processor_ack_out -- Output this is going to lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
entity axi_intc is
generic
(
-- System Parameter
C_FAMILY : string := "virtex6";
C_INSTANCE : string := "axi_intc_inst";
-- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 9; -- 9
C_S_AXI_DATA_WIDTH : integer := 32;
-- Intc Parameters
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_NUM_SW_INTR : integer range 0 to 31 := 0;
C_KIND_OF_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_ASYNC_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_NUM_SYNC_FF : integer range 0 to 7 := 2;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000";
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_HAS_ILR : integer range 0 to 1 := 0;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1';
C_DISABLE_SYNCHRONIZERS : integer range 0 to 1 := 0;
C_MB_CLK_NOT_CONNECTED : integer range 0 to 1 := 1;
C_HAS_FAST : integer range 0 to 1 := 0;
-- The below parameter is unused in RTL but required in Vivado Native
C_ENABLE_ASYNC : integer range 0 to 1 := 0; --not used for EDK, used only for Vivado
--
C_EN_CASCADE_MODE : integer range 0 to 1 := 0; -- default no cascade mode, if set enable cascade mode
C_CASCADE_MASTER : integer range 0 to 1 := 0 -- default slave, if set become cascade master and connects ports to Processor
--
);
port
(
-- system signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- axi interface signals
s_axi_awaddr : in std_logic_vector (8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector (31 downto 0);
s_axi_wstrb : in std_logic_vector (3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector (8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector (31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Intc iInterface signals
intr : in std_logic_vector(C_NUM_INTR_INPUTS-1 downto 0);
processor_clk : in std_logic; --- MB Clk, clock from MicroBlaze
processor_rst : in std_logic; --- MB rst, reset from MicroBlaze
irq : out std_logic;
processor_ack : in std_logic_vector(1 downto 0); --- newly added port
interrupt_address : out std_logic_vector(31 downto 0); --- newly added port
--
interrupt_address_in : in std_logic_vector(31 downto 0);
processor_ack_out : out std_logic_vector(1 downto 0)
--
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of S_AXI_ACLK : signal is "10000";
ATTRIBUTE MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
-- SIGIS attribute for specifying clocks,interrupts,resets for EDK
ATTRIBUTE IP_GROUP : string;
ATTRIBUTE IP_GROUP of axi_intc : entity is "LOGICORE";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE of axi_intc : entity is "PERIPHERAL";
ATTRIBUTE HDL : string;
ATTRIBUTE HDL of axi_intc : entity is "VHDL";
ATTRIBUTE STYLE : string;
ATTRIBUTE STYLE of axi_intc : entity is "HDL";
ATTRIBUTE IMP_NETLIST : string;
ATTRIBUTE IMP_NETLIST of axi_intc : entity is "TRUE";
ATTRIBUTE RUN_NGCBUILD : string;
ATTRIBUTE RUN_NGCBUILD of axi_intc : entity is "TRUE";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of S_AXI_ACLK : signal is "Clk";
ATTRIBUTE SIGIS of S_AXI_ARESETN : signal is "Rstn";
end axi_intc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_intc is
---------------------------------------------------------------------------
-- Component Declarations
---------------------------------------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(31 downto 0)
:= (others => '0');
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := (0 => 1);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= (
ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & (X"00000000" or X"0000003F"), --- changed the high address
ZERO_ADDR_PAD & (X"00000000" or X"00000100"), --- changed the high address
ZERO_ADDR_PAD & (X"00000000" or X"0000017F") --- changed the high address
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (16, 1); --- changed no. of chip enables
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000017F"; --- changed min memory size required
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 8;
constant RESET_ACTIVE : std_logic := '0';
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
signal register_addr : std_logic_vector(6 downto 0); -- changed
signal read_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal write_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal bus2ip_addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector((
(ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(
calc_num_ce(ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(
calc_num_ce(ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_be : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal word_access : std_logic;
signal ip2bus_rdack_int : std_logic;
signal ip2bus_wrack_int : std_logic;
signal ip2bus_rdack_int_d1 : std_logic;
signal ip2bus_wrack_int_d1 : std_logic;
signal ip2bus_rdack_prev2 : std_logic;
signal ip2bus_wrack_prev2 : std_logic;
function Or128_vec2stdlogic (vec_in : std_logic_vector) return std_logic is
variable or_out : std_logic := '0';
begin
for i in 0 to 16 loop
or_out := vec_in(i) or or_out;
end loop;
return or_out;
end function Or128_vec2stdlogic;
------------------------------------------------------------------------------
-----
begin
-----
assert C_NUM_SW_INTR + C_NUM_INTR_INPUTS <= 32
report "C_NUM_SW_INTR + C_NUM_INTR_INPUTS must be less than or equal to 32"
severity error;
register_addr <= bus2ip_addr(8 downto 2); -- changed the range as no. of register increased
--- Internal ack signals
ip2bus_rdack_int <= Or128_vec2stdlogic(bus2ip_rdce); -- changed, utilized function as no. chip enables increased
ip2bus_wrack_int <= Or128_vec2stdlogic(bus2ip_wrce); -- changed, utilized function as no. chip enables increased
-- Error signal generation
word_access <= bus2ip_be(0) and
bus2ip_be(1) and
bus2ip_be(2) and
bus2ip_be(3);
ip2bus_error <= not word_access;
--------------------------------------------------------------------------
-- Process DACK_DELAY_P for generating write and read data acknowledge
-- signals.
--------------------------------------------------------------------------
DACK_DELAY_P: process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk='1' then
if bus2ip_resetn = RESET_ACTIVE then
ip2bus_rdack_int_d1 <= '0';
ip2bus_wrack_int_d1 <= '0';
ip2bus_rdack <= '0';
ip2bus_wrack <= '0';
else
ip2bus_rdack_int_d1 <= ip2bus_rdack_int;
ip2bus_wrack_int_d1 <= ip2bus_wrack_int;
ip2bus_rdack <= ip2bus_rdack_prev2;
ip2bus_wrack <= ip2bus_wrack_prev2;
end if;
end if;
end process DACK_DELAY_P;
-- Detecting rising edge by creating one shot
ip2bus_rdack_prev2 <= ip2bus_rdack_int and (not ip2bus_rdack_int_d1);
ip2bus_wrack_prev2 <= ip2bus_wrack_int and (not ip2bus_wrack_int_d1);
---------------------------------------------------------------------------
-- Component Instantiations
---------------------------------------------------------------------------
-----------------------------------------------------------------
-- Instantiating intc_core from axi_intc_v4_1
-----------------------------------------------------------------
INTC_CORE_I : entity axi_intc_v4_1.intc_core
generic map
(
C_FAMILY => C_FAMILY,
C_DWIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_INTR_INPUTS => C_NUM_INTR_INPUTS,
C_NUM_SW_INTR => C_NUM_SW_INTR,
C_KIND_OF_INTR => C_KIND_OF_INTR,
C_KIND_OF_EDGE => C_KIND_OF_EDGE,
C_KIND_OF_LVL => C_KIND_OF_LVL,
C_ASYNC_INTR => C_ASYNC_INTR,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HAS_IPR => C_HAS_IPR,
C_HAS_SIE => C_HAS_SIE,
C_HAS_CIE => C_HAS_CIE,
C_HAS_IVR => C_HAS_IVR,
C_HAS_ILR => C_HAS_ILR,
C_IRQ_IS_LEVEL => C_IRQ_IS_LEVEL,
C_IRQ_ACTIVE => C_IRQ_ACTIVE,
C_DISABLE_SYNCHRONIZERS => C_DISABLE_SYNCHRONIZERS,
C_MB_CLK_NOT_CONNECTED => C_MB_CLK_NOT_CONNECTED,
C_HAS_FAST => C_HAS_FAST,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE,
--
C_EN_CASCADE_MODE => C_EN_CASCADE_MODE,
C_CASCADE_MASTER => C_CASCADE_MASTER
--
)
port map
(
-- Intc Interface Signals
Clk => bus2ip_clk,
Rst_n => bus2ip_resetn,
Intr => intr,
Reg_addr => register_addr,
Bus2ip_rdce => bus2ip_rdce,
Bus2ip_wrce => bus2ip_wrce,
Wr_data => write_data,
Rd_data => read_data,
Processor_clk => processor_clk,
Processor_rst => processor_rst,
Irq => Irq,
Processor_ack => processor_ack,
Interrupt_address => interrupt_address,
Interrupt_address_in => interrupt_address_in,
Processor_ack_out => processor_ack_out
);
-----------------------------------------------------------------
--Instantiating axi_lite_ipif from axi_lite_ipif_v3_0
-----------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY=> ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
--System signals
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
-- AXI interface signals
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- Controls to the IP/IPIF modules
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce,
Bus2IP_Data => write_data,
IP2Bus_Data => read_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error
);
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_intc.vhd
-- Version: v3.1
-- Description: Interrupt controller interfaced to AXI.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_intc.vhd (wrapper for top level)
-- -- axi_lite_ipif.vhd
-- -- intc_core.vhd
--
-------------------------------------------------------------------------------
-- Author: PB
-- History:
-- PB 07/29/09
-- ^^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
-- PB 03/26/10
--
-- - updated based on the xps_intc_v2_01_a
-- PB 09/21/10
--
-- - updated the axi_lite_ipif from v1.00.a to v1.01.a
-- ~~~~~~
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-- ^^^^^^^
-- SA 03/25/13
--
-- 1. Added software interrupt support
-- ~~~~~~
-- SA 09/05/13
--
-- 1. Added support for nested interrupts using ILR register in v4.1
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------
-- Library axi_lite_ipif_v3_0 is used because it contains the
-- axi_lite_ipif which interraces intc_core to AXI.
-------------------------------------------------------------------------
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------
-- Library axi_intc_v4_1 is used because it contains the intc_core.
-- The complete interrupt controller logic is designed in intc_core.
-------------------------------------------------------------------------
library axi_intc_v4_1;
use axi_intc_v4_1.intc_core;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- System Parameter
-- C_FAMILY -- Target FPGA family
-- AXI Parameters
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- Intc Parameters
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_NUM_SW_INTR -- Number of software interrupts
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_ASYNC_INTR -- Interrupt is asynchronous (0-sync/1-async)
-- C_NUM_SYNC_FF -- Number of synchronization flip-flops for async interrupts
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_HAS_ILR -- Set to 1 if has Interrupt Level Register for nested interupt support
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
-- C_IVR_RESET_VALUE -- Reset value for the vectroed interrupt registers in RAM
-- C_DISABLE_SYNCHRONIZERS -- If the processor clock and axi clock are of same
-- value then user can decide to disable this
-- C_MB_CLK_NOT_CONNECTED -- If the processor clock is not connected or used in design
-- C_HAS_FAST -- If user wants to choose the fast interrupt mode of the core
-- -- then it is needed to have this paraemter set. Default is Standard Mode interrupt
-- C_ENABLE_ASYNC -- This parameter is used only for Vivado standalone mode of the core, not used in RTL
-- C_EN_CASCADE_MODE -- If no. of interrupts goes beyond 32, then this parameter need to set
-- C_CASCADE_MASTER -- If cascade mode is set, then this parameter should be set to the first instance
-- -- of the core which is connected to the processor
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clocks and reset
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset - Active Low Reset
-- Axi interface signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- Intc Interface Signals
-- intr -- Input Interruput request
-- irq -- Output Interruput request
-- processor_clk -- in put same as processor clock
-- processor_rst -- in put same as processor reset
-- processor_ack -- input Connected to processor ACK
-- interrupt_address -- output Connected to processor interrupt address pins
-- interrupt_address_in-- Input this is coming from lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-- processor_ack_out -- Output this is going to lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
entity axi_intc is
generic
(
-- System Parameter
C_FAMILY : string := "virtex6";
C_INSTANCE : string := "axi_intc_inst";
-- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 9; -- 9
C_S_AXI_DATA_WIDTH : integer := 32;
-- Intc Parameters
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_NUM_SW_INTR : integer range 0 to 31 := 0;
C_KIND_OF_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_ASYNC_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_NUM_SYNC_FF : integer range 0 to 7 := 2;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000";
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_HAS_ILR : integer range 0 to 1 := 0;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1';
C_DISABLE_SYNCHRONIZERS : integer range 0 to 1 := 0;
C_MB_CLK_NOT_CONNECTED : integer range 0 to 1 := 1;
C_HAS_FAST : integer range 0 to 1 := 0;
-- The below parameter is unused in RTL but required in Vivado Native
C_ENABLE_ASYNC : integer range 0 to 1 := 0; --not used for EDK, used only for Vivado
--
C_EN_CASCADE_MODE : integer range 0 to 1 := 0; -- default no cascade mode, if set enable cascade mode
C_CASCADE_MASTER : integer range 0 to 1 := 0 -- default slave, if set become cascade master and connects ports to Processor
--
);
port
(
-- system signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- axi interface signals
s_axi_awaddr : in std_logic_vector (8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector (31 downto 0);
s_axi_wstrb : in std_logic_vector (3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector (8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector (31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Intc iInterface signals
intr : in std_logic_vector(C_NUM_INTR_INPUTS-1 downto 0);
processor_clk : in std_logic; --- MB Clk, clock from MicroBlaze
processor_rst : in std_logic; --- MB rst, reset from MicroBlaze
irq : out std_logic;
processor_ack : in std_logic_vector(1 downto 0); --- newly added port
interrupt_address : out std_logic_vector(31 downto 0); --- newly added port
--
interrupt_address_in : in std_logic_vector(31 downto 0);
processor_ack_out : out std_logic_vector(1 downto 0)
--
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of S_AXI_ACLK : signal is "10000";
ATTRIBUTE MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
-- SIGIS attribute for specifying clocks,interrupts,resets for EDK
ATTRIBUTE IP_GROUP : string;
ATTRIBUTE IP_GROUP of axi_intc : entity is "LOGICORE";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE of axi_intc : entity is "PERIPHERAL";
ATTRIBUTE HDL : string;
ATTRIBUTE HDL of axi_intc : entity is "VHDL";
ATTRIBUTE STYLE : string;
ATTRIBUTE STYLE of axi_intc : entity is "HDL";
ATTRIBUTE IMP_NETLIST : string;
ATTRIBUTE IMP_NETLIST of axi_intc : entity is "TRUE";
ATTRIBUTE RUN_NGCBUILD : string;
ATTRIBUTE RUN_NGCBUILD of axi_intc : entity is "TRUE";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of S_AXI_ACLK : signal is "Clk";
ATTRIBUTE SIGIS of S_AXI_ARESETN : signal is "Rstn";
end axi_intc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_intc is
---------------------------------------------------------------------------
-- Component Declarations
---------------------------------------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(31 downto 0)
:= (others => '0');
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := (0 => 1);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= (
ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & (X"00000000" or X"0000003F"), --- changed the high address
ZERO_ADDR_PAD & (X"00000000" or X"00000100"), --- changed the high address
ZERO_ADDR_PAD & (X"00000000" or X"0000017F") --- changed the high address
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (16, 1); --- changed no. of chip enables
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000017F"; --- changed min memory size required
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 8;
constant RESET_ACTIVE : std_logic := '0';
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
signal register_addr : std_logic_vector(6 downto 0); -- changed
signal read_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal write_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal bus2ip_addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector((
(ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(
calc_num_ce(ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(
calc_num_ce(ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_be : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal word_access : std_logic;
signal ip2bus_rdack_int : std_logic;
signal ip2bus_wrack_int : std_logic;
signal ip2bus_rdack_int_d1 : std_logic;
signal ip2bus_wrack_int_d1 : std_logic;
signal ip2bus_rdack_prev2 : std_logic;
signal ip2bus_wrack_prev2 : std_logic;
function Or128_vec2stdlogic (vec_in : std_logic_vector) return std_logic is
variable or_out : std_logic := '0';
begin
for i in 0 to 16 loop
or_out := vec_in(i) or or_out;
end loop;
return or_out;
end function Or128_vec2stdlogic;
------------------------------------------------------------------------------
-----
begin
-----
assert C_NUM_SW_INTR + C_NUM_INTR_INPUTS <= 32
report "C_NUM_SW_INTR + C_NUM_INTR_INPUTS must be less than or equal to 32"
severity error;
register_addr <= bus2ip_addr(8 downto 2); -- changed the range as no. of register increased
--- Internal ack signals
ip2bus_rdack_int <= Or128_vec2stdlogic(bus2ip_rdce); -- changed, utilized function as no. chip enables increased
ip2bus_wrack_int <= Or128_vec2stdlogic(bus2ip_wrce); -- changed, utilized function as no. chip enables increased
-- Error signal generation
word_access <= bus2ip_be(0) and
bus2ip_be(1) and
bus2ip_be(2) and
bus2ip_be(3);
ip2bus_error <= not word_access;
--------------------------------------------------------------------------
-- Process DACK_DELAY_P for generating write and read data acknowledge
-- signals.
--------------------------------------------------------------------------
DACK_DELAY_P: process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk='1' then
if bus2ip_resetn = RESET_ACTIVE then
ip2bus_rdack_int_d1 <= '0';
ip2bus_wrack_int_d1 <= '0';
ip2bus_rdack <= '0';
ip2bus_wrack <= '0';
else
ip2bus_rdack_int_d1 <= ip2bus_rdack_int;
ip2bus_wrack_int_d1 <= ip2bus_wrack_int;
ip2bus_rdack <= ip2bus_rdack_prev2;
ip2bus_wrack <= ip2bus_wrack_prev2;
end if;
end if;
end process DACK_DELAY_P;
-- Detecting rising edge by creating one shot
ip2bus_rdack_prev2 <= ip2bus_rdack_int and (not ip2bus_rdack_int_d1);
ip2bus_wrack_prev2 <= ip2bus_wrack_int and (not ip2bus_wrack_int_d1);
---------------------------------------------------------------------------
-- Component Instantiations
---------------------------------------------------------------------------
-----------------------------------------------------------------
-- Instantiating intc_core from axi_intc_v4_1
-----------------------------------------------------------------
INTC_CORE_I : entity axi_intc_v4_1.intc_core
generic map
(
C_FAMILY => C_FAMILY,
C_DWIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_INTR_INPUTS => C_NUM_INTR_INPUTS,
C_NUM_SW_INTR => C_NUM_SW_INTR,
C_KIND_OF_INTR => C_KIND_OF_INTR,
C_KIND_OF_EDGE => C_KIND_OF_EDGE,
C_KIND_OF_LVL => C_KIND_OF_LVL,
C_ASYNC_INTR => C_ASYNC_INTR,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HAS_IPR => C_HAS_IPR,
C_HAS_SIE => C_HAS_SIE,
C_HAS_CIE => C_HAS_CIE,
C_HAS_IVR => C_HAS_IVR,
C_HAS_ILR => C_HAS_ILR,
C_IRQ_IS_LEVEL => C_IRQ_IS_LEVEL,
C_IRQ_ACTIVE => C_IRQ_ACTIVE,
C_DISABLE_SYNCHRONIZERS => C_DISABLE_SYNCHRONIZERS,
C_MB_CLK_NOT_CONNECTED => C_MB_CLK_NOT_CONNECTED,
C_HAS_FAST => C_HAS_FAST,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE,
--
C_EN_CASCADE_MODE => C_EN_CASCADE_MODE,
C_CASCADE_MASTER => C_CASCADE_MASTER
--
)
port map
(
-- Intc Interface Signals
Clk => bus2ip_clk,
Rst_n => bus2ip_resetn,
Intr => intr,
Reg_addr => register_addr,
Bus2ip_rdce => bus2ip_rdce,
Bus2ip_wrce => bus2ip_wrce,
Wr_data => write_data,
Rd_data => read_data,
Processor_clk => processor_clk,
Processor_rst => processor_rst,
Irq => Irq,
Processor_ack => processor_ack,
Interrupt_address => interrupt_address,
Interrupt_address_in => interrupt_address_in,
Processor_ack_out => processor_ack_out
);
-----------------------------------------------------------------
--Instantiating axi_lite_ipif from axi_lite_ipif_v3_0
-----------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY=> ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
--System signals
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
-- AXI interface signals
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- Controls to the IP/IPIF modules
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce,
Bus2IP_Data => write_data,
IP2Bus_Data => read_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error
);
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_intc.vhd
-- Version: v3.1
-- Description: Interrupt controller interfaced to AXI.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_intc.vhd (wrapper for top level)
-- -- axi_lite_ipif.vhd
-- -- intc_core.vhd
--
-------------------------------------------------------------------------------
-- Author: PB
-- History:
-- PB 07/29/09
-- ^^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
-- PB 03/26/10
--
-- - updated based on the xps_intc_v2_01_a
-- PB 09/21/10
--
-- - updated the axi_lite_ipif from v1.00.a to v1.01.a
-- ~~~~~~
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-- ^^^^^^^
-- SA 03/25/13
--
-- 1. Added software interrupt support
-- ~~~~~~
-- SA 09/05/13
--
-- 1. Added support for nested interrupts using ILR register in v4.1
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------
-- Library axi_lite_ipif_v3_0 is used because it contains the
-- axi_lite_ipif which interraces intc_core to AXI.
-------------------------------------------------------------------------
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------
-- Library axi_intc_v4_1 is used because it contains the intc_core.
-- The complete interrupt controller logic is designed in intc_core.
-------------------------------------------------------------------------
library axi_intc_v4_1;
use axi_intc_v4_1.intc_core;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- System Parameter
-- C_FAMILY -- Target FPGA family
-- AXI Parameters
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- Intc Parameters
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_NUM_SW_INTR -- Number of software interrupts
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_ASYNC_INTR -- Interrupt is asynchronous (0-sync/1-async)
-- C_NUM_SYNC_FF -- Number of synchronization flip-flops for async interrupts
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_HAS_ILR -- Set to 1 if has Interrupt Level Register for nested interupt support
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
-- C_IVR_RESET_VALUE -- Reset value for the vectroed interrupt registers in RAM
-- C_DISABLE_SYNCHRONIZERS -- If the processor clock and axi clock are of same
-- value then user can decide to disable this
-- C_MB_CLK_NOT_CONNECTED -- If the processor clock is not connected or used in design
-- C_HAS_FAST -- If user wants to choose the fast interrupt mode of the core
-- -- then it is needed to have this paraemter set. Default is Standard Mode interrupt
-- C_ENABLE_ASYNC -- This parameter is used only for Vivado standalone mode of the core, not used in RTL
-- C_EN_CASCADE_MODE -- If no. of interrupts goes beyond 32, then this parameter need to set
-- C_CASCADE_MASTER -- If cascade mode is set, then this parameter should be set to the first instance
-- -- of the core which is connected to the processor
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clocks and reset
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset - Active Low Reset
-- Axi interface signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- Intc Interface Signals
-- intr -- Input Interruput request
-- irq -- Output Interruput request
-- processor_clk -- in put same as processor clock
-- processor_rst -- in put same as processor reset
-- processor_ack -- input Connected to processor ACK
-- interrupt_address -- output Connected to processor interrupt address pins
-- interrupt_address_in-- Input this is coming from lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-- processor_ack_out -- Output this is going to lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
entity axi_intc is
generic
(
-- System Parameter
C_FAMILY : string := "virtex6";
C_INSTANCE : string := "axi_intc_inst";
-- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 9; -- 9
C_S_AXI_DATA_WIDTH : integer := 32;
-- Intc Parameters
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_NUM_SW_INTR : integer range 0 to 31 := 0;
C_KIND_OF_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_ASYNC_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_NUM_SYNC_FF : integer range 0 to 7 := 2;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000";
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_HAS_ILR : integer range 0 to 1 := 0;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1';
C_DISABLE_SYNCHRONIZERS : integer range 0 to 1 := 0;
C_MB_CLK_NOT_CONNECTED : integer range 0 to 1 := 1;
C_HAS_FAST : integer range 0 to 1 := 0;
-- The below parameter is unused in RTL but required in Vivado Native
C_ENABLE_ASYNC : integer range 0 to 1 := 0; --not used for EDK, used only for Vivado
--
C_EN_CASCADE_MODE : integer range 0 to 1 := 0; -- default no cascade mode, if set enable cascade mode
C_CASCADE_MASTER : integer range 0 to 1 := 0 -- default slave, if set become cascade master and connects ports to Processor
--
);
port
(
-- system signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- axi interface signals
s_axi_awaddr : in std_logic_vector (8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector (31 downto 0);
s_axi_wstrb : in std_logic_vector (3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector (8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector (31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Intc iInterface signals
intr : in std_logic_vector(C_NUM_INTR_INPUTS-1 downto 0);
processor_clk : in std_logic; --- MB Clk, clock from MicroBlaze
processor_rst : in std_logic; --- MB rst, reset from MicroBlaze
irq : out std_logic;
processor_ack : in std_logic_vector(1 downto 0); --- newly added port
interrupt_address : out std_logic_vector(31 downto 0); --- newly added port
--
interrupt_address_in : in std_logic_vector(31 downto 0);
processor_ack_out : out std_logic_vector(1 downto 0)
--
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of S_AXI_ACLK : signal is "10000";
ATTRIBUTE MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
-- SIGIS attribute for specifying clocks,interrupts,resets for EDK
ATTRIBUTE IP_GROUP : string;
ATTRIBUTE IP_GROUP of axi_intc : entity is "LOGICORE";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE of axi_intc : entity is "PERIPHERAL";
ATTRIBUTE HDL : string;
ATTRIBUTE HDL of axi_intc : entity is "VHDL";
ATTRIBUTE STYLE : string;
ATTRIBUTE STYLE of axi_intc : entity is "HDL";
ATTRIBUTE IMP_NETLIST : string;
ATTRIBUTE IMP_NETLIST of axi_intc : entity is "TRUE";
ATTRIBUTE RUN_NGCBUILD : string;
ATTRIBUTE RUN_NGCBUILD of axi_intc : entity is "TRUE";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of S_AXI_ACLK : signal is "Clk";
ATTRIBUTE SIGIS of S_AXI_ARESETN : signal is "Rstn";
end axi_intc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_intc is
---------------------------------------------------------------------------
-- Component Declarations
---------------------------------------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(31 downto 0)
:= (others => '0');
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := (0 => 1);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= (
ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & (X"00000000" or X"0000003F"), --- changed the high address
ZERO_ADDR_PAD & (X"00000000" or X"00000100"), --- changed the high address
ZERO_ADDR_PAD & (X"00000000" or X"0000017F") --- changed the high address
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (16, 1); --- changed no. of chip enables
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000017F"; --- changed min memory size required
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 8;
constant RESET_ACTIVE : std_logic := '0';
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
signal register_addr : std_logic_vector(6 downto 0); -- changed
signal read_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal write_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal bus2ip_addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector((
(ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(
calc_num_ce(ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(
calc_num_ce(ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_be : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal word_access : std_logic;
signal ip2bus_rdack_int : std_logic;
signal ip2bus_wrack_int : std_logic;
signal ip2bus_rdack_int_d1 : std_logic;
signal ip2bus_wrack_int_d1 : std_logic;
signal ip2bus_rdack_prev2 : std_logic;
signal ip2bus_wrack_prev2 : std_logic;
function Or128_vec2stdlogic (vec_in : std_logic_vector) return std_logic is
variable or_out : std_logic := '0';
begin
for i in 0 to 16 loop
or_out := vec_in(i) or or_out;
end loop;
return or_out;
end function Or128_vec2stdlogic;
------------------------------------------------------------------------------
-----
begin
-----
assert C_NUM_SW_INTR + C_NUM_INTR_INPUTS <= 32
report "C_NUM_SW_INTR + C_NUM_INTR_INPUTS must be less than or equal to 32"
severity error;
register_addr <= bus2ip_addr(8 downto 2); -- changed the range as no. of register increased
--- Internal ack signals
ip2bus_rdack_int <= Or128_vec2stdlogic(bus2ip_rdce); -- changed, utilized function as no. chip enables increased
ip2bus_wrack_int <= Or128_vec2stdlogic(bus2ip_wrce); -- changed, utilized function as no. chip enables increased
-- Error signal generation
word_access <= bus2ip_be(0) and
bus2ip_be(1) and
bus2ip_be(2) and
bus2ip_be(3);
ip2bus_error <= not word_access;
--------------------------------------------------------------------------
-- Process DACK_DELAY_P for generating write and read data acknowledge
-- signals.
--------------------------------------------------------------------------
DACK_DELAY_P: process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk='1' then
if bus2ip_resetn = RESET_ACTIVE then
ip2bus_rdack_int_d1 <= '0';
ip2bus_wrack_int_d1 <= '0';
ip2bus_rdack <= '0';
ip2bus_wrack <= '0';
else
ip2bus_rdack_int_d1 <= ip2bus_rdack_int;
ip2bus_wrack_int_d1 <= ip2bus_wrack_int;
ip2bus_rdack <= ip2bus_rdack_prev2;
ip2bus_wrack <= ip2bus_wrack_prev2;
end if;
end if;
end process DACK_DELAY_P;
-- Detecting rising edge by creating one shot
ip2bus_rdack_prev2 <= ip2bus_rdack_int and (not ip2bus_rdack_int_d1);
ip2bus_wrack_prev2 <= ip2bus_wrack_int and (not ip2bus_wrack_int_d1);
---------------------------------------------------------------------------
-- Component Instantiations
---------------------------------------------------------------------------
-----------------------------------------------------------------
-- Instantiating intc_core from axi_intc_v4_1
-----------------------------------------------------------------
INTC_CORE_I : entity axi_intc_v4_1.intc_core
generic map
(
C_FAMILY => C_FAMILY,
C_DWIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_INTR_INPUTS => C_NUM_INTR_INPUTS,
C_NUM_SW_INTR => C_NUM_SW_INTR,
C_KIND_OF_INTR => C_KIND_OF_INTR,
C_KIND_OF_EDGE => C_KIND_OF_EDGE,
C_KIND_OF_LVL => C_KIND_OF_LVL,
C_ASYNC_INTR => C_ASYNC_INTR,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HAS_IPR => C_HAS_IPR,
C_HAS_SIE => C_HAS_SIE,
C_HAS_CIE => C_HAS_CIE,
C_HAS_IVR => C_HAS_IVR,
C_HAS_ILR => C_HAS_ILR,
C_IRQ_IS_LEVEL => C_IRQ_IS_LEVEL,
C_IRQ_ACTIVE => C_IRQ_ACTIVE,
C_DISABLE_SYNCHRONIZERS => C_DISABLE_SYNCHRONIZERS,
C_MB_CLK_NOT_CONNECTED => C_MB_CLK_NOT_CONNECTED,
C_HAS_FAST => C_HAS_FAST,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE,
--
C_EN_CASCADE_MODE => C_EN_CASCADE_MODE,
C_CASCADE_MASTER => C_CASCADE_MASTER
--
)
port map
(
-- Intc Interface Signals
Clk => bus2ip_clk,
Rst_n => bus2ip_resetn,
Intr => intr,
Reg_addr => register_addr,
Bus2ip_rdce => bus2ip_rdce,
Bus2ip_wrce => bus2ip_wrce,
Wr_data => write_data,
Rd_data => read_data,
Processor_clk => processor_clk,
Processor_rst => processor_rst,
Irq => Irq,
Processor_ack => processor_ack,
Interrupt_address => interrupt_address,
Interrupt_address_in => interrupt_address_in,
Processor_ack_out => processor_ack_out
);
-----------------------------------------------------------------
--Instantiating axi_lite_ipif from axi_lite_ipif_v3_0
-----------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY=> ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
--System signals
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
-- AXI interface signals
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- Controls to the IP/IPIF modules
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce,
Bus2IP_Data => write_data,
IP2Bus_Data => read_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error
);
end imp;
|
-- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
entity test_nicctrl is
end;
architecture BENCH of test_nicctrl is
component clkgen is
port (
pciclk : out bit;
nicclk : out bit;
ethclk : out bit
);
end component;
component traffgen is
port (
pktarrival : out bit;
pktsize : out integer;
ethclk : in bit
);
end component;
component buffmngr is
port (
pktarrival : in bit;
pktsize : in integer;
transfer_start_req : out bit;
transfer_end : in bit;
ethclk : in bit;
pciclk : in bit;
pktreceived : out bit;
payload_size_in_data_blocks : out integer;
buffer_fill_level_in_bytes : out integer;
buffer_fill_level_in_data_units : out integer;
max_buffer_fill_level : out integer;
dropped_packets_count : out integer;
buffer_size_in_data_units : out integer
);
end component;
component nicctrl is
port (
transfer_start_req : in bit;
transfer_end : out bit;
req : out bit;
gnt : in bit;
frame : inout std_logic;
irdy : out bit;
trdy : in bit;
AD : out bit;
payload_size_in_data_blocks : in integer;
payload_transfer_req : out bit;
descriptor_transfer_req : out bit;
payload_transfer_end : in bit;
descriptor_transfer_end : in bit;
payload_transfer_aborted : in bit;
resume_aborted_payload_transfer : out bit;
descriptor_transfer_aborted : in bit;
resume_aborted_descriptor_transfer : out bit;
acq_latency_cycles_counter_out : out integer;
nic_proc_latency_cycles_counter_out : out integer;
nicclk : in bit;
pciclk : in bit
);
end component;
component dmactrl is
port (
payload_transfer_req : in bit;
descriptor_transfer_req : in bit;
payload_transfer_end : out bit;
descriptor_transfer_end : out bit;
payload_transfer_aborted : out bit;
descriptor_transfer_aborted : out bit;
resume_aborted_payload_transfer : in bit;
resume_aborted_descriptor_transfer : in bit;
irdy : in bit;
trdy : in bit;
gnt : in bit;
payload_size_in_data_blocks : in integer;
dma_cycles_counter_out : out integer;
burst_cycles_counter_out : out integer;
pciclk : in bit
);
end component;
component arbiter is
port (
req : in bit;
gnt : out bit;
-- burst_cycles_counter_out : out integer;
arb_latency_cycles_counter_out : out integer;
pciclk : in bit
);
end component;
component memsub is
port (
irdy : in bit;
trdy : out bit;
frame : inout std_logic;
AD : in bit;
target_latency_cycles_counter_out : out integer; -- Always is 1 cycle
pciclk : in bit
);
end component;
component othermaster is
port (
frame : inout std_logic;
pciclk : in bit
);
end component;
component statsgen is
port (
pciclk : in bit;
ethclk : in bit;
pktreceived : in bit;
pktsize : in integer;
transfer_start_req : in bit;
--payload_transfer_req : in bit;
--payload_transfer_aborted : in bit;
--resume_aborted_payload_transfer : in bit;
--descriptor_transfer_req : in bit;
--descriptor_transfer_aborted : in bit;
--resume_aborted_descriptor_transfer : in bit;
transfer_end : in bit;
buffer_fill_level_in_bytes : in integer;
buffer_fill_level_in_data_units : in integer;
max_buffer_fill_level : in integer;
dropped_packets_count : in integer;
nic_proc_latency_cycles_counter_out : in integer;
acq_latency_cycles_counter_out : in integer;
arb_latency_cycles_counter_out : in integer;
target_latency_cycles_counter_out : in integer;
burst_cycles_counter_out : in integer;
dma_cycles_counter_out : in integer;
clock_counter_out : out integer
);
end component;
signal sig_pciclk, sig_nicclk, sig_ethclk : bit;
signal sig_frame : std_logic;
signal sig_pktarrival, sig_transfer_start_req, sig_transfer_end, sig_req, sig_gnt, sig_irdy, sig_payload_transfer_req, sig_descriptor_transfer_req, sig_payload_transfer_end, sig_descriptor_transfer_end, sig_payload_transfer_aborted, sig_descriptor_transfer_aborted, sig_resume_aborted_payload_transfer, sig_resume_aborted_descriptor_transfer, sig_trdy, sig_AD, sig_pktreceived : bit;
signal sig_payload_size_in_data_blocks, sig_dma_cycles_counter_out, sig_buffer_fill_level_in_bytes, sig_buffer_fill_level_in_data_units, sig_burst_cycles_counter_out, sig_arb_latency_cycles_counter_out, sig_pktsize, sig_acq_latency_cycles_counter_out, sig_nic_proc_latency_cycles_counter_out, sig_target_latency_cycles_counter_out, sig_clock_counter_out, sig_max_buffer_fill_level, sig_dropped_packets_count, sig_buffer_size_in_data_units : integer;
begin
-- Components Port Map
clkgen_comp: clkgen port map (pciclk => sig_pciclk, nicclk => sig_nicclk, ethclk => sig_ethclk);
traffgen_comp : traffgen port map (pktarrival => sig_pktarrival, pktsize => sig_pktsize, ethclk => sig_ethclk);
buffmngr_comp: buffmngr port map (pktarrival => sig_pktarrival, pktsize => sig_pktsize, transfer_start_req => sig_transfer_start_req, transfer_end => sig_transfer_end, ethclk => sig_ethclk, pciclk => sig_pciclk, pktreceived => sig_pktreceived, payload_size_in_data_blocks => sig_payload_size_in_data_blocks, buffer_fill_level_in_bytes => sig_buffer_fill_level_in_bytes, buffer_fill_level_in_data_units => sig_buffer_fill_level_in_data_units, max_buffer_fill_level => sig_max_buffer_fill_level, dropped_packets_count => sig_dropped_packets_count, buffer_size_in_data_units => sig_buffer_size_in_data_units);
nicctrl_comp: nicctrl port map (transfer_start_req => sig_transfer_start_req, transfer_end => sig_transfer_end, req => sig_req, gnt => sig_gnt, frame => sig_frame, irdy => sig_irdy, trdy => sig_trdy, AD => sig_AD, payload_size_in_data_blocks => sig_payload_size_in_data_blocks, payload_transfer_req => sig_payload_transfer_req, descriptor_transfer_req => sig_descriptor_transfer_req, payload_transfer_end => sig_payload_transfer_end, descriptor_transfer_end => sig_descriptor_transfer_end, payload_transfer_aborted => sig_payload_transfer_aborted, resume_aborted_payload_transfer => sig_resume_aborted_payload_transfer, descriptor_transfer_aborted => sig_descriptor_transfer_aborted, resume_aborted_descriptor_transfer => sig_resume_aborted_descriptor_transfer, acq_latency_cycles_counter_out => sig_acq_latency_cycles_counter_out, nic_proc_latency_cycles_counter_out => sig_nic_proc_latency_cycles_counter_out, nicclk => sig_nicclk, pciclk => sig_pciclk);
dmactrl_comp: dmactrl port map (payload_transfer_req => sig_payload_transfer_req, descriptor_transfer_req => sig_descriptor_transfer_req, payload_transfer_end => sig_payload_transfer_end, descriptor_transfer_end => sig_descriptor_transfer_end, payload_transfer_aborted => sig_payload_transfer_aborted, descriptor_transfer_aborted => sig_descriptor_transfer_aborted, resume_aborted_payload_transfer => sig_resume_aborted_payload_transfer, resume_aborted_descriptor_transfer => sig_resume_aborted_descriptor_transfer, irdy => sig_irdy, trdy => sig_trdy, gnt => sig_gnt, payload_size_in_data_blocks => sig_payload_size_in_data_blocks, dma_cycles_counter_out => sig_dma_cycles_counter_out, burst_cycles_counter_out => sig_burst_cycles_counter_out, pciclk => sig_pciclk);
arbiter_comp: arbiter port map (req => sig_req, gnt => sig_gnt, arb_latency_cycles_counter_out => sig_arb_latency_cycles_counter_out, pciclk => sig_pciclk);
memsub_comp: memsub port map (irdy => sig_irdy, trdy => sig_trdy, frame => sig_frame, AD => sig_AD, target_latency_cycles_counter_out => sig_target_latency_cycles_counter_out, pciclk => sig_pciclk);
statsgen_comp: statsgen port map (pciclk => sig_pciclk, ethclk => sig_ethclk, pktreceived => sig_pktreceived, pktsize => sig_pktsize,transfer_start_req => sig_transfer_start_req, transfer_end => sig_transfer_end, buffer_fill_level_in_bytes => sig_buffer_fill_level_in_bytes, buffer_fill_level_in_data_units => sig_buffer_fill_level_in_data_units, max_buffer_fill_level => sig_max_buffer_fill_level, dropped_packets_count => sig_dropped_packets_count, nic_proc_latency_cycles_counter_out => sig_nic_proc_latency_cycles_counter_out, acq_latency_cycles_counter_out => sig_acq_latency_cycles_counter_out, arb_latency_cycles_counter_out => sig_arb_latency_cycles_counter_out, target_latency_cycles_counter_out => sig_target_latency_cycles_counter_out, burst_cycles_counter_out => sig_burst_cycles_counter_out, dma_cycles_counter_out => sig_dma_cycles_counter_out, clock_counter_out => sig_clock_counter_out);
othermaster_comp: othermaster port map (frame => sig_frame, pciclk => sig_pciclk);
end BENCH;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:45:16 07/16/2015
-- Design Name:
-- Module Name: decode4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity decode4 is
port(
d : in std_logic_vector(3 downto 0);
enable : in std_logic;
q8, q9, q11 : out std_logic
);
end decode4 ;
architecture main of decode4 is
begin
process( enable, d )
begin
if enable = '1' then
case d is
when "1000" => q8 <= '0'; q9 <= '1'; q11 <= '1';
when "1001" => q8 <= '1'; q9 <= '0'; q11 <= '1';
when "1011" => q8 <= '1'; q9 <= '1'; q11 <= '0';
when others => q8 <= '1'; q9 <= '1'; q11 <= '1';
end case;
else
q8 <= '1'; q9 <= '1'; q11 <= '1';
end if;
end process;
end main;
|
entity agg7 is
end entity;
architecture test of agg7 is
begin
main: process is
variable x : integer_vector(1 to 4);
variable y, z : integer_vector(1 to 2);
begin
x := ( integer_vector'(1, 2), integer_vector'(3, 4) );
assert x = (1, 2, 3, 4);
y := (5, 6);
z := (7, 8);
x := ( y, z );
assert x = (5, 6, 7, 8);
x := ( 1 to 2 => z, 3 to 4 => integer_vector'(1, 2) );
assert x = (7, 8, 1, 2);
x := ( 4 downto 1 => x );
assert x = (7, 8, 1, 2);
x := ( y, 9, 8 );
assert x = (5, 6, 9, 8);
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: allmul
-- File: allmul.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Multiplier components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package allmul is
component mul_dw is
generic (
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end component;
component gen_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1); -- '0': non-stallable; '1': stallable
port (
clk : in std_logic; -- register clock
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component axcel_mul_33x33_signed
generic (
pipe: Integer := 0);
port (
a: in Std_Logic_Vector(32 downto 0);
b: in Std_Logic_Vector(32 downto 0);
en: in Std_Logic;
clk: in Std_Logic;
p: out Std_Logic_Vector(65 downto 0));
end component;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: saed32pads
-- File: pads_saed32.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
-- Description: SAED32 pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package saed32pads is
-- input pad
component I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic;DOUT : out std_logic); end component;
-- input pad with pull-up and pull-down
component B4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT: out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
-- schmitt input pad
component ISH1025_EW port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic; DOUT : out std_logic); end component;
-- output pads
component D4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D12I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D16I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
-- bidirectional pads (and tri-state output pads)
component B4ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B12ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B16ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.I1025_NS;
use saed32.B4I1025_NS;
use saed32.ISH1025_EW;
-- pragma translate_on
entity saed32_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of saed32_inpad is
component I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic; DOUT : out std_logic); end component;
component B4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT: out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component ISH1025_EW port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic; DOUT : out std_logic); end component;
signal localout,localpad : std_logic;
begin
norm : if filter = 0 generate
ip : I1025_NS port map (PADIO => localpad, DOUT => localout, VSS => OPEN, R_EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
pu : if filter = pullup generate
ip : B4I1025_NS port map (PADIO => localpad, PULL_UP => '1', PULL_DOWN => '0', DOUT => localout, DIN => '0', VSS => OPEN, R_EN => '1', EN => '0', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
pd : if filter = pulldown generate
ip : B4I1025_NS port map (PADIO => localpad, PULL_UP => '0', PULL_DOWN => '1', DOUT => localout, DIN => '0', VSS => OPEN, R_EN => '1', EN => '0', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
sch : if filter = schmitt generate
ip : ISH1025_EW port map (PADIO => localpad, DOUT => localout, VSS => OPEN, R_EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
o <= localout;
localpad <= pad;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.B4ISH1025_NS;
use saed32.B12ISH1025_NS;
use saed32.B16ISH1025_NS;
-- pragma translate_on
entity saed32_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of saed32_iopad is
component B4ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B12ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B16ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
signal localen : std_logic;
signal localout,localpad : std_logic;
begin
localen <= not en;
f4 : if (strength <= 4) generate
op : B4ISH1025_NS port map (DIN => i,PADIO => localpad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : B12ISH1025_NS port map (DIN => i, PADIO => localpad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f16 : if (strength > 12) generate
op : B16ISH1025_NS port map (DIN => i, PADIO => localpad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
pad <= localpad;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.D4I1025_NS;
use saed32.D12I1025_NS;
use saed32.D16I1025_NS;
-- pragma translate_on
entity saed32_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of saed32_outpad is
component D4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D12I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D16I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
signal localout,localpad : std_logic;
begin
f4 : if (strength <= 4) generate
op : D4I1025_NS port map (DIN => i, PADIO => localpad, VSS => OPEN, EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : D12I1025_NS port map (DIN => i, PADIO => localpad, VSS => OPEN, EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
f16 : if (strength > 12) generate
op : D16I1025_NS port map (DIN => i, PADIO => localpad, VSS => OPEN, EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
pad <= localpad;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.B4ISH1025_NS;
use saed32.B12ISH1025_NS;
use saed32.B16ISH1025_NS;
-- pragma translate_on
entity saed32_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of saed32_toutpad is
component B4ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B12ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B16ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
signal localpad : std_logic;
begin
f4 : if (strength <= 4) generate
op : B4ISH1025_NS port map (DIN => i,PADIO => localpad, DOUT => OPEN, VSS => OPEN, R_EN => '0', EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : B12ISH1025_NS port map (DIN => i, PADIO => localpad, DOUT => OPEN, VSS => OPEN, R_EN => '0', EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f16 : if (strength > 12) generate
op : B16ISH1025_NS port map (DIN => i, PADIO => localpad, DOUT => OPEN, VSS => OPEN, R_EN => '0', EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
pad <= localpad;
end;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_08.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package fg_11_08 is
type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
function resolved ( s : std_ulogic_vector ) return std_ulogic;
end package fg_11_08;
package body fg_11_08 is
-- code from book
type stdlogic_table is array (std_ulogic, std_ulogic) of std_ulogic;
constant resolution_table : stdlogic_table :=
-- ---------------------------------------------
-- 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'
-- ---------------------------------------------
( ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- 'U'
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- 'X'
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- '0'
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- '1'
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- 'Z'
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- 'W'
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- 'L'
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- 'H'
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- '-'
);
function resolved ( s : std_ulogic_vector ) return std_ulogic is
variable result : std_ulogic := 'Z'; -- weakest state default
begin
if s'length = 1 then
return s(s'low);
else
for i in s'range loop
result := resolution_table(result, s(i));
end loop;
end if;
return result;
end function resolved;
-- end code from book
end package body fg_11_08;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_08.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package fg_11_08 is
type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
function resolved ( s : std_ulogic_vector ) return std_ulogic;
end package fg_11_08;
package body fg_11_08 is
-- code from book
type stdlogic_table is array (std_ulogic, std_ulogic) of std_ulogic;
constant resolution_table : stdlogic_table :=
-- ---------------------------------------------
-- 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'
-- ---------------------------------------------
( ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- 'U'
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- 'X'
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- '0'
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- '1'
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- 'Z'
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- 'W'
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- 'L'
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- 'H'
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- '-'
);
function resolved ( s : std_ulogic_vector ) return std_ulogic is
variable result : std_ulogic := 'Z'; -- weakest state default
begin
if s'length = 1 then
return s(s'low);
else
for i in s'range loop
result := resolution_table(result, s(i));
end loop;
end if;
return result;
end function resolved;
-- end code from book
end package body fg_11_08;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_08.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package fg_11_08 is
type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
function resolved ( s : std_ulogic_vector ) return std_ulogic;
end package fg_11_08;
package body fg_11_08 is
-- code from book
type stdlogic_table is array (std_ulogic, std_ulogic) of std_ulogic;
constant resolution_table : stdlogic_table :=
-- ---------------------------------------------
-- 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'
-- ---------------------------------------------
( ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- 'U'
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- 'X'
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- '0'
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- '1'
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- 'Z'
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- 'W'
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- 'L'
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- 'H'
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- '-'
);
function resolved ( s : std_ulogic_vector ) return std_ulogic is
variable result : std_ulogic := 'Z'; -- weakest state default
begin
if s'length = 1 then
return s(s'low);
else
for i in s'range loop
result := resolution_table(result, s(i));
end loop;
end if;
return result;
end function resolved;
-- end code from book
end package body fg_11_08;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:23:13 11/21/2013
-- Design Name:
-- Module Name: ID_EX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ID_EX is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
WriteIn : in STD_LOGIC;
ALUopInput : in STD_LOGIC_VECTOR (2 downto 0);
ALUsrcInput : in STD_LOGIC;
TTypeInput : in STD_LOGIC;
TWriteInput : in STD_LOGIC;
MemReadInput : in STD_LOGIC;
MemWriteInput : in STD_LOGIC;
MemtoRegInput : in STD_LOGIC;
RegWriteInput: in STD_LOGIC;
RegWriteOutput: out STD_LOGIC;
ALUopOutput : out STD_LOGIC_VECTOR (2 downto 0);
ALUsrcOutput : out STD_LOGIC;
TTypeOutput : out STD_LOGIC;
TWriteOutput : out STD_LOGIC;
MemReadOutput : out STD_LOGIC;
MemWriteOutput : out STD_LOGIC;
MemtoRegOutput : out STD_LOGIC;
DataInput1 : in STD_LOGIC_VECTOR (15 downto 0);
DataInput2 : in STD_LOGIC_VECTOR (15 downto 0);
ImmediateInput : in STD_LOGIC_VECTOR (15 downto 0);
RegResult: out Int16;
ALUdata1 : out STD_LOGIC_VECTOR (15 downto 0);
ALUdata2 : out STD_LOGIC_VECTOR (15 downto 0);
RegReadInput1 : in STD_LOGIC_VECTOR (3 downto 0);
RegReadInput2 : in STD_LOGIC_VECTOR (3 downto 0);
RegWriteToInput : in STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput1 : out STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput2 : out STD_LOGIC_VECTOR (3 downto 0);
RegWriteToOutput : out STD_LOGIC_VECTOR (3 downto 0);
retinput: in std_logic;
retoutput: out std_logic
);
end ID_EX;
architecture Behavioral of ID_EX is
begin
process (rst, clk, WriteIn)
begin
if (rst = '0') then
ALUopOutput <= Int3_Zero;
RegWriteOutput <= '0';
ALUsrcOutput <= '0';
TTypeOutput <= '0';
TWriteOutput <= '0';
MemReadOutput <= '0';
MemWriteOutput <= '0';
MemtoRegOutput <= '0';
RegResult <= Int16_Zero;
retoutput <= '0';
elsif (clk'event and clk = '1') then
if (WriteIn = '1') then
ALUopOutput <= ALUopInput;
RegWriteOutput <= RegWriteInput;
ALUsrcOutput <= ALUsrcInput;
TTypeOutput <= TTypeInput;
TWriteOutput <= TWriteInput;
MemReadOutput <= MemReadInput;
MemWriteOutput <= MemWriteInput;
MemtoRegOutput <= MemtoRegInput;
ALUdata1 <= DataInput1;
RegResult <= DataInput2;
if ALUsrcInput = '0' then
ALUdata2 <= DataInput2;
else
ALUdata2 <= ImmediateInput;
end if;
RegReadOutput1 <= RegReadInput1;
RegReadOutput2 <= RegReadInput2;
RegWriteToOutput <= RegWriteToInput;
retoutput <= retinput;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "AudioCodecAvalon"
-- Project :
-------------------------------------------------------------------------------
-- File : AudioCodecAvalon_tb.vhd
-- Author : <fxst@FXST-PC>
-- Company :
-- Created : 2017-05-23
-- Last update: 2017-05-23
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-05-23 1.0 fxst Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity AudioCodecAvalon_tb is
end entity AudioCodecAvalon_tb;
-------------------------------------------------------------------------------
architecture Bhv of AudioCodecAvalon_tb is
-- component generics
constant gDataWidth : natural := 8;
constant gDataWidthLen : natural := 5;
-- component ports
signal csi_clk : std_logic := '1';
signal rsi_reset_n : std_logic := '0';
signal AUD_ADCDAT : std_logic;
signal AUD_ADCLRCK : std_logic;
signal AUD_BCLK : std_logic := '1';
signal AUD_DACDAT : std_logic;
signal AUD_DACLRCK : std_logic;
signal asi_left_data : std_logic_vector(gDataWidth-1 downto 0);
signal asi_left_valid : std_logic;
signal asi_right_data : std_logic_vector(gDataWidth-1 downto 0);
signal asi_right_valid : std_logic;
signal aso_left_data : std_logic_vector(gDataWidth-1 downto 0);
signal aso_left_valid : std_logic;
signal aso_right_data : std_logic_vector(gDataWidth-1 downto 0);
signal aso_right_valid : std_logic;
signal LRC : std_logic := '0';
begin -- architecture Bhv
-- component instantiation
DUT : entity work.AudioCodecAvalon
generic map (
gDataWidth => gDataWidth,
gDataWidthLen => gDataWidthLen)
port map (
csi_clk => csi_clk,
rsi_reset_n => rsi_reset_n,
AUD_ADCDAT => AUD_ADCDAT,
AUD_ADCLRCK => AUD_ADCLRCK,
AUD_BCLK => AUD_BCLK,
AUD_DACDAT => AUD_DACDAT,
AUD_DACLRCK => AUD_DACLRCK,
asi_left_data => asi_left_data,
asi_left_valid => asi_left_valid,
asi_right_data => asi_right_data,
asi_right_valid => asi_right_valid,
aso_left_data => aso_left_data,
aso_left_valid => aso_left_valid,
aso_right_data => aso_right_data,
aso_right_valid => aso_right_valid);
-- clock generation
csi_clk <= not csi_clk after 10 ns; -- 50MHz
-- BCLK generation 48kHz
AUD_BCLK <= not AUD_BCLK after 10 us;
-- LRC generation
LRC <= not LRC after 190 us;
AUD_ADCDAT <= AUD_DACDAT;
AUD_ADCLRCK <= LRC;
AUD_DACLRCK <= LRC;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
rsi_reset_n <= '1' after 10 ns;
asi_left_data <= "11110001" after 0 ns;
asi_left_valid <= '1' after 60 ns;
asi_right_data <= "10001111" after 60 ns;
asi_right_valid <= '1' after 80 ns;
wait;
end process WaveGen_Proc;
end architecture Bhv;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inductor is
port (terminal n1, n2: electrical);
end entity inductor;
----------------------------------------------------------------
architecture ideal of inductor is
constant L: inductance := 0.5;
quantity branch_voltage across branch_current through n1 to n2;
begin
branch_voltage == L* branch_current'dot;
end architecture ideal;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inductor is
port (terminal n1, n2: electrical);
end entity inductor;
----------------------------------------------------------------
architecture ideal of inductor is
constant L: inductance := 0.5;
quantity branch_voltage across branch_current through n1 to n2;
begin
branch_voltage == L* branch_current'dot;
end architecture ideal;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inductor is
port (terminal n1, n2: electrical);
end entity inductor;
----------------------------------------------------------------
architecture ideal of inductor is
constant L: inductance := 0.5;
quantity branch_voltage across branch_current through n1 to n2;
begin
branch_voltage == L* branch_current'dot;
end architecture ideal;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "igmp_processor"
-- Project :
-------------------------------------------------------------------------------
-- File : igmp_processor_tb.vhd
-- Author : <sheac@DRESDEN>
-- Company :
-- Created : 2010-06-26
-- Last update: 2010-06-27
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-06-26 1.0 sheac Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity igmp_processor_tb is
end igmp_processor_tb;
architecture testbench of igmp_processor_tb is
component igmp_processor
generic (
gen_dataWidth : integer);
port (
dataClk : in std_logic;
reset : in std_logic;
in_destIP : in std_logic_vector(31 downto 0);
igmp_data : in std_logic_vector(gen_dataWidth - 1 downto 0);
igmp_vld : in std_logic;
igmp_sof : in std_logic;
igmp_eof : in std_logic;
respond : out std_logic;
rsptime : out std_logic_vector(gen_dataWidth - 1 downto 0));
end component;
-- component generics
constant gen_dataWidth : integer := 8;
-- component ports
signal dataClk : std_logic;
signal reset : std_logic;
signal in_destIP : std_logic_vector(31 downto 0);
signal igmp_data : std_logic_vector(gen_dataWidth - 1 downto 0);
signal igmp_vld : std_logic;
signal igmp_sof : std_logic;
signal igmp_eof : std_logic;
signal respond : std_logic;
signal rsptime : std_logic_vector(gen_dataWidth - 1 downto 0);
begin -- testbench
-- component instantiation
DUT: igmp_processor
generic map (
gen_dataWidth => gen_dataWidth)
port map (
dataClk => dataClk,
reset => reset,
in_destIP => in_destIP,
igmp_data => igmp_data,
igmp_vld => igmp_vld,
igmp_sof => igmp_sof,
igmp_eof => igmp_eof,
respond => respond,
rsptime => rsptime);
process
begin
dataClk <= '1';
wait for 4 ns;
dataClk <= '0';
wait for 4 ns;
end process;
in_destIP <= X"E1234223";
process
begin
reset <= '1';
igmp_data <= (others => '0');
igmp_vld <= '0';
igmp_sof <= '0';
igmp_eof <= '0';
wait for 24 ns;
reset <= '0';
wait for 16 ns;
igmp_data <= X"11";
igmp_vld <= '1';
igmp_sof <= '1';
igmp_eof <= '0';
wait for 8 ns;
igmp_data <= X"64";
igmp_vld <= '1';
igmp_sof <= '0';
igmp_eof <= '0';
wait for 8 ns;
igmp_data <= X"12";
igmp_vld <= '1';
igmp_sof <= '0';
igmp_eof <= '0';
wait for 8 ns;
igmp_data <= X"56";
igmp_vld <= '1';
igmp_sof <= '0';
igmp_eof <= '0';
wait for 8 ns;
igmp_data <= X"E1";
igmp_vld <= '1';
igmp_sof <= '0';
igmp_eof <= '0';
wait for 8 ns;
igmp_data <= X"23";
igmp_vld <= '1';
igmp_sof <= '0';
igmp_eof <= '0';
wait for 8 ns;
igmp_data <= X"42";
igmp_vld <= '1';
igmp_sof <= '0';
igmp_eof <= '0';
wait for 8 ns;
igmp_data <= X"23";
igmp_vld <= '1';
igmp_sof <= '0';
igmp_eof <= '1';
wait for 8 ns;
igmp_eof <= '0';
wait;
end process;
end testbench;
|
-- program counter circuit
-- combines a register and a call/return stack into a program counter with 6 modes
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
-- 000 - increment by constant value (4)
-- 001 - set to value
-- 010 - offset by value
-- 100 - push to stack and set to value
-- 101 - push to stack and offset by value
-- 110 - pop top value from stack
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity program_counter is
port (
-- value for set/offset
val_32 : in std_logic_vector(31 downto 0);
-- clock, rst, clr, en inputs
clk : in std_logic;
rst : in std_logic;
clr : in std_logic;
en : in std_logic;
-- opcode
opcode : in std_logic_vector(2 downto 0);
-- address out
addr_32 : out std_logic_vector(31 downto 0)
);
end entity program_counter;
architecture program_counter_arch of program_counter is
-- component declarations
-- controller component
component pc_controller is
port (
-- opcode
opcode : in std_logic_vector(2 downto 0);
-- control signals
stack_push : out std_logic;
pc_value_select : out std_logic_vector(1 downto 0);
inc_select : out std_logic;
stack_clk_enable : out std_logic
);
end component;
-- register component
component reg_32_bit is
port (
-- input
in_32 : in std_logic_vector(31 downto 0);
-- clk, rst, clr
clk : in std_logic;
rst : in std_logic;
clr : in std_logic;
-- write enable
wr_en : in std_logic;
-- output
out_32 : out std_logic_vector(31 downto 0)
);
end component;
-- stack component
component stack_32_bit is
port (
-- top of stack write
stack_top_write : in std_logic_vector(31 downto 0);
-- push, clk, clk_en, rst
push : in std_logic;
clk : in std_logic;
clk_enable : in std_logic;
rst : in std_logic;
-- top of stack read
stack_top_read : out std_logic_vector(31 downto 0)
);
end component;
-- incrementer component
component incrementer_32_bit is
port (
-- inputs
a_32 : in std_logic_vector(31 downto 0);
b_32 : in std_logic_vector(31 downto 0);
-- output
out_32 : out std_logic_vector(31 downto 0)
);
end component;
-- 4-input 32-bit mux component
component mux_4_32_bit is
port (
-- inputs
in_32_0 : in std_logic_vector(31 downto 0);
in_32_1 : in std_logic_vector(31 downto 0);
in_32_2 : in std_logic_vector(31 downto 0);
in_32_3 : in std_logic_vector(31 downto 0);
-- input select
input_select : in std_logic_vector(1 downto 0);
-- output
out_32 : out std_logic_vector(31 downto 0)
);
end component;
-- 2-input 32-bit mux component
component mux_2_32_bit is
port (
-- inputs
in_32_0 : in std_logic_vector(31 downto 0);
in_32_1 : in std_logic_vector(31 downto 0);
-- input select
input_select : in std_logic;
-- output
out_32 : out std_logic_vector(31 downto 0)
);
end component;
-- signal declarations
-- pc output signal
signal reg_out : std_logic_vector(31 downto 0);
-- pc reg input
signal reg_in : std_logic_vector(31 downto 0);
-- control signals from controller
signal val_select : std_logic_vector(1 downto 0);
signal offset_select : std_logic;
signal stack_push : std_logic;
signal stack_clk_en : std_logic;
-- stack top in and out
signal stack_top_in : std_logic_vector(31 downto 0);
signal stack_top_out : std_logic_vector(31 downto 0);
-- offset result signal
signal offset_result : std_logic_vector(31 downto 0);
-- offset input a signal
signal offset_inc_a : std_logic_vector(31 downto 0);
begin
-- design implementation
-- controller instantiation
controller : pc_controller
port map (
-- opcode mapped to opcode input
opcode => opcode,
-- stack push mapped to stack push signal
stack_push => stack_push,
-- pc val select mapped to val select signal
pc_value_select => val_select,
-- inc select mapped to offset select signal
inc_select => offset_select,
-- stack clock enable mapped to stack clock enable signal
stack_clk_enable => stack_clk_en
);
-- register insantiation
reg : reg_32_bit
port map (
-- input mapped to reg in signal
in_32 => reg_in,
-- clk, rst and clr inputs mapped to clk, rst and clr inputs
clk => clk,
rst => rst,
clr => clr,
-- wr en mapped to en input
wr_en => en,
-- output mapped to reg out signal
out_32 => reg_out
);
-- stack instantiation
stack : stack_32_bit
port map (
-- stack top write mapped to stack top in signal
stack_top_write => stack_top_in,
-- push mapped to stack_push signal
push => stack_push,
-- clk mapped to clk input
clk => clk,
-- clk_enable mapped to stack_clk_en signal
clk_enable => stack_clk_en,
-- rst mapped to rst input
rst => rst,
-- stack top read mapped to stack top out signal
stack_top_read => stack_top_out
);
-- 4-input set mux instantiation
set_mux : mux_4_32_bit
port map (
-- input 0 is offset result
in_32_0 => offset_result,
-- input 1 is set value
in_32_1 => val_32,
-- input 2 is top of stack
in_32_2 => stack_top_out,
-- input 3 is 0
in_32_3 => (others => '0'),
-- input select mapped to val select signal
input_select => val_select,
-- output mapped to reg in signal
out_32 => reg_in
);
-- 2-input offset mux instantiation
offset_mux : mux_2_32_bit
port map (
-- input 0 is constant 4
in_32_0 => (2 => '1', others => '0'),
-- input 1 is input value
in_32_1 => val_32,
-- input select mapped to offset select signal
input_select => offset_select,
-- output mapped to offset operand a
out_32 => offset_inc_a
);
-- offset incrementer instantiation
offset_inc : incrementer_32_bit
port map (
-- operand a is offset operand a from mux
a_32 => offset_inc_a,
-- operand b is current value of register
b_32 => reg_out,
-- result mapped to offset result signal
out_32 => offset_result
);
-- stack top write incrementer instantiation
stack_top_inc : incrementer_32_bit
port map (
-- operand a is current value of register
a_32 => reg_out,
-- operand b is constant 4
b_32 => (2 => '1', others => '0'),
-- output mapped to stack top in
out_32 => stack_top_in
);
-- set address output to current register value
addr_32 <= reg_out;
end architecture program_counter_arch;
|
-------------------------------------------------------------------------------
--
-- File : imx27_wb16_wrapper.vhd
-- Related files : (none)
--
-- Author(s) : Fabrice Mousset (fabrice.mousset@laposte.net)
-- Project : i.MX wrapper to Wishbone bus
--
-- Creation Date : 2007/01/19
--
-- Description : This is the top file of the IP
-------------------------------------------------------------------------------
-- Modifications :
-----
-- 2008/03/05
-- Fabien Marteau (fabien.marteau@armadeus.com)
-- adding comments and changing some signals names
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- ----------------------------------------------------------------------------
Entity imx27_wb16_wrapper is
-- ----------------------------------------------------------------------------
port
(
-- i.MX Signals
imx_address : in std_logic_vector(11 downto 0);
imx_data : inout std_logic_vector(15 downto 0);
imx_cs_n : in std_logic;
imx_oe_n : in std_logic;
imx_eb0_n : in std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone interface signals
wbm_address : out std_logic_vector(12 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end entity;
-- ----------------------------------------------------------------------------
Architecture RTL of imx27_wb16_wrapper is
-- ----------------------------------------------------------------------------
signal write : std_logic;
signal read : std_logic;
signal strobe : std_logic;
signal writedata : std_logic_vector(15 downto 0);
signal address : std_logic_vector(12 downto 0);
begin
-- ----------------------------------------------------------------------------
-- External signals synchronization process
-- ----------------------------------------------------------------------------
process(gls_clk, gls_reset)
begin
if(gls_reset='1') then
write <= '0';
read <= '0';
strobe <= '0';
writedata <= (others => '0');
address <= (others => '0');
elsif(rising_edge(gls_clk)) then
strobe <= not (imx_cs_n) and not(imx_oe_n and imx_eb0_n);
write <= not (imx_cs_n or imx_eb0_n);
read <= not (imx_cs_n or imx_oe_n);
address <= imx_address & '0';
writedata <= imx_data;
end if;
end process;
wbm_address <= address when (strobe = '1') else (others => '0');
wbm_writedata <= writedata when (write = '1') else (others => '0');
wbm_strobe <= strobe;
wbm_write <= write;
wbm_cycle <= strobe;
imx_data <= wbm_readdata when (read = '1') else (others => 'Z');
end architecture RTL;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity agito_shift is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
operands_V : IN STD_LOGIC_VECTOR (26 downto 0);
right_flag : IN STD_LOGIC;
arithmetic_flag : IN STD_LOGIC;
registers_V_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
registers_V_ce0 : OUT STD_LOGIC;
registers_V_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
registers_V_address1 : OUT STD_LOGIC_VECTOR (3 downto 0);
registers_V_ce1 : OUT STD_LOGIC;
registers_V_we1 : OUT STD_LOGIC;
registers_V_d1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of agito_shift is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv9_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv9_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv30_0 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000000000";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_23 : BOOLEAN;
signal r_V_reg_254 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_3_fu_140_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_3_reg_259 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_57 : BOOLEAN;
signal input_V_reg_269 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_65 : BOOLEAN;
signal tmp_2_reg_275 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_76 : BOOLEAN;
signal sel_tmp2_fu_156_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_reg_285 : STD_LOGIC_VECTOR (0 downto 0);
signal i_1_fu_167_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_87 : BOOLEAN;
signal p_058_1_fu_228_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal exitcond_fu_162_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_1_reg_109 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_119 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_fu_144_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_9_fu_244_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal sel_tmp2_fu_156_p0 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_fu_156_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_6_fu_179_p4 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_7_fu_193_p3 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_5_fu_206_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_200_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal sel_tmp1_fu_221_p0 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_5_fu_189_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_7_fu_173_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_4_fu_213_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp1_fu_221_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_2_fu_235_p4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- i_reg_119 assign process. --
i_reg_119_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (exitcond_fu_162_p2 = ap_const_lv1_0))) then
i_reg_119 <= i_1_fu_167_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
i_reg_119 <= ap_const_lv9_0;
end if;
end if;
end process;
-- p_1_reg_109 assign process. --
p_1_reg_109_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (exitcond_fu_162_p2 = ap_const_lv1_0))) then
p_1_reg_109 <= p_058_1_fu_228_p3;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
p_1_reg_109 <= input_V_reg_269;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
input_V_reg_269 <= registers_V_q0;
tmp_2_reg_275 <= registers_V_q0(30 downto 30);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
r_V_reg_254 <= operands_V(17 downto 9);
tmp_3_reg_259 <= tmp_3_fu_140_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
sel_tmp2_reg_285 <= sel_tmp2_fu_156_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, exitcond_fu_162_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
if (not((exitcond_fu_162_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st5_fsm_4, exitcond_fu_162_p2)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((exitcond_fu_162_p2 = ap_const_lv1_0))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st5_fsm_4, exitcond_fu_162_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((exitcond_fu_162_p2 = ap_const_lv1_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_23 assign process. --
ap_sig_bdd_23_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_23 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_57 assign process. --
ap_sig_bdd_57_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_57 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_65 assign process. --
ap_sig_bdd_65_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_65 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_76 assign process. --
ap_sig_bdd_76_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_76 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_87 assign process. --
ap_sig_bdd_87_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_87 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_23)
begin
if (ap_sig_bdd_23) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_57)
begin
if (ap_sig_bdd_57) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_65)
begin
if (ap_sig_bdd_65) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_76)
begin
if (ap_sig_bdd_76) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_87)
begin
if (ap_sig_bdd_87) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
exitcond_fu_162_p2 <= "1" when (i_reg_119 = tmp_3_reg_259) else "0";
i_1_fu_167_p2 <= std_logic_vector(unsigned(i_reg_119) + unsigned(ap_const_lv9_1));
p_058_1_fu_228_p3 <=
r_V_4_fu_213_p3 when (sel_tmp2_reg_285(0) = '1') else
sel_tmp1_fu_221_p3;
r_V_2_fu_235_p4 <= operands_V(26 downto 18);
r_V_4_fu_213_p3 <= (tmp_5_fu_206_p3 & tmp_8_fu_200_p2);
r_V_5_fu_189_p1 <= std_logic_vector(resize(unsigned(r_V_6_fu_179_p4),32));
r_V_6_fu_179_p4 <= p_1_reg_109(31 downto 1);
r_V_7_fu_173_p2 <= std_logic_vector(shift_left(unsigned(p_1_reg_109),to_integer(unsigned('0' & ap_const_lv32_1(31-1 downto 0)))));
registers_V_address0 <= tmp_fu_144_p1(4 - 1 downto 0);
registers_V_address1 <= tmp_9_fu_244_p1(4 - 1 downto 0);
-- registers_V_ce0 assign process. --
registers_V_ce0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
registers_V_ce0 <= ap_const_logic_1;
else
registers_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- registers_V_ce1 assign process. --
registers_V_ce1_assign_proc : process(ap_sig_cseq_ST_st5_fsm_4)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
registers_V_ce1 <= ap_const_logic_1;
else
registers_V_ce1 <= ap_const_logic_0;
end if;
end process;
registers_V_d1 <= p_1_reg_109;
-- registers_V_we1 assign process. --
registers_V_we1_assign_proc : process(ap_sig_cseq_ST_st5_fsm_4, exitcond_fu_162_p2)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((exitcond_fu_162_p2 = ap_const_lv1_0))))) then
registers_V_we1 <= ap_const_logic_1;
else
registers_V_we1 <= ap_const_logic_0;
end if;
end process;
sel_tmp1_fu_221_p0 <= (0=>right_flag, others=>'-');
sel_tmp1_fu_221_p3 <=
r_V_5_fu_189_p1 when (sel_tmp1_fu_221_p0(0) = '1') else
r_V_7_fu_173_p2;
sel_tmp2_fu_156_p0 <= (0=>right_flag, others=>'-');
sel_tmp2_fu_156_p1 <= (0=>arithmetic_flag, others=>'-');
sel_tmp2_fu_156_p2 <= (sel_tmp2_fu_156_p0 and sel_tmp2_fu_156_p1);
tmp_3_fu_140_p1 <= operands_V(9 - 1 downto 0);
tmp_5_fu_206_p3 <= input_V_reg_269(31 downto 31);
tmp_7_fu_193_p3 <= (tmp_2_reg_275 & ap_const_lv30_0);
tmp_8_fu_200_p2 <= (tmp_7_fu_193_p3 or r_V_6_fu_179_p4);
tmp_9_fu_244_p1 <= std_logic_vector(resize(unsigned(r_V_2_fu_235_p4),64));
tmp_fu_144_p1 <= std_logic_vector(resize(unsigned(r_V_reg_254),64));
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity Chip_tb is
end Chip_tb;
architecture behavior of Chip_tb is
component Chip
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Cpu_En_i : in std_logic;
Dbg_En_i : in std_logic;
-- Dbg_UART_RxD_i : in std_logic;
-- Dbg_UART_TxD_o : out std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_b : inout std_logic;
P1_b : inout std_logic_vector(7 downto 0);
P2_b : inout std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_b : out std_logic;
I2CSDA_b : inout std_logic;
-- OneWire_b : inout std_logic;
-- PWM_i : in std_logic;
-- SENT_i : in std_logic;
-- SPC_b : inout std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0));
end component;
component adt7410_model
port (
scl_i : in std_logic;
sda_io : inout std_logic;
i2c_addr_i : in std_logic_vector(1 downto 0);
int_o : out std_logic;
ct_o : out std_logic;
temp_i : in std_logic_vector(15 downto 0));
end component;
component ExtNames
port (
I2CFSM_Done : out std_logic;
CpuIntr : out std_logic;
SensorValue : out std_logic_vector(15 downto 0)
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal Cpu_En_i : std_logic := '1';
signal Dbg_En_i : std_logic;
-- signal Dbg_UART_RxD_i : std_logic;
-- signal Dbg_UART_TxD_o : std_logic;
signal Dbg_SCL_i : std_logic;
signal Dbg_SDA_b : std_logic;
signal P1_b : std_logic_vector(7 downto 0);
signal P2_b : std_logic_vector(7 downto 0);
signal UartRxD_i : std_logic;
signal UartTxD_o : std_logic;
signal SCK_o : std_logic;
signal MOSI_o : std_logic;
signal MISO_i : std_logic := '0';
signal Inputs_i : std_logic_vector(7 downto 0);
signal Outputs_o : std_logic_vector(7 downto 0);
signal SPIMISO_i : std_logic;
signal SPIMOSI_o : std_logic;
signal SPISCK_o : std_logic;
signal I2CSCL_b : std_logic;
signal I2CSDA_b : std_logic;
-- signal OneWire_b : std_logic;
-- signal PWM_i : std_logic;
-- signal SENT_i : std_logic;
-- signal SPC_b : std_logic;
signal AdcConvComplete_i : std_logic;
signal AdcDoConvert_o : std_logic;
signal AdcValue_i : std_logic_vector(9 downto 0);
-- look into the ADT7310 app
-- alias I2CFSM_Done_i is << signal .adt7310_tb.DUT.I2CFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the I2CFSM_Done_i signal.
signal I2CFSM_Done_e : std_logic; -- directly from inside I2C_FSM
signal CpuIntr_e : std_logic; -- directly from inside I2C_FSM
signal SensorValue_e : std_logic_vector(15 downto 0);
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- I2CFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal I2CFSM_Done_d : std_logic; -- sightly delayed
signal CpuIntr_o : std_logic; -- sightly delayed
signal SensorValue_o : std_logic_vector(15 downto 0); -- sightly delayed
signal SensorValue_real : real;
-- ADT7410 component ports
signal CT_n_s : std_logic;
signal INT_n_s : std_logic;
signal Temp_s : real := 23.7;
signal TempBin_s : std_logic_vector(15 downto 0);
-- The timer has to wait for 240ms. With a 16 bit resolution, the maximumn
-- counting periode is 3.66us. Here we set the clock signal to 10us = 100kHz.
-- The timer is preset to 24000.
constant ClkPeriode : time := 10 us;
begin
DUT: Chip
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Cpu_En_i => Cpu_En_i,
Dbg_En_i => Dbg_En_i,
-- Dbg_UART_RxD_i => Dbg_UART_RxD_i,
-- Dbg_UART_TxD_o => Dbg_UART_TxD_o,
Dbg_SCL_i => Dbg_SCL_i,
Dbg_SDA_b => Dbg_SDA_b,
P1_b => P1_b,
P2_b => P2_b,
UartRxD_i => UartRxD_i,
UartTxD_o => UartTxD_o,
SCK_o => SCK_o,
MOSI_o => MOSI_o,
MISO_i => MISO_i,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
SPIMISO_i => SPIMISO_i,
SPIMOSI_o => SPIMOSI_o,
SPISCK_o => SPISCK_o,
I2CSCL_b => I2CSCL_b,
I2CSDA_b => I2CSDA_b,
-- OneWire_b => OneWire_b,
-- PWM_i => PWM_i,
-- SENT_i => SENT_i,
-- SPC_b => SPC_b,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i
);
Inputs_i <= (others => '0');
Cpu_En_i <= '1';
Dbg_En_i <= '0';
-- Dbg_UART_RxD_i <= '1';
Dbg_SCL_i <= 'H';
Dbg_SDA_b <= 'H';
P1_b <= (others => 'H');
P2_b <= (others => 'H');
UartRxD_i <= '1';
MISO_i <= '0';
I2CSCL_b <= 'H';
I2CSDA_b <= 'H';
-- OneWire_b <= 'H';
-- PWM_i <= 'H';
-- SENT_i <= 'H';
-- SPC_b <= 'H';
AdcConvComplete_i <= '0';
AdcValue_i <= (others => '0');
ExtNames_1: ExtNames
port map (
I2CFSM_Done => I2CFSM_Done_e,
CpuIntr => CpuIntr_e,
SensorValue => SensorValue_e
);
I2CFSM_Done_d <= I2CFSM_Done_e after 1.0 ns;
CpuIntr_o <= CpuIntr_e after 1.0 ns;
SensorValue_o <= SensorValue_e after 1.0 ns;
TempBin_s <= std_logic_vector(to_unsigned(integer(Temp_s*128.0),16));
SensorValue_real <= real(to_integer(unsigned(SensorValue_o)))/128.0;
-- I2CSDA_i <= to_01(I2C_SDA_s) after 0.2 us;
adt7410_1: adt7410_model
port map (
scl_i => I2CSCL_b,
sda_io => I2CSDA_b,
i2c_addr_i => "00",
INT_o => INT_n_s,
CT_o => CT_n_s,
temp_i => TempBin_s);
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
wait for 2.3*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
wait for 1.3*ClkPeriode; -- wait until spi_master's SCK_o goes '1' to conform to CPOL_i = '1'
Temp_s <= 23.7; -- degree C
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
wait until I2CFSM_Done_d = '1' and I2CFSM_Done_d'quiet(10 ns);
report "Starting with test pattern" severity note;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- The digital value is 128*Temp_s (plus/minus rounding to nearest
-- modulo 8). The threshold for too large changes is 30 (see
-- sensorfsm.vhd).
-- 23.7°C --> 3032
-- 25.7°C --> 3288 (delta: | 256| > 30)
-- 25.6°C --> 3280 (delta: | -8| < 30)
-- 25.5°C --> 3264 (delta: | -24| < 30)
-- 25.4°C --> 3248 (delta: | -40| >= 30)
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.7;
wait until I2CFSM_Done_d = '1' and I2CFSM_Done_d'quiet(10 ns);
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.6;
wait until I2CFSM_Done_d = '1' and I2CFSM_Done_d'quiet(10 ns);
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after I2CFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.5;
wait until I2CFSM_Done_d = '1' and I2CFSM_Done_d'quiet(10 ns);
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after I2CFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.4;
wait until I2CFSM_Done_d = '1' and I2CFSM_Done_d'quiet(10 ns);
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
wait for 100 ms;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1781.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
Package c09s06b00x00p04n05i01781pkg is
type info is record
field_1 : integer;
field_2 : real;
end record;
type stuff is array (Integer range 1 to 2) of info;
end c09s06b00x00p04n05i01781pkg;
use work.c09s06b00x00p04n05i01781pkg.all;
entity c09s06b00x00p04n05i01781ent_a is
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector ;
gB : stuff
);
end c09s06b00x00p04n05i01781ent_a;
use work.c09s06b00x00p04n05i01781pkg.all;
architecture c09s06b00x00p04n05i01781arch_a of c09s06b00x00p04n05i01781ent_a is
-- Check that the data was passed...
begin
TESTING: PROCESS
BEGIN
assert NOT( g0 = True and
g1 = '0' and
g2 = '@' and
g3 = NOTE and
g4 = 123456789 and
g5 = 987654321.5 and
g6 = 110 ns and
g7 = 12312 and
g8 = 3423 and
g9 = "16 characters OK" and
gA = B"01010010100101010010101001010100"and
gB = ((123, 456.7 ), (890, 135.7)))
report "***PASSED TEST: c09s06b00x00p04n05i01781"
severity NOTE;
assert ( g0 = True and
g1 = '0' and
g2 = '@' and
g3 = NOTE and
g4 = 123456789 and
g5 = 987654321.5 and
g6 = 110 ns and
g7 = 12312 and
g8 = 3423 and
g9 = "16 characters OK" and
gA = B"01010010100101010010101001010100"and
gB = ((123, 456.7 ), (890, 135.7)))
report "***FAILED TEST: c09s06b00x00p04n05i01781 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
end c09s06b00x00p04n05i01781arch_a;
-------------------------------------------------------------------------
ENTITY c09s06b00x00p04n05i01781ent IS
END c09s06b00x00p04n05i01781ent;
use work.c09s06b00x00p04n05i01781pkg.all;
ARCHITECTURE c09s06b00x00p04n05i01781arch OF c09s06b00x00p04n05i01781ent IS
subtype reg32 is Bit_vector ( 31 downto 0 );
subtype string16 is String ( 1 to 16 );
component MultiType
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector ;
gB : stuff
);
end component;
for u1 : MultiType use entity work.c09s06b00x00p04n05i01781ent_a(c09s06b00x00p04n05i01781arch_a);
BEGIN
u1 : MultiType
generic map (
True,
'0',
'@',
NOTE,
123456789,
987654321.5,
110 ns,
12312,
3423,
"16 characters OK",
B"0101_0010_1001_0101_0010_1010_0101_0100",
gB(2) => ( 890, 135.7 ),
gB(1) => ( 123, 456.7 )
);
END c09s06b00x00p04n05i01781arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1781.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
Package c09s06b00x00p04n05i01781pkg is
type info is record
field_1 : integer;
field_2 : real;
end record;
type stuff is array (Integer range 1 to 2) of info;
end c09s06b00x00p04n05i01781pkg;
use work.c09s06b00x00p04n05i01781pkg.all;
entity c09s06b00x00p04n05i01781ent_a is
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector ;
gB : stuff
);
end c09s06b00x00p04n05i01781ent_a;
use work.c09s06b00x00p04n05i01781pkg.all;
architecture c09s06b00x00p04n05i01781arch_a of c09s06b00x00p04n05i01781ent_a is
-- Check that the data was passed...
begin
TESTING: PROCESS
BEGIN
assert NOT( g0 = True and
g1 = '0' and
g2 = '@' and
g3 = NOTE and
g4 = 123456789 and
g5 = 987654321.5 and
g6 = 110 ns and
g7 = 12312 and
g8 = 3423 and
g9 = "16 characters OK" and
gA = B"01010010100101010010101001010100"and
gB = ((123, 456.7 ), (890, 135.7)))
report "***PASSED TEST: c09s06b00x00p04n05i01781"
severity NOTE;
assert ( g0 = True and
g1 = '0' and
g2 = '@' and
g3 = NOTE and
g4 = 123456789 and
g5 = 987654321.5 and
g6 = 110 ns and
g7 = 12312 and
g8 = 3423 and
g9 = "16 characters OK" and
gA = B"01010010100101010010101001010100"and
gB = ((123, 456.7 ), (890, 135.7)))
report "***FAILED TEST: c09s06b00x00p04n05i01781 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
end c09s06b00x00p04n05i01781arch_a;
-------------------------------------------------------------------------
ENTITY c09s06b00x00p04n05i01781ent IS
END c09s06b00x00p04n05i01781ent;
use work.c09s06b00x00p04n05i01781pkg.all;
ARCHITECTURE c09s06b00x00p04n05i01781arch OF c09s06b00x00p04n05i01781ent IS
subtype reg32 is Bit_vector ( 31 downto 0 );
subtype string16 is String ( 1 to 16 );
component MultiType
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector ;
gB : stuff
);
end component;
for u1 : MultiType use entity work.c09s06b00x00p04n05i01781ent_a(c09s06b00x00p04n05i01781arch_a);
BEGIN
u1 : MultiType
generic map (
True,
'0',
'@',
NOTE,
123456789,
987654321.5,
110 ns,
12312,
3423,
"16 characters OK",
B"0101_0010_1001_0101_0010_1010_0101_0100",
gB(2) => ( 890, 135.7 ),
gB(1) => ( 123, 456.7 )
);
END c09s06b00x00p04n05i01781arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1781.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
Package c09s06b00x00p04n05i01781pkg is
type info is record
field_1 : integer;
field_2 : real;
end record;
type stuff is array (Integer range 1 to 2) of info;
end c09s06b00x00p04n05i01781pkg;
use work.c09s06b00x00p04n05i01781pkg.all;
entity c09s06b00x00p04n05i01781ent_a is
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector ;
gB : stuff
);
end c09s06b00x00p04n05i01781ent_a;
use work.c09s06b00x00p04n05i01781pkg.all;
architecture c09s06b00x00p04n05i01781arch_a of c09s06b00x00p04n05i01781ent_a is
-- Check that the data was passed...
begin
TESTING: PROCESS
BEGIN
assert NOT( g0 = True and
g1 = '0' and
g2 = '@' and
g3 = NOTE and
g4 = 123456789 and
g5 = 987654321.5 and
g6 = 110 ns and
g7 = 12312 and
g8 = 3423 and
g9 = "16 characters OK" and
gA = B"01010010100101010010101001010100"and
gB = ((123, 456.7 ), (890, 135.7)))
report "***PASSED TEST: c09s06b00x00p04n05i01781"
severity NOTE;
assert ( g0 = True and
g1 = '0' and
g2 = '@' and
g3 = NOTE and
g4 = 123456789 and
g5 = 987654321.5 and
g6 = 110 ns and
g7 = 12312 and
g8 = 3423 and
g9 = "16 characters OK" and
gA = B"01010010100101010010101001010100"and
gB = ((123, 456.7 ), (890, 135.7)))
report "***FAILED TEST: c09s06b00x00p04n05i01781 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
end c09s06b00x00p04n05i01781arch_a;
-------------------------------------------------------------------------
ENTITY c09s06b00x00p04n05i01781ent IS
END c09s06b00x00p04n05i01781ent;
use work.c09s06b00x00p04n05i01781pkg.all;
ARCHITECTURE c09s06b00x00p04n05i01781arch OF c09s06b00x00p04n05i01781ent IS
subtype reg32 is Bit_vector ( 31 downto 0 );
subtype string16 is String ( 1 to 16 );
component MultiType
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector ;
gB : stuff
);
end component;
for u1 : MultiType use entity work.c09s06b00x00p04n05i01781ent_a(c09s06b00x00p04n05i01781arch_a);
BEGIN
u1 : MultiType
generic map (
True,
'0',
'@',
NOTE,
123456789,
987654321.5,
110 ns,
12312,
3423,
"16 characters OK",
B"0101_0010_1001_0101_0010_1010_0101_0100",
gB(2) => ( 890, 135.7 ),
gB(1) => ( 123, 456.7 )
);
END c09s06b00x00p04n05i01781arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/26/2016 11:44:06 PM
-- Design Name:
-- Module Name: sim_pbkdf2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
-- Takes about 1400us to complete
-- signal 'i' will be 0x157002
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.sha1_pkg.all;
entity sim_pbkdf2 is
end sim_pbkdf2;
architecture Behavioral of sim_pbkdf2 is
component pbkdf2_main is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
load_i : in std_ulogic;
mk_i : in mk_data;
ssid_i : in ssid_data;
dat_o : out w_pmk;
valid_o : out std_ulogic
);
end component;
signal valid : std_ulogic;
signal load : std_ulogic := '0';
signal clk_i : std_ulogic := '0';
signal rst_i : std_ulogic := '0';
signal mk : mk_data;
signal ssid : ssid_data;
signal dat : w_pmk;
signal i: integer range 0 to 65535;
constant clock_period : time := 1 ns;
begin
pbkdf2: pbkdf2_main port map (clk_i,rst_i, load, mk, ssid, dat, valid);
stim_proc: process
begin
rst_i <= '0';
i <= 0;
load <= '0';
for x in 0 to 35 loop
ssid(x) <= X"00";
end loop;
--linksys
--6c 69 6e 6b 73 79 73
ssid(0) <= X"6C";
ssid(1) <= X"69";
ssid(2) <= X"6E";
ssid(3) <= X"6B";
ssid(4) <= X"73";
ssid(5) <= X"79";
ssid(6) <= X"73";
--dictionary
--64 69 63 74 69 6f 6e 61 72 79
for x in 0 to 9 loop
mk(x) <= X"00";
end loop;
mk(0) <= X"64";
mk(1) <= X"69";
mk(2) <= X"63";
mk(3) <= X"74";
mk(4) <= X"69";
mk(5) <= X"6F";
mk(6) <= X"6E";
mk(7) <= X"61";
mk(8) <= X"72";
mk(9) <= X"79";
wait until rising_edge(clk_i);
rst_i <= '1';
wait until rising_edge(clk_i);
rst_i <= '0';
wait until rising_edge(clk_i);
load <= '1';
wait until rising_edge(clk_i);
load <= '0';
wait until rising_edge(clk_i);
while valid = '0' loop
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
-- 5df920b5481ed70538dd5fd02423d7e2522205feeebb974cad08a52b5613ede2
assert not (
dat(0) = X"5df920b5" and
dat(0) = X"481ed705" and
dat(0) = X"38dd5fd0" and
dat(0) = X"2423d7e2" and
dat(0) = X"522205fe" and
dat(0) = X"eebb974c" and
dat(0) = X"ad08a52b" and
dat(0) = X"5613ede2"
)
report "Data output is wrong."
severity ERROR;
wait;
end process;
--ssid_dat <= ssid_data(handshake_dat(0 to 35)); --36
clock_process: process
begin
clk_i <= '0';
wait for clock_period/2;
clk_i <= '1';
wait for clock_period/2;
end process;
end Behavioral;
|
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