content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- multiplexes valid groups, output is registered
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity group_selector is
port(
clock : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_input_ready : in std_logic;
output : out std_logic_vector(31 downto 0);
output_ready : out std_logic;
disabledGroups : in std_logic_vector(3 downto 0)
);
end group_selector;
architecture behavioral of group_selector is
signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0);
signal tmp : std_logic_vector(31 downto 0);
begin
ib0 <= la_input(7 downto 0);
ib1 <= la_input(15 downto 8);
ib2 <= la_input(23 downto 16);
ib3 <= la_input(31 downto 24);
tmp <= -- select 8-bit enabled group
x"000000" & ib0 when disabledGroups = "1110" else
x"000000" & ib1 when disabledGroups = "1101" else
x"000000" & ib2 when disabledGroups = "1011" else
x"000000" & ib3 when disabledGroups = "0111" else
-- select 2 8-bit enabled groups
x"0000" & ib1 & ib0 when disabledGroups = "1100" else
x"0000" & ib2 & ib0 when disabledGroups = "1010" else
x"0000" & ib3 & ib0 when disabledGroups = "0110" else
x"0000" & ib2 & ib1 when disabledGroups = "1001" else
x"0000" & ib3 & ib1 when disabledGroups = "0101" else
x"0000" & ib3 & ib2 when disabledGroups = "0011" else
-- clear unused group
ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else
ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else
ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else
x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else
-- full
la_input when disabledGroups = "0000" else
(others => 'X');
process (clock)
begin
if rising_edge(clock) then
output <= tmp;
output_ready <= la_input_ready;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- multiplexes valid groups, output is registered
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity group_selector is
port(
clock : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_input_ready : in std_logic;
output : out std_logic_vector(31 downto 0);
output_ready : out std_logic;
disabledGroups : in std_logic_vector(3 downto 0)
);
end group_selector;
architecture behavioral of group_selector is
signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0);
signal tmp : std_logic_vector(31 downto 0);
begin
ib0 <= la_input(7 downto 0);
ib1 <= la_input(15 downto 8);
ib2 <= la_input(23 downto 16);
ib3 <= la_input(31 downto 24);
tmp <= -- select 8-bit enabled group
x"000000" & ib0 when disabledGroups = "1110" else
x"000000" & ib1 when disabledGroups = "1101" else
x"000000" & ib2 when disabledGroups = "1011" else
x"000000" & ib3 when disabledGroups = "0111" else
-- select 2 8-bit enabled groups
x"0000" & ib1 & ib0 when disabledGroups = "1100" else
x"0000" & ib2 & ib0 when disabledGroups = "1010" else
x"0000" & ib3 & ib0 when disabledGroups = "0110" else
x"0000" & ib2 & ib1 when disabledGroups = "1001" else
x"0000" & ib3 & ib1 when disabledGroups = "0101" else
x"0000" & ib3 & ib2 when disabledGroups = "0011" else
-- clear unused group
ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else
ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else
ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else
x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else
-- full
la_input when disabledGroups = "0000" else
(others => 'X');
process (clock)
begin
if rising_edge(clock) then
output <= tmp;
output_ready <= la_input_ready;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- multiplexes valid groups, output is registered
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity group_selector is
port(
clock : in std_logic;
la_input : in std_logic_vector(31 downto 0);
la_input_ready : in std_logic;
output : out std_logic_vector(31 downto 0);
output_ready : out std_logic;
disabledGroups : in std_logic_vector(3 downto 0)
);
end group_selector;
architecture behavioral of group_selector is
signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0);
signal tmp : std_logic_vector(31 downto 0);
begin
ib0 <= la_input(7 downto 0);
ib1 <= la_input(15 downto 8);
ib2 <= la_input(23 downto 16);
ib3 <= la_input(31 downto 24);
tmp <= -- select 8-bit enabled group
x"000000" & ib0 when disabledGroups = "1110" else
x"000000" & ib1 when disabledGroups = "1101" else
x"000000" & ib2 when disabledGroups = "1011" else
x"000000" & ib3 when disabledGroups = "0111" else
-- select 2 8-bit enabled groups
x"0000" & ib1 & ib0 when disabledGroups = "1100" else
x"0000" & ib2 & ib0 when disabledGroups = "1010" else
x"0000" & ib3 & ib0 when disabledGroups = "0110" else
x"0000" & ib2 & ib1 when disabledGroups = "1001" else
x"0000" & ib3 & ib1 when disabledGroups = "0101" else
x"0000" & ib3 & ib2 when disabledGroups = "0011" else
-- clear unused group
ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else
ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else
ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else
x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else
-- full
la_input when disabledGroups = "0000" else
(others => 'X');
process (clock)
begin
if rising_edge(clock) then
output <= tmp;
output_ready <= la_input_ready;
end if;
end process;
end behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity harris is
generic (
LINE_WIDTH_MAX : integer := 320;
IN_SIZE : integer := 8;
OUT_SIZE : integer := 8;
CLK_PROC_FREQ : integer := 48000000
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
in_data : in std_logic_vector((IN_SIZE-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector((OUT_SIZE-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end harris;
architecture rtl of harris is
component harris_slave
port (
clk_proc : in std_logic;
reset_n : in std_logic;
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
enable_o : out std_logic;
widthimg_o : out std_logic_vector(15 downto 0)
);
end component;
component harris_process
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
signal enable_s : std_logic;
signal widthimg_s : std_logic_vector(15 downto 0);
begin
harris_slave_inst : harris_slave
port map (
clk_proc => clk_proc,
reset_n => reset_n,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o,
enable_o => enable_s,
widthimg_o => widthimg_s
);
harris_process_inst : harris_process
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv,
enable_i => enable_s,
widthimg_i => widthimg_s
);
end rtl;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for labeled assignment statements
library ieee;
use ieee.std_logic_1164.all;
entity labeled_assign is
port (input : in std_logic_vector(7 downto 0);
output : out std_Logic_vector(7 downto 0));
end entity;
architecture test of labeled_assign is
signal test_rx : std_logic_vector (7 downto 0);
begin
first_label: test_rx <= x"aa";
process(input)
variable tmp : std_logic_vector(7 downto 0);
begin
second_label: tmp := input;
third_label: output <= tmp xor x"cc";
end process;
end architecture;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for labeled assignment statements
library ieee;
use ieee.std_logic_1164.all;
entity labeled_assign is
port (input : in std_logic_vector(7 downto 0);
output : out std_Logic_vector(7 downto 0));
end entity;
architecture test of labeled_assign is
signal test_rx : std_logic_vector (7 downto 0);
begin
first_label: test_rx <= x"aa";
process(input)
variable tmp : std_logic_vector(7 downto 0);
begin
second_label: tmp := input;
third_label: output <= tmp xor x"cc";
end process;
end architecture;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for labeled assignment statements
library ieee;
use ieee.std_logic_1164.all;
entity labeled_assign is
port (input : in std_logic_vector(7 downto 0);
output : out std_Logic_vector(7 downto 0));
end entity;
architecture test of labeled_assign is
signal test_rx : std_logic_vector (7 downto 0);
begin
first_label: test_rx <= x"aa";
process(input)
variable tmp : std_logic_vector(7 downto 0);
begin
second_label: tmp := input;
third_label: output <= tmp xor x"cc";
end process;
end architecture;
|
package some_package is
-- this signal seems to be problematic
-- uncomment to reproduce the bug
signal some_signal :bit;
component some_component end component;
end package;
entity some_component is end entity;
architecture a of some_component is begin end architecture;
entity wrapper is end entity;
architecture a of wrapper is begin
inst :work.some_package.some_component;
end architecture;
entity test is end entity;
architecture a of test is
component wrapper is end component;
signal dummy :bit;
begin
inst :if false generate inst :wrapper; end generate;
process begin
wait for 1 ns; dummy <= '1';
wait for 1 ns; dummy <= '0';
wait;
end process;
end architecture;
|
package some_package is
-- this signal seems to be problematic
-- uncomment to reproduce the bug
signal some_signal :bit;
component some_component end component;
end package;
entity some_component is end entity;
architecture a of some_component is begin end architecture;
entity wrapper is end entity;
architecture a of wrapper is begin
inst :work.some_package.some_component;
end architecture;
entity test is end entity;
architecture a of test is
component wrapper is end component;
signal dummy :bit;
begin
inst :if false generate inst :wrapper; end generate;
process begin
wait for 1 ns; dummy <= '1';
wait for 1 ns; dummy <= '0';
wait;
end process;
end architecture;
|
package some_package is
-- this signal seems to be problematic
-- uncomment to reproduce the bug
signal some_signal :bit;
component some_component end component;
end package;
entity some_component is end entity;
architecture a of some_component is begin end architecture;
entity wrapper is end entity;
architecture a of wrapper is begin
inst :work.some_package.some_component;
end architecture;
entity test is end entity;
architecture a of test is
component wrapper is end component;
signal dummy :bit;
begin
inst :if false generate inst :wrapper; end generate;
process begin
wait for 1 ns; dummy <= '1';
wait for 1 ns; dummy <= '0';
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_MIN_MAX_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
FONCTION : in STD_LOGIC_VECTOR( 1 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MMX_MIN_MAX_8b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
REPORT "(IMS) MMX 8bis MIN RESSOURCE : ALLOCATION OK !";
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp3 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp4 : STD_LOGIC_VECTOR(7 downto 0);
variable bTemp1 : STD_LOGIC;
variable bTemp2 : STD_LOGIC;
variable bTemp3 : STD_LOGIC;
variable bTemp4 : STD_LOGIC;
begin
IF( UNSIGNED(INPUT_1( 7 downto 0)) < UNSIGNED(INPUT_2( 7 downto 0)) ) THEN bTemp1 := 1; ELSE bTemp1 := 0; END IF;
IF( UNSIGNED(INPUT_1(15 downto 8)) < UNSIGNED(INPUT_2(15 downto 8)) ) THEN bTemp2 := 1; ELSE bTemp2 := 0; END IF;
IF( UNSIGNED(INPUT_1(23 downto 16)) < UNSIGNED(INPUT_2(23 downto 16)) ) THEN bTemp3 := 1; ELSE bTemp3 := 0; END IF;
IF( UNSIGNED(INPUT_1(31 downto 24)) < UNSIGNED(INPUT_2(31 downto 24)) ) THEN bTemp4 := 1; ELSE bTemp4 := 0; END IF;
bTemp1 := bTemp1 XOR FONCTION(0);
bTemp2 := bTemp2 XOR FONCTION(0);
bTemp3 := bTemp3 XOR FONCTION(0);
bTemp4 := bTemp4 XOR FONCTION(0);
CASE bTemp1 IS
WHEN '0' => rTemp1 := INPUT_1(7 downto 0);
WHEN '1' => rTemp1 := INPUT_2(7 downto 0);
WHEN OTHERS => null;
END CASE;
CASE bTemp2 IS
WHEN '0' => rTemp2 := INPUT_1(15 downto 8);
WHEN '1' => rTemp2 := INPUT_2(15 downto 8);
WHEN OTHERS => null;
END CASE;
CASE bTemp3 IS
WHEN '0' => rTemp3 := INPUT_1(23 downto 16);
WHEN '1' => rTemp3 := INPUT_2(23 downto 16);
WHEN OTHERS => null;
END CASE;
CASE bTemp4 IS
WHEN '0' => rTemp4 := INPUT_1(31 downto 24);
WHEN '1' => rTemp4 := INPUT_2(31 downto 24);
WHEN OTHERS => null;
END CASE;
OUTPUT_1 <= (rTemp4 & rTemp3 & rTemp2 & rTemp1);
end process;
-------------------------------------------------------------------------
end;
|
architecture rtl of fifo is
begin
GEN_LABEL : case expression generate
when OTHERS =>
end generate;
GEN_LABEL : case expression generate
when OTHERS =>
end generate;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc357.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00357ent IS
END c03s02b01x01p02n01i00357ent;
ARCHITECTURE c03s02b01x01p02n01i00357arch OF c03s02b01x01p02n01i00357ent IS
type page is array (0 to X"FFF") of bit;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00357 - Both bounds in the constrained array definition must have the same discrete type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00357arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc357.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00357ent IS
END c03s02b01x01p02n01i00357ent;
ARCHITECTURE c03s02b01x01p02n01i00357arch OF c03s02b01x01p02n01i00357ent IS
type page is array (0 to X"FFF") of bit;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00357 - Both bounds in the constrained array definition must have the same discrete type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00357arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc357.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00357ent IS
END c03s02b01x01p02n01i00357ent;
ARCHITECTURE c03s02b01x01p02n01i00357arch OF c03s02b01x01p02n01i00357ent IS
type page is array (0 to X"FFF") of bit;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00357 - Both bounds in the constrained array definition must have the same discrete type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00357arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNFEQ57IEX is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "000";
width : positive := 3);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNFEQ57IEX is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 3,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "000")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNFEQ57IEX is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "000";
width : positive := 3);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNFEQ57IEX is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 3,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "000")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
use work.issue_pkg.t_one_two; -- does not work
--use work.issue_pkg.all; -- works
entity issue is
port (
clk : in std_logic;
input : in t_one_two;
output : out std_logic
);
end entity issue;
architecture rtl of issue is
begin -- architecture rtl
process (clk) is
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if input = one then
output <= '1';
else
output <= '0';
end if;
end if;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use work.issue_pkg.t_one_two; -- does not work
--use work.issue_pkg.all; -- works
entity issue is
port (
clk : in std_logic;
input : in t_one_two;
output : out std_logic
);
end entity issue;
architecture rtl of issue is
begin -- architecture rtl
process (clk) is
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if input = one then
output <= '1';
else
output <= '0';
end if;
end if;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity map2 is
port
(
F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15: out std_logic_vector(31 downto 0)
);
end map2;
architecture map2_struct of map2 is
begin
F0 <= "00000000000000011100000011000000";
F1 <= "00000001100000001000000011000000";
F2 <= "00000001100000000000000011000000";
F3 <= "00000001100000000000000011000000";
F4 <= "00000001111000011100000011000000";
F5 <= "00000000111000000000000011000000";
F6 <= "00000000001000000000000011000000";
F7 <= "00000110001000000010000000000000";
F8 <= "00000110000000000000000011000000";
F9 <= "00000000000001110000000011000000";
F10 <= "00000011000011100001000011000000";
F11 <= "00000011000000000001000011000000";
F12 <= "00000001110000000000000011000000";
F13 <= "00000000011100000100000011000000";
F14 <= "00000011000000000000000011000000";
F15 <= "00000000000110000000000011000000";
end map2_struct; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grethm
-- File: grethm.vhd
-- Author: Jiri Gaisler
-- Description: Module to select between greth and greth1g
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
entity grethm is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of grethm is
begin
m100 : if giga = 0 generate
u0 : greth generic map ( hindex, pindex, paddr, pmask, pirq,
memtech, ifg_gap, attempt_limit, backoff_limit, slot_time, mdcscaler,
enable_mdio, fifosize, nsync, edcl, edclbufsz, macaddrh, macaddrl,
ipaddrh, ipaddrl, phyrstadr, rmii, oepol, scanen)
port map ( rst, clk, ahbmi, ahbmo, apbi, apbo, ethi, etho);
end generate;
m1000 : if giga = 1 generate
u0 : greth_gbit generic map ( hindex, pindex, paddr, pmask, pirq,
memtech, ifg_gap, attempt_limit, backoff_limit, slot_time, mdcscaler,
nsync, edcl, edclbufsz, burstlength, macaddrh, macaddrl, ipaddrh,
ipaddrl, phyrstadr, sim, oepol, scanen)
port map ( rst, clk, ahbmi, ahbmo, apbi, apbo, ethi, etho);
end generate;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grethm
-- File: grethm.vhd
-- Author: Jiri Gaisler
-- Description: Module to select between greth and greth1g
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
entity grethm is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of grethm is
begin
m100 : if giga = 0 generate
u0 : greth generic map ( hindex, pindex, paddr, pmask, pirq,
memtech, ifg_gap, attempt_limit, backoff_limit, slot_time, mdcscaler,
enable_mdio, fifosize, nsync, edcl, edclbufsz, macaddrh, macaddrl,
ipaddrh, ipaddrl, phyrstadr, rmii, oepol, scanen)
port map ( rst, clk, ahbmi, ahbmo, apbi, apbo, ethi, etho);
end generate;
m1000 : if giga = 1 generate
u0 : greth_gbit generic map ( hindex, pindex, paddr, pmask, pirq,
memtech, ifg_gap, attempt_limit, backoff_limit, slot_time, mdcscaler,
nsync, edcl, edclbufsz, burstlength, macaddrh, macaddrl, ipaddrh,
ipaddrl, phyrstadr, sim, oepol, scanen)
port map ( rst, clk, ahbmi, ahbmo, apbi, apbo, ethi, etho);
end generate;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity caseT is
port(A : out std_logic;
baz : in std_logic_vector(2 downto 0));
end caseT;
architecture behv of caseT is
begin
process(A) is
begin
case baz is
when "000" => A <= '0';
when "001" => A <= '1';
when "010" => A <= '1';
when "011" => A <= '1';
when "100" => A <= '0';
when "101" => A <= '1';
when "110" => A <= '1';
when "111" => A <= '1';
end case;
end process;
end behv;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity caseT is
port(A : out std_logic;
baz : in std_logic_vector(2 downto 0));
end caseT;
architecture behv of caseT is
begin
process(A) is
begin
case baz is
when "000" => A <= '0';
when "001" => A <= '1';
when "010" => A <= '1';
when "011" => A <= '1';
when "100" => A <= '0';
when "101" => A <= '1';
when "110" => A <= '1';
when "111" => A <= '1';
end case;
end process;
end behv;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1438.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01438ent IS
END c08s07b00x00p02n01i01438ent;
ARCHITECTURE c08s07b00x00p02n01i01438arch OF c08s07b00x00p02n01i01438ent IS
begin
process
variable VAR_1: INTEGER := 3;
begin
if VAR_1 > 2 then
NULL;
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01438 - reserved word 'end if;' is missing"
severity ERROR;
wait;
end process;
END c08s07b00x00p02n01i01438arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1438.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01438ent IS
END c08s07b00x00p02n01i01438ent;
ARCHITECTURE c08s07b00x00p02n01i01438arch OF c08s07b00x00p02n01i01438ent IS
begin
process
variable VAR_1: INTEGER := 3;
begin
if VAR_1 > 2 then
NULL;
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01438 - reserved word 'end if;' is missing"
severity ERROR;
wait;
end process;
END c08s07b00x00p02n01i01438arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1438.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01438ent IS
END c08s07b00x00p02n01i01438ent;
ARCHITECTURE c08s07b00x00p02n01i01438arch OF c08s07b00x00p02n01i01438ent IS
begin
process
variable VAR_1: INTEGER := 3;
begin
if VAR_1 > 2 then
NULL;
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01438 - reserved word 'end if;' is missing"
severity ERROR;
wait;
end process;
END c08s07b00x00p02n01i01438arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:47:10 09/25/2015
-- Design Name:
-- Module Name: MUX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX_4in is
port ( TO_REG : out std_logic_vector(7 downto 0);
FROM_IN : in std_logic_vector(7 downto 0);
FROM_BUS : in std_logic_vector(7 downto 0);
FROM_ALU : in std_logic_vector(7 downto 0);
SEL : in std_logic_vector(1 downto 0));
end MUX_4in;
architecture Behavioral of MUX_4in is
begin
with SEL select
TO_REG <= FROM_ALU when "00",
FROM_BUS when "01",
FROM_IN when "11",
"00000000" when others;
end Behavioral;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pci_sys_pll_125M.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pci_sys_pll_125M IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END pci_sys_pll_125M;
ARCHITECTURE SYN OF pci_sys_pll_125m IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 5,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV GX",
lpm_hint => "CBX_MODULE_PREFIX=pci_sys_pll_125M",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pci_sys_pll_125M.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pci_sys_pll_125M.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pci_sys_pll_125M.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pci_sys_pll_125M.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pci_sys_pll_125M.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pci_sys_pll_125M.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pci_sys_pll_125M_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
----------------------------------------------------------------------------------
-- Module Name: pixel_x4_generator - Behavioral
--
-- Description: A module to generate a group of pixels at a time.
-- Not yet in use in the main project.
--
----------------------------------------------------------------------------------
-- NOTE FOR THIS TO WORK CORRECTLY h_visible_en, h_blank_len, h_front_len & h_sync_len
-- MUST BE DIVISIBLE BY 4!!!!!
------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email (hamster@snap.net.nz)?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pixel_x4_generator is
port (
clk_135 : in std_logic;
pixel_rate_div_10k : in std_logic(15 downto 0); -- 0 to 643.5 MHz rates
h_visible_len : in std_logic(11 downto 0);
h_blank_len : in std_logic(11 downto 0);
h_front_len : in std_logic(11 downto 0);
h_sync_len : in std_logic(11 downto 0);
v_visible_len : in std_logic(11 downto 0);
v_blank_len : in std_logic(11 downto 0);
v_front_len : in std_logic(11 downto 0);
v_sync_len : in std_logic(11 downto 0);
-----------------------------------------------
px_de : out std_logic;
px_blank : out std_logic;
px_vsync : out std_logic;
px_hsync : out std_logic;
p0_Cb : out std_logic(7 downto 0);
p0_Y : out std_logic(7 downto 0);
p1_Cr : out std_logic(7 downto 0);
p1_Y : out std_logic(7 downto 0);
p2_Cb : out std_logic(7 downto 0);
p2_Y : out std_logic(7 downto 0);
p2_blue : out std_logic(7 downto 0);
p2_Cr : out std_logic(7 downto 0);
p2_Y : out std_logic(7 downto 0));
end entity;
architecture arch of pixel_x4_generator is
signal h_count_0 : unsigned(11 downto 0) := (others => '0');
signal h_counter : unsigned(11 downto 0) := (others => '0');
signal v_counter : unsigned(11 downto 0) := (others => '0');
signal v_sync : std_logic := '0';
signal v_blank : std_logic := '0';
signal new_pixels : std_logic := '0';
signal phase_accumulator : unsigned(18 downto 0) := (others => '0');
begin
clk_proc: process(clk_135)
begin
if rising_edge(clk_135) then
h_total <= h_visible_len - h_blank_len;
-------------------------------------
-- Generate new pixels
-------------------------------------
px_de <= '0';
if new_pixels = '1' then
px_de <= '1';
-----------------
-- For all pixels
-----------------
-- Are we in the horizontal sync?
if h_count_0 >= h_front_len and h_count_0 < h_front_len+h_sync_len then
px_hsync <= '1';
else
px_hsync <= '0';
end if;
-- Are we in the horizontal blank?
px_blank <= '0';
if h_count_0 < h_blank_len then
px_blank <= '1';
end if;
-- Are we in the vertical blank?
if v_count_0 < v_blank_len then
px_blank <= '1';
end if;
-- Are we in the vertical sync?
if v_count_0 > v_front_len or v_counter < v_front_len+v_sync_len then
px_vsync <= '1';
else
px_vsync <= '0';
end if;
-------------------
-- Per pixel levels
-------------------
if h_count_0 < h_blank_len then
p0_cb <= x"80";
p1_cb <= x"80";
p2_cb <= x"80";
p3_cb <= x"80";
p0_y <= x"10";
p1_y <= x"10";
p2_y <= x"10";
p3_y <= x"10";
else
p0_cb <= x"80";
p1_cb <= x"80";
p2_cb <= x"80";
p3_cb <= x"80";
p0_y <= std_logic_vector(h_count_0(7 downto 0));
p1_y <= std_logic_vector(h_count_0(7 downto 0));
p2_y <= std_logic_vector(h_count_0(7 downto 0));
p3_y <= std_logic_vector(h_count_0(7 downto 0));
end if;
end if;
---------------------------------------------
-- Advance the counters and trigger the
-- generation of four new pixels
---------------------------------------------
if generate_pixels = '1' then
new_pixels <= '1';
h_count_0 <= h_counter;
v_count_0 <= v_counter;
if h_counter >= h_blank_len+h_visible_len-4 then
h_counter <= (others => '0');
if v_counter = v_blank_len + v_visible_len then
v_counter <= (others => '0');
else
v_counter <= v_counter + 1;
end if;
else
h_counter <= h_counter+4;
end if;
else
new_pixels <= '0';
end if;
--------------------------------------------------
-- Generate a pulse at 1/4th the pixel clock rate
-- but in the clk_135 domain.
--------------------------------------------------
if phase_accumulator < pixel_rate_div_10k then
phase_accumulator <= phase_accumulator + (13500*4) - pixel_rate_div_10k;
generate_pixels <= '1';
else
phase_accumulator <= phase_accumulator - pixel_rate_div_10k;
generate_pixels <= '0';
end if;
end if;
end process;
end architecture; |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp_s5
-- VHDL created on Tue Mar 12 11:36:13 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.hcc_package_cmd.all;
use work.math_package_cmd.all;
use work.fpc_library_package_cmd.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal fpExpTest_reset : std_logic;
signal fpExpTest_q : std_logic_vector (31 downto 0);
-- synopsys translate off
signal fpExpTest_q_real : REAL;
-- synopsys translate on
begin
--GND(CONSTANT,0)
--VCC(CONSTANT,1)
--xIn(GPIN,3)@0
--fpExpTest(FLOATEXP,2)@0
fpExpTest_reset <= areset;
fpExpTest_inst : fp_exp_sIEEE_2_sIEEE
PORT MAP (
clk_en => '1',
clock => clk,
reset => fpExpTest_reset,
dataa => a,
result => fpExpTest_q
);
-- synopsys translate off
fpExpTest_q_real <= sIEEE_2_real(fpExpTest_q);
-- synopsys translate on
--xOut(GPOUT,4)@16
q <= fpExpTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp_s5
-- VHDL created on Tue Mar 12 11:36:13 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.hcc_package_cmd.all;
use work.math_package_cmd.all;
use work.fpc_library_package_cmd.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal fpExpTest_reset : std_logic;
signal fpExpTest_q : std_logic_vector (31 downto 0);
-- synopsys translate off
signal fpExpTest_q_real : REAL;
-- synopsys translate on
begin
--GND(CONSTANT,0)
--VCC(CONSTANT,1)
--xIn(GPIN,3)@0
--fpExpTest(FLOATEXP,2)@0
fpExpTest_reset <= areset;
fpExpTest_inst : fp_exp_sIEEE_2_sIEEE
PORT MAP (
clk_en => '1',
clock => clk,
reset => fpExpTest_reset,
dataa => a,
result => fpExpTest_q
);
-- synopsys translate off
fpExpTest_q_real <= sIEEE_2_real(fpExpTest_q);
-- synopsys translate on
--xOut(GPOUT,4)@16
q <= fpExpTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp_s5
-- VHDL created on Tue Mar 12 11:36:13 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.hcc_package_cmd.all;
use work.math_package_cmd.all;
use work.fpc_library_package_cmd.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal fpExpTest_reset : std_logic;
signal fpExpTest_q : std_logic_vector (31 downto 0);
-- synopsys translate off
signal fpExpTest_q_real : REAL;
-- synopsys translate on
begin
--GND(CONSTANT,0)
--VCC(CONSTANT,1)
--xIn(GPIN,3)@0
--fpExpTest(FLOATEXP,2)@0
fpExpTest_reset <= areset;
fpExpTest_inst : fp_exp_sIEEE_2_sIEEE
PORT MAP (
clk_en => '1',
clock => clk,
reset => fpExpTest_reset,
dataa => a,
result => fpExpTest_q
);
-- synopsys translate off
fpExpTest_q_real <= sIEEE_2_real(fpExpTest_q);
-- synopsys translate on
--xOut(GPOUT,4)@16
q <= fpExpTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp_s5
-- VHDL created on Tue Mar 12 11:36:13 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.hcc_package_cmd.all;
use work.math_package_cmd.all;
use work.fpc_library_package_cmd.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal fpExpTest_reset : std_logic;
signal fpExpTest_q : std_logic_vector (31 downto 0);
-- synopsys translate off
signal fpExpTest_q_real : REAL;
-- synopsys translate on
begin
--GND(CONSTANT,0)
--VCC(CONSTANT,1)
--xIn(GPIN,3)@0
--fpExpTest(FLOATEXP,2)@0
fpExpTest_reset <= areset;
fpExpTest_inst : fp_exp_sIEEE_2_sIEEE
PORT MAP (
clk_en => '1',
clock => clk,
reset => fpExpTest_reset,
dataa => a,
result => fpExpTest_q
);
-- synopsys translate off
fpExpTest_q_real <= sIEEE_2_real(fpExpTest_q);
-- synopsys translate on
--xOut(GPOUT,4)@16
q <= fpExpTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp_s5
-- VHDL created on Tue Mar 12 11:36:13 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.hcc_package_cmd.all;
use work.math_package_cmd.all;
use work.fpc_library_package_cmd.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal fpExpTest_reset : std_logic;
signal fpExpTest_q : std_logic_vector (31 downto 0);
-- synopsys translate off
signal fpExpTest_q_real : REAL;
-- synopsys translate on
begin
--GND(CONSTANT,0)
--VCC(CONSTANT,1)
--xIn(GPIN,3)@0
--fpExpTest(FLOATEXP,2)@0
fpExpTest_reset <= areset;
fpExpTest_inst : fp_exp_sIEEE_2_sIEEE
PORT MAP (
clk_en => '1',
clock => clk,
reset => fpExpTest_reset,
dataa => a,
result => fpExpTest_q
);
-- synopsys translate off
fpExpTest_q_real <= sIEEE_2_real(fpExpTest_q);
-- synopsys translate on
--xOut(GPOUT,4)@16
q <= fpExpTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp_s5
-- VHDL created on Tue Mar 12 11:36:13 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.hcc_package_cmd.all;
use work.math_package_cmd.all;
use work.fpc_library_package_cmd.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal fpExpTest_reset : std_logic;
signal fpExpTest_q : std_logic_vector (31 downto 0);
-- synopsys translate off
signal fpExpTest_q_real : REAL;
-- synopsys translate on
begin
--GND(CONSTANT,0)
--VCC(CONSTANT,1)
--xIn(GPIN,3)@0
--fpExpTest(FLOATEXP,2)@0
fpExpTest_reset <= areset;
fpExpTest_inst : fp_exp_sIEEE_2_sIEEE
PORT MAP (
clk_en => '1',
clock => clk,
reset => fpExpTest_reset,
dataa => a,
result => fpExpTest_q
);
-- synopsys translate off
fpExpTest_q_real <= sIEEE_2_real(fpExpTest_q);
-- synopsys translate on
--xOut(GPOUT,4)@16
q <= fpExpTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp_s5
-- VHDL created on Tue Mar 12 11:36:13 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.hcc_package_cmd.all;
use work.math_package_cmd.all;
use work.fpc_library_package_cmd.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal fpExpTest_reset : std_logic;
signal fpExpTest_q : std_logic_vector (31 downto 0);
-- synopsys translate off
signal fpExpTest_q_real : REAL;
-- synopsys translate on
begin
--GND(CONSTANT,0)
--VCC(CONSTANT,1)
--xIn(GPIN,3)@0
--fpExpTest(FLOATEXP,2)@0
fpExpTest_reset <= areset;
fpExpTest_inst : fp_exp_sIEEE_2_sIEEE
PORT MAP (
clk_en => '1',
clock => clk,
reset => fpExpTest_reset,
dataa => a,
result => fpExpTest_q
);
-- synopsys translate off
fpExpTest_q_real <= sIEEE_2_real(fpExpTest_q);
-- synopsys translate on
--xOut(GPOUT,4)@16
q <= fpExpTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp_s5
-- VHDL created on Tue Mar 12 11:36:13 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.hcc_package_cmd.all;
use work.math_package_cmd.all;
use work.fpc_library_package_cmd.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal fpExpTest_reset : std_logic;
signal fpExpTest_q : std_logic_vector (31 downto 0);
-- synopsys translate off
signal fpExpTest_q_real : REAL;
-- synopsys translate on
begin
--GND(CONSTANT,0)
--VCC(CONSTANT,1)
--xIn(GPIN,3)@0
--fpExpTest(FLOATEXP,2)@0
fpExpTest_reset <= areset;
fpExpTest_inst : fp_exp_sIEEE_2_sIEEE
PORT MAP (
clk_en => '1',
clock => clk,
reset => fpExpTest_reset,
dataa => a,
result => fpExpTest_q
);
-- synopsys translate off
fpExpTest_q_real <= sIEEE_2_real(fpExpTest_q);
-- synopsys translate on
--xOut(GPOUT,4)@16
q <= fpExpTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp_s5
-- VHDL created on Tue Mar 12 11:36:13 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.hcc_package_cmd.all;
use work.math_package_cmd.all;
use work.fpc_library_package_cmd.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal fpExpTest_reset : std_logic;
signal fpExpTest_q : std_logic_vector (31 downto 0);
-- synopsys translate off
signal fpExpTest_q_real : REAL;
-- synopsys translate on
begin
--GND(CONSTANT,0)
--VCC(CONSTANT,1)
--xIn(GPIN,3)@0
--fpExpTest(FLOATEXP,2)@0
fpExpTest_reset <= areset;
fpExpTest_inst : fp_exp_sIEEE_2_sIEEE
PORT MAP (
clk_en => '1',
clock => clk,
reset => fpExpTest_reset,
dataa => a,
result => fpExpTest_q
);
-- synopsys translate off
fpExpTest_q_real <= sIEEE_2_real(fpExpTest_q);
-- synopsys translate on
--xOut(GPOUT,4)@16
q <= fpExpTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp_s5
-- VHDL created on Tue Mar 12 11:36:13 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.hcc_package_cmd.all;
use work.math_package_cmd.all;
use work.fpc_library_package_cmd.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal fpExpTest_reset : std_logic;
signal fpExpTest_q : std_logic_vector (31 downto 0);
-- synopsys translate off
signal fpExpTest_q_real : REAL;
-- synopsys translate on
begin
--GND(CONSTANT,0)
--VCC(CONSTANT,1)
--xIn(GPIN,3)@0
--fpExpTest(FLOATEXP,2)@0
fpExpTest_reset <= areset;
fpExpTest_inst : fp_exp_sIEEE_2_sIEEE
PORT MAP (
clk_en => '1',
clock => clk,
reset => fpExpTest_reset,
dataa => a,
result => fpExpTest_q
);
-- synopsys translate off
fpExpTest_q_real <= sIEEE_2_real(fpExpTest_q);
-- synopsys translate on
--xOut(GPOUT,4)@16
q <= fpExpTest_q;
end normal;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_reg.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity reg is
port ( clk : in std_ulogic;
d : in std_ulogic_vector;
q : out std_ulogic_vector );
end entity reg;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_reg.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity reg is
port ( clk : in std_ulogic;
d : in std_ulogic_vector;
q : out std_ulogic_vector );
end entity reg;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_reg.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity reg is
port ( clk : in std_ulogic;
d : in std_ulogic_vector;
q : out std_ulogic_vector );
end entity reg;
|
--
-- Controller.vhd
-- The core controller module of VM2413
--
-- Copyright (c) 2006 Mitsutaka Okazaki (brezza@pokipoki.org)
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
-- [Description]
--
-- The Controller is the beginning module of the OPLL slot calculation.
-- It manages register accesses from I/O and sends proper voice parameters
-- to the succeding PhaseGenerator and EnvelopeGenerator modules.
-- The one cycle of the Controller consists of 4 stages as follows.
--
-- 1st stage:
-- * Prepare to read the register value for the current slot from RegisterMemory.
-- * Prepare to read the voice parameter for the current slot from VoiceMemory.
-- * Prepare to read the user-voice data from VoiceMemory.
--
-- 2nd stage:
-- * Wait for RegisterMemory and VoiceMemory
--
-- 3rd clock stage:
-- * Update register value if wr='1' and addr points the current OPLL channel.
-- * Update voice parameter if wr='1' and addr points the voice parameter area.
-- * Write register value to RegisterMemory.
-- * Write voice parameter to VoiceMemory.
--
-- 4th stage:
-- * Send voice and register parameters to PhaseGenerator and EnvelopeGenerator.
-- * Increment the number of the current slot.
--
-- Each stage is completed in one clock. Thus the Controller traverses all 18 opll
-- slots in 72 clocks.
--
--
-- modified by t.hara
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.vm2413.all;
entity controller is port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in std_logic_vector( 4 downto 0 );
stage : in std_logic_vector( 1 downto 0 );
wr : in std_logic;
addr : in std_logic_vector( 7 downto 0 );
data : in std_logic_vector( 7 downto 0 );
-- output parameters for phasegenerator and envelopegenerator
am : out std_logic;
pm : out std_logic;
wf : out std_logic;
ml : out std_logic_vector(3 downto 0);
tl : out std_logic_vector(6 downto 0);
fb : out std_logic_vector(2 downto 0);
ar : out std_logic_vector(3 downto 0);
dr : out std_logic_vector(3 downto 0);
sl : out std_logic_vector(3 downto 0);
rr : out std_logic_vector(3 downto 0);
blk : out std_logic_vector(2 downto 0);
fnum : out std_logic_vector(8 downto 0);
rks : out std_logic_vector(3 downto 0);
key : out std_logic;
rhythm : out std_logic
-- slot_out : out slot_id
);
end controller;
architecture rtl of controller is
-- the array which caches instrument number of each channel.
type inst_array is array ( 0 to 9-1) of integer range 0 to 15;
signal inst_cache : inst_array;
attribute ram_style : string;
attribute ram_style of inst_cache : signal is "block";
type kl_array is array (0 to 15) of std_logic_vector(5 downto 0);
constant kl_table : kl_array := (
"000000", "011000", "100000", "100101",
"101000", "101011", "101101", "101111",
"110000", "110010", "110011", "110100",
"110101", "110110", "110111", "111000"
); -- 0.75db/step, 6db/oct
-- signals for the read-only access ports of voicememory module.
signal slot_voice_addr : integer range 0 to 37;
signal slot_voice_data : voice_type;
-- signals for the read-write access ports of voicememory module.
signal user_voice_wr : std_logic;
signal user_voice_addr : integer range 0 to 37;
signal user_voice_rdata : voice_type;
signal user_voice_wdata : voice_type;
-- signals for the registermemory module.
signal regs_wr : std_logic;
signal regs_addr : std_logic_vector( 3 downto 0 );
signal regs_rdata : std_logic_vector( 23 downto 0 );
signal regs_wdata : std_logic_vector( 23 downto 0 );
signal rflag : std_logic_vector( 7 downto 0 );
signal w_channel : std_logic_vector( 3 downto 0 );
-- signal w_is_carrier : std_logic;
begin -- rtl
-- ���W�X�^�ݒ��l���ێ����邽�߂̃�����
u_register_memory : entity work.RegisterMemory
port map (
clk => clk,
reset => reset,
addr => regs_addr,
wr => regs_wr,
idata => regs_wdata,
odata => regs_rdata
);
vmem : entity work.VoiceMemory
port map (
clk, reset, user_voice_wdata, user_voice_wr, user_voice_addr, slot_voice_addr,
user_voice_rdata, slot_voice_data );
-- ���W�X�^�A�h���X���b�` (���P�X�e�[�W)
process( reset, clk )
begin
if( reset = '1' )then
regs_addr <= (others => '0');
elsif( clk'event and clk = '1' )then
if clkena='1' then
if( stage = "00" )then
regs_addr <= slot( 4 downto 1 );
else
-- hold
end if;
end if;
end if;
end process;
-- ���݂̃X���b�g�̉��F�f�[�^�ǂݏo���A�h���X���b�` (���P�X�e�[�W)
process( reset, clk )
begin
if( reset = '1' )then
slot_voice_addr <= 0;
elsif( clk'event and clk = '1' )then
if clkena='1' then
if( stage = "00" )then
if( rflag(5) = '1' and w_channel >= "0110" )then
-- ���Y�����[�h�� ch6 �ȍ~
slot_voice_addr <= conv_integer(slot) - 12 + 32;
else
slot_voice_addr <= inst_cache(conv_integer(slot)/2) * 2 + conv_integer(slot) mod 2;
end if;
else
-- hold
end if;
end if;
end if;
end process;
w_channel <= slot( 4 downto 1 );
-- w_is_carrier <= slot( 0 );
process (clk, reset)
variable kflag : std_logic;
variable tll : std_logic_vector(7 downto 0);
variable kll : std_logic_vector(7 downto 0);
variable regs_tmp : std_logic_vector(23 downto 0);
variable user_voice_tmp : voice_type;
variable fb_buf : std_logic_vector(2 downto 0);
variable wf_buf : std_logic;
variable extra_mode : std_logic;
variable vindex : integer range 0 to 37;
begin -- process
if(reset = '1') then
key <= '0';
rhythm <= '0';
tll := (others=>'0');
kll := (others=>'0');
kflag := '0';
rflag <= (others=>'0');
user_voice_wr <= '0';
user_voice_addr <= 0;
regs_wr <='0';
ar <= (others=>'0');
dr <= (others=>'0');
sl <= (others=>'0');
rr <= (others=>'0');
tl <= (others=>'0');
fb <= (others=>'0');
wf <= '0';
ml <= (others=>'0');
fnum <= (others=>'0');
blk <= (others=>'0');
key <= '0';
rks <= (others=>'0');
rhythm <= '0';
extra_mode := '0';
vindex := 0;
elsif clk'event and clk='1' then
if clkena='1' then
case stage is
--------------------------------------------------------------------------
-- 1st stage (setting up a read request for register and voice memories.)
--------------------------------------------------------------------------
when "00" =>
-- if extra_mode = '0' then
-- alternately read modulator or carrior.
vindex := conv_integer(slot) mod 2;
-- else
-- if vindex = 37 then
-- vindex:= 0;
-- else
-- vindex:= vindex + 1;
-- end if;
-- end if;
user_voice_addr <= vindex;
regs_wr <= '0';
user_voice_wr <='0';
--------------------------------------------------------------------------
-- 2nd stage (just a wait for register and voice memories.)
--------------------------------------------------------------------------
when "01" =>
null;
--------------------------------------------------------------------------
-- 3rd stage (updating a register and voice parameters.)
--------------------------------------------------------------------------
when "10" =>
if wr='1' then
-- if ( extra_mode = '0' and conv_integer(addr) < 8 ) or
-- ( extra_mode = '1' and ( conv_integer(addr) - 64 ) / 8 = vindex / 2 ) then
if( extra_mode = '0' and conv_integer(addr) < 8 )then
-- update user voice parameter.
user_voice_tmp := user_voice_rdata;
case addr(2 downto 1) is
when "00" =>
if conv_integer(addr(0 downto 0)) = (vindex mod 2) then
user_voice_tmp.am := data(7);
user_voice_tmp.pm := data(6);
user_voice_tmp.eg := data(5);
user_voice_tmp.kr := data(4);
user_voice_tmp.ml := data(3 downto 0);
user_voice_wr <= '1';
end if;
when "01" =>
if addr(0)='0' and (vindex mod 2 = 0) then
user_voice_tmp.kl := data(7 downto 6);
user_voice_tmp.tl := data(5 downto 0);
user_voice_wr <= '1';
elsif addr(0)='1' and (vindex mod 2 = 0) then
user_voice_tmp.wf := data(3);
user_voice_tmp.fb := data(2 downto 0);
user_voice_wr <= '1';
elsif addr(0)='1' and (vindex mod 2 = 1) then
user_voice_tmp.kl := data(7 downto 6);
user_voice_tmp.wf := data(4);
user_voice_wr <= '1';
end if;
when "10" =>
if conv_integer(addr(0 downto 0)) = (vindex mod 2) then
user_voice_tmp.ar := data(7 downto 4);
user_voice_tmp.dr := data(3 downto 0);
user_voice_wr <= '1';
end if;
when "11" =>
if conv_integer(addr(0 downto 0)) = (vindex mod 2) then
user_voice_tmp.sl := data(7 downto 4);
user_voice_tmp.rr := data(3 downto 0);
user_voice_wr <= '1';
end if;
when others =>
null;
end case;
user_voice_wdata <= user_voice_tmp;
elsif conv_integer(addr) = 14 then
rflag <= data;
elsif conv_integer(addr) < 16 then
null;
elsif conv_integer(addr) <= 63 then
if( conv_integer(addr(3 downto 0) ) = conv_integer(slot) / 2 ) then
regs_tmp := regs_rdata;
case addr( 5 downto 4 ) is
when "01" => -- 10h�`18h �̏ꍇ�i���� F-Number�j
regs_tmp(7 downto 0) := data; -- F-Number
regs_wr <= '1';
when "10" => -- 20h�`28h �̏ꍇ�iSus, Key, Block, F-Number MSB�j
regs_tmp(13) := data(5); -- Sus
regs_tmp(12) := data(4); -- Key
regs_tmp(11 downto 9) := data(3 downto 1); -- Block
regs_tmp(8) := data(0); -- F-Number
regs_wr <= '1';
when "11" => -- 30h�`38h �̏ꍇ�iInst, Vol�j
regs_tmp(23 downto 20) := data(7 downto 4); -- Inst
regs_tmp(19 downto 16) := data(3 downto 0); -- Vol
regs_wr <='1';
when others =>
null;
end case;
regs_wdata <= regs_tmp;
end if;
elsif conv_integer(addr) = 240 then
if data(7 downto 0) = "10000000" then
extra_mode := '1';
else
extra_mode := '0';
end if;
end if;
end if;
--------------------------------------------------------------------------
-- 4th stage (updating a register and voice parameters.)
--------------------------------------------------------------------------
when "11" =>
-- output slot number (for explicit synchonization with other units).
-- slot_out <= slot;
-- updating insturument cache
inst_cache(conv_integer(slot)/2) <= conv_integer(regs_rdata(23 downto 20));
rhythm <= rflag(5);
-- updating rhythm status and key flag
if rflag(5) = '1' and 12 <= slot then
case slot is
when "01100" | "01101" => -- bd
kflag := rflag(4);
when "01110" => -- hh
kflag := rflag(0);
when "01111" => -- sd
kflag := rflag(3);
when "10000" => -- tom
kflag := rflag(2);
when "10001" => -- cym
kflag := rflag(1);
when others => null;
end case;
else
kflag := '0';
end if;
kflag := kflag or regs_rdata(12);
-- calculate key-scale attenuation amount.
kll := (("0"&kl_table(conv_integer(regs_rdata(8 downto 5))))
- ("0"&("111"-regs_rdata(11 downto 9))&"000")) & '0';
if kll(kll'high) ='1' or slot_voice_data.kl = "00" then
kll := (others=>'0');
else
kll := shr(kll, "11" - slot_voice_data.kl );
end if;
-- calculate base total level from volume register value.
if rflag(5) = '1' and (slot = "01110" or slot = "10000") then -- hh and cym
tll := ('0' & regs_rdata(23 downto 20) & "000");
elsif( slot(0) = '0' )then
tll := ('0' & slot_voice_data.tl & '0'); -- mod
else
tll := ('0' & regs_rdata(19 downto 16) & "000"); -- car
end if;
tll := tll + kll;
if tll(tll'high) ='1' then
tl <= (others=>'1');
else
tl <= tll(tl'range);
end if;
-- output rks, f-number, block and key-status.
fnum <= regs_rdata(8 downto 0);
blk <= regs_rdata(11 downto 9);
key <= kflag;
if rflag(5) = '1' and 14 <= slot then
if slot_voice_data.kr = '1' then
rks <= "0101";
else
rks <= "00" & regs_rdata(11 downto 10);
end if;
else
if slot_voice_data.kr = '1' then
rks <= regs_rdata(11 downto 9) & regs_rdata(8);
else
rks <= "00" & regs_rdata(11 downto 10);
end if;
end if;
-- output voice parameters
-- note that wf and fb output must keep its value
-- at least 3 clocks since the operator module will fetch
-- the wf and fb 2 clocks later of this stage.
am <= slot_voice_data.am;
pm <= slot_voice_data.pm;
ml <= slot_voice_data.ml;
wf_buf := slot_voice_data.wf;
fb_buf := slot_voice_data.fb;
wf <= wf_buf;
fb <= fb_buf;
ar <= slot_voice_data.ar;
dr <= slot_voice_data.dr;
sl <= slot_voice_data.sl;
-- output release rate (depends on the sustine and envelope type).
if( kflag = '1' ) then -- key on
if slot_voice_data.eg = '1' then
rr <= "0000";
else
rr <= slot_voice_data.rr;
end if;
else -- key off
if (slot(0) = '0') and not ( rflag(5) = '1' and (7 <= conv_integer(slot)/2) ) then
rr <= "0000";
elsif regs_rdata(13) = '1' then
rr <= "0101";
elsif slot_voice_data.eg = '0' then
rr <= "0111";
else
rr <= slot_voice_data.rr;
end if;
end if;
when others =>
null;
end case;
end if; end if;
end process;
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MuxPC is
Port ( PCdisp30 : in STD_LOGIC_VECTOR(31 downto 0);
PCdisp22 : in STD_LOGIC_VECTOR(31 downto 0);
PC : in STD_LOGIC_VECTOR(31 downto 0);
PCplus1 : in STD_LOGIC_VECTOR(31 downto 0);
PCSource: in STD_LOGIC_VECTOR(1 downto 0);
nPC : out STD_LOGIC_VECTOR(31 downto 0)
);
end MuxPC;
architecture Behavioral of MuxPC is
begin
process(PCdisp30,PCdisp22,PC,PCSource)
begin
if (PCSource="10") then
nPC <= PCdisp22;
elsif (PCsource="01") then
nPC <= PCdisp30;
elsif (PCSource="00") then
nPC <= PC;
else
nPC <= PCplus1;
end if;
end process;
end Behavioral;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY SimpleIfStatementPartialOverride IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SimpleIfStatementPartialOverride IS
BEGIN
assig_process_c: PROCESS(a, b)
BEGIN
IF b = '1' THEN
c <= '1';
IF a = '1' THEN
c <= b;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D13_C2 is
port(
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D13_C2;
architecture D13_C2 of D13_C2 is
begin
process(clk)
variable dem:integer range 0 to 4;
begin
if (rising_edge(clk)) then
if (dem=4) then dem:=0;
else dem:=dem+1;
end if;
end if;
case dem is
when 0=> seg <="00000000";
when 1=> seg <="00011000";
when 2=> seg <="00111100";
when 3=> seg <="01111110";
when 4=> seg <="11111111";
when others=> seg <="XXXXXXXX";
end case;
end process;
end D13_C2;
-- clk=5Mhz; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arpv2 - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP lookup in 1-deep cache and arp store
-- request cache fill through ARP protocol if required
-- Handle ARP protocol
-- Respond to ARP requests and replies
-- Ignore pkts that are not ARP
-- Ignore pkts that are not addressed to us
--
-- structural decomposition includes
-- arp TX block - encoding of ARP protocol
-- arp RX block - decoding of ARP protocol
-- arp REQ block - sequencing requests for resolution
-- arp STORE block - storing address resolution entries (indexed by IP addr)
-- arp sync block - sync between master RX clock and TX clock domains
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arpv2 is
generic (
no_default_gateway : boolean := true; -- set to false if communicating with devices accessed
-- though a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the arp store
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
nwk_gateway : in std_logic_vector (31 downto 0) := (others => '0'); -- IP address of default gateway
nwk_mask : in std_logic_vector (31 downto 0) := (others => '0'); -- Net mask
control : in arp_control_type;
req_count : out std_logic_vector(7 downto 0) -- count of arp pkts received
);
end arpv2;
architecture structural of arpv2 is
component arp_req
generic (
no_default_gateway : boolean := true;
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5 -- # wrong nwk pkts received before set error
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type; -- request for a translation from IP to MAC
arp_req_rslt : out arp_req_rslt_type; -- the result
-- external arp store signals
arp_store_req : out arp_store_rdrequest_t; -- requesting a lookup or store
arp_store_result : in arp_store_result_t; -- the result
-- network request signals
arp_nwk_req : out arp_nwk_request_t; -- requesting resolution via the network
arp_nwk_result : in arp_nwk_result_t; -- the result
-- system signals
clear_cache : in std_logic; -- clear the internal cache
nwk_gateway : in std_logic_vector(31 downto 0); -- IP address of default gateway
nwk_mask : in std_logic_vector(31 downto 0); -- Net mask
clk : in std_logic;
reset : in std_logic
);
end component;
component arp_tx
port(
-- control signals
send_I_have : in std_logic; -- pulse will be latched
arp_entry : in arp_entry_t; -- arp target for I_have req (will be latched)
send_who_has : in std_logic; -- pulse will be latched
ip_entry : in std_logic_vector (31 downto 0); -- ip target for who_has req (will be latched)
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
tx_clk : in std_logic;
reset : in std_logic
);
end component;
component arp_rx
port(
-- MAC layer RX signals
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- ARP output signals
recv_who_has : out std_logic; -- pulse will be latched
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to)
recv_I_have : out std_logic; -- pulse will be latched
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg
-- control and status signals
req_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
-- system signals
our_ip_address : in std_logic_vector (31 downto 0);
rx_clk : in std_logic;
reset : in std_logic
);
end component;
component arp_store_br
generic (
MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
);
port (
-- read signals
read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
read_result : out arp_store_result_t; -- the result
-- write signals
write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
-- control and status signals
clear_store : in std_logic; -- erase all entries
entry_count : out unsigned(7 downto 0); -- how many entries currently in store
-- system signals
clk : in std_logic;
reset : in std_logic
);
end component;
component arp_sync
port (
-- REQ to TX
arp_nwk_req : in arp_nwk_request_t; -- request for a translation from IP to MAC
send_who_has : out std_logic;
ip_entry : out std_logic_vector (31 downto 0);
-- RX to TX
recv_who_has : in std_logic; -- this is for us, we will respond
arp_entry_for_who_has : in arp_entry_t;
send_I_have : out std_logic;
arp_entry : out arp_entry_t;
-- RX to REQ
I_have_received : in std_logic;
nwk_result_status : out arp_nwk_rslt_t;
-- System Signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic
);
end component;
-- interconnect REQ -> ARP_TX
signal arp_nwk_req_int : arp_nwk_request_t; -- tx req from REQ
signal send_I_have_int : std_logic;
signal arp_entry_int : arp_entry_t;
signal send_who_has_int : std_logic;
signal ip_entry_int : std_logic_vector (31 downto 0);
-- interconnect REQ <-> ARP_STORE
signal arp_store_req_int : arp_store_rdrequest_t; -- lookup request
signal arp_store_result_int : arp_store_result_t; -- lookup result
-- interconnect ARP_RX -> REQ
signal nwk_result_status_int : arp_nwk_rslt_t; -- response from a TX req
-- interconnect ARP_RX -> ARP_STORE
signal recv_I_have_int : std_logic; -- path to store new arp entry
signal arp_entry_for_I_have_int : arp_entry_t;
-- interconnect ARP_RX -> ARP_TX
signal recv_who_has_int : std_logic; -- path for reply when we can anser
signal arp_entry_for_who_has_int : arp_entry_t; -- target for who_has msg (ie, who to reply to)
begin
req : arp_req
generic map (
no_default_gateway => no_default_gateway,
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO
)
port map (
-- lookup request signals
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
-- external arp store signals
arp_store_req => arp_store_req_int,
arp_store_result => arp_store_result_int,
-- network request signals
arp_nwk_req => arp_nwk_req_int,
arp_nwk_result.status => nwk_result_status_int,
arp_nwk_result.entry => arp_entry_for_I_have_int,
-- system signals
clear_cache => control.clear_cache,
nwk_gateway => nwk_gateway,
nwk_mask => nwk_mask,
clk => data_in_clk,
reset => reset
);
sync : arp_sync port map (
-- REQ to TX
arp_nwk_req => arp_nwk_req_int,
send_who_has => send_who_has_int,
ip_entry => ip_entry_int,
-- RX to TX
recv_who_has => recv_who_has_int,
arp_entry_for_who_has => arp_entry_for_who_has_int,
send_I_have => send_I_have_int,
arp_entry => arp_entry_int,
-- RX to REQ
I_have_received => recv_I_have_int,
nwk_result_status => nwk_result_status_int,
-- system
rx_clk => data_in_clk,
tx_clk => data_out_clk,
reset => reset
);
tx : arp_tx port map (
-- control signals
send_I_have => send_I_have_int,
arp_entry => arp_entry_int,
send_who_has => send_who_has_int,
ip_entry => ip_entry_int,
-- MAC layer TX signals
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
data_out_ready => data_out_ready,
data_out_valid => data_out_valid,
data_out_first => data_out_first,
data_out_last => data_out_last,
data_out => data_out,
-- system signals
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
tx_clk => data_out_clk,
reset => reset
);
rx : arp_rx port map (
-- MAC layer RX signals
data_in => data_in,
data_in_valid => data_in_valid,
data_in_last => data_in_last,
-- ARP output signals
recv_who_has => recv_who_has_int,
arp_entry_for_who_has => arp_entry_for_who_has_int,
recv_I_have => recv_I_have_int,
arp_entry_for_I_have => arp_entry_for_I_have_int,
-- control and status signals
req_count => req_count,
-- system signals
our_ip_address => our_ip_address,
rx_clk => data_in_clk,
reset => reset
);
store : arp_store_br
generic map (
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map (
-- read signals
read_req => arp_store_req_int,
read_result => arp_store_result_int,
-- write signals
write_req.req => recv_I_have_int,
write_req.entry => arp_entry_for_I_have_int,
-- control and status signals
clear_store => control.clear_cache,
entry_count => open,
-- system signals
clk => data_in_clk,
reset => reset
);
end structural;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arpv2 - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP lookup in 1-deep cache and arp store
-- request cache fill through ARP protocol if required
-- Handle ARP protocol
-- Respond to ARP requests and replies
-- Ignore pkts that are not ARP
-- Ignore pkts that are not addressed to us
--
-- structural decomposition includes
-- arp TX block - encoding of ARP protocol
-- arp RX block - decoding of ARP protocol
-- arp REQ block - sequencing requests for resolution
-- arp STORE block - storing address resolution entries (indexed by IP addr)
-- arp sync block - sync between master RX clock and TX clock domains
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arpv2 is
generic (
no_default_gateway : boolean := true; -- set to false if communicating with devices accessed
-- though a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the arp store
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
nwk_gateway : in std_logic_vector (31 downto 0) := (others => '0'); -- IP address of default gateway
nwk_mask : in std_logic_vector (31 downto 0) := (others => '0'); -- Net mask
control : in arp_control_type;
req_count : out std_logic_vector(7 downto 0) -- count of arp pkts received
);
end arpv2;
architecture structural of arpv2 is
component arp_req
generic (
no_default_gateway : boolean := true;
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5 -- # wrong nwk pkts received before set error
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type; -- request for a translation from IP to MAC
arp_req_rslt : out arp_req_rslt_type; -- the result
-- external arp store signals
arp_store_req : out arp_store_rdrequest_t; -- requesting a lookup or store
arp_store_result : in arp_store_result_t; -- the result
-- network request signals
arp_nwk_req : out arp_nwk_request_t; -- requesting resolution via the network
arp_nwk_result : in arp_nwk_result_t; -- the result
-- system signals
clear_cache : in std_logic; -- clear the internal cache
nwk_gateway : in std_logic_vector(31 downto 0); -- IP address of default gateway
nwk_mask : in std_logic_vector(31 downto 0); -- Net mask
clk : in std_logic;
reset : in std_logic
);
end component;
component arp_tx
port(
-- control signals
send_I_have : in std_logic; -- pulse will be latched
arp_entry : in arp_entry_t; -- arp target for I_have req (will be latched)
send_who_has : in std_logic; -- pulse will be latched
ip_entry : in std_logic_vector (31 downto 0); -- ip target for who_has req (will be latched)
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
tx_clk : in std_logic;
reset : in std_logic
);
end component;
component arp_rx
port(
-- MAC layer RX signals
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- ARP output signals
recv_who_has : out std_logic; -- pulse will be latched
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to)
recv_I_have : out std_logic; -- pulse will be latched
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg
-- control and status signals
req_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
-- system signals
our_ip_address : in std_logic_vector (31 downto 0);
rx_clk : in std_logic;
reset : in std_logic
);
end component;
component arp_store_br
generic (
MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
);
port (
-- read signals
read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
read_result : out arp_store_result_t; -- the result
-- write signals
write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
-- control and status signals
clear_store : in std_logic; -- erase all entries
entry_count : out unsigned(7 downto 0); -- how many entries currently in store
-- system signals
clk : in std_logic;
reset : in std_logic
);
end component;
component arp_sync
port (
-- REQ to TX
arp_nwk_req : in arp_nwk_request_t; -- request for a translation from IP to MAC
send_who_has : out std_logic;
ip_entry : out std_logic_vector (31 downto 0);
-- RX to TX
recv_who_has : in std_logic; -- this is for us, we will respond
arp_entry_for_who_has : in arp_entry_t;
send_I_have : out std_logic;
arp_entry : out arp_entry_t;
-- RX to REQ
I_have_received : in std_logic;
nwk_result_status : out arp_nwk_rslt_t;
-- System Signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic
);
end component;
-- interconnect REQ -> ARP_TX
signal arp_nwk_req_int : arp_nwk_request_t; -- tx req from REQ
signal send_I_have_int : std_logic;
signal arp_entry_int : arp_entry_t;
signal send_who_has_int : std_logic;
signal ip_entry_int : std_logic_vector (31 downto 0);
-- interconnect REQ <-> ARP_STORE
signal arp_store_req_int : arp_store_rdrequest_t; -- lookup request
signal arp_store_result_int : arp_store_result_t; -- lookup result
-- interconnect ARP_RX -> REQ
signal nwk_result_status_int : arp_nwk_rslt_t; -- response from a TX req
-- interconnect ARP_RX -> ARP_STORE
signal recv_I_have_int : std_logic; -- path to store new arp entry
signal arp_entry_for_I_have_int : arp_entry_t;
-- interconnect ARP_RX -> ARP_TX
signal recv_who_has_int : std_logic; -- path for reply when we can anser
signal arp_entry_for_who_has_int : arp_entry_t; -- target for who_has msg (ie, who to reply to)
begin
req : arp_req
generic map (
no_default_gateway => no_default_gateway,
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO
)
port map (
-- lookup request signals
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
-- external arp store signals
arp_store_req => arp_store_req_int,
arp_store_result => arp_store_result_int,
-- network request signals
arp_nwk_req => arp_nwk_req_int,
arp_nwk_result.status => nwk_result_status_int,
arp_nwk_result.entry => arp_entry_for_I_have_int,
-- system signals
clear_cache => control.clear_cache,
nwk_gateway => nwk_gateway,
nwk_mask => nwk_mask,
clk => data_in_clk,
reset => reset
);
sync : arp_sync port map (
-- REQ to TX
arp_nwk_req => arp_nwk_req_int,
send_who_has => send_who_has_int,
ip_entry => ip_entry_int,
-- RX to TX
recv_who_has => recv_who_has_int,
arp_entry_for_who_has => arp_entry_for_who_has_int,
send_I_have => send_I_have_int,
arp_entry => arp_entry_int,
-- RX to REQ
I_have_received => recv_I_have_int,
nwk_result_status => nwk_result_status_int,
-- system
rx_clk => data_in_clk,
tx_clk => data_out_clk,
reset => reset
);
tx : arp_tx port map (
-- control signals
send_I_have => send_I_have_int,
arp_entry => arp_entry_int,
send_who_has => send_who_has_int,
ip_entry => ip_entry_int,
-- MAC layer TX signals
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
data_out_ready => data_out_ready,
data_out_valid => data_out_valid,
data_out_first => data_out_first,
data_out_last => data_out_last,
data_out => data_out,
-- system signals
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
tx_clk => data_out_clk,
reset => reset
);
rx : arp_rx port map (
-- MAC layer RX signals
data_in => data_in,
data_in_valid => data_in_valid,
data_in_last => data_in_last,
-- ARP output signals
recv_who_has => recv_who_has_int,
arp_entry_for_who_has => arp_entry_for_who_has_int,
recv_I_have => recv_I_have_int,
arp_entry_for_I_have => arp_entry_for_I_have_int,
-- control and status signals
req_count => req_count,
-- system signals
our_ip_address => our_ip_address,
rx_clk => data_in_clk,
reset => reset
);
store : arp_store_br
generic map (
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map (
-- read signals
read_req => arp_store_req_int,
read_result => arp_store_result_int,
-- write signals
write_req.req => recv_I_have_int,
write_req.entry => arp_entry_for_I_have_int,
-- control and status signals
clear_store => control.clear_cache,
entry_count => open,
-- system signals
clk => data_in_clk,
reset => reset
);
end structural;
|
library verilog;
use verilog.vl_types.all;
entity reg_shifter is
port(
rt_out : in vl_logic_vector(31 downto 0);
mem_addr_in : in vl_logic_vector(1 downto 0);
MemWrite : in vl_logic;
IR_out : in vl_logic_vector(5 downto 0);
rt_out_shift : out vl_logic_vector(31 downto 0);
mem_byte_write_out: out vl_logic_vector(3 downto 0)
);
end reg_shifter;
|
-------------------------------------------------------------------------------
-- Entity: fmc_top
-- Author: Waj
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Top-level of Floppy-Music Controller peripheral module in MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity fmc_top is
generic(CLK_FRQ : natural := CF
);
port(rst : in std_logic;
clk : in std_logic;
-- FMC bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus;
-- FMC pin signals
fmc_enable : out std_logic_vector(FMC_NUM_CHN-1 downto 0);
fmc_direct : out std_logic_vector(FMC_NUM_CHN-1 downto 0);
fmc_step : out std_logic_vector(FMC_NUM_CHN-1 downto 0)
);
end fmc_top;
architecture rtl of fmc_top is
-- address select signal
signal addr_sel : t_fmc_addr_sel;
-- peripheral registers
signal chn_enb_reg : std_logic_vector(FMC_NUM_CHN-1 downto 0);
signal tmp_ctrl_reg : std_logic_vector(9 downto 0);
-- prescaler signals
signal tick_dur, tick_nco : std_logic;
signal tick_dur_cnt : unsigned(15 downto 0);
signal tick_nco_cnt : unsigned( 5 downto 0);
signal tick_dur_speed : unsigned(25 downto 0);
-- prescaler constants
constant C_TICK_DUR : unsigned(15 downto 0) := to_unsigned(CLK_FRQ/1_000 -1,16); -- 1 kHZ = 1s/1_000
constant C_TICK_NCO : unsigned( 5 downto 0) := to_unsigned(CLK_FRQ/1_000_000-1, 6); -- 1 MHZ = 1s/1_000_000
begin
-----------------------------------------------------------------------------
-- Address Decoding (combinationally)
-----------------------------------------------------------------------------
process(bus_in.addr)
begin
case bus_in.addr is
-- FMC addresses --------------------------------------------------------
when c_addr_fmc_chn_enb => addr_sel <= fmc_chn_enb;
when c_addr_fmc_tmp_ctrl => addr_sel <= fmc_tmp_ctrl;
-- unused addresses -----------------------------------------------------
when others => addr_sel <= none;
end case;
end process;
-----------------------------------------------------------------------------
-- Read Access (R and R/W registers)
-----------------------------------------------------------------------------
P_read: process(clk)
begin
if rising_edge(clk) then
-- default assignment
bus_out.data <= (others => '0');
-- use address select signal
case addr_sel is
when fmc_chn_enb => bus_out.data(FMC_NUM_CHN-1 downto 0) <= chn_enb_reg;
when fmc_tmp_ctrl => bus_out.data( 9 downto 0) <= tmp_ctrl_reg;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- Write Access (R/W regsiters only)
-----------------------------------------------------------------------------
P_write: process(clk, rst)
begin
if rst = '1' then
chn_enb_reg <= (others => '0');
tmp_ctrl_reg <= (others => '0');
elsif rising_edge(clk) then
if bus_in.wr_enb = '1' then
-- use address select signal
case addr_sel is
when fmc_chn_enb => chn_enb_reg <= bus_in.data(FMC_NUM_CHN-1 downto 0);
when fmc_tmp_ctrl => tmp_ctrl_reg <= bus_in.data( 9 downto 0);
when others => null;
end case;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock Prescaler
-----------------------------------------------------------------------------
P_scl: process(rst,clk)
begin
if rst = '1' then
tick_dur_cnt <= (others => '0');
tick_nco_cnt <= (others => '0');
elsif rising_edge(clk) then
-- default assignment
tick_dur <= '0';
tick_nco <= '0';
tick_dur_cnt <= tick_dur_cnt + 1;
tick_nco_cnt <= tick_nco_cnt + 1;
-- maintain duration tick counter
tick_dur_speed <= unsigned(tmp_ctrl_reg) * C_TICK_DUR; -- UFix_10_6 * UFix_16_0 = UFix_26_6
if tick_dur_cnt = tick_dur_speed(25 downto 6) then -- drop fractional bits
tick_dur <= '1';
tick_dur_cnt <= (others => '0');
end if;
-- maintain NCO tick counter
if tick_nco_cnt = C_TICK_NCO then
tick_nco <= '1';
tick_nco_cnt <= (others => '0');
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Instantiation of FMC channels
-----------------------------------------------------------------------------
fmc_i: for i in 0 to FMC_NUM_CHN-1 generate
fmc_chn_i : entity work.fmc_chn
generic map(N => i)
port map (rst => rst,
clk => clk,
tick_dur => tick_dur,
tick_nco => tick_nco,
chn_enb => chn_enb_reg(i),
fmc_enb => fmc_enable(i),
fmc_dir => fmc_direct(i),
fmc_stp => fmc_step(i)
);
end generate;
end rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:20:16 11/19/2014
-- Design Name:
-- Module Name: clk_prescaler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clk_prescaler is
Port ( in_clk : in STD_LOGIC;
rst : in STD_LOGIC;
prescaler_value : in STD_LOGIC_VECTOR (4 downto 0);
out_clk : out STD_LOGIC);
end clk_prescaler;
architecture Behavioral of clk_prescaler is
signal clk_count : unsigned(31 downto 0);
signal clk_count_vector : std_logic_vector(31 downto 0);
begin
clock_scaler_proc: process(in_clk, rst)
begin
if(rst = '1') then
clk_count <= (others => '0');
out_clk <= '0';
elsif(rising_edge(in_clk)) then
clk_count <= clk_count + 1;
case prescaler_value is
when "00000" =>
out_clk <= in_clk;
when "00001" =>
out_clk <= clk_count_vector(0);
when "00010" =>
out_clk <= clk_count_vector(1);
when "00011" =>
out_clk <= clk_count_vector(2);
when "00100" =>
out_clk <= clk_count_vector(3);
when "00101" =>
out_clk <= clk_count_vector(4);
when "00110" =>
out_clk <= clk_count_vector(5);
when "00111" =>
out_clk <= clk_count_vector(6);
when "01000" =>
out_clk <= clk_count_vector(7);
when "01001" =>
out_clk <= clk_count_vector(8);
when "01010" =>
out_clk <= clk_count_vector(9);
when "01011" =>
out_clk <= clk_count_vector(10);
when "01100" =>
out_clk <= clk_count_vector(11);
when "01101" =>
out_clk <= clk_count_vector(12);
when "01110" =>
out_clk <= clk_count_vector(13);
when "01111" =>
out_clk <= clk_count_vector(14);
when "10000" =>
out_clk <= clk_count_vector(15);
when "10001" =>
out_clk <= clk_count_vector(16);
when "10010" =>
out_clk <= clk_count_vector(17);
when "10011" =>
out_clk <= clk_count_vector(18);
when "10100" =>
out_clk <= clk_count_vector(19);
when "10101" =>
out_clk <= clk_count_vector(20);
when "10110" =>
out_clk <= clk_count_vector(21);
when "10111" =>
out_clk <= clk_count_vector(22);
when "11000" =>
out_clk <= clk_count_vector(23);
when "11001" =>
out_clk <= clk_count_vector(24);
when "11010" =>
out_clk <= clk_count_vector(25);
when "11011" =>
out_clk <= clk_count_vector(26);
when "11100" =>
out_clk <= clk_count_vector(27);
when "11101" =>
out_clk <= clk_count_vector(28);
when "11110" =>
out_clk <= clk_count_vector(29);
when "11111" =>
out_clk <= clk_count_vector(30);
when others =>
out_clk <= '0';
end case;
end if;
end process;
clk_count_vector <= std_logic_vector(clk_count);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:20:16 11/19/2014
-- Design Name:
-- Module Name: clk_prescaler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clk_prescaler is
Port ( in_clk : in STD_LOGIC;
rst : in STD_LOGIC;
prescaler_value : in STD_LOGIC_VECTOR (4 downto 0);
out_clk : out STD_LOGIC);
end clk_prescaler;
architecture Behavioral of clk_prescaler is
signal clk_count : unsigned(31 downto 0);
signal clk_count_vector : std_logic_vector(31 downto 0);
begin
clock_scaler_proc: process(in_clk, rst)
begin
if(rst = '1') then
clk_count <= (others => '0');
out_clk <= '0';
elsif(rising_edge(in_clk)) then
clk_count <= clk_count + 1;
case prescaler_value is
when "00000" =>
out_clk <= in_clk;
when "00001" =>
out_clk <= clk_count_vector(0);
when "00010" =>
out_clk <= clk_count_vector(1);
when "00011" =>
out_clk <= clk_count_vector(2);
when "00100" =>
out_clk <= clk_count_vector(3);
when "00101" =>
out_clk <= clk_count_vector(4);
when "00110" =>
out_clk <= clk_count_vector(5);
when "00111" =>
out_clk <= clk_count_vector(6);
when "01000" =>
out_clk <= clk_count_vector(7);
when "01001" =>
out_clk <= clk_count_vector(8);
when "01010" =>
out_clk <= clk_count_vector(9);
when "01011" =>
out_clk <= clk_count_vector(10);
when "01100" =>
out_clk <= clk_count_vector(11);
when "01101" =>
out_clk <= clk_count_vector(12);
when "01110" =>
out_clk <= clk_count_vector(13);
when "01111" =>
out_clk <= clk_count_vector(14);
when "10000" =>
out_clk <= clk_count_vector(15);
when "10001" =>
out_clk <= clk_count_vector(16);
when "10010" =>
out_clk <= clk_count_vector(17);
when "10011" =>
out_clk <= clk_count_vector(18);
when "10100" =>
out_clk <= clk_count_vector(19);
when "10101" =>
out_clk <= clk_count_vector(20);
when "10110" =>
out_clk <= clk_count_vector(21);
when "10111" =>
out_clk <= clk_count_vector(22);
when "11000" =>
out_clk <= clk_count_vector(23);
when "11001" =>
out_clk <= clk_count_vector(24);
when "11010" =>
out_clk <= clk_count_vector(25);
when "11011" =>
out_clk <= clk_count_vector(26);
when "11100" =>
out_clk <= clk_count_vector(27);
when "11101" =>
out_clk <= clk_count_vector(28);
when "11110" =>
out_clk <= clk_count_vector(29);
when "11111" =>
out_clk <= clk_count_vector(30);
when others =>
out_clk <= '0';
end case;
end if;
end process;
clk_count_vector <= std_logic_vector(clk_count);
end Behavioral;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc379.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n03i00379ent IS
END c03s02b01x01p03n03i00379ent;
ARCHITECTURE c03s02b01x01p03n03i00379arch OF c03s02b01x01p03n03i00379ent IS
type M1 is array (positive range <>) of real;
subtype M2 is natural range 0 to 5;
subtype M3 is M1(M2); -- failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n03i00379 - Type of discrete range different from the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n03i00379arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc379.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n03i00379ent IS
END c03s02b01x01p03n03i00379ent;
ARCHITECTURE c03s02b01x01p03n03i00379arch OF c03s02b01x01p03n03i00379ent IS
type M1 is array (positive range <>) of real;
subtype M2 is natural range 0 to 5;
subtype M3 is M1(M2); -- failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n03i00379 - Type of discrete range different from the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n03i00379arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc379.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n03i00379ent IS
END c03s02b01x01p03n03i00379ent;
ARCHITECTURE c03s02b01x01p03n03i00379arch OF c03s02b01x01p03n03i00379ent IS
type M1 is array (positive range <>) of real;
subtype M2 is natural range 0 to 5;
subtype M3 is M1(M2); -- failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n03i00379 - Type of discrete range different from the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n03i00379arch;
|
---------------Reset the contents of the Map to border and empty unexplored cell encoding
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Reset_Module is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Request_Set : out STD_LOGIC;
X_out : out STD_LOGIC_VECTOR (4 downto 0);
Y_out : out STD_LOGIC_VECTOR (4 downto 0);
Data_out : out STD_LOGIC_VECTOR (4 downto 0)
);
end Reset_Module;
architecture Behavioral of Reset_Module is
------
signal x_temp: unsigned (4 downto 0):="00000";
signal y_temp: unsigned (4 downto 0):="00000";
signal set_temp: STD_LOGIC:='0';
Type State_type is
(Fill,Move);
signal state:State_type:=(Fill);
begin
process
begin
Wait until Clk'event AND Clk='1';
If Reset='0' then-----------------------EINAI TO ANAPODO. KATALAVATE ?
x_temp<="00000";
y_temp<="00000";
set_temp<='0';
state<=Fill;
else
Case state is
When Fill=>
set_temp<='1';
If (x_temp=0) then
Data_out<="11011";
elsif (x_temp=21) then
Data_out<="11011";
else
If (y_temp=0) then
Data_out<="11011";
elsif (y_temp=21) then
Data_out<="11011";
else
Data_out<="00000";
end if;
end if;
state<=Move;
When Move =>
set_temp<='0';
If (y_temp=21) then
if (x_temp=21) then
x_temp<="00000";
y_temp<="00000";
else
x_temp<=x_temp+1;
y_temp<="00000";
end if;
else
y_temp<=y_temp+1;
end if;
state<=Fill;
When others=> NULL;
end case;
end if;
end process;
X_out<=STD_LOGIC_VECTOR(x_temp);
Y_out<=STD_LOGIC_VECTOR(y_temp);
Request_set<=set_temp;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ecb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ecb_e-e.vhd,v 1.1 2004/04/06 10:50:04 wig Exp $
-- $Date: 2004/04/06 10:50:04 $
-- $Log: inst_ecb_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:04 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ecb_e
--
entity inst_ecb_e is
-- Generics:
-- No Generated Generics for Entity inst_ecb_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ecb_e
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_ecb_e
);
end inst_ecb_e;
--
-- End of Generated Entity inst_ecb_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.numeric_bit.all;
entity udiv23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity udiv23;
architecture rtl of udiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity udiv23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity udiv23;
architecture rtl of udiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity udiv23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity udiv23;
architecture rtl of udiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity udiv23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity udiv23;
architecture rtl of udiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
b51+hsnCybOdW1OE0ZcOlRhAV5kZ1Ru6+rRHLVNiISiIMtbIecpfGSDxsvxDvBtRLTt1wvyiHBK5
7E0cw3IkmA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Iz6+AbbgStYdCBB//4ZAV1DrKpjt103liCPpm1WQ9eWto6sfvqtgzJcOysKq1XHDVtSLp/vI6Nsw
R6YiVdMHTqkkhlUvFaA51/b2yf2dIYmYlbInMzEdGQ646MC1SLcz3swvTa/d6M1O0CxqaPF3TXV0
+R2xA9w5M1gJQZHx7ac=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
3YdzUWjUsJk+gTCRXSXb+KrNLT7ZgZ0yFfe2sGRg6JuapbTIeGQK8WhDXRYDHOJDYflYxj0I59Iw
fgJ6VVuAusorBYKu9IRr+Lw6xSw7qd0E8aZ0FYCJ3lyBSHkO2zP8PBn6RXnSISQsNBmcsggDKv69
vd1ct+wICRJh5hdyFug2ySeMQfY08sc1j5NszllNujg2b1/gLTZyI8oLz07gNfrmVOUtYxweKY6v
1WtxRwBpMlhFAmQIZF4q7YgmYTKYYhW4ydy+g8a/Pruwdjm8+5G7E2EQ2Io6TFpwsFEfGe8Uiyeu
890ukUf3R/lzITUpdwUTR+iiZ+369jfaD/66JQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
tu0ozJYZNTiJI8TIF5xT+fCx6WyGK3aLHTT3T5DGA+cmNW/owfUc4iPf1lYkX8ZVg+MdjFUvIZWA
oc/dA/rq28JEujWkZKnTQCF2ygpvrwPwwHqsLPJ3Cdqtigu0/2/n1FckHeT19r1D4hvrNQmpVByS
522RznRpWkKwAEBO31o=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
AfjKebprRhmjOzGs7RV5SXCXT/zlmn+BaqMqubBZr3XmBpXqm0npT+dDd4QZsAhfSPlWpthTZjri
Xpg74EyTiyUXwG7DFRK+OpW1ako730rMOZUWf2i3dqqnZSyJ+5ecUEdz4pXGR69gs6O1X2+qjyiD
LHrH993UsKiz5iLGZ5aEdngffoCeMKEXNifXLtb2svPW8jfHluro9oekY2nHcxAeXLHEjcLXnKFq
4xNFWDOj8NUxpiZPRAL6LFi33O5DirX6BjCTPskNnad3o+AuypLLQUESNpbaPGjSestJqFh+YXRj
M4eqyUwHK2LayEbO9KyZ5R9c5GTjUEHZ1fACbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13776)
`protect data_block
qQSJpuiE9ypyXSTue9xr8FIVBHob4wpWABrOmcx32WIH3+v8WOIl2PiiTpA8vJp700nD8NOckAdQ
LQSbda7GjTBhwvxAVb0ogaA+zrFLRZMC1rEEuZXbS6vQl8FDS2x9QKqcCE0nQiDmAMI5rU+m4nJ5
8IBwLl6WOC14uKucse/XDWGXa13dy2L7XhBxEYRMXIoYkgGLk3d2Ws1831AUHCnbPgCjFKdcB+eO
f8PMlmqoblynD6VM6bb8KAF8VFSnuoTZ1WrC5rJeRiuUSlv/Pb1nUpgb4TO4KP4oOlVPzBRaK6c0
Rmov4xwJPv7yr7vVlEC5tqDxq4mN+Rh3Qsp3nRGhx2X2tf10CwdgQ552TJNVB9fZ+ap32UvN67wv
QogMHJdh7ofxnZXPq2SI9VxyhCQBJWYDepvOdNkaMex5zjPtBCITKReQLsWxCxJy6ZCwxAafJ3P6
gXvqk+9MkHKfWhzdEhd5OV8sKeJfO5kwr85tePhqhtYUrhFqi7jnsRpVywqCjHAutKjQKeBcoMEI
cfWI7Li36vqHa7IKVTCvtlB3XKkk9cesqXMxRAWnuS0sEx0mt7iw0Rmdbajnp3I7W2OCQfmX9rmi
CNZwPEqp7ytD+hlaJfHpG+5ncukOgybISmTdt8/ziqyr/+bKbCTNs2SzjKB7IXDMPAoKOwdvxT3v
qRN1O07lrbL2OcD64P+JEoHBMb+BT3M6AhDOxfPIvXh/eYj3gfFvd9158K6WCR+W/oRPN+PpgCEA
zNXQoD6ZRMR/VloDcgZxFVImeJKjViEP4pbBryP+Y9ToE2HSFwKyDcWQvswOKX3yd7lQDt50Ki6E
oBYUxFa+uogUmz/zhihKLjf8ecQeaMRcmmViDdY439A4dfQYDQFyRa/6VrGg5MsVBx8f+hCrRy85
iIv/h6m9jYk5n3k63/8gnFjChs+QxYy03+1Ft9q3NoRRDQiheVSQfVSHn+jiEyWyIKdxhRX5RCLd
1cCgQUNrtUvoUxmhp1ZZTV5judJtSRaWS4ymkDTogAuzytKbOtW8DSnXNNDOe2fosL3L8+MzLmgz
LBOihjzut8u6eXOodufe5ohMhwdTKj1DioUR/Jwx+raab3GhkEMjeTMY5Jylcip40t3cxtvUq46Q
T4OrR6TBaSDgicQj4vlKfN+f7ey1uhnw+Ad0LT3t9RI8/HUIecKxxDj5SE+AdC7JsqOGhNjFhl+m
/fiv74t3RV4RzkB4/GpcODKXm90ZW+BDBRphL69ozCi4Pt4gTFR858fcEHRyPePZck2HoHAYn0YF
adZN0habXKEhnYCG+cyS9Bt9y06A/5ppCI4fg63MZnrtmkIFldmQcxljN6v8O+QpIetfkYQiUFOg
1Qz35Cc20FdJp9jmQt4QpBHn2eZpgadKBDvjKIlCBFCtRGXntKU/zx4lzKFh9sjJFlDfdBbjHPb6
+FuWJdiHabu1cKN6D83LYLEym08kbQALPCO+qbg/uFtKpieIbpjxUlu1D6jn/JYlQhK6e4o/T0ox
nvLVKiSTyTlvXcZnwWdH2lkJcdRpcn3BVv0VIA+OgjG4FZg5ilpp2FjS1/SU3QbsIWLONHGXb9Op
b3D6V4RSO5GkKSQT8qmSa9cwN9nmM1CIiJW/gQEYeHFJIMN/ENOEZgB1SFHCHmb+FOaQ/B7rVt/Z
+LB3mvLCrwt+sB674Nw1G5v1StCTbQMGiC3fLyReOUqkLjlQEFnugNuLTsJVQY4xna8tdK/GKwVs
3HSB+LWU2/7xCU1+44W2bRbl7VbE7HG46AttryDEDSoZDI3jUX3BC7UuzneKP0MHPivRiTw6ls1h
acuAdLjldEV9JuUUuD9sGb4e1ySe1UtTwtPo0eRFpKKj8HstiFr20MYU8/K0Xju0D6rRPUWbxbj9
8EvEbukkthZeDqoqfPODkummbiykq0J9pR8xTKL/8cRSNkidFhSX5tqgtcNd9Uc5Bds0YeTXUYPF
pvNvMDaiEMBddMdsaCH5wD5DkUjTmLWfkixxISC8p0bP8Iei07xwtVZb1EJGM+UEBq73u7lr2hT4
NIb8Q9d3mH4cNCvfNsK9MlVN1e4v70jt6rLUx3zzDyyH0Tu8fMCx8RHJg4etYmkxu9l3hiu2j7f3
/IKwW9talUGtI7+M+0MJCcPhnbGA+MinV7KwhN+Cj3zeWV9DDwCGrtaYd2k0LjeB7WUurafun3BB
aS4bYEXvNn8yfaEo4LNcmHBRmX6QIgm3802fxarlWMobcQTxlrTz0xgslFcsXtixqLBR/fPA89FQ
Sl6N6ik6R3wWhpqfJ399I9BBjNYtAsIyaT+D8WBAeCM7c3q4xH7sZ1S4BNV1dQU1fr20zwrvEpz2
qXxi5SPP1R0DDcBmX6DqwvB26bg8rBTPZWV1MT/lbLwleY34M07Ln8NHJJuo+KiW8fBkLPb8lJ6t
9MC4h4ZFp/ZN0gy27DUwu10QjvzadOEodK5eokP7V6eNKkIlDi5okdzr3TOSsFttQ0gZXh01ZUeA
NLJlkqzxFPzqzyw5H7rX7orCRWqBRfkGH+48ovqSc/+Y5f2kXg3OfSUtOlbeJggLUfHBuajRMkhm
C331lLXYCizLqCAnk8r3HHJx1RuZZqqBEU9n8RpEEBrCKeUoqRd60A459rxp3SYLuhuVnXm8v+e3
fT6mqvH6GH0ESE0s/uJWB5NCcOQ4UgvncVIw5Z6qSHJ7PhvzMqrpoUeADSs28EJ/gtx3c2bNfaqC
mKEQLnoWhfI2ECzgQoLEzUlo3k+Yyshs0TSrwo2keGuVpT7WOFR/A9gVtip98+BaYLRY6/cGLlq9
CwXkR9KyoiRNtnzSkySubqxhRkIHuPr2All6fDamG3WvmdZmCHa7ztiVWV6ZTqTL2gBcOQ53OuGP
E1UMQdAAIGx7usPaHIMw0QPrvMcLV2nEF49k2h8Z5GINRydyTiWWh4rC/ROSWqCxTy+to7QVpcwK
5JScf5Uw0lXlFVTIvnOeQq/+iy4dyDnu6TKiKkL22c3El5FflImM+bLArW8tjxr96kw5t4Ch1y7S
nQUqr5mvfkV19Bs/6UF8e01xxhDiMPc0Yq1WBaOmi3q02FVIlwWzqfdluYI7N7MLJd/Av/OAkCZv
nYfPWXY3P1Jkh3ODA3CY599Y08dDAyR/XEvrXFze9zcgxK8tuRulES0QjgqlOYt+dNkgizfdYVSV
VyXWwORapmHRg0AWxTxvSED0FTvjvB12wA188mgnYLxwggmFWMcSPkGzNS1jR2aousciyYObp+AM
Vcwipw90+ARMUxs3cZRtNmlAaRspLtsnArqUrOR2ThUz8hki1vU4Dxx8qEQnu6dEd96UExb1V0Xz
SgqWFXoW6eJmPe/NqTrtnUQr/WCNvQuruxttVIKQ3epmp6L8Anng8v6oyqYgqDEEpRf2UMPoxwvG
jK6r/ice2I9x+ObZhpw6N/9Wjo9lxTWtNQK6Lr5qkNby8FgcnzuyvDuXxJuX11H+1mnbS1HXHJlD
Z9MM97OBVnxEFdmos5kkGYyvoemB5gjZjV5B+8eVWx0GfJCMR7eGpVLeRIppqZejYRCYm4+JJZ/g
ReYkWSIFV8YegST4BojW/onGASnBmOs2Lih2ufMC9+RAJ0XPcZ/TF4ndy6JL5gK/KG2YVPkWIkCk
kiePoB+i2fcIJnScm0yvmtyIS2HVzQFlFnAj7UB9Le77hRgD1KEY4LQyVF1syG6+H61doH0YBEiZ
+79Fsrm8r151u6UHa14/PbFDAU13bnmhGbyxPovTOciqq5BjzbqfidKi4b98muUrJQaqzByYRsTF
OXg0XBrt+GVgvHDoy4HTJZOjwBYJANDLrbzeh1xATikOWeA7oqOIxMOM29112X/tSIY2EM6wMsZr
jJZypS1fW4MAZCrsrYH7QuQUycCLYFPZ7w2DPI7EZqP8O3Q/XCH31F8MOea/LvXMozROsMBjnGDj
Gmkl77ISkHm3IOd4CVmVJdvwYY6GrCNfahhpEDfFPTkLXuCQbn1O7mq6yRcbu4ROkjsdu3pldLc0
S0dnFSnfmi+4BncR1KacEQUzn7JWgc8YcvtgDXi8tTihP9qSfdaX+9k2WHh89PN/bpheqPYGM5Ow
Shf96A+qzO4MYhXvKqAdef9Tf6McmcfbjJRtsuJ9zAbRBth+tgYUk/VQJlnl4hc8oqI/bdgEuudv
WpHxY62VWL3RnGEYLhpKD7kIonPiRtxfAtw8oYzobR9wdWwvPP2siIwAzB6PzQjLbUkatcmVgk1g
mz3TLXXM2VkTVIaxVkB2owBkgcatGi8R3VVhOIFDbAdqZhRCjvJgeKJIw0Bfz8JJ2Q/rami6Ax64
z16UQo8h4j/Y/L3Ra0plXa66FmBF4/1iLzqUvhNmsSnhB8EmElJFWUUchTQaX7KdTfGdfVbOyoE4
EpisRHGcZ1/CYLqKWstxgQCbupIM/sM3AmKVb5V9vfdjySPvuJsGrjbSXuT+SjP+Lm+Y1QmSWFUF
GznK3M1HNjerNH2UZPQo+alIq57fCDzD37e0OE/C6Z8uPqrOovwG5NfVtmiB4lxVcDCT7dBwHmRO
dIF2ErXEv7ByT2orZtRayV9hu8GWIF3UpDC5r+CTDKWo2j6fsJXwCdrgOzwRZAtmlMqSQD+zJTFk
4w9b2QpvxnynlM1yw7cbNHPr7cmoCTUYQWDuosQeMXBPi1JUuPJYHuzcB6n+4ifQb/Sy89XVHBIR
PKR1b2k+ZCM9xyS8hBRoKLrzktPAAq14EVSxIrSqTCqOtWdXADHuDO+aN22hstyXSDgEuey7eN4t
KToWrybn7iU7o0UuVQ5OElzsGBYMufFcKoxQUTBCPt8uXeioWmYdJLW2AvqFeokcsk/8ucTgPjxN
6ng7XuxxQAu13aSP2p4ToYamTryPS96HLPY3PUQ3O5vwyCgZjGnhuHlOVJGc+9n955a9DHjOK8HS
OGwPi5J3TnVNfjQOCtemjGWxgff9bk++maxUz3Yo/QA1RMt8SF/VQP7yRCzgXetkaCFYVJOd1Zt0
rskvd7iqvHUjVw77OszgIyM369qjVx4A3kIPqYj5RHAzh709QwEC6rF8lN1ba8drx/vHbLLg2UL+
V/XtzV531fTdq2x6PODtmj7B4KVAdYBgHniCrwUOpXz3qG5RA2rRXfrLygBhemuD4UPVGiuMlnLx
9/tTZRa3xvdzM2MUj6VwBdGT22dfLN2H9rdV2bWr6fEeDt0VSnZ+NrjgeEr3bw1pEG8ZsFQjBTVQ
r9Bm0pmvvzywShrlTy/YqGshxka+YO4+VAGT/c8WcTYPhHSKYcxVGh8xIWouF2z0D9f1DkpfYBrt
gR4khkkapOh9Tj2jr1lAgfomPd8vDz3hY84YZeTUeSYoUFgzIewL+yIrj1/mZUhsGDSfMnYoxfBu
kUliTrgyEYGkMgCo0UPyAU9+OVGh+2yGlu1pdrXHHHvsN8FcoSig3SWJaG73s1p2CcQhUSYvxZGa
LU9PIjQZ1PcnJM1dyTsubWARjKlg2Da5WL0/hG7/RVrAb6J7P3Ws8zng+mrRS+RlpJn/7iOyK21O
MDmqQ+RO3Dc3abMgLqeptZ4YXD56cTTeq3yzYMKLVX+3ZcIGMfTvBABPivc7Ajod/dY5EPwEeB81
/QhS6fNfnlydTPNudP1+FRn7ihqJEup2PzBLLNzxlWYaGF4tDSieF451DjiDXV4653vawCYqFCi5
JLG6gyl1pU2fGD2SDByv07h4dIn3XGjEE2LSHznpx7flkqcl9sXovIJzDFEXkwSiTuvX0odx3tcK
cIWbTfK/yj4C/cneD2yxNCqecRPodVy+2R/xU2n912rtU/o2cW0QWjwa68oEQbina8vi/NGNWQpe
7wbNrIwIbAy4UJKRlxQvhQ99nSV74ZFC4x5UXgLJMw1dDNV9+rOXawjJefx1NVr3wLzvKauOmAQ2
xpdbUG7BSWDkrljmyYwHQpabOFnzZpy4+JkSVoRPaKp6RMR2KiJDrIqxJJ+/yk5Axs6XXHlY7HAq
h0Sal+AChNzO2zSp3fl4Mz+oI9d0Nu+xk0kH1jiL4A1Xzbce2YkS2SNCPFy6L3j0DY2Tqk0rEGQV
zUgx6utIs8wNxvp5aV+1LSjzFiJGB/lULZ6hxZq7PUJNo9XxgdcIoL9rAfXueamiRNykHXswS3OU
OgsAaMu0ajYZvy+fZTBPBImuFTzqqdGByOhZ0rwk/hTxhzvLT3F0IF6IB8E4ir1oHLXD8J/+GGER
ZdMyt2BPuiYdjhrUhX0z8Qx6XMzZCRl1TkjBH9j8FaLKOAls4DTOHDohscRwkBfP2uoXws9vPqvi
r4VKQc7V0f6IlqZRWp1APaTN2if+tJ92tLFrgNEGU0vpIR7b5TwHPwNV5Qy9eodHcqqOrlwN3RAa
1GnVV1QWSftqlHn5oQmjj6/ePfujIICrEW2EQsKG3hTaPtiS1ZI7+266D7QeS1X2HlpA79EoOVTJ
vF1UL7DFOJ277603npFv6LoT1zmGUU3wgoJVNw9YlES5lxA5jgkAzkEA+GDMYL/8VJ9gxuIW37hA
R/unD2sW3nRGsWLk+87ho9jG1x+eg0n02jRB461C7ZJVNA4TuvY4B/JuTGBNYRSWG0zbxmmb4IuO
L1hMp8JTOuFCErgNGZSWNC0jFLj38g2ySLkk212enZf12qBfKilndeumepkXNGQW50g9akoo0SJ0
/RN4FgTgeuG6z9u0IaUr7txKtiXd73qWMLHhpArOkpfK0u45Nkl5NpgitW1OzsPZKOq83YoWRqo3
qXg0vjIMSLiWqdKBDehehsUIH46Ie1G73dkPHYB9pte/Yd2PL96k5TXriZd1iE8Op4mIC3p/fhKo
NROwC9HjWBkGMuwq3w0d1wRcLXR5A/2vYQJS24OVA28apnuO/3hrsPiZmT6+8rIDF2Kbj1Me0DA6
2OGF3mAy9w3MxP404yfoZ8CYgoYN7QqNpbO8wui6wnuNnX5gcv5GgiM8RLHK/UveNeqfDrb4i/be
LMHQ+VhEkktEr+itxQ3jiVHlPjZxsLhiQT/CRObfVSbAKrW350yUC09eqRFXNH/BwwNTKdPgXi2e
E9vnfv1x/Lh3d2hUW8OUuxM7WBmmPMEdVuQy3SKXUJJEk+ceMFqNLZj9mA7LpLTYxFZXOuWfVY4P
JdpDRRhSV2G+5Seiex2BZgwe7avOHToo8j4J445CFXxPVMe7pAmTGGc/sPf7tJW2RX2r7oBAJvXK
Ve2S+ESNp91839qQ81I/2ry2JckKOMjhLKoiICa9XQeoxZzMVhslF2RzoGDJEEY97Eyytb56yzUH
HzEQCHZUkGc4FqfLLB+NQuDmpkAh6pgFks5GNupTqFVbBcX4XN4aXzcWzXLXtwgL8FAMwoUVLCgM
JAqLKpuAqhWc56Jp8xc5cEizPq3x9+ILae7frQPmk6JvvB0v/9FODtA+rnS6r40wWbxz5vlaHuo5
aUkUJe33GqSDN8ciRYfbto74b92POWbQAXGTF3mHfmx+xobacyqFbR4QBmZ9jS3/eCz/aK+BDzVh
AO0VX5r040hPoEzKEdE/ThFyhd3v9nfGxrg+6rigStjP4lzp5F8JZo+LFq1vYBN4RQstTvZeNG5U
zjrn1m+cnt/o0IiPUSTwjJrHrArFVyBt22t2VnbzXbcXTVmDkjqQ6dhlVqyb7UKA5WEKC7mg0atL
NRzGfpR0pXUvHZlpf8V6Ast2Tw9lC2ZNCLl+LwnFA4w6gPPhZnuXxWzD67F80y88KqML2bLNHlhj
sFa/MeYw6AKe4o2GeMZOKyHqLgX6GSIRFNj9JXwtU1f1/+N3QZpDYoDe/BMX16Kw3QbhMpsf2+/H
e4C1wlocebax2toKHEYDbhZTaUtaQ3PAtoO2DJkqr/AFmC5GbYsEB2ijOuTfuj9Dnl1QEyHX2bZD
q+KQba6/J2pFfa1cLMRzci5WtZJa2xq8eO3eJaaGDtEEmdS67+zgyabCPnS3yCvAXsqNIc7KQsOo
sh660pIRF3VxZxAeYqS1HfW3yc7ECik/DTlsYX97efsQ5WPM7aP4E+bgLlEUNwae5OhhLLGxd8Pq
Qnv1fhXAY6Ba88KH5Xg+Sw0nXSoZn4E4Xx8LYjJpMgnJ+yx6IRdsDeapjkUjlnRfbNTieiqji8xF
rqsEpMOn6I4PeGsZCvWaMkK+QkaRcgIDEfzfd+yKQiVbDxvhtEKZcaFrYgpY+18j9u1Kzfn2xkxp
k8LVzgMAjFJEE4JMbLCc4zEyAWPrKMUfyCroYppLedJ/ttNLu5bGbw7/GB3A9Ncn7eiC3efRxcyD
kDDJTUkPNnk46OFPtEExqYPPf1y0a1yH+LF8GJ4AIIlaY+5kXNvio/0qj0mIYP3Una0X0I2df6Io
4jB+fWqPiyUMyF0dxOH/9N3yJZ+5MARHgcqu+Wnd2Ekjj7rBbUoGO6im7D1n/e0PvHDITYuZnYxm
DIxGwHX24dhpRy98qIBq6dDCznbjI1NaLFIxWw3WvvCJmDtPbc1bX953l0QFQTNuBFlUuEuSkgKc
kjZPUFcy7Jw9lRVADX07xyyjc64aSWC/iYuDIFtDkk079w5T88eLej20gw3sQxfRHDlOgc29Wxq4
3obhZIiAseqxE+u5DNH2lUKZXZPHokJw3Z6AgF/87DdJblB98Kyxy8v5IwqPgZKcjOgRXWTO9+UH
RIfDs6eizlhZDmMVrREj4MlO1X+F6tgQ6EC1111N5DDXLpDyPfsP90FcsaHN2wTkFY0Km89GD4UQ
9xzofz4w9BysAmN9T/POuOw0ogjVI29ucDk9h+4oIa+FY0ttQcPcT5v4Hk2VjdUrNEq+C5asKNe4
G5CtYv2fmeMtqmOEcA9VZXnHGboH3y/e4Y8Ks4xjviyqVPdjEGw/DtQb3u6RTwETn7PGGYpFg2ca
f2tCUxPoFulox6U7Pp8jIQveEdnLYWlOSjiOLa5KgyvS+3umXZCQ9Pyx8D2c9KCOMvvg4SAi/Ido
ERjPBLvg/plAo+t8zcL7TpxWSCIjoUMBtuEE/HGNET+5b94QWH1YxxYqjpK+085S9hqRgs1QHm+b
quHYhMroresYD37eXVrI0ZvnywrqntmqrphlPN1MFReAL8JIy2FA3thgB9RsqZ+Vnz1g9plotCTQ
e9IE6KagbaR13iIZ5IscxG9e+5IMCOK0Cm3y/lRRgxCCo/HUBbw63gnt6jCoIBZOWQtBgRG51dEK
4K4jFVLBCbv3ppV9t1lShgpUXSHWZeLwnqyssxbCODqoUhjVS1rBym2MRHKz1pCpLUqWHwFEwE3s
QeuvBFt2qti7uUDhFu5BCtYBCZx+npTLTjCwPSsv80vmmt0Tu4048uyOpw0eRepVsmUwFKfgXfhP
IFb2vNClQoiJEQa9KoCYV6aY3v48UdbV9CM9W4lZ3P0cteFa6cu2HdgI6C8+QQlAg6RaOkOdDCq+
D8KfXZlXWpIdaeLkLq1zYC4q0pSQQHrK9wzQDUDPVFn1mHiZWc2eGbQfGHnylFL8gSJ7Gq/9rKUZ
07NHIvBdfhTfUO7DuD9QA4Hjn6jcTC0DCvscy55Muu5z0oM3J12Vbz6MdONQ357tdjMB4m+zGbrm
d77ZlknyNa9XMXzKbACGST2m7bo7q3S7aTlCSn9ZWNoC09f/XQW6cp8RzwhFSpArvKLoyJ2G7sXj
17bqofMB3AAF+5yTID/Cgi35+a2ufGlJP2hRQBpOfd4JZia1lJQyMgpEI/XYoasx3dPMNJchabr7
5my8376O1WbnVq8cN5Zl4Sznw5vzckx1Tl8aRcd/xzICaR36/Z7VeZ7868cENfIEl1mfaooZ2Q8t
/XFDu2apKhIXbn/uYR5P1kEUwx6YoaVhgBKMaJIO3bOjPM6Y94l/v22KMBafa2/6Y99Xxdd0ke6G
Le64hfArT/3TRTl6RC9/pfHxrA6mhKeHFYGWjcMs0W9UlLCIuZr2Tcoolq8JvWbQxo2RZm/KCm5j
OJHdlClipprH8+026XthUX/AOrvxTwenT5Ru45NBdawRnR1lsaLaG0IBkBFN7vj5/qGyg0IFmA3u
go5Ue6osNEWYs5ZZv7dX6jFpCYIpBUxcXQWRjlITZ5XUA709oHrizuhQD+voREUXDGQ22eh1uVbO
1uyJ9kGqANlYJ9dj8sNbX1N0uGmuExmUU2HMDyQV2yVW330C7r+Hv3Vieo4myPK07XUQoPr+zyIY
z543pC9ML7lO3VsIiMAnMyNDvXCahcA5F7eriVzeKbu8eTe+nr2pwUn16awl4v5u5I+V0SIyGROF
fUe/8kdTdblkGssCvnfBUQgjqT0D/bMYmQSFtq04i6bsmKCXq0Qn/ruOCGehOhY8Xv0IN7IN6R1L
iyBeXtHA2zUdRgMOo8oUQ2CoURGY3HLCuLssmVNC9yW+3lzlYwNFAWams8YuV6ZaTdWYL/5STHr8
kkyQzw5HYde+UHsK329wL2GOr3mP4ncuqFsLxvv66MyDZLkWAT4sa0GxhacQ8pu2yqwbQj7E0pNT
sgLJpgT3U6Qww10kfyz3ybledZPqg7bB3UEBm60I2BkDCvpa7VrKVKz08QePNCF2EaCY3/eBSO8J
8rzFBOlByMRcrtIWe7otg1ym3//qfw7Dr1370VinSYEzMqujn5C6bkGZvqyByxwTzSL7W0ioKHRx
xMS0kHWOii/nAguE+RbgVsX0/S3nLn4+kHt77unIB3dGhuD0FMnVC9dNL39BvhXX7rcai1mRx6zS
jBFoPUjJlRVtkWe2TNIJfD6OyOa+ip4XTgAEegogXea/PAHCuxXgV/7yWyMbdHGdX0wcU7Z6xggG
XoR0mIwKiRc8yieqwsVQ93Lml3URTPoev/VklC/aoJVq40vaJtEY9Fxe9x4MfDD5BzmeDKVgwb/k
iBLbSsA2hP8FE03QO6irPRz/RGlZGuE+n4S/rUwRgiCn3dMCEMEl2rqd1dXvpXJb5gOfQocb3N4U
XnrZmDxnCQzBnazkwkoc6UB5xgQnnOBjrDmgt8nSkHf3OGzTZT7tx68Jur0XirII+skGBOM/t7Jf
fGNV+rvA7wD+0Z4UkpFdKwhnFlhR4SrjHRv8JMZg7vyZISMA/MuEVn1sy5HBA915kTKO1BupeYgf
4jiqUTWp8A6YQ3Hjn+chuKKSq1jPBCk1tN3v7PwYSnYsMdlTqzBqr5IHP/Ge0UdnKRynT3MBxoQX
0Vx6fpdnxMaHZrT8171LZmsLhr1xqUyJWMNDvSNzXe77V7kag5D8uBbciFudJwQWqN6fdq377Lx6
XobZDXsXRtYB9IWc4EcU0KzcXdQ1Cx0Kz0xf/KnQFG09ZL6/sO1q9RZC+wl2TOD8OmgNViCriqxA
YHSyfKaZm5ctbjj1LqCraYgaMelXMRGTH0KFfeWL7Q44j/G5nRrOdouz7oaZFxK9dVKgnbD3ythG
wJEduGTtOwnecD2dV+2RBw/s43BGrs7xJXdStK0WEtaJqj+0wTXBpG2J/gj2m0eyY4RiCNIhCB2F
Vaak47mqNAEN4B5YKHLiuLrn/A4Rpo2vNC7Br33RbC5cTrEFIvf4f7DS6rkzVY1sv/doKEbCLXX0
8AhIOdNZHhEcYZEtnRG6rOxADyC8Be1pgbKraSFaGlHXQCGb19azaKhYGx3Fdy9UkAEtU6zW5Oas
eSqGuasQNJHeaydHjETYMjPND2O43yBV1A4Z4x47TPSW7mcI/xznckxyLbLsgLFz8nefiXhcCIw+
cSK1oB3LwVN4BgkiUDlnAiQXGla+jpC5LPlKuXO+dAbgrOGGMqwSDasPFHGX712kmT4qmKjY0V+e
Vf35kWQojmoWsWBhVOweF98sIO/buN7zkHsvxYUZmSm7drgbfr8jzol5OZYlPY8M8x8h7UZOlP19
LlNSBuvylOdSH53vHASKcXjaLUyrBN7095AoUfocyYZ8TerxT5EjyOLfjbVb1MSwxZLNc9z5c5Xs
qkOSa+IzZQksPP9wwJDOoDIjzriBjEyL+S2IRA0FRR8Mi5v3exo7hA3/53WXs6qMWFTOoqVCkfas
fK4Yn+CAl8QnxiDNr4c2V8p6KOikc9bVQtyR7JbpJgdUIsd1NA4g/MVhWFyMSTrEdoKuNS430Rey
GW7LCpgzFp72S0tpTI2SmH+TS6fF0l6tYQzEGgu8APJqCqv8P3Cva2z2no9dMXgQ+uc/5PazXBxX
D3PpFbnbWx5G5t1pd9QRhrAOYLV+IEcnEoZqoQgThMR2eux/Jp5fpbyG9uN5I3pYmVNS4WidpCcN
UthTUg5Pu2MgktlOKnApx3h8CIS/sjTciCe2i3ef6+B1enhNfk5vVBv9rVTrZX1wyjqI9CtbZKx2
XNyfxlhrgM0OpftBoVYPoD8smTYOPrpkHhxVUN5OOTmLkTxwk0wnsf52aPrjyJ+gjpO0zubXUFGQ
ujc+y07iR4D87aq++osqhLcs2fMQtyruWM7XJTrVTz7PhHR0+xZt50fQsSmTEMrGDwO170sju+lx
jKH6dGiluG0HmRcQxRbU4FiTCh9nUlhSYYYwjfDp1KFFecxB/dASA5MiCNiMb+UfakV1wv14vUNM
x2szR10JXplzalDSfaccjNHNVDY4s8xJFSqCm5EZQkKveIycnwrnoh45gDR54FvOndzsvqZmJZdO
tM9gS2gtgRpgEEQASBfEl4dujWL3+ExxlNQwIKA5aJCg/P6QJHYlkbaezDsaE6G1H42jUeJBQGtt
mCZgLK3Tb9IthijvzNwSmqrHPOs4gjXDv/AaupECL3nGJCfT+20V42jCIXQDOa2dWGngxjEQckvf
b+cMhm/ACS0q09452kaCDEdNK/SwB1iOkymdP3hnZIYLVNn/8sHPE5VgD2bbo8fj0JWIbLC/IRBi
ESfNOXm83RlaOecoQE8nmXFC8kp4Rw6tkUKEax8w26inzOrIzHgwTpgVHA3G9AIj+vqh5jQjUgz6
AOV3GB8yWHWo1RvtNtGS+EzLkO1PXk473YD9r0a88VEchbWzs5EKZbwlluYm1W+uNqV6cFyc9bjP
qtGsKEPwZA2jV4Cg+1ZsASKPOKGIH6A74u70WleANIkBVSkaaym7IautsOkr07zSmfsU0UKfq5xN
qUFXxZ2enxk1VNA0GUePskaZwM4NqKbep2+9M2iDWjIN/uKEjM6JwHNWhqmT634H6b5wRO0xZqUv
QevE7f2F0UP6rnky1bTTMCU0MFQl8doARuuxI5L/b00Ve9xO6XPapqp11Gxk3bMjk/9NR+kJR+Qy
/6pt8iFoRuDIfGBc1Ilomk+DZA7ZrhCrVBqw3qxeQuAg+O1MuIKRKvI3OcEP2BMM0z1u3Ub6yO00
AGY3WzjbMBX5S4lI1Sv184INkGDAqbTzy6LI4dWvvp19m4uinNrvgKOiyG3/aflrSBfbW7JLImQZ
4SBR/UOUS6jLiE7F8RWXwhwYdlqdP7jUuM1Ni3eVOiMOWfnO+0bDxLMNGhDMp06iN1WpNfwhkOJS
4ZE/68rZaxzofzcs/0IECFAnWmxOlw3rPIQFpjZeKGJ7eNVdErfJgq4W6qOxv52DGq7oI/9qjPDR
OtH0V+0+xe+Mqj+ZHzP0etIPj32xq/3YTmRd3SmfvEEoUBjLSPmTfUb6fm2rvbTw602z0zepAPiE
fyUAQvdiUNEP5jq6MfE2GfuLVSQepLQKcw1VmKUgknInjBBw+ijE0S77GbJBfKHTEPNhCtNeIy7Z
Ca+I4MiylejhF6qEceNTbPIPGx+vLkYDytNb5kQIsGqLR2Es4mAi3GRkqWXP604mH6qPI1CaiRTa
JuX3LwE3JGcn3568AiPrHwEqcJkg4sC3Q8zjjaPlyshBHiA3n6FZbnCDOrjzsKYnKpH1Nhs/e2bP
2gPznWcRfTEjqvsuZeqphrDzjqxqOQon/bPL4qSuKZzYhc2UMCpvcKYevCKM7lClk6luvd94JAhV
at+yb9eVXS0v/TDNrb0a1BW9Jb+Vpr3HSkYP61O+IGpN4gtra+wkliRblrxX8Yv5gPqYC2KC7x5I
lzNnJxdcU52D68XLSThFpMymAvQubVnWinc9yZz3bt6+77ZzSApEz27T0J4Yg2Xgpqj5KBNAk7+J
i7IDYUG8vgEUoL89saW9h9WrOhveDHBBsL/x82Z2BB8Zw2UTbaA/XJq2KE/2EUHDtzPzSLLRKEZ/
9m0fDEnYkZX1TdanAFASZf/QOQwOtomjTn01WqngXwE3UQpwuIg08J8BHdyxMRy07Lpf+UKUcuPu
vNqB+jeR+otYOas3v/w8LYIrdZIqS+xwYAncF2LeZKZRoeFUcWO48fmXYdP4v74xEbPpgMA6FLcd
r99DHc0qhXPz1/D6A8sxtxYIZz3lc3ProuWsB59R2alrRPnlvOIrBrsTEcYvWm+4RLId6n2EuKo7
Atmsdr785nm610MzsX7u7rEOV0E89JVFQXj0/CAUw6NkLSKS27TdPo3vPiF+N0bCLDkr3QJD3uZc
vaRN8zfHNMsgBZNE/NI3tvjRvzUWSbi9bUscoV1n2XhstnHNXaTXAuO1bsZpxm+E/Fpl7r9OG140
y8itpAJCvnalZcl5OD7+TOQqwSP+L5MEovphk5Nfc4WvpoSbhl7cPuoXtZu6MplwcX7gdp2NfNKd
TYSX0lZiXXXgzYWJfrRBbp7kzIwFGGSPNVWKG+qsu4sF+kqznlc0C4Jio4iZt3HsQCm87abVOWXj
93BTYZ37mQu0394j6qzwN4lbXiNGjo1lnXr/2LfNqVux6W8eDDseYSYnxcKfeaQp1hhjZxASHauP
StkTr9dma1IoJ7C7+w/NIP8DZE/HKbCiGJOikO3b8P/fVjig8NptbYYrgULP9rTNhAsT1iIyIHBF
XEcCHJj+pEdMUZRv/epRpU8CIwZTo4v8KZFVO9ZjG5DS3Qty+XNX9ShiDvw8iDmo81Mae1WYTPAr
/FmHsx42D/Vp2xKSlZL97ZCZmDQRMRhcAS/h0GDYyeemHQnHRv86r51+v9j0YIYmft3j6tAnK/kg
72QhvuDXGKg5NBKq2AsoegBWUFniXjjXA0nfelXW2hCKB12xNvAL//EV8Z0V1c4R5Sg3l2urVBu2
tIx2Of72WdQx76xSgngOc2LdPuI3Pdsn8dI2FAPNQCzS4OiDU4LCLJGOm4cT4HflAUjBcPx6dTeK
qyS0DzdiVgIYhmWWOg1Z53JEcaJXx3rwb0ce0X2ypx4y2ph9MlNnukf1ZdI/g+4k2XySeOoCSIHq
vYjMIbHoFmzdYmRWwhX5W/0bOTAaLMepUi8w5AsdQBFjKOfxZdD+NTlRI2BZHZUsMHw45bmvwkyy
Mm2wx7M1BXqey7sDNnuPrP6Z8IN62g+IBBAVGZy6ApqnmABjvBIpe25efwflrQHjR4NiUYBCvuj/
Gg9PjnvR3mPRjeNE08LWzceNDP5YIOnUp1clJ/LUVdIM+U6RYdsFuyosFASscoSi8QYrrhH9Bhfh
bEICg4+wmhz0f0M0ebw6Z/vUNokkI6eZXshNun1Lxjgu2NFynk19GcVBA7SseOd/zh27t6R3S0ax
0GjPj4brRtUFyu8JgJ8f655SaQ1Ew8a7FMpfSNIU8MgS4FOEu0AjPtbDqI+5r4Luoo+QEi4smeV4
kPUuZNxvMc/TkUL+EOHyhtkdYw1yw5ZV6VE77A/5/gCkOymRPvrsv07P2yOUHsHfLKJZyjZQV4yZ
C8Qy0YSioJYc2HYf9g2XzNItSrWxysBLuInHyhV9UlM5gskZYc1rSQvCTQUJCLSQoerwC0UByOuV
HlxxiLqSrUmQEXf439hqNV0J4FnCvLUnhUIJwoSkgfarQO+7tjmSApi/sN8rLC6B3I/iT73n0duR
D30k4SxxkCgTgaIucmxww+pzkOQTyEjrlRSOD57W53Jv+LuyYTaxOwMYzH90BZ0RQgFNLaPVxq51
RI+T8N7qA3TpaLl638p9WTSMPK4+wtete6Sof7Icic3EjmpOctb/IEZ+CISxUk1/KikU+JF3tW1W
8KtXSaSidE3He6rZ+Pl1tYmgU4ceH3Tet5rl6D8poTQnvuLJnap4dHdLe/eX1Vmvr41Uz+Dgaz4y
KxFEUDUz00YhuUO0B0WaNz2M6z2Ftv8zju/V3+8F0O5c+BVFCAcV/+wDF0CD21vvYLJZymw6GSx4
8HyaUIDmchf2QhIPJs0g/l7JWhf1voP24Uwq7r6+xbCB7GIOqPxBsf8d+CJdo1L+TOoXVkYNNCjD
CYD5eL2UBTdeyfgL2G0yscyEnM/lNwSrHvas8Mu7oc+d5enJz1Wq1SWx6Xldil3TLwS0Ou58e3j2
Kt5iaJyNBg8sVoaDIBkVfH6TkNilZ3xqf9GZnwrdts9hAVOz6vzxQ1aiMoMU5Gk18JTiZUEEvFOh
iCExxmCQzZSF2jTBv7I24svE4Ypo+62MytBjM53RBFtw6RNsJ+VKPwDr34ahep6QfvgSv7888lwK
BZn0XWpis/sZstVtMMgqZ7lnV176fSARQTEKEV9lplDetwLnJabTRV4OLWTdl2T7rZDumMG2+Ijs
E/3QsmV3xQgTZogUR/i2/ffciU/O/pILukQbq0qcu+3EzzHwYT4GsntFO+TQkq9b0VJ6U9wDmpk9
nX52pqSggl8oRsRUO4OgEEGRZOxQhjXIC0JuLGa8yamUM6ProZBqkXP51hHjCnhe6Ixk3koSqPad
J2gkaK2vGcZprHQm/eEFsfudcj7VQgXN1zAigyA7d24bv6nH+QmpmfUCKF5hCzFzJhoEfjL2QNJA
BP1+ylAR3qiRxr7Kf97Erp/bGkLVvXqZSAQLqtzkyBKUow6ltMBq9R4wf1Ti652NAnopaxE2BCFq
27pPskAxbdJ8qaHWb5IOxsPjvqCTyWoKW5UY8eE1ItLQXnMwahCJi57XA5trhpcnfxqIEZFzIZ7S
XmT/k1Rxjm5GXkQi9EknSasIfLaCEniCJ4gL3W0pyH82AOy4yJvaOq4BVJ3ImdQNaQ9ozKrcbTK5
oeWUoiDE5FjH8sBt/qU/DVK2DPzi1y6D67hJ131t3b+G6VK5OutFM3voTNc5r7UyewnWEma7ueHZ
Q5Cz7VbLbiBLmie/OS4Pr9voEri8xTVcYWvnU3NGLBLtUlCxlxyT0nJ0KfHsu2JA1dnAQ0WkBDvw
NgI7YGi33euXKMkAZKVPidGcNIzKEKHkyYXI/Gl9mRKlHYfYuOJ39n6ds/CqRlCvQUKaqmrbPzZr
5kdmPVlOfQ9e7XEDJI198X9lzhh09fL9cKJTCmSxRVGz8nLs5TdxtMosSmYXRBkOywxhw5VBq51t
LUN2KQMQmbnoiQvV2bJmbl5jFtII0aoJrkkM8rPR13lutmfBy+zhXhKOdB4D6uzPdNBKSbfT/N/+
Wv0lXzvDVbmfs7qzdxG1lnWy5vzDP4yqh1KE/u4okvk8QyI9x+ix25DpouSUO1Hi/g4Dt5W89UW6
WSiaV2iMB4buLVpOz9+GkF3k2RfCrSpQa5K6e61H0nY+0QY1acmXezlHde2xrseRmUejPXulk9bx
kS4ASctD8PgeBQ185E6KVG8B2cKEE+dGRGi0IGAx93F4BCvWuBf/6r/DF14KYzHU3gwoSXvhz36s
9FP578Jlnkq5GXfdMJwA4C0baY3rKcHyHIRTcvDxrscTqWnFR4pmbHzARTrHfG1P8qLgJU2YFlst
N2Nf9ZRGQ8w7GyskkKmwEvw2x/HzZGsp53aKSCMlvr3Fl4QMOY4p3eax2+2tYAD/MRvTnDhY6vCP
StUUD569IX74bYULbLxFpEEmshFFPV2ZacI5XKXMabFRwUUBkOaCYRLF3MsB6IZEFY0a77jinnNw
Th/66VTpam74Kg38bCy5e88iLriZoKRVmAH74Q84dQ7LxSJ3xaBvSG8q14hmbtTzzcaaGYAiSoD4
AXmaSrWAhD2P1lvURojKUROZqhRIwrD1OU2i4ZhmuoMNndmyqm7xqWRT2yUVKYMd1XYm3XKOmYt7
vY8qEhRVmavsn+wo70benIjynOXbK2BOEBt8ygAWSre5DgR8UH+n2DtsDO/LYWXrf9i0U8KgrFgV
AgeyEBE34/kGDhEKpl2GWvFesg4dUv5IyZbpQ4C5jeqtB0G+EhvQoeBiUQQbS+Btm5U/i9Q16d4Z
ct8AXu+0Jjj96YQ9F8NMCDS6+AlKmjRYAh+87yWK0ZqR/wcMNyPvxL05GCcQYjsjbyXL2E6sHKMZ
eihayNygkx05JoVQZbDzJ2433g+w6UuzGheKf+9owIKWWYh3g6EnIOSq17RMUveVnqVSI5KkKo05
IEAmR/d0CRY4erlR5c6NWwcISxAP5GwsVIutx+0TWKiwqIdxw3FzaP0giwz6GKiJMfGvDj8ByoHq
4uyVtJgNcypCSTdQGMgogoCs1WmJCebb0xdS305K62jPl6YDDc1E
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
b51+hsnCybOdW1OE0ZcOlRhAV5kZ1Ru6+rRHLVNiISiIMtbIecpfGSDxsvxDvBtRLTt1wvyiHBK5
7E0cw3IkmA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Iz6+AbbgStYdCBB//4ZAV1DrKpjt103liCPpm1WQ9eWto6sfvqtgzJcOysKq1XHDVtSLp/vI6Nsw
R6YiVdMHTqkkhlUvFaA51/b2yf2dIYmYlbInMzEdGQ646MC1SLcz3swvTa/d6M1O0CxqaPF3TXV0
+R2xA9w5M1gJQZHx7ac=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
3YdzUWjUsJk+gTCRXSXb+KrNLT7ZgZ0yFfe2sGRg6JuapbTIeGQK8WhDXRYDHOJDYflYxj0I59Iw
fgJ6VVuAusorBYKu9IRr+Lw6xSw7qd0E8aZ0FYCJ3lyBSHkO2zP8PBn6RXnSISQsNBmcsggDKv69
vd1ct+wICRJh5hdyFug2ySeMQfY08sc1j5NszllNujg2b1/gLTZyI8oLz07gNfrmVOUtYxweKY6v
1WtxRwBpMlhFAmQIZF4q7YgmYTKYYhW4ydy+g8a/Pruwdjm8+5G7E2EQ2Io6TFpwsFEfGe8Uiyeu
890ukUf3R/lzITUpdwUTR+iiZ+369jfaD/66JQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
tu0ozJYZNTiJI8TIF5xT+fCx6WyGK3aLHTT3T5DGA+cmNW/owfUc4iPf1lYkX8ZVg+MdjFUvIZWA
oc/dA/rq28JEujWkZKnTQCF2ygpvrwPwwHqsLPJ3Cdqtigu0/2/n1FckHeT19r1D4hvrNQmpVByS
522RznRpWkKwAEBO31o=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
AfjKebprRhmjOzGs7RV5SXCXT/zlmn+BaqMqubBZr3XmBpXqm0npT+dDd4QZsAhfSPlWpthTZjri
Xpg74EyTiyUXwG7DFRK+OpW1ako730rMOZUWf2i3dqqnZSyJ+5ecUEdz4pXGR69gs6O1X2+qjyiD
LHrH993UsKiz5iLGZ5aEdngffoCeMKEXNifXLtb2svPW8jfHluro9oekY2nHcxAeXLHEjcLXnKFq
4xNFWDOj8NUxpiZPRAL6LFi33O5DirX6BjCTPskNnad3o+AuypLLQUESNpbaPGjSestJqFh+YXRj
M4eqyUwHK2LayEbO9KyZ5R9c5GTjUEHZ1fACbg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13776)
`protect data_block
qQSJpuiE9ypyXSTue9xr8FIVBHob4wpWABrOmcx32WIH3+v8WOIl2PiiTpA8vJp700nD8NOckAdQ
LQSbda7GjTBhwvxAVb0ogaA+zrFLRZMC1rEEuZXbS6vQl8FDS2x9QKqcCE0nQiDmAMI5rU+m4nJ5
8IBwLl6WOC14uKucse/XDWGXa13dy2L7XhBxEYRMXIoYkgGLk3d2Ws1831AUHCnbPgCjFKdcB+eO
f8PMlmqoblynD6VM6bb8KAF8VFSnuoTZ1WrC5rJeRiuUSlv/Pb1nUpgb4TO4KP4oOlVPzBRaK6c0
Rmov4xwJPv7yr7vVlEC5tqDxq4mN+Rh3Qsp3nRGhx2X2tf10CwdgQ552TJNVB9fZ+ap32UvN67wv
QogMHJdh7ofxnZXPq2SI9VxyhCQBJWYDepvOdNkaMex5zjPtBCITKReQLsWxCxJy6ZCwxAafJ3P6
gXvqk+9MkHKfWhzdEhd5OV8sKeJfO5kwr85tePhqhtYUrhFqi7jnsRpVywqCjHAutKjQKeBcoMEI
cfWI7Li36vqHa7IKVTCvtlB3XKkk9cesqXMxRAWnuS0sEx0mt7iw0Rmdbajnp3I7W2OCQfmX9rmi
CNZwPEqp7ytD+hlaJfHpG+5ncukOgybISmTdt8/ziqyr/+bKbCTNs2SzjKB7IXDMPAoKOwdvxT3v
qRN1O07lrbL2OcD64P+JEoHBMb+BT3M6AhDOxfPIvXh/eYj3gfFvd9158K6WCR+W/oRPN+PpgCEA
zNXQoD6ZRMR/VloDcgZxFVImeJKjViEP4pbBryP+Y9ToE2HSFwKyDcWQvswOKX3yd7lQDt50Ki6E
oBYUxFa+uogUmz/zhihKLjf8ecQeaMRcmmViDdY439A4dfQYDQFyRa/6VrGg5MsVBx8f+hCrRy85
iIv/h6m9jYk5n3k63/8gnFjChs+QxYy03+1Ft9q3NoRRDQiheVSQfVSHn+jiEyWyIKdxhRX5RCLd
1cCgQUNrtUvoUxmhp1ZZTV5judJtSRaWS4ymkDTogAuzytKbOtW8DSnXNNDOe2fosL3L8+MzLmgz
LBOihjzut8u6eXOodufe5ohMhwdTKj1DioUR/Jwx+raab3GhkEMjeTMY5Jylcip40t3cxtvUq46Q
T4OrR6TBaSDgicQj4vlKfN+f7ey1uhnw+Ad0LT3t9RI8/HUIecKxxDj5SE+AdC7JsqOGhNjFhl+m
/fiv74t3RV4RzkB4/GpcODKXm90ZW+BDBRphL69ozCi4Pt4gTFR858fcEHRyPePZck2HoHAYn0YF
adZN0habXKEhnYCG+cyS9Bt9y06A/5ppCI4fg63MZnrtmkIFldmQcxljN6v8O+QpIetfkYQiUFOg
1Qz35Cc20FdJp9jmQt4QpBHn2eZpgadKBDvjKIlCBFCtRGXntKU/zx4lzKFh9sjJFlDfdBbjHPb6
+FuWJdiHabu1cKN6D83LYLEym08kbQALPCO+qbg/uFtKpieIbpjxUlu1D6jn/JYlQhK6e4o/T0ox
nvLVKiSTyTlvXcZnwWdH2lkJcdRpcn3BVv0VIA+OgjG4FZg5ilpp2FjS1/SU3QbsIWLONHGXb9Op
b3D6V4RSO5GkKSQT8qmSa9cwN9nmM1CIiJW/gQEYeHFJIMN/ENOEZgB1SFHCHmb+FOaQ/B7rVt/Z
+LB3mvLCrwt+sB674Nw1G5v1StCTbQMGiC3fLyReOUqkLjlQEFnugNuLTsJVQY4xna8tdK/GKwVs
3HSB+LWU2/7xCU1+44W2bRbl7VbE7HG46AttryDEDSoZDI3jUX3BC7UuzneKP0MHPivRiTw6ls1h
acuAdLjldEV9JuUUuD9sGb4e1ySe1UtTwtPo0eRFpKKj8HstiFr20MYU8/K0Xju0D6rRPUWbxbj9
8EvEbukkthZeDqoqfPODkummbiykq0J9pR8xTKL/8cRSNkidFhSX5tqgtcNd9Uc5Bds0YeTXUYPF
pvNvMDaiEMBddMdsaCH5wD5DkUjTmLWfkixxISC8p0bP8Iei07xwtVZb1EJGM+UEBq73u7lr2hT4
NIb8Q9d3mH4cNCvfNsK9MlVN1e4v70jt6rLUx3zzDyyH0Tu8fMCx8RHJg4etYmkxu9l3hiu2j7f3
/IKwW9talUGtI7+M+0MJCcPhnbGA+MinV7KwhN+Cj3zeWV9DDwCGrtaYd2k0LjeB7WUurafun3BB
aS4bYEXvNn8yfaEo4LNcmHBRmX6QIgm3802fxarlWMobcQTxlrTz0xgslFcsXtixqLBR/fPA89FQ
Sl6N6ik6R3wWhpqfJ399I9BBjNYtAsIyaT+D8WBAeCM7c3q4xH7sZ1S4BNV1dQU1fr20zwrvEpz2
qXxi5SPP1R0DDcBmX6DqwvB26bg8rBTPZWV1MT/lbLwleY34M07Ln8NHJJuo+KiW8fBkLPb8lJ6t
9MC4h4ZFp/ZN0gy27DUwu10QjvzadOEodK5eokP7V6eNKkIlDi5okdzr3TOSsFttQ0gZXh01ZUeA
NLJlkqzxFPzqzyw5H7rX7orCRWqBRfkGH+48ovqSc/+Y5f2kXg3OfSUtOlbeJggLUfHBuajRMkhm
C331lLXYCizLqCAnk8r3HHJx1RuZZqqBEU9n8RpEEBrCKeUoqRd60A459rxp3SYLuhuVnXm8v+e3
fT6mqvH6GH0ESE0s/uJWB5NCcOQ4UgvncVIw5Z6qSHJ7PhvzMqrpoUeADSs28EJ/gtx3c2bNfaqC
mKEQLnoWhfI2ECzgQoLEzUlo3k+Yyshs0TSrwo2keGuVpT7WOFR/A9gVtip98+BaYLRY6/cGLlq9
CwXkR9KyoiRNtnzSkySubqxhRkIHuPr2All6fDamG3WvmdZmCHa7ztiVWV6ZTqTL2gBcOQ53OuGP
E1UMQdAAIGx7usPaHIMw0QPrvMcLV2nEF49k2h8Z5GINRydyTiWWh4rC/ROSWqCxTy+to7QVpcwK
5JScf5Uw0lXlFVTIvnOeQq/+iy4dyDnu6TKiKkL22c3El5FflImM+bLArW8tjxr96kw5t4Ch1y7S
nQUqr5mvfkV19Bs/6UF8e01xxhDiMPc0Yq1WBaOmi3q02FVIlwWzqfdluYI7N7MLJd/Av/OAkCZv
nYfPWXY3P1Jkh3ODA3CY599Y08dDAyR/XEvrXFze9zcgxK8tuRulES0QjgqlOYt+dNkgizfdYVSV
VyXWwORapmHRg0AWxTxvSED0FTvjvB12wA188mgnYLxwggmFWMcSPkGzNS1jR2aousciyYObp+AM
Vcwipw90+ARMUxs3cZRtNmlAaRspLtsnArqUrOR2ThUz8hki1vU4Dxx8qEQnu6dEd96UExb1V0Xz
SgqWFXoW6eJmPe/NqTrtnUQr/WCNvQuruxttVIKQ3epmp6L8Anng8v6oyqYgqDEEpRf2UMPoxwvG
jK6r/ice2I9x+ObZhpw6N/9Wjo9lxTWtNQK6Lr5qkNby8FgcnzuyvDuXxJuX11H+1mnbS1HXHJlD
Z9MM97OBVnxEFdmos5kkGYyvoemB5gjZjV5B+8eVWx0GfJCMR7eGpVLeRIppqZejYRCYm4+JJZ/g
ReYkWSIFV8YegST4BojW/onGASnBmOs2Lih2ufMC9+RAJ0XPcZ/TF4ndy6JL5gK/KG2YVPkWIkCk
kiePoB+i2fcIJnScm0yvmtyIS2HVzQFlFnAj7UB9Le77hRgD1KEY4LQyVF1syG6+H61doH0YBEiZ
+79Fsrm8r151u6UHa14/PbFDAU13bnmhGbyxPovTOciqq5BjzbqfidKi4b98muUrJQaqzByYRsTF
OXg0XBrt+GVgvHDoy4HTJZOjwBYJANDLrbzeh1xATikOWeA7oqOIxMOM29112X/tSIY2EM6wMsZr
jJZypS1fW4MAZCrsrYH7QuQUycCLYFPZ7w2DPI7EZqP8O3Q/XCH31F8MOea/LvXMozROsMBjnGDj
Gmkl77ISkHm3IOd4CVmVJdvwYY6GrCNfahhpEDfFPTkLXuCQbn1O7mq6yRcbu4ROkjsdu3pldLc0
S0dnFSnfmi+4BncR1KacEQUzn7JWgc8YcvtgDXi8tTihP9qSfdaX+9k2WHh89PN/bpheqPYGM5Ow
Shf96A+qzO4MYhXvKqAdef9Tf6McmcfbjJRtsuJ9zAbRBth+tgYUk/VQJlnl4hc8oqI/bdgEuudv
WpHxY62VWL3RnGEYLhpKD7kIonPiRtxfAtw8oYzobR9wdWwvPP2siIwAzB6PzQjLbUkatcmVgk1g
mz3TLXXM2VkTVIaxVkB2owBkgcatGi8R3VVhOIFDbAdqZhRCjvJgeKJIw0Bfz8JJ2Q/rami6Ax64
z16UQo8h4j/Y/L3Ra0plXa66FmBF4/1iLzqUvhNmsSnhB8EmElJFWUUchTQaX7KdTfGdfVbOyoE4
EpisRHGcZ1/CYLqKWstxgQCbupIM/sM3AmKVb5V9vfdjySPvuJsGrjbSXuT+SjP+Lm+Y1QmSWFUF
GznK3M1HNjerNH2UZPQo+alIq57fCDzD37e0OE/C6Z8uPqrOovwG5NfVtmiB4lxVcDCT7dBwHmRO
dIF2ErXEv7ByT2orZtRayV9hu8GWIF3UpDC5r+CTDKWo2j6fsJXwCdrgOzwRZAtmlMqSQD+zJTFk
4w9b2QpvxnynlM1yw7cbNHPr7cmoCTUYQWDuosQeMXBPi1JUuPJYHuzcB6n+4ifQb/Sy89XVHBIR
PKR1b2k+ZCM9xyS8hBRoKLrzktPAAq14EVSxIrSqTCqOtWdXADHuDO+aN22hstyXSDgEuey7eN4t
KToWrybn7iU7o0UuVQ5OElzsGBYMufFcKoxQUTBCPt8uXeioWmYdJLW2AvqFeokcsk/8ucTgPjxN
6ng7XuxxQAu13aSP2p4ToYamTryPS96HLPY3PUQ3O5vwyCgZjGnhuHlOVJGc+9n955a9DHjOK8HS
OGwPi5J3TnVNfjQOCtemjGWxgff9bk++maxUz3Yo/QA1RMt8SF/VQP7yRCzgXetkaCFYVJOd1Zt0
rskvd7iqvHUjVw77OszgIyM369qjVx4A3kIPqYj5RHAzh709QwEC6rF8lN1ba8drx/vHbLLg2UL+
V/XtzV531fTdq2x6PODtmj7B4KVAdYBgHniCrwUOpXz3qG5RA2rRXfrLygBhemuD4UPVGiuMlnLx
9/tTZRa3xvdzM2MUj6VwBdGT22dfLN2H9rdV2bWr6fEeDt0VSnZ+NrjgeEr3bw1pEG8ZsFQjBTVQ
r9Bm0pmvvzywShrlTy/YqGshxka+YO4+VAGT/c8WcTYPhHSKYcxVGh8xIWouF2z0D9f1DkpfYBrt
gR4khkkapOh9Tj2jr1lAgfomPd8vDz3hY84YZeTUeSYoUFgzIewL+yIrj1/mZUhsGDSfMnYoxfBu
kUliTrgyEYGkMgCo0UPyAU9+OVGh+2yGlu1pdrXHHHvsN8FcoSig3SWJaG73s1p2CcQhUSYvxZGa
LU9PIjQZ1PcnJM1dyTsubWARjKlg2Da5WL0/hG7/RVrAb6J7P3Ws8zng+mrRS+RlpJn/7iOyK21O
MDmqQ+RO3Dc3abMgLqeptZ4YXD56cTTeq3yzYMKLVX+3ZcIGMfTvBABPivc7Ajod/dY5EPwEeB81
/QhS6fNfnlydTPNudP1+FRn7ihqJEup2PzBLLNzxlWYaGF4tDSieF451DjiDXV4653vawCYqFCi5
JLG6gyl1pU2fGD2SDByv07h4dIn3XGjEE2LSHznpx7flkqcl9sXovIJzDFEXkwSiTuvX0odx3tcK
cIWbTfK/yj4C/cneD2yxNCqecRPodVy+2R/xU2n912rtU/o2cW0QWjwa68oEQbina8vi/NGNWQpe
7wbNrIwIbAy4UJKRlxQvhQ99nSV74ZFC4x5UXgLJMw1dDNV9+rOXawjJefx1NVr3wLzvKauOmAQ2
xpdbUG7BSWDkrljmyYwHQpabOFnzZpy4+JkSVoRPaKp6RMR2KiJDrIqxJJ+/yk5Axs6XXHlY7HAq
h0Sal+AChNzO2zSp3fl4Mz+oI9d0Nu+xk0kH1jiL4A1Xzbce2YkS2SNCPFy6L3j0DY2Tqk0rEGQV
zUgx6utIs8wNxvp5aV+1LSjzFiJGB/lULZ6hxZq7PUJNo9XxgdcIoL9rAfXueamiRNykHXswS3OU
OgsAaMu0ajYZvy+fZTBPBImuFTzqqdGByOhZ0rwk/hTxhzvLT3F0IF6IB8E4ir1oHLXD8J/+GGER
ZdMyt2BPuiYdjhrUhX0z8Qx6XMzZCRl1TkjBH9j8FaLKOAls4DTOHDohscRwkBfP2uoXws9vPqvi
r4VKQc7V0f6IlqZRWp1APaTN2if+tJ92tLFrgNEGU0vpIR7b5TwHPwNV5Qy9eodHcqqOrlwN3RAa
1GnVV1QWSftqlHn5oQmjj6/ePfujIICrEW2EQsKG3hTaPtiS1ZI7+266D7QeS1X2HlpA79EoOVTJ
vF1UL7DFOJ277603npFv6LoT1zmGUU3wgoJVNw9YlES5lxA5jgkAzkEA+GDMYL/8VJ9gxuIW37hA
R/unD2sW3nRGsWLk+87ho9jG1x+eg0n02jRB461C7ZJVNA4TuvY4B/JuTGBNYRSWG0zbxmmb4IuO
L1hMp8JTOuFCErgNGZSWNC0jFLj38g2ySLkk212enZf12qBfKilndeumepkXNGQW50g9akoo0SJ0
/RN4FgTgeuG6z9u0IaUr7txKtiXd73qWMLHhpArOkpfK0u45Nkl5NpgitW1OzsPZKOq83YoWRqo3
qXg0vjIMSLiWqdKBDehehsUIH46Ie1G73dkPHYB9pte/Yd2PL96k5TXriZd1iE8Op4mIC3p/fhKo
NROwC9HjWBkGMuwq3w0d1wRcLXR5A/2vYQJS24OVA28apnuO/3hrsPiZmT6+8rIDF2Kbj1Me0DA6
2OGF3mAy9w3MxP404yfoZ8CYgoYN7QqNpbO8wui6wnuNnX5gcv5GgiM8RLHK/UveNeqfDrb4i/be
LMHQ+VhEkktEr+itxQ3jiVHlPjZxsLhiQT/CRObfVSbAKrW350yUC09eqRFXNH/BwwNTKdPgXi2e
E9vnfv1x/Lh3d2hUW8OUuxM7WBmmPMEdVuQy3SKXUJJEk+ceMFqNLZj9mA7LpLTYxFZXOuWfVY4P
JdpDRRhSV2G+5Seiex2BZgwe7avOHToo8j4J445CFXxPVMe7pAmTGGc/sPf7tJW2RX2r7oBAJvXK
Ve2S+ESNp91839qQ81I/2ry2JckKOMjhLKoiICa9XQeoxZzMVhslF2RzoGDJEEY97Eyytb56yzUH
HzEQCHZUkGc4FqfLLB+NQuDmpkAh6pgFks5GNupTqFVbBcX4XN4aXzcWzXLXtwgL8FAMwoUVLCgM
JAqLKpuAqhWc56Jp8xc5cEizPq3x9+ILae7frQPmk6JvvB0v/9FODtA+rnS6r40wWbxz5vlaHuo5
aUkUJe33GqSDN8ciRYfbto74b92POWbQAXGTF3mHfmx+xobacyqFbR4QBmZ9jS3/eCz/aK+BDzVh
AO0VX5r040hPoEzKEdE/ThFyhd3v9nfGxrg+6rigStjP4lzp5F8JZo+LFq1vYBN4RQstTvZeNG5U
zjrn1m+cnt/o0IiPUSTwjJrHrArFVyBt22t2VnbzXbcXTVmDkjqQ6dhlVqyb7UKA5WEKC7mg0atL
NRzGfpR0pXUvHZlpf8V6Ast2Tw9lC2ZNCLl+LwnFA4w6gPPhZnuXxWzD67F80y88KqML2bLNHlhj
sFa/MeYw6AKe4o2GeMZOKyHqLgX6GSIRFNj9JXwtU1f1/+N3QZpDYoDe/BMX16Kw3QbhMpsf2+/H
e4C1wlocebax2toKHEYDbhZTaUtaQ3PAtoO2DJkqr/AFmC5GbYsEB2ijOuTfuj9Dnl1QEyHX2bZD
q+KQba6/J2pFfa1cLMRzci5WtZJa2xq8eO3eJaaGDtEEmdS67+zgyabCPnS3yCvAXsqNIc7KQsOo
sh660pIRF3VxZxAeYqS1HfW3yc7ECik/DTlsYX97efsQ5WPM7aP4E+bgLlEUNwae5OhhLLGxd8Pq
Qnv1fhXAY6Ba88KH5Xg+Sw0nXSoZn4E4Xx8LYjJpMgnJ+yx6IRdsDeapjkUjlnRfbNTieiqji8xF
rqsEpMOn6I4PeGsZCvWaMkK+QkaRcgIDEfzfd+yKQiVbDxvhtEKZcaFrYgpY+18j9u1Kzfn2xkxp
k8LVzgMAjFJEE4JMbLCc4zEyAWPrKMUfyCroYppLedJ/ttNLu5bGbw7/GB3A9Ncn7eiC3efRxcyD
kDDJTUkPNnk46OFPtEExqYPPf1y0a1yH+LF8GJ4AIIlaY+5kXNvio/0qj0mIYP3Una0X0I2df6Io
4jB+fWqPiyUMyF0dxOH/9N3yJZ+5MARHgcqu+Wnd2Ekjj7rBbUoGO6im7D1n/e0PvHDITYuZnYxm
DIxGwHX24dhpRy98qIBq6dDCznbjI1NaLFIxWw3WvvCJmDtPbc1bX953l0QFQTNuBFlUuEuSkgKc
kjZPUFcy7Jw9lRVADX07xyyjc64aSWC/iYuDIFtDkk079w5T88eLej20gw3sQxfRHDlOgc29Wxq4
3obhZIiAseqxE+u5DNH2lUKZXZPHokJw3Z6AgF/87DdJblB98Kyxy8v5IwqPgZKcjOgRXWTO9+UH
RIfDs6eizlhZDmMVrREj4MlO1X+F6tgQ6EC1111N5DDXLpDyPfsP90FcsaHN2wTkFY0Km89GD4UQ
9xzofz4w9BysAmN9T/POuOw0ogjVI29ucDk9h+4oIa+FY0ttQcPcT5v4Hk2VjdUrNEq+C5asKNe4
G5CtYv2fmeMtqmOEcA9VZXnHGboH3y/e4Y8Ks4xjviyqVPdjEGw/DtQb3u6RTwETn7PGGYpFg2ca
f2tCUxPoFulox6U7Pp8jIQveEdnLYWlOSjiOLa5KgyvS+3umXZCQ9Pyx8D2c9KCOMvvg4SAi/Ido
ERjPBLvg/plAo+t8zcL7TpxWSCIjoUMBtuEE/HGNET+5b94QWH1YxxYqjpK+085S9hqRgs1QHm+b
quHYhMroresYD37eXVrI0ZvnywrqntmqrphlPN1MFReAL8JIy2FA3thgB9RsqZ+Vnz1g9plotCTQ
e9IE6KagbaR13iIZ5IscxG9e+5IMCOK0Cm3y/lRRgxCCo/HUBbw63gnt6jCoIBZOWQtBgRG51dEK
4K4jFVLBCbv3ppV9t1lShgpUXSHWZeLwnqyssxbCODqoUhjVS1rBym2MRHKz1pCpLUqWHwFEwE3s
QeuvBFt2qti7uUDhFu5BCtYBCZx+npTLTjCwPSsv80vmmt0Tu4048uyOpw0eRepVsmUwFKfgXfhP
IFb2vNClQoiJEQa9KoCYV6aY3v48UdbV9CM9W4lZ3P0cteFa6cu2HdgI6C8+QQlAg6RaOkOdDCq+
D8KfXZlXWpIdaeLkLq1zYC4q0pSQQHrK9wzQDUDPVFn1mHiZWc2eGbQfGHnylFL8gSJ7Gq/9rKUZ
07NHIvBdfhTfUO7DuD9QA4Hjn6jcTC0DCvscy55Muu5z0oM3J12Vbz6MdONQ357tdjMB4m+zGbrm
d77ZlknyNa9XMXzKbACGST2m7bo7q3S7aTlCSn9ZWNoC09f/XQW6cp8RzwhFSpArvKLoyJ2G7sXj
17bqofMB3AAF+5yTID/Cgi35+a2ufGlJP2hRQBpOfd4JZia1lJQyMgpEI/XYoasx3dPMNJchabr7
5my8376O1WbnVq8cN5Zl4Sznw5vzckx1Tl8aRcd/xzICaR36/Z7VeZ7868cENfIEl1mfaooZ2Q8t
/XFDu2apKhIXbn/uYR5P1kEUwx6YoaVhgBKMaJIO3bOjPM6Y94l/v22KMBafa2/6Y99Xxdd0ke6G
Le64hfArT/3TRTl6RC9/pfHxrA6mhKeHFYGWjcMs0W9UlLCIuZr2Tcoolq8JvWbQxo2RZm/KCm5j
OJHdlClipprH8+026XthUX/AOrvxTwenT5Ru45NBdawRnR1lsaLaG0IBkBFN7vj5/qGyg0IFmA3u
go5Ue6osNEWYs5ZZv7dX6jFpCYIpBUxcXQWRjlITZ5XUA709oHrizuhQD+voREUXDGQ22eh1uVbO
1uyJ9kGqANlYJ9dj8sNbX1N0uGmuExmUU2HMDyQV2yVW330C7r+Hv3Vieo4myPK07XUQoPr+zyIY
z543pC9ML7lO3VsIiMAnMyNDvXCahcA5F7eriVzeKbu8eTe+nr2pwUn16awl4v5u5I+V0SIyGROF
fUe/8kdTdblkGssCvnfBUQgjqT0D/bMYmQSFtq04i6bsmKCXq0Qn/ruOCGehOhY8Xv0IN7IN6R1L
iyBeXtHA2zUdRgMOo8oUQ2CoURGY3HLCuLssmVNC9yW+3lzlYwNFAWams8YuV6ZaTdWYL/5STHr8
kkyQzw5HYde+UHsK329wL2GOr3mP4ncuqFsLxvv66MyDZLkWAT4sa0GxhacQ8pu2yqwbQj7E0pNT
sgLJpgT3U6Qww10kfyz3ybledZPqg7bB3UEBm60I2BkDCvpa7VrKVKz08QePNCF2EaCY3/eBSO8J
8rzFBOlByMRcrtIWe7otg1ym3//qfw7Dr1370VinSYEzMqujn5C6bkGZvqyByxwTzSL7W0ioKHRx
xMS0kHWOii/nAguE+RbgVsX0/S3nLn4+kHt77unIB3dGhuD0FMnVC9dNL39BvhXX7rcai1mRx6zS
jBFoPUjJlRVtkWe2TNIJfD6OyOa+ip4XTgAEegogXea/PAHCuxXgV/7yWyMbdHGdX0wcU7Z6xggG
XoR0mIwKiRc8yieqwsVQ93Lml3URTPoev/VklC/aoJVq40vaJtEY9Fxe9x4MfDD5BzmeDKVgwb/k
iBLbSsA2hP8FE03QO6irPRz/RGlZGuE+n4S/rUwRgiCn3dMCEMEl2rqd1dXvpXJb5gOfQocb3N4U
XnrZmDxnCQzBnazkwkoc6UB5xgQnnOBjrDmgt8nSkHf3OGzTZT7tx68Jur0XirII+skGBOM/t7Jf
fGNV+rvA7wD+0Z4UkpFdKwhnFlhR4SrjHRv8JMZg7vyZISMA/MuEVn1sy5HBA915kTKO1BupeYgf
4jiqUTWp8A6YQ3Hjn+chuKKSq1jPBCk1tN3v7PwYSnYsMdlTqzBqr5IHP/Ge0UdnKRynT3MBxoQX
0Vx6fpdnxMaHZrT8171LZmsLhr1xqUyJWMNDvSNzXe77V7kag5D8uBbciFudJwQWqN6fdq377Lx6
XobZDXsXRtYB9IWc4EcU0KzcXdQ1Cx0Kz0xf/KnQFG09ZL6/sO1q9RZC+wl2TOD8OmgNViCriqxA
YHSyfKaZm5ctbjj1LqCraYgaMelXMRGTH0KFfeWL7Q44j/G5nRrOdouz7oaZFxK9dVKgnbD3ythG
wJEduGTtOwnecD2dV+2RBw/s43BGrs7xJXdStK0WEtaJqj+0wTXBpG2J/gj2m0eyY4RiCNIhCB2F
Vaak47mqNAEN4B5YKHLiuLrn/A4Rpo2vNC7Br33RbC5cTrEFIvf4f7DS6rkzVY1sv/doKEbCLXX0
8AhIOdNZHhEcYZEtnRG6rOxADyC8Be1pgbKraSFaGlHXQCGb19azaKhYGx3Fdy9UkAEtU6zW5Oas
eSqGuasQNJHeaydHjETYMjPND2O43yBV1A4Z4x47TPSW7mcI/xznckxyLbLsgLFz8nefiXhcCIw+
cSK1oB3LwVN4BgkiUDlnAiQXGla+jpC5LPlKuXO+dAbgrOGGMqwSDasPFHGX712kmT4qmKjY0V+e
Vf35kWQojmoWsWBhVOweF98sIO/buN7zkHsvxYUZmSm7drgbfr8jzol5OZYlPY8M8x8h7UZOlP19
LlNSBuvylOdSH53vHASKcXjaLUyrBN7095AoUfocyYZ8TerxT5EjyOLfjbVb1MSwxZLNc9z5c5Xs
qkOSa+IzZQksPP9wwJDOoDIjzriBjEyL+S2IRA0FRR8Mi5v3exo7hA3/53WXs6qMWFTOoqVCkfas
fK4Yn+CAl8QnxiDNr4c2V8p6KOikc9bVQtyR7JbpJgdUIsd1NA4g/MVhWFyMSTrEdoKuNS430Rey
GW7LCpgzFp72S0tpTI2SmH+TS6fF0l6tYQzEGgu8APJqCqv8P3Cva2z2no9dMXgQ+uc/5PazXBxX
D3PpFbnbWx5G5t1pd9QRhrAOYLV+IEcnEoZqoQgThMR2eux/Jp5fpbyG9uN5I3pYmVNS4WidpCcN
UthTUg5Pu2MgktlOKnApx3h8CIS/sjTciCe2i3ef6+B1enhNfk5vVBv9rVTrZX1wyjqI9CtbZKx2
XNyfxlhrgM0OpftBoVYPoD8smTYOPrpkHhxVUN5OOTmLkTxwk0wnsf52aPrjyJ+gjpO0zubXUFGQ
ujc+y07iR4D87aq++osqhLcs2fMQtyruWM7XJTrVTz7PhHR0+xZt50fQsSmTEMrGDwO170sju+lx
jKH6dGiluG0HmRcQxRbU4FiTCh9nUlhSYYYwjfDp1KFFecxB/dASA5MiCNiMb+UfakV1wv14vUNM
x2szR10JXplzalDSfaccjNHNVDY4s8xJFSqCm5EZQkKveIycnwrnoh45gDR54FvOndzsvqZmJZdO
tM9gS2gtgRpgEEQASBfEl4dujWL3+ExxlNQwIKA5aJCg/P6QJHYlkbaezDsaE6G1H42jUeJBQGtt
mCZgLK3Tb9IthijvzNwSmqrHPOs4gjXDv/AaupECL3nGJCfT+20V42jCIXQDOa2dWGngxjEQckvf
b+cMhm/ACS0q09452kaCDEdNK/SwB1iOkymdP3hnZIYLVNn/8sHPE5VgD2bbo8fj0JWIbLC/IRBi
ESfNOXm83RlaOecoQE8nmXFC8kp4Rw6tkUKEax8w26inzOrIzHgwTpgVHA3G9AIj+vqh5jQjUgz6
AOV3GB8yWHWo1RvtNtGS+EzLkO1PXk473YD9r0a88VEchbWzs5EKZbwlluYm1W+uNqV6cFyc9bjP
qtGsKEPwZA2jV4Cg+1ZsASKPOKGIH6A74u70WleANIkBVSkaaym7IautsOkr07zSmfsU0UKfq5xN
qUFXxZ2enxk1VNA0GUePskaZwM4NqKbep2+9M2iDWjIN/uKEjM6JwHNWhqmT634H6b5wRO0xZqUv
QevE7f2F0UP6rnky1bTTMCU0MFQl8doARuuxI5L/b00Ve9xO6XPapqp11Gxk3bMjk/9NR+kJR+Qy
/6pt8iFoRuDIfGBc1Ilomk+DZA7ZrhCrVBqw3qxeQuAg+O1MuIKRKvI3OcEP2BMM0z1u3Ub6yO00
AGY3WzjbMBX5S4lI1Sv184INkGDAqbTzy6LI4dWvvp19m4uinNrvgKOiyG3/aflrSBfbW7JLImQZ
4SBR/UOUS6jLiE7F8RWXwhwYdlqdP7jUuM1Ni3eVOiMOWfnO+0bDxLMNGhDMp06iN1WpNfwhkOJS
4ZE/68rZaxzofzcs/0IECFAnWmxOlw3rPIQFpjZeKGJ7eNVdErfJgq4W6qOxv52DGq7oI/9qjPDR
OtH0V+0+xe+Mqj+ZHzP0etIPj32xq/3YTmRd3SmfvEEoUBjLSPmTfUb6fm2rvbTw602z0zepAPiE
fyUAQvdiUNEP5jq6MfE2GfuLVSQepLQKcw1VmKUgknInjBBw+ijE0S77GbJBfKHTEPNhCtNeIy7Z
Ca+I4MiylejhF6qEceNTbPIPGx+vLkYDytNb5kQIsGqLR2Es4mAi3GRkqWXP604mH6qPI1CaiRTa
JuX3LwE3JGcn3568AiPrHwEqcJkg4sC3Q8zjjaPlyshBHiA3n6FZbnCDOrjzsKYnKpH1Nhs/e2bP
2gPznWcRfTEjqvsuZeqphrDzjqxqOQon/bPL4qSuKZzYhc2UMCpvcKYevCKM7lClk6luvd94JAhV
at+yb9eVXS0v/TDNrb0a1BW9Jb+Vpr3HSkYP61O+IGpN4gtra+wkliRblrxX8Yv5gPqYC2KC7x5I
lzNnJxdcU52D68XLSThFpMymAvQubVnWinc9yZz3bt6+77ZzSApEz27T0J4Yg2Xgpqj5KBNAk7+J
i7IDYUG8vgEUoL89saW9h9WrOhveDHBBsL/x82Z2BB8Zw2UTbaA/XJq2KE/2EUHDtzPzSLLRKEZ/
9m0fDEnYkZX1TdanAFASZf/QOQwOtomjTn01WqngXwE3UQpwuIg08J8BHdyxMRy07Lpf+UKUcuPu
vNqB+jeR+otYOas3v/w8LYIrdZIqS+xwYAncF2LeZKZRoeFUcWO48fmXYdP4v74xEbPpgMA6FLcd
r99DHc0qhXPz1/D6A8sxtxYIZz3lc3ProuWsB59R2alrRPnlvOIrBrsTEcYvWm+4RLId6n2EuKo7
Atmsdr785nm610MzsX7u7rEOV0E89JVFQXj0/CAUw6NkLSKS27TdPo3vPiF+N0bCLDkr3QJD3uZc
vaRN8zfHNMsgBZNE/NI3tvjRvzUWSbi9bUscoV1n2XhstnHNXaTXAuO1bsZpxm+E/Fpl7r9OG140
y8itpAJCvnalZcl5OD7+TOQqwSP+L5MEovphk5Nfc4WvpoSbhl7cPuoXtZu6MplwcX7gdp2NfNKd
TYSX0lZiXXXgzYWJfrRBbp7kzIwFGGSPNVWKG+qsu4sF+kqznlc0C4Jio4iZt3HsQCm87abVOWXj
93BTYZ37mQu0394j6qzwN4lbXiNGjo1lnXr/2LfNqVux6W8eDDseYSYnxcKfeaQp1hhjZxASHauP
StkTr9dma1IoJ7C7+w/NIP8DZE/HKbCiGJOikO3b8P/fVjig8NptbYYrgULP9rTNhAsT1iIyIHBF
XEcCHJj+pEdMUZRv/epRpU8CIwZTo4v8KZFVO9ZjG5DS3Qty+XNX9ShiDvw8iDmo81Mae1WYTPAr
/FmHsx42D/Vp2xKSlZL97ZCZmDQRMRhcAS/h0GDYyeemHQnHRv86r51+v9j0YIYmft3j6tAnK/kg
72QhvuDXGKg5NBKq2AsoegBWUFniXjjXA0nfelXW2hCKB12xNvAL//EV8Z0V1c4R5Sg3l2urVBu2
tIx2Of72WdQx76xSgngOc2LdPuI3Pdsn8dI2FAPNQCzS4OiDU4LCLJGOm4cT4HflAUjBcPx6dTeK
qyS0DzdiVgIYhmWWOg1Z53JEcaJXx3rwb0ce0X2ypx4y2ph9MlNnukf1ZdI/g+4k2XySeOoCSIHq
vYjMIbHoFmzdYmRWwhX5W/0bOTAaLMepUi8w5AsdQBFjKOfxZdD+NTlRI2BZHZUsMHw45bmvwkyy
Mm2wx7M1BXqey7sDNnuPrP6Z8IN62g+IBBAVGZy6ApqnmABjvBIpe25efwflrQHjR4NiUYBCvuj/
Gg9PjnvR3mPRjeNE08LWzceNDP5YIOnUp1clJ/LUVdIM+U6RYdsFuyosFASscoSi8QYrrhH9Bhfh
bEICg4+wmhz0f0M0ebw6Z/vUNokkI6eZXshNun1Lxjgu2NFynk19GcVBA7SseOd/zh27t6R3S0ax
0GjPj4brRtUFyu8JgJ8f655SaQ1Ew8a7FMpfSNIU8MgS4FOEu0AjPtbDqI+5r4Luoo+QEi4smeV4
kPUuZNxvMc/TkUL+EOHyhtkdYw1yw5ZV6VE77A/5/gCkOymRPvrsv07P2yOUHsHfLKJZyjZQV4yZ
C8Qy0YSioJYc2HYf9g2XzNItSrWxysBLuInHyhV9UlM5gskZYc1rSQvCTQUJCLSQoerwC0UByOuV
HlxxiLqSrUmQEXf439hqNV0J4FnCvLUnhUIJwoSkgfarQO+7tjmSApi/sN8rLC6B3I/iT73n0duR
D30k4SxxkCgTgaIucmxww+pzkOQTyEjrlRSOD57W53Jv+LuyYTaxOwMYzH90BZ0RQgFNLaPVxq51
RI+T8N7qA3TpaLl638p9WTSMPK4+wtete6Sof7Icic3EjmpOctb/IEZ+CISxUk1/KikU+JF3tW1W
8KtXSaSidE3He6rZ+Pl1tYmgU4ceH3Tet5rl6D8poTQnvuLJnap4dHdLe/eX1Vmvr41Uz+Dgaz4y
KxFEUDUz00YhuUO0B0WaNz2M6z2Ftv8zju/V3+8F0O5c+BVFCAcV/+wDF0CD21vvYLJZymw6GSx4
8HyaUIDmchf2QhIPJs0g/l7JWhf1voP24Uwq7r6+xbCB7GIOqPxBsf8d+CJdo1L+TOoXVkYNNCjD
CYD5eL2UBTdeyfgL2G0yscyEnM/lNwSrHvas8Mu7oc+d5enJz1Wq1SWx6Xldil3TLwS0Ou58e3j2
Kt5iaJyNBg8sVoaDIBkVfH6TkNilZ3xqf9GZnwrdts9hAVOz6vzxQ1aiMoMU5Gk18JTiZUEEvFOh
iCExxmCQzZSF2jTBv7I24svE4Ypo+62MytBjM53RBFtw6RNsJ+VKPwDr34ahep6QfvgSv7888lwK
BZn0XWpis/sZstVtMMgqZ7lnV176fSARQTEKEV9lplDetwLnJabTRV4OLWTdl2T7rZDumMG2+Ijs
E/3QsmV3xQgTZogUR/i2/ffciU/O/pILukQbq0qcu+3EzzHwYT4GsntFO+TQkq9b0VJ6U9wDmpk9
nX52pqSggl8oRsRUO4OgEEGRZOxQhjXIC0JuLGa8yamUM6ProZBqkXP51hHjCnhe6Ixk3koSqPad
J2gkaK2vGcZprHQm/eEFsfudcj7VQgXN1zAigyA7d24bv6nH+QmpmfUCKF5hCzFzJhoEfjL2QNJA
BP1+ylAR3qiRxr7Kf97Erp/bGkLVvXqZSAQLqtzkyBKUow6ltMBq9R4wf1Ti652NAnopaxE2BCFq
27pPskAxbdJ8qaHWb5IOxsPjvqCTyWoKW5UY8eE1ItLQXnMwahCJi57XA5trhpcnfxqIEZFzIZ7S
XmT/k1Rxjm5GXkQi9EknSasIfLaCEniCJ4gL3W0pyH82AOy4yJvaOq4BVJ3ImdQNaQ9ozKrcbTK5
oeWUoiDE5FjH8sBt/qU/DVK2DPzi1y6D67hJ131t3b+G6VK5OutFM3voTNc5r7UyewnWEma7ueHZ
Q5Cz7VbLbiBLmie/OS4Pr9voEri8xTVcYWvnU3NGLBLtUlCxlxyT0nJ0KfHsu2JA1dnAQ0WkBDvw
NgI7YGi33euXKMkAZKVPidGcNIzKEKHkyYXI/Gl9mRKlHYfYuOJ39n6ds/CqRlCvQUKaqmrbPzZr
5kdmPVlOfQ9e7XEDJI198X9lzhh09fL9cKJTCmSxRVGz8nLs5TdxtMosSmYXRBkOywxhw5VBq51t
LUN2KQMQmbnoiQvV2bJmbl5jFtII0aoJrkkM8rPR13lutmfBy+zhXhKOdB4D6uzPdNBKSbfT/N/+
Wv0lXzvDVbmfs7qzdxG1lnWy5vzDP4yqh1KE/u4okvk8QyI9x+ix25DpouSUO1Hi/g4Dt5W89UW6
WSiaV2iMB4buLVpOz9+GkF3k2RfCrSpQa5K6e61H0nY+0QY1acmXezlHde2xrseRmUejPXulk9bx
kS4ASctD8PgeBQ185E6KVG8B2cKEE+dGRGi0IGAx93F4BCvWuBf/6r/DF14KYzHU3gwoSXvhz36s
9FP578Jlnkq5GXfdMJwA4C0baY3rKcHyHIRTcvDxrscTqWnFR4pmbHzARTrHfG1P8qLgJU2YFlst
N2Nf9ZRGQ8w7GyskkKmwEvw2x/HzZGsp53aKSCMlvr3Fl4QMOY4p3eax2+2tYAD/MRvTnDhY6vCP
StUUD569IX74bYULbLxFpEEmshFFPV2ZacI5XKXMabFRwUUBkOaCYRLF3MsB6IZEFY0a77jinnNw
Th/66VTpam74Kg38bCy5e88iLriZoKRVmAH74Q84dQ7LxSJ3xaBvSG8q14hmbtTzzcaaGYAiSoD4
AXmaSrWAhD2P1lvURojKUROZqhRIwrD1OU2i4ZhmuoMNndmyqm7xqWRT2yUVKYMd1XYm3XKOmYt7
vY8qEhRVmavsn+wo70benIjynOXbK2BOEBt8ygAWSre5DgR8UH+n2DtsDO/LYWXrf9i0U8KgrFgV
AgeyEBE34/kGDhEKpl2GWvFesg4dUv5IyZbpQ4C5jeqtB0G+EhvQoeBiUQQbS+Btm5U/i9Q16d4Z
ct8AXu+0Jjj96YQ9F8NMCDS6+AlKmjRYAh+87yWK0ZqR/wcMNyPvxL05GCcQYjsjbyXL2E6sHKMZ
eihayNygkx05JoVQZbDzJ2433g+w6UuzGheKf+9owIKWWYh3g6EnIOSq17RMUveVnqVSI5KkKo05
IEAmR/d0CRY4erlR5c6NWwcISxAP5GwsVIutx+0TWKiwqIdxw3FzaP0giwz6GKiJMfGvDj8ByoHq
4uyVtJgNcypCSTdQGMgogoCs1WmJCebb0xdS305K62jPl6YDDc1E
`protect end_protected
|
-------------------------------------------------------------------------------
--
-- The Wishbone master module.
--
-- $Id: wb_master-c.vhd,v 1.2 2005-06-11 10:16:05 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t48_wb_master_rtl_c0 of t48_wb_master is
for rtl
end for;
end t48_wb_master_rtl_c0;
|
--
-- USB Full-Speed/Hi-Speed Device Controller core - usb_packet.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.USBCore.all;
entity usb_packet is
port (
rst : in std_logic;
clk : in std_logic;
axis_rx_tvalid : in std_logic;
axis_rx_tready : out std_logic;
axis_rx_tlast : in std_logic;
axis_rx_tdata : in std_logic_vector(7 downto 0);
axis_tx_tvalid : out std_logic;
axis_tx_tready : in std_logic;
axis_tx_tlast : out std_logic;
axis_tx_tdata : out std_logic_vector(7 downto 0);
trn_type : out std_logic_vector(1 downto 0);
trn_address : out std_logic_vector(6 downto 0);
trn_endpoint : out std_logic_vector(3 downto 0);
trn_start : out std_logic;
-- DATA0/1/2 MDATA
rx_trn_data_type : out std_logic_vector(1 downto 0);
rx_trn_end : out std_logic;
rx_trn_data : out std_logic_vector(7 downto 0);
rx_trn_valid : out std_logic;
rx_trn_hsk_type : out std_logic_vector(1 downto 0);
rx_trn_hsk_received : out std_logic;
-- 00 - ACK, 10 - NAK, 11 - STALL, 01 - NYET
tx_trn_hsk_type : in std_logic_vector(1 downto 0);
tx_trn_send_hsk : in std_logic;
tx_trn_hsk_sended : out std_logic;
-- DATA0/1/2 MDATA
tx_trn_data_type : in std_logic_vector(1 downto 0);
-- Set tx_trn_data_last to '1' when start for zero packet
tx_trn_data_start : in std_logic;
tx_trn_data : in std_logic_vector(7 downto 0);
tx_trn_data_valid : in std_logic;
tx_trn_data_ready : out std_logic;
tx_trn_data_last : in std_logic;
start_of_frame : out std_logic;
crc_error : out std_logic;
device_address : in std_logic_vector(6 downto 0)
);
end usb_packet;
architecture usb_packet of usb_packet is
type RX_MACHINE is (S_Idle, S_SOF, S_SOFCRC, S_Token, S_TokenCRC, S_Data, S_DataCRC);
type TX_MACHINE is (S_Idle, S_HSK, S_HSK_Wait, S_DataPID, S_Data, S_DataCRC1, S_DataCRC2);
function crc5(data : std_logic_vector) return std_logic_vector is
variable crc : std_logic_vector(4 downto 0);
begin
crc(4) := not ('1' xor data(10) xor data(7) xor data(5) xor data(4) xor data(1) xor data(0));
crc(3) := not ('1' xor data(9) xor data(6) xor data(4) xor data(3) xor data(0));
crc(2) := not ('1' xor data(10) xor data(8) xor data(7) xor data(4) xor data(3) xor data(2) xor data(1) xor data(0));
crc(1) := not ('0' xor data(9) xor data(7) xor data(6) xor data(3) xor data(2) xor data(1) xor data(0));
crc(0) := not ('1' xor data(8) xor data(6) xor data(5) xor data(2) xor data(1) xor data(0));
return crc;
end;
function crc16(d : std_logic_vector; c : std_logic_vector) return std_logic_vector is
variable crc : std_logic_vector(15 downto 0);
begin
crc(0) := d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor c(8) xor c(9) xor c(10) xor c(11) xor c(12) xor c(13) xor c(14) xor c(15);
crc(1) := d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor c(9) xor c(10) xor c(11) xor c(12) xor c(13) xor c(14) xor c(15);
crc(2) := d(6) xor d(7) xor c(8) xor c(9);
crc(3) := d(5) xor d(6) xor c(9) xor c(10);
crc(4) := d(4) xor d(5) xor c(10) xor c(11);
crc(5) := d(3) xor d(4) xor c(11) xor c(12);
crc(6) := d(2) xor d(3) xor c(12) xor c(13);
crc(7) := d(1) xor d(2) xor c(13) xor c(14);
crc(8) := d(0) xor d(1) xor c(0) xor c(14) xor c(15);
crc(9) := d(0) xor c(1) xor c(15);
crc(10) := c(2);
crc(11) := c(3);
crc(12) := c(4);
crc(13) := c(5);
crc(14) := c(6);
crc(15) := d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor c(7) xor c(8) xor c(9) xor c(10) xor c(11) xor c(12) xor c(13) xor c(14) xor c(15);
return crc;
end;
signal rx_state : RX_MACHINE := S_Idle;
signal tx_state : TX_MACHINE := S_Idle;
signal rx_crc5 : std_logic_vector(4 downto 0);
signal rx_pid : std_logic_vector(3 downto 0);
signal rx_counter : std_logic_vector(10 downto 0);
signal token_data : std_logic_vector(10 downto 0);
signal token_crc5 : std_logic_vector(4 downto 0);
signal rx_crc16 : std_logic_vector(15 downto 0);
signal rx_data_crc : std_logic_vector(15 downto 0);
signal tx_crc16 : std_logic_vector(15 downto 0);
signal tx_crc16_r : std_logic_vector(15 downto 0);
signal rx_buf1 : std_logic_vector(7 downto 0);
signal rx_buf2 : std_logic_vector(7 downto 0);
signal tx_zero_packet : std_logic;
begin
RX_COUNT : process(clk) is
begin
if rising_edge(clk) then
if rx_state = S_Idle then
rx_counter <= (others => '0');
elsif axis_rx_tvalid = '1' then
rx_counter <= rx_counter + 1;
end if;
end if;
end process;
DATA_CRC_CALC : process(clk) is
begin
if rising_edge(clk) then
if rx_state = S_Idle then
rx_crc16 <= (others => '1');
elsif rx_state = S_Data and axis_rx_tvalid = '1' and rx_counter > 1 then
rx_crc16 <= crc16(rx_buf1, rx_crc16);
end if;
end if;
end process;
TX_DATA_CRC_CALC : process(clk) is
begin
if rising_edge(clk) then
if tx_state = S_Idle then
tx_crc16 <= (others => '1');
elsif tx_state = S_Data and axis_tx_tready = '1' and tx_trn_data_valid = '1' then
tx_crc16 <= crc16(tx_trn_data, tx_crc16);
end if;
end if;
end process;
rx_trn_data <= rx_buf1;
rx_trn_valid <= '1' when rx_state = S_Data and axis_rx_tvalid = '1' and rx_counter > 1 else
'0';
rx_crc5 <= crc5(token_data);
rx_data_crc <= rx_buf2 & rx_buf1;
trn_address <= token_data(6 downto 0);
trn_endpoint <= token_data(10 downto 7);
RX_FSM : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
start_of_frame <= '0';
crc_error <= '0';
trn_start <= '0';
rx_trn_end <= '0';
rx_trn_hsk_received <= '0';
rx_state <= S_Idle;
else
case rx_state is
when S_Idle =>
start_of_frame <= '0';
crc_error <= '0';
trn_start <= '0';
rx_trn_end <= '0';
rx_trn_hsk_received <= '0';
if axis_rx_tvalid = '1' and rx_pid = (not axis_rx_tdata(7 downto 4)) then
if rx_pid = "0101" then
rx_state <= S_SOF;
elsif rx_pid(1 downto 0) = "01" then
trn_type <= rx_pid(3 downto 2);
rx_state <= S_Token;
elsif rx_pid(1 downto 0) = "11" then
rx_trn_data_type <= rx_pid(3 downto 2);
rx_state <= S_Data;
elsif rx_pid(1 downto 0) = "10" then
rx_trn_hsk_type <= rx_pid(3 downto 2);
rx_trn_hsk_received <= '1';
end if;
end if;
when S_SOF =>
if axis_rx_tvalid = '1' then
if rx_counter = 0 then
token_data(7 downto 0) <= axis_rx_tdata;
elsif rx_counter = 1 then
token_data(10 downto 8) <= axis_rx_tdata(2 downto 0);
token_crc5 <= axis_rx_tdata(7 downto 3);
end if;
if axis_rx_tlast = '1' then
rx_state <= S_SOFCRC;
end if;
end if;
when S_SOFCRC =>
if token_crc5 /= rx_crc5 then
crc_error <= '1';
else
start_of_frame <= '1';
end if;
rx_state <= S_Idle;
when S_Token =>
if axis_rx_tvalid = '1' then
if rx_counter = 0 then
token_data(7 downto 0) <= axis_rx_tdata;
elsif rx_counter = 1 then
token_data(10 downto 8) <= axis_rx_tdata(2 downto 0);
token_crc5 <= axis_rx_tdata(7 downto 3);
end if;
if axis_rx_tlast = '1' then
rx_state <= S_TokenCRC;
end if;
end if;
when S_TokenCRC =>
if device_address = token_data(6 downto 0) then
if token_crc5 = rx_crc5 then
trn_start <= '1';
else
crc_error <= '1';
end if;
end if;
rx_state <= S_Idle;
when S_Data =>
if axis_rx_tvalid = '1' then
if rx_counter = 0 then
rx_buf1 <= axis_rx_tdata;
elsif rx_counter = 1 then
rx_buf2 <= axis_rx_tdata;
else
rx_buf1 <= rx_buf2;
rx_buf2 <= axis_rx_tdata;
end if;
if axis_rx_tlast = '1' then
rx_state <= S_DataCRC;
end if;
end if;
when S_DataCRC =>
rx_trn_end <= '1';
if rx_data_crc /= rx_crc16 then
crc_error <= '1';
end if;
rx_state <= S_Idle;
end case;
end if;
end if;
end process;
TX_FSM : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
tx_state <= S_Idle;
else
case tx_state is
when S_Idle =>
if tx_trn_send_hsk = '1' then
tx_state <= S_HSK;
elsif tx_trn_data_start = '1' then
if tx_trn_data_last = '1' and tx_trn_data_valid = '0' then
tx_zero_packet <= '1';
else
tx_zero_packet <= '0';
end if;
tx_state <= S_DataPID;
end if;
when S_HSK =>
if axis_tx_tready = '1' then
tx_state <= S_HSK_Wait;
end if;
when S_HSK_Wait =>
if tx_trn_send_hsk = '0' then
tx_state <= S_Idle;
end if;
when S_DataPID =>
if axis_tx_tready = '1' then
if tx_zero_packet = '1' then
tx_state <= S_DataCRC1;
else
tx_state <= S_Data;
end if;
end if;
when S_Data =>
if axis_tx_tready = '1' and tx_trn_data_valid = '1' then
if tx_trn_data_last = '1' then
tx_state <= S_DataCRC1;
end if;
elsif tx_trn_data_valid = '0' then
tx_state <= S_DataCRC2;
end if;
when S_DataCRC1 =>
if axis_tx_tready = '1' then
tx_state <= S_DataCRC2;
end if;
when S_DataCRC2 =>
if axis_tx_tready = '1' then
tx_state <= S_Idle;
end if;
end case;
end if;
end if;
end process;
axis_tx_tdata <= (not (tx_trn_data_type & "11")) & tx_trn_data_type & "11" when tx_state = S_DataPID else
(not (tx_trn_hsk_type & "10")) & tx_trn_hsk_type & "10" when tx_state = S_HSK else
tx_crc16_r(7 downto 0) when tx_state = S_DataCRC1 or (tx_state = S_Data and tx_trn_data_valid = '0') else
tx_crc16_r(15 downto 8) when tx_state = S_DataCRC2 else
tx_trn_data;
axis_tx_tvalid <= '1' when tx_state = S_DataPID or tx_state = S_HSK or tx_state = S_DataCRC1 or tx_state = S_DataCRC2 else
'1' when tx_state = S_Data else
'0';
axis_tx_tlast <= '1' when tx_state = S_HSK else
'1' when tx_state = S_DataCRC2 else
'0';
tx_trn_data_ready <= axis_tx_tready when tx_state = S_Data else
'0';
tx_trn_hsk_sended <= '1' when tx_state = S_HSK_Wait else
'0';
tx_crc16_r <= (not (tx_crc16(0) & tx_crc16(1) & tx_crc16(2) & tx_crc16(3) &
tx_crc16(4) & tx_crc16(5) & tx_crc16(6) & tx_crc16(7) &
tx_crc16(8) & tx_crc16(9) & tx_crc16(10) & tx_crc16(11) &
tx_crc16(12) & tx_crc16(13) & tx_crc16(14) & tx_crc16(15)));
rx_pid <= axis_rx_tdata(3 downto 0);
axis_rx_tready <= '1';
end usb_packet;
|
library ieee;
use ieee.std_logic_1164.all;
library foo;
use foo.foo_m;
library bar;
use bar.bar_m;
entity top is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of top is
component foo_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end component;
component bar_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end component;
signal t1, t2 : std_logic;
begin
foo_inst : foo_m port map (
clock => clock,
a => a,
b => b,
x => t1,
y => t2
);
bar_inst : bar_m port map (
clock => clock,
a => t1,
b => t2,
x => x,
y => y
);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library foo;
use foo.foo_m;
library bar;
use bar.bar_m;
entity top is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of top is
component foo_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end component;
component bar_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end component;
signal t1, t2 : std_logic;
begin
foo_inst : foo_m port map (
clock => clock,
a => a,
b => b,
x => t1,
y => t2
);
bar_inst : bar_m port map (
clock => clock,
a => t1,
b => t2,
x => x,
y => y
);
end architecture;
|
-- author: Antonio Gutierrez
-- date: 09/10/13
-- description:
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity ent is
--generic declarations
port (
x: in std_logic_vector(2 downto 0);
y: out std_logic_vector(1 downto 0));
end entity;
--------------------------------------
architecture circuit of ent is
--signals and declarations
begin
y(0) <= '1' when not x(2) or (x(1) and x(0)
else '0';);
y(1) <= '1' when x(1)
else '0';
-- with x select
-- y <= "01" when "0--",
-- <= "10" when "11-",
-- <= "00" when others;
end architecture;
--------------------------------------
|
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fp_sum36x18 IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END fp_sum36x18;
ARCHITECTURE SYN OF fp_sum36x18 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (54 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (71 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
accumulator : STRING;
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
chainout_adder : STRING;
chainout_register : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_a1 : STRING;
input_aclr_b0 : STRING;
input_aclr_b1 : STRING;
input_register_a0 : STRING;
input_register_a1 : STRING;
input_register_b0 : STRING;
input_register_b1 : STRING;
input_source_a0 : STRING;
input_source_a1 : STRING;
input_source_b0 : STRING;
input_source_b1 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_aclr1 : STRING;
multiplier_register0 : STRING;
multiplier_register1 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_chainin : NATURAL;
width_result : NATURAL;
zero_chainout_output_aclr : STRING;
zero_chainout_output_register : STRING;
zero_loopback_aclr : STRING;
zero_loopback_output_aclr : STRING;
zero_loopback_output_register : STRING;
zero_loopback_pipeline_aclr : STRING;
zero_loopback_pipeline_register : STRING;
zero_loopback_register : STRING
);
PORT (
dataa : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6 <= datab_1(35 DOWNTO 0);
sub_wire3 <= dataa_1(17 DOWNTO 0);
result <= sub_wire0(54 DOWNTO 0);
sub_wire1 <= dataa_0(17 DOWNTO 0);
sub_wire2 <= sub_wire3(17 DOWNTO 0) & sub_wire1(17 DOWNTO 0);
sub_wire4 <= datab_0(35 DOWNTO 0);
sub_wire5 <= sub_wire6(35 DOWNTO 0) & sub_wire4(35 DOWNTO 0);
ALTMULT_ADD_component : ALTMULT_ADD
GENERIC MAP (
accumulator => "NO",
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
chainout_adder => "NO",
chainout_register => "UNREGISTERED",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_a1 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_aclr_b1 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_a1 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_register_b1 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_a1 => "DATAA",
input_source_b0 => "DATAB",
input_source_b1 => "DATAB",
intended_device_family => "Stratix III",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_aclr1 => "ACLR3",
multiplier_register0 => "CLOCK0",
multiplier_register1 => "CLOCK0",
number_of_multipliers => 2,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 36,
width_chainin => 1,
width_result => 55,
zero_chainout_output_aclr => "ACLR3",
zero_chainout_output_register => "CLOCK0",
zero_loopback_aclr => "ACLR3",
zero_loopback_output_aclr => "ACLR3",
zero_loopback_output_register => "CLOCK0",
zero_loopback_pipeline_aclr => "ACLR3",
zero_loopback_pipeline_register => "CLOCK0",
zero_loopback_register => "CLOCK0"
)
PORT MAP (
dataa => sub_wire2,
datab => sub_wire5,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
-- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
-- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
-- Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "1"
-- Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_MAC STRING "0"
-- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
-- Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
-- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
-- Retrieval info: PRIVATE: NUM_MULT STRING "2"
-- Retrieval info: PRIVATE: OP1 STRING "Add"
-- Retrieval info: PRIVATE: OP3 STRING "Add"
-- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
-- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: RNFORMAT STRING "55"
-- Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_REG STRING "1"
-- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
-- Retrieval info: PRIVATE: RTS_WIDTH STRING "55"
-- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
-- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
-- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
-- Retrieval info: PRIVATE: SIGNA STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNA_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB_REG STRING "1"
-- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTHA STRING "18"
-- Retrieval info: PRIVATE: WIDTHB STRING "36"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
-- Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
-- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
-- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
-- Retrieval info: CONSTANT: OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
-- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
-- Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "55"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr3 0 0 0 0 INPUT GND "aclr3"
-- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
-- Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
-- Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
-- Retrieval info: USED_PORT: datab_0 0 0 36 0 INPUT GND "datab_0[35..0]"
-- Retrieval info: USED_PORT: datab_1 0 0 36 0 INPUT GND "datab_1[35..0]"
-- Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
-- Retrieval info: USED_PORT: result 0 0 55 0 OUTPUT GND "result[54..0]"
-- Retrieval info: CONNECT: @datab 0 0 36 36 datab_1 0 0 36 0
-- Retrieval info: CONNECT: @aclr3 0 0 0 0 aclr3 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 55 0 @result 0 0 55 0
-- Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
-- Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
-- Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
-- Retrieval info: CONNECT: @datab 0 0 36 0 datab_0 0 0 36 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_inst.vhd FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fp_sum36x18 IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END fp_sum36x18;
ARCHITECTURE SYN OF fp_sum36x18 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (54 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (71 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
accumulator : STRING;
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
chainout_adder : STRING;
chainout_register : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_a1 : STRING;
input_aclr_b0 : STRING;
input_aclr_b1 : STRING;
input_register_a0 : STRING;
input_register_a1 : STRING;
input_register_b0 : STRING;
input_register_b1 : STRING;
input_source_a0 : STRING;
input_source_a1 : STRING;
input_source_b0 : STRING;
input_source_b1 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_aclr1 : STRING;
multiplier_register0 : STRING;
multiplier_register1 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_chainin : NATURAL;
width_result : NATURAL;
zero_chainout_output_aclr : STRING;
zero_chainout_output_register : STRING;
zero_loopback_aclr : STRING;
zero_loopback_output_aclr : STRING;
zero_loopback_output_register : STRING;
zero_loopback_pipeline_aclr : STRING;
zero_loopback_pipeline_register : STRING;
zero_loopback_register : STRING
);
PORT (
dataa : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6 <= datab_1(35 DOWNTO 0);
sub_wire3 <= dataa_1(17 DOWNTO 0);
result <= sub_wire0(54 DOWNTO 0);
sub_wire1 <= dataa_0(17 DOWNTO 0);
sub_wire2 <= sub_wire3(17 DOWNTO 0) & sub_wire1(17 DOWNTO 0);
sub_wire4 <= datab_0(35 DOWNTO 0);
sub_wire5 <= sub_wire6(35 DOWNTO 0) & sub_wire4(35 DOWNTO 0);
ALTMULT_ADD_component : ALTMULT_ADD
GENERIC MAP (
accumulator => "NO",
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
chainout_adder => "NO",
chainout_register => "UNREGISTERED",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_a1 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_aclr_b1 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_a1 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_register_b1 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_a1 => "DATAA",
input_source_b0 => "DATAB",
input_source_b1 => "DATAB",
intended_device_family => "Stratix III",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_aclr1 => "ACLR3",
multiplier_register0 => "CLOCK0",
multiplier_register1 => "CLOCK0",
number_of_multipliers => 2,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 36,
width_chainin => 1,
width_result => 55,
zero_chainout_output_aclr => "ACLR3",
zero_chainout_output_register => "CLOCK0",
zero_loopback_aclr => "ACLR3",
zero_loopback_output_aclr => "ACLR3",
zero_loopback_output_register => "CLOCK0",
zero_loopback_pipeline_aclr => "ACLR3",
zero_loopback_pipeline_register => "CLOCK0",
zero_loopback_register => "CLOCK0"
)
PORT MAP (
dataa => sub_wire2,
datab => sub_wire5,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
-- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
-- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
-- Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "1"
-- Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_MAC STRING "0"
-- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
-- Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
-- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
-- Retrieval info: PRIVATE: NUM_MULT STRING "2"
-- Retrieval info: PRIVATE: OP1 STRING "Add"
-- Retrieval info: PRIVATE: OP3 STRING "Add"
-- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
-- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: RNFORMAT STRING "55"
-- Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_REG STRING "1"
-- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
-- Retrieval info: PRIVATE: RTS_WIDTH STRING "55"
-- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
-- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
-- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
-- Retrieval info: PRIVATE: SIGNA STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNA_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB_REG STRING "1"
-- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTHA STRING "18"
-- Retrieval info: PRIVATE: WIDTHB STRING "36"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
-- Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
-- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
-- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
-- Retrieval info: CONSTANT: OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
-- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
-- Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "55"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr3 0 0 0 0 INPUT GND "aclr3"
-- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
-- Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
-- Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
-- Retrieval info: USED_PORT: datab_0 0 0 36 0 INPUT GND "datab_0[35..0]"
-- Retrieval info: USED_PORT: datab_1 0 0 36 0 INPUT GND "datab_1[35..0]"
-- Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
-- Retrieval info: USED_PORT: result 0 0 55 0 OUTPUT GND "result[54..0]"
-- Retrieval info: CONNECT: @datab 0 0 36 36 datab_1 0 0 36 0
-- Retrieval info: CONNECT: @aclr3 0 0 0 0 aclr3 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 55 0 @result 0 0 55 0
-- Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
-- Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
-- Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
-- Retrieval info: CONNECT: @datab 0 0 36 0 datab_0 0 0 36 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_inst.vhd FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fp_sum36x18 IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END fp_sum36x18;
ARCHITECTURE SYN OF fp_sum36x18 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (54 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (71 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
accumulator : STRING;
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
chainout_adder : STRING;
chainout_register : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_a1 : STRING;
input_aclr_b0 : STRING;
input_aclr_b1 : STRING;
input_register_a0 : STRING;
input_register_a1 : STRING;
input_register_b0 : STRING;
input_register_b1 : STRING;
input_source_a0 : STRING;
input_source_a1 : STRING;
input_source_b0 : STRING;
input_source_b1 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_aclr1 : STRING;
multiplier_register0 : STRING;
multiplier_register1 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_chainin : NATURAL;
width_result : NATURAL;
zero_chainout_output_aclr : STRING;
zero_chainout_output_register : STRING;
zero_loopback_aclr : STRING;
zero_loopback_output_aclr : STRING;
zero_loopback_output_register : STRING;
zero_loopback_pipeline_aclr : STRING;
zero_loopback_pipeline_register : STRING;
zero_loopback_register : STRING
);
PORT (
dataa : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6 <= datab_1(35 DOWNTO 0);
sub_wire3 <= dataa_1(17 DOWNTO 0);
result <= sub_wire0(54 DOWNTO 0);
sub_wire1 <= dataa_0(17 DOWNTO 0);
sub_wire2 <= sub_wire3(17 DOWNTO 0) & sub_wire1(17 DOWNTO 0);
sub_wire4 <= datab_0(35 DOWNTO 0);
sub_wire5 <= sub_wire6(35 DOWNTO 0) & sub_wire4(35 DOWNTO 0);
ALTMULT_ADD_component : ALTMULT_ADD
GENERIC MAP (
accumulator => "NO",
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
chainout_adder => "NO",
chainout_register => "UNREGISTERED",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_a1 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_aclr_b1 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_a1 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_register_b1 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_a1 => "DATAA",
input_source_b0 => "DATAB",
input_source_b1 => "DATAB",
intended_device_family => "Stratix III",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_aclr1 => "ACLR3",
multiplier_register0 => "CLOCK0",
multiplier_register1 => "CLOCK0",
number_of_multipliers => 2,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 36,
width_chainin => 1,
width_result => 55,
zero_chainout_output_aclr => "ACLR3",
zero_chainout_output_register => "CLOCK0",
zero_loopback_aclr => "ACLR3",
zero_loopback_output_aclr => "ACLR3",
zero_loopback_output_register => "CLOCK0",
zero_loopback_pipeline_aclr => "ACLR3",
zero_loopback_pipeline_register => "CLOCK0",
zero_loopback_register => "CLOCK0"
)
PORT MAP (
dataa => sub_wire2,
datab => sub_wire5,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
-- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
-- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
-- Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "1"
-- Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_MAC STRING "0"
-- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
-- Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
-- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
-- Retrieval info: PRIVATE: NUM_MULT STRING "2"
-- Retrieval info: PRIVATE: OP1 STRING "Add"
-- Retrieval info: PRIVATE: OP3 STRING "Add"
-- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
-- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: RNFORMAT STRING "55"
-- Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_REG STRING "1"
-- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
-- Retrieval info: PRIVATE: RTS_WIDTH STRING "55"
-- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
-- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
-- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
-- Retrieval info: PRIVATE: SIGNA STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNA_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB_REG STRING "1"
-- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTHA STRING "18"
-- Retrieval info: PRIVATE: WIDTHB STRING "36"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
-- Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
-- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
-- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
-- Retrieval info: CONSTANT: OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
-- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
-- Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "55"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr3 0 0 0 0 INPUT GND "aclr3"
-- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
-- Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
-- Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
-- Retrieval info: USED_PORT: datab_0 0 0 36 0 INPUT GND "datab_0[35..0]"
-- Retrieval info: USED_PORT: datab_1 0 0 36 0 INPUT GND "datab_1[35..0]"
-- Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
-- Retrieval info: USED_PORT: result 0 0 55 0 OUTPUT GND "result[54..0]"
-- Retrieval info: CONNECT: @datab 0 0 36 36 datab_1 0 0 36 0
-- Retrieval info: CONNECT: @aclr3 0 0 0 0 aclr3 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 55 0 @result 0 0 55 0
-- Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
-- Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
-- Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
-- Retrieval info: CONNECT: @datab 0 0 36 0 datab_0 0 0 36 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_inst.vhd FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fp_sum36x18 IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END fp_sum36x18;
ARCHITECTURE SYN OF fp_sum36x18 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (54 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (71 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
accumulator : STRING;
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
chainout_adder : STRING;
chainout_register : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_a1 : STRING;
input_aclr_b0 : STRING;
input_aclr_b1 : STRING;
input_register_a0 : STRING;
input_register_a1 : STRING;
input_register_b0 : STRING;
input_register_b1 : STRING;
input_source_a0 : STRING;
input_source_a1 : STRING;
input_source_b0 : STRING;
input_source_b1 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_aclr1 : STRING;
multiplier_register0 : STRING;
multiplier_register1 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_chainin : NATURAL;
width_result : NATURAL;
zero_chainout_output_aclr : STRING;
zero_chainout_output_register : STRING;
zero_loopback_aclr : STRING;
zero_loopback_output_aclr : STRING;
zero_loopback_output_register : STRING;
zero_loopback_pipeline_aclr : STRING;
zero_loopback_pipeline_register : STRING;
zero_loopback_register : STRING
);
PORT (
dataa : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6 <= datab_1(35 DOWNTO 0);
sub_wire3 <= dataa_1(17 DOWNTO 0);
result <= sub_wire0(54 DOWNTO 0);
sub_wire1 <= dataa_0(17 DOWNTO 0);
sub_wire2 <= sub_wire3(17 DOWNTO 0) & sub_wire1(17 DOWNTO 0);
sub_wire4 <= datab_0(35 DOWNTO 0);
sub_wire5 <= sub_wire6(35 DOWNTO 0) & sub_wire4(35 DOWNTO 0);
ALTMULT_ADD_component : ALTMULT_ADD
GENERIC MAP (
accumulator => "NO",
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
chainout_adder => "NO",
chainout_register => "UNREGISTERED",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_a1 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_aclr_b1 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_a1 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_register_b1 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_a1 => "DATAA",
input_source_b0 => "DATAB",
input_source_b1 => "DATAB",
intended_device_family => "Stratix III",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_aclr1 => "ACLR3",
multiplier_register0 => "CLOCK0",
multiplier_register1 => "CLOCK0",
number_of_multipliers => 2,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 36,
width_chainin => 1,
width_result => 55,
zero_chainout_output_aclr => "ACLR3",
zero_chainout_output_register => "CLOCK0",
zero_loopback_aclr => "ACLR3",
zero_loopback_output_aclr => "ACLR3",
zero_loopback_output_register => "CLOCK0",
zero_loopback_pipeline_aclr => "ACLR3",
zero_loopback_pipeline_register => "CLOCK0",
zero_loopback_register => "CLOCK0"
)
PORT MAP (
dataa => sub_wire2,
datab => sub_wire5,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
-- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
-- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
-- Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "1"
-- Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_MAC STRING "0"
-- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
-- Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
-- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
-- Retrieval info: PRIVATE: NUM_MULT STRING "2"
-- Retrieval info: PRIVATE: OP1 STRING "Add"
-- Retrieval info: PRIVATE: OP3 STRING "Add"
-- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
-- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: RNFORMAT STRING "55"
-- Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_REG STRING "1"
-- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
-- Retrieval info: PRIVATE: RTS_WIDTH STRING "55"
-- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
-- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
-- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
-- Retrieval info: PRIVATE: SIGNA STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNA_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB_REG STRING "1"
-- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTHA STRING "18"
-- Retrieval info: PRIVATE: WIDTHB STRING "36"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
-- Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
-- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
-- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
-- Retrieval info: CONSTANT: OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
-- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
-- Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "55"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr3 0 0 0 0 INPUT GND "aclr3"
-- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
-- Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
-- Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
-- Retrieval info: USED_PORT: datab_0 0 0 36 0 INPUT GND "datab_0[35..0]"
-- Retrieval info: USED_PORT: datab_1 0 0 36 0 INPUT GND "datab_1[35..0]"
-- Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
-- Retrieval info: USED_PORT: result 0 0 55 0 OUTPUT GND "result[54..0]"
-- Retrieval info: CONNECT: @datab 0 0 36 36 datab_1 0 0 36 0
-- Retrieval info: CONNECT: @aclr3 0 0 0 0 aclr3 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 55 0 @result 0 0 55 0
-- Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
-- Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
-- Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
-- Retrieval info: CONNECT: @datab 0 0 36 0 datab_0 0 0 36 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_inst.vhd FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fp_sum36x18 IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END fp_sum36x18;
ARCHITECTURE SYN OF fp_sum36x18 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (54 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (71 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
accumulator : STRING;
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
chainout_adder : STRING;
chainout_register : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_a1 : STRING;
input_aclr_b0 : STRING;
input_aclr_b1 : STRING;
input_register_a0 : STRING;
input_register_a1 : STRING;
input_register_b0 : STRING;
input_register_b1 : STRING;
input_source_a0 : STRING;
input_source_a1 : STRING;
input_source_b0 : STRING;
input_source_b1 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_aclr1 : STRING;
multiplier_register0 : STRING;
multiplier_register1 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_chainin : NATURAL;
width_result : NATURAL;
zero_chainout_output_aclr : STRING;
zero_chainout_output_register : STRING;
zero_loopback_aclr : STRING;
zero_loopback_output_aclr : STRING;
zero_loopback_output_register : STRING;
zero_loopback_pipeline_aclr : STRING;
zero_loopback_pipeline_register : STRING;
zero_loopback_register : STRING
);
PORT (
dataa : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6 <= datab_1(35 DOWNTO 0);
sub_wire3 <= dataa_1(17 DOWNTO 0);
result <= sub_wire0(54 DOWNTO 0);
sub_wire1 <= dataa_0(17 DOWNTO 0);
sub_wire2 <= sub_wire3(17 DOWNTO 0) & sub_wire1(17 DOWNTO 0);
sub_wire4 <= datab_0(35 DOWNTO 0);
sub_wire5 <= sub_wire6(35 DOWNTO 0) & sub_wire4(35 DOWNTO 0);
ALTMULT_ADD_component : ALTMULT_ADD
GENERIC MAP (
accumulator => "NO",
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
chainout_adder => "NO",
chainout_register => "UNREGISTERED",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_a1 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_aclr_b1 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_a1 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_register_b1 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_a1 => "DATAA",
input_source_b0 => "DATAB",
input_source_b1 => "DATAB",
intended_device_family => "Stratix III",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_aclr1 => "ACLR3",
multiplier_register0 => "CLOCK0",
multiplier_register1 => "CLOCK0",
number_of_multipliers => 2,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 36,
width_chainin => 1,
width_result => 55,
zero_chainout_output_aclr => "ACLR3",
zero_chainout_output_register => "CLOCK0",
zero_loopback_aclr => "ACLR3",
zero_loopback_output_aclr => "ACLR3",
zero_loopback_output_register => "CLOCK0",
zero_loopback_pipeline_aclr => "ACLR3",
zero_loopback_pipeline_register => "CLOCK0",
zero_loopback_register => "CLOCK0"
)
PORT MAP (
dataa => sub_wire2,
datab => sub_wire5,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
-- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
-- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
-- Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "1"
-- Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_MAC STRING "0"
-- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
-- Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
-- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
-- Retrieval info: PRIVATE: NUM_MULT STRING "2"
-- Retrieval info: PRIVATE: OP1 STRING "Add"
-- Retrieval info: PRIVATE: OP3 STRING "Add"
-- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
-- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: RNFORMAT STRING "55"
-- Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_REG STRING "1"
-- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
-- Retrieval info: PRIVATE: RTS_WIDTH STRING "55"
-- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
-- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
-- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
-- Retrieval info: PRIVATE: SIGNA STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNA_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB_REG STRING "1"
-- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTHA STRING "18"
-- Retrieval info: PRIVATE: WIDTHB STRING "36"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
-- Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
-- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
-- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
-- Retrieval info: CONSTANT: OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
-- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
-- Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "55"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr3 0 0 0 0 INPUT GND "aclr3"
-- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
-- Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
-- Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
-- Retrieval info: USED_PORT: datab_0 0 0 36 0 INPUT GND "datab_0[35..0]"
-- Retrieval info: USED_PORT: datab_1 0 0 36 0 INPUT GND "datab_1[35..0]"
-- Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
-- Retrieval info: USED_PORT: result 0 0 55 0 OUTPUT GND "result[54..0]"
-- Retrieval info: CONNECT: @datab 0 0 36 36 datab_1 0 0 36 0
-- Retrieval info: CONNECT: @aclr3 0 0 0 0 aclr3 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 55 0 @result 0 0 55 0
-- Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
-- Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
-- Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
-- Retrieval info: CONNECT: @datab 0 0 36 0 datab_0 0 0 36 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_inst.vhd FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fp_sum36x18 IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END fp_sum36x18;
ARCHITECTURE SYN OF fp_sum36x18 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (54 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (71 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
accumulator : STRING;
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
chainout_adder : STRING;
chainout_register : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_a1 : STRING;
input_aclr_b0 : STRING;
input_aclr_b1 : STRING;
input_register_a0 : STRING;
input_register_a1 : STRING;
input_register_b0 : STRING;
input_register_b1 : STRING;
input_source_a0 : STRING;
input_source_a1 : STRING;
input_source_b0 : STRING;
input_source_b1 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_aclr1 : STRING;
multiplier_register0 : STRING;
multiplier_register1 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_chainin : NATURAL;
width_result : NATURAL;
zero_chainout_output_aclr : STRING;
zero_chainout_output_register : STRING;
zero_loopback_aclr : STRING;
zero_loopback_output_aclr : STRING;
zero_loopback_output_register : STRING;
zero_loopback_pipeline_aclr : STRING;
zero_loopback_pipeline_register : STRING;
zero_loopback_register : STRING
);
PORT (
dataa : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6 <= datab_1(35 DOWNTO 0);
sub_wire3 <= dataa_1(17 DOWNTO 0);
result <= sub_wire0(54 DOWNTO 0);
sub_wire1 <= dataa_0(17 DOWNTO 0);
sub_wire2 <= sub_wire3(17 DOWNTO 0) & sub_wire1(17 DOWNTO 0);
sub_wire4 <= datab_0(35 DOWNTO 0);
sub_wire5 <= sub_wire6(35 DOWNTO 0) & sub_wire4(35 DOWNTO 0);
ALTMULT_ADD_component : ALTMULT_ADD
GENERIC MAP (
accumulator => "NO",
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
chainout_adder => "NO",
chainout_register => "UNREGISTERED",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_a1 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_aclr_b1 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_a1 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_register_b1 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_a1 => "DATAA",
input_source_b0 => "DATAB",
input_source_b1 => "DATAB",
intended_device_family => "Stratix III",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_aclr1 => "ACLR3",
multiplier_register0 => "CLOCK0",
multiplier_register1 => "CLOCK0",
number_of_multipliers => 2,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 36,
width_chainin => 1,
width_result => 55,
zero_chainout_output_aclr => "ACLR3",
zero_chainout_output_register => "CLOCK0",
zero_loopback_aclr => "ACLR3",
zero_loopback_output_aclr => "ACLR3",
zero_loopback_output_register => "CLOCK0",
zero_loopback_pipeline_aclr => "ACLR3",
zero_loopback_pipeline_register => "CLOCK0",
zero_loopback_register => "CLOCK0"
)
PORT MAP (
dataa => sub_wire2,
datab => sub_wire5,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
-- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
-- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
-- Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "1"
-- Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_MAC STRING "0"
-- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
-- Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
-- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
-- Retrieval info: PRIVATE: NUM_MULT STRING "2"
-- Retrieval info: PRIVATE: OP1 STRING "Add"
-- Retrieval info: PRIVATE: OP3 STRING "Add"
-- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
-- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: RNFORMAT STRING "55"
-- Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_REG STRING "1"
-- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
-- Retrieval info: PRIVATE: RTS_WIDTH STRING "55"
-- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
-- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
-- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
-- Retrieval info: PRIVATE: SIGNA STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNA_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB_REG STRING "1"
-- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTHA STRING "18"
-- Retrieval info: PRIVATE: WIDTHB STRING "36"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
-- Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
-- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
-- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
-- Retrieval info: CONSTANT: OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
-- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
-- Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "55"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr3 0 0 0 0 INPUT GND "aclr3"
-- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
-- Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
-- Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
-- Retrieval info: USED_PORT: datab_0 0 0 36 0 INPUT GND "datab_0[35..0]"
-- Retrieval info: USED_PORT: datab_1 0 0 36 0 INPUT GND "datab_1[35..0]"
-- Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
-- Retrieval info: USED_PORT: result 0 0 55 0 OUTPUT GND "result[54..0]"
-- Retrieval info: CONNECT: @datab 0 0 36 36 datab_1 0 0 36 0
-- Retrieval info: CONNECT: @aclr3 0 0 0 0 aclr3 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 55 0 @result 0 0 55 0
-- Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
-- Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
-- Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
-- Retrieval info: CONNECT: @datab 0 0 36 0 datab_0 0 0 36 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_inst.vhd FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fp_sum36x18 IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END fp_sum36x18;
ARCHITECTURE SYN OF fp_sum36x18 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (54 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (71 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
accumulator : STRING;
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
chainout_adder : STRING;
chainout_register : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_a1 : STRING;
input_aclr_b0 : STRING;
input_aclr_b1 : STRING;
input_register_a0 : STRING;
input_register_a1 : STRING;
input_register_b0 : STRING;
input_register_b1 : STRING;
input_source_a0 : STRING;
input_source_a1 : STRING;
input_source_b0 : STRING;
input_source_b1 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_aclr1 : STRING;
multiplier_register0 : STRING;
multiplier_register1 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_chainin : NATURAL;
width_result : NATURAL;
zero_chainout_output_aclr : STRING;
zero_chainout_output_register : STRING;
zero_loopback_aclr : STRING;
zero_loopback_output_aclr : STRING;
zero_loopback_output_register : STRING;
zero_loopback_pipeline_aclr : STRING;
zero_loopback_pipeline_register : STRING;
zero_loopback_register : STRING
);
PORT (
dataa : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6 <= datab_1(35 DOWNTO 0);
sub_wire3 <= dataa_1(17 DOWNTO 0);
result <= sub_wire0(54 DOWNTO 0);
sub_wire1 <= dataa_0(17 DOWNTO 0);
sub_wire2 <= sub_wire3(17 DOWNTO 0) & sub_wire1(17 DOWNTO 0);
sub_wire4 <= datab_0(35 DOWNTO 0);
sub_wire5 <= sub_wire6(35 DOWNTO 0) & sub_wire4(35 DOWNTO 0);
ALTMULT_ADD_component : ALTMULT_ADD
GENERIC MAP (
accumulator => "NO",
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
chainout_adder => "NO",
chainout_register => "UNREGISTERED",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_a1 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_aclr_b1 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_a1 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_register_b1 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_a1 => "DATAA",
input_source_b0 => "DATAB",
input_source_b1 => "DATAB",
intended_device_family => "Stratix III",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_aclr1 => "ACLR3",
multiplier_register0 => "CLOCK0",
multiplier_register1 => "CLOCK0",
number_of_multipliers => 2,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 36,
width_chainin => 1,
width_result => 55,
zero_chainout_output_aclr => "ACLR3",
zero_chainout_output_register => "CLOCK0",
zero_loopback_aclr => "ACLR3",
zero_loopback_output_aclr => "ACLR3",
zero_loopback_output_register => "CLOCK0",
zero_loopback_pipeline_aclr => "ACLR3",
zero_loopback_pipeline_register => "CLOCK0",
zero_loopback_register => "CLOCK0"
)
PORT MAP (
dataa => sub_wire2,
datab => sub_wire5,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
-- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
-- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
-- Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "1"
-- Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_MAC STRING "0"
-- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
-- Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
-- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
-- Retrieval info: PRIVATE: NUM_MULT STRING "2"
-- Retrieval info: PRIVATE: OP1 STRING "Add"
-- Retrieval info: PRIVATE: OP3 STRING "Add"
-- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
-- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: RNFORMAT STRING "55"
-- Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_REG STRING "1"
-- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
-- Retrieval info: PRIVATE: RTS_WIDTH STRING "55"
-- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
-- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
-- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
-- Retrieval info: PRIVATE: SIGNA STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNA_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB_REG STRING "1"
-- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTHA STRING "18"
-- Retrieval info: PRIVATE: WIDTHB STRING "36"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
-- Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
-- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
-- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
-- Retrieval info: CONSTANT: OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
-- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
-- Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "55"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr3 0 0 0 0 INPUT GND "aclr3"
-- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
-- Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
-- Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
-- Retrieval info: USED_PORT: datab_0 0 0 36 0 INPUT GND "datab_0[35..0]"
-- Retrieval info: USED_PORT: datab_1 0 0 36 0 INPUT GND "datab_1[35..0]"
-- Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
-- Retrieval info: USED_PORT: result 0 0 55 0 OUTPUT GND "result[54..0]"
-- Retrieval info: CONNECT: @datab 0 0 36 36 datab_1 0 0 36 0
-- Retrieval info: CONNECT: @aclr3 0 0 0 0 aclr3 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 55 0 @result 0 0 55 0
-- Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
-- Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
-- Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
-- Retrieval info: CONNECT: @datab 0 0 36 0 datab_0 0 0 36 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_inst.vhd FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fp_sum36x18 IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END fp_sum36x18;
ARCHITECTURE SYN OF fp_sum36x18 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (54 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (71 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
accumulator : STRING;
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
chainout_adder : STRING;
chainout_register : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_a1 : STRING;
input_aclr_b0 : STRING;
input_aclr_b1 : STRING;
input_register_a0 : STRING;
input_register_a1 : STRING;
input_register_b0 : STRING;
input_register_b1 : STRING;
input_source_a0 : STRING;
input_source_a1 : STRING;
input_source_b0 : STRING;
input_source_b1 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_aclr1 : STRING;
multiplier_register0 : STRING;
multiplier_register1 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_chainin : NATURAL;
width_result : NATURAL;
zero_chainout_output_aclr : STRING;
zero_chainout_output_register : STRING;
zero_loopback_aclr : STRING;
zero_loopback_output_aclr : STRING;
zero_loopback_output_register : STRING;
zero_loopback_pipeline_aclr : STRING;
zero_loopback_pipeline_register : STRING;
zero_loopback_register : STRING
);
PORT (
dataa : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6 <= datab_1(35 DOWNTO 0);
sub_wire3 <= dataa_1(17 DOWNTO 0);
result <= sub_wire0(54 DOWNTO 0);
sub_wire1 <= dataa_0(17 DOWNTO 0);
sub_wire2 <= sub_wire3(17 DOWNTO 0) & sub_wire1(17 DOWNTO 0);
sub_wire4 <= datab_0(35 DOWNTO 0);
sub_wire5 <= sub_wire6(35 DOWNTO 0) & sub_wire4(35 DOWNTO 0);
ALTMULT_ADD_component : ALTMULT_ADD
GENERIC MAP (
accumulator => "NO",
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
chainout_adder => "NO",
chainout_register => "UNREGISTERED",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_a1 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_aclr_b1 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_a1 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_register_b1 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_a1 => "DATAA",
input_source_b0 => "DATAB",
input_source_b1 => "DATAB",
intended_device_family => "Stratix III",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_aclr1 => "ACLR3",
multiplier_register0 => "CLOCK0",
multiplier_register1 => "CLOCK0",
number_of_multipliers => 2,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 36,
width_chainin => 1,
width_result => 55,
zero_chainout_output_aclr => "ACLR3",
zero_chainout_output_register => "CLOCK0",
zero_loopback_aclr => "ACLR3",
zero_loopback_output_aclr => "ACLR3",
zero_loopback_output_register => "CLOCK0",
zero_loopback_pipeline_aclr => "ACLR3",
zero_loopback_pipeline_register => "CLOCK0",
zero_loopback_register => "CLOCK0"
)
PORT MAP (
dataa => sub_wire2,
datab => sub_wire5,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
-- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
-- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
-- Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "1"
-- Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_MAC STRING "0"
-- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
-- Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
-- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
-- Retrieval info: PRIVATE: NUM_MULT STRING "2"
-- Retrieval info: PRIVATE: OP1 STRING "Add"
-- Retrieval info: PRIVATE: OP3 STRING "Add"
-- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
-- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: RNFORMAT STRING "55"
-- Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_REG STRING "1"
-- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
-- Retrieval info: PRIVATE: RTS_WIDTH STRING "55"
-- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
-- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
-- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
-- Retrieval info: PRIVATE: SIGNA STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNA_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB_REG STRING "1"
-- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTHA STRING "18"
-- Retrieval info: PRIVATE: WIDTHB STRING "36"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
-- Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
-- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
-- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
-- Retrieval info: CONSTANT: OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
-- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
-- Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "55"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr3 0 0 0 0 INPUT GND "aclr3"
-- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
-- Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
-- Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
-- Retrieval info: USED_PORT: datab_0 0 0 36 0 INPUT GND "datab_0[35..0]"
-- Retrieval info: USED_PORT: datab_1 0 0 36 0 INPUT GND "datab_1[35..0]"
-- Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
-- Retrieval info: USED_PORT: result 0 0 55 0 OUTPUT GND "result[54..0]"
-- Retrieval info: CONNECT: @datab 0 0 36 36 datab_1 0 0 36 0
-- Retrieval info: CONNECT: @aclr3 0 0 0 0 aclr3 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 55 0 @result 0 0 55 0
-- Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
-- Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
-- Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
-- Retrieval info: CONNECT: @datab 0 0 36 0 datab_0 0 0 36 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_inst.vhd FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.