content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either ver... |
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either ver... |
----------------------------------------------------------------------------------
-- group_selector.vhd
--
-- Copyright (C) 2011
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either ver... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity harris is
generic (
LINE_WIDTH_MAX : integer := 320;
IN_SIZE : integer := 8;
OUT_SIZE : integer := 8;
CLK_PROC_FREQ : integer := 48000000
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
package some_package is
-- this signal seems to be problematic
-- uncomment to reproduce the bug
signal some_signal :bit;
component some_component end component;
end package;
entity some_component is end entity;
architecture a of some_component is begin end architecture;
entity wrapper is end entity;
archi... |
package some_package is
-- this signal seems to be problematic
-- uncomment to reproduce the bug
signal some_signal :bit;
component some_component end component;
end package;
entity some_component is end entity;
architecture a of some_component is begin end architecture;
entity wrapper is end entity;
archi... |
package some_package is
-- this signal seems to be problematic
-- uncomment to reproduce the bug
signal some_signal :bit;
component some_component end component;
end package;
entity some_component is end entity;
architecture a of some_component is begin end architecture;
entity wrapper is end entity;
archi... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_MIN_MAX_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
FONCTION : in STD_LOGIC_VECTOR( 1 downto 0);
OUTPUT_1 : out STD_LOGIC_VEC... |
architecture rtl of fifo is
begin
GEN_LABEL : case expression generate
when OTHERS =>
end generate;
GEN_LABEL : case expression generate
when OTHERS =>
end generate;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNFEQ57IEX is
generic ( ClockPhase : string := "1";
delay : positive := 1;
us... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNFEQ57IEX is
generic ( ClockPhase : string := "1";
delay : positive := 1;
us... |
library ieee;
use ieee.std_logic_1164.all;
use work.issue_pkg.t_one_two; -- does not work
--use work.issue_pkg.all; -- works
entity issue is
port (
clk : in std_logic;
input : in t_one_two;
output : out std_logic
);
end entity issue;
architecture rtl of issue is
b... |
library ieee;
use ieee.std_logic_1164.all;
use work.issue_pkg.t_one_two; -- does not work
--use work.issue_pkg.all; -- works
entity issue is
port (
clk : in std_logic;
input : in t_one_two;
output : out std_logic
);
end entity issue;
architecture rtl of issue is
b... |
library ieee;
use ieee.std_logic_1164.all;
entity map2 is
port
(
F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15: out std_logic_vector(31 downto 0)
);
end map2;
architecture map2_struct of map2 is
begin
F0 <= "00000000000000011100000011000000";
F1 <= "00000001100000001000000011000000";... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as publis... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as publis... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity caseT is
port(A : out std_logic;
baz : in std_logic_vector(2 downto 0));
end caseT;
architecture behv of caseT is
begin
process(A) is
begin
case baz is
when "00... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity caseT is
port(A : out std_logic;
baz : in std_logic_vector(2 downto 0));
end caseT;
architecture behv of caseT is
begin
process(A) is
begin
case baz is
when "00... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:47:10 09/25/2015
-- Design Name:
-- Module Name: MUX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pci_sys_pll_125M.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ==================================... |
----------------------------------------------------------------------------------
-- Module Name: pixel_x4_generator - Behavioral
--
-- Description: A module to generate a group of pixels at a time.
-- Not yet in use in the main project.
--
---------------------------------------------------------------... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--
-- Controller.vhd
-- The core controller module of VM2413
--
-- Copyright (c) 2006 Mitsutaka Okazaki (brezza@pokipoki.org)
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of sou... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MuxPC is
Port ( PCdisp30 : in STD_LOGIC_VECTOR(31 downto 0);
PCdisp22 : in STD_LOGIC_VECTOR(31 downto 0);
PC : in STD_LOGIC_VECTOR(31 downto 0);
PCplus1 : in STD_LOGIC_VECTOR(31 downto 0);
PCSource: in STD_LOGIC_VECTOR(1 downto ... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY SimpleIfStatementPartialOverride IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SimpleIfStatementPartialOverride IS
BEGIN
a... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D13_C2 is
port(
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D13_C2;
architecture D13_C2 of D13_C2 is
begin
process(clk)
variable dem:integer range 0 to 4;
begin
if (rising_edge(clk)) then
if (dem=4) then dem:=0;
else de... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arpv2 - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle s... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arpv2 - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle s... |
library verilog;
use verilog.vl_types.all;
entity reg_shifter is
port(
rt_out : in vl_logic_vector(31 downto 0);
mem_addr_in : in vl_logic_vector(1 downto 0);
MemWrite : in vl_logic;
IR_out : in vl_logic_vector(5 downto 0);
rt_out_... |
-------------------------------------------------------------------------------
-- Entity: fmc_top
-- Author: Waj
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Top-level of Floppy-Music Controller peripheral module in MCU.
-----------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:20:16 11/19/2014
-- Design Name:
-- Module Name: clk_prescaler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:20:16 11/19/2014
-- Design Name:
-- Module Name: clk_prescaler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
--------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------------Reset the contents of the Map to border and empty unexplored cell encoding
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Reset_Module is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Request_Set : out STD_LOGIC;
X_out : out STD_LOGIC_VECTOR (4 down... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ecb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-... |
library ieee;
use ieee.numeric_bit.all;
entity udiv23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity udiv23;
architecture rtl of udiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity udiv23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity udiv23;
architecture rtl of udiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity udiv23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity udiv23;
architecture rtl of udiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity udiv23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity udiv23;
architecture rtl of udiv23 is
begin
c_o <= a_i / b_i;
end architecture rtl;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
--
-- The Wishbone master module.
--
-- $Id: wb_master-c.vhd,v 1.2 2005-06-11 10:16:05 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
------------------------------------------------... |
--
-- USB Full-Speed/Hi-Speed Device Controller core - usb_packet.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction,... |
library ieee;
use ieee.std_logic_1164.all;
library foo;
use foo.foo_m;
library bar;
use bar.bar_m;
entity top is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of top is
component foo_m is
port (
clock : in std_... |
library ieee;
use ieee.std_logic_1164.all;
library foo;
use foo.foo_m;
library bar;
use bar.bar_m;
entity top is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of top is
component foo_m is
port (
clock : in std_... |
-- author: Antonio Gutierrez
-- date: 09/10/13
-- description:
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity ent is
--generic declarations
port (
x: in std_logic_vector(2 downto 0);
y: out std_logic_vector(1 downto 0)... |
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================... |
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================... |
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================... |
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================... |
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================... |
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================... |
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================... |
-- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================... |
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